1 /* bnx2x.h: QLogic Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * Copyright (c) 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12 * Written by: Eliezer Tamir 13 * Based on code from Michael Chan's bnx2 driver 14 */ 15 16 #ifndef BNX2X_H 17 #define BNX2X_H 18 19 #include <linux/pci.h> 20 #include <linux/netdevice.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/types.h> 23 #include <linux/pci_regs.h> 24 25 #include <linux/ptp_clock_kernel.h> 26 #include <linux/net_tstamp.h> 27 #include <linux/timecounter.h> 28 29 /* compilation time flags */ 30 31 /* define this to make the driver freeze on error to allow getting debug info 32 * (you will need to reboot afterwards) */ 33 /* #define BNX2X_STOP_ON_ERROR */ 34 35 #define DRV_MODULE_VERSION "1.712.30-0" 36 #define DRV_MODULE_RELDATE "2014/02/10" 37 #define BNX2X_BC_VER 0x040200 38 39 #if defined(CONFIG_DCB) 40 #define BCM_DCBNL 41 #endif 42 43 #include "bnx2x_hsi.h" 44 45 #include "../cnic_if.h" 46 47 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 48 49 #include <linux/mdio.h> 50 51 #include "bnx2x_reg.h" 52 #include "bnx2x_fw_defs.h" 53 #include "bnx2x_mfw_req.h" 54 #include "bnx2x_link.h" 55 #include "bnx2x_sp.h" 56 #include "bnx2x_dcb.h" 57 #include "bnx2x_stats.h" 58 #include "bnx2x_vfpf.h" 59 60 enum bnx2x_int_mode { 61 BNX2X_INT_MODE_MSIX, 62 BNX2X_INT_MODE_INTX, 63 BNX2X_INT_MODE_MSI 64 }; 65 66 /* error/debug prints */ 67 68 #define DRV_MODULE_NAME "bnx2x" 69 70 /* for messages that are currently off */ 71 #define BNX2X_MSG_OFF 0x0 72 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 73 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 74 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 75 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 76 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 77 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 78 #define BNX2X_MSG_IOV 0x0800000 79 #define BNX2X_MSG_PTP 0x1000000 80 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 81 #define BNX2X_MSG_ETHTOOL 0x4000000 82 #define BNX2X_MSG_DCB 0x8000000 83 84 /* regular debug print */ 85 #define DP_INNER(fmt, ...) \ 86 pr_notice("[%s:%d(%s)]" fmt, \ 87 __func__, __LINE__, \ 88 bp->dev ? (bp->dev->name) : "?", \ 89 ##__VA_ARGS__); 90 91 #define DP(__mask, fmt, ...) \ 92 do { \ 93 if (unlikely(bp->msg_enable & (__mask))) \ 94 DP_INNER(fmt, ##__VA_ARGS__); \ 95 } while (0) 96 97 #define DP_AND(__mask, fmt, ...) \ 98 do { \ 99 if (unlikely((bp->msg_enable & (__mask)) == __mask)) \ 100 DP_INNER(fmt, ##__VA_ARGS__); \ 101 } while (0) 102 103 #define DP_CONT(__mask, fmt, ...) \ 104 do { \ 105 if (unlikely(bp->msg_enable & (__mask))) \ 106 pr_cont(fmt, ##__VA_ARGS__); \ 107 } while (0) 108 109 /* errors debug print */ 110 #define BNX2X_DBG_ERR(fmt, ...) \ 111 do { \ 112 if (unlikely(netif_msg_probe(bp))) \ 113 pr_err("[%s:%d(%s)]" fmt, \ 114 __func__, __LINE__, \ 115 bp->dev ? (bp->dev->name) : "?", \ 116 ##__VA_ARGS__); \ 117 } while (0) 118 119 /* for errors (never masked) */ 120 #define BNX2X_ERR(fmt, ...) \ 121 do { \ 122 pr_err("[%s:%d(%s)]" fmt, \ 123 __func__, __LINE__, \ 124 bp->dev ? (bp->dev->name) : "?", \ 125 ##__VA_ARGS__); \ 126 } while (0) 127 128 #define BNX2X_ERROR(fmt, ...) \ 129 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 130 131 /* before we have a dev->name use dev_info() */ 132 #define BNX2X_DEV_INFO(fmt, ...) \ 133 do { \ 134 if (unlikely(netif_msg_probe(bp))) \ 135 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 136 } while (0) 137 138 /* Error handling */ 139 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); 140 #ifdef BNX2X_STOP_ON_ERROR 141 #define bnx2x_panic() \ 142 do { \ 143 bp->panic = 1; \ 144 BNX2X_ERR("driver assert\n"); \ 145 bnx2x_panic_dump(bp, true); \ 146 } while (0) 147 #else 148 #define bnx2x_panic() \ 149 do { \ 150 bp->panic = 1; \ 151 BNX2X_ERR("driver assert\n"); \ 152 bnx2x_panic_dump(bp, false); \ 153 } while (0) 154 #endif 155 156 #define bnx2x_mc_addr(ha) ((ha)->addr) 157 #define bnx2x_uc_addr(ha) ((ha)->addr) 158 159 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 160 #define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 161 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 162 163 #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 164 165 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 166 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 167 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 168 169 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 170 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 171 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 172 173 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 174 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 175 176 #define REG_RD_DMAE(bp, offset, valp, len32) \ 177 do { \ 178 bnx2x_read_dmae(bp, offset, len32);\ 179 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 180 } while (0) 181 182 #define REG_WR_DMAE(bp, offset, valp, len32) \ 183 do { \ 184 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 185 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 186 offset, len32); \ 187 } while (0) 188 189 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 190 REG_WR_DMAE(bp, offset, valp, len32) 191 192 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 193 do { \ 194 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 195 bnx2x_write_big_buf_wb(bp, addr, len32); \ 196 } while (0) 197 198 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 199 offsetof(struct shmem_region, field)) 200 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 201 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 202 203 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 204 offsetof(struct shmem2_region, field)) 205 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 206 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 207 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 208 offsetof(struct mf_cfg, field)) 209 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 210 offsetof(struct mf2_cfg, field)) 211 212 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 213 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 214 MF_CFG_ADDR(bp, field), (val)) 215 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 216 217 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 218 (SHMEM2_RD((bp), size) > \ 219 offsetof(struct shmem2_region, field))) 220 221 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 222 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 223 224 /* SP SB indices */ 225 226 /* General SP events - stats query, cfc delete, etc */ 227 #define HC_SP_INDEX_ETH_DEF_CONS 3 228 229 /* EQ completions */ 230 #define HC_SP_INDEX_EQ_CONS 7 231 232 /* FCoE L2 connection completions */ 233 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 234 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 235 /* iSCSI L2 */ 236 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 237 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 238 239 /* Special clients parameters */ 240 241 /* SB indices */ 242 /* FCoE L2 */ 243 #define BNX2X_FCOE_L2_RX_INDEX \ 244 (&bp->def_status_blk->sp_sb.\ 245 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 246 247 #define BNX2X_FCOE_L2_TX_INDEX \ 248 (&bp->def_status_blk->sp_sb.\ 249 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 250 251 /** 252 * CIDs and CLIDs: 253 * CLIDs below is a CLID for func 0, then the CLID for other 254 * functions will be calculated by the formula: 255 * 256 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 257 * 258 */ 259 enum { 260 BNX2X_ISCSI_ETH_CL_ID_IDX, 261 BNX2X_FCOE_ETH_CL_ID_IDX, 262 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 263 }; 264 265 /* use a value high enough to be above all the PFs, which has least significant 266 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to 267 * calculate doorbell address according to old doorbell configuration scheme 268 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number 269 * We must avoid coming up with cid 8 for iscsi since according to this method 270 * the designated UIO cid will come out 0 and it has a special handling for that 271 * case which doesn't suit us. Therefore will will cieling to closes cid which 272 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18. 273 */ 274 275 #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \ 276 (bp)->max_cos) 277 /* amount of cids traversed by UIO's DPM addition to doorbell */ 278 #define UIO_DPM 8 279 /* roundup to DPM offset */ 280 #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \ 281 UIO_DPM)) 282 /* offset to nearest value which has lsb nibble matching DPM */ 283 #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \ 284 (UIO_DPM * 2)) 285 /* add offset to rounded-up cid to get a value which could be used with UIO */ 286 #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp)) 287 /* but wait - avoid UIO special case for cid 0 */ 288 #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \ 289 (UIO_DPM_ALIGN(bp) == UIO_DPM)) 290 /* Properly DPM aligned CID dajusted to cid 0 secal case */ 291 #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \ 292 (UIO_DPM_CID0_OFFSET(bp))) 293 /* how many cids were wasted - need this value for cid allocation */ 294 #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \ 295 BNX2X_1st_NON_L2_ETH_CID(bp)) 296 /* iSCSI L2 */ 297 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 298 /* FCoE L2 */ 299 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 300 301 #define CNIC_SUPPORT(bp) ((bp)->cnic_support) 302 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 303 #define CNIC_LOADED(bp) ((bp)->cnic_loaded) 304 #define FCOE_INIT(bp) ((bp)->fcoe_init) 305 306 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 307 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 308 309 #define SM_RX_ID 0 310 #define SM_TX_ID 1 311 312 /* defines for multiple tx priority indices */ 313 #define FIRST_TX_ONLY_COS_INDEX 1 314 #define FIRST_TX_COS_INDEX 0 315 316 /* rules for calculating the cids of tx-only connections */ 317 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 318 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 319 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 320 321 /* fp index inside class of service range */ 322 #define FP_COS_TO_TXQ(fp, cos, bp) \ 323 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 324 325 /* Indexes for transmission queues array: 326 * txdata for RSS i CoS j is at location i + (j * num of RSS) 327 * txdata for FCoE (if exist) is at location max cos * num of RSS 328 * txdata for FWD (if exist) is one location after FCoE 329 * txdata for OOO (if exist) is one location after FWD 330 */ 331 enum { 332 FCOE_TXQ_IDX_OFFSET, 333 FWD_TXQ_IDX_OFFSET, 334 OOO_TXQ_IDX_OFFSET, 335 }; 336 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 337 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 338 339 /* fast path */ 340 /* 341 * This driver uses new build_skb() API : 342 * RX ring buffer contains pointer to kmalloc() data only, 343 * skb are built only after Hardware filled the frame. 344 */ 345 struct sw_rx_bd { 346 u8 *data; 347 DEFINE_DMA_UNMAP_ADDR(mapping); 348 }; 349 350 struct sw_tx_bd { 351 struct sk_buff *skb; 352 u16 first_bd; 353 u8 flags; 354 /* Set on the first BD descriptor when there is a split BD */ 355 #define BNX2X_TSO_SPLIT_BD (1<<0) 356 #define BNX2X_HAS_SECOND_PBD (1<<1) 357 }; 358 359 struct sw_rx_page { 360 struct page *page; 361 DEFINE_DMA_UNMAP_ADDR(mapping); 362 unsigned int offset; 363 }; 364 365 union db_prod { 366 struct doorbell_set_prod data; 367 u32 raw; 368 }; 369 370 /* dropless fc FW/HW related params */ 371 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 372 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 373 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 374 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 375 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 376 #define FW_PREFETCH_CNT 16 377 #define DROPLESS_FC_HEADROOM 100 378 379 /* MC hsi */ 380 #define BCM_PAGE_SHIFT 12 381 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 382 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 383 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 384 385 #define PAGES_PER_SGE_SHIFT 0 386 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 387 #define SGE_PAGE_SHIFT 12 388 #define SGE_PAGE_SIZE (1 << SGE_PAGE_SHIFT) 389 #define SGE_PAGE_MASK (~(SGE_PAGE_SIZE - 1)) 390 #define SGE_PAGE_ALIGN(addr) (((addr) + SGE_PAGE_SIZE - 1) & SGE_PAGE_MASK) 391 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 392 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 393 SGE_PAGES), 0xffff) 394 395 /* SGE ring related macros */ 396 #define NUM_RX_SGE_PAGES 2 397 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 398 #define NEXT_PAGE_SGE_DESC_CNT 2 399 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 400 /* RX_SGE_CNT is promised to be a power of 2 */ 401 #define RX_SGE_MASK (RX_SGE_CNT - 1) 402 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 403 #define MAX_RX_SGE (NUM_RX_SGE - 1) 404 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 405 (MAX_RX_SGE_CNT - 1)) ? \ 406 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 407 (x) + 1) 408 #define RX_SGE(x) ((x) & MAX_RX_SGE) 409 410 /* 411 * Number of required SGEs is the sum of two: 412 * 1. Number of possible opened aggregations (next packet for 413 * these aggregations will probably consume SGE immediately) 414 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 415 * after placement on BD for new TPA aggregation) 416 * 417 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 418 */ 419 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 420 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 421 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 422 MAX_RX_SGE_CNT) 423 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 424 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 425 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 426 427 /* Manipulate a bit vector defined as an array of u64 */ 428 429 /* Number of bits in one sge_mask array element */ 430 #define BIT_VEC64_ELEM_SZ 64 431 #define BIT_VEC64_ELEM_SHIFT 6 432 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 433 434 #define __BIT_VEC64_SET_BIT(el, bit) \ 435 do { \ 436 el = ((el) | ((u64)0x1 << (bit))); \ 437 } while (0) 438 439 #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 440 do { \ 441 el = ((el) & (~((u64)0x1 << (bit)))); \ 442 } while (0) 443 444 #define BIT_VEC64_SET_BIT(vec64, idx) \ 445 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 446 (idx) & BIT_VEC64_ELEM_MASK) 447 448 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 449 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 450 (idx) & BIT_VEC64_ELEM_MASK) 451 452 #define BIT_VEC64_TEST_BIT(vec64, idx) \ 453 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 454 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 455 456 /* Creates a bitmask of all ones in less significant bits. 457 idx - index of the most significant bit in the created mask */ 458 #define BIT_VEC64_ONES_MASK(idx) \ 459 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 460 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 461 462 /*******************************************************/ 463 464 /* Number of u64 elements in SGE mask array */ 465 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 466 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 467 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 468 469 union host_hc_status_block { 470 /* pointer to fp status block e1x */ 471 struct host_hc_status_block_e1x *e1x_sb; 472 /* pointer to fp status block e2 */ 473 struct host_hc_status_block_e2 *e2_sb; 474 }; 475 476 struct bnx2x_agg_info { 477 /* 478 * First aggregation buffer is a data buffer, the following - are pages. 479 * We will preallocate the data buffer for each aggregation when 480 * we open the interface and will replace the BD at the consumer 481 * with this one when we receive the TPA_START CQE in order to 482 * keep the Rx BD ring consistent. 483 */ 484 struct sw_rx_bd first_buf; 485 u8 tpa_state; 486 #define BNX2X_TPA_START 1 487 #define BNX2X_TPA_STOP 2 488 #define BNX2X_TPA_ERROR 3 489 u8 placement_offset; 490 u16 parsing_flags; 491 u16 vlan_tag; 492 u16 len_on_bd; 493 u32 rxhash; 494 enum pkt_hash_types rxhash_type; 495 u16 gro_size; 496 u16 full_page; 497 }; 498 499 #define Q_STATS_OFFSET32(stat_name) \ 500 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 501 502 struct bnx2x_fp_txdata { 503 504 struct sw_tx_bd *tx_buf_ring; 505 506 union eth_tx_bd_types *tx_desc_ring; 507 dma_addr_t tx_desc_mapping; 508 509 u32 cid; 510 511 union db_prod tx_db; 512 513 u16 tx_pkt_prod; 514 u16 tx_pkt_cons; 515 u16 tx_bd_prod; 516 u16 tx_bd_cons; 517 518 unsigned long tx_pkt; 519 520 __le16 *tx_cons_sb; 521 522 int txq_index; 523 struct bnx2x_fastpath *parent_fp; 524 int tx_ring_size; 525 }; 526 527 enum bnx2x_tpa_mode_t { 528 TPA_MODE_DISABLED, 529 TPA_MODE_LRO, 530 TPA_MODE_GRO 531 }; 532 533 struct bnx2x_alloc_pool { 534 struct page *page; 535 unsigned int offset; 536 }; 537 538 struct bnx2x_fastpath { 539 struct bnx2x *bp; /* parent */ 540 541 struct napi_struct napi; 542 543 union host_hc_status_block status_blk; 544 /* chip independent shortcuts into sb structure */ 545 __le16 *sb_index_values; 546 __le16 *sb_running_index; 547 /* chip independent shortcut into rx_prods_offset memory */ 548 u32 ustorm_rx_prods_offset; 549 550 u32 rx_buf_size; 551 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 552 dma_addr_t status_blk_mapping; 553 554 enum bnx2x_tpa_mode_t mode; 555 556 u8 max_cos; /* actual number of active tx coses */ 557 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 558 559 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 560 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 561 562 struct eth_rx_bd *rx_desc_ring; 563 dma_addr_t rx_desc_mapping; 564 565 union eth_rx_cqe *rx_comp_ring; 566 dma_addr_t rx_comp_mapping; 567 568 /* SGE ring */ 569 struct eth_rx_sge *rx_sge_ring; 570 dma_addr_t rx_sge_mapping; 571 572 u64 sge_mask[RX_SGE_MASK_LEN]; 573 574 u32 cid; 575 576 __le16 fp_hc_idx; 577 578 u8 index; /* number in fp array */ 579 u8 rx_queue; /* index for skb_record */ 580 u8 cl_id; /* eth client id */ 581 u8 cl_qzone_id; 582 u8 fw_sb_id; /* status block number in FW */ 583 u8 igu_sb_id; /* status block number in HW */ 584 585 u16 rx_bd_prod; 586 u16 rx_bd_cons; 587 u16 rx_comp_prod; 588 u16 rx_comp_cons; 589 u16 rx_sge_prod; 590 /* The last maximal completed SGE */ 591 u16 last_max_sge; 592 __le16 *rx_cons_sb; 593 594 /* TPA related */ 595 struct bnx2x_agg_info *tpa_info; 596 #ifdef BNX2X_STOP_ON_ERROR 597 u64 tpa_queue_used; 598 #endif 599 /* The size is calculated using the following: 600 sizeof name field from netdev structure + 601 4 ('-Xx-' string) + 602 4 (for the digits and to make it DWORD aligned) */ 603 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 604 char name[FP_NAME_SIZE]; 605 606 struct bnx2x_alloc_pool page_pool; 607 }; 608 609 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 610 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 611 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 612 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 613 614 /* Use 2500 as a mini-jumbo MTU for FCoE */ 615 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 616 617 #define FCOE_IDX_OFFSET 0 618 619 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 620 FCOE_IDX_OFFSET) 621 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 622 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 623 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 624 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 625 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 626 txdata_ptr[FIRST_TX_COS_INDEX] \ 627 ->var) 628 629 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 630 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 631 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 632 633 /* MC hsi */ 634 #define MAX_FETCH_BD 13 /* HW max BDs per packet */ 635 #define RX_COPY_THRESH 92 636 637 #define NUM_TX_RINGS 16 638 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 639 #define NEXT_PAGE_TX_DESC_CNT 1 640 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 641 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 642 #define MAX_TX_BD (NUM_TX_BD - 1) 643 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 644 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 645 (MAX_TX_DESC_CNT - 1)) ? \ 646 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 647 (x) + 1) 648 #define TX_BD(x) ((x) & MAX_TX_BD) 649 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 650 651 /* number of NEXT_PAGE descriptors may be required during placement */ 652 #define NEXT_CNT_PER_TX_PKT(bds) \ 653 (((bds) + MAX_TX_DESC_CNT - 1) / \ 654 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 655 /* max BDs per tx packet w/o next_pages: 656 * START_BD - describes packed 657 * START_BD(splitted) - includes unpaged data segment for GSO 658 * PARSING_BD - for TSO and CSUM data 659 * PARSING_BD2 - for encapsulation data 660 * Frag BDs - describes pages for frags 661 */ 662 #define BDS_PER_TX_PKT 4 663 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 664 /* max BDs per tx packet including next pages */ 665 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 666 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 667 668 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 669 #define NUM_RX_RINGS 8 670 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 671 #define NEXT_PAGE_RX_DESC_CNT 2 672 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 673 #define RX_DESC_MASK (RX_DESC_CNT - 1) 674 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 675 #define MAX_RX_BD (NUM_RX_BD - 1) 676 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 677 678 /* dropless fc calculations for BDs 679 * 680 * Number of BDs should as number of buffers in BRB: 681 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 682 * "next" elements on each page 683 */ 684 #define NUM_BD_REQ BRB_SIZE(bp) 685 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 686 MAX_RX_DESC_CNT) 687 #define BD_TH_LO(bp) (NUM_BD_REQ + \ 688 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 689 FW_DROP_LEVEL(bp)) 690 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 691 692 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 693 694 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 695 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 696 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 697 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 698 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 699 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 700 MIN_RX_AVAIL)) 701 702 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 703 (MAX_RX_DESC_CNT - 1)) ? \ 704 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 705 (x) + 1) 706 #define RX_BD(x) ((x) & MAX_RX_BD) 707 708 /* 709 * As long as CQE is X times bigger than BD entry we have to allocate X times 710 * more pages for CQ ring in order to keep it balanced with BD ring 711 */ 712 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 713 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 714 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 715 #define NEXT_PAGE_RCQ_DESC_CNT 1 716 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 717 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 718 #define MAX_RCQ_BD (NUM_RCQ_BD - 1) 719 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 720 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 721 (MAX_RCQ_DESC_CNT - 1)) ? \ 722 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 723 (x) + 1) 724 #define RCQ_BD(x) ((x) & MAX_RCQ_BD) 725 726 /* dropless fc calculations for RCQs 727 * 728 * Number of RCQs should be as number of buffers in BRB: 729 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 730 * "next" elements on each page 731 */ 732 #define NUM_RCQ_REQ BRB_SIZE(bp) 733 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 734 MAX_RCQ_DESC_CNT) 735 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 736 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 737 FW_DROP_LEVEL(bp)) 738 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 739 740 /* This is needed for determining of last_max */ 741 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 742 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 743 744 #define BNX2X_SWCID_SHIFT 17 745 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 746 747 /* used on a CID received from the HW */ 748 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 749 #define CQE_CMD(x) (le32_to_cpu(x) >> \ 750 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 751 752 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 753 le32_to_cpu((bd)->addr_lo)) 754 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 755 756 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 757 #define BNX2X_DB_SHIFT 3 /* 8 bytes*/ 758 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 759 #error "Min DB doorbell stride is 8" 760 #endif 761 #define DOORBELL(bp, cid, val) \ 762 do { \ 763 writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \ 764 } while (0) 765 766 /* TX CSUM helpers */ 767 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 768 skb->csum_offset) 769 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 770 skb->csum_offset)) 771 772 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) 773 774 #define XMIT_PLAIN 0 775 #define XMIT_CSUM_V4 (1 << 0) 776 #define XMIT_CSUM_V6 (1 << 1) 777 #define XMIT_CSUM_TCP (1 << 2) 778 #define XMIT_GSO_V4 (1 << 3) 779 #define XMIT_GSO_V6 (1 << 4) 780 #define XMIT_CSUM_ENC_V4 (1 << 5) 781 #define XMIT_CSUM_ENC_V6 (1 << 6) 782 #define XMIT_GSO_ENC_V4 (1 << 7) 783 #define XMIT_GSO_ENC_V6 (1 << 8) 784 785 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) 786 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) 787 788 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) 789 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) 790 791 /* stuff added to make the code fit 80Col */ 792 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 793 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 794 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 795 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 796 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 797 798 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 799 800 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 801 (((le16_to_cpu(flags) & \ 802 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 803 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 804 == PRS_FLAG_OVERETH_IPV4) 805 #define BNX2X_RX_SUM_FIX(cqe) \ 806 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 807 808 #define FP_USB_FUNC_OFF \ 809 offsetof(struct cstorm_status_block_u, func) 810 #define FP_CSB_FUNC_OFF \ 811 offsetof(struct cstorm_status_block_c, func) 812 813 #define HC_INDEX_ETH_RX_CQ_CONS 1 814 815 #define HC_INDEX_OOO_TX_CQ_CONS 4 816 817 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 818 819 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 820 821 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 822 823 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 824 825 #define BNX2X_RX_SB_INDEX \ 826 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 827 828 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 829 830 #define BNX2X_TX_SB_INDEX_COS0 \ 831 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 832 833 /* end of fast path */ 834 835 /* common */ 836 837 struct bnx2x_common { 838 839 u32 chip_id; 840 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 841 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 842 843 #define CHIP_NUM(bp) (bp->common.chip_id >> 16) 844 #define CHIP_NUM_57710 0x164e 845 #define CHIP_NUM_57711 0x164f 846 #define CHIP_NUM_57711E 0x1650 847 #define CHIP_NUM_57712 0x1662 848 #define CHIP_NUM_57712_MF 0x1663 849 #define CHIP_NUM_57712_VF 0x166f 850 #define CHIP_NUM_57713 0x1651 851 #define CHIP_NUM_57713E 0x1652 852 #define CHIP_NUM_57800 0x168a 853 #define CHIP_NUM_57800_MF 0x16a5 854 #define CHIP_NUM_57800_VF 0x16a9 855 #define CHIP_NUM_57810 0x168e 856 #define CHIP_NUM_57810_MF 0x16ae 857 #define CHIP_NUM_57810_VF 0x16af 858 #define CHIP_NUM_57811 0x163d 859 #define CHIP_NUM_57811_MF 0x163e 860 #define CHIP_NUM_57811_VF 0x163f 861 #define CHIP_NUM_57840_OBSOLETE 0x168d 862 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 863 #define CHIP_NUM_57840_4_10 0x16a1 864 #define CHIP_NUM_57840_2_20 0x16a2 865 #define CHIP_NUM_57840_MF 0x16a4 866 #define CHIP_NUM_57840_VF 0x16ad 867 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 868 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 869 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 870 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 871 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 872 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 873 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 874 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 875 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 876 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 877 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 878 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 879 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 880 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 881 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 882 #define CHIP_IS_57840(bp) \ 883 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 884 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 885 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 886 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 887 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 888 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 889 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 890 CHIP_IS_57711E(bp)) 891 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ 892 CHIP_IS_57811_MF(bp) || \ 893 CHIP_IS_57811_VF(bp)) 894 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 895 CHIP_IS_57712_MF(bp) || \ 896 CHIP_IS_57712_VF(bp)) 897 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 898 CHIP_IS_57800_MF(bp) || \ 899 CHIP_IS_57800_VF(bp) || \ 900 CHIP_IS_57810(bp) || \ 901 CHIP_IS_57810_MF(bp) || \ 902 CHIP_IS_57810_VF(bp) || \ 903 CHIP_IS_57811xx(bp) || \ 904 CHIP_IS_57840(bp) || \ 905 CHIP_IS_57840_MF(bp) || \ 906 CHIP_IS_57840_VF(bp)) 907 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 908 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 909 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 910 911 #define CHIP_REV_SHIFT 12 912 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 913 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 914 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 915 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 916 /* assume maximum 5 revisions */ 917 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 918 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 919 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 920 !(CHIP_REV_VAL(bp) & 0x00001000)) 921 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 922 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 923 (CHIP_REV_VAL(bp) & 0x00001000)) 924 925 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 926 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 927 928 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 929 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 930 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 931 (CHIP_REV_SHIFT + 1)) \ 932 << CHIP_REV_SHIFT) 933 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 934 CHIP_REV_SIM(bp) :\ 935 CHIP_REV_VAL(bp)) 936 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 937 (CHIP_REV(bp) == CHIP_REV_Bx)) 938 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 939 (CHIP_REV(bp) == CHIP_REV_Ax)) 940 /* This define is used in two main places: 941 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher 942 * to nic-only mode or to offload mode. Offload mode is configured if either the 943 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 944 * registered for this port (which means that the user wants storage services). 945 * 2. During cnic-related load, to know if offload mode is already configured in 946 * the HW or needs to be configured. 947 * Since the transition from nic-mode to offload-mode in HW causes traffic 948 * corruption, nic-mode is configured only in ports on which storage services 949 * where never requested. 950 */ 951 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 952 953 int flash_size; 954 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 955 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 956 #define BNX2X_NVRAM_PAGE_SIZE 256 957 958 u32 shmem_base; 959 u32 shmem2_base; 960 u32 mf_cfg_base; 961 u32 mf2_cfg_base; 962 963 u32 hw_config; 964 965 u32 bc_ver; 966 967 u8 int_block; 968 #define INT_BLOCK_HC 0 969 #define INT_BLOCK_IGU 1 970 #define INT_BLOCK_MODE_NORMAL 0 971 #define INT_BLOCK_MODE_BW_COMP 2 972 #define CHIP_INT_MODE_IS_NBC(bp) \ 973 (!CHIP_IS_E1x(bp) && \ 974 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 975 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 976 977 u8 chip_port_mode; 978 #define CHIP_4_PORT_MODE 0x0 979 #define CHIP_2_PORT_MODE 0x1 980 #define CHIP_PORT_MODE_NONE 0x2 981 #define CHIP_MODE(bp) (bp->common.chip_port_mode) 982 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 983 984 u32 boot_mode; 985 }; 986 987 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 988 #define BNX2X_IGU_STAS_MSG_VF_CNT 64 989 #define BNX2X_IGU_STAS_MSG_PF_CNT 4 990 991 #define MAX_IGU_ATTN_ACK_TO 100 992 /* end of common */ 993 994 /* port */ 995 996 struct bnx2x_port { 997 u32 pmf; 998 999 u32 link_config[LINK_CONFIG_SIZE]; 1000 1001 u32 supported[LINK_CONFIG_SIZE]; 1002 1003 u32 advertising[LINK_CONFIG_SIZE]; 1004 1005 u32 phy_addr; 1006 1007 /* used to synchronize phy accesses */ 1008 struct mutex phy_mutex; 1009 1010 u32 port_stx; 1011 1012 struct nig_stats old_nig_stats; 1013 }; 1014 1015 /* end of port */ 1016 1017 #define STATS_OFFSET32(stat_name) \ 1018 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 1019 1020 /* slow path */ 1021 #define BNX2X_MAX_NUM_OF_VFS 64 1022 #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */ 1023 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 1024 1025 /* We need to reserve doorbell addresses for all VF and queue combinations */ 1026 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 1027 1028 /* The doorbell is configured to have the same number of CIDs for PFs and for 1029 * VFs. For this reason the PF CID zone is as large as the VF zone. 1030 */ 1031 #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS 1032 #define BNX2X_MAX_NUM_VF_QUEUES 64 1033 #define BNX2X_VF_ID_INVALID 0xFF 1034 1035 /* the number of VF CIDS multiplied by the amount of bytes reserved for each 1036 * cid must not exceed the size of the VF doorbell 1037 */ 1038 #define BNX2X_VF_BAR_SIZE 512 1039 #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT)) 1040 #error "VF doorbell bar size is 512" 1041 #endif 1042 1043 /* 1044 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 1045 * control by the number of fast-path status blocks supported by the 1046 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 1047 * status block represents an independent interrupts context that can 1048 * serve a regular L2 networking queue. However special L2 queues such 1049 * as the FCoE queue do not require a FP-SB and other components like 1050 * the CNIC may consume FP-SB reducing the number of possible L2 queues 1051 * 1052 * If the maximum number of FP-SB available is X then: 1053 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 1054 * regular L2 queues is Y=X-1 1055 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1056 * c. If the FCoE L2 queue is supported the actual number of L2 queues 1057 * is Y+1 1058 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1059 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1060 * FP interrupt context for the CNIC). 1061 * e. The number of HW context (CID count) is always X or X+1 if FCoE 1062 * L2 queue is supported. The cid for the FCoE L2 queue is always X. 1063 */ 1064 1065 /* fast-path interrupt contexts E1x */ 1066 #define FP_SB_MAX_E1x 16 1067 /* fast-path interrupt contexts E2 */ 1068 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1069 1070 union cdu_context { 1071 struct eth_context eth; 1072 char pad[1024]; 1073 }; 1074 1075 /* CDU host DB constants */ 1076 #define CDU_ILT_PAGE_SZ_HW 2 1077 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1078 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1079 1080 #define CNIC_ISCSI_CID_MAX 256 1081 #define CNIC_FCOE_CID_MAX 2048 1082 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1083 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1084 1085 #define QM_ILT_PAGE_SZ_HW 0 1086 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1087 #define QM_CID_ROUND 1024 1088 1089 /* TM (timers) host DB constants */ 1090 #define TM_ILT_PAGE_SZ_HW 0 1091 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1092 #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \ 1093 BNX2X_VF_CIDS + \ 1094 CNIC_ISCSI_CID_MAX) 1095 #define TM_ILT_SZ (8 * TM_CONN_NUM) 1096 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1097 1098 /* SRC (Searcher) host DB constants */ 1099 #define SRC_ILT_PAGE_SZ_HW 0 1100 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1101 #define SRC_HASH_BITS 10 1102 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1103 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1104 #define SRC_T2_SZ SRC_ILT_SZ 1105 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1106 1107 #define MAX_DMAE_C 8 1108 1109 /* DMA memory not used in fastpath */ 1110 struct bnx2x_slowpath { 1111 union { 1112 struct mac_configuration_cmd e1x; 1113 struct eth_classify_rules_ramrod_data e2; 1114 } mac_rdata; 1115 1116 union { 1117 struct eth_classify_rules_ramrod_data e2; 1118 } vlan_rdata; 1119 1120 union { 1121 struct tstorm_eth_mac_filter_config e1x; 1122 struct eth_filter_rules_ramrod_data e2; 1123 } rx_mode_rdata; 1124 1125 union { 1126 struct mac_configuration_cmd e1; 1127 struct eth_multicast_rules_ramrod_data e2; 1128 } mcast_rdata; 1129 1130 struct eth_rss_update_ramrod_data rss_rdata; 1131 1132 /* Queue State related ramrods are always sent under rtnl_lock */ 1133 union { 1134 struct client_init_ramrod_data init_data; 1135 struct client_update_ramrod_data update_data; 1136 struct tpa_update_ramrod_data tpa_data; 1137 } q_rdata; 1138 1139 union { 1140 struct function_start_data func_start; 1141 /* pfc configuration for DCBX ramrod */ 1142 struct flow_control_configuration pfc_config; 1143 } func_rdata; 1144 1145 /* afex ramrod can not be a part of func_rdata union because these 1146 * events might arrive in parallel to other events from func_rdata. 1147 * Therefore, if they would have been defined in the same union, 1148 * data can get corrupted. 1149 */ 1150 union { 1151 struct afex_vif_list_ramrod_data viflist_data; 1152 struct function_update_data func_update; 1153 } func_afex_rdata; 1154 1155 /* used by dmae command executer */ 1156 struct dmae_command dmae[MAX_DMAE_C]; 1157 1158 u32 stats_comp; 1159 union mac_stats mac_stats; 1160 struct nig_stats nig_stats; 1161 struct host_port_stats port_stats; 1162 struct host_func_stats func_stats; 1163 1164 u32 wb_comp; 1165 u32 wb_data[4]; 1166 1167 union drv_info_to_mcp drv_info_to_mcp; 1168 }; 1169 1170 #define bnx2x_sp(bp, var) (&bp->slowpath->var) 1171 #define bnx2x_sp_mapping(bp, var) \ 1172 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1173 1174 /* attn group wiring */ 1175 #define MAX_DYNAMIC_ATTN_GRPS 8 1176 1177 struct attn_route { 1178 u32 sig[5]; 1179 }; 1180 1181 struct iro { 1182 u32 base; 1183 u16 m1; 1184 u16 m2; 1185 u16 m3; 1186 u16 size; 1187 }; 1188 1189 struct hw_context { 1190 union cdu_context *vcxt; 1191 dma_addr_t cxt_mapping; 1192 size_t size; 1193 }; 1194 1195 /* forward */ 1196 struct bnx2x_ilt; 1197 1198 struct bnx2x_vfdb; 1199 1200 enum bnx2x_recovery_state { 1201 BNX2X_RECOVERY_DONE, 1202 BNX2X_RECOVERY_INIT, 1203 BNX2X_RECOVERY_WAIT, 1204 BNX2X_RECOVERY_FAILED, 1205 BNX2X_RECOVERY_NIC_LOADING 1206 }; 1207 1208 /* 1209 * Event queue (EQ or event ring) MC hsi 1210 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1211 */ 1212 #define NUM_EQ_PAGES 1 1213 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1214 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1215 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1216 #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1217 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1218 1219 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1220 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1221 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1222 1223 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1224 #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1225 1226 #define BNX2X_EQ_INDEX \ 1227 (&bp->def_status_blk->sp_sb.\ 1228 index_values[HC_SP_INDEX_EQ_CONS]) 1229 1230 /* This is a data that will be used to create a link report message. 1231 * We will keep the data used for the last link report in order 1232 * to prevent reporting the same link parameters twice. 1233 */ 1234 struct bnx2x_link_report_data { 1235 u16 line_speed; /* Effective line speed */ 1236 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1237 }; 1238 1239 enum { 1240 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1241 BNX2X_LINK_REPORT_LINK_DOWN, 1242 BNX2X_LINK_REPORT_RX_FC_ON, 1243 BNX2X_LINK_REPORT_TX_FC_ON, 1244 }; 1245 1246 enum { 1247 BNX2X_PORT_QUERY_IDX, 1248 BNX2X_PF_QUERY_IDX, 1249 BNX2X_FCOE_QUERY_IDX, 1250 BNX2X_FIRST_QUEUE_QUERY_IDX, 1251 }; 1252 1253 struct bnx2x_fw_stats_req { 1254 struct stats_query_header hdr; 1255 struct stats_query_entry query[FP_SB_MAX_E1x+ 1256 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1257 }; 1258 1259 struct bnx2x_fw_stats_data { 1260 struct stats_counter storm_counters; 1261 struct per_port_stats port; 1262 struct per_pf_stats pf; 1263 struct fcoe_statistics_params fcoe; 1264 struct per_queue_stats queue_stats[1]; 1265 }; 1266 1267 /* Public slow path states */ 1268 enum sp_rtnl_flag { 1269 BNX2X_SP_RTNL_SETUP_TC, 1270 BNX2X_SP_RTNL_TX_TIMEOUT, 1271 BNX2X_SP_RTNL_FAN_FAILURE, 1272 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1273 BNX2X_SP_RTNL_ENABLE_SRIOV, 1274 BNX2X_SP_RTNL_VFPF_MCAST, 1275 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 1276 BNX2X_SP_RTNL_RX_MODE, 1277 BNX2X_SP_RTNL_HYPERVISOR_VLAN, 1278 BNX2X_SP_RTNL_TX_STOP, 1279 BNX2X_SP_RTNL_GET_DRV_VERSION, 1280 BNX2X_SP_RTNL_CHANGE_UDP_PORT, 1281 }; 1282 1283 enum bnx2x_iov_flag { 1284 BNX2X_IOV_HANDLE_VF_MSG, 1285 BNX2X_IOV_HANDLE_FLR, 1286 }; 1287 1288 struct bnx2x_prev_path_list { 1289 struct list_head list; 1290 u8 bus; 1291 u8 slot; 1292 u8 path; 1293 u8 aer; 1294 u8 undi; 1295 }; 1296 1297 struct bnx2x_sp_objs { 1298 /* MACs object */ 1299 struct bnx2x_vlan_mac_obj mac_obj; 1300 1301 /* Queue State object */ 1302 struct bnx2x_queue_sp_obj q_obj; 1303 1304 /* VLANs object */ 1305 struct bnx2x_vlan_mac_obj vlan_obj; 1306 }; 1307 1308 struct bnx2x_fp_stats { 1309 struct tstorm_per_queue_stats old_tclient; 1310 struct ustorm_per_queue_stats old_uclient; 1311 struct xstorm_per_queue_stats old_xclient; 1312 struct bnx2x_eth_q_stats eth_q_stats; 1313 struct bnx2x_eth_q_stats_old eth_q_stats_old; 1314 }; 1315 1316 enum { 1317 SUB_MF_MODE_UNKNOWN = 0, 1318 SUB_MF_MODE_UFP, 1319 SUB_MF_MODE_NPAR1_DOT_5, 1320 SUB_MF_MODE_BD, 1321 }; 1322 1323 struct bnx2x_vlan_entry { 1324 struct list_head link; 1325 u16 vid; 1326 bool hw; 1327 }; 1328 1329 enum bnx2x_udp_port_type { 1330 BNX2X_UDP_PORT_VXLAN, 1331 BNX2X_UDP_PORT_GENEVE, 1332 BNX2X_UDP_PORT_MAX, 1333 }; 1334 1335 struct bnx2x_udp_tunnel { 1336 u16 dst_port; 1337 u8 count; 1338 }; 1339 1340 struct bnx2x { 1341 /* Fields used in the tx and intr/napi performance paths 1342 * are grouped together in the beginning of the structure 1343 */ 1344 struct bnx2x_fastpath *fp; 1345 struct bnx2x_sp_objs *sp_objs; 1346 struct bnx2x_fp_stats *fp_stats; 1347 struct bnx2x_fp_txdata *bnx2x_txq; 1348 void __iomem *regview; 1349 void __iomem *doorbells; 1350 u16 db_size; 1351 1352 u8 pf_num; /* absolute PF number */ 1353 u8 pfid; /* per-path PF number */ 1354 int base_fw_ndsb; /**/ 1355 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1356 #define BP_PORT(bp) (bp->pfid & 1) 1357 #define BP_FUNC(bp) (bp->pfid) 1358 #define BP_ABS_FUNC(bp) (bp->pf_num) 1359 #define BP_VN(bp) ((bp)->pfid >> 1) 1360 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1361 #define BP_L_ID(bp) (BP_VN(bp) << 2) 1362 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1363 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1364 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1365 1366 #ifdef CONFIG_BNX2X_SRIOV 1367 /* protects vf2pf mailbox from simultaneous access */ 1368 struct mutex vf2pf_mutex; 1369 /* vf pf channel mailbox contains request and response buffers */ 1370 struct bnx2x_vf_mbx_msg *vf2pf_mbox; 1371 dma_addr_t vf2pf_mbox_mapping; 1372 1373 /* we set aside a copy of the acquire response */ 1374 struct pfvf_acquire_resp_tlv acquire_resp; 1375 1376 /* bulletin board for messages from pf to vf */ 1377 union pf_vf_bulletin *pf2vf_bulletin; 1378 dma_addr_t pf2vf_bulletin_mapping; 1379 1380 union pf_vf_bulletin shadow_bulletin; 1381 struct pf_vf_bulletin_content old_bulletin; 1382 1383 u16 requested_nr_virtfn; 1384 #endif /* CONFIG_BNX2X_SRIOV */ 1385 1386 struct net_device *dev; 1387 struct pci_dev *pdev; 1388 1389 const struct iro *iro_arr; 1390 #define IRO (bp->iro_arr) 1391 1392 enum bnx2x_recovery_state recovery_state; 1393 int is_leader; 1394 struct msix_entry *msix_table; 1395 1396 int tx_ring_size; 1397 1398 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1399 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 1400 #define ETH_MIN_PACKET_SIZE (ETH_ZLEN - ETH_HLEN) 1401 #define ETH_MAX_PACKET_SIZE ETH_DATA_LEN 1402 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 1403 /* TCP with Timestamp Option (32) + IPv6 (40) */ 1404 #define ETH_MAX_TPA_HEADER_SIZE 72 1405 1406 /* Max supported alignment is 256 (8 shift) 1407 * minimal alignment shift 6 is optimal for 57xxx HW performance 1408 */ 1409 #define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT)) 1410 1411 /* FW uses 2 Cache lines Alignment for start packet and size 1412 * 1413 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1414 * at the end of skb->data, to avoid wasting a full cache line. 1415 * This reduces memory use (skb->truesize). 1416 */ 1417 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1418 1419 #define BNX2X_FW_RX_ALIGN_END \ 1420 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1421 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1422 1423 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1424 1425 struct host_sp_status_block *def_status_blk; 1426 #define DEF_SB_IGU_ID 16 1427 #define DEF_SB_ID HC_SP_SB_ID 1428 __le16 def_idx; 1429 __le16 def_att_idx; 1430 u32 attn_state; 1431 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1432 1433 /* slow path ring */ 1434 struct eth_spe *spq; 1435 dma_addr_t spq_mapping; 1436 u16 spq_prod_idx; 1437 struct eth_spe *spq_prod_bd; 1438 struct eth_spe *spq_last_bd; 1439 __le16 *dsb_sp_prod; 1440 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1441 /* used to synchronize spq accesses */ 1442 spinlock_t spq_lock; 1443 1444 /* event queue */ 1445 union event_ring_elem *eq_ring; 1446 dma_addr_t eq_mapping; 1447 u16 eq_prod; 1448 u16 eq_cons; 1449 __le16 *eq_cons_sb; 1450 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1451 1452 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1453 u16 stats_pending; 1454 /* Counter for completed statistics ramrods */ 1455 u16 stats_comp; 1456 1457 /* End of fields used in the performance code paths */ 1458 1459 int panic; 1460 int msg_enable; 1461 1462 u32 flags; 1463 #define PCIX_FLAG (1 << 0) 1464 #define PCI_32BIT_FLAG (1 << 1) 1465 #define ONE_PORT_FLAG (1 << 2) 1466 #define NO_WOL_FLAG (1 << 3) 1467 #define USING_MSIX_FLAG (1 << 5) 1468 #define USING_MSI_FLAG (1 << 6) 1469 #define DISABLE_MSI_FLAG (1 << 7) 1470 #define NO_MCP_FLAG (1 << 9) 1471 #define MF_FUNC_DIS (1 << 11) 1472 #define OWN_CNIC_IRQ (1 << 12) 1473 #define NO_ISCSI_OOO_FLAG (1 << 13) 1474 #define NO_ISCSI_FLAG (1 << 14) 1475 #define NO_FCOE_FLAG (1 << 15) 1476 #define BC_SUPPORTS_PFC_STATS (1 << 17) 1477 #define TX_SWITCHING (1 << 18) 1478 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 1479 #define USING_SINGLE_MSIX_FLAG (1 << 20) 1480 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 1481 #define IS_VF_FLAG (1 << 22) 1482 #define BC_SUPPORTS_RMMOD_CMD (1 << 23) 1483 #define HAS_PHYS_PORT_ID (1 << 24) 1484 #define AER_ENABLED (1 << 25) 1485 #define PTP_SUPPORTED (1 << 26) 1486 #define TX_TIMESTAMPING_EN (1 << 27) 1487 1488 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 1489 1490 #ifdef CONFIG_BNX2X_SRIOV 1491 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 1492 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 1493 #else 1494 #define IS_VF(bp) false 1495 #define IS_PF(bp) true 1496 #endif 1497 1498 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1499 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1500 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1501 1502 u8 cnic_support; 1503 bool cnic_enabled; 1504 bool cnic_loaded; 1505 struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 1506 1507 /* Flag that indicates that we can start looking for FCoE L2 queue 1508 * completions in the default status block. 1509 */ 1510 bool fcoe_init; 1511 1512 int mrrs; 1513 1514 struct delayed_work sp_task; 1515 struct delayed_work iov_task; 1516 1517 atomic_t interrupt_occurred; 1518 struct delayed_work sp_rtnl_task; 1519 1520 struct delayed_work period_task; 1521 struct timer_list timer; 1522 int current_interval; 1523 1524 u16 fw_seq; 1525 u16 fw_drv_pulse_wr_seq; 1526 u32 func_stx; 1527 1528 struct link_params link_params; 1529 struct link_vars link_vars; 1530 u32 link_cnt; 1531 struct bnx2x_link_report_data last_reported_link; 1532 1533 struct mdio_if_info mdio; 1534 1535 struct bnx2x_common common; 1536 struct bnx2x_port port; 1537 1538 struct cmng_init cmng; 1539 1540 u32 mf_config[E1HVN_MAX]; 1541 u32 mf_ext_config; 1542 u32 path_has_ovlan; /* E3 */ 1543 u16 mf_ov; 1544 u8 mf_mode; 1545 #define IS_MF(bp) (bp->mf_mode != 0) 1546 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1547 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1548 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1549 u8 mf_sub_mode; 1550 #define IS_MF_UFP(bp) (IS_MF_SD(bp) && \ 1551 bp->mf_sub_mode == SUB_MF_MODE_UFP) 1552 #define IS_MF_BD(bp) (IS_MF_SD(bp) && \ 1553 bp->mf_sub_mode == SUB_MF_MODE_BD) 1554 1555 u8 wol; 1556 1557 int rx_ring_size; 1558 1559 u16 tx_quick_cons_trip_int; 1560 u16 tx_quick_cons_trip; 1561 u16 tx_ticks_int; 1562 u16 tx_ticks; 1563 1564 u16 rx_quick_cons_trip_int; 1565 u16 rx_quick_cons_trip; 1566 u16 rx_ticks_int; 1567 u16 rx_ticks; 1568 /* Maximal coalescing timeout in us */ 1569 #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR) 1570 1571 u32 lin_cnt; 1572 1573 u16 state; 1574 #define BNX2X_STATE_CLOSED 0 1575 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1576 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1577 #define BNX2X_STATE_OPEN 0x3000 1578 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1579 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1580 1581 #define BNX2X_STATE_DIAG 0xe000 1582 #define BNX2X_STATE_ERROR 0xf000 1583 1584 #define BNX2X_MAX_PRIORITY 8 1585 int num_queues; 1586 uint num_ethernet_queues; 1587 uint num_cnic_queues; 1588 int disable_tpa; 1589 1590 u32 rx_mode; 1591 #define BNX2X_RX_MODE_NONE 0 1592 #define BNX2X_RX_MODE_NORMAL 1 1593 #define BNX2X_RX_MODE_ALLMULTI 2 1594 #define BNX2X_RX_MODE_PROMISC 3 1595 #define BNX2X_MAX_MULTICAST 64 1596 1597 u8 igu_dsb_id; 1598 u8 igu_base_sb; 1599 u8 igu_sb_cnt; 1600 u8 min_msix_vec_cnt; 1601 1602 u32 igu_base_addr; 1603 dma_addr_t def_status_blk_mapping; 1604 1605 struct bnx2x_slowpath *slowpath; 1606 dma_addr_t slowpath_mapping; 1607 1608 /* Mechanism protecting the drv_info_to_mcp */ 1609 struct mutex drv_info_mutex; 1610 bool drv_info_mng_owner; 1611 1612 /* Total number of FW statistics requests */ 1613 u8 fw_stats_num; 1614 1615 /* 1616 * This is a memory buffer that will contain both statistics 1617 * ramrod request and data. 1618 */ 1619 void *fw_stats; 1620 dma_addr_t fw_stats_mapping; 1621 1622 /* 1623 * FW statistics request shortcut (points at the 1624 * beginning of fw_stats buffer). 1625 */ 1626 struct bnx2x_fw_stats_req *fw_stats_req; 1627 dma_addr_t fw_stats_req_mapping; 1628 int fw_stats_req_sz; 1629 1630 /* 1631 * FW statistics data shortcut (points at the beginning of 1632 * fw_stats buffer + fw_stats_req_sz). 1633 */ 1634 struct bnx2x_fw_stats_data *fw_stats_data; 1635 dma_addr_t fw_stats_data_mapping; 1636 int fw_stats_data_sz; 1637 1638 /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB 1639 * context size we need 8 ILT entries. 1640 */ 1641 #define ILT_MAX_L2_LINES 32 1642 struct hw_context context[ILT_MAX_L2_LINES]; 1643 1644 struct bnx2x_ilt *ilt; 1645 #define BP_ILT(bp) ((bp)->ilt) 1646 #define ILT_MAX_LINES 256 1647 /* 1648 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1649 * to CNIC. 1650 */ 1651 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1652 1653 /* 1654 * Maximum CID count that might be required by the bnx2x: 1655 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1656 */ 1657 1658 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1659 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1660 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1661 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1662 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1663 ILT_PAGE_CIDS)) 1664 1665 int qm_cid_count; 1666 1667 bool dropless_fc; 1668 1669 void *t2; 1670 dma_addr_t t2_mapping; 1671 struct cnic_ops __rcu *cnic_ops; 1672 void *cnic_data; 1673 u32 cnic_tag; 1674 struct cnic_eth_dev cnic_eth_dev; 1675 union host_hc_status_block cnic_sb; 1676 dma_addr_t cnic_sb_mapping; 1677 struct eth_spe *cnic_kwq; 1678 struct eth_spe *cnic_kwq_prod; 1679 struct eth_spe *cnic_kwq_cons; 1680 struct eth_spe *cnic_kwq_last; 1681 u16 cnic_kwq_pending; 1682 u16 cnic_spq_pending; 1683 u8 fip_mac[ETH_ALEN]; 1684 struct mutex cnic_mutex; 1685 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1686 1687 /* Start index of the "special" (CNIC related) L2 clients */ 1688 u8 cnic_base_cl_id; 1689 1690 int dmae_ready; 1691 /* used to synchronize dmae accesses */ 1692 spinlock_t dmae_lock; 1693 1694 /* used to protect the FW mail box */ 1695 struct mutex fw_mb_mutex; 1696 1697 /* used to synchronize stats collecting */ 1698 int stats_state; 1699 1700 /* used for synchronization of concurrent threads statistics handling */ 1701 struct semaphore stats_lock; 1702 1703 /* used by dmae command loader */ 1704 struct dmae_command stats_dmae; 1705 int executer_idx; 1706 1707 u16 stats_counter; 1708 struct bnx2x_eth_stats eth_stats; 1709 struct host_func_stats func_stats; 1710 struct bnx2x_eth_stats_old eth_stats_old; 1711 struct bnx2x_net_stats_old net_stats_old; 1712 struct bnx2x_fw_port_stats_old fw_stats_old; 1713 bool stats_init; 1714 1715 struct z_stream_s *strm; 1716 void *gunzip_buf; 1717 dma_addr_t gunzip_mapping; 1718 int gunzip_outlen; 1719 #define FW_BUF_SIZE 0x8000 1720 #define GUNZIP_BUF(bp) (bp->gunzip_buf) 1721 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1722 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1723 1724 struct raw_op *init_ops; 1725 /* Init blocks offsets inside init_ops */ 1726 u16 *init_ops_offsets; 1727 /* Data blob - has 32 bit granularity */ 1728 u32 *init_data; 1729 u32 init_mode_flags; 1730 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1731 /* Zipped PRAM blobs - raw data */ 1732 const u8 *tsem_int_table_data; 1733 const u8 *tsem_pram_data; 1734 const u8 *usem_int_table_data; 1735 const u8 *usem_pram_data; 1736 const u8 *xsem_int_table_data; 1737 const u8 *xsem_pram_data; 1738 const u8 *csem_int_table_data; 1739 const u8 *csem_pram_data; 1740 #define INIT_OPS(bp) (bp->init_ops) 1741 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1742 #define INIT_DATA(bp) (bp->init_data) 1743 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1744 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1745 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1746 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1747 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1748 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1749 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1750 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1751 1752 #define PHY_FW_VER_LEN 20 1753 char fw_ver[32]; 1754 const struct firmware *firmware; 1755 1756 struct bnx2x_vfdb *vfdb; 1757 #define IS_SRIOV(bp) ((bp)->vfdb) 1758 1759 /* DCB support on/off */ 1760 u16 dcb_state; 1761 #define BNX2X_DCB_STATE_OFF 0 1762 #define BNX2X_DCB_STATE_ON 1 1763 1764 /* DCBX engine mode */ 1765 int dcbx_enabled; 1766 #define BNX2X_DCBX_ENABLED_OFF 0 1767 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1768 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1769 #define BNX2X_DCBX_ENABLED_INVALID (-1) 1770 1771 bool dcbx_mode_uset; 1772 1773 struct bnx2x_config_dcbx_params dcbx_config_params; 1774 struct bnx2x_dcbx_port_params dcbx_port_params; 1775 int dcb_version; 1776 1777 /* CAM credit pools */ 1778 struct bnx2x_credit_pool_obj vlans_pool; 1779 1780 struct bnx2x_credit_pool_obj macs_pool; 1781 1782 /* RX_MODE object */ 1783 struct bnx2x_rx_mode_obj rx_mode_obj; 1784 1785 /* MCAST object */ 1786 struct bnx2x_mcast_obj mcast_obj; 1787 1788 /* RSS configuration object */ 1789 struct bnx2x_rss_config_obj rss_conf_obj; 1790 1791 /* Function State controlling object */ 1792 struct bnx2x_func_sp_obj func_obj; 1793 1794 unsigned long sp_state; 1795 1796 /* operation indication for the sp_rtnl task */ 1797 unsigned long sp_rtnl_state; 1798 1799 /* Indication of the IOV tasks */ 1800 unsigned long iov_task_state; 1801 1802 /* DCBX Negotiation results */ 1803 struct dcbx_features dcbx_local_feat; 1804 u32 dcbx_error; 1805 1806 #ifdef BCM_DCBNL 1807 struct dcbx_features dcbx_remote_feat; 1808 u32 dcbx_remote_flags; 1809 #endif 1810 /* AFEX: store default vlan used */ 1811 int afex_def_vlan_tag; 1812 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1813 u32 pending_max; 1814 1815 /* multiple tx classes of service */ 1816 u8 max_cos; 1817 1818 /* priority to cos mapping */ 1819 u8 prio_to_cos[8]; 1820 1821 int fp_array_size; 1822 u32 dump_preset_idx; 1823 1824 u8 phys_port_id[ETH_ALEN]; 1825 1826 /* PTP related context */ 1827 struct ptp_clock *ptp_clock; 1828 struct ptp_clock_info ptp_clock_info; 1829 struct work_struct ptp_task; 1830 struct cyclecounter cyclecounter; 1831 struct timecounter timecounter; 1832 bool timecounter_init_done; 1833 struct sk_buff *ptp_tx_skb; 1834 unsigned long ptp_tx_start; 1835 bool hwtstamp_ioctl_called; 1836 u16 tx_type; 1837 u16 rx_filter; 1838 1839 struct bnx2x_link_report_data vf_link_vars; 1840 struct list_head vlan_reg; 1841 u16 vlan_cnt; 1842 u16 vlan_credit; 1843 bool accept_any_vlan; 1844 1845 /* Vxlan/Geneve related information */ 1846 struct bnx2x_udp_tunnel udp_tunnel_ports[BNX2X_UDP_PORT_MAX]; 1847 }; 1848 1849 /* Tx queues may be less or equal to Rx queues */ 1850 extern int num_queues; 1851 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1852 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 1853 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 1854 (bp)->num_cnic_queues) 1855 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1856 1857 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1858 1859 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1860 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1861 1862 #define RSS_IPV4_CAP_MASK \ 1863 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1864 1865 #define RSS_IPV4_TCP_CAP_MASK \ 1866 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1867 1868 #define RSS_IPV6_CAP_MASK \ 1869 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1870 1871 #define RSS_IPV6_TCP_CAP_MASK \ 1872 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1873 1874 struct bnx2x_func_init_params { 1875 /* dma */ 1876 bool spq_active; 1877 dma_addr_t spq_map; 1878 u16 spq_prod; 1879 1880 u16 func_id; /* abs fid */ 1881 u16 pf_id; 1882 }; 1883 1884 #define for_each_cnic_queue(bp, var) \ 1885 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1886 (var)++) \ 1887 if (skip_queue(bp, var)) \ 1888 continue; \ 1889 else 1890 1891 #define for_each_eth_queue(bp, var) \ 1892 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1893 1894 #define for_each_nondefault_eth_queue(bp, var) \ 1895 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1896 1897 #define for_each_queue(bp, var) \ 1898 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1899 if (skip_queue(bp, var)) \ 1900 continue; \ 1901 else 1902 1903 /* Skip forwarding FP */ 1904 #define for_each_valid_rx_queue(bp, var) \ 1905 for ((var) = 0; \ 1906 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1907 BNX2X_NUM_ETH_QUEUES(bp)); \ 1908 (var)++) \ 1909 if (skip_rx_queue(bp, var)) \ 1910 continue; \ 1911 else 1912 1913 #define for_each_rx_queue_cnic(bp, var) \ 1914 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1915 (var)++) \ 1916 if (skip_rx_queue(bp, var)) \ 1917 continue; \ 1918 else 1919 1920 #define for_each_rx_queue(bp, var) \ 1921 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1922 if (skip_rx_queue(bp, var)) \ 1923 continue; \ 1924 else 1925 1926 /* Skip OOO FP */ 1927 #define for_each_valid_tx_queue(bp, var) \ 1928 for ((var) = 0; \ 1929 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1930 BNX2X_NUM_ETH_QUEUES(bp)); \ 1931 (var)++) \ 1932 if (skip_tx_queue(bp, var)) \ 1933 continue; \ 1934 else 1935 1936 #define for_each_tx_queue_cnic(bp, var) \ 1937 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1938 (var)++) \ 1939 if (skip_tx_queue(bp, var)) \ 1940 continue; \ 1941 else 1942 1943 #define for_each_tx_queue(bp, var) \ 1944 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1945 if (skip_tx_queue(bp, var)) \ 1946 continue; \ 1947 else 1948 1949 #define for_each_nondefault_queue(bp, var) \ 1950 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1951 if (skip_queue(bp, var)) \ 1952 continue; \ 1953 else 1954 1955 #define for_each_cos_in_tx_queue(fp, var) \ 1956 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1957 1958 /* skip rx queue 1959 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1960 */ 1961 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1962 1963 /* skip tx queue 1964 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1965 */ 1966 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1967 1968 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1969 1970 /** 1971 * bnx2x_set_mac_one - configure a single MAC address 1972 * 1973 * @bp: driver handle 1974 * @mac: MAC to configure 1975 * @obj: MAC object handle 1976 * @set: if 'true' add a new MAC, otherwise - delete 1977 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1978 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1979 * 1980 * Configures one MAC according to provided parameters or continues the 1981 * execution of previously scheduled commands if RAMROD_CONT is set in 1982 * ramrod_flags. 1983 * 1984 * Returns zero if operation has successfully completed, a positive value if the 1985 * operation has been successfully scheduled and a negative - if a requested 1986 * operations has failed. 1987 */ 1988 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1989 struct bnx2x_vlan_mac_obj *obj, bool set, 1990 int mac_type, unsigned long *ramrod_flags); 1991 1992 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan, 1993 struct bnx2x_vlan_mac_obj *obj, bool set, 1994 unsigned long *ramrod_flags); 1995 1996 /** 1997 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1998 * 1999 * @bp: driver handle 2000 * @mac_obj: MAC object handle 2001 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 2002 * @wait_for_comp: if 'true' block until completion 2003 * 2004 * Deletes all MACs of the specific type (e.g. ETH, UC list). 2005 * 2006 * Returns zero if operation has successfully completed, a positive value if the 2007 * operation has been successfully scheduled and a negative - if a requested 2008 * operations has failed. 2009 */ 2010 int bnx2x_del_all_macs(struct bnx2x *bp, 2011 struct bnx2x_vlan_mac_obj *mac_obj, 2012 int mac_type, bool wait_for_comp); 2013 2014 /* Init Function API */ 2015 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 2016 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 2017 u8 vf_valid, int fw_sb_id, int igu_sb_id); 2018 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 2019 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2020 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 2021 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2022 void bnx2x_read_mf_cfg(struct bnx2x *bp); 2023 2024 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 2025 2026 /* dmae */ 2027 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 2028 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 2029 u32 len32); 2030 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 2031 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 2032 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 2033 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 2034 bool with_comp, u8 comp_type); 2035 2036 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2037 u8 src_type, u8 dst_type); 2038 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2039 u32 *comp); 2040 2041 /* FLR related routines */ 2042 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 2043 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 2044 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 2045 u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 2046 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 2047 char *msg, u32 poll_cnt); 2048 2049 void bnx2x_calc_fc_adv(struct bnx2x *bp); 2050 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 2051 u32 data_hi, u32 data_lo, int cmd_type); 2052 void bnx2x_update_coalesce(struct bnx2x *bp); 2053 int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 2054 2055 bool bnx2x_port_after_undi(struct bnx2x *bp); 2056 2057 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 2058 int wait) 2059 { 2060 u32 val; 2061 2062 do { 2063 val = REG_RD(bp, reg); 2064 if (val == expected) 2065 break; 2066 ms -= wait; 2067 msleep(wait); 2068 2069 } while (ms > 0); 2070 2071 return val; 2072 } 2073 2074 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 2075 bool is_pf); 2076 2077 #define BNX2X_ILT_ZALLOC(x, y, size) \ 2078 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL) 2079 2080 #define BNX2X_ILT_FREE(x, y, size) \ 2081 do { \ 2082 if (x) { \ 2083 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 2084 x = NULL; \ 2085 y = 0; \ 2086 } \ 2087 } while (0) 2088 2089 #define ILOG2(x) (ilog2((x))) 2090 2091 #define ILT_NUM_PAGE_ENTRIES (3072) 2092 /* In 57710/11 we use whole table since we have 8 func 2093 * In 57712 we have only 4 func, but use same size per func, then only half of 2094 * the table in use 2095 */ 2096 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 2097 2098 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 2099 /* 2100 * the phys address is shifted right 12 bits and has an added 2101 * 1=valid bit added to the 53rd bit 2102 * then since this is a wide register(TM) 2103 * we split it into two 32 bit writes 2104 */ 2105 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 2106 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 2107 2108 /* load/unload mode */ 2109 #define LOAD_NORMAL 0 2110 #define LOAD_OPEN 1 2111 #define LOAD_DIAG 2 2112 #define LOAD_LOOPBACK_EXT 3 2113 #define UNLOAD_NORMAL 0 2114 #define UNLOAD_CLOSE 1 2115 #define UNLOAD_RECOVERY 2 2116 2117 /* DMAE command defines */ 2118 #define DMAE_TIMEOUT -1 2119 #define DMAE_PCI_ERROR -2 /* E2 and onward */ 2120 #define DMAE_NOT_RDY -3 2121 #define DMAE_PCI_ERR_FLAG 0x80000000 2122 2123 #define DMAE_SRC_PCI 0 2124 #define DMAE_SRC_GRC 1 2125 2126 #define DMAE_DST_NONE 0 2127 #define DMAE_DST_PCI 1 2128 #define DMAE_DST_GRC 2 2129 2130 #define DMAE_COMP_PCI 0 2131 #define DMAE_COMP_GRC 1 2132 2133 /* E2 and onward - PCI error handling in the completion */ 2134 2135 #define DMAE_COMP_REGULAR 0 2136 #define DMAE_COM_SET_ERR 1 2137 2138 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2139 DMAE_COMMAND_SRC_SHIFT) 2140 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2141 DMAE_COMMAND_SRC_SHIFT) 2142 2143 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2144 DMAE_COMMAND_DST_SHIFT) 2145 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2146 DMAE_COMMAND_DST_SHIFT) 2147 2148 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2149 DMAE_COMMAND_C_DST_SHIFT) 2150 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2151 DMAE_COMMAND_C_DST_SHIFT) 2152 2153 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2154 2155 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2156 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2157 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2158 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2159 2160 #define DMAE_CMD_PORT_0 0 2161 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2162 2163 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2164 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2165 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2166 2167 #define DMAE_SRC_PF 0 2168 #define DMAE_SRC_VF 1 2169 2170 #define DMAE_DST_PF 0 2171 #define DMAE_DST_VF 1 2172 2173 #define DMAE_C_SRC 0 2174 #define DMAE_C_DST 1 2175 2176 #define DMAE_LEN32_RD_MAX 0x80 2177 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2178 2179 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 2180 * indicates error 2181 */ 2182 2183 #define MAX_DMAE_C_PER_PORT 8 2184 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2185 BP_VN(bp)) 2186 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2187 E1HVN_MAX) 2188 2189 /* PCIE link and speed */ 2190 #define PCICFG_LINK_WIDTH 0x1f00000 2191 #define PCICFG_LINK_WIDTH_SHIFT 20 2192 #define PCICFG_LINK_SPEED 0xf0000 2193 #define PCICFG_LINK_SPEED_SHIFT 16 2194 2195 #define BNX2X_NUM_TESTS_SF 7 2196 #define BNX2X_NUM_TESTS_MF 3 2197 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 2198 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF) 2199 2200 #define BNX2X_PHY_LOOPBACK 0 2201 #define BNX2X_MAC_LOOPBACK 1 2202 #define BNX2X_EXT_LOOPBACK 2 2203 #define BNX2X_PHY_LOOPBACK_FAILED 1 2204 #define BNX2X_MAC_LOOPBACK_FAILED 2 2205 #define BNX2X_EXT_LOOPBACK_FAILED 3 2206 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2207 BNX2X_PHY_LOOPBACK_FAILED) 2208 2209 #define STROM_ASSERT_ARRAY_SIZE 50 2210 2211 /* must be used on a CID before placing it on a HW ring */ 2212 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 2213 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2214 (x)) 2215 2216 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2217 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2218 2219 #define BNX2X_BTR 4 2220 #define MAX_SPQ_PENDING 8 2221 2222 /* CMNG constants, as derived from system spec calculations */ 2223 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2224 #define DEF_MIN_RATE 100 2225 /* resolution of the rate shaping timer - 400 usec */ 2226 #define RS_PERIODIC_TIMEOUT_USEC 400 2227 /* number of bytes in single QM arbitration cycle - 2228 * coefficient for calculating the fairness timer */ 2229 #define QM_ARB_BYTES 160000 2230 /* resolution of Min algorithm 1:100 */ 2231 #define MIN_RES 100 2232 /* how many bytes above threshold for the minimal credit of Min algorithm*/ 2233 #define MIN_ABOVE_THRESH 32768 2234 /* Fairness algorithm integration time coefficient - 2235 * for calculating the actual Tfair */ 2236 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2237 /* Memory of fairness algorithm . 2 cycles */ 2238 #define FAIR_MEM 2 2239 2240 #define ATTN_NIG_FOR_FUNC (1L << 8) 2241 #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2242 #define GPIO_2_FUNC (1L << 10) 2243 #define GPIO_3_FUNC (1L << 11) 2244 #define GPIO_4_FUNC (1L << 12) 2245 #define ATTN_GENERAL_ATTN_1 (1L << 13) 2246 #define ATTN_GENERAL_ATTN_2 (1L << 14) 2247 #define ATTN_GENERAL_ATTN_3 (1L << 15) 2248 #define ATTN_GENERAL_ATTN_4 (1L << 13) 2249 #define ATTN_GENERAL_ATTN_5 (1L << 14) 2250 #define ATTN_GENERAL_ATTN_6 (1L << 15) 2251 2252 #define ATTN_HARD_WIRED_MASK 0xff00 2253 #define ATTENTION_ID 4 2254 2255 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \ 2256 IS_MF_FCOE_AFEX(bp)) 2257 2258 /* stuff added to make the code fit 80Col */ 2259 2260 #define BNX2X_PMF_LINK_ASSERT \ 2261 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2262 2263 #define BNX2X_MC_ASSERT_BITS \ 2264 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2265 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2266 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2267 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2268 2269 #define BNX2X_MCP_ASSERT \ 2270 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2271 2272 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2273 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2274 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2275 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2276 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2277 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2278 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2279 2280 #define HW_INTERRUPT_ASSERT_SET_0 \ 2281 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2282 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2283 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2284 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2285 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2286 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2287 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2288 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2289 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2290 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2291 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2292 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2293 #define HW_INTERRUPT_ASSERT_SET_1 \ 2294 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2295 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2296 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2297 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2298 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2299 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2300 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2301 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2302 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2303 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2304 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2305 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2306 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2307 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2308 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2309 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2310 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2311 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2312 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2313 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2314 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2315 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2316 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2317 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2318 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2319 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2320 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2321 #define HW_INTERRUPT_ASSERT_SET_2 \ 2322 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2323 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2324 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2325 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2326 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2327 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2328 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2329 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2330 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2331 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2332 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2333 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2334 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2335 2336 #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \ 2337 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2338 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2339 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY) 2340 2341 #define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \ 2342 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2343 2344 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2345 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2346 2347 #define MULTI_MASK 0x7f 2348 2349 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2350 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2351 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2352 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2353 2354 #define DEF_USB_IGU_INDEX_OFF \ 2355 offsetof(struct cstorm_def_status_block_u, igu_index) 2356 #define DEF_CSB_IGU_INDEX_OFF \ 2357 offsetof(struct cstorm_def_status_block_c, igu_index) 2358 #define DEF_XSB_IGU_INDEX_OFF \ 2359 offsetof(struct xstorm_def_status_block, igu_index) 2360 #define DEF_TSB_IGU_INDEX_OFF \ 2361 offsetof(struct tstorm_def_status_block, igu_index) 2362 2363 #define DEF_USB_SEGMENT_OFF \ 2364 offsetof(struct cstorm_def_status_block_u, segment) 2365 #define DEF_CSB_SEGMENT_OFF \ 2366 offsetof(struct cstorm_def_status_block_c, segment) 2367 #define DEF_XSB_SEGMENT_OFF \ 2368 offsetof(struct xstorm_def_status_block, segment) 2369 #define DEF_TSB_SEGMENT_OFF \ 2370 offsetof(struct tstorm_def_status_block, segment) 2371 2372 #define BNX2X_SP_DSB_INDEX \ 2373 (&bp->def_status_blk->sp_sb.\ 2374 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2375 2376 #define CAM_IS_INVALID(x) \ 2377 (GET_FLAG(x.flags, \ 2378 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2379 (T_ETH_MAC_COMMAND_INVALIDATE)) 2380 2381 /* Number of u32 elements in MC hash array */ 2382 #define MC_HASH_SIZE 8 2383 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2384 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2385 2386 #ifndef PXP2_REG_PXP2_INT_STS 2387 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2388 #endif 2389 2390 #ifndef ETH_MAX_RX_CLIENTS_E2 2391 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2392 #endif 2393 2394 #define BNX2X_VPD_LEN 128 2395 #define VENDOR_ID_LEN 4 2396 2397 #define VF_ACQUIRE_THRESH 3 2398 #define VF_ACQUIRE_MAC_FILTERS 1 2399 #define VF_ACQUIRE_MC_FILTERS 10 2400 #define VF_ACQUIRE_VLAN_FILTERS 2 /* VLAN0 + 'real' VLAN */ 2401 2402 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2403 (!((me_reg) & ME_REG_VF_ERR))) 2404 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err); 2405 2406 /* Congestion management fairness mode */ 2407 #define CMNG_FNS_NONE 0 2408 #define CMNG_FNS_MINMAX 1 2409 2410 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2411 #define HC_SEG_ACCESS_ATTN 4 2412 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2413 2414 static const u32 dmae_reg_go_c[] = { 2415 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2416 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2417 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2418 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2419 }; 2420 2421 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); 2422 void bnx2x_notify_link_changed(struct bnx2x *bp); 2423 2424 #define BNX2X_MF_SD_PROTOCOL(bp) \ 2425 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2426 2427 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2428 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2429 2430 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2431 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2432 2433 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2434 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2435 #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp)) 2436 2437 #define IS_MF_ISCSI_ONLY(bp) (IS_MF_ISCSI_SD(bp) || IS_MF_ISCSI_SI(bp)) 2438 2439 #define BNX2X_MF_EXT_PROTOCOL_MASK \ 2440 (MACP_FUNC_CFG_FLAGS_ETHERNET | \ 2441 MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD | \ 2442 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2443 2444 #define BNX2X_MF_EXT_PROT(bp) ((bp)->mf_ext_config & \ 2445 BNX2X_MF_EXT_PROTOCOL_MASK) 2446 2447 #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) \ 2448 (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2449 2450 #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) \ 2451 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2452 2453 #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) \ 2454 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) 2455 2456 #define IS_MF_FCOE_AFEX(bp) \ 2457 (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)) 2458 2459 #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) \ 2460 (IS_MF_SD(bp) && \ 2461 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2462 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2463 2464 #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) \ 2465 (IS_MF_SI(bp) && \ 2466 (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \ 2467 BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))) 2468 2469 #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) \ 2470 (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) || \ 2471 IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp)) 2472 2473 /* Determines whether BW configuration arrives in 100Mb units or in 2474 * percentages from actual physical link speed. 2475 */ 2476 #define IS_MF_PERCENT_BW(bp) (IS_MF_SI(bp) || IS_MF_UFP(bp) || IS_MF_BD(bp)) 2477 2478 #define SET_FLAG(value, mask, flag) \ 2479 do {\ 2480 (value) &= ~(mask);\ 2481 (value) |= ((flag) << (mask##_SHIFT));\ 2482 } while (0) 2483 2484 #define GET_FLAG(value, mask) \ 2485 (((value) & (mask)) >> (mask##_SHIFT)) 2486 2487 #define GET_FIELD(value, fname) \ 2488 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2489 2490 enum { 2491 SWITCH_UPDATE, 2492 AFEX_UPDATE, 2493 }; 2494 2495 #define NUM_MACS 8 2496 2497 void bnx2x_set_local_cmng(struct bnx2x *bp); 2498 2499 void bnx2x_update_mng_version(struct bnx2x *bp); 2500 2501 void bnx2x_update_mfw_dump(struct bnx2x *bp); 2502 2503 #define MCPR_SCRATCH_BASE(bp) \ 2504 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 2505 2506 #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX)) 2507 2508 void bnx2x_init_ptp(struct bnx2x *bp); 2509 int bnx2x_configure_ptp_filters(struct bnx2x *bp); 2510 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb); 2511 2512 #define BNX2X_MAX_PHC_DRIFT 31000000 2513 #define BNX2X_PTP_TX_TIMEOUT 2514 2515 /* Re-configure all previously configured vlan filters. 2516 * Meant for implicit re-load flows. 2517 */ 2518 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp); 2519 2520 #endif /* bnx2x.h */ 2521