1 /* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14 #ifndef BNX2X_H 15 #define BNX2X_H 16 #include <linux/netdevice.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/types.h> 19 20 /* compilation time flags */ 21 22 /* define this to make the driver freeze on error to allow getting debug info 23 * (you will need to reboot afterwards) */ 24 /* #define BNX2X_STOP_ON_ERROR */ 25 26 #define DRV_MODULE_VERSION "1.72.00-0" 27 #define DRV_MODULE_RELDATE "2012/01/26" 28 #define BNX2X_BC_VER 0x040200 29 30 #if defined(CONFIG_DCB) 31 #define BCM_DCBNL 32 #endif 33 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) 34 #define BCM_CNIC 1 35 #include "../cnic_if.h" 36 #endif 37 38 #ifdef BCM_CNIC 39 #define BNX2X_MIN_MSIX_VEC_CNT 3 40 #define BNX2X_MSIX_VEC_FP_START 2 41 #else 42 #define BNX2X_MIN_MSIX_VEC_CNT 2 43 #define BNX2X_MSIX_VEC_FP_START 1 44 #endif 45 46 #include <linux/mdio.h> 47 48 #include "bnx2x_reg.h" 49 #include "bnx2x_fw_defs.h" 50 #include "bnx2x_hsi.h" 51 #include "bnx2x_link.h" 52 #include "bnx2x_sp.h" 53 #include "bnx2x_dcb.h" 54 #include "bnx2x_stats.h" 55 56 /* error/debug prints */ 57 58 #define DRV_MODULE_NAME "bnx2x" 59 60 /* for messages that are currently off */ 61 #define BNX2X_MSG_OFF 0 62 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ 63 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ 64 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ 65 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ 66 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ 67 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ 68 69 /* regular debug print */ 70 #define DP(__mask, fmt, ...) \ 71 do { \ 72 if (bp->msg_enable & (__mask)) \ 73 pr_notice("[%s:%d(%s)]" fmt, \ 74 __func__, __LINE__, \ 75 bp->dev ? (bp->dev->name) : "?", \ 76 ##__VA_ARGS__); \ 77 } while (0) 78 79 #define DP_CONT(__mask, fmt, ...) \ 80 do { \ 81 if (bp->msg_enable & (__mask)) \ 82 pr_cont(fmt, ##__VA_ARGS__); \ 83 } while (0) 84 85 /* errors debug print */ 86 #define BNX2X_DBG_ERR(fmt, ...) \ 87 do { \ 88 if (netif_msg_probe(bp)) \ 89 pr_err("[%s:%d(%s)]" fmt, \ 90 __func__, __LINE__, \ 91 bp->dev ? (bp->dev->name) : "?", \ 92 ##__VA_ARGS__); \ 93 } while (0) 94 95 /* for errors (never masked) */ 96 #define BNX2X_ERR(fmt, ...) \ 97 do { \ 98 pr_err("[%s:%d(%s)]" fmt, \ 99 __func__, __LINE__, \ 100 bp->dev ? (bp->dev->name) : "?", \ 101 ##__VA_ARGS__); \ 102 } while (0) 103 104 #define BNX2X_ERROR(fmt, ...) \ 105 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 106 107 108 /* before we have a dev->name use dev_info() */ 109 #define BNX2X_DEV_INFO(fmt, ...) \ 110 do { \ 111 if (netif_msg_probe(bp)) \ 112 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 113 } while (0) 114 115 #ifdef BNX2X_STOP_ON_ERROR 116 void bnx2x_int_disable(struct bnx2x *bp); 117 #define bnx2x_panic() \ 118 do { \ 119 bp->panic = 1; \ 120 BNX2X_ERR("driver assert\n"); \ 121 bnx2x_int_disable(bp); \ 122 bnx2x_panic_dump(bp); \ 123 } while (0) 124 #else 125 #define bnx2x_panic() \ 126 do { \ 127 bp->panic = 1; \ 128 BNX2X_ERR("driver assert\n"); \ 129 bnx2x_panic_dump(bp); \ 130 } while (0) 131 #endif 132 133 #define bnx2x_mc_addr(ha) ((ha)->addr) 134 #define bnx2x_uc_addr(ha) ((ha)->addr) 135 136 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) 137 #define U64_HI(x) (u32)(((u64)(x)) >> 32) 138 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 139 140 141 #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 142 143 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 144 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 145 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 146 147 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 148 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 149 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 150 151 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 152 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 153 154 #define REG_RD_DMAE(bp, offset, valp, len32) \ 155 do { \ 156 bnx2x_read_dmae(bp, offset, len32);\ 157 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 158 } while (0) 159 160 #define REG_WR_DMAE(bp, offset, valp, len32) \ 161 do { \ 162 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 163 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 164 offset, len32); \ 165 } while (0) 166 167 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 168 REG_WR_DMAE(bp, offset, valp, len32) 169 170 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 171 do { \ 172 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 173 bnx2x_write_big_buf_wb(bp, addr, len32); \ 174 } while (0) 175 176 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 177 offsetof(struct shmem_region, field)) 178 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 179 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 180 181 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 182 offsetof(struct shmem2_region, field)) 183 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 184 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 185 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 186 offsetof(struct mf_cfg, field)) 187 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 188 offsetof(struct mf2_cfg, field)) 189 190 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 191 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 192 MF_CFG_ADDR(bp, field), (val)) 193 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 194 195 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 196 (SHMEM2_RD((bp), size) > \ 197 offsetof(struct shmem2_region, field))) 198 199 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 200 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 201 202 /* SP SB indices */ 203 204 /* General SP events - stats query, cfc delete, etc */ 205 #define HC_SP_INDEX_ETH_DEF_CONS 3 206 207 /* EQ completions */ 208 #define HC_SP_INDEX_EQ_CONS 7 209 210 /* FCoE L2 connection completions */ 211 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 212 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 213 /* iSCSI L2 */ 214 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 215 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 216 217 /* Special clients parameters */ 218 219 /* SB indices */ 220 /* FCoE L2 */ 221 #define BNX2X_FCOE_L2_RX_INDEX \ 222 (&bp->def_status_blk->sp_sb.\ 223 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 224 225 #define BNX2X_FCOE_L2_TX_INDEX \ 226 (&bp->def_status_blk->sp_sb.\ 227 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 228 229 /** 230 * CIDs and CLIDs: 231 * CLIDs below is a CLID for func 0, then the CLID for other 232 * functions will be calculated by the formula: 233 * 234 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 235 * 236 */ 237 enum { 238 BNX2X_ISCSI_ETH_CL_ID_IDX, 239 BNX2X_FCOE_ETH_CL_ID_IDX, 240 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 241 }; 242 243 #define BNX2X_CNIC_START_ETH_CID 48 244 enum { 245 /* iSCSI L2 */ 246 BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID, 247 /* FCoE L2 */ 248 BNX2X_FCOE_ETH_CID, 249 }; 250 251 /** Additional rings budgeting */ 252 #ifdef BCM_CNIC 253 #define CNIC_PRESENT 1 254 #define FCOE_PRESENT 1 255 #else 256 #define CNIC_PRESENT 0 257 #define FCOE_PRESENT 0 258 #endif /* BCM_CNIC */ 259 #define NON_ETH_CONTEXT_USE (FCOE_PRESENT) 260 261 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 262 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 263 264 #define SM_RX_ID 0 265 #define SM_TX_ID 1 266 267 /* defines for multiple tx priority indices */ 268 #define FIRST_TX_ONLY_COS_INDEX 1 269 #define FIRST_TX_COS_INDEX 0 270 271 /* defines for decodeing the fastpath index and the cos index out of the 272 * transmission queue index 273 */ 274 #define MAX_TXQS_PER_COS FP_SB_MAX_E1x 275 276 #define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS) 277 #define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS) 278 279 /* rules for calculating the cids of tx-only connections */ 280 #define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS) 281 #define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS) 282 283 /* fp index inside class of service range */ 284 #define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS) 285 286 /* 287 * 0..15 eth cos0 288 * 16..31 eth cos1 if applicable 289 * 32..47 eth cos2 If applicable 290 * fcoe queue follows eth queues (16, 32, 48 depending on cos) 291 */ 292 #define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos) 293 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp)) 294 295 /* fast path */ 296 /* 297 * This driver uses new build_skb() API : 298 * RX ring buffer contains pointer to kmalloc() data only, 299 * skb are built only after Hardware filled the frame. 300 */ 301 struct sw_rx_bd { 302 u8 *data; 303 DEFINE_DMA_UNMAP_ADDR(mapping); 304 }; 305 306 struct sw_tx_bd { 307 struct sk_buff *skb; 308 u16 first_bd; 309 u8 flags; 310 /* Set on the first BD descriptor when there is a split BD */ 311 #define BNX2X_TSO_SPLIT_BD (1<<0) 312 }; 313 314 struct sw_rx_page { 315 struct page *page; 316 DEFINE_DMA_UNMAP_ADDR(mapping); 317 }; 318 319 union db_prod { 320 struct doorbell_set_prod data; 321 u32 raw; 322 }; 323 324 /* dropless fc FW/HW related params */ 325 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 326 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 327 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 328 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 329 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 330 #define FW_PREFETCH_CNT 16 331 #define DROPLESS_FC_HEADROOM 100 332 333 /* MC hsi */ 334 #define BCM_PAGE_SHIFT 12 335 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 336 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 337 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 338 339 #define PAGES_PER_SGE_SHIFT 0 340 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 341 #define SGE_PAGE_SIZE PAGE_SIZE 342 #define SGE_PAGE_SHIFT PAGE_SHIFT 343 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 344 345 /* SGE ring related macros */ 346 #define NUM_RX_SGE_PAGES 2 347 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 348 #define NEXT_PAGE_SGE_DESC_CNT 2 349 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 350 /* RX_SGE_CNT is promised to be a power of 2 */ 351 #define RX_SGE_MASK (RX_SGE_CNT - 1) 352 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 353 #define MAX_RX_SGE (NUM_RX_SGE - 1) 354 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 355 (MAX_RX_SGE_CNT - 1)) ? \ 356 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 357 (x) + 1) 358 #define RX_SGE(x) ((x) & MAX_RX_SGE) 359 360 /* 361 * Number of required SGEs is the sum of two: 362 * 1. Number of possible opened aggregations (next packet for 363 * these aggregations will probably consume SGE immidiatelly) 364 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 365 * after placement on BD for new TPA aggregation) 366 * 367 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 368 */ 369 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 370 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 371 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 372 MAX_RX_SGE_CNT) 373 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 374 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 375 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 376 377 /* Manipulate a bit vector defined as an array of u64 */ 378 379 /* Number of bits in one sge_mask array element */ 380 #define BIT_VEC64_ELEM_SZ 64 381 #define BIT_VEC64_ELEM_SHIFT 6 382 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 383 384 385 #define __BIT_VEC64_SET_BIT(el, bit) \ 386 do { \ 387 el = ((el) | ((u64)0x1 << (bit))); \ 388 } while (0) 389 390 #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 391 do { \ 392 el = ((el) & (~((u64)0x1 << (bit)))); \ 393 } while (0) 394 395 396 #define BIT_VEC64_SET_BIT(vec64, idx) \ 397 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 398 (idx) & BIT_VEC64_ELEM_MASK) 399 400 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 401 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 402 (idx) & BIT_VEC64_ELEM_MASK) 403 404 #define BIT_VEC64_TEST_BIT(vec64, idx) \ 405 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 406 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 407 408 /* Creates a bitmask of all ones in less significant bits. 409 idx - index of the most significant bit in the created mask */ 410 #define BIT_VEC64_ONES_MASK(idx) \ 411 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 412 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 413 414 /*******************************************************/ 415 416 417 418 /* Number of u64 elements in SGE mask array */ 419 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 420 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 421 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 422 423 union host_hc_status_block { 424 /* pointer to fp status block e1x */ 425 struct host_hc_status_block_e1x *e1x_sb; 426 /* pointer to fp status block e2 */ 427 struct host_hc_status_block_e2 *e2_sb; 428 }; 429 430 struct bnx2x_agg_info { 431 /* 432 * First aggregation buffer is a data buffer, the following - are pages. 433 * We will preallocate the data buffer for each aggregation when 434 * we open the interface and will replace the BD at the consumer 435 * with this one when we receive the TPA_START CQE in order to 436 * keep the Rx BD ring consistent. 437 */ 438 struct sw_rx_bd first_buf; 439 u8 tpa_state; 440 #define BNX2X_TPA_START 1 441 #define BNX2X_TPA_STOP 2 442 #define BNX2X_TPA_ERROR 3 443 u8 placement_offset; 444 u16 parsing_flags; 445 u16 vlan_tag; 446 u16 len_on_bd; 447 u32 rxhash; 448 u16 gro_size; 449 u16 full_page; 450 }; 451 452 #define Q_STATS_OFFSET32(stat_name) \ 453 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 454 455 struct bnx2x_fp_txdata { 456 457 struct sw_tx_bd *tx_buf_ring; 458 459 union eth_tx_bd_types *tx_desc_ring; 460 dma_addr_t tx_desc_mapping; 461 462 u32 cid; 463 464 union db_prod tx_db; 465 466 u16 tx_pkt_prod; 467 u16 tx_pkt_cons; 468 u16 tx_bd_prod; 469 u16 tx_bd_cons; 470 471 unsigned long tx_pkt; 472 473 __le16 *tx_cons_sb; 474 475 int txq_index; 476 }; 477 478 enum bnx2x_tpa_mode_t { 479 TPA_MODE_LRO, 480 TPA_MODE_GRO 481 }; 482 483 struct bnx2x_fastpath { 484 struct bnx2x *bp; /* parent */ 485 486 #define BNX2X_NAPI_WEIGHT 128 487 struct napi_struct napi; 488 union host_hc_status_block status_blk; 489 /* chip independed shortcuts into sb structure */ 490 __le16 *sb_index_values; 491 __le16 *sb_running_index; 492 /* chip independed shortcut into rx_prods_offset memory */ 493 u32 ustorm_rx_prods_offset; 494 495 u32 rx_buf_size; 496 497 dma_addr_t status_blk_mapping; 498 499 enum bnx2x_tpa_mode_t mode; 500 501 u8 max_cos; /* actual number of active tx coses */ 502 struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS]; 503 504 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 505 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 506 507 struct eth_rx_bd *rx_desc_ring; 508 dma_addr_t rx_desc_mapping; 509 510 union eth_rx_cqe *rx_comp_ring; 511 dma_addr_t rx_comp_mapping; 512 513 /* SGE ring */ 514 struct eth_rx_sge *rx_sge_ring; 515 dma_addr_t rx_sge_mapping; 516 517 u64 sge_mask[RX_SGE_MASK_LEN]; 518 519 u32 cid; 520 521 __le16 fp_hc_idx; 522 523 u8 index; /* number in fp array */ 524 u8 rx_queue; /* index for skb_record */ 525 u8 cl_id; /* eth client id */ 526 u8 cl_qzone_id; 527 u8 fw_sb_id; /* status block number in FW */ 528 u8 igu_sb_id; /* status block number in HW */ 529 530 u16 rx_bd_prod; 531 u16 rx_bd_cons; 532 u16 rx_comp_prod; 533 u16 rx_comp_cons; 534 u16 rx_sge_prod; 535 /* The last maximal completed SGE */ 536 u16 last_max_sge; 537 __le16 *rx_cons_sb; 538 unsigned long rx_pkt, 539 rx_calls; 540 541 /* TPA related */ 542 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 543 u8 disable_tpa; 544 #ifdef BNX2X_STOP_ON_ERROR 545 u64 tpa_queue_used; 546 #endif 547 548 struct tstorm_per_queue_stats old_tclient; 549 struct ustorm_per_queue_stats old_uclient; 550 struct xstorm_per_queue_stats old_xclient; 551 struct bnx2x_eth_q_stats eth_q_stats; 552 struct bnx2x_eth_q_stats_old eth_q_stats_old; 553 554 /* The size is calculated using the following: 555 sizeof name field from netdev structure + 556 4 ('-Xx-' string) + 557 4 (for the digits and to make it DWORD aligned) */ 558 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 559 char name[FP_NAME_SIZE]; 560 561 /* MACs object */ 562 struct bnx2x_vlan_mac_obj mac_obj; 563 564 /* Queue State object */ 565 struct bnx2x_queue_sp_obj q_obj; 566 567 }; 568 569 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) 570 571 /* Use 2500 as a mini-jumbo MTU for FCoE */ 572 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 573 574 /* FCoE L2 `fastpath' entry is right after the eth entries */ 575 #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp) 576 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX]) 577 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 578 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 579 txdata[FIRST_TX_COS_INDEX].var) 580 581 582 #define IS_ETH_FP(fp) (fp->index < \ 583 BNX2X_NUM_ETH_QUEUES(fp->bp)) 584 #ifdef BCM_CNIC 585 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX) 586 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX) 587 #else 588 #define IS_FCOE_FP(fp) false 589 #define IS_FCOE_IDX(idx) false 590 #endif 591 592 593 /* MC hsi */ 594 #define MAX_FETCH_BD 13 /* HW max BDs per packet */ 595 #define RX_COPY_THRESH 92 596 597 #define NUM_TX_RINGS 16 598 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 599 #define NEXT_PAGE_TX_DESC_CNT 1 600 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 601 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 602 #define MAX_TX_BD (NUM_TX_BD - 1) 603 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 604 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 605 (MAX_TX_DESC_CNT - 1)) ? \ 606 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 607 (x) + 1) 608 #define TX_BD(x) ((x) & MAX_TX_BD) 609 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 610 611 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 612 #define NUM_RX_RINGS 8 613 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 614 #define NEXT_PAGE_RX_DESC_CNT 2 615 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 616 #define RX_DESC_MASK (RX_DESC_CNT - 1) 617 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 618 #define MAX_RX_BD (NUM_RX_BD - 1) 619 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 620 621 /* dropless fc calculations for BDs 622 * 623 * Number of BDs should as number of buffers in BRB: 624 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 625 * "next" elements on each page 626 */ 627 #define NUM_BD_REQ BRB_SIZE(bp) 628 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 629 MAX_RX_DESC_CNT) 630 #define BD_TH_LO(bp) (NUM_BD_REQ + \ 631 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 632 FW_DROP_LEVEL(bp)) 633 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 634 635 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 636 637 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 638 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 639 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 640 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 641 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 642 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 643 MIN_RX_AVAIL)) 644 645 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 646 (MAX_RX_DESC_CNT - 1)) ? \ 647 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 648 (x) + 1) 649 #define RX_BD(x) ((x) & MAX_RX_BD) 650 651 /* 652 * As long as CQE is X times bigger than BD entry we have to allocate X times 653 * more pages for CQ ring in order to keep it balanced with BD ring 654 */ 655 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 656 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 657 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 658 #define NEXT_PAGE_RCQ_DESC_CNT 1 659 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 660 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 661 #define MAX_RCQ_BD (NUM_RCQ_BD - 1) 662 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 663 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 664 (MAX_RCQ_DESC_CNT - 1)) ? \ 665 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 666 (x) + 1) 667 #define RCQ_BD(x) ((x) & MAX_RCQ_BD) 668 669 /* dropless fc calculations for RCQs 670 * 671 * Number of RCQs should be as number of buffers in BRB: 672 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 673 * "next" elements on each page 674 */ 675 #define NUM_RCQ_REQ BRB_SIZE(bp) 676 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 677 MAX_RCQ_DESC_CNT) 678 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 679 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 680 FW_DROP_LEVEL(bp)) 681 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 682 683 684 /* This is needed for determining of last_max */ 685 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 686 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 687 688 689 #define BNX2X_SWCID_SHIFT 17 690 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 691 692 /* used on a CID received from the HW */ 693 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 694 #define CQE_CMD(x) (le32_to_cpu(x) >> \ 695 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 696 697 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 698 le32_to_cpu((bd)->addr_lo)) 699 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 700 701 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 702 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/ 703 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 704 #error "Min DB doorbell stride is 8" 705 #endif 706 #define DPM_TRIGER_TYPE 0x40 707 #define DOORBELL(bp, cid, val) \ 708 do { \ 709 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ 710 DPM_TRIGER_TYPE); \ 711 } while (0) 712 713 714 /* TX CSUM helpers */ 715 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 716 skb->csum_offset) 717 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 718 skb->csum_offset)) 719 720 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) 721 722 #define XMIT_PLAIN 0 723 #define XMIT_CSUM_V4 0x1 724 #define XMIT_CSUM_V6 0x2 725 #define XMIT_CSUM_TCP 0x4 726 #define XMIT_GSO_V4 0x8 727 #define XMIT_GSO_V6 0x10 728 729 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) 730 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) 731 732 733 /* stuff added to make the code fit 80Col */ 734 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 735 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 736 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 737 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 738 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 739 740 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 741 742 #define BNX2X_IP_CSUM_ERR(cqe) \ 743 (!((cqe)->fast_path_cqe.status_flags & \ 744 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ 745 ((cqe)->fast_path_cqe.type_error_flags & \ 746 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) 747 748 #define BNX2X_L4_CSUM_ERR(cqe) \ 749 (!((cqe)->fast_path_cqe.status_flags & \ 750 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ 751 ((cqe)->fast_path_cqe.type_error_flags & \ 752 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) 753 754 #define BNX2X_RX_CSUM_OK(cqe) \ 755 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) 756 757 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 758 (((le16_to_cpu(flags) & \ 759 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 760 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 761 == PRS_FLAG_OVERETH_IPV4) 762 #define BNX2X_RX_SUM_FIX(cqe) \ 763 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 764 765 766 #define FP_USB_FUNC_OFF \ 767 offsetof(struct cstorm_status_block_u, func) 768 #define FP_CSB_FUNC_OFF \ 769 offsetof(struct cstorm_status_block_c, func) 770 771 #define HC_INDEX_ETH_RX_CQ_CONS 1 772 773 #define HC_INDEX_OOO_TX_CQ_CONS 4 774 775 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 776 777 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 778 779 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 780 781 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 782 783 #define BNX2X_RX_SB_INDEX \ 784 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 785 786 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 787 788 #define BNX2X_TX_SB_INDEX_COS0 \ 789 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 790 791 /* end of fast path */ 792 793 /* common */ 794 795 struct bnx2x_common { 796 797 u32 chip_id; 798 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 799 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 800 801 #define CHIP_NUM(bp) (bp->common.chip_id >> 16) 802 #define CHIP_NUM_57710 0x164e 803 #define CHIP_NUM_57711 0x164f 804 #define CHIP_NUM_57711E 0x1650 805 #define CHIP_NUM_57712 0x1662 806 #define CHIP_NUM_57712_MF 0x1663 807 #define CHIP_NUM_57713 0x1651 808 #define CHIP_NUM_57713E 0x1652 809 #define CHIP_NUM_57800 0x168a 810 #define CHIP_NUM_57800_MF 0x16a5 811 #define CHIP_NUM_57810 0x168e 812 #define CHIP_NUM_57810_MF 0x16ae 813 #define CHIP_NUM_57840 0x168d 814 #define CHIP_NUM_57840_MF 0x16ab 815 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 816 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 817 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 818 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 819 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 820 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 821 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 822 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 823 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 824 #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840) 825 #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF) 826 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 827 CHIP_IS_57711E(bp)) 828 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 829 CHIP_IS_57712_MF(bp)) 830 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 831 CHIP_IS_57800_MF(bp) || \ 832 CHIP_IS_57810(bp) || \ 833 CHIP_IS_57810_MF(bp) || \ 834 CHIP_IS_57840(bp) || \ 835 CHIP_IS_57840_MF(bp)) 836 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 837 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 838 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 839 840 #define CHIP_REV_SHIFT 12 841 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 842 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 843 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 844 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 845 /* assume maximum 5 revisions */ 846 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 847 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 848 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 849 !(CHIP_REV_VAL(bp) & 0x00001000)) 850 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 851 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 852 (CHIP_REV_VAL(bp) & 0x00001000)) 853 854 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 855 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 856 857 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 858 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 859 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 860 (CHIP_REV_SHIFT + 1)) \ 861 << CHIP_REV_SHIFT) 862 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 863 CHIP_REV_SIM(bp) :\ 864 CHIP_REV_VAL(bp)) 865 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 866 (CHIP_REV(bp) == CHIP_REV_Bx)) 867 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 868 (CHIP_REV(bp) == CHIP_REV_Ax)) 869 870 int flash_size; 871 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 872 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 873 #define BNX2X_NVRAM_PAGE_SIZE 256 874 875 u32 shmem_base; 876 u32 shmem2_base; 877 u32 mf_cfg_base; 878 u32 mf2_cfg_base; 879 880 u32 hw_config; 881 882 u32 bc_ver; 883 884 u8 int_block; 885 #define INT_BLOCK_HC 0 886 #define INT_BLOCK_IGU 1 887 #define INT_BLOCK_MODE_NORMAL 0 888 #define INT_BLOCK_MODE_BW_COMP 2 889 #define CHIP_INT_MODE_IS_NBC(bp) \ 890 (!CHIP_IS_E1x(bp) && \ 891 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 892 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 893 894 u8 chip_port_mode; 895 #define CHIP_4_PORT_MODE 0x0 896 #define CHIP_2_PORT_MODE 0x1 897 #define CHIP_PORT_MODE_NONE 0x2 898 #define CHIP_MODE(bp) (bp->common.chip_port_mode) 899 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 900 901 u32 boot_mode; 902 }; 903 904 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 905 #define BNX2X_IGU_STAS_MSG_VF_CNT 64 906 #define BNX2X_IGU_STAS_MSG_PF_CNT 4 907 908 /* end of common */ 909 910 /* port */ 911 912 struct bnx2x_port { 913 u32 pmf; 914 915 u32 link_config[LINK_CONFIG_SIZE]; 916 917 u32 supported[LINK_CONFIG_SIZE]; 918 /* link settings - missing defines */ 919 #define SUPPORTED_2500baseX_Full (1 << 15) 920 921 u32 advertising[LINK_CONFIG_SIZE]; 922 /* link settings - missing defines */ 923 #define ADVERTISED_2500baseX_Full (1 << 15) 924 925 u32 phy_addr; 926 927 /* used to synchronize phy accesses */ 928 struct mutex phy_mutex; 929 int need_hw_lock; 930 931 u32 port_stx; 932 933 struct nig_stats old_nig_stats; 934 }; 935 936 /* end of port */ 937 938 #define STATS_OFFSET32(stat_name) \ 939 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 940 941 /* slow path */ 942 943 /* slow path work-queue */ 944 extern struct workqueue_struct *bnx2x_wq; 945 946 #define BNX2X_MAX_NUM_OF_VFS 64 947 #define BNX2X_VF_ID_INVALID 0xFF 948 949 /* 950 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 951 * control by the number of fast-path status blocks supported by the 952 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 953 * status block represents an independent interrupts context that can 954 * serve a regular L2 networking queue. However special L2 queues such 955 * as the FCoE queue do not require a FP-SB and other components like 956 * the CNIC may consume FP-SB reducing the number of possible L2 queues 957 * 958 * If the maximum number of FP-SB available is X then: 959 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 960 * regular L2 queues is Y=X-1 961 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 962 * c. If the FCoE L2 queue is supported the actual number of L2 queues 963 * is Y+1 964 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 965 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 966 * FP interrupt context for the CNIC). 967 * e. The number of HW context (CID count) is always X or X+1 if FCoE 968 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 969 */ 970 971 /* fast-path interrupt contexts E1x */ 972 #define FP_SB_MAX_E1x 16 973 /* fast-path interrupt contexts E2 */ 974 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 975 976 union cdu_context { 977 struct eth_context eth; 978 char pad[1024]; 979 }; 980 981 /* CDU host DB constants */ 982 #define CDU_ILT_PAGE_SZ_HW 3 983 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */ 984 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 985 986 #ifdef BCM_CNIC 987 #define CNIC_ISCSI_CID_MAX 256 988 #define CNIC_FCOE_CID_MAX 2048 989 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 990 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 991 #endif 992 993 #define QM_ILT_PAGE_SZ_HW 0 994 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 995 #define QM_CID_ROUND 1024 996 997 #ifdef BCM_CNIC 998 /* TM (timers) host DB constants */ 999 #define TM_ILT_PAGE_SZ_HW 0 1000 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1001 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 1002 #define TM_CONN_NUM 1024 1003 #define TM_ILT_SZ (8 * TM_CONN_NUM) 1004 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1005 1006 /* SRC (Searcher) host DB constants */ 1007 #define SRC_ILT_PAGE_SZ_HW 0 1008 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1009 #define SRC_HASH_BITS 10 1010 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1011 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1012 #define SRC_T2_SZ SRC_ILT_SZ 1013 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1014 1015 #endif 1016 1017 #define MAX_DMAE_C 8 1018 1019 /* DMA memory not used in fastpath */ 1020 struct bnx2x_slowpath { 1021 union { 1022 struct mac_configuration_cmd e1x; 1023 struct eth_classify_rules_ramrod_data e2; 1024 } mac_rdata; 1025 1026 1027 union { 1028 struct tstorm_eth_mac_filter_config e1x; 1029 struct eth_filter_rules_ramrod_data e2; 1030 } rx_mode_rdata; 1031 1032 union { 1033 struct mac_configuration_cmd e1; 1034 struct eth_multicast_rules_ramrod_data e2; 1035 } mcast_rdata; 1036 1037 struct eth_rss_update_ramrod_data rss_rdata; 1038 1039 /* Queue State related ramrods are always sent under rtnl_lock */ 1040 union { 1041 struct client_init_ramrod_data init_data; 1042 struct client_update_ramrod_data update_data; 1043 } q_rdata; 1044 1045 union { 1046 struct function_start_data func_start; 1047 /* pfc configuration for DCBX ramrod */ 1048 struct flow_control_configuration pfc_config; 1049 } func_rdata; 1050 1051 /* used by dmae command executer */ 1052 struct dmae_command dmae[MAX_DMAE_C]; 1053 1054 u32 stats_comp; 1055 union mac_stats mac_stats; 1056 struct nig_stats nig_stats; 1057 struct host_port_stats port_stats; 1058 struct host_func_stats func_stats; 1059 1060 u32 wb_comp; 1061 u32 wb_data[4]; 1062 1063 union drv_info_to_mcp drv_info_to_mcp; 1064 }; 1065 1066 #define bnx2x_sp(bp, var) (&bp->slowpath->var) 1067 #define bnx2x_sp_mapping(bp, var) \ 1068 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1069 1070 1071 /* attn group wiring */ 1072 #define MAX_DYNAMIC_ATTN_GRPS 8 1073 1074 struct attn_route { 1075 u32 sig[5]; 1076 }; 1077 1078 struct iro { 1079 u32 base; 1080 u16 m1; 1081 u16 m2; 1082 u16 m3; 1083 u16 size; 1084 }; 1085 1086 struct hw_context { 1087 union cdu_context *vcxt; 1088 dma_addr_t cxt_mapping; 1089 size_t size; 1090 }; 1091 1092 /* forward */ 1093 struct bnx2x_ilt; 1094 1095 1096 enum bnx2x_recovery_state { 1097 BNX2X_RECOVERY_DONE, 1098 BNX2X_RECOVERY_INIT, 1099 BNX2X_RECOVERY_WAIT, 1100 BNX2X_RECOVERY_FAILED, 1101 BNX2X_RECOVERY_NIC_LOADING 1102 }; 1103 1104 /* 1105 * Event queue (EQ or event ring) MC hsi 1106 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1107 */ 1108 #define NUM_EQ_PAGES 1 1109 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1110 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1111 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1112 #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1113 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1114 1115 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1116 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1117 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1118 1119 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1120 #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1121 1122 #define BNX2X_EQ_INDEX \ 1123 (&bp->def_status_blk->sp_sb.\ 1124 index_values[HC_SP_INDEX_EQ_CONS]) 1125 1126 /* This is a data that will be used to create a link report message. 1127 * We will keep the data used for the last link report in order 1128 * to prevent reporting the same link parameters twice. 1129 */ 1130 struct bnx2x_link_report_data { 1131 u16 line_speed; /* Effective line speed */ 1132 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1133 }; 1134 1135 enum { 1136 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1137 BNX2X_LINK_REPORT_LINK_DOWN, 1138 BNX2X_LINK_REPORT_RX_FC_ON, 1139 BNX2X_LINK_REPORT_TX_FC_ON, 1140 }; 1141 1142 enum { 1143 BNX2X_PORT_QUERY_IDX, 1144 BNX2X_PF_QUERY_IDX, 1145 BNX2X_FCOE_QUERY_IDX, 1146 BNX2X_FIRST_QUEUE_QUERY_IDX, 1147 }; 1148 1149 struct bnx2x_fw_stats_req { 1150 struct stats_query_header hdr; 1151 struct stats_query_entry query[FP_SB_MAX_E1x+ 1152 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1153 }; 1154 1155 struct bnx2x_fw_stats_data { 1156 struct stats_counter storm_counters; 1157 struct per_port_stats port; 1158 struct per_pf_stats pf; 1159 struct fcoe_statistics_params fcoe; 1160 struct per_queue_stats queue_stats[1]; 1161 }; 1162 1163 /* Public slow path states */ 1164 enum { 1165 BNX2X_SP_RTNL_SETUP_TC, 1166 BNX2X_SP_RTNL_TX_TIMEOUT, 1167 BNX2X_SP_RTNL_FAN_FAILURE, 1168 }; 1169 1170 1171 struct bnx2x { 1172 /* Fields used in the tx and intr/napi performance paths 1173 * are grouped together in the beginning of the structure 1174 */ 1175 struct bnx2x_fastpath *fp; 1176 void __iomem *regview; 1177 void __iomem *doorbells; 1178 u16 db_size; 1179 1180 u8 pf_num; /* absolute PF number */ 1181 u8 pfid; /* per-path PF number */ 1182 int base_fw_ndsb; /**/ 1183 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1184 #define BP_PORT(bp) (bp->pfid & 1) 1185 #define BP_FUNC(bp) (bp->pfid) 1186 #define BP_ABS_FUNC(bp) (bp->pf_num) 1187 #define BP_VN(bp) ((bp)->pfid >> 1) 1188 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1189 #define BP_L_ID(bp) (BP_VN(bp) << 2) 1190 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1191 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1192 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1193 1194 struct net_device *dev; 1195 struct pci_dev *pdev; 1196 1197 const struct iro *iro_arr; 1198 #define IRO (bp->iro_arr) 1199 1200 enum bnx2x_recovery_state recovery_state; 1201 int is_leader; 1202 struct msix_entry *msix_table; 1203 1204 int tx_ring_size; 1205 1206 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1207 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1208 #define ETH_MIN_PACKET_SIZE 60 1209 #define ETH_MAX_PACKET_SIZE 1500 1210 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 1211 /* TCP with Timestamp Option (32) + IPv6 (40) */ 1212 #define ETH_MAX_TPA_HEADER_SIZE 72 1213 1214 /* Max supported alignment is 256 (8 shift) */ 1215 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1216 1217 /* FW uses 2 Cache lines Alignment for start packet and size 1218 * 1219 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1220 * at the end of skb->data, to avoid wasting a full cache line. 1221 * This reduces memory use (skb->truesize). 1222 */ 1223 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1224 1225 #define BNX2X_FW_RX_ALIGN_END \ 1226 max(1UL << BNX2X_RX_ALIGN_SHIFT, \ 1227 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1228 1229 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1230 1231 struct host_sp_status_block *def_status_blk; 1232 #define DEF_SB_IGU_ID 16 1233 #define DEF_SB_ID HC_SP_SB_ID 1234 __le16 def_idx; 1235 __le16 def_att_idx; 1236 u32 attn_state; 1237 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1238 1239 /* slow path ring */ 1240 struct eth_spe *spq; 1241 dma_addr_t spq_mapping; 1242 u16 spq_prod_idx; 1243 struct eth_spe *spq_prod_bd; 1244 struct eth_spe *spq_last_bd; 1245 __le16 *dsb_sp_prod; 1246 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1247 /* used to synchronize spq accesses */ 1248 spinlock_t spq_lock; 1249 1250 /* event queue */ 1251 union event_ring_elem *eq_ring; 1252 dma_addr_t eq_mapping; 1253 u16 eq_prod; 1254 u16 eq_cons; 1255 __le16 *eq_cons_sb; 1256 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1257 1258 1259 1260 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1261 u16 stats_pending; 1262 /* Counter for completed statistics ramrods */ 1263 u16 stats_comp; 1264 1265 /* End of fields used in the performance code paths */ 1266 1267 int panic; 1268 int msg_enable; 1269 1270 u32 flags; 1271 #define PCIX_FLAG (1 << 0) 1272 #define PCI_32BIT_FLAG (1 << 1) 1273 #define ONE_PORT_FLAG (1 << 2) 1274 #define NO_WOL_FLAG (1 << 3) 1275 #define USING_DAC_FLAG (1 << 4) 1276 #define USING_MSIX_FLAG (1 << 5) 1277 #define USING_MSI_FLAG (1 << 6) 1278 #define DISABLE_MSI_FLAG (1 << 7) 1279 #define TPA_ENABLE_FLAG (1 << 8) 1280 #define NO_MCP_FLAG (1 << 9) 1281 1282 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) 1283 #define GRO_ENABLE_FLAG (1 << 10) 1284 #define MF_FUNC_DIS (1 << 11) 1285 #define OWN_CNIC_IRQ (1 << 12) 1286 #define NO_ISCSI_OOO_FLAG (1 << 13) 1287 #define NO_ISCSI_FLAG (1 << 14) 1288 #define NO_FCOE_FLAG (1 << 15) 1289 #define BC_SUPPORTS_PFC_STATS (1 << 17) 1290 1291 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1292 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1293 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1294 1295 int pm_cap; 1296 int mrrs; 1297 1298 struct delayed_work sp_task; 1299 struct delayed_work sp_rtnl_task; 1300 1301 struct delayed_work period_task; 1302 struct timer_list timer; 1303 int current_interval; 1304 1305 u16 fw_seq; 1306 u16 fw_drv_pulse_wr_seq; 1307 u32 func_stx; 1308 1309 struct link_params link_params; 1310 struct link_vars link_vars; 1311 u32 link_cnt; 1312 struct bnx2x_link_report_data last_reported_link; 1313 1314 struct mdio_if_info mdio; 1315 1316 struct bnx2x_common common; 1317 struct bnx2x_port port; 1318 1319 struct cmng_struct_per_port cmng; 1320 u32 vn_weight_sum; 1321 u32 mf_config[E1HVN_MAX]; 1322 u32 mf2_config[E2_FUNC_MAX]; 1323 u32 path_has_ovlan; /* E3 */ 1324 u16 mf_ov; 1325 u8 mf_mode; 1326 #define IS_MF(bp) (bp->mf_mode != 0) 1327 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1328 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1329 1330 u8 wol; 1331 1332 int rx_ring_size; 1333 1334 u16 tx_quick_cons_trip_int; 1335 u16 tx_quick_cons_trip; 1336 u16 tx_ticks_int; 1337 u16 tx_ticks; 1338 1339 u16 rx_quick_cons_trip_int; 1340 u16 rx_quick_cons_trip; 1341 u16 rx_ticks_int; 1342 u16 rx_ticks; 1343 /* Maximal coalescing timeout in us */ 1344 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) 1345 1346 u32 lin_cnt; 1347 1348 u16 state; 1349 #define BNX2X_STATE_CLOSED 0 1350 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1351 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1352 #define BNX2X_STATE_OPEN 0x3000 1353 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1354 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1355 1356 #define BNX2X_STATE_DIAG 0xe000 1357 #define BNX2X_STATE_ERROR 0xf000 1358 1359 int multi_mode; 1360 #define BNX2X_MAX_PRIORITY 8 1361 #define BNX2X_MAX_ENTRIES_PER_PRI 16 1362 #define BNX2X_MAX_COS 3 1363 #define BNX2X_MAX_TX_COS 2 1364 int num_queues; 1365 int disable_tpa; 1366 1367 u32 rx_mode; 1368 #define BNX2X_RX_MODE_NONE 0 1369 #define BNX2X_RX_MODE_NORMAL 1 1370 #define BNX2X_RX_MODE_ALLMULTI 2 1371 #define BNX2X_RX_MODE_PROMISC 3 1372 #define BNX2X_MAX_MULTICAST 64 1373 1374 u8 igu_dsb_id; 1375 u8 igu_base_sb; 1376 u8 igu_sb_cnt; 1377 dma_addr_t def_status_blk_mapping; 1378 1379 struct bnx2x_slowpath *slowpath; 1380 dma_addr_t slowpath_mapping; 1381 1382 /* Total number of FW statistics requests */ 1383 u8 fw_stats_num; 1384 1385 /* 1386 * This is a memory buffer that will contain both statistics 1387 * ramrod request and data. 1388 */ 1389 void *fw_stats; 1390 dma_addr_t fw_stats_mapping; 1391 1392 /* 1393 * FW statistics request shortcut (points at the 1394 * beginning of fw_stats buffer). 1395 */ 1396 struct bnx2x_fw_stats_req *fw_stats_req; 1397 dma_addr_t fw_stats_req_mapping; 1398 int fw_stats_req_sz; 1399 1400 /* 1401 * FW statistics data shortcut (points at the begining of 1402 * fw_stats buffer + fw_stats_req_sz). 1403 */ 1404 struct bnx2x_fw_stats_data *fw_stats_data; 1405 dma_addr_t fw_stats_data_mapping; 1406 int fw_stats_data_sz; 1407 1408 struct hw_context context; 1409 1410 struct bnx2x_ilt *ilt; 1411 #define BP_ILT(bp) ((bp)->ilt) 1412 #define ILT_MAX_LINES 256 1413 /* 1414 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1415 * to CNIC. 1416 */ 1417 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT) 1418 1419 /* 1420 * Maximum CID count that might be required by the bnx2x: 1421 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related) 1422 */ 1423 #define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\ 1424 NON_ETH_CONTEXT_USE + CNIC_PRESENT) 1425 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1426 ILT_PAGE_CIDS)) 1427 #define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT)) 1428 1429 int qm_cid_count; 1430 1431 int dropless_fc; 1432 1433 #ifdef BCM_CNIC 1434 u32 cnic_flags; 1435 #define BNX2X_CNIC_FLAG_MAC_SET 1 1436 void *t2; 1437 dma_addr_t t2_mapping; 1438 struct cnic_ops __rcu *cnic_ops; 1439 void *cnic_data; 1440 u32 cnic_tag; 1441 struct cnic_eth_dev cnic_eth_dev; 1442 union host_hc_status_block cnic_sb; 1443 dma_addr_t cnic_sb_mapping; 1444 struct eth_spe *cnic_kwq; 1445 struct eth_spe *cnic_kwq_prod; 1446 struct eth_spe *cnic_kwq_cons; 1447 struct eth_spe *cnic_kwq_last; 1448 u16 cnic_kwq_pending; 1449 u16 cnic_spq_pending; 1450 u8 fip_mac[ETH_ALEN]; 1451 struct mutex cnic_mutex; 1452 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1453 1454 /* Start index of the "special" (CNIC related) L2 cleints */ 1455 u8 cnic_base_cl_id; 1456 #endif 1457 1458 int dmae_ready; 1459 /* used to synchronize dmae accesses */ 1460 spinlock_t dmae_lock; 1461 1462 /* used to protect the FW mail box */ 1463 struct mutex fw_mb_mutex; 1464 1465 /* used to synchronize stats collecting */ 1466 int stats_state; 1467 1468 /* used for synchronization of concurrent threads statistics handling */ 1469 spinlock_t stats_lock; 1470 1471 /* used by dmae command loader */ 1472 struct dmae_command stats_dmae; 1473 int executer_idx; 1474 1475 u16 stats_counter; 1476 struct bnx2x_eth_stats eth_stats; 1477 struct bnx2x_eth_stats_old eth_stats_old; 1478 struct bnx2x_net_stats_old net_stats_old; 1479 struct bnx2x_fw_port_stats_old fw_stats_old; 1480 bool stats_init; 1481 1482 struct z_stream_s *strm; 1483 void *gunzip_buf; 1484 dma_addr_t gunzip_mapping; 1485 int gunzip_outlen; 1486 #define FW_BUF_SIZE 0x8000 1487 #define GUNZIP_BUF(bp) (bp->gunzip_buf) 1488 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1489 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1490 1491 struct raw_op *init_ops; 1492 /* Init blocks offsets inside init_ops */ 1493 u16 *init_ops_offsets; 1494 /* Data blob - has 32 bit granularity */ 1495 u32 *init_data; 1496 u32 init_mode_flags; 1497 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1498 /* Zipped PRAM blobs - raw data */ 1499 const u8 *tsem_int_table_data; 1500 const u8 *tsem_pram_data; 1501 const u8 *usem_int_table_data; 1502 const u8 *usem_pram_data; 1503 const u8 *xsem_int_table_data; 1504 const u8 *xsem_pram_data; 1505 const u8 *csem_int_table_data; 1506 const u8 *csem_pram_data; 1507 #define INIT_OPS(bp) (bp->init_ops) 1508 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1509 #define INIT_DATA(bp) (bp->init_data) 1510 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1511 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1512 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1513 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1514 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1515 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1516 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1517 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1518 1519 #define PHY_FW_VER_LEN 20 1520 char fw_ver[32]; 1521 const struct firmware *firmware; 1522 1523 /* DCB support on/off */ 1524 u16 dcb_state; 1525 #define BNX2X_DCB_STATE_OFF 0 1526 #define BNX2X_DCB_STATE_ON 1 1527 1528 /* DCBX engine mode */ 1529 int dcbx_enabled; 1530 #define BNX2X_DCBX_ENABLED_OFF 0 1531 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1532 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1533 #define BNX2X_DCBX_ENABLED_INVALID (-1) 1534 1535 bool dcbx_mode_uset; 1536 1537 struct bnx2x_config_dcbx_params dcbx_config_params; 1538 struct bnx2x_dcbx_port_params dcbx_port_params; 1539 int dcb_version; 1540 1541 /* CAM credit pools */ 1542 struct bnx2x_credit_pool_obj macs_pool; 1543 1544 /* RX_MODE object */ 1545 struct bnx2x_rx_mode_obj rx_mode_obj; 1546 1547 /* MCAST object */ 1548 struct bnx2x_mcast_obj mcast_obj; 1549 1550 /* RSS configuration object */ 1551 struct bnx2x_rss_config_obj rss_conf_obj; 1552 1553 /* Function State controlling object */ 1554 struct bnx2x_func_sp_obj func_obj; 1555 1556 unsigned long sp_state; 1557 1558 /* operation indication for the sp_rtnl task */ 1559 unsigned long sp_rtnl_state; 1560 1561 /* DCBX Negotation results */ 1562 struct dcbx_features dcbx_local_feat; 1563 u32 dcbx_error; 1564 1565 #ifdef BCM_DCBNL 1566 struct dcbx_features dcbx_remote_feat; 1567 u32 dcbx_remote_flags; 1568 #endif 1569 u32 pending_max; 1570 1571 /* multiple tx classes of service */ 1572 u8 max_cos; 1573 1574 /* priority to cos mapping */ 1575 u8 prio_to_cos[8]; 1576 }; 1577 1578 /* Tx queues may be less or equal to Rx queues */ 1579 extern int num_queues; 1580 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1581 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE) 1582 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1583 1584 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1585 1586 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1587 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1588 1589 #define RSS_IPV4_CAP_MASK \ 1590 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1591 1592 #define RSS_IPV4_TCP_CAP_MASK \ 1593 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1594 1595 #define RSS_IPV6_CAP_MASK \ 1596 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1597 1598 #define RSS_IPV6_TCP_CAP_MASK \ 1599 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1600 1601 /* func init flags */ 1602 #define FUNC_FLG_RSS 0x0001 1603 #define FUNC_FLG_STATS 0x0002 1604 /* removed FUNC_FLG_UNMATCHED 0x0004 */ 1605 #define FUNC_FLG_TPA 0x0008 1606 #define FUNC_FLG_SPQ 0x0010 1607 #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1608 1609 1610 struct bnx2x_func_init_params { 1611 /* dma */ 1612 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1613 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1614 1615 u16 func_flgs; 1616 u16 func_id; /* abs fid */ 1617 u16 pf_id; 1618 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1619 }; 1620 1621 #define for_each_eth_queue(bp, var) \ 1622 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1623 1624 #define for_each_nondefault_eth_queue(bp, var) \ 1625 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1626 1627 #define for_each_queue(bp, var) \ 1628 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1629 if (skip_queue(bp, var)) \ 1630 continue; \ 1631 else 1632 1633 /* Skip forwarding FP */ 1634 #define for_each_rx_queue(bp, var) \ 1635 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1636 if (skip_rx_queue(bp, var)) \ 1637 continue; \ 1638 else 1639 1640 /* Skip OOO FP */ 1641 #define for_each_tx_queue(bp, var) \ 1642 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1643 if (skip_tx_queue(bp, var)) \ 1644 continue; \ 1645 else 1646 1647 #define for_each_nondefault_queue(bp, var) \ 1648 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1649 if (skip_queue(bp, var)) \ 1650 continue; \ 1651 else 1652 1653 #define for_each_cos_in_tx_queue(fp, var) \ 1654 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1655 1656 /* skip rx queue 1657 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1658 */ 1659 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1660 1661 /* skip tx queue 1662 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1663 */ 1664 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1665 1666 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1667 1668 1669 1670 1671 /** 1672 * bnx2x_set_mac_one - configure a single MAC address 1673 * 1674 * @bp: driver handle 1675 * @mac: MAC to configure 1676 * @obj: MAC object handle 1677 * @set: if 'true' add a new MAC, otherwise - delete 1678 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1679 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1680 * 1681 * Configures one MAC according to provided parameters or continues the 1682 * execution of previously scheduled commands if RAMROD_CONT is set in 1683 * ramrod_flags. 1684 * 1685 * Returns zero if operation has successfully completed, a positive value if the 1686 * operation has been successfully scheduled and a negative - if a requested 1687 * operations has failed. 1688 */ 1689 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1690 struct bnx2x_vlan_mac_obj *obj, bool set, 1691 int mac_type, unsigned long *ramrod_flags); 1692 /** 1693 * Deletes all MACs configured for the specific MAC object. 1694 * 1695 * @param bp Function driver instance 1696 * @param mac_obj MAC object to cleanup 1697 * 1698 * @return zero if all MACs were cleaned 1699 */ 1700 1701 /** 1702 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1703 * 1704 * @bp: driver handle 1705 * @mac_obj: MAC object handle 1706 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 1707 * @wait_for_comp: if 'true' block until completion 1708 * 1709 * Deletes all MACs of the specific type (e.g. ETH, UC list). 1710 * 1711 * Returns zero if operation has successfully completed, a positive value if the 1712 * operation has been successfully scheduled and a negative - if a requested 1713 * operations has failed. 1714 */ 1715 int bnx2x_del_all_macs(struct bnx2x *bp, 1716 struct bnx2x_vlan_mac_obj *mac_obj, 1717 int mac_type, bool wait_for_comp); 1718 1719 /* Init Function API */ 1720 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 1721 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 1722 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1723 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 1724 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1725 void bnx2x_read_mf_cfg(struct bnx2x *bp); 1726 1727 1728 /* dmae */ 1729 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 1730 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 1731 u32 len32); 1732 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 1733 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 1734 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 1735 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 1736 bool with_comp, u8 comp_type); 1737 1738 1739 void bnx2x_calc_fc_adv(struct bnx2x *bp); 1740 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 1741 u32 data_hi, u32 data_lo, int cmd_type); 1742 void bnx2x_update_coalesce(struct bnx2x *bp); 1743 int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 1744 1745 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 1746 int wait) 1747 { 1748 u32 val; 1749 1750 do { 1751 val = REG_RD(bp, reg); 1752 if (val == expected) 1753 break; 1754 ms -= wait; 1755 msleep(wait); 1756 1757 } while (ms > 0); 1758 1759 return val; 1760 } 1761 1762 #define BNX2X_ILT_ZALLOC(x, y, size) \ 1763 do { \ 1764 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 1765 if (x) \ 1766 memset(x, 0, size); \ 1767 } while (0) 1768 1769 #define BNX2X_ILT_FREE(x, y, size) \ 1770 do { \ 1771 if (x) { \ 1772 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 1773 x = NULL; \ 1774 y = 0; \ 1775 } \ 1776 } while (0) 1777 1778 #define ILOG2(x) (ilog2((x))) 1779 1780 #define ILT_NUM_PAGE_ENTRIES (3072) 1781 /* In 57710/11 we use whole table since we have 8 func 1782 * In 57712 we have only 4 func, but use same size per func, then only half of 1783 * the table in use 1784 */ 1785 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 1786 1787 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 1788 /* 1789 * the phys address is shifted right 12 bits and has an added 1790 * 1=valid bit added to the 53rd bit 1791 * then since this is a wide register(TM) 1792 * we split it into two 32 bit writes 1793 */ 1794 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 1795 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 1796 1797 /* load/unload mode */ 1798 #define LOAD_NORMAL 0 1799 #define LOAD_OPEN 1 1800 #define LOAD_DIAG 2 1801 #define UNLOAD_NORMAL 0 1802 #define UNLOAD_CLOSE 1 1803 #define UNLOAD_RECOVERY 2 1804 1805 1806 /* DMAE command defines */ 1807 #define DMAE_TIMEOUT -1 1808 #define DMAE_PCI_ERROR -2 /* E2 and onward */ 1809 #define DMAE_NOT_RDY -3 1810 #define DMAE_PCI_ERR_FLAG 0x80000000 1811 1812 #define DMAE_SRC_PCI 0 1813 #define DMAE_SRC_GRC 1 1814 1815 #define DMAE_DST_NONE 0 1816 #define DMAE_DST_PCI 1 1817 #define DMAE_DST_GRC 2 1818 1819 #define DMAE_COMP_PCI 0 1820 #define DMAE_COMP_GRC 1 1821 1822 /* E2 and onward - PCI error handling in the completion */ 1823 1824 #define DMAE_COMP_REGULAR 0 1825 #define DMAE_COM_SET_ERR 1 1826 1827 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 1828 DMAE_COMMAND_SRC_SHIFT) 1829 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 1830 DMAE_COMMAND_SRC_SHIFT) 1831 1832 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 1833 DMAE_COMMAND_DST_SHIFT) 1834 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 1835 DMAE_COMMAND_DST_SHIFT) 1836 1837 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 1838 DMAE_COMMAND_C_DST_SHIFT) 1839 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 1840 DMAE_COMMAND_C_DST_SHIFT) 1841 1842 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 1843 1844 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 1845 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 1846 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 1847 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 1848 1849 #define DMAE_CMD_PORT_0 0 1850 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 1851 1852 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 1853 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 1854 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 1855 1856 #define DMAE_SRC_PF 0 1857 #define DMAE_SRC_VF 1 1858 1859 #define DMAE_DST_PF 0 1860 #define DMAE_DST_VF 1 1861 1862 #define DMAE_C_SRC 0 1863 #define DMAE_C_DST 1 1864 1865 #define DMAE_LEN32_RD_MAX 0x80 1866 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 1867 1868 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 1869 indicates eror */ 1870 1871 #define MAX_DMAE_C_PER_PORT 8 1872 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1873 BP_VN(bp)) 1874 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1875 E1HVN_MAX) 1876 1877 /* PCIE link and speed */ 1878 #define PCICFG_LINK_WIDTH 0x1f00000 1879 #define PCICFG_LINK_WIDTH_SHIFT 20 1880 #define PCICFG_LINK_SPEED 0xf0000 1881 #define PCICFG_LINK_SPEED_SHIFT 16 1882 1883 1884 #define BNX2X_NUM_TESTS 7 1885 1886 #define BNX2X_PHY_LOOPBACK 0 1887 #define BNX2X_MAC_LOOPBACK 1 1888 #define BNX2X_PHY_LOOPBACK_FAILED 1 1889 #define BNX2X_MAC_LOOPBACK_FAILED 2 1890 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 1891 BNX2X_PHY_LOOPBACK_FAILED) 1892 1893 1894 #define STROM_ASSERT_ARRAY_SIZE 50 1895 1896 1897 /* must be used on a CID before placing it on a HW ring */ 1898 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 1899 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 1900 (x)) 1901 1902 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1903 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1904 1905 1906 #define BNX2X_BTR 4 1907 #define MAX_SPQ_PENDING 8 1908 1909 /* CMNG constants, as derived from system spec calculations */ 1910 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 1911 #define DEF_MIN_RATE 100 1912 /* resolution of the rate shaping timer - 400 usec */ 1913 #define RS_PERIODIC_TIMEOUT_USEC 400 1914 /* number of bytes in single QM arbitration cycle - 1915 * coefficient for calculating the fairness timer */ 1916 #define QM_ARB_BYTES 160000 1917 /* resolution of Min algorithm 1:100 */ 1918 #define MIN_RES 100 1919 /* how many bytes above threshold for the minimal credit of Min algorithm*/ 1920 #define MIN_ABOVE_THRESH 32768 1921 /* Fairness algorithm integration time coefficient - 1922 * for calculating the actual Tfair */ 1923 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 1924 /* Memory of fairness algorithm . 2 cycles */ 1925 #define FAIR_MEM 2 1926 1927 1928 #define ATTN_NIG_FOR_FUNC (1L << 8) 1929 #define ATTN_SW_TIMER_4_FUNC (1L << 9) 1930 #define GPIO_2_FUNC (1L << 10) 1931 #define GPIO_3_FUNC (1L << 11) 1932 #define GPIO_4_FUNC (1L << 12) 1933 #define ATTN_GENERAL_ATTN_1 (1L << 13) 1934 #define ATTN_GENERAL_ATTN_2 (1L << 14) 1935 #define ATTN_GENERAL_ATTN_3 (1L << 15) 1936 #define ATTN_GENERAL_ATTN_4 (1L << 13) 1937 #define ATTN_GENERAL_ATTN_5 (1L << 14) 1938 #define ATTN_GENERAL_ATTN_6 (1L << 15) 1939 1940 #define ATTN_HARD_WIRED_MASK 0xff00 1941 #define ATTENTION_ID 4 1942 1943 1944 /* stuff added to make the code fit 80Col */ 1945 1946 #define BNX2X_PMF_LINK_ASSERT \ 1947 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 1948 1949 #define BNX2X_MC_ASSERT_BITS \ 1950 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1951 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1952 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1953 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 1954 1955 #define BNX2X_MCP_ASSERT \ 1956 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 1957 1958 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 1959 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 1960 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 1961 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 1962 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 1963 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 1964 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 1965 1966 #define HW_INTERRUT_ASSERT_SET_0 \ 1967 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 1968 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 1969 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 1970 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 1971 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 1972 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 1973 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 1974 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 1975 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 1976 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 1977 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 1978 #define HW_INTERRUT_ASSERT_SET_1 \ 1979 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 1980 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 1981 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 1982 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 1983 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 1984 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 1985 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 1986 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 1987 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 1988 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 1989 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 1990 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 1991 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 1992 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 1993 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 1994 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 1995 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 1996 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 1997 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 1998 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 1999 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2000 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2001 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2002 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2003 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2004 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2005 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2006 #define HW_INTERRUT_ASSERT_SET_2 \ 2007 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2008 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2009 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2010 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2011 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2012 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2013 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2014 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2015 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2016 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2017 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2018 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2019 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2020 2021 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2022 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2023 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2024 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2025 2026 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2027 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2028 2029 #define MULTI_MASK 0x7f 2030 2031 2032 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2033 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2034 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2035 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2036 2037 #define DEF_USB_IGU_INDEX_OFF \ 2038 offsetof(struct cstorm_def_status_block_u, igu_index) 2039 #define DEF_CSB_IGU_INDEX_OFF \ 2040 offsetof(struct cstorm_def_status_block_c, igu_index) 2041 #define DEF_XSB_IGU_INDEX_OFF \ 2042 offsetof(struct xstorm_def_status_block, igu_index) 2043 #define DEF_TSB_IGU_INDEX_OFF \ 2044 offsetof(struct tstorm_def_status_block, igu_index) 2045 2046 #define DEF_USB_SEGMENT_OFF \ 2047 offsetof(struct cstorm_def_status_block_u, segment) 2048 #define DEF_CSB_SEGMENT_OFF \ 2049 offsetof(struct cstorm_def_status_block_c, segment) 2050 #define DEF_XSB_SEGMENT_OFF \ 2051 offsetof(struct xstorm_def_status_block, segment) 2052 #define DEF_TSB_SEGMENT_OFF \ 2053 offsetof(struct tstorm_def_status_block, segment) 2054 2055 #define BNX2X_SP_DSB_INDEX \ 2056 (&bp->def_status_blk->sp_sb.\ 2057 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2058 2059 #define SET_FLAG(value, mask, flag) \ 2060 do {\ 2061 (value) &= ~(mask);\ 2062 (value) |= ((flag) << (mask##_SHIFT));\ 2063 } while (0) 2064 2065 #define GET_FLAG(value, mask) \ 2066 (((value) & (mask)) >> (mask##_SHIFT)) 2067 2068 #define GET_FIELD(value, fname) \ 2069 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2070 2071 #define CAM_IS_INVALID(x) \ 2072 (GET_FLAG(x.flags, \ 2073 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2074 (T_ETH_MAC_COMMAND_INVALIDATE)) 2075 2076 /* Number of u32 elements in MC hash array */ 2077 #define MC_HASH_SIZE 8 2078 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2079 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2080 2081 2082 #ifndef PXP2_REG_PXP2_INT_STS 2083 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2084 #endif 2085 2086 #ifndef ETH_MAX_RX_CLIENTS_E2 2087 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2088 #endif 2089 2090 #define BNX2X_VPD_LEN 128 2091 #define VENDOR_ID_LEN 4 2092 2093 /* Congestion management fairness mode */ 2094 #define CMNG_FNS_NONE 0 2095 #define CMNG_FNS_MINMAX 1 2096 2097 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2098 #define HC_SEG_ACCESS_ATTN 4 2099 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2100 2101 static const u32 dmae_reg_go_c[] = { 2102 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2103 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2104 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2105 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2106 }; 2107 2108 void bnx2x_set_ethtool_ops(struct net_device *netdev); 2109 void bnx2x_notify_link_changed(struct bnx2x *bp); 2110 2111 2112 #define BNX2X_MF_PROTOCOL(bp) \ 2113 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2114 2115 #ifdef BCM_CNIC 2116 #define BNX2X_IS_MF_PROTOCOL_ISCSI(bp) \ 2117 (BNX2X_MF_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2118 2119 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) 2120 #endif 2121 2122 #endif /* bnx2x.h */ 2123