1 /* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14 #ifndef BNX2X_H 15 #define BNX2X_H 16 17 #include <linux/pci.h> 18 #include <linux/netdevice.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/types.h> 21 #include <linux/pci_regs.h> 22 23 /* compilation time flags */ 24 25 /* define this to make the driver freeze on error to allow getting debug info 26 * (you will need to reboot afterwards) */ 27 /* #define BNX2X_STOP_ON_ERROR */ 28 29 #define DRV_MODULE_VERSION "1.78.17-0" 30 #define DRV_MODULE_RELDATE "2013/04/11" 31 #define BNX2X_BC_VER 0x040200 32 33 #if defined(CONFIG_DCB) 34 #define BCM_DCBNL 35 #endif 36 37 #include "bnx2x_hsi.h" 38 39 #include "../cnic_if.h" 40 41 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 42 43 #include <linux/mdio.h> 44 45 #include "bnx2x_reg.h" 46 #include "bnx2x_fw_defs.h" 47 #include "bnx2x_mfw_req.h" 48 #include "bnx2x_link.h" 49 #include "bnx2x_sp.h" 50 #include "bnx2x_dcb.h" 51 #include "bnx2x_stats.h" 52 #include "bnx2x_vfpf.h" 53 54 enum bnx2x_int_mode { 55 BNX2X_INT_MODE_MSIX, 56 BNX2X_INT_MODE_INTX, 57 BNX2X_INT_MODE_MSI 58 }; 59 60 /* error/debug prints */ 61 62 #define DRV_MODULE_NAME "bnx2x" 63 64 /* for messages that are currently off */ 65 #define BNX2X_MSG_OFF 0x0 66 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 67 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 68 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 69 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 70 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 71 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 72 #define BNX2X_MSG_IOV 0x0800000 73 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 74 #define BNX2X_MSG_ETHTOOL 0x4000000 75 #define BNX2X_MSG_DCB 0x8000000 76 77 /* regular debug print */ 78 #define DP(__mask, fmt, ...) \ 79 do { \ 80 if (unlikely(bp->msg_enable & (__mask))) \ 81 pr_notice("[%s:%d(%s)]" fmt, \ 82 __func__, __LINE__, \ 83 bp->dev ? (bp->dev->name) : "?", \ 84 ##__VA_ARGS__); \ 85 } while (0) 86 87 #define DP_CONT(__mask, fmt, ...) \ 88 do { \ 89 if (unlikely(bp->msg_enable & (__mask))) \ 90 pr_cont(fmt, ##__VA_ARGS__); \ 91 } while (0) 92 93 /* errors debug print */ 94 #define BNX2X_DBG_ERR(fmt, ...) \ 95 do { \ 96 if (unlikely(netif_msg_probe(bp))) \ 97 pr_err("[%s:%d(%s)]" fmt, \ 98 __func__, __LINE__, \ 99 bp->dev ? (bp->dev->name) : "?", \ 100 ##__VA_ARGS__); \ 101 } while (0) 102 103 /* for errors (never masked) */ 104 #define BNX2X_ERR(fmt, ...) \ 105 do { \ 106 pr_err("[%s:%d(%s)]" fmt, \ 107 __func__, __LINE__, \ 108 bp->dev ? (bp->dev->name) : "?", \ 109 ##__VA_ARGS__); \ 110 } while (0) 111 112 #define BNX2X_ERROR(fmt, ...) \ 113 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 114 115 /* before we have a dev->name use dev_info() */ 116 #define BNX2X_DEV_INFO(fmt, ...) \ 117 do { \ 118 if (unlikely(netif_msg_probe(bp))) \ 119 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 120 } while (0) 121 122 /* Error handling */ 123 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); 124 #ifdef BNX2X_STOP_ON_ERROR 125 #define bnx2x_panic() \ 126 do { \ 127 bp->panic = 1; \ 128 BNX2X_ERR("driver assert\n"); \ 129 bnx2x_panic_dump(bp, true); \ 130 } while (0) 131 #else 132 #define bnx2x_panic() \ 133 do { \ 134 bp->panic = 1; \ 135 BNX2X_ERR("driver assert\n"); \ 136 bnx2x_panic_dump(bp, false); \ 137 } while (0) 138 #endif 139 140 #define bnx2x_mc_addr(ha) ((ha)->addr) 141 #define bnx2x_uc_addr(ha) ((ha)->addr) 142 143 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 144 #define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 145 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 146 147 #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 148 149 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 150 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 151 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 152 153 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 154 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 155 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 156 157 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 158 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 159 160 #define REG_RD_DMAE(bp, offset, valp, len32) \ 161 do { \ 162 bnx2x_read_dmae(bp, offset, len32);\ 163 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 164 } while (0) 165 166 #define REG_WR_DMAE(bp, offset, valp, len32) \ 167 do { \ 168 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 169 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 170 offset, len32); \ 171 } while (0) 172 173 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 174 REG_WR_DMAE(bp, offset, valp, len32) 175 176 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 177 do { \ 178 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 179 bnx2x_write_big_buf_wb(bp, addr, len32); \ 180 } while (0) 181 182 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 183 offsetof(struct shmem_region, field)) 184 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 185 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 186 187 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 188 offsetof(struct shmem2_region, field)) 189 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 190 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 191 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 192 offsetof(struct mf_cfg, field)) 193 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 194 offsetof(struct mf2_cfg, field)) 195 196 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 197 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 198 MF_CFG_ADDR(bp, field), (val)) 199 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 200 201 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 202 (SHMEM2_RD((bp), size) > \ 203 offsetof(struct shmem2_region, field))) 204 205 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 206 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 207 208 /* SP SB indices */ 209 210 /* General SP events - stats query, cfc delete, etc */ 211 #define HC_SP_INDEX_ETH_DEF_CONS 3 212 213 /* EQ completions */ 214 #define HC_SP_INDEX_EQ_CONS 7 215 216 /* FCoE L2 connection completions */ 217 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 218 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 219 /* iSCSI L2 */ 220 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 221 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 222 223 /* Special clients parameters */ 224 225 /* SB indices */ 226 /* FCoE L2 */ 227 #define BNX2X_FCOE_L2_RX_INDEX \ 228 (&bp->def_status_blk->sp_sb.\ 229 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 230 231 #define BNX2X_FCOE_L2_TX_INDEX \ 232 (&bp->def_status_blk->sp_sb.\ 233 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 234 235 /** 236 * CIDs and CLIDs: 237 * CLIDs below is a CLID for func 0, then the CLID for other 238 * functions will be calculated by the formula: 239 * 240 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 241 * 242 */ 243 enum { 244 BNX2X_ISCSI_ETH_CL_ID_IDX, 245 BNX2X_FCOE_ETH_CL_ID_IDX, 246 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 247 }; 248 249 #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\ 250 (bp)->max_cos) 251 /* iSCSI L2 */ 252 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 253 /* FCoE L2 */ 254 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 255 256 #define CNIC_SUPPORT(bp) ((bp)->cnic_support) 257 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 258 #define CNIC_LOADED(bp) ((bp)->cnic_loaded) 259 #define FCOE_INIT(bp) ((bp)->fcoe_init) 260 261 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 262 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 263 264 #define SM_RX_ID 0 265 #define SM_TX_ID 1 266 267 /* defines for multiple tx priority indices */ 268 #define FIRST_TX_ONLY_COS_INDEX 1 269 #define FIRST_TX_COS_INDEX 0 270 271 /* rules for calculating the cids of tx-only connections */ 272 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 273 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 274 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 275 276 /* fp index inside class of service range */ 277 #define FP_COS_TO_TXQ(fp, cos, bp) \ 278 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 279 280 /* Indexes for transmission queues array: 281 * txdata for RSS i CoS j is at location i + (j * num of RSS) 282 * txdata for FCoE (if exist) is at location max cos * num of RSS 283 * txdata for FWD (if exist) is one location after FCoE 284 * txdata for OOO (if exist) is one location after FWD 285 */ 286 enum { 287 FCOE_TXQ_IDX_OFFSET, 288 FWD_TXQ_IDX_OFFSET, 289 OOO_TXQ_IDX_OFFSET, 290 }; 291 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 292 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 293 294 /* fast path */ 295 /* 296 * This driver uses new build_skb() API : 297 * RX ring buffer contains pointer to kmalloc() data only, 298 * skb are built only after Hardware filled the frame. 299 */ 300 struct sw_rx_bd { 301 u8 *data; 302 DEFINE_DMA_UNMAP_ADDR(mapping); 303 }; 304 305 struct sw_tx_bd { 306 struct sk_buff *skb; 307 u16 first_bd; 308 u8 flags; 309 /* Set on the first BD descriptor when there is a split BD */ 310 #define BNX2X_TSO_SPLIT_BD (1<<0) 311 }; 312 313 struct sw_rx_page { 314 struct page *page; 315 DEFINE_DMA_UNMAP_ADDR(mapping); 316 }; 317 318 union db_prod { 319 struct doorbell_set_prod data; 320 u32 raw; 321 }; 322 323 /* dropless fc FW/HW related params */ 324 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 325 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 326 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 327 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 328 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 329 #define FW_PREFETCH_CNT 16 330 #define DROPLESS_FC_HEADROOM 100 331 332 /* MC hsi */ 333 #define BCM_PAGE_SHIFT 12 334 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 335 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 336 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 337 338 #define PAGES_PER_SGE_SHIFT 0 339 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 340 #define SGE_PAGE_SIZE PAGE_SIZE 341 #define SGE_PAGE_SHIFT PAGE_SHIFT 342 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 343 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 344 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 345 SGE_PAGES), 0xffff) 346 347 /* SGE ring related macros */ 348 #define NUM_RX_SGE_PAGES 2 349 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 350 #define NEXT_PAGE_SGE_DESC_CNT 2 351 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 352 /* RX_SGE_CNT is promised to be a power of 2 */ 353 #define RX_SGE_MASK (RX_SGE_CNT - 1) 354 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 355 #define MAX_RX_SGE (NUM_RX_SGE - 1) 356 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 357 (MAX_RX_SGE_CNT - 1)) ? \ 358 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 359 (x) + 1) 360 #define RX_SGE(x) ((x) & MAX_RX_SGE) 361 362 /* 363 * Number of required SGEs is the sum of two: 364 * 1. Number of possible opened aggregations (next packet for 365 * these aggregations will probably consume SGE immediately) 366 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 367 * after placement on BD for new TPA aggregation) 368 * 369 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 370 */ 371 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 372 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 373 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 374 MAX_RX_SGE_CNT) 375 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 376 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 377 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 378 379 /* Manipulate a bit vector defined as an array of u64 */ 380 381 /* Number of bits in one sge_mask array element */ 382 #define BIT_VEC64_ELEM_SZ 64 383 #define BIT_VEC64_ELEM_SHIFT 6 384 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 385 386 #define __BIT_VEC64_SET_BIT(el, bit) \ 387 do { \ 388 el = ((el) | ((u64)0x1 << (bit))); \ 389 } while (0) 390 391 #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 392 do { \ 393 el = ((el) & (~((u64)0x1 << (bit)))); \ 394 } while (0) 395 396 #define BIT_VEC64_SET_BIT(vec64, idx) \ 397 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 398 (idx) & BIT_VEC64_ELEM_MASK) 399 400 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 401 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 402 (idx) & BIT_VEC64_ELEM_MASK) 403 404 #define BIT_VEC64_TEST_BIT(vec64, idx) \ 405 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 406 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 407 408 /* Creates a bitmask of all ones in less significant bits. 409 idx - index of the most significant bit in the created mask */ 410 #define BIT_VEC64_ONES_MASK(idx) \ 411 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 412 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 413 414 /*******************************************************/ 415 416 /* Number of u64 elements in SGE mask array */ 417 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 418 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 419 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 420 421 union host_hc_status_block { 422 /* pointer to fp status block e1x */ 423 struct host_hc_status_block_e1x *e1x_sb; 424 /* pointer to fp status block e2 */ 425 struct host_hc_status_block_e2 *e2_sb; 426 }; 427 428 struct bnx2x_agg_info { 429 /* 430 * First aggregation buffer is a data buffer, the following - are pages. 431 * We will preallocate the data buffer for each aggregation when 432 * we open the interface and will replace the BD at the consumer 433 * with this one when we receive the TPA_START CQE in order to 434 * keep the Rx BD ring consistent. 435 */ 436 struct sw_rx_bd first_buf; 437 u8 tpa_state; 438 #define BNX2X_TPA_START 1 439 #define BNX2X_TPA_STOP 2 440 #define BNX2X_TPA_ERROR 3 441 u8 placement_offset; 442 u16 parsing_flags; 443 u16 vlan_tag; 444 u16 len_on_bd; 445 u32 rxhash; 446 bool l4_rxhash; 447 u16 gro_size; 448 u16 full_page; 449 }; 450 451 #define Q_STATS_OFFSET32(stat_name) \ 452 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 453 454 struct bnx2x_fp_txdata { 455 456 struct sw_tx_bd *tx_buf_ring; 457 458 union eth_tx_bd_types *tx_desc_ring; 459 dma_addr_t tx_desc_mapping; 460 461 u32 cid; 462 463 union db_prod tx_db; 464 465 u16 tx_pkt_prod; 466 u16 tx_pkt_cons; 467 u16 tx_bd_prod; 468 u16 tx_bd_cons; 469 470 unsigned long tx_pkt; 471 472 __le16 *tx_cons_sb; 473 474 int txq_index; 475 struct bnx2x_fastpath *parent_fp; 476 int tx_ring_size; 477 }; 478 479 enum bnx2x_tpa_mode_t { 480 TPA_MODE_LRO, 481 TPA_MODE_GRO 482 }; 483 484 struct bnx2x_fastpath { 485 struct bnx2x *bp; /* parent */ 486 487 struct napi_struct napi; 488 489 #ifdef CONFIG_NET_RX_BUSY_POLL 490 unsigned int state; 491 #define BNX2X_FP_STATE_IDLE 0 492 #define BNX2X_FP_STATE_NAPI (1 << 0) /* NAPI owns this FP */ 493 #define BNX2X_FP_STATE_POLL (1 << 1) /* poll owns this FP */ 494 #define BNX2X_FP_STATE_NAPI_YIELD (1 << 2) /* NAPI yielded this FP */ 495 #define BNX2X_FP_STATE_POLL_YIELD (1 << 3) /* poll yielded this FP */ 496 #define BNX2X_FP_YIELD (BNX2X_FP_STATE_NAPI_YIELD | BNX2X_FP_STATE_POLL_YIELD) 497 #define BNX2X_FP_LOCKED (BNX2X_FP_STATE_NAPI | BNX2X_FP_STATE_POLL) 498 #define BNX2X_FP_USER_PEND (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_POLL_YIELD) 499 /* protect state */ 500 spinlock_t lock; 501 #endif /* CONFIG_NET_RX_BUSY_POLL */ 502 503 union host_hc_status_block status_blk; 504 /* chip independent shortcuts into sb structure */ 505 __le16 *sb_index_values; 506 __le16 *sb_running_index; 507 /* chip independent shortcut into rx_prods_offset memory */ 508 u32 ustorm_rx_prods_offset; 509 510 u32 rx_buf_size; 511 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 512 dma_addr_t status_blk_mapping; 513 514 enum bnx2x_tpa_mode_t mode; 515 516 u8 max_cos; /* actual number of active tx coses */ 517 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 518 519 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 520 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 521 522 struct eth_rx_bd *rx_desc_ring; 523 dma_addr_t rx_desc_mapping; 524 525 union eth_rx_cqe *rx_comp_ring; 526 dma_addr_t rx_comp_mapping; 527 528 /* SGE ring */ 529 struct eth_rx_sge *rx_sge_ring; 530 dma_addr_t rx_sge_mapping; 531 532 u64 sge_mask[RX_SGE_MASK_LEN]; 533 534 u32 cid; 535 536 __le16 fp_hc_idx; 537 538 u8 index; /* number in fp array */ 539 u8 rx_queue; /* index for skb_record */ 540 u8 cl_id; /* eth client id */ 541 u8 cl_qzone_id; 542 u8 fw_sb_id; /* status block number in FW */ 543 u8 igu_sb_id; /* status block number in HW */ 544 545 u16 rx_bd_prod; 546 u16 rx_bd_cons; 547 u16 rx_comp_prod; 548 u16 rx_comp_cons; 549 u16 rx_sge_prod; 550 /* The last maximal completed SGE */ 551 u16 last_max_sge; 552 __le16 *rx_cons_sb; 553 unsigned long rx_pkt, 554 rx_calls; 555 556 /* TPA related */ 557 struct bnx2x_agg_info *tpa_info; 558 u8 disable_tpa; 559 #ifdef BNX2X_STOP_ON_ERROR 560 u64 tpa_queue_used; 561 #endif 562 /* The size is calculated using the following: 563 sizeof name field from netdev structure + 564 4 ('-Xx-' string) + 565 4 (for the digits and to make it DWORD aligned) */ 566 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 567 char name[FP_NAME_SIZE]; 568 }; 569 570 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 571 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 572 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 573 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 574 575 #ifdef CONFIG_NET_RX_BUSY_POLL 576 static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp) 577 { 578 spin_lock_init(&fp->lock); 579 fp->state = BNX2X_FP_STATE_IDLE; 580 } 581 582 /* called from the device poll routine to get ownership of a FP */ 583 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 584 { 585 bool rc = true; 586 587 spin_lock(&fp->lock); 588 if (fp->state & BNX2X_FP_LOCKED) { 589 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI); 590 fp->state |= BNX2X_FP_STATE_NAPI_YIELD; 591 rc = false; 592 } else { 593 /* we don't care if someone yielded */ 594 fp->state = BNX2X_FP_STATE_NAPI; 595 } 596 spin_unlock(&fp->lock); 597 return rc; 598 } 599 600 /* returns true is someone tried to get the FP while napi had it */ 601 static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 602 { 603 bool rc = false; 604 605 spin_lock(&fp->lock); 606 WARN_ON(fp->state & 607 (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_NAPI_YIELD)); 608 609 if (fp->state & BNX2X_FP_STATE_POLL_YIELD) 610 rc = true; 611 fp->state = BNX2X_FP_STATE_IDLE; 612 spin_unlock(&fp->lock); 613 return rc; 614 } 615 616 /* called from bnx2x_low_latency_poll() */ 617 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 618 { 619 bool rc = true; 620 621 spin_lock_bh(&fp->lock); 622 if ((fp->state & BNX2X_FP_LOCKED)) { 623 fp->state |= BNX2X_FP_STATE_POLL_YIELD; 624 rc = false; 625 } else { 626 /* preserve yield marks */ 627 fp->state |= BNX2X_FP_STATE_POLL; 628 } 629 spin_unlock_bh(&fp->lock); 630 return rc; 631 } 632 633 /* returns true if someone tried to get the FP while it was locked */ 634 static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 635 { 636 bool rc = false; 637 638 spin_lock_bh(&fp->lock); 639 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI); 640 641 if (fp->state & BNX2X_FP_STATE_POLL_YIELD) 642 rc = true; 643 fp->state = BNX2X_FP_STATE_IDLE; 644 spin_unlock_bh(&fp->lock); 645 return rc; 646 } 647 648 /* true if a socket is polling, even if it did not get the lock */ 649 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 650 { 651 WARN_ON(!(fp->state & BNX2X_FP_LOCKED)); 652 return fp->state & BNX2X_FP_USER_PEND; 653 } 654 #else 655 static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp) 656 { 657 } 658 659 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 660 { 661 return true; 662 } 663 664 static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 665 { 666 return false; 667 } 668 669 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 670 { 671 return false; 672 } 673 674 static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 675 { 676 return false; 677 } 678 679 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 680 { 681 return false; 682 } 683 #endif /* CONFIG_NET_RX_BUSY_POLL */ 684 685 /* Use 2500 as a mini-jumbo MTU for FCoE */ 686 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 687 688 #define FCOE_IDX_OFFSET 0 689 690 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 691 FCOE_IDX_OFFSET) 692 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 693 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 694 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 695 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 696 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 697 txdata_ptr[FIRST_TX_COS_INDEX] \ 698 ->var) 699 700 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 701 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 702 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 703 704 /* MC hsi */ 705 #define MAX_FETCH_BD 13 /* HW max BDs per packet */ 706 #define RX_COPY_THRESH 92 707 708 #define NUM_TX_RINGS 16 709 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 710 #define NEXT_PAGE_TX_DESC_CNT 1 711 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 712 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 713 #define MAX_TX_BD (NUM_TX_BD - 1) 714 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 715 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 716 (MAX_TX_DESC_CNT - 1)) ? \ 717 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 718 (x) + 1) 719 #define TX_BD(x) ((x) & MAX_TX_BD) 720 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 721 722 /* number of NEXT_PAGE descriptors may be required during placement */ 723 #define NEXT_CNT_PER_TX_PKT(bds) \ 724 (((bds) + MAX_TX_DESC_CNT - 1) / \ 725 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 726 /* max BDs per tx packet w/o next_pages: 727 * START_BD - describes packed 728 * START_BD(splitted) - includes unpaged data segment for GSO 729 * PARSING_BD - for TSO and CSUM data 730 * PARSING_BD2 - for encapsulation data 731 * Frag BDs - describes pages for frags 732 */ 733 #define BDS_PER_TX_PKT 4 734 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 735 /* max BDs per tx packet including next pages */ 736 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 737 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 738 739 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 740 #define NUM_RX_RINGS 8 741 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 742 #define NEXT_PAGE_RX_DESC_CNT 2 743 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 744 #define RX_DESC_MASK (RX_DESC_CNT - 1) 745 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 746 #define MAX_RX_BD (NUM_RX_BD - 1) 747 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 748 749 /* dropless fc calculations for BDs 750 * 751 * Number of BDs should as number of buffers in BRB: 752 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 753 * "next" elements on each page 754 */ 755 #define NUM_BD_REQ BRB_SIZE(bp) 756 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 757 MAX_RX_DESC_CNT) 758 #define BD_TH_LO(bp) (NUM_BD_REQ + \ 759 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 760 FW_DROP_LEVEL(bp)) 761 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 762 763 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 764 765 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 766 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 767 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 768 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 769 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 770 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 771 MIN_RX_AVAIL)) 772 773 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 774 (MAX_RX_DESC_CNT - 1)) ? \ 775 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 776 (x) + 1) 777 #define RX_BD(x) ((x) & MAX_RX_BD) 778 779 /* 780 * As long as CQE is X times bigger than BD entry we have to allocate X times 781 * more pages for CQ ring in order to keep it balanced with BD ring 782 */ 783 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 784 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 785 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 786 #define NEXT_PAGE_RCQ_DESC_CNT 1 787 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 788 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 789 #define MAX_RCQ_BD (NUM_RCQ_BD - 1) 790 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 791 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 792 (MAX_RCQ_DESC_CNT - 1)) ? \ 793 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 794 (x) + 1) 795 #define RCQ_BD(x) ((x) & MAX_RCQ_BD) 796 797 /* dropless fc calculations for RCQs 798 * 799 * Number of RCQs should be as number of buffers in BRB: 800 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 801 * "next" elements on each page 802 */ 803 #define NUM_RCQ_REQ BRB_SIZE(bp) 804 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 805 MAX_RCQ_DESC_CNT) 806 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 807 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 808 FW_DROP_LEVEL(bp)) 809 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 810 811 /* This is needed for determining of last_max */ 812 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 813 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 814 815 #define BNX2X_SWCID_SHIFT 17 816 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 817 818 /* used on a CID received from the HW */ 819 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 820 #define CQE_CMD(x) (le32_to_cpu(x) >> \ 821 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 822 823 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 824 le32_to_cpu((bd)->addr_lo)) 825 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 826 827 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 828 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/ 829 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 830 #error "Min DB doorbell stride is 8" 831 #endif 832 #define DPM_TRIGER_TYPE 0x40 833 #define DOORBELL(bp, cid, val) \ 834 do { \ 835 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ 836 DPM_TRIGER_TYPE); \ 837 } while (0) 838 839 /* TX CSUM helpers */ 840 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 841 skb->csum_offset) 842 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 843 skb->csum_offset)) 844 845 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) 846 847 #define XMIT_PLAIN 0 848 #define XMIT_CSUM_V4 (1 << 0) 849 #define XMIT_CSUM_V6 (1 << 1) 850 #define XMIT_CSUM_TCP (1 << 2) 851 #define XMIT_GSO_V4 (1 << 3) 852 #define XMIT_GSO_V6 (1 << 4) 853 #define XMIT_CSUM_ENC_V4 (1 << 5) 854 #define XMIT_CSUM_ENC_V6 (1 << 6) 855 #define XMIT_GSO_ENC_V4 (1 << 7) 856 #define XMIT_GSO_ENC_V6 (1 << 8) 857 858 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) 859 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) 860 861 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) 862 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) 863 864 /* stuff added to make the code fit 80Col */ 865 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 866 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 867 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 868 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 869 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 870 871 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 872 873 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 874 (((le16_to_cpu(flags) & \ 875 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 876 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 877 == PRS_FLAG_OVERETH_IPV4) 878 #define BNX2X_RX_SUM_FIX(cqe) \ 879 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 880 881 #define FP_USB_FUNC_OFF \ 882 offsetof(struct cstorm_status_block_u, func) 883 #define FP_CSB_FUNC_OFF \ 884 offsetof(struct cstorm_status_block_c, func) 885 886 #define HC_INDEX_ETH_RX_CQ_CONS 1 887 888 #define HC_INDEX_OOO_TX_CQ_CONS 4 889 890 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 891 892 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 893 894 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 895 896 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 897 898 #define BNX2X_RX_SB_INDEX \ 899 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 900 901 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 902 903 #define BNX2X_TX_SB_INDEX_COS0 \ 904 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 905 906 /* end of fast path */ 907 908 /* common */ 909 910 struct bnx2x_common { 911 912 u32 chip_id; 913 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 914 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 915 916 #define CHIP_NUM(bp) (bp->common.chip_id >> 16) 917 #define CHIP_NUM_57710 0x164e 918 #define CHIP_NUM_57711 0x164f 919 #define CHIP_NUM_57711E 0x1650 920 #define CHIP_NUM_57712 0x1662 921 #define CHIP_NUM_57712_MF 0x1663 922 #define CHIP_NUM_57712_VF 0x166f 923 #define CHIP_NUM_57713 0x1651 924 #define CHIP_NUM_57713E 0x1652 925 #define CHIP_NUM_57800 0x168a 926 #define CHIP_NUM_57800_MF 0x16a5 927 #define CHIP_NUM_57800_VF 0x16a9 928 #define CHIP_NUM_57810 0x168e 929 #define CHIP_NUM_57810_MF 0x16ae 930 #define CHIP_NUM_57810_VF 0x16af 931 #define CHIP_NUM_57811 0x163d 932 #define CHIP_NUM_57811_MF 0x163e 933 #define CHIP_NUM_57811_VF 0x163f 934 #define CHIP_NUM_57840_OBSOLETE 0x168d 935 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 936 #define CHIP_NUM_57840_4_10 0x16a1 937 #define CHIP_NUM_57840_2_20 0x16a2 938 #define CHIP_NUM_57840_MF 0x16a4 939 #define CHIP_NUM_57840_VF 0x16ad 940 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 941 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 942 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 943 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 944 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 945 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 946 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 947 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 948 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 949 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 950 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 951 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 952 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 953 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 954 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 955 #define CHIP_IS_57840(bp) \ 956 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 957 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 958 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 959 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 960 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 961 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 962 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 963 CHIP_IS_57711E(bp)) 964 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ 965 CHIP_IS_57811_MF(bp) || \ 966 CHIP_IS_57811_VF(bp)) 967 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 968 CHIP_IS_57712_MF(bp) || \ 969 CHIP_IS_57712_VF(bp)) 970 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 971 CHIP_IS_57800_MF(bp) || \ 972 CHIP_IS_57800_VF(bp) || \ 973 CHIP_IS_57810(bp) || \ 974 CHIP_IS_57810_MF(bp) || \ 975 CHIP_IS_57810_VF(bp) || \ 976 CHIP_IS_57811xx(bp) || \ 977 CHIP_IS_57840(bp) || \ 978 CHIP_IS_57840_MF(bp) || \ 979 CHIP_IS_57840_VF(bp)) 980 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 981 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 982 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 983 984 #define CHIP_REV_SHIFT 12 985 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 986 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 987 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 988 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 989 /* assume maximum 5 revisions */ 990 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 991 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 992 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 993 !(CHIP_REV_VAL(bp) & 0x00001000)) 994 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 995 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 996 (CHIP_REV_VAL(bp) & 0x00001000)) 997 998 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 999 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 1000 1001 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 1002 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 1003 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 1004 (CHIP_REV_SHIFT + 1)) \ 1005 << CHIP_REV_SHIFT) 1006 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 1007 CHIP_REV_SIM(bp) :\ 1008 CHIP_REV_VAL(bp)) 1009 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 1010 (CHIP_REV(bp) == CHIP_REV_Bx)) 1011 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 1012 (CHIP_REV(bp) == CHIP_REV_Ax)) 1013 /* This define is used in two main places: 1014 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher 1015 * to nic-only mode or to offload mode. Offload mode is configured if either the 1016 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 1017 * registered for this port (which means that the user wants storage services). 1018 * 2. During cnic-related load, to know if offload mode is already configured in 1019 * the HW or needs to be configured. 1020 * Since the transition from nic-mode to offload-mode in HW causes traffic 1021 * corruption, nic-mode is configured only in ports on which storage services 1022 * where never requested. 1023 */ 1024 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 1025 1026 int flash_size; 1027 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 1028 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 1029 #define BNX2X_NVRAM_PAGE_SIZE 256 1030 1031 u32 shmem_base; 1032 u32 shmem2_base; 1033 u32 mf_cfg_base; 1034 u32 mf2_cfg_base; 1035 1036 u32 hw_config; 1037 1038 u32 bc_ver; 1039 1040 u8 int_block; 1041 #define INT_BLOCK_HC 0 1042 #define INT_BLOCK_IGU 1 1043 #define INT_BLOCK_MODE_NORMAL 0 1044 #define INT_BLOCK_MODE_BW_COMP 2 1045 #define CHIP_INT_MODE_IS_NBC(bp) \ 1046 (!CHIP_IS_E1x(bp) && \ 1047 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 1048 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 1049 1050 u8 chip_port_mode; 1051 #define CHIP_4_PORT_MODE 0x0 1052 #define CHIP_2_PORT_MODE 0x1 1053 #define CHIP_PORT_MODE_NONE 0x2 1054 #define CHIP_MODE(bp) (bp->common.chip_port_mode) 1055 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 1056 1057 u32 boot_mode; 1058 }; 1059 1060 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 1061 #define BNX2X_IGU_STAS_MSG_VF_CNT 64 1062 #define BNX2X_IGU_STAS_MSG_PF_CNT 4 1063 1064 #define MAX_IGU_ATTN_ACK_TO 100 1065 /* end of common */ 1066 1067 /* port */ 1068 1069 struct bnx2x_port { 1070 u32 pmf; 1071 1072 u32 link_config[LINK_CONFIG_SIZE]; 1073 1074 u32 supported[LINK_CONFIG_SIZE]; 1075 /* link settings - missing defines */ 1076 #define SUPPORTED_2500baseX_Full (1 << 15) 1077 1078 u32 advertising[LINK_CONFIG_SIZE]; 1079 /* link settings - missing defines */ 1080 #define ADVERTISED_2500baseX_Full (1 << 15) 1081 1082 u32 phy_addr; 1083 1084 /* used to synchronize phy accesses */ 1085 struct mutex phy_mutex; 1086 1087 u32 port_stx; 1088 1089 struct nig_stats old_nig_stats; 1090 }; 1091 1092 /* end of port */ 1093 1094 #define STATS_OFFSET32(stat_name) \ 1095 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 1096 1097 /* slow path */ 1098 1099 /* slow path work-queue */ 1100 extern struct workqueue_struct *bnx2x_wq; 1101 1102 #define BNX2X_MAX_NUM_OF_VFS 64 1103 #define BNX2X_VF_CID_WND 0 1104 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 1105 #define BNX2X_CLIENTS_PER_VF 1 1106 #define BNX2X_FIRST_VF_CID 256 1107 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 1108 #define BNX2X_VF_ID_INVALID 0xFF 1109 1110 /* 1111 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 1112 * control by the number of fast-path status blocks supported by the 1113 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 1114 * status block represents an independent interrupts context that can 1115 * serve a regular L2 networking queue. However special L2 queues such 1116 * as the FCoE queue do not require a FP-SB and other components like 1117 * the CNIC may consume FP-SB reducing the number of possible L2 queues 1118 * 1119 * If the maximum number of FP-SB available is X then: 1120 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 1121 * regular L2 queues is Y=X-1 1122 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1123 * c. If the FCoE L2 queue is supported the actual number of L2 queues 1124 * is Y+1 1125 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1126 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1127 * FP interrupt context for the CNIC). 1128 * e. The number of HW context (CID count) is always X or X+1 if FCoE 1129 * L2 queue is supported. The cid for the FCoE L2 queue is always X. 1130 */ 1131 1132 /* fast-path interrupt contexts E1x */ 1133 #define FP_SB_MAX_E1x 16 1134 /* fast-path interrupt contexts E2 */ 1135 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1136 1137 union cdu_context { 1138 struct eth_context eth; 1139 char pad[1024]; 1140 }; 1141 1142 /* CDU host DB constants */ 1143 #define CDU_ILT_PAGE_SZ_HW 2 1144 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1145 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1146 1147 #define CNIC_ISCSI_CID_MAX 256 1148 #define CNIC_FCOE_CID_MAX 2048 1149 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1150 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1151 1152 #define QM_ILT_PAGE_SZ_HW 0 1153 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1154 #define QM_CID_ROUND 1024 1155 1156 /* TM (timers) host DB constants */ 1157 #define TM_ILT_PAGE_SZ_HW 0 1158 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1159 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 1160 #define TM_CONN_NUM 1024 1161 #define TM_ILT_SZ (8 * TM_CONN_NUM) 1162 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1163 1164 /* SRC (Searcher) host DB constants */ 1165 #define SRC_ILT_PAGE_SZ_HW 0 1166 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1167 #define SRC_HASH_BITS 10 1168 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1169 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1170 #define SRC_T2_SZ SRC_ILT_SZ 1171 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1172 1173 #define MAX_DMAE_C 8 1174 1175 /* DMA memory not used in fastpath */ 1176 struct bnx2x_slowpath { 1177 union { 1178 struct mac_configuration_cmd e1x; 1179 struct eth_classify_rules_ramrod_data e2; 1180 } mac_rdata; 1181 1182 union { 1183 struct tstorm_eth_mac_filter_config e1x; 1184 struct eth_filter_rules_ramrod_data e2; 1185 } rx_mode_rdata; 1186 1187 union { 1188 struct mac_configuration_cmd e1; 1189 struct eth_multicast_rules_ramrod_data e2; 1190 } mcast_rdata; 1191 1192 struct eth_rss_update_ramrod_data rss_rdata; 1193 1194 /* Queue State related ramrods are always sent under rtnl_lock */ 1195 union { 1196 struct client_init_ramrod_data init_data; 1197 struct client_update_ramrod_data update_data; 1198 } q_rdata; 1199 1200 union { 1201 struct function_start_data func_start; 1202 /* pfc configuration for DCBX ramrod */ 1203 struct flow_control_configuration pfc_config; 1204 } func_rdata; 1205 1206 /* afex ramrod can not be a part of func_rdata union because these 1207 * events might arrive in parallel to other events from func_rdata. 1208 * Therefore, if they would have been defined in the same union, 1209 * data can get corrupted. 1210 */ 1211 struct afex_vif_list_ramrod_data func_afex_rdata; 1212 1213 /* used by dmae command executer */ 1214 struct dmae_command dmae[MAX_DMAE_C]; 1215 1216 u32 stats_comp; 1217 union mac_stats mac_stats; 1218 struct nig_stats nig_stats; 1219 struct host_port_stats port_stats; 1220 struct host_func_stats func_stats; 1221 1222 u32 wb_comp; 1223 u32 wb_data[4]; 1224 1225 union drv_info_to_mcp drv_info_to_mcp; 1226 }; 1227 1228 #define bnx2x_sp(bp, var) (&bp->slowpath->var) 1229 #define bnx2x_sp_mapping(bp, var) \ 1230 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1231 1232 /* attn group wiring */ 1233 #define MAX_DYNAMIC_ATTN_GRPS 8 1234 1235 struct attn_route { 1236 u32 sig[5]; 1237 }; 1238 1239 struct iro { 1240 u32 base; 1241 u16 m1; 1242 u16 m2; 1243 u16 m3; 1244 u16 size; 1245 }; 1246 1247 struct hw_context { 1248 union cdu_context *vcxt; 1249 dma_addr_t cxt_mapping; 1250 size_t size; 1251 }; 1252 1253 /* forward */ 1254 struct bnx2x_ilt; 1255 1256 struct bnx2x_vfdb; 1257 1258 enum bnx2x_recovery_state { 1259 BNX2X_RECOVERY_DONE, 1260 BNX2X_RECOVERY_INIT, 1261 BNX2X_RECOVERY_WAIT, 1262 BNX2X_RECOVERY_FAILED, 1263 BNX2X_RECOVERY_NIC_LOADING 1264 }; 1265 1266 /* 1267 * Event queue (EQ or event ring) MC hsi 1268 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1269 */ 1270 #define NUM_EQ_PAGES 1 1271 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1272 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1273 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1274 #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1275 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1276 1277 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1278 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1279 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1280 1281 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1282 #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1283 1284 #define BNX2X_EQ_INDEX \ 1285 (&bp->def_status_blk->sp_sb.\ 1286 index_values[HC_SP_INDEX_EQ_CONS]) 1287 1288 /* This is a data that will be used to create a link report message. 1289 * We will keep the data used for the last link report in order 1290 * to prevent reporting the same link parameters twice. 1291 */ 1292 struct bnx2x_link_report_data { 1293 u16 line_speed; /* Effective line speed */ 1294 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1295 }; 1296 1297 enum { 1298 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1299 BNX2X_LINK_REPORT_LINK_DOWN, 1300 BNX2X_LINK_REPORT_RX_FC_ON, 1301 BNX2X_LINK_REPORT_TX_FC_ON, 1302 }; 1303 1304 enum { 1305 BNX2X_PORT_QUERY_IDX, 1306 BNX2X_PF_QUERY_IDX, 1307 BNX2X_FCOE_QUERY_IDX, 1308 BNX2X_FIRST_QUEUE_QUERY_IDX, 1309 }; 1310 1311 struct bnx2x_fw_stats_req { 1312 struct stats_query_header hdr; 1313 struct stats_query_entry query[FP_SB_MAX_E1x+ 1314 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1315 }; 1316 1317 struct bnx2x_fw_stats_data { 1318 struct stats_counter storm_counters; 1319 struct per_port_stats port; 1320 struct per_pf_stats pf; 1321 struct fcoe_statistics_params fcoe; 1322 struct per_queue_stats queue_stats[1]; 1323 }; 1324 1325 /* Public slow path states */ 1326 enum { 1327 BNX2X_SP_RTNL_SETUP_TC, 1328 BNX2X_SP_RTNL_TX_TIMEOUT, 1329 BNX2X_SP_RTNL_FAN_FAILURE, 1330 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1331 BNX2X_SP_RTNL_ENABLE_SRIOV, 1332 BNX2X_SP_RTNL_VFPF_MCAST, 1333 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 1334 BNX2X_SP_RTNL_RX_MODE, 1335 BNX2X_SP_RTNL_HYPERVISOR_VLAN, 1336 }; 1337 1338 struct bnx2x_prev_path_list { 1339 struct list_head list; 1340 u8 bus; 1341 u8 slot; 1342 u8 path; 1343 u8 aer; 1344 u8 undi; 1345 }; 1346 1347 struct bnx2x_sp_objs { 1348 /* MACs object */ 1349 struct bnx2x_vlan_mac_obj mac_obj; 1350 1351 /* Queue State object */ 1352 struct bnx2x_queue_sp_obj q_obj; 1353 }; 1354 1355 struct bnx2x_fp_stats { 1356 struct tstorm_per_queue_stats old_tclient; 1357 struct ustorm_per_queue_stats old_uclient; 1358 struct xstorm_per_queue_stats old_xclient; 1359 struct bnx2x_eth_q_stats eth_q_stats; 1360 struct bnx2x_eth_q_stats_old eth_q_stats_old; 1361 }; 1362 1363 struct bnx2x { 1364 /* Fields used in the tx and intr/napi performance paths 1365 * are grouped together in the beginning of the structure 1366 */ 1367 struct bnx2x_fastpath *fp; 1368 struct bnx2x_sp_objs *sp_objs; 1369 struct bnx2x_fp_stats *fp_stats; 1370 struct bnx2x_fp_txdata *bnx2x_txq; 1371 void __iomem *regview; 1372 void __iomem *doorbells; 1373 u16 db_size; 1374 1375 u8 pf_num; /* absolute PF number */ 1376 u8 pfid; /* per-path PF number */ 1377 int base_fw_ndsb; /**/ 1378 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1379 #define BP_PORT(bp) (bp->pfid & 1) 1380 #define BP_FUNC(bp) (bp->pfid) 1381 #define BP_ABS_FUNC(bp) (bp->pf_num) 1382 #define BP_VN(bp) ((bp)->pfid >> 1) 1383 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1384 #define BP_L_ID(bp) (BP_VN(bp) << 2) 1385 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1386 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1387 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1388 1389 #ifdef CONFIG_BNX2X_SRIOV 1390 /* protects vf2pf mailbox from simultaneous access */ 1391 struct mutex vf2pf_mutex; 1392 /* vf pf channel mailbox contains request and response buffers */ 1393 struct bnx2x_vf_mbx_msg *vf2pf_mbox; 1394 dma_addr_t vf2pf_mbox_mapping; 1395 1396 /* we set aside a copy of the acquire response */ 1397 struct pfvf_acquire_resp_tlv acquire_resp; 1398 1399 /* bulletin board for messages from pf to vf */ 1400 union pf_vf_bulletin *pf2vf_bulletin; 1401 dma_addr_t pf2vf_bulletin_mapping; 1402 1403 struct pf_vf_bulletin_content old_bulletin; 1404 1405 u16 requested_nr_virtfn; 1406 #endif /* CONFIG_BNX2X_SRIOV */ 1407 1408 struct net_device *dev; 1409 struct pci_dev *pdev; 1410 1411 const struct iro *iro_arr; 1412 #define IRO (bp->iro_arr) 1413 1414 enum bnx2x_recovery_state recovery_state; 1415 int is_leader; 1416 struct msix_entry *msix_table; 1417 1418 int tx_ring_size; 1419 1420 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1421 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1422 #define ETH_MIN_PACKET_SIZE 60 1423 #define ETH_MAX_PACKET_SIZE 1500 1424 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 1425 /* TCP with Timestamp Option (32) + IPv6 (40) */ 1426 #define ETH_MAX_TPA_HEADER_SIZE 72 1427 1428 /* Max supported alignment is 256 (8 shift) */ 1429 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1430 1431 /* FW uses 2 Cache lines Alignment for start packet and size 1432 * 1433 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1434 * at the end of skb->data, to avoid wasting a full cache line. 1435 * This reduces memory use (skb->truesize). 1436 */ 1437 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1438 1439 #define BNX2X_FW_RX_ALIGN_END \ 1440 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1441 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1442 1443 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1444 1445 struct host_sp_status_block *def_status_blk; 1446 #define DEF_SB_IGU_ID 16 1447 #define DEF_SB_ID HC_SP_SB_ID 1448 __le16 def_idx; 1449 __le16 def_att_idx; 1450 u32 attn_state; 1451 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1452 1453 /* slow path ring */ 1454 struct eth_spe *spq; 1455 dma_addr_t spq_mapping; 1456 u16 spq_prod_idx; 1457 struct eth_spe *spq_prod_bd; 1458 struct eth_spe *spq_last_bd; 1459 __le16 *dsb_sp_prod; 1460 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1461 /* used to synchronize spq accesses */ 1462 spinlock_t spq_lock; 1463 1464 /* event queue */ 1465 union event_ring_elem *eq_ring; 1466 dma_addr_t eq_mapping; 1467 u16 eq_prod; 1468 u16 eq_cons; 1469 __le16 *eq_cons_sb; 1470 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1471 1472 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1473 u16 stats_pending; 1474 /* Counter for completed statistics ramrods */ 1475 u16 stats_comp; 1476 1477 /* End of fields used in the performance code paths */ 1478 1479 int panic; 1480 int msg_enable; 1481 1482 u32 flags; 1483 #define PCIX_FLAG (1 << 0) 1484 #define PCI_32BIT_FLAG (1 << 1) 1485 #define ONE_PORT_FLAG (1 << 2) 1486 #define NO_WOL_FLAG (1 << 3) 1487 #define USING_DAC_FLAG (1 << 4) 1488 #define USING_MSIX_FLAG (1 << 5) 1489 #define USING_MSI_FLAG (1 << 6) 1490 #define DISABLE_MSI_FLAG (1 << 7) 1491 #define TPA_ENABLE_FLAG (1 << 8) 1492 #define NO_MCP_FLAG (1 << 9) 1493 #define GRO_ENABLE_FLAG (1 << 10) 1494 #define MF_FUNC_DIS (1 << 11) 1495 #define OWN_CNIC_IRQ (1 << 12) 1496 #define NO_ISCSI_OOO_FLAG (1 << 13) 1497 #define NO_ISCSI_FLAG (1 << 14) 1498 #define NO_FCOE_FLAG (1 << 15) 1499 #define BC_SUPPORTS_PFC_STATS (1 << 17) 1500 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 1501 #define USING_SINGLE_MSIX_FLAG (1 << 20) 1502 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 1503 #define IS_VF_FLAG (1 << 22) 1504 #define INTERRUPTS_ENABLED_FLAG (1 << 23) 1505 1506 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 1507 1508 #ifdef CONFIG_BNX2X_SRIOV 1509 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 1510 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 1511 #else 1512 #define IS_VF(bp) false 1513 #define IS_PF(bp) true 1514 #endif 1515 1516 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1517 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1518 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1519 1520 u8 cnic_support; 1521 bool cnic_enabled; 1522 bool cnic_loaded; 1523 struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 1524 1525 /* Flag that indicates that we can start looking for FCoE L2 queue 1526 * completions in the default status block. 1527 */ 1528 bool fcoe_init; 1529 1530 int pm_cap; 1531 int mrrs; 1532 1533 struct delayed_work sp_task; 1534 atomic_t interrupt_occurred; 1535 struct delayed_work sp_rtnl_task; 1536 1537 struct delayed_work period_task; 1538 struct timer_list timer; 1539 int current_interval; 1540 1541 u16 fw_seq; 1542 u16 fw_drv_pulse_wr_seq; 1543 u32 func_stx; 1544 1545 struct link_params link_params; 1546 struct link_vars link_vars; 1547 u32 link_cnt; 1548 struct bnx2x_link_report_data last_reported_link; 1549 1550 struct mdio_if_info mdio; 1551 1552 struct bnx2x_common common; 1553 struct bnx2x_port port; 1554 1555 struct cmng_init cmng; 1556 1557 u32 mf_config[E1HVN_MAX]; 1558 u32 mf_ext_config; 1559 u32 path_has_ovlan; /* E3 */ 1560 u16 mf_ov; 1561 u8 mf_mode; 1562 #define IS_MF(bp) (bp->mf_mode != 0) 1563 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1564 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1565 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1566 1567 u8 wol; 1568 1569 int rx_ring_size; 1570 1571 u16 tx_quick_cons_trip_int; 1572 u16 tx_quick_cons_trip; 1573 u16 tx_ticks_int; 1574 u16 tx_ticks; 1575 1576 u16 rx_quick_cons_trip_int; 1577 u16 rx_quick_cons_trip; 1578 u16 rx_ticks_int; 1579 u16 rx_ticks; 1580 /* Maximal coalescing timeout in us */ 1581 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) 1582 1583 u32 lin_cnt; 1584 1585 u16 state; 1586 #define BNX2X_STATE_CLOSED 0 1587 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1588 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1589 #define BNX2X_STATE_OPEN 0x3000 1590 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1591 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1592 1593 #define BNX2X_STATE_DIAG 0xe000 1594 #define BNX2X_STATE_ERROR 0xf000 1595 1596 #define BNX2X_MAX_PRIORITY 8 1597 #define BNX2X_MAX_ENTRIES_PER_PRI 16 1598 #define BNX2X_MAX_COS 3 1599 #define BNX2X_MAX_TX_COS 2 1600 int num_queues; 1601 uint num_ethernet_queues; 1602 uint num_cnic_queues; 1603 int num_napi_queues; 1604 int disable_tpa; 1605 1606 u32 rx_mode; 1607 #define BNX2X_RX_MODE_NONE 0 1608 #define BNX2X_RX_MODE_NORMAL 1 1609 #define BNX2X_RX_MODE_ALLMULTI 2 1610 #define BNX2X_RX_MODE_PROMISC 3 1611 #define BNX2X_MAX_MULTICAST 64 1612 1613 u8 igu_dsb_id; 1614 u8 igu_base_sb; 1615 u8 igu_sb_cnt; 1616 u8 min_msix_vec_cnt; 1617 1618 u32 igu_base_addr; 1619 dma_addr_t def_status_blk_mapping; 1620 1621 struct bnx2x_slowpath *slowpath; 1622 dma_addr_t slowpath_mapping; 1623 1624 /* Total number of FW statistics requests */ 1625 u8 fw_stats_num; 1626 1627 /* 1628 * This is a memory buffer that will contain both statistics 1629 * ramrod request and data. 1630 */ 1631 void *fw_stats; 1632 dma_addr_t fw_stats_mapping; 1633 1634 /* 1635 * FW statistics request shortcut (points at the 1636 * beginning of fw_stats buffer). 1637 */ 1638 struct bnx2x_fw_stats_req *fw_stats_req; 1639 dma_addr_t fw_stats_req_mapping; 1640 int fw_stats_req_sz; 1641 1642 /* 1643 * FW statistics data shortcut (points at the beginning of 1644 * fw_stats buffer + fw_stats_req_sz). 1645 */ 1646 struct bnx2x_fw_stats_data *fw_stats_data; 1647 dma_addr_t fw_stats_data_mapping; 1648 int fw_stats_data_sz; 1649 1650 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1651 * context size we need 8 ILT entries. 1652 */ 1653 #define ILT_MAX_L2_LINES 8 1654 struct hw_context context[ILT_MAX_L2_LINES]; 1655 1656 struct bnx2x_ilt *ilt; 1657 #define BP_ILT(bp) ((bp)->ilt) 1658 #define ILT_MAX_LINES 256 1659 /* 1660 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1661 * to CNIC. 1662 */ 1663 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1664 1665 /* 1666 * Maximum CID count that might be required by the bnx2x: 1667 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1668 */ 1669 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1670 + 2 * CNIC_SUPPORT(bp)) 1671 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1672 + 2 * CNIC_SUPPORT(bp)) 1673 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1674 ILT_PAGE_CIDS)) 1675 1676 int qm_cid_count; 1677 1678 bool dropless_fc; 1679 1680 void *t2; 1681 dma_addr_t t2_mapping; 1682 struct cnic_ops __rcu *cnic_ops; 1683 void *cnic_data; 1684 u32 cnic_tag; 1685 struct cnic_eth_dev cnic_eth_dev; 1686 union host_hc_status_block cnic_sb; 1687 dma_addr_t cnic_sb_mapping; 1688 struct eth_spe *cnic_kwq; 1689 struct eth_spe *cnic_kwq_prod; 1690 struct eth_spe *cnic_kwq_cons; 1691 struct eth_spe *cnic_kwq_last; 1692 u16 cnic_kwq_pending; 1693 u16 cnic_spq_pending; 1694 u8 fip_mac[ETH_ALEN]; 1695 struct mutex cnic_mutex; 1696 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1697 1698 /* Start index of the "special" (CNIC related) L2 clients */ 1699 u8 cnic_base_cl_id; 1700 1701 int dmae_ready; 1702 /* used to synchronize dmae accesses */ 1703 spinlock_t dmae_lock; 1704 1705 /* used to protect the FW mail box */ 1706 struct mutex fw_mb_mutex; 1707 1708 /* used to synchronize stats collecting */ 1709 int stats_state; 1710 1711 /* used for synchronization of concurrent threads statistics handling */ 1712 spinlock_t stats_lock; 1713 1714 /* used by dmae command loader */ 1715 struct dmae_command stats_dmae; 1716 int executer_idx; 1717 1718 u16 stats_counter; 1719 struct bnx2x_eth_stats eth_stats; 1720 struct host_func_stats func_stats; 1721 struct bnx2x_eth_stats_old eth_stats_old; 1722 struct bnx2x_net_stats_old net_stats_old; 1723 struct bnx2x_fw_port_stats_old fw_stats_old; 1724 bool stats_init; 1725 1726 struct z_stream_s *strm; 1727 void *gunzip_buf; 1728 dma_addr_t gunzip_mapping; 1729 int gunzip_outlen; 1730 #define FW_BUF_SIZE 0x8000 1731 #define GUNZIP_BUF(bp) (bp->gunzip_buf) 1732 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1733 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1734 1735 struct raw_op *init_ops; 1736 /* Init blocks offsets inside init_ops */ 1737 u16 *init_ops_offsets; 1738 /* Data blob - has 32 bit granularity */ 1739 u32 *init_data; 1740 u32 init_mode_flags; 1741 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1742 /* Zipped PRAM blobs - raw data */ 1743 const u8 *tsem_int_table_data; 1744 const u8 *tsem_pram_data; 1745 const u8 *usem_int_table_data; 1746 const u8 *usem_pram_data; 1747 const u8 *xsem_int_table_data; 1748 const u8 *xsem_pram_data; 1749 const u8 *csem_int_table_data; 1750 const u8 *csem_pram_data; 1751 #define INIT_OPS(bp) (bp->init_ops) 1752 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1753 #define INIT_DATA(bp) (bp->init_data) 1754 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1755 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1756 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1757 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1758 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1759 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1760 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1761 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1762 1763 #define PHY_FW_VER_LEN 20 1764 char fw_ver[32]; 1765 const struct firmware *firmware; 1766 1767 struct bnx2x_vfdb *vfdb; 1768 #define IS_SRIOV(bp) ((bp)->vfdb) 1769 1770 /* DCB support on/off */ 1771 u16 dcb_state; 1772 #define BNX2X_DCB_STATE_OFF 0 1773 #define BNX2X_DCB_STATE_ON 1 1774 1775 /* DCBX engine mode */ 1776 int dcbx_enabled; 1777 #define BNX2X_DCBX_ENABLED_OFF 0 1778 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1779 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1780 #define BNX2X_DCBX_ENABLED_INVALID (-1) 1781 1782 bool dcbx_mode_uset; 1783 1784 struct bnx2x_config_dcbx_params dcbx_config_params; 1785 struct bnx2x_dcbx_port_params dcbx_port_params; 1786 int dcb_version; 1787 1788 /* CAM credit pools */ 1789 1790 /* used only in sriov */ 1791 struct bnx2x_credit_pool_obj vlans_pool; 1792 1793 struct bnx2x_credit_pool_obj macs_pool; 1794 1795 /* RX_MODE object */ 1796 struct bnx2x_rx_mode_obj rx_mode_obj; 1797 1798 /* MCAST object */ 1799 struct bnx2x_mcast_obj mcast_obj; 1800 1801 /* RSS configuration object */ 1802 struct bnx2x_rss_config_obj rss_conf_obj; 1803 1804 /* Function State controlling object */ 1805 struct bnx2x_func_sp_obj func_obj; 1806 1807 unsigned long sp_state; 1808 1809 /* operation indication for the sp_rtnl task */ 1810 unsigned long sp_rtnl_state; 1811 1812 /* DCBX Negotiation results */ 1813 struct dcbx_features dcbx_local_feat; 1814 u32 dcbx_error; 1815 1816 #ifdef BCM_DCBNL 1817 struct dcbx_features dcbx_remote_feat; 1818 u32 dcbx_remote_flags; 1819 #endif 1820 /* AFEX: store default vlan used */ 1821 int afex_def_vlan_tag; 1822 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1823 u32 pending_max; 1824 1825 /* multiple tx classes of service */ 1826 u8 max_cos; 1827 1828 /* priority to cos mapping */ 1829 u8 prio_to_cos[8]; 1830 1831 int fp_array_size; 1832 u32 dump_preset_idx; 1833 }; 1834 1835 /* Tx queues may be less or equal to Rx queues */ 1836 extern int num_queues; 1837 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1838 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 1839 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 1840 (bp)->num_cnic_queues) 1841 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1842 1843 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1844 1845 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1846 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1847 1848 #define RSS_IPV4_CAP_MASK \ 1849 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1850 1851 #define RSS_IPV4_TCP_CAP_MASK \ 1852 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1853 1854 #define RSS_IPV6_CAP_MASK \ 1855 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1856 1857 #define RSS_IPV6_TCP_CAP_MASK \ 1858 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1859 1860 /* func init flags */ 1861 #define FUNC_FLG_RSS 0x0001 1862 #define FUNC_FLG_STATS 0x0002 1863 /* removed FUNC_FLG_UNMATCHED 0x0004 */ 1864 #define FUNC_FLG_TPA 0x0008 1865 #define FUNC_FLG_SPQ 0x0010 1866 #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1867 1868 struct bnx2x_func_init_params { 1869 /* dma */ 1870 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1871 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1872 1873 u16 func_flgs; 1874 u16 func_id; /* abs fid */ 1875 u16 pf_id; 1876 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1877 }; 1878 1879 #define for_each_cnic_queue(bp, var) \ 1880 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1881 (var)++) \ 1882 if (skip_queue(bp, var)) \ 1883 continue; \ 1884 else 1885 1886 #define for_each_eth_queue(bp, var) \ 1887 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1888 1889 #define for_each_nondefault_eth_queue(bp, var) \ 1890 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1891 1892 #define for_each_queue(bp, var) \ 1893 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1894 if (skip_queue(bp, var)) \ 1895 continue; \ 1896 else 1897 1898 /* Skip forwarding FP */ 1899 #define for_each_valid_rx_queue(bp, var) \ 1900 for ((var) = 0; \ 1901 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1902 BNX2X_NUM_ETH_QUEUES(bp)); \ 1903 (var)++) \ 1904 if (skip_rx_queue(bp, var)) \ 1905 continue; \ 1906 else 1907 1908 #define for_each_rx_queue_cnic(bp, var) \ 1909 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1910 (var)++) \ 1911 if (skip_rx_queue(bp, var)) \ 1912 continue; \ 1913 else 1914 1915 #define for_each_rx_queue(bp, var) \ 1916 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1917 if (skip_rx_queue(bp, var)) \ 1918 continue; \ 1919 else 1920 1921 /* Skip OOO FP */ 1922 #define for_each_valid_tx_queue(bp, var) \ 1923 for ((var) = 0; \ 1924 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1925 BNX2X_NUM_ETH_QUEUES(bp)); \ 1926 (var)++) \ 1927 if (skip_tx_queue(bp, var)) \ 1928 continue; \ 1929 else 1930 1931 #define for_each_tx_queue_cnic(bp, var) \ 1932 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1933 (var)++) \ 1934 if (skip_tx_queue(bp, var)) \ 1935 continue; \ 1936 else 1937 1938 #define for_each_tx_queue(bp, var) \ 1939 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1940 if (skip_tx_queue(bp, var)) \ 1941 continue; \ 1942 else 1943 1944 #define for_each_nondefault_queue(bp, var) \ 1945 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1946 if (skip_queue(bp, var)) \ 1947 continue; \ 1948 else 1949 1950 #define for_each_cos_in_tx_queue(fp, var) \ 1951 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1952 1953 /* skip rx queue 1954 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1955 */ 1956 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1957 1958 /* skip tx queue 1959 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1960 */ 1961 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1962 1963 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1964 1965 /** 1966 * bnx2x_set_mac_one - configure a single MAC address 1967 * 1968 * @bp: driver handle 1969 * @mac: MAC to configure 1970 * @obj: MAC object handle 1971 * @set: if 'true' add a new MAC, otherwise - delete 1972 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1973 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1974 * 1975 * Configures one MAC according to provided parameters or continues the 1976 * execution of previously scheduled commands if RAMROD_CONT is set in 1977 * ramrod_flags. 1978 * 1979 * Returns zero if operation has successfully completed, a positive value if the 1980 * operation has been successfully scheduled and a negative - if a requested 1981 * operations has failed. 1982 */ 1983 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1984 struct bnx2x_vlan_mac_obj *obj, bool set, 1985 int mac_type, unsigned long *ramrod_flags); 1986 /** 1987 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1988 * 1989 * @bp: driver handle 1990 * @mac_obj: MAC object handle 1991 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 1992 * @wait_for_comp: if 'true' block until completion 1993 * 1994 * Deletes all MACs of the specific type (e.g. ETH, UC list). 1995 * 1996 * Returns zero if operation has successfully completed, a positive value if the 1997 * operation has been successfully scheduled and a negative - if a requested 1998 * operations has failed. 1999 */ 2000 int bnx2x_del_all_macs(struct bnx2x *bp, 2001 struct bnx2x_vlan_mac_obj *mac_obj, 2002 int mac_type, bool wait_for_comp); 2003 2004 /* Init Function API */ 2005 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 2006 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 2007 u8 vf_valid, int fw_sb_id, int igu_sb_id); 2008 u32 bnx2x_get_pretend_reg(struct bnx2x *bp); 2009 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 2010 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2011 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 2012 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2013 void bnx2x_read_mf_cfg(struct bnx2x *bp); 2014 2015 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 2016 2017 /* dmae */ 2018 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 2019 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 2020 u32 len32); 2021 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 2022 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 2023 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 2024 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 2025 bool with_comp, u8 comp_type); 2026 2027 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2028 u8 src_type, u8 dst_type); 2029 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae); 2030 2031 /* FLR related routines */ 2032 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 2033 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 2034 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 2035 u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 2036 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 2037 char *msg, u32 poll_cnt); 2038 2039 void bnx2x_calc_fc_adv(struct bnx2x *bp); 2040 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 2041 u32 data_hi, u32 data_lo, int cmd_type); 2042 void bnx2x_update_coalesce(struct bnx2x *bp); 2043 int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 2044 2045 bool bnx2x_port_after_undi(struct bnx2x *bp); 2046 2047 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 2048 int wait) 2049 { 2050 u32 val; 2051 2052 do { 2053 val = REG_RD(bp, reg); 2054 if (val == expected) 2055 break; 2056 ms -= wait; 2057 msleep(wait); 2058 2059 } while (ms > 0); 2060 2061 return val; 2062 } 2063 2064 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 2065 bool is_pf); 2066 2067 #define BNX2X_ILT_ZALLOC(x, y, size) \ 2068 x = dma_alloc_coherent(&bp->pdev->dev, size, y, \ 2069 GFP_KERNEL | __GFP_ZERO) 2070 2071 #define BNX2X_ILT_FREE(x, y, size) \ 2072 do { \ 2073 if (x) { \ 2074 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 2075 x = NULL; \ 2076 y = 0; \ 2077 } \ 2078 } while (0) 2079 2080 #define ILOG2(x) (ilog2((x))) 2081 2082 #define ILT_NUM_PAGE_ENTRIES (3072) 2083 /* In 57710/11 we use whole table since we have 8 func 2084 * In 57712 we have only 4 func, but use same size per func, then only half of 2085 * the table in use 2086 */ 2087 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 2088 2089 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 2090 /* 2091 * the phys address is shifted right 12 bits and has an added 2092 * 1=valid bit added to the 53rd bit 2093 * then since this is a wide register(TM) 2094 * we split it into two 32 bit writes 2095 */ 2096 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 2097 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 2098 2099 /* load/unload mode */ 2100 #define LOAD_NORMAL 0 2101 #define LOAD_OPEN 1 2102 #define LOAD_DIAG 2 2103 #define LOAD_LOOPBACK_EXT 3 2104 #define UNLOAD_NORMAL 0 2105 #define UNLOAD_CLOSE 1 2106 #define UNLOAD_RECOVERY 2 2107 2108 /* DMAE command defines */ 2109 #define DMAE_TIMEOUT -1 2110 #define DMAE_PCI_ERROR -2 /* E2 and onward */ 2111 #define DMAE_NOT_RDY -3 2112 #define DMAE_PCI_ERR_FLAG 0x80000000 2113 2114 #define DMAE_SRC_PCI 0 2115 #define DMAE_SRC_GRC 1 2116 2117 #define DMAE_DST_NONE 0 2118 #define DMAE_DST_PCI 1 2119 #define DMAE_DST_GRC 2 2120 2121 #define DMAE_COMP_PCI 0 2122 #define DMAE_COMP_GRC 1 2123 2124 /* E2 and onward - PCI error handling in the completion */ 2125 2126 #define DMAE_COMP_REGULAR 0 2127 #define DMAE_COM_SET_ERR 1 2128 2129 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2130 DMAE_COMMAND_SRC_SHIFT) 2131 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2132 DMAE_COMMAND_SRC_SHIFT) 2133 2134 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2135 DMAE_COMMAND_DST_SHIFT) 2136 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2137 DMAE_COMMAND_DST_SHIFT) 2138 2139 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2140 DMAE_COMMAND_C_DST_SHIFT) 2141 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2142 DMAE_COMMAND_C_DST_SHIFT) 2143 2144 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2145 2146 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2147 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2148 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2149 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2150 2151 #define DMAE_CMD_PORT_0 0 2152 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2153 2154 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2155 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2156 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2157 2158 #define DMAE_SRC_PF 0 2159 #define DMAE_SRC_VF 1 2160 2161 #define DMAE_DST_PF 0 2162 #define DMAE_DST_VF 1 2163 2164 #define DMAE_C_SRC 0 2165 #define DMAE_C_DST 1 2166 2167 #define DMAE_LEN32_RD_MAX 0x80 2168 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2169 2170 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 2171 * indicates error 2172 */ 2173 2174 #define MAX_DMAE_C_PER_PORT 8 2175 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2176 BP_VN(bp)) 2177 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2178 E1HVN_MAX) 2179 2180 /* PCIE link and speed */ 2181 #define PCICFG_LINK_WIDTH 0x1f00000 2182 #define PCICFG_LINK_WIDTH_SHIFT 20 2183 #define PCICFG_LINK_SPEED 0xf0000 2184 #define PCICFG_LINK_SPEED_SHIFT 16 2185 2186 #define BNX2X_NUM_TESTS_SF 7 2187 #define BNX2X_NUM_TESTS_MF 3 2188 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 2189 BNX2X_NUM_TESTS_SF) 2190 2191 #define BNX2X_PHY_LOOPBACK 0 2192 #define BNX2X_MAC_LOOPBACK 1 2193 #define BNX2X_EXT_LOOPBACK 2 2194 #define BNX2X_PHY_LOOPBACK_FAILED 1 2195 #define BNX2X_MAC_LOOPBACK_FAILED 2 2196 #define BNX2X_EXT_LOOPBACK_FAILED 3 2197 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2198 BNX2X_PHY_LOOPBACK_FAILED) 2199 2200 #define STROM_ASSERT_ARRAY_SIZE 50 2201 2202 /* must be used on a CID before placing it on a HW ring */ 2203 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 2204 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2205 (x)) 2206 2207 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2208 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2209 2210 #define BNX2X_BTR 4 2211 #define MAX_SPQ_PENDING 8 2212 2213 /* CMNG constants, as derived from system spec calculations */ 2214 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2215 #define DEF_MIN_RATE 100 2216 /* resolution of the rate shaping timer - 400 usec */ 2217 #define RS_PERIODIC_TIMEOUT_USEC 400 2218 /* number of bytes in single QM arbitration cycle - 2219 * coefficient for calculating the fairness timer */ 2220 #define QM_ARB_BYTES 160000 2221 /* resolution of Min algorithm 1:100 */ 2222 #define MIN_RES 100 2223 /* how many bytes above threshold for the minimal credit of Min algorithm*/ 2224 #define MIN_ABOVE_THRESH 32768 2225 /* Fairness algorithm integration time coefficient - 2226 * for calculating the actual Tfair */ 2227 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2228 /* Memory of fairness algorithm . 2 cycles */ 2229 #define FAIR_MEM 2 2230 2231 #define ATTN_NIG_FOR_FUNC (1L << 8) 2232 #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2233 #define GPIO_2_FUNC (1L << 10) 2234 #define GPIO_3_FUNC (1L << 11) 2235 #define GPIO_4_FUNC (1L << 12) 2236 #define ATTN_GENERAL_ATTN_1 (1L << 13) 2237 #define ATTN_GENERAL_ATTN_2 (1L << 14) 2238 #define ATTN_GENERAL_ATTN_3 (1L << 15) 2239 #define ATTN_GENERAL_ATTN_4 (1L << 13) 2240 #define ATTN_GENERAL_ATTN_5 (1L << 14) 2241 #define ATTN_GENERAL_ATTN_6 (1L << 15) 2242 2243 #define ATTN_HARD_WIRED_MASK 0xff00 2244 #define ATTENTION_ID 4 2245 2246 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \ 2247 IS_MF_FCOE_AFEX(bp)) 2248 2249 /* stuff added to make the code fit 80Col */ 2250 2251 #define BNX2X_PMF_LINK_ASSERT \ 2252 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2253 2254 #define BNX2X_MC_ASSERT_BITS \ 2255 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2256 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2257 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2258 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2259 2260 #define BNX2X_MCP_ASSERT \ 2261 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2262 2263 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2264 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2265 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2266 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2267 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2268 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2269 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2270 2271 #define HW_INTERRUT_ASSERT_SET_0 \ 2272 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2273 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2274 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2275 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2276 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2277 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2278 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2279 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2280 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2281 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2282 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2283 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2284 #define HW_INTERRUT_ASSERT_SET_1 \ 2285 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2286 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2287 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2288 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2289 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2290 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2291 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2292 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2293 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2294 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2295 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2296 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2297 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2298 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2299 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2300 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2301 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2302 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2303 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2304 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2305 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2306 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2307 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2308 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2309 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2310 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2311 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2312 #define HW_INTERRUT_ASSERT_SET_2 \ 2313 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2314 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2315 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2316 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2317 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2318 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2319 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2320 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2321 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2322 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2323 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2324 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2325 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2326 2327 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2328 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2329 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2330 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2331 2332 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2333 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2334 2335 #define MULTI_MASK 0x7f 2336 2337 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2338 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2339 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2340 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2341 2342 #define DEF_USB_IGU_INDEX_OFF \ 2343 offsetof(struct cstorm_def_status_block_u, igu_index) 2344 #define DEF_CSB_IGU_INDEX_OFF \ 2345 offsetof(struct cstorm_def_status_block_c, igu_index) 2346 #define DEF_XSB_IGU_INDEX_OFF \ 2347 offsetof(struct xstorm_def_status_block, igu_index) 2348 #define DEF_TSB_IGU_INDEX_OFF \ 2349 offsetof(struct tstorm_def_status_block, igu_index) 2350 2351 #define DEF_USB_SEGMENT_OFF \ 2352 offsetof(struct cstorm_def_status_block_u, segment) 2353 #define DEF_CSB_SEGMENT_OFF \ 2354 offsetof(struct cstorm_def_status_block_c, segment) 2355 #define DEF_XSB_SEGMENT_OFF \ 2356 offsetof(struct xstorm_def_status_block, segment) 2357 #define DEF_TSB_SEGMENT_OFF \ 2358 offsetof(struct tstorm_def_status_block, segment) 2359 2360 #define BNX2X_SP_DSB_INDEX \ 2361 (&bp->def_status_blk->sp_sb.\ 2362 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2363 2364 #define CAM_IS_INVALID(x) \ 2365 (GET_FLAG(x.flags, \ 2366 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2367 (T_ETH_MAC_COMMAND_INVALIDATE)) 2368 2369 /* Number of u32 elements in MC hash array */ 2370 #define MC_HASH_SIZE 8 2371 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2372 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2373 2374 #ifndef PXP2_REG_PXP2_INT_STS 2375 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2376 #endif 2377 2378 #ifndef ETH_MAX_RX_CLIENTS_E2 2379 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2380 #endif 2381 2382 #define BNX2X_VPD_LEN 128 2383 #define VENDOR_ID_LEN 4 2384 2385 #define VF_ACQUIRE_THRESH 3 2386 #define VF_ACQUIRE_MAC_FILTERS 1 2387 #define VF_ACQUIRE_MC_FILTERS 10 2388 2389 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2390 (!((me_reg) & ME_REG_VF_ERR))) 2391 int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code); 2392 /* Congestion management fairness mode */ 2393 #define CMNG_FNS_NONE 0 2394 #define CMNG_FNS_MINMAX 1 2395 2396 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2397 #define HC_SEG_ACCESS_ATTN 4 2398 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2399 2400 static const u32 dmae_reg_go_c[] = { 2401 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2402 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2403 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2404 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2405 }; 2406 2407 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); 2408 void bnx2x_notify_link_changed(struct bnx2x *bp); 2409 2410 #define BNX2X_MF_SD_PROTOCOL(bp) \ 2411 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2412 2413 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2414 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2415 2416 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2417 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2418 2419 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2420 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2421 2422 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2423 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2424 2425 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 2426 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 2427 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2428 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2429 2430 #define SET_FLAG(value, mask, flag) \ 2431 do {\ 2432 (value) &= ~(mask);\ 2433 (value) |= ((flag) << (mask##_SHIFT));\ 2434 } while (0) 2435 2436 #define GET_FLAG(value, mask) \ 2437 (((value) & (mask)) >> (mask##_SHIFT)) 2438 2439 #define GET_FIELD(value, fname) \ 2440 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2441 2442 enum { 2443 SWITCH_UPDATE, 2444 AFEX_UPDATE, 2445 }; 2446 2447 #define NUM_MACS 8 2448 2449 enum bnx2x_pci_bus_speed { 2450 BNX2X_PCI_LINK_SPEED_2500 = 2500, 2451 BNX2X_PCI_LINK_SPEED_5000 = 5000, 2452 BNX2X_PCI_LINK_SPEED_8000 = 8000 2453 }; 2454 #endif /* bnx2x.h */ 2455