1adfc5217SJeff Kirsher /* bnx2x.h: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 385b26ea1SAriel Elior * Copyright (c) 2007-2012 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7adfc5217SJeff Kirsher * the Free Software Foundation. 8adfc5217SJeff Kirsher * 9adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10adfc5217SJeff Kirsher * Written by: Eliezer Tamir 11adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 12adfc5217SJeff Kirsher */ 13adfc5217SJeff Kirsher 14adfc5217SJeff Kirsher #ifndef BNX2X_H 15adfc5217SJeff Kirsher #define BNX2X_H 16adfc5217SJeff Kirsher #include <linux/netdevice.h> 17adfc5217SJeff Kirsher #include <linux/dma-mapping.h> 18adfc5217SJeff Kirsher #include <linux/types.h> 19adfc5217SJeff Kirsher 20adfc5217SJeff Kirsher /* compilation time flags */ 21adfc5217SJeff Kirsher 22adfc5217SJeff Kirsher /* define this to make the driver freeze on error to allow getting debug info 23adfc5217SJeff Kirsher * (you will need to reboot afterwards) */ 24adfc5217SJeff Kirsher /* #define BNX2X_STOP_ON_ERROR */ 25adfc5217SJeff Kirsher 26515e1240SYuval Mintz #define DRV_MODULE_VERSION "1.78.00-0" 27515e1240SYuval Mintz #define DRV_MODULE_RELDATE "2012/09/27" 28adfc5217SJeff Kirsher #define BNX2X_BC_VER 0x040200 29adfc5217SJeff Kirsher 30adfc5217SJeff Kirsher #if defined(CONFIG_DCB) 31adfc5217SJeff Kirsher #define BCM_DCBNL 32adfc5217SJeff Kirsher #endif 33b475d78fSYuval Mintz 34b475d78fSYuval Mintz 35b475d78fSYuval Mintz #include "bnx2x_hsi.h" 36b475d78fSYuval Mintz 37adfc5217SJeff Kirsher #include "../cnic_if.h" 38adfc5217SJeff Kirsher 3955c11941SMerav Sicron 4055c11941SMerav Sicron #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 41adfc5217SJeff Kirsher 42adfc5217SJeff Kirsher #include <linux/mdio.h> 43adfc5217SJeff Kirsher 44adfc5217SJeff Kirsher #include "bnx2x_reg.h" 45adfc5217SJeff Kirsher #include "bnx2x_fw_defs.h" 462e499d3cSBarak Witkowski #include "bnx2x_mfw_req.h" 47adfc5217SJeff Kirsher #include "bnx2x_link.h" 48adfc5217SJeff Kirsher #include "bnx2x_sp.h" 49adfc5217SJeff Kirsher #include "bnx2x_dcb.h" 50adfc5217SJeff Kirsher #include "bnx2x_stats.h" 51be1f1ffaSAriel Elior #include "bnx2x_vfpf.h" 52adfc5217SJeff Kirsher 531ab4434cSAriel Elior enum bnx2x_int_mode { 541ab4434cSAriel Elior BNX2X_INT_MODE_MSIX, 551ab4434cSAriel Elior BNX2X_INT_MODE_INTX, 561ab4434cSAriel Elior BNX2X_INT_MODE_MSI 571ab4434cSAriel Elior }; 581ab4434cSAriel Elior 59adfc5217SJeff Kirsher /* error/debug prints */ 60adfc5217SJeff Kirsher 61adfc5217SJeff Kirsher #define DRV_MODULE_NAME "bnx2x" 62adfc5217SJeff Kirsher 63adfc5217SJeff Kirsher /* for messages that are currently off */ 6451c1a580SMerav Sicron #define BNX2X_MSG_OFF 0x0 6551c1a580SMerav Sicron #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 6651c1a580SMerav Sicron #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 6751c1a580SMerav Sicron #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 6851c1a580SMerav Sicron #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 6951c1a580SMerav Sicron #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 7051c1a580SMerav Sicron #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 7151c1a580SMerav Sicron #define BNX2X_MSG_IOV 0x0800000 7251c1a580SMerav Sicron #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 7351c1a580SMerav Sicron #define BNX2X_MSG_ETHTOOL 0x4000000 7451c1a580SMerav Sicron #define BNX2X_MSG_DCB 0x8000000 75adfc5217SJeff Kirsher 76adfc5217SJeff Kirsher /* regular debug print */ 77f1deab50SJoe Perches #define DP(__mask, fmt, ...) \ 78adfc5217SJeff Kirsher do { \ 7951c1a580SMerav Sicron if (unlikely(bp->msg_enable & (__mask))) \ 80f1deab50SJoe Perches pr_notice("[%s:%d(%s)]" fmt, \ 81adfc5217SJeff Kirsher __func__, __LINE__, \ 82adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 83f1deab50SJoe Perches ##__VA_ARGS__); \ 84adfc5217SJeff Kirsher } while (0) 85adfc5217SJeff Kirsher 86f1deab50SJoe Perches #define DP_CONT(__mask, fmt, ...) \ 87adfc5217SJeff Kirsher do { \ 8851c1a580SMerav Sicron if (unlikely(bp->msg_enable & (__mask))) \ 89f1deab50SJoe Perches pr_cont(fmt, ##__VA_ARGS__); \ 90adfc5217SJeff Kirsher } while (0) 91adfc5217SJeff Kirsher 92adfc5217SJeff Kirsher /* errors debug print */ 93f1deab50SJoe Perches #define BNX2X_DBG_ERR(fmt, ...) \ 94adfc5217SJeff Kirsher do { \ 9551c1a580SMerav Sicron if (unlikely(netif_msg_probe(bp))) \ 96f1deab50SJoe Perches pr_err("[%s:%d(%s)]" fmt, \ 97adfc5217SJeff Kirsher __func__, __LINE__, \ 98adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 99f1deab50SJoe Perches ##__VA_ARGS__); \ 100adfc5217SJeff Kirsher } while (0) 101adfc5217SJeff Kirsher 102adfc5217SJeff Kirsher /* for errors (never masked) */ 103f1deab50SJoe Perches #define BNX2X_ERR(fmt, ...) \ 104adfc5217SJeff Kirsher do { \ 105f1deab50SJoe Perches pr_err("[%s:%d(%s)]" fmt, \ 106adfc5217SJeff Kirsher __func__, __LINE__, \ 107adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 108f1deab50SJoe Perches ##__VA_ARGS__); \ 109adfc5217SJeff Kirsher } while (0) 110adfc5217SJeff Kirsher 111f1deab50SJoe Perches #define BNX2X_ERROR(fmt, ...) \ 112f1deab50SJoe Perches pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 113adfc5217SJeff Kirsher 114adfc5217SJeff Kirsher 115adfc5217SJeff Kirsher /* before we have a dev->name use dev_info() */ 116f1deab50SJoe Perches #define BNX2X_DEV_INFO(fmt, ...) \ 117adfc5217SJeff Kirsher do { \ 11851c1a580SMerav Sicron if (unlikely(netif_msg_probe(bp))) \ 119f1deab50SJoe Perches dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 120adfc5217SJeff Kirsher } while (0) 121adfc5217SJeff Kirsher 122adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 123adfc5217SJeff Kirsher void bnx2x_int_disable(struct bnx2x *bp); 124f1deab50SJoe Perches #define bnx2x_panic() \ 125f1deab50SJoe Perches do { \ 126adfc5217SJeff Kirsher bp->panic = 1; \ 127adfc5217SJeff Kirsher BNX2X_ERR("driver assert\n"); \ 128adfc5217SJeff Kirsher bnx2x_int_disable(bp); \ 129adfc5217SJeff Kirsher bnx2x_panic_dump(bp); \ 130adfc5217SJeff Kirsher } while (0) 131adfc5217SJeff Kirsher #else 132f1deab50SJoe Perches #define bnx2x_panic() \ 133f1deab50SJoe Perches do { \ 134adfc5217SJeff Kirsher bp->panic = 1; \ 135adfc5217SJeff Kirsher BNX2X_ERR("driver assert\n"); \ 136adfc5217SJeff Kirsher bnx2x_panic_dump(bp); \ 137adfc5217SJeff Kirsher } while (0) 138adfc5217SJeff Kirsher #endif 139adfc5217SJeff Kirsher 140adfc5217SJeff Kirsher #define bnx2x_mc_addr(ha) ((ha)->addr) 141adfc5217SJeff Kirsher #define bnx2x_uc_addr(ha) ((ha)->addr) 142adfc5217SJeff Kirsher 143adfc5217SJeff Kirsher #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) 144adfc5217SJeff Kirsher #define U64_HI(x) (u32)(((u64)(x)) >> 32) 145adfc5217SJeff Kirsher #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 146adfc5217SJeff Kirsher 147adfc5217SJeff Kirsher 148adfc5217SJeff Kirsher #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 149adfc5217SJeff Kirsher 150adfc5217SJeff Kirsher #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 151adfc5217SJeff Kirsher #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 152adfc5217SJeff Kirsher #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 153adfc5217SJeff Kirsher 154adfc5217SJeff Kirsher #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 155adfc5217SJeff Kirsher #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 156adfc5217SJeff Kirsher #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 157adfc5217SJeff Kirsher 158adfc5217SJeff Kirsher #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 159adfc5217SJeff Kirsher #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 160adfc5217SJeff Kirsher 161adfc5217SJeff Kirsher #define REG_RD_DMAE(bp, offset, valp, len32) \ 162adfc5217SJeff Kirsher do { \ 163adfc5217SJeff Kirsher bnx2x_read_dmae(bp, offset, len32);\ 164adfc5217SJeff Kirsher memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 165adfc5217SJeff Kirsher } while (0) 166adfc5217SJeff Kirsher 167adfc5217SJeff Kirsher #define REG_WR_DMAE(bp, offset, valp, len32) \ 168adfc5217SJeff Kirsher do { \ 169adfc5217SJeff Kirsher memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 170adfc5217SJeff Kirsher bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 171adfc5217SJeff Kirsher offset, len32); \ 172adfc5217SJeff Kirsher } while (0) 173adfc5217SJeff Kirsher 174adfc5217SJeff Kirsher #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 175adfc5217SJeff Kirsher REG_WR_DMAE(bp, offset, valp, len32) 176adfc5217SJeff Kirsher 177adfc5217SJeff Kirsher #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 178adfc5217SJeff Kirsher do { \ 179adfc5217SJeff Kirsher memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 180adfc5217SJeff Kirsher bnx2x_write_big_buf_wb(bp, addr, len32); \ 181adfc5217SJeff Kirsher } while (0) 182adfc5217SJeff Kirsher 183adfc5217SJeff Kirsher #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 184adfc5217SJeff Kirsher offsetof(struct shmem_region, field)) 185adfc5217SJeff Kirsher #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 186adfc5217SJeff Kirsher #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 187adfc5217SJeff Kirsher 188adfc5217SJeff Kirsher #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 189adfc5217SJeff Kirsher offsetof(struct shmem2_region, field)) 190adfc5217SJeff Kirsher #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 191adfc5217SJeff Kirsher #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 192adfc5217SJeff Kirsher #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 193adfc5217SJeff Kirsher offsetof(struct mf_cfg, field)) 194adfc5217SJeff Kirsher #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 195adfc5217SJeff Kirsher offsetof(struct mf2_cfg, field)) 196adfc5217SJeff Kirsher 197adfc5217SJeff Kirsher #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 198adfc5217SJeff Kirsher #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 199adfc5217SJeff Kirsher MF_CFG_ADDR(bp, field), (val)) 200adfc5217SJeff Kirsher #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 201adfc5217SJeff Kirsher 202adfc5217SJeff Kirsher #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 203adfc5217SJeff Kirsher (SHMEM2_RD((bp), size) > \ 204adfc5217SJeff Kirsher offsetof(struct shmem2_region, field))) 205adfc5217SJeff Kirsher 206adfc5217SJeff Kirsher #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 207adfc5217SJeff Kirsher #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 208adfc5217SJeff Kirsher 209adfc5217SJeff Kirsher /* SP SB indices */ 210adfc5217SJeff Kirsher 211adfc5217SJeff Kirsher /* General SP events - stats query, cfc delete, etc */ 212adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_DEF_CONS 3 213adfc5217SJeff Kirsher 214adfc5217SJeff Kirsher /* EQ completions */ 215adfc5217SJeff Kirsher #define HC_SP_INDEX_EQ_CONS 7 216adfc5217SJeff Kirsher 217adfc5217SJeff Kirsher /* FCoE L2 connection completions */ 218adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 219adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 220adfc5217SJeff Kirsher /* iSCSI L2 */ 221adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 222adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 223adfc5217SJeff Kirsher 224adfc5217SJeff Kirsher /* Special clients parameters */ 225adfc5217SJeff Kirsher 226adfc5217SJeff Kirsher /* SB indices */ 227adfc5217SJeff Kirsher /* FCoE L2 */ 228adfc5217SJeff Kirsher #define BNX2X_FCOE_L2_RX_INDEX \ 229adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 230adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 231adfc5217SJeff Kirsher 232adfc5217SJeff Kirsher #define BNX2X_FCOE_L2_TX_INDEX \ 233adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 234adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 235adfc5217SJeff Kirsher 236adfc5217SJeff Kirsher /** 237adfc5217SJeff Kirsher * CIDs and CLIDs: 238adfc5217SJeff Kirsher * CLIDs below is a CLID for func 0, then the CLID for other 239adfc5217SJeff Kirsher * functions will be calculated by the formula: 240adfc5217SJeff Kirsher * 241adfc5217SJeff Kirsher * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 242adfc5217SJeff Kirsher * 243adfc5217SJeff Kirsher */ 2441805b2f0SDavid S. Miller enum { 2451805b2f0SDavid S. Miller BNX2X_ISCSI_ETH_CL_ID_IDX, 2461805b2f0SDavid S. Miller BNX2X_FCOE_ETH_CL_ID_IDX, 2471805b2f0SDavid S. Miller BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 2481805b2f0SDavid S. Miller }; 249adfc5217SJeff Kirsher 25037ae41a9SMerav Sicron #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\ 25137ae41a9SMerav Sicron (bp)->max_cos) 2521805b2f0SDavid S. Miller /* iSCSI L2 */ 25337ae41a9SMerav Sicron #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 254adfc5217SJeff Kirsher /* FCoE L2 */ 25537ae41a9SMerav Sicron #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 256adfc5217SJeff Kirsher 25755c11941SMerav Sicron #define CNIC_SUPPORT(bp) ((bp)->cnic_support) 25855c11941SMerav Sicron #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 25955c11941SMerav Sicron #define CNIC_LOADED(bp) ((bp)->cnic_loaded) 26055c11941SMerav Sicron #define FCOE_INIT(bp) ((bp)->fcoe_init) 261adfc5217SJeff Kirsher 262adfc5217SJeff Kirsher #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 263adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 264adfc5217SJeff Kirsher 265adfc5217SJeff Kirsher #define SM_RX_ID 0 266adfc5217SJeff Kirsher #define SM_TX_ID 1 267adfc5217SJeff Kirsher 268adfc5217SJeff Kirsher /* defines for multiple tx priority indices */ 269adfc5217SJeff Kirsher #define FIRST_TX_ONLY_COS_INDEX 1 270adfc5217SJeff Kirsher #define FIRST_TX_COS_INDEX 0 271adfc5217SJeff Kirsher 272adfc5217SJeff Kirsher /* rules for calculating the cids of tx-only connections */ 27365565884SMerav Sicron #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 27465565884SMerav Sicron #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 27565565884SMerav Sicron (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 276adfc5217SJeff Kirsher 277adfc5217SJeff Kirsher /* fp index inside class of service range */ 27865565884SMerav Sicron #define FP_COS_TO_TXQ(fp, cos, bp) \ 27965565884SMerav Sicron ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 280adfc5217SJeff Kirsher 28165565884SMerav Sicron /* Indexes for transmission queues array: 28265565884SMerav Sicron * txdata for RSS i CoS j is at location i + (j * num of RSS) 28365565884SMerav Sicron * txdata for FCoE (if exist) is at location max cos * num of RSS 28465565884SMerav Sicron * txdata for FWD (if exist) is one location after FCoE 28565565884SMerav Sicron * txdata for OOO (if exist) is one location after FWD 286adfc5217SJeff Kirsher */ 28765565884SMerav Sicron enum { 28865565884SMerav Sicron FCOE_TXQ_IDX_OFFSET, 28965565884SMerav Sicron FWD_TXQ_IDX_OFFSET, 29065565884SMerav Sicron OOO_TXQ_IDX_OFFSET, 29165565884SMerav Sicron }; 29265565884SMerav Sicron #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 29365565884SMerav Sicron #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 294adfc5217SJeff Kirsher 295adfc5217SJeff Kirsher /* fast path */ 296e52fcb24SEric Dumazet /* 297e52fcb24SEric Dumazet * This driver uses new build_skb() API : 298e52fcb24SEric Dumazet * RX ring buffer contains pointer to kmalloc() data only, 299e52fcb24SEric Dumazet * skb are built only after Hardware filled the frame. 300e52fcb24SEric Dumazet */ 301adfc5217SJeff Kirsher struct sw_rx_bd { 302e52fcb24SEric Dumazet u8 *data; 303adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping); 304adfc5217SJeff Kirsher }; 305adfc5217SJeff Kirsher 306adfc5217SJeff Kirsher struct sw_tx_bd { 307adfc5217SJeff Kirsher struct sk_buff *skb; 308adfc5217SJeff Kirsher u16 first_bd; 309adfc5217SJeff Kirsher u8 flags; 310adfc5217SJeff Kirsher /* Set on the first BD descriptor when there is a split BD */ 311adfc5217SJeff Kirsher #define BNX2X_TSO_SPLIT_BD (1<<0) 312adfc5217SJeff Kirsher }; 313adfc5217SJeff Kirsher 314adfc5217SJeff Kirsher struct sw_rx_page { 315adfc5217SJeff Kirsher struct page *page; 316adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping); 317adfc5217SJeff Kirsher }; 318adfc5217SJeff Kirsher 319adfc5217SJeff Kirsher union db_prod { 320adfc5217SJeff Kirsher struct doorbell_set_prod data; 321adfc5217SJeff Kirsher u32 raw; 322adfc5217SJeff Kirsher }; 323adfc5217SJeff Kirsher 3248decf868SDavid S. Miller /* dropless fc FW/HW related params */ 3258decf868SDavid S. Miller #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 3268decf868SDavid S. Miller #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 3278decf868SDavid S. Miller ETH_MAX_AGGREGATION_QUEUES_E1 :\ 3288decf868SDavid S. Miller ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 3298decf868SDavid S. Miller #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 3308decf868SDavid S. Miller #define FW_PREFETCH_CNT 16 3318decf868SDavid S. Miller #define DROPLESS_FC_HEADROOM 100 332adfc5217SJeff Kirsher 333adfc5217SJeff Kirsher /* MC hsi */ 334adfc5217SJeff Kirsher #define BCM_PAGE_SHIFT 12 335adfc5217SJeff Kirsher #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 336adfc5217SJeff Kirsher #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 337adfc5217SJeff Kirsher #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 338adfc5217SJeff Kirsher 339adfc5217SJeff Kirsher #define PAGES_PER_SGE_SHIFT 0 340adfc5217SJeff Kirsher #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 341adfc5217SJeff Kirsher #define SGE_PAGE_SIZE PAGE_SIZE 342adfc5217SJeff Kirsher #define SGE_PAGE_SHIFT PAGE_SHIFT 343adfc5217SJeff Kirsher #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 344adfc5217SJeff Kirsher 345adfc5217SJeff Kirsher /* SGE ring related macros */ 346adfc5217SJeff Kirsher #define NUM_RX_SGE_PAGES 2 347adfc5217SJeff Kirsher #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 3488decf868SDavid S. Miller #define NEXT_PAGE_SGE_DESC_CNT 2 3498decf868SDavid S. Miller #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 350adfc5217SJeff Kirsher /* RX_SGE_CNT is promised to be a power of 2 */ 351adfc5217SJeff Kirsher #define RX_SGE_MASK (RX_SGE_CNT - 1) 352adfc5217SJeff Kirsher #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 353adfc5217SJeff Kirsher #define MAX_RX_SGE (NUM_RX_SGE - 1) 354adfc5217SJeff Kirsher #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 3558decf868SDavid S. Miller (MAX_RX_SGE_CNT - 1)) ? \ 3568decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 3578decf868SDavid S. Miller (x) + 1) 358adfc5217SJeff Kirsher #define RX_SGE(x) ((x) & MAX_RX_SGE) 359adfc5217SJeff Kirsher 3608decf868SDavid S. Miller /* 3618decf868SDavid S. Miller * Number of required SGEs is the sum of two: 3628decf868SDavid S. Miller * 1. Number of possible opened aggregations (next packet for 3638decf868SDavid S. Miller * these aggregations will probably consume SGE immidiatelly) 3648decf868SDavid S. Miller * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 3658decf868SDavid S. Miller * after placement on BD for new TPA aggregation) 3668decf868SDavid S. Miller * 3678decf868SDavid S. Miller * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 3688decf868SDavid S. Miller */ 3698decf868SDavid S. Miller #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 3708decf868SDavid S. Miller (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 3718decf868SDavid S. Miller #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 3728decf868SDavid S. Miller MAX_RX_SGE_CNT) 3738decf868SDavid S. Miller #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 3748decf868SDavid S. Miller NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 3758decf868SDavid S. Miller #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 3768decf868SDavid S. Miller 377adfc5217SJeff Kirsher /* Manipulate a bit vector defined as an array of u64 */ 378adfc5217SJeff Kirsher 379adfc5217SJeff Kirsher /* Number of bits in one sge_mask array element */ 380adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_SZ 64 381adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_SHIFT 6 382adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 383adfc5217SJeff Kirsher 384adfc5217SJeff Kirsher 385adfc5217SJeff Kirsher #define __BIT_VEC64_SET_BIT(el, bit) \ 386adfc5217SJeff Kirsher do { \ 387adfc5217SJeff Kirsher el = ((el) | ((u64)0x1 << (bit))); \ 388adfc5217SJeff Kirsher } while (0) 389adfc5217SJeff Kirsher 390adfc5217SJeff Kirsher #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 391adfc5217SJeff Kirsher do { \ 392adfc5217SJeff Kirsher el = ((el) & (~((u64)0x1 << (bit)))); \ 393adfc5217SJeff Kirsher } while (0) 394adfc5217SJeff Kirsher 395adfc5217SJeff Kirsher 396adfc5217SJeff Kirsher #define BIT_VEC64_SET_BIT(vec64, idx) \ 397adfc5217SJeff Kirsher __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 398adfc5217SJeff Kirsher (idx) & BIT_VEC64_ELEM_MASK) 399adfc5217SJeff Kirsher 400adfc5217SJeff Kirsher #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 401adfc5217SJeff Kirsher __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 402adfc5217SJeff Kirsher (idx) & BIT_VEC64_ELEM_MASK) 403adfc5217SJeff Kirsher 404adfc5217SJeff Kirsher #define BIT_VEC64_TEST_BIT(vec64, idx) \ 405adfc5217SJeff Kirsher (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 406adfc5217SJeff Kirsher ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 407adfc5217SJeff Kirsher 408adfc5217SJeff Kirsher /* Creates a bitmask of all ones in less significant bits. 409adfc5217SJeff Kirsher idx - index of the most significant bit in the created mask */ 410adfc5217SJeff Kirsher #define BIT_VEC64_ONES_MASK(idx) \ 411adfc5217SJeff Kirsher (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 412adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 413adfc5217SJeff Kirsher 414adfc5217SJeff Kirsher /*******************************************************/ 415adfc5217SJeff Kirsher 416adfc5217SJeff Kirsher 417adfc5217SJeff Kirsher 418adfc5217SJeff Kirsher /* Number of u64 elements in SGE mask array */ 419b3637827SDmitry Kravkov #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 420adfc5217SJeff Kirsher #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 421adfc5217SJeff Kirsher #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 422adfc5217SJeff Kirsher 423adfc5217SJeff Kirsher union host_hc_status_block { 424adfc5217SJeff Kirsher /* pointer to fp status block e1x */ 425adfc5217SJeff Kirsher struct host_hc_status_block_e1x *e1x_sb; 426adfc5217SJeff Kirsher /* pointer to fp status block e2 */ 427adfc5217SJeff Kirsher struct host_hc_status_block_e2 *e2_sb; 428adfc5217SJeff Kirsher }; 429adfc5217SJeff Kirsher 430adfc5217SJeff Kirsher struct bnx2x_agg_info { 431adfc5217SJeff Kirsher /* 432e52fcb24SEric Dumazet * First aggregation buffer is a data buffer, the following - are pages. 433e52fcb24SEric Dumazet * We will preallocate the data buffer for each aggregation when 434adfc5217SJeff Kirsher * we open the interface and will replace the BD at the consumer 435adfc5217SJeff Kirsher * with this one when we receive the TPA_START CQE in order to 436adfc5217SJeff Kirsher * keep the Rx BD ring consistent. 437adfc5217SJeff Kirsher */ 438adfc5217SJeff Kirsher struct sw_rx_bd first_buf; 439adfc5217SJeff Kirsher u8 tpa_state; 440adfc5217SJeff Kirsher #define BNX2X_TPA_START 1 441adfc5217SJeff Kirsher #define BNX2X_TPA_STOP 2 442adfc5217SJeff Kirsher #define BNX2X_TPA_ERROR 3 443adfc5217SJeff Kirsher u8 placement_offset; 444adfc5217SJeff Kirsher u16 parsing_flags; 445adfc5217SJeff Kirsher u16 vlan_tag; 446adfc5217SJeff Kirsher u16 len_on_bd; 447e52fcb24SEric Dumazet u32 rxhash; 448a334b5fbSEric Dumazet bool l4_rxhash; 449621b4d66SDmitry Kravkov u16 gro_size; 450621b4d66SDmitry Kravkov u16 full_page; 451adfc5217SJeff Kirsher }; 452adfc5217SJeff Kirsher 453adfc5217SJeff Kirsher #define Q_STATS_OFFSET32(stat_name) \ 454adfc5217SJeff Kirsher (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 455adfc5217SJeff Kirsher 456adfc5217SJeff Kirsher struct bnx2x_fp_txdata { 457adfc5217SJeff Kirsher 458adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf_ring; 459adfc5217SJeff Kirsher 460adfc5217SJeff Kirsher union eth_tx_bd_types *tx_desc_ring; 461adfc5217SJeff Kirsher dma_addr_t tx_desc_mapping; 462adfc5217SJeff Kirsher 463adfc5217SJeff Kirsher u32 cid; 464adfc5217SJeff Kirsher 465adfc5217SJeff Kirsher union db_prod tx_db; 466adfc5217SJeff Kirsher 467adfc5217SJeff Kirsher u16 tx_pkt_prod; 468adfc5217SJeff Kirsher u16 tx_pkt_cons; 469adfc5217SJeff Kirsher u16 tx_bd_prod; 470adfc5217SJeff Kirsher u16 tx_bd_cons; 471adfc5217SJeff Kirsher 472adfc5217SJeff Kirsher unsigned long tx_pkt; 473adfc5217SJeff Kirsher 474adfc5217SJeff Kirsher __le16 *tx_cons_sb; 475adfc5217SJeff Kirsher 476adfc5217SJeff Kirsher int txq_index; 47765565884SMerav Sicron struct bnx2x_fastpath *parent_fp; 47865565884SMerav Sicron int tx_ring_size; 479adfc5217SJeff Kirsher }; 480adfc5217SJeff Kirsher 481621b4d66SDmitry Kravkov enum bnx2x_tpa_mode_t { 482621b4d66SDmitry Kravkov TPA_MODE_LRO, 483621b4d66SDmitry Kravkov TPA_MODE_GRO 484621b4d66SDmitry Kravkov }; 485621b4d66SDmitry Kravkov 486adfc5217SJeff Kirsher struct bnx2x_fastpath { 487adfc5217SJeff Kirsher struct bnx2x *bp; /* parent */ 488adfc5217SJeff Kirsher 489adfc5217SJeff Kirsher #define BNX2X_NAPI_WEIGHT 128 490adfc5217SJeff Kirsher struct napi_struct napi; 491adfc5217SJeff Kirsher union host_hc_status_block status_blk; 492adfc5217SJeff Kirsher /* chip independed shortcuts into sb structure */ 493adfc5217SJeff Kirsher __le16 *sb_index_values; 494adfc5217SJeff Kirsher __le16 *sb_running_index; 495adfc5217SJeff Kirsher /* chip independed shortcut into rx_prods_offset memory */ 496adfc5217SJeff Kirsher u32 ustorm_rx_prods_offset; 497adfc5217SJeff Kirsher 498adfc5217SJeff Kirsher u32 rx_buf_size; 499d46d132cSEric Dumazet u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 500adfc5217SJeff Kirsher dma_addr_t status_blk_mapping; 501adfc5217SJeff Kirsher 502621b4d66SDmitry Kravkov enum bnx2x_tpa_mode_t mode; 503621b4d66SDmitry Kravkov 504adfc5217SJeff Kirsher u8 max_cos; /* actual number of active tx coses */ 50565565884SMerav Sicron struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 506adfc5217SJeff Kirsher 507adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 508adfc5217SJeff Kirsher struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 509adfc5217SJeff Kirsher 510adfc5217SJeff Kirsher struct eth_rx_bd *rx_desc_ring; 511adfc5217SJeff Kirsher dma_addr_t rx_desc_mapping; 512adfc5217SJeff Kirsher 513adfc5217SJeff Kirsher union eth_rx_cqe *rx_comp_ring; 514adfc5217SJeff Kirsher dma_addr_t rx_comp_mapping; 515adfc5217SJeff Kirsher 516adfc5217SJeff Kirsher /* SGE ring */ 517adfc5217SJeff Kirsher struct eth_rx_sge *rx_sge_ring; 518adfc5217SJeff Kirsher dma_addr_t rx_sge_mapping; 519adfc5217SJeff Kirsher 520adfc5217SJeff Kirsher u64 sge_mask[RX_SGE_MASK_LEN]; 521adfc5217SJeff Kirsher 522adfc5217SJeff Kirsher u32 cid; 523adfc5217SJeff Kirsher 524adfc5217SJeff Kirsher __le16 fp_hc_idx; 525adfc5217SJeff Kirsher 526adfc5217SJeff Kirsher u8 index; /* number in fp array */ 527f233cafeSDmitry Kravkov u8 rx_queue; /* index for skb_record */ 528adfc5217SJeff Kirsher u8 cl_id; /* eth client id */ 529adfc5217SJeff Kirsher u8 cl_qzone_id; 530adfc5217SJeff Kirsher u8 fw_sb_id; /* status block number in FW */ 531adfc5217SJeff Kirsher u8 igu_sb_id; /* status block number in HW */ 532adfc5217SJeff Kirsher 533adfc5217SJeff Kirsher u16 rx_bd_prod; 534adfc5217SJeff Kirsher u16 rx_bd_cons; 535adfc5217SJeff Kirsher u16 rx_comp_prod; 536adfc5217SJeff Kirsher u16 rx_comp_cons; 537adfc5217SJeff Kirsher u16 rx_sge_prod; 538adfc5217SJeff Kirsher /* The last maximal completed SGE */ 539adfc5217SJeff Kirsher u16 last_max_sge; 540adfc5217SJeff Kirsher __le16 *rx_cons_sb; 541adfc5217SJeff Kirsher unsigned long rx_pkt, 542adfc5217SJeff Kirsher rx_calls; 543adfc5217SJeff Kirsher 544adfc5217SJeff Kirsher /* TPA related */ 54515192a8cSBarak Witkowski struct bnx2x_agg_info *tpa_info; 546adfc5217SJeff Kirsher u8 disable_tpa; 547adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 548adfc5217SJeff Kirsher u64 tpa_queue_used; 549adfc5217SJeff Kirsher #endif 550adfc5217SJeff Kirsher /* The size is calculated using the following: 551adfc5217SJeff Kirsher sizeof name field from netdev structure + 552adfc5217SJeff Kirsher 4 ('-Xx-' string) + 553adfc5217SJeff Kirsher 4 (for the digits and to make it DWORD aligned) */ 554adfc5217SJeff Kirsher #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 555adfc5217SJeff Kirsher char name[FP_NAME_SIZE]; 556adfc5217SJeff Kirsher }; 557adfc5217SJeff Kirsher 55815192a8cSBarak Witkowski #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 55915192a8cSBarak Witkowski #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 56015192a8cSBarak Witkowski #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 56115192a8cSBarak Witkowski #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 562adfc5217SJeff Kirsher 563adfc5217SJeff Kirsher /* Use 2500 as a mini-jumbo MTU for FCoE */ 564adfc5217SJeff Kirsher #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 565adfc5217SJeff Kirsher 56665565884SMerav Sicron #define FCOE_IDX_OFFSET 0 56765565884SMerav Sicron 56865565884SMerav Sicron #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 56965565884SMerav Sicron FCOE_IDX_OFFSET) 57065565884SMerav Sicron #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 571adfc5217SJeff Kirsher #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 57215192a8cSBarak Witkowski #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 57315192a8cSBarak Witkowski #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 574adfc5217SJeff Kirsher #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 57565565884SMerav Sicron txdata_ptr[FIRST_TX_COS_INDEX] \ 57665565884SMerav Sicron ->var) 577adfc5217SJeff Kirsher 578adfc5217SJeff Kirsher 57955c11941SMerav Sicron #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 58055c11941SMerav Sicron #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 58165565884SMerav Sicron #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 582adfc5217SJeff Kirsher 583adfc5217SJeff Kirsher 584adfc5217SJeff Kirsher /* MC hsi */ 585adfc5217SJeff Kirsher #define MAX_FETCH_BD 13 /* HW max BDs per packet */ 586adfc5217SJeff Kirsher #define RX_COPY_THRESH 92 587adfc5217SJeff Kirsher 588adfc5217SJeff Kirsher #define NUM_TX_RINGS 16 589adfc5217SJeff Kirsher #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 5908decf868SDavid S. Miller #define NEXT_PAGE_TX_DESC_CNT 1 5918decf868SDavid S. Miller #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 592adfc5217SJeff Kirsher #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 593adfc5217SJeff Kirsher #define MAX_TX_BD (NUM_TX_BD - 1) 594adfc5217SJeff Kirsher #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 595adfc5217SJeff Kirsher #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 5968decf868SDavid S. Miller (MAX_TX_DESC_CNT - 1)) ? \ 5978decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 5988decf868SDavid S. Miller (x) + 1) 599adfc5217SJeff Kirsher #define TX_BD(x) ((x) & MAX_TX_BD) 600adfc5217SJeff Kirsher #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 601adfc5217SJeff Kirsher 6027df2dc6bSDmitry Kravkov /* number of NEXT_PAGE descriptors may be required during placement */ 6037df2dc6bSDmitry Kravkov #define NEXT_CNT_PER_TX_PKT(bds) \ 6047df2dc6bSDmitry Kravkov (((bds) + MAX_TX_DESC_CNT - 1) / \ 6057df2dc6bSDmitry Kravkov MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 6067df2dc6bSDmitry Kravkov /* max BDs per tx packet w/o next_pages: 6077df2dc6bSDmitry Kravkov * START_BD - describes packed 6087df2dc6bSDmitry Kravkov * START_BD(splitted) - includes unpaged data segment for GSO 6097df2dc6bSDmitry Kravkov * PARSING_BD - for TSO and CSUM data 6107df2dc6bSDmitry Kravkov * Frag BDs - decribes pages for frags 6117df2dc6bSDmitry Kravkov */ 6127df2dc6bSDmitry Kravkov #define BDS_PER_TX_PKT 3 6137df2dc6bSDmitry Kravkov #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 6147df2dc6bSDmitry Kravkov /* max BDs per tx packet including next pages */ 6157df2dc6bSDmitry Kravkov #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 6167df2dc6bSDmitry Kravkov NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 6177df2dc6bSDmitry Kravkov 618adfc5217SJeff Kirsher /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 619adfc5217SJeff Kirsher #define NUM_RX_RINGS 8 620adfc5217SJeff Kirsher #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 6218decf868SDavid S. Miller #define NEXT_PAGE_RX_DESC_CNT 2 6228decf868SDavid S. Miller #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 623adfc5217SJeff Kirsher #define RX_DESC_MASK (RX_DESC_CNT - 1) 624adfc5217SJeff Kirsher #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 625adfc5217SJeff Kirsher #define MAX_RX_BD (NUM_RX_BD - 1) 626adfc5217SJeff Kirsher #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 6278decf868SDavid S. Miller 6288decf868SDavid S. Miller /* dropless fc calculations for BDs 6298decf868SDavid S. Miller * 6308decf868SDavid S. Miller * Number of BDs should as number of buffers in BRB: 6318decf868SDavid S. Miller * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 6328decf868SDavid S. Miller * "next" elements on each page 6338decf868SDavid S. Miller */ 6348decf868SDavid S. Miller #define NUM_BD_REQ BRB_SIZE(bp) 6358decf868SDavid S. Miller #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 6368decf868SDavid S. Miller MAX_RX_DESC_CNT) 6378decf868SDavid S. Miller #define BD_TH_LO(bp) (NUM_BD_REQ + \ 6388decf868SDavid S. Miller NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 6398decf868SDavid S. Miller FW_DROP_LEVEL(bp)) 6408decf868SDavid S. Miller #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 6418decf868SDavid S. Miller 6428decf868SDavid S. Miller #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 643adfc5217SJeff Kirsher 644adfc5217SJeff Kirsher #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 645adfc5217SJeff Kirsher ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 646adfc5217SJeff Kirsher ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 647adfc5217SJeff Kirsher #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 648adfc5217SJeff Kirsher #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 649adfc5217SJeff Kirsher #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 650adfc5217SJeff Kirsher MIN_RX_AVAIL)) 651adfc5217SJeff Kirsher 652adfc5217SJeff Kirsher #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 6538decf868SDavid S. Miller (MAX_RX_DESC_CNT - 1)) ? \ 6548decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 6558decf868SDavid S. Miller (x) + 1) 656adfc5217SJeff Kirsher #define RX_BD(x) ((x) & MAX_RX_BD) 657adfc5217SJeff Kirsher 658adfc5217SJeff Kirsher /* 659adfc5217SJeff Kirsher * As long as CQE is X times bigger than BD entry we have to allocate X times 660adfc5217SJeff Kirsher * more pages for CQ ring in order to keep it balanced with BD ring 661adfc5217SJeff Kirsher */ 662adfc5217SJeff Kirsher #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 663adfc5217SJeff Kirsher #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 664adfc5217SJeff Kirsher #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 6658decf868SDavid S. Miller #define NEXT_PAGE_RCQ_DESC_CNT 1 6668decf868SDavid S. Miller #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 667adfc5217SJeff Kirsher #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 668adfc5217SJeff Kirsher #define MAX_RCQ_BD (NUM_RCQ_BD - 1) 669adfc5217SJeff Kirsher #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 670adfc5217SJeff Kirsher #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 6718decf868SDavid S. Miller (MAX_RCQ_DESC_CNT - 1)) ? \ 6728decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 6738decf868SDavid S. Miller (x) + 1) 674adfc5217SJeff Kirsher #define RCQ_BD(x) ((x) & MAX_RCQ_BD) 675adfc5217SJeff Kirsher 6768decf868SDavid S. Miller /* dropless fc calculations for RCQs 6778decf868SDavid S. Miller * 6788decf868SDavid S. Miller * Number of RCQs should be as number of buffers in BRB: 6798decf868SDavid S. Miller * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 6808decf868SDavid S. Miller * "next" elements on each page 6818decf868SDavid S. Miller */ 6828decf868SDavid S. Miller #define NUM_RCQ_REQ BRB_SIZE(bp) 6838decf868SDavid S. Miller #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 6848decf868SDavid S. Miller MAX_RCQ_DESC_CNT) 6858decf868SDavid S. Miller #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 6868decf868SDavid S. Miller NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 6878decf868SDavid S. Miller FW_DROP_LEVEL(bp)) 6888decf868SDavid S. Miller #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 6898decf868SDavid S. Miller 690adfc5217SJeff Kirsher 691adfc5217SJeff Kirsher /* This is needed for determining of last_max */ 692adfc5217SJeff Kirsher #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 693adfc5217SJeff Kirsher #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 694adfc5217SJeff Kirsher 695adfc5217SJeff Kirsher 696adfc5217SJeff Kirsher #define BNX2X_SWCID_SHIFT 17 697adfc5217SJeff Kirsher #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 698adfc5217SJeff Kirsher 699adfc5217SJeff Kirsher /* used on a CID received from the HW */ 700adfc5217SJeff Kirsher #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 701adfc5217SJeff Kirsher #define CQE_CMD(x) (le32_to_cpu(x) >> \ 702adfc5217SJeff Kirsher COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 703adfc5217SJeff Kirsher 704adfc5217SJeff Kirsher #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 705adfc5217SJeff Kirsher le32_to_cpu((bd)->addr_lo)) 706adfc5217SJeff Kirsher #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 707adfc5217SJeff Kirsher 708adfc5217SJeff Kirsher #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 709adfc5217SJeff Kirsher #define BNX2X_DB_SHIFT 7 /* 128 bytes*/ 710adfc5217SJeff Kirsher #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 711adfc5217SJeff Kirsher #error "Min DB doorbell stride is 8" 712adfc5217SJeff Kirsher #endif 713adfc5217SJeff Kirsher #define DPM_TRIGER_TYPE 0x40 714adfc5217SJeff Kirsher #define DOORBELL(bp, cid, val) \ 715adfc5217SJeff Kirsher do { \ 716adfc5217SJeff Kirsher writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ 717adfc5217SJeff Kirsher DPM_TRIGER_TYPE); \ 718adfc5217SJeff Kirsher } while (0) 719adfc5217SJeff Kirsher 720adfc5217SJeff Kirsher 721adfc5217SJeff Kirsher /* TX CSUM helpers */ 722adfc5217SJeff Kirsher #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 723adfc5217SJeff Kirsher skb->csum_offset) 724adfc5217SJeff Kirsher #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 725adfc5217SJeff Kirsher skb->csum_offset)) 726adfc5217SJeff Kirsher 727adfc5217SJeff Kirsher #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) 728adfc5217SJeff Kirsher 729adfc5217SJeff Kirsher #define XMIT_PLAIN 0 730adfc5217SJeff Kirsher #define XMIT_CSUM_V4 0x1 731adfc5217SJeff Kirsher #define XMIT_CSUM_V6 0x2 732adfc5217SJeff Kirsher #define XMIT_CSUM_TCP 0x4 733adfc5217SJeff Kirsher #define XMIT_GSO_V4 0x8 734adfc5217SJeff Kirsher #define XMIT_GSO_V6 0x10 735adfc5217SJeff Kirsher 736adfc5217SJeff Kirsher #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) 737adfc5217SJeff Kirsher #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) 738adfc5217SJeff Kirsher 739adfc5217SJeff Kirsher 740adfc5217SJeff Kirsher /* stuff added to make the code fit 80Col */ 741adfc5217SJeff Kirsher #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 742adfc5217SJeff Kirsher #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 743adfc5217SJeff Kirsher #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 744adfc5217SJeff Kirsher #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 745adfc5217SJeff Kirsher #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 746adfc5217SJeff Kirsher 747adfc5217SJeff Kirsher #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 748adfc5217SJeff Kirsher 749adfc5217SJeff Kirsher #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 750adfc5217SJeff Kirsher (((le16_to_cpu(flags) & \ 751adfc5217SJeff Kirsher PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 752adfc5217SJeff Kirsher PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 753adfc5217SJeff Kirsher == PRS_FLAG_OVERETH_IPV4) 754adfc5217SJeff Kirsher #define BNX2X_RX_SUM_FIX(cqe) \ 755adfc5217SJeff Kirsher BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 756adfc5217SJeff Kirsher 757adfc5217SJeff Kirsher 758adfc5217SJeff Kirsher #define FP_USB_FUNC_OFF \ 759adfc5217SJeff Kirsher offsetof(struct cstorm_status_block_u, func) 760adfc5217SJeff Kirsher #define FP_CSB_FUNC_OFF \ 761adfc5217SJeff Kirsher offsetof(struct cstorm_status_block_c, func) 762adfc5217SJeff Kirsher 7638decf868SDavid S. Miller #define HC_INDEX_ETH_RX_CQ_CONS 1 764adfc5217SJeff Kirsher 7658decf868SDavid S. Miller #define HC_INDEX_OOO_TX_CQ_CONS 4 7668decf868SDavid S. Miller 7678decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 7688decf868SDavid S. Miller 7698decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 7708decf868SDavid S. Miller 7718decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 772adfc5217SJeff Kirsher 773adfc5217SJeff Kirsher #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 774adfc5217SJeff Kirsher 775adfc5217SJeff Kirsher #define BNX2X_RX_SB_INDEX \ 776adfc5217SJeff Kirsher (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 777adfc5217SJeff Kirsher 778adfc5217SJeff Kirsher #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 779adfc5217SJeff Kirsher 780adfc5217SJeff Kirsher #define BNX2X_TX_SB_INDEX_COS0 \ 781adfc5217SJeff Kirsher (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 782adfc5217SJeff Kirsher 783adfc5217SJeff Kirsher /* end of fast path */ 784adfc5217SJeff Kirsher 785adfc5217SJeff Kirsher /* common */ 786adfc5217SJeff Kirsher 787adfc5217SJeff Kirsher struct bnx2x_common { 788adfc5217SJeff Kirsher 789adfc5217SJeff Kirsher u32 chip_id; 790adfc5217SJeff Kirsher /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 791adfc5217SJeff Kirsher #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 792adfc5217SJeff Kirsher 793adfc5217SJeff Kirsher #define CHIP_NUM(bp) (bp->common.chip_id >> 16) 794adfc5217SJeff Kirsher #define CHIP_NUM_57710 0x164e 795adfc5217SJeff Kirsher #define CHIP_NUM_57711 0x164f 796adfc5217SJeff Kirsher #define CHIP_NUM_57711E 0x1650 797adfc5217SJeff Kirsher #define CHIP_NUM_57712 0x1662 798adfc5217SJeff Kirsher #define CHIP_NUM_57712_MF 0x1663 799adfc5217SJeff Kirsher #define CHIP_NUM_57713 0x1651 800adfc5217SJeff Kirsher #define CHIP_NUM_57713E 0x1652 801adfc5217SJeff Kirsher #define CHIP_NUM_57800 0x168a 802adfc5217SJeff Kirsher #define CHIP_NUM_57800_MF 0x16a5 803adfc5217SJeff Kirsher #define CHIP_NUM_57810 0x168e 804adfc5217SJeff Kirsher #define CHIP_NUM_57810_MF 0x16ae 8057e8e02dfSBarak Witkowski #define CHIP_NUM_57811 0x163d 8067e8e02dfSBarak Witkowski #define CHIP_NUM_57811_MF 0x163e 807c3def943SYuval Mintz #define CHIP_NUM_57840_OBSOLETE 0x168d 808c3def943SYuval Mintz #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 809c3def943SYuval Mintz #define CHIP_NUM_57840_4_10 0x16a1 810c3def943SYuval Mintz #define CHIP_NUM_57840_2_20 0x16a2 811c3def943SYuval Mintz #define CHIP_NUM_57840_MF 0x16a4 812adfc5217SJeff Kirsher #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 813adfc5217SJeff Kirsher #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 814adfc5217SJeff Kirsher #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 815adfc5217SJeff Kirsher #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 816adfc5217SJeff Kirsher #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 817adfc5217SJeff Kirsher #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 818adfc5217SJeff Kirsher #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 819adfc5217SJeff Kirsher #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 820adfc5217SJeff Kirsher #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 8217e8e02dfSBarak Witkowski #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 8227e8e02dfSBarak Witkowski #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 823c3def943SYuval Mintz #define CHIP_IS_57840(bp) \ 824c3def943SYuval Mintz ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 825c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 826c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 827c3def943SYuval Mintz #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 828c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 829adfc5217SJeff Kirsher #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 830adfc5217SJeff Kirsher CHIP_IS_57711E(bp)) 831adfc5217SJeff Kirsher #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 832adfc5217SJeff Kirsher CHIP_IS_57712_MF(bp)) 833adfc5217SJeff Kirsher #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 834adfc5217SJeff Kirsher CHIP_IS_57800_MF(bp) || \ 835adfc5217SJeff Kirsher CHIP_IS_57810(bp) || \ 836adfc5217SJeff Kirsher CHIP_IS_57810_MF(bp) || \ 8377e8e02dfSBarak Witkowski CHIP_IS_57811(bp) || \ 8387e8e02dfSBarak Witkowski CHIP_IS_57811_MF(bp) || \ 839adfc5217SJeff Kirsher CHIP_IS_57840(bp) || \ 840adfc5217SJeff Kirsher CHIP_IS_57840_MF(bp)) 841adfc5217SJeff Kirsher #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 842adfc5217SJeff Kirsher #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 843adfc5217SJeff Kirsher #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 844adfc5217SJeff Kirsher 845adfc5217SJeff Kirsher #define CHIP_REV_SHIFT 12 846adfc5217SJeff Kirsher #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 847adfc5217SJeff Kirsher #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 848adfc5217SJeff Kirsher #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 849adfc5217SJeff Kirsher #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 850adfc5217SJeff Kirsher /* assume maximum 5 revisions */ 851adfc5217SJeff Kirsher #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 852adfc5217SJeff Kirsher /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 853adfc5217SJeff Kirsher #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 854adfc5217SJeff Kirsher !(CHIP_REV_VAL(bp) & 0x00001000)) 855adfc5217SJeff Kirsher /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 856adfc5217SJeff Kirsher #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 857adfc5217SJeff Kirsher (CHIP_REV_VAL(bp) & 0x00001000)) 858adfc5217SJeff Kirsher 859adfc5217SJeff Kirsher #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 860adfc5217SJeff Kirsher ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 861adfc5217SJeff Kirsher 862adfc5217SJeff Kirsher #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 863adfc5217SJeff Kirsher #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 864adfc5217SJeff Kirsher #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 865adfc5217SJeff Kirsher (CHIP_REV_SHIFT + 1)) \ 866adfc5217SJeff Kirsher << CHIP_REV_SHIFT) 867adfc5217SJeff Kirsher #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 868adfc5217SJeff Kirsher CHIP_REV_SIM(bp) :\ 869adfc5217SJeff Kirsher CHIP_REV_VAL(bp)) 870adfc5217SJeff Kirsher #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 871adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Bx)) 872adfc5217SJeff Kirsher #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 873adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Ax)) 87455c11941SMerav Sicron /* This define is used in two main places: 87555c11941SMerav Sicron * 1. In the early stages of nic_load, to know if to configrue Parser / Searcher 87655c11941SMerav Sicron * to nic-only mode or to offload mode. Offload mode is configured if either the 87755c11941SMerav Sicron * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 87855c11941SMerav Sicron * registered for this port (which means that the user wants storage services). 87955c11941SMerav Sicron * 2. During cnic-related load, to know if offload mode is already configured in 88055c11941SMerav Sicron * the HW or needs to be configrued. 88155c11941SMerav Sicron * Since the transition from nic-mode to offload-mode in HW causes traffic 88255c11941SMerav Sicron * coruption, nic-mode is configured only in ports on which storage services 88355c11941SMerav Sicron * where never requested. 88455c11941SMerav Sicron */ 88555c11941SMerav Sicron #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 886adfc5217SJeff Kirsher 887adfc5217SJeff Kirsher int flash_size; 888adfc5217SJeff Kirsher #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 889adfc5217SJeff Kirsher #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 890adfc5217SJeff Kirsher #define BNX2X_NVRAM_PAGE_SIZE 256 891adfc5217SJeff Kirsher 892adfc5217SJeff Kirsher u32 shmem_base; 893adfc5217SJeff Kirsher u32 shmem2_base; 894adfc5217SJeff Kirsher u32 mf_cfg_base; 895adfc5217SJeff Kirsher u32 mf2_cfg_base; 896adfc5217SJeff Kirsher 897adfc5217SJeff Kirsher u32 hw_config; 898adfc5217SJeff Kirsher 899adfc5217SJeff Kirsher u32 bc_ver; 900adfc5217SJeff Kirsher 901adfc5217SJeff Kirsher u8 int_block; 902adfc5217SJeff Kirsher #define INT_BLOCK_HC 0 903adfc5217SJeff Kirsher #define INT_BLOCK_IGU 1 904adfc5217SJeff Kirsher #define INT_BLOCK_MODE_NORMAL 0 905adfc5217SJeff Kirsher #define INT_BLOCK_MODE_BW_COMP 2 906adfc5217SJeff Kirsher #define CHIP_INT_MODE_IS_NBC(bp) \ 907adfc5217SJeff Kirsher (!CHIP_IS_E1x(bp) && \ 908adfc5217SJeff Kirsher !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 909adfc5217SJeff Kirsher #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 910adfc5217SJeff Kirsher 911adfc5217SJeff Kirsher u8 chip_port_mode; 912adfc5217SJeff Kirsher #define CHIP_4_PORT_MODE 0x0 913adfc5217SJeff Kirsher #define CHIP_2_PORT_MODE 0x1 914adfc5217SJeff Kirsher #define CHIP_PORT_MODE_NONE 0x2 915adfc5217SJeff Kirsher #define CHIP_MODE(bp) (bp->common.chip_port_mode) 916adfc5217SJeff Kirsher #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 9171d187b34SBarak Witkowski 9181d187b34SBarak Witkowski u32 boot_mode; 919adfc5217SJeff Kirsher }; 920adfc5217SJeff Kirsher 921adfc5217SJeff Kirsher /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 922adfc5217SJeff Kirsher #define BNX2X_IGU_STAS_MSG_VF_CNT 64 923adfc5217SJeff Kirsher #define BNX2X_IGU_STAS_MSG_PF_CNT 4 924adfc5217SJeff Kirsher 92527c1151cSYaniv Rosner #define MAX_IGU_ATTN_ACK_TO 100 926adfc5217SJeff Kirsher /* end of common */ 927adfc5217SJeff Kirsher 928adfc5217SJeff Kirsher /* port */ 929adfc5217SJeff Kirsher 930adfc5217SJeff Kirsher struct bnx2x_port { 931adfc5217SJeff Kirsher u32 pmf; 932adfc5217SJeff Kirsher 933adfc5217SJeff Kirsher u32 link_config[LINK_CONFIG_SIZE]; 934adfc5217SJeff Kirsher 935adfc5217SJeff Kirsher u32 supported[LINK_CONFIG_SIZE]; 936adfc5217SJeff Kirsher /* link settings - missing defines */ 937adfc5217SJeff Kirsher #define SUPPORTED_2500baseX_Full (1 << 15) 938adfc5217SJeff Kirsher 939adfc5217SJeff Kirsher u32 advertising[LINK_CONFIG_SIZE]; 940adfc5217SJeff Kirsher /* link settings - missing defines */ 941adfc5217SJeff Kirsher #define ADVERTISED_2500baseX_Full (1 << 15) 942adfc5217SJeff Kirsher 943adfc5217SJeff Kirsher u32 phy_addr; 944adfc5217SJeff Kirsher 945adfc5217SJeff Kirsher /* used to synchronize phy accesses */ 946adfc5217SJeff Kirsher struct mutex phy_mutex; 947adfc5217SJeff Kirsher 948adfc5217SJeff Kirsher u32 port_stx; 949adfc5217SJeff Kirsher 950adfc5217SJeff Kirsher struct nig_stats old_nig_stats; 951adfc5217SJeff Kirsher }; 952adfc5217SJeff Kirsher 953adfc5217SJeff Kirsher /* end of port */ 954adfc5217SJeff Kirsher 955adfc5217SJeff Kirsher #define STATS_OFFSET32(stat_name) \ 956adfc5217SJeff Kirsher (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 957adfc5217SJeff Kirsher 958adfc5217SJeff Kirsher /* slow path */ 959adfc5217SJeff Kirsher 960adfc5217SJeff Kirsher /* slow path work-queue */ 961adfc5217SJeff Kirsher extern struct workqueue_struct *bnx2x_wq; 962adfc5217SJeff Kirsher 963adfc5217SJeff Kirsher #define BNX2X_MAX_NUM_OF_VFS 64 9641ab4434cSAriel Elior #define BNX2X_VF_CID_WND 0 9651ab4434cSAriel Elior #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 9661ab4434cSAriel Elior #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 967adfc5217SJeff Kirsher #define BNX2X_VF_ID_INVALID 0xFF 968adfc5217SJeff Kirsher 969adfc5217SJeff Kirsher /* 970adfc5217SJeff Kirsher * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 971adfc5217SJeff Kirsher * control by the number of fast-path status blocks supported by the 972adfc5217SJeff Kirsher * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 973adfc5217SJeff Kirsher * status block represents an independent interrupts context that can 974adfc5217SJeff Kirsher * serve a regular L2 networking queue. However special L2 queues such 975adfc5217SJeff Kirsher * as the FCoE queue do not require a FP-SB and other components like 976adfc5217SJeff Kirsher * the CNIC may consume FP-SB reducing the number of possible L2 queues 977adfc5217SJeff Kirsher * 978adfc5217SJeff Kirsher * If the maximum number of FP-SB available is X then: 979adfc5217SJeff Kirsher * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 980adfc5217SJeff Kirsher * regular L2 queues is Y=X-1 981adfc5217SJeff Kirsher * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 982adfc5217SJeff Kirsher * c. If the FCoE L2 queue is supported the actual number of L2 queues 983adfc5217SJeff Kirsher * is Y+1 984adfc5217SJeff Kirsher * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 985adfc5217SJeff Kirsher * slow-path interrupts) or Y+2 if CNIC is supported (one additional 986adfc5217SJeff Kirsher * FP interrupt context for the CNIC). 987adfc5217SJeff Kirsher * e. The number of HW context (CID count) is always X or X+1 if FCoE 988adfc5217SJeff Kirsher * L2 queue is supported. the cid for the FCoE L2 queue is always X. 989adfc5217SJeff Kirsher */ 990adfc5217SJeff Kirsher 991adfc5217SJeff Kirsher /* fast-path interrupt contexts E1x */ 992adfc5217SJeff Kirsher #define FP_SB_MAX_E1x 16 993adfc5217SJeff Kirsher /* fast-path interrupt contexts E2 */ 994adfc5217SJeff Kirsher #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 995adfc5217SJeff Kirsher 996adfc5217SJeff Kirsher union cdu_context { 997adfc5217SJeff Kirsher struct eth_context eth; 998adfc5217SJeff Kirsher char pad[1024]; 999adfc5217SJeff Kirsher }; 1000adfc5217SJeff Kirsher 1001adfc5217SJeff Kirsher /* CDU host DB constants */ 1002a052997eSMerav Sicron #define CDU_ILT_PAGE_SZ_HW 2 1003a052997eSMerav Sicron #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1004adfc5217SJeff Kirsher #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1005adfc5217SJeff Kirsher 1006adfc5217SJeff Kirsher #define CNIC_ISCSI_CID_MAX 256 1007adfc5217SJeff Kirsher #define CNIC_FCOE_CID_MAX 2048 1008adfc5217SJeff Kirsher #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1009adfc5217SJeff Kirsher #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1010adfc5217SJeff Kirsher 1011adfc5217SJeff Kirsher #define QM_ILT_PAGE_SZ_HW 0 1012adfc5217SJeff Kirsher #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1013adfc5217SJeff Kirsher #define QM_CID_ROUND 1024 1014adfc5217SJeff Kirsher 1015adfc5217SJeff Kirsher /* TM (timers) host DB constants */ 1016adfc5217SJeff Kirsher #define TM_ILT_PAGE_SZ_HW 0 1017adfc5217SJeff Kirsher #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1018adfc5217SJeff Kirsher /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 1019adfc5217SJeff Kirsher #define TM_CONN_NUM 1024 1020adfc5217SJeff Kirsher #define TM_ILT_SZ (8 * TM_CONN_NUM) 1021adfc5217SJeff Kirsher #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1022adfc5217SJeff Kirsher 1023adfc5217SJeff Kirsher /* SRC (Searcher) host DB constants */ 1024adfc5217SJeff Kirsher #define SRC_ILT_PAGE_SZ_HW 0 1025adfc5217SJeff Kirsher #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1026adfc5217SJeff Kirsher #define SRC_HASH_BITS 10 1027adfc5217SJeff Kirsher #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1028adfc5217SJeff Kirsher #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1029adfc5217SJeff Kirsher #define SRC_T2_SZ SRC_ILT_SZ 1030adfc5217SJeff Kirsher #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1031adfc5217SJeff Kirsher 1032adfc5217SJeff Kirsher #define MAX_DMAE_C 8 1033adfc5217SJeff Kirsher 1034adfc5217SJeff Kirsher /* DMA memory not used in fastpath */ 1035adfc5217SJeff Kirsher struct bnx2x_slowpath { 1036adfc5217SJeff Kirsher union { 1037adfc5217SJeff Kirsher struct mac_configuration_cmd e1x; 1038adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data e2; 1039adfc5217SJeff Kirsher } mac_rdata; 1040adfc5217SJeff Kirsher 1041adfc5217SJeff Kirsher 1042adfc5217SJeff Kirsher union { 1043adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config e1x; 1044adfc5217SJeff Kirsher struct eth_filter_rules_ramrod_data e2; 1045adfc5217SJeff Kirsher } rx_mode_rdata; 1046adfc5217SJeff Kirsher 1047adfc5217SJeff Kirsher union { 1048adfc5217SJeff Kirsher struct mac_configuration_cmd e1; 1049adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data e2; 1050adfc5217SJeff Kirsher } mcast_rdata; 1051adfc5217SJeff Kirsher 1052adfc5217SJeff Kirsher struct eth_rss_update_ramrod_data rss_rdata; 1053adfc5217SJeff Kirsher 1054adfc5217SJeff Kirsher /* Queue State related ramrods are always sent under rtnl_lock */ 1055adfc5217SJeff Kirsher union { 1056adfc5217SJeff Kirsher struct client_init_ramrod_data init_data; 1057adfc5217SJeff Kirsher struct client_update_ramrod_data update_data; 1058adfc5217SJeff Kirsher } q_rdata; 1059adfc5217SJeff Kirsher 1060adfc5217SJeff Kirsher union { 1061adfc5217SJeff Kirsher struct function_start_data func_start; 1062adfc5217SJeff Kirsher /* pfc configuration for DCBX ramrod */ 1063adfc5217SJeff Kirsher struct flow_control_configuration pfc_config; 1064adfc5217SJeff Kirsher } func_rdata; 1065adfc5217SJeff Kirsher 1066a3348722SBarak Witkowski /* afex ramrod can not be a part of func_rdata union because these 1067a3348722SBarak Witkowski * events might arrive in parallel to other events from func_rdata. 1068a3348722SBarak Witkowski * Therefore, if they would have been defined in the same union, 1069a3348722SBarak Witkowski * data can get corrupted. 1070a3348722SBarak Witkowski */ 1071a3348722SBarak Witkowski struct afex_vif_list_ramrod_data func_afex_rdata; 1072a3348722SBarak Witkowski 1073adfc5217SJeff Kirsher /* used by dmae command executer */ 1074adfc5217SJeff Kirsher struct dmae_command dmae[MAX_DMAE_C]; 1075adfc5217SJeff Kirsher 1076adfc5217SJeff Kirsher u32 stats_comp; 1077adfc5217SJeff Kirsher union mac_stats mac_stats; 1078adfc5217SJeff Kirsher struct nig_stats nig_stats; 1079adfc5217SJeff Kirsher struct host_port_stats port_stats; 1080adfc5217SJeff Kirsher struct host_func_stats func_stats; 1081adfc5217SJeff Kirsher 1082adfc5217SJeff Kirsher u32 wb_comp; 1083adfc5217SJeff Kirsher u32 wb_data[4]; 10841d187b34SBarak Witkowski 10851d187b34SBarak Witkowski union drv_info_to_mcp drv_info_to_mcp; 1086adfc5217SJeff Kirsher }; 1087adfc5217SJeff Kirsher 1088adfc5217SJeff Kirsher #define bnx2x_sp(bp, var) (&bp->slowpath->var) 1089adfc5217SJeff Kirsher #define bnx2x_sp_mapping(bp, var) \ 1090adfc5217SJeff Kirsher (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1091adfc5217SJeff Kirsher 1092adfc5217SJeff Kirsher 1093adfc5217SJeff Kirsher /* attn group wiring */ 1094adfc5217SJeff Kirsher #define MAX_DYNAMIC_ATTN_GRPS 8 1095adfc5217SJeff Kirsher 1096adfc5217SJeff Kirsher struct attn_route { 1097adfc5217SJeff Kirsher u32 sig[5]; 1098adfc5217SJeff Kirsher }; 1099adfc5217SJeff Kirsher 1100adfc5217SJeff Kirsher struct iro { 1101adfc5217SJeff Kirsher u32 base; 1102adfc5217SJeff Kirsher u16 m1; 1103adfc5217SJeff Kirsher u16 m2; 1104adfc5217SJeff Kirsher u16 m3; 1105adfc5217SJeff Kirsher u16 size; 1106adfc5217SJeff Kirsher }; 1107adfc5217SJeff Kirsher 1108adfc5217SJeff Kirsher struct hw_context { 1109adfc5217SJeff Kirsher union cdu_context *vcxt; 1110adfc5217SJeff Kirsher dma_addr_t cxt_mapping; 1111adfc5217SJeff Kirsher size_t size; 1112adfc5217SJeff Kirsher }; 1113adfc5217SJeff Kirsher 1114adfc5217SJeff Kirsher /* forward */ 1115adfc5217SJeff Kirsher struct bnx2x_ilt; 1116adfc5217SJeff Kirsher 1117adfc5217SJeff Kirsher 1118adfc5217SJeff Kirsher enum bnx2x_recovery_state { 1119adfc5217SJeff Kirsher BNX2X_RECOVERY_DONE, 1120adfc5217SJeff Kirsher BNX2X_RECOVERY_INIT, 1121adfc5217SJeff Kirsher BNX2X_RECOVERY_WAIT, 112295c6c616SAriel Elior BNX2X_RECOVERY_FAILED, 112395c6c616SAriel Elior BNX2X_RECOVERY_NIC_LOADING 1124adfc5217SJeff Kirsher }; 1125adfc5217SJeff Kirsher 1126adfc5217SJeff Kirsher /* 1127adfc5217SJeff Kirsher * Event queue (EQ or event ring) MC hsi 1128adfc5217SJeff Kirsher * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1129adfc5217SJeff Kirsher */ 1130adfc5217SJeff Kirsher #define NUM_EQ_PAGES 1 1131adfc5217SJeff Kirsher #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1132adfc5217SJeff Kirsher #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1133adfc5217SJeff Kirsher #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1134adfc5217SJeff Kirsher #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1135adfc5217SJeff Kirsher #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1136adfc5217SJeff Kirsher 1137adfc5217SJeff Kirsher /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1138adfc5217SJeff Kirsher #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1139adfc5217SJeff Kirsher (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1140adfc5217SJeff Kirsher 1141adfc5217SJeff Kirsher /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1142adfc5217SJeff Kirsher #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1143adfc5217SJeff Kirsher 1144adfc5217SJeff Kirsher #define BNX2X_EQ_INDEX \ 1145adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 1146adfc5217SJeff Kirsher index_values[HC_SP_INDEX_EQ_CONS]) 1147adfc5217SJeff Kirsher 1148adfc5217SJeff Kirsher /* This is a data that will be used to create a link report message. 1149adfc5217SJeff Kirsher * We will keep the data used for the last link report in order 1150adfc5217SJeff Kirsher * to prevent reporting the same link parameters twice. 1151adfc5217SJeff Kirsher */ 1152adfc5217SJeff Kirsher struct bnx2x_link_report_data { 1153adfc5217SJeff Kirsher u16 line_speed; /* Effective line speed */ 1154adfc5217SJeff Kirsher unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1155adfc5217SJeff Kirsher }; 1156adfc5217SJeff Kirsher 1157adfc5217SJeff Kirsher enum { 1158adfc5217SJeff Kirsher BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1159adfc5217SJeff Kirsher BNX2X_LINK_REPORT_LINK_DOWN, 1160adfc5217SJeff Kirsher BNX2X_LINK_REPORT_RX_FC_ON, 1161adfc5217SJeff Kirsher BNX2X_LINK_REPORT_TX_FC_ON, 1162adfc5217SJeff Kirsher }; 1163adfc5217SJeff Kirsher 1164adfc5217SJeff Kirsher enum { 1165adfc5217SJeff Kirsher BNX2X_PORT_QUERY_IDX, 1166adfc5217SJeff Kirsher BNX2X_PF_QUERY_IDX, 116750f0a562SBarak Witkowski BNX2X_FCOE_QUERY_IDX, 1168adfc5217SJeff Kirsher BNX2X_FIRST_QUEUE_QUERY_IDX, 1169adfc5217SJeff Kirsher }; 1170adfc5217SJeff Kirsher 1171adfc5217SJeff Kirsher struct bnx2x_fw_stats_req { 1172adfc5217SJeff Kirsher struct stats_query_header hdr; 117350f0a562SBarak Witkowski struct stats_query_entry query[FP_SB_MAX_E1x+ 117450f0a562SBarak Witkowski BNX2X_FIRST_QUEUE_QUERY_IDX]; 1175adfc5217SJeff Kirsher }; 1176adfc5217SJeff Kirsher 1177adfc5217SJeff Kirsher struct bnx2x_fw_stats_data { 1178adfc5217SJeff Kirsher struct stats_counter storm_counters; 1179adfc5217SJeff Kirsher struct per_port_stats port; 1180adfc5217SJeff Kirsher struct per_pf_stats pf; 118150f0a562SBarak Witkowski struct fcoe_statistics_params fcoe; 1182adfc5217SJeff Kirsher struct per_queue_stats queue_stats[1]; 1183adfc5217SJeff Kirsher }; 1184adfc5217SJeff Kirsher 1185adfc5217SJeff Kirsher /* Public slow path states */ 1186adfc5217SJeff Kirsher enum { 1187adfc5217SJeff Kirsher BNX2X_SP_RTNL_SETUP_TC, 1188adfc5217SJeff Kirsher BNX2X_SP_RTNL_TX_TIMEOUT, 1189a3348722SBarak Witkowski BNX2X_SP_RTNL_AFEX_F_UPDATE, 11908304859aSAriel Elior BNX2X_SP_RTNL_FAN_FAILURE, 1191adfc5217SJeff Kirsher }; 1192adfc5217SJeff Kirsher 1193adfc5217SJeff Kirsher 1194452427b0SYuval Mintz struct bnx2x_prev_path_list { 1195452427b0SYuval Mintz u8 bus; 1196452427b0SYuval Mintz u8 slot; 1197452427b0SYuval Mintz u8 path; 1198452427b0SYuval Mintz struct list_head list; 1199c63da990SBarak Witkowski u8 undi; 1200452427b0SYuval Mintz }; 1201452427b0SYuval Mintz 120215192a8cSBarak Witkowski struct bnx2x_sp_objs { 120315192a8cSBarak Witkowski /* MACs object */ 120415192a8cSBarak Witkowski struct bnx2x_vlan_mac_obj mac_obj; 120515192a8cSBarak Witkowski 120615192a8cSBarak Witkowski /* Queue State object */ 120715192a8cSBarak Witkowski struct bnx2x_queue_sp_obj q_obj; 120815192a8cSBarak Witkowski }; 120915192a8cSBarak Witkowski 121015192a8cSBarak Witkowski struct bnx2x_fp_stats { 121115192a8cSBarak Witkowski struct tstorm_per_queue_stats old_tclient; 121215192a8cSBarak Witkowski struct ustorm_per_queue_stats old_uclient; 121315192a8cSBarak Witkowski struct xstorm_per_queue_stats old_xclient; 121415192a8cSBarak Witkowski struct bnx2x_eth_q_stats eth_q_stats; 121515192a8cSBarak Witkowski struct bnx2x_eth_q_stats_old eth_q_stats_old; 121615192a8cSBarak Witkowski }; 121715192a8cSBarak Witkowski 1218adfc5217SJeff Kirsher struct bnx2x { 1219adfc5217SJeff Kirsher /* Fields used in the tx and intr/napi performance paths 1220adfc5217SJeff Kirsher * are grouped together in the beginning of the structure 1221adfc5217SJeff Kirsher */ 1222adfc5217SJeff Kirsher struct bnx2x_fastpath *fp; 122315192a8cSBarak Witkowski struct bnx2x_sp_objs *sp_objs; 122415192a8cSBarak Witkowski struct bnx2x_fp_stats *fp_stats; 122565565884SMerav Sicron struct bnx2x_fp_txdata *bnx2x_txq; 1226adfc5217SJeff Kirsher void __iomem *regview; 1227adfc5217SJeff Kirsher void __iomem *doorbells; 1228adfc5217SJeff Kirsher u16 db_size; 1229adfc5217SJeff Kirsher 1230adfc5217SJeff Kirsher u8 pf_num; /* absolute PF number */ 1231adfc5217SJeff Kirsher u8 pfid; /* per-path PF number */ 1232adfc5217SJeff Kirsher int base_fw_ndsb; /**/ 1233adfc5217SJeff Kirsher #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1234adfc5217SJeff Kirsher #define BP_PORT(bp) (bp->pfid & 1) 1235adfc5217SJeff Kirsher #define BP_FUNC(bp) (bp->pfid) 1236adfc5217SJeff Kirsher #define BP_ABS_FUNC(bp) (bp->pf_num) 12378decf868SDavid S. Miller #define BP_VN(bp) ((bp)->pfid >> 1) 12388decf868SDavid S. Miller #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 12398decf868SDavid S. Miller #define BP_L_ID(bp) (BP_VN(bp) << 2) 12408decf868SDavid S. Miller #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 12418decf868SDavid S. Miller (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 12428decf868SDavid S. Miller #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1243adfc5217SJeff Kirsher 12441ab4434cSAriel Elior /* vf pf channel mailbox contains request and response buffers */ 12451ab4434cSAriel Elior struct bnx2x_vf_mbx_msg *vf2pf_mbox; 12461ab4434cSAriel Elior dma_addr_t vf2pf_mbox_mapping; 12471ab4434cSAriel Elior 1248be1f1ffaSAriel Elior /* we set aside a copy of the acquire response */ 1249be1f1ffaSAriel Elior struct pfvf_acquire_resp_tlv acquire_resp; 1250be1f1ffaSAriel Elior 1251adfc5217SJeff Kirsher struct net_device *dev; 1252adfc5217SJeff Kirsher struct pci_dev *pdev; 1253adfc5217SJeff Kirsher 1254adfc5217SJeff Kirsher const struct iro *iro_arr; 1255adfc5217SJeff Kirsher #define IRO (bp->iro_arr) 1256adfc5217SJeff Kirsher 1257adfc5217SJeff Kirsher enum bnx2x_recovery_state recovery_state; 1258adfc5217SJeff Kirsher int is_leader; 1259adfc5217SJeff Kirsher struct msix_entry *msix_table; 1260adfc5217SJeff Kirsher 1261adfc5217SJeff Kirsher int tx_ring_size; 1262adfc5217SJeff Kirsher 1263adfc5217SJeff Kirsher /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1264adfc5217SJeff Kirsher #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1265adfc5217SJeff Kirsher #define ETH_MIN_PACKET_SIZE 60 1266adfc5217SJeff Kirsher #define ETH_MAX_PACKET_SIZE 1500 1267adfc5217SJeff Kirsher #define ETH_MAX_JUMBO_PACKET_SIZE 9600 1268621b4d66SDmitry Kravkov /* TCP with Timestamp Option (32) + IPv6 (40) */ 1269621b4d66SDmitry Kravkov #define ETH_MAX_TPA_HEADER_SIZE 72 1270adfc5217SJeff Kirsher 1271adfc5217SJeff Kirsher /* Max supported alignment is 256 (8 shift) */ 1272e52fcb24SEric Dumazet #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1273e52fcb24SEric Dumazet 1274e52fcb24SEric Dumazet /* FW uses 2 Cache lines Alignment for start packet and size 1275e52fcb24SEric Dumazet * 1276e52fcb24SEric Dumazet * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1277e52fcb24SEric Dumazet * at the end of skb->data, to avoid wasting a full cache line. 1278e52fcb24SEric Dumazet * This reduces memory use (skb->truesize). 1279e52fcb24SEric Dumazet */ 1280e52fcb24SEric Dumazet #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1281e52fcb24SEric Dumazet 1282e52fcb24SEric Dumazet #define BNX2X_FW_RX_ALIGN_END \ 1283f57b07c0SJoren Van Onder max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1284e52fcb24SEric Dumazet SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1285e52fcb24SEric Dumazet 1286adfc5217SJeff Kirsher #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1287adfc5217SJeff Kirsher 1288adfc5217SJeff Kirsher struct host_sp_status_block *def_status_blk; 1289adfc5217SJeff Kirsher #define DEF_SB_IGU_ID 16 1290adfc5217SJeff Kirsher #define DEF_SB_ID HC_SP_SB_ID 1291adfc5217SJeff Kirsher __le16 def_idx; 1292adfc5217SJeff Kirsher __le16 def_att_idx; 1293adfc5217SJeff Kirsher u32 attn_state; 1294adfc5217SJeff Kirsher struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1295adfc5217SJeff Kirsher 1296adfc5217SJeff Kirsher /* slow path ring */ 1297adfc5217SJeff Kirsher struct eth_spe *spq; 1298adfc5217SJeff Kirsher dma_addr_t spq_mapping; 1299adfc5217SJeff Kirsher u16 spq_prod_idx; 1300adfc5217SJeff Kirsher struct eth_spe *spq_prod_bd; 1301adfc5217SJeff Kirsher struct eth_spe *spq_last_bd; 1302adfc5217SJeff Kirsher __le16 *dsb_sp_prod; 1303adfc5217SJeff Kirsher atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1304adfc5217SJeff Kirsher /* used to synchronize spq accesses */ 1305adfc5217SJeff Kirsher spinlock_t spq_lock; 1306adfc5217SJeff Kirsher 1307adfc5217SJeff Kirsher /* event queue */ 1308adfc5217SJeff Kirsher union event_ring_elem *eq_ring; 1309adfc5217SJeff Kirsher dma_addr_t eq_mapping; 1310adfc5217SJeff Kirsher u16 eq_prod; 1311adfc5217SJeff Kirsher u16 eq_cons; 1312adfc5217SJeff Kirsher __le16 *eq_cons_sb; 1313adfc5217SJeff Kirsher atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1314adfc5217SJeff Kirsher 1315adfc5217SJeff Kirsher 1316adfc5217SJeff Kirsher 1317adfc5217SJeff Kirsher /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1318adfc5217SJeff Kirsher u16 stats_pending; 1319adfc5217SJeff Kirsher /* Counter for completed statistics ramrods */ 1320adfc5217SJeff Kirsher u16 stats_comp; 1321adfc5217SJeff Kirsher 1322adfc5217SJeff Kirsher /* End of fields used in the performance code paths */ 1323adfc5217SJeff Kirsher 1324adfc5217SJeff Kirsher int panic; 1325adfc5217SJeff Kirsher int msg_enable; 1326adfc5217SJeff Kirsher 1327adfc5217SJeff Kirsher u32 flags; 1328adfc5217SJeff Kirsher #define PCIX_FLAG (1 << 0) 1329adfc5217SJeff Kirsher #define PCI_32BIT_FLAG (1 << 1) 1330adfc5217SJeff Kirsher #define ONE_PORT_FLAG (1 << 2) 1331adfc5217SJeff Kirsher #define NO_WOL_FLAG (1 << 3) 1332adfc5217SJeff Kirsher #define USING_DAC_FLAG (1 << 4) 1333adfc5217SJeff Kirsher #define USING_MSIX_FLAG (1 << 5) 1334adfc5217SJeff Kirsher #define USING_MSI_FLAG (1 << 6) 1335adfc5217SJeff Kirsher #define DISABLE_MSI_FLAG (1 << 7) 1336adfc5217SJeff Kirsher #define TPA_ENABLE_FLAG (1 << 8) 1337adfc5217SJeff Kirsher #define NO_MCP_FLAG (1 << 9) 1338621b4d66SDmitry Kravkov #define GRO_ENABLE_FLAG (1 << 10) 1339adfc5217SJeff Kirsher #define MF_FUNC_DIS (1 << 11) 1340adfc5217SJeff Kirsher #define OWN_CNIC_IRQ (1 << 12) 1341adfc5217SJeff Kirsher #define NO_ISCSI_OOO_FLAG (1 << 13) 1342adfc5217SJeff Kirsher #define NO_ISCSI_FLAG (1 << 14) 1343adfc5217SJeff Kirsher #define NO_FCOE_FLAG (1 << 15) 13440e898dd7SBarak Witkowski #define BC_SUPPORTS_PFC_STATS (1 << 17) 13452e499d3cSBarak Witkowski #define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 134630a5de77SDmitry Kravkov #define USING_SINGLE_MSIX_FLAG (1 << 20) 13479876879fSBarak Witkowski #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 13481ab4434cSAriel Elior #define IS_VF_FLAG (1 << 22) 13491ab4434cSAriel Elior 13501ab4434cSAriel Elior #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 13511ab4434cSAriel Elior #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 13521ab4434cSAriel Elior #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 1353adfc5217SJeff Kirsher 1354adfc5217SJeff Kirsher #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1355adfc5217SJeff Kirsher #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1356adfc5217SJeff Kirsher #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1357adfc5217SJeff Kirsher 135855c11941SMerav Sicron u8 cnic_support; 135955c11941SMerav Sicron bool cnic_enabled; 136055c11941SMerav Sicron bool cnic_loaded; 13614bd9b0ffSMichael Chan struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 136255c11941SMerav Sicron 136355c11941SMerav Sicron /* Flag that indicates that we can start looking for FCoE L2 queue 136455c11941SMerav Sicron * completions in the default status block. 136555c11941SMerav Sicron */ 136655c11941SMerav Sicron bool fcoe_init; 136755c11941SMerav Sicron 1368adfc5217SJeff Kirsher int pm_cap; 1369adfc5217SJeff Kirsher int mrrs; 1370adfc5217SJeff Kirsher 1371adfc5217SJeff Kirsher struct delayed_work sp_task; 1372adfc5217SJeff Kirsher struct delayed_work sp_rtnl_task; 1373adfc5217SJeff Kirsher 1374adfc5217SJeff Kirsher struct delayed_work period_task; 1375adfc5217SJeff Kirsher struct timer_list timer; 1376adfc5217SJeff Kirsher int current_interval; 1377adfc5217SJeff Kirsher 1378adfc5217SJeff Kirsher u16 fw_seq; 1379adfc5217SJeff Kirsher u16 fw_drv_pulse_wr_seq; 1380adfc5217SJeff Kirsher u32 func_stx; 1381adfc5217SJeff Kirsher 1382adfc5217SJeff Kirsher struct link_params link_params; 1383adfc5217SJeff Kirsher struct link_vars link_vars; 1384adfc5217SJeff Kirsher u32 link_cnt; 1385adfc5217SJeff Kirsher struct bnx2x_link_report_data last_reported_link; 1386adfc5217SJeff Kirsher 1387adfc5217SJeff Kirsher struct mdio_if_info mdio; 1388adfc5217SJeff Kirsher 1389adfc5217SJeff Kirsher struct bnx2x_common common; 1390adfc5217SJeff Kirsher struct bnx2x_port port; 1391adfc5217SJeff Kirsher 1392b475d78fSYuval Mintz struct cmng_init cmng; 1393b475d78fSYuval Mintz 1394adfc5217SJeff Kirsher u32 mf_config[E1HVN_MAX]; 1395a3348722SBarak Witkowski u32 mf_ext_config; 1396adfc5217SJeff Kirsher u32 path_has_ovlan; /* E3 */ 1397adfc5217SJeff Kirsher u16 mf_ov; 1398adfc5217SJeff Kirsher u8 mf_mode; 1399adfc5217SJeff Kirsher #define IS_MF(bp) (bp->mf_mode != 0) 1400adfc5217SJeff Kirsher #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1401adfc5217SJeff Kirsher #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1402a3348722SBarak Witkowski #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1403adfc5217SJeff Kirsher 1404adfc5217SJeff Kirsher u8 wol; 1405adfc5217SJeff Kirsher 1406adfc5217SJeff Kirsher int rx_ring_size; 1407adfc5217SJeff Kirsher 1408adfc5217SJeff Kirsher u16 tx_quick_cons_trip_int; 1409adfc5217SJeff Kirsher u16 tx_quick_cons_trip; 1410adfc5217SJeff Kirsher u16 tx_ticks_int; 1411adfc5217SJeff Kirsher u16 tx_ticks; 1412adfc5217SJeff Kirsher 1413adfc5217SJeff Kirsher u16 rx_quick_cons_trip_int; 1414adfc5217SJeff Kirsher u16 rx_quick_cons_trip; 1415adfc5217SJeff Kirsher u16 rx_ticks_int; 1416adfc5217SJeff Kirsher u16 rx_ticks; 1417adfc5217SJeff Kirsher /* Maximal coalescing timeout in us */ 1418adfc5217SJeff Kirsher #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) 1419adfc5217SJeff Kirsher 1420adfc5217SJeff Kirsher u32 lin_cnt; 1421adfc5217SJeff Kirsher 1422adfc5217SJeff Kirsher u16 state; 1423adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSED 0 1424adfc5217SJeff Kirsher #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1425adfc5217SJeff Kirsher #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1426adfc5217SJeff Kirsher #define BNX2X_STATE_OPEN 0x3000 1427adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1428adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1429adfc5217SJeff Kirsher 1430adfc5217SJeff Kirsher #define BNX2X_STATE_DIAG 0xe000 1431adfc5217SJeff Kirsher #define BNX2X_STATE_ERROR 0xf000 1432adfc5217SJeff Kirsher 1433adfc5217SJeff Kirsher #define BNX2X_MAX_PRIORITY 8 1434adfc5217SJeff Kirsher #define BNX2X_MAX_ENTRIES_PER_PRI 16 1435adfc5217SJeff Kirsher #define BNX2X_MAX_COS 3 1436adfc5217SJeff Kirsher #define BNX2X_MAX_TX_COS 2 1437adfc5217SJeff Kirsher int num_queues; 143855c11941SMerav Sicron uint num_ethernet_queues; 143955c11941SMerav Sicron uint num_cnic_queues; 14400e8d2ec5SMerav Sicron int num_napi_queues; 1441adfc5217SJeff Kirsher int disable_tpa; 1442adfc5217SJeff Kirsher 1443adfc5217SJeff Kirsher u32 rx_mode; 1444adfc5217SJeff Kirsher #define BNX2X_RX_MODE_NONE 0 1445adfc5217SJeff Kirsher #define BNX2X_RX_MODE_NORMAL 1 1446adfc5217SJeff Kirsher #define BNX2X_RX_MODE_ALLMULTI 2 1447adfc5217SJeff Kirsher #define BNX2X_RX_MODE_PROMISC 3 1448adfc5217SJeff Kirsher #define BNX2X_MAX_MULTICAST 64 1449adfc5217SJeff Kirsher 1450adfc5217SJeff Kirsher u8 igu_dsb_id; 1451adfc5217SJeff Kirsher u8 igu_base_sb; 1452adfc5217SJeff Kirsher u8 igu_sb_cnt; 145355c11941SMerav Sicron u8 min_msix_vec_cnt; 145465565884SMerav Sicron 14551ab4434cSAriel Elior u32 igu_base_addr; 1456adfc5217SJeff Kirsher dma_addr_t def_status_blk_mapping; 1457adfc5217SJeff Kirsher 1458adfc5217SJeff Kirsher struct bnx2x_slowpath *slowpath; 1459adfc5217SJeff Kirsher dma_addr_t slowpath_mapping; 1460adfc5217SJeff Kirsher 1461adfc5217SJeff Kirsher /* Total number of FW statistics requests */ 1462adfc5217SJeff Kirsher u8 fw_stats_num; 1463adfc5217SJeff Kirsher 1464adfc5217SJeff Kirsher /* 1465adfc5217SJeff Kirsher * This is a memory buffer that will contain both statistics 1466adfc5217SJeff Kirsher * ramrod request and data. 1467adfc5217SJeff Kirsher */ 1468adfc5217SJeff Kirsher void *fw_stats; 1469adfc5217SJeff Kirsher dma_addr_t fw_stats_mapping; 1470adfc5217SJeff Kirsher 1471adfc5217SJeff Kirsher /* 1472adfc5217SJeff Kirsher * FW statistics request shortcut (points at the 1473adfc5217SJeff Kirsher * beginning of fw_stats buffer). 1474adfc5217SJeff Kirsher */ 1475adfc5217SJeff Kirsher struct bnx2x_fw_stats_req *fw_stats_req; 1476adfc5217SJeff Kirsher dma_addr_t fw_stats_req_mapping; 1477adfc5217SJeff Kirsher int fw_stats_req_sz; 1478adfc5217SJeff Kirsher 1479adfc5217SJeff Kirsher /* 14804907cb7bSAnatol Pomozov * FW statistics data shortcut (points at the beginning of 1481adfc5217SJeff Kirsher * fw_stats buffer + fw_stats_req_sz). 1482adfc5217SJeff Kirsher */ 1483adfc5217SJeff Kirsher struct bnx2x_fw_stats_data *fw_stats_data; 1484adfc5217SJeff Kirsher dma_addr_t fw_stats_data_mapping; 1485adfc5217SJeff Kirsher int fw_stats_data_sz; 1486adfc5217SJeff Kirsher 1487a052997eSMerav Sicron /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1488a052997eSMerav Sicron * context size we need 8 ILT entries. 1489a052997eSMerav Sicron */ 1490a052997eSMerav Sicron #define ILT_MAX_L2_LINES 8 1491a052997eSMerav Sicron struct hw_context context[ILT_MAX_L2_LINES]; 1492adfc5217SJeff Kirsher 1493adfc5217SJeff Kirsher struct bnx2x_ilt *ilt; 1494adfc5217SJeff Kirsher #define BP_ILT(bp) ((bp)->ilt) 1495adfc5217SJeff Kirsher #define ILT_MAX_LINES 256 1496adfc5217SJeff Kirsher /* 1497adfc5217SJeff Kirsher * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1498adfc5217SJeff Kirsher * to CNIC. 1499adfc5217SJeff Kirsher */ 150055c11941SMerav Sicron #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1501adfc5217SJeff Kirsher 1502adfc5217SJeff Kirsher /* 1503adfc5217SJeff Kirsher * Maximum CID count that might be required by the bnx2x: 150437ae41a9SMerav Sicron * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1505adfc5217SJeff Kirsher */ 150637ae41a9SMerav Sicron #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 150755c11941SMerav Sicron + 2 * CNIC_SUPPORT(bp)) 150837ae41a9SMerav Sicron #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 150955c11941SMerav Sicron + 2 * CNIC_SUPPORT(bp)) 1510adfc5217SJeff Kirsher #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1511adfc5217SJeff Kirsher ILT_PAGE_CIDS)) 1512adfc5217SJeff Kirsher 1513adfc5217SJeff Kirsher int qm_cid_count; 1514adfc5217SJeff Kirsher 15157964211dSYuval Mintz bool dropless_fc; 1516adfc5217SJeff Kirsher 1517adfc5217SJeff Kirsher void *t2; 1518adfc5217SJeff Kirsher dma_addr_t t2_mapping; 1519adfc5217SJeff Kirsher struct cnic_ops __rcu *cnic_ops; 1520adfc5217SJeff Kirsher void *cnic_data; 1521adfc5217SJeff Kirsher u32 cnic_tag; 1522adfc5217SJeff Kirsher struct cnic_eth_dev cnic_eth_dev; 1523adfc5217SJeff Kirsher union host_hc_status_block cnic_sb; 1524adfc5217SJeff Kirsher dma_addr_t cnic_sb_mapping; 1525adfc5217SJeff Kirsher struct eth_spe *cnic_kwq; 1526adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_prod; 1527adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_cons; 1528adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_last; 1529adfc5217SJeff Kirsher u16 cnic_kwq_pending; 1530adfc5217SJeff Kirsher u16 cnic_spq_pending; 1531adfc5217SJeff Kirsher u8 fip_mac[ETH_ALEN]; 1532adfc5217SJeff Kirsher struct mutex cnic_mutex; 1533adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1534adfc5217SJeff Kirsher 1535adfc5217SJeff Kirsher /* Start index of the "special" (CNIC related) L2 cleints */ 1536adfc5217SJeff Kirsher u8 cnic_base_cl_id; 1537adfc5217SJeff Kirsher 1538adfc5217SJeff Kirsher int dmae_ready; 1539adfc5217SJeff Kirsher /* used to synchronize dmae accesses */ 1540adfc5217SJeff Kirsher spinlock_t dmae_lock; 1541adfc5217SJeff Kirsher 1542adfc5217SJeff Kirsher /* used to protect the FW mail box */ 1543adfc5217SJeff Kirsher struct mutex fw_mb_mutex; 1544adfc5217SJeff Kirsher 1545adfc5217SJeff Kirsher /* used to synchronize stats collecting */ 1546adfc5217SJeff Kirsher int stats_state; 1547adfc5217SJeff Kirsher 1548adfc5217SJeff Kirsher /* used for synchronization of concurrent threads statistics handling */ 1549adfc5217SJeff Kirsher spinlock_t stats_lock; 1550adfc5217SJeff Kirsher 1551adfc5217SJeff Kirsher /* used by dmae command loader */ 1552adfc5217SJeff Kirsher struct dmae_command stats_dmae; 1553adfc5217SJeff Kirsher int executer_idx; 1554adfc5217SJeff Kirsher 1555adfc5217SJeff Kirsher u16 stats_counter; 1556adfc5217SJeff Kirsher struct bnx2x_eth_stats eth_stats; 1557cb4dca27SYuval Mintz struct host_func_stats func_stats; 15581355b704SMintz Yuval struct bnx2x_eth_stats_old eth_stats_old; 15591355b704SMintz Yuval struct bnx2x_net_stats_old net_stats_old; 15601355b704SMintz Yuval struct bnx2x_fw_port_stats_old fw_stats_old; 15611355b704SMintz Yuval bool stats_init; 1562adfc5217SJeff Kirsher 1563adfc5217SJeff Kirsher struct z_stream_s *strm; 1564adfc5217SJeff Kirsher void *gunzip_buf; 1565adfc5217SJeff Kirsher dma_addr_t gunzip_mapping; 1566adfc5217SJeff Kirsher int gunzip_outlen; 1567adfc5217SJeff Kirsher #define FW_BUF_SIZE 0x8000 1568adfc5217SJeff Kirsher #define GUNZIP_BUF(bp) (bp->gunzip_buf) 1569adfc5217SJeff Kirsher #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1570adfc5217SJeff Kirsher #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1571adfc5217SJeff Kirsher 1572adfc5217SJeff Kirsher struct raw_op *init_ops; 1573adfc5217SJeff Kirsher /* Init blocks offsets inside init_ops */ 1574adfc5217SJeff Kirsher u16 *init_ops_offsets; 1575adfc5217SJeff Kirsher /* Data blob - has 32 bit granularity */ 1576adfc5217SJeff Kirsher u32 *init_data; 1577adfc5217SJeff Kirsher u32 init_mode_flags; 1578adfc5217SJeff Kirsher #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1579adfc5217SJeff Kirsher /* Zipped PRAM blobs - raw data */ 1580adfc5217SJeff Kirsher const u8 *tsem_int_table_data; 1581adfc5217SJeff Kirsher const u8 *tsem_pram_data; 1582adfc5217SJeff Kirsher const u8 *usem_int_table_data; 1583adfc5217SJeff Kirsher const u8 *usem_pram_data; 1584adfc5217SJeff Kirsher const u8 *xsem_int_table_data; 1585adfc5217SJeff Kirsher const u8 *xsem_pram_data; 1586adfc5217SJeff Kirsher const u8 *csem_int_table_data; 1587adfc5217SJeff Kirsher const u8 *csem_pram_data; 1588adfc5217SJeff Kirsher #define INIT_OPS(bp) (bp->init_ops) 1589adfc5217SJeff Kirsher #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1590adfc5217SJeff Kirsher #define INIT_DATA(bp) (bp->init_data) 1591adfc5217SJeff Kirsher #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1592adfc5217SJeff Kirsher #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1593adfc5217SJeff Kirsher #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1594adfc5217SJeff Kirsher #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1595adfc5217SJeff Kirsher #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1596adfc5217SJeff Kirsher #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1597adfc5217SJeff Kirsher #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1598adfc5217SJeff Kirsher #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1599adfc5217SJeff Kirsher 1600adfc5217SJeff Kirsher #define PHY_FW_VER_LEN 20 1601adfc5217SJeff Kirsher char fw_ver[32]; 1602adfc5217SJeff Kirsher const struct firmware *firmware; 1603adfc5217SJeff Kirsher 1604adfc5217SJeff Kirsher /* DCB support on/off */ 1605adfc5217SJeff Kirsher u16 dcb_state; 1606adfc5217SJeff Kirsher #define BNX2X_DCB_STATE_OFF 0 1607adfc5217SJeff Kirsher #define BNX2X_DCB_STATE_ON 1 1608adfc5217SJeff Kirsher 1609adfc5217SJeff Kirsher /* DCBX engine mode */ 1610adfc5217SJeff Kirsher int dcbx_enabled; 1611adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_OFF 0 1612adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1613adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1614adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_INVALID (-1) 1615adfc5217SJeff Kirsher 1616adfc5217SJeff Kirsher bool dcbx_mode_uset; 1617adfc5217SJeff Kirsher 1618adfc5217SJeff Kirsher struct bnx2x_config_dcbx_params dcbx_config_params; 1619adfc5217SJeff Kirsher struct bnx2x_dcbx_port_params dcbx_port_params; 1620adfc5217SJeff Kirsher int dcb_version; 1621adfc5217SJeff Kirsher 1622adfc5217SJeff Kirsher /* CAM credit pools */ 1623adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj macs_pool; 1624adfc5217SJeff Kirsher 1625adfc5217SJeff Kirsher /* RX_MODE object */ 1626adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj rx_mode_obj; 1627adfc5217SJeff Kirsher 1628adfc5217SJeff Kirsher /* MCAST object */ 1629adfc5217SJeff Kirsher struct bnx2x_mcast_obj mcast_obj; 1630adfc5217SJeff Kirsher 1631adfc5217SJeff Kirsher /* RSS configuration object */ 1632adfc5217SJeff Kirsher struct bnx2x_rss_config_obj rss_conf_obj; 1633adfc5217SJeff Kirsher 1634adfc5217SJeff Kirsher /* Function State controlling object */ 1635adfc5217SJeff Kirsher struct bnx2x_func_sp_obj func_obj; 1636adfc5217SJeff Kirsher 1637adfc5217SJeff Kirsher unsigned long sp_state; 1638adfc5217SJeff Kirsher 1639adfc5217SJeff Kirsher /* operation indication for the sp_rtnl task */ 1640adfc5217SJeff Kirsher unsigned long sp_rtnl_state; 1641adfc5217SJeff Kirsher 1642adfc5217SJeff Kirsher /* DCBX Negotation results */ 1643adfc5217SJeff Kirsher struct dcbx_features dcbx_local_feat; 1644adfc5217SJeff Kirsher u32 dcbx_error; 1645adfc5217SJeff Kirsher 1646adfc5217SJeff Kirsher #ifdef BCM_DCBNL 1647adfc5217SJeff Kirsher struct dcbx_features dcbx_remote_feat; 1648adfc5217SJeff Kirsher u32 dcbx_remote_flags; 1649adfc5217SJeff Kirsher #endif 1650a3348722SBarak Witkowski /* AFEX: store default vlan used */ 1651a3348722SBarak Witkowski int afex_def_vlan_tag; 1652a3348722SBarak Witkowski enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1653adfc5217SJeff Kirsher u32 pending_max; 1654adfc5217SJeff Kirsher 1655adfc5217SJeff Kirsher /* multiple tx classes of service */ 1656adfc5217SJeff Kirsher u8 max_cos; 1657adfc5217SJeff Kirsher 1658adfc5217SJeff Kirsher /* priority to cos mapping */ 1659adfc5217SJeff Kirsher u8 prio_to_cos[8]; 1660adfc5217SJeff Kirsher }; 1661adfc5217SJeff Kirsher 1662adfc5217SJeff Kirsher /* Tx queues may be less or equal to Rx queues */ 1663adfc5217SJeff Kirsher extern int num_queues; 1664adfc5217SJeff Kirsher #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 166555c11941SMerav Sicron #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 166665565884SMerav Sicron #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 166755c11941SMerav Sicron (bp)->num_cnic_queues) 1668adfc5217SJeff Kirsher #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1669adfc5217SJeff Kirsher 1670adfc5217SJeff Kirsher #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1671adfc5217SJeff Kirsher 1672adfc5217SJeff Kirsher #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1673adfc5217SJeff Kirsher /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1674adfc5217SJeff Kirsher 1675adfc5217SJeff Kirsher #define RSS_IPV4_CAP_MASK \ 1676adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1677adfc5217SJeff Kirsher 1678adfc5217SJeff Kirsher #define RSS_IPV4_TCP_CAP_MASK \ 1679adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1680adfc5217SJeff Kirsher 1681adfc5217SJeff Kirsher #define RSS_IPV6_CAP_MASK \ 1682adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1683adfc5217SJeff Kirsher 1684adfc5217SJeff Kirsher #define RSS_IPV6_TCP_CAP_MASK \ 1685adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1686adfc5217SJeff Kirsher 1687adfc5217SJeff Kirsher /* func init flags */ 1688adfc5217SJeff Kirsher #define FUNC_FLG_RSS 0x0001 1689adfc5217SJeff Kirsher #define FUNC_FLG_STATS 0x0002 1690adfc5217SJeff Kirsher /* removed FUNC_FLG_UNMATCHED 0x0004 */ 1691adfc5217SJeff Kirsher #define FUNC_FLG_TPA 0x0008 1692adfc5217SJeff Kirsher #define FUNC_FLG_SPQ 0x0010 1693adfc5217SJeff Kirsher #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1694adfc5217SJeff Kirsher 1695adfc5217SJeff Kirsher 1696adfc5217SJeff Kirsher struct bnx2x_func_init_params { 1697adfc5217SJeff Kirsher /* dma */ 1698adfc5217SJeff Kirsher dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1699adfc5217SJeff Kirsher dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1700adfc5217SJeff Kirsher 1701adfc5217SJeff Kirsher u16 func_flgs; 1702adfc5217SJeff Kirsher u16 func_id; /* abs fid */ 1703adfc5217SJeff Kirsher u16 pf_id; 1704adfc5217SJeff Kirsher u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1705adfc5217SJeff Kirsher }; 1706adfc5217SJeff Kirsher 170755c11941SMerav Sicron #define for_each_cnic_queue(bp, var) \ 170855c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 170955c11941SMerav Sicron (var)++) \ 171055c11941SMerav Sicron if (skip_queue(bp, var)) \ 171155c11941SMerav Sicron continue; \ 171255c11941SMerav Sicron else 171355c11941SMerav Sicron 1714adfc5217SJeff Kirsher #define for_each_eth_queue(bp, var) \ 1715adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1716adfc5217SJeff Kirsher 1717adfc5217SJeff Kirsher #define for_each_nondefault_eth_queue(bp, var) \ 1718adfc5217SJeff Kirsher for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1719adfc5217SJeff Kirsher 1720adfc5217SJeff Kirsher #define for_each_queue(bp, var) \ 1721adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1722adfc5217SJeff Kirsher if (skip_queue(bp, var)) \ 1723adfc5217SJeff Kirsher continue; \ 1724adfc5217SJeff Kirsher else 1725adfc5217SJeff Kirsher 1726adfc5217SJeff Kirsher /* Skip forwarding FP */ 172755c11941SMerav Sicron #define for_each_valid_rx_queue(bp, var) \ 172855c11941SMerav Sicron for ((var) = 0; \ 172955c11941SMerav Sicron (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 173055c11941SMerav Sicron BNX2X_NUM_ETH_QUEUES(bp)); \ 173155c11941SMerav Sicron (var)++) \ 173255c11941SMerav Sicron if (skip_rx_queue(bp, var)) \ 173355c11941SMerav Sicron continue; \ 173455c11941SMerav Sicron else 173555c11941SMerav Sicron 173655c11941SMerav Sicron #define for_each_rx_queue_cnic(bp, var) \ 173755c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 173855c11941SMerav Sicron (var)++) \ 173955c11941SMerav Sicron if (skip_rx_queue(bp, var)) \ 174055c11941SMerav Sicron continue; \ 174155c11941SMerav Sicron else 174255c11941SMerav Sicron 1743adfc5217SJeff Kirsher #define for_each_rx_queue(bp, var) \ 1744adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1745adfc5217SJeff Kirsher if (skip_rx_queue(bp, var)) \ 1746adfc5217SJeff Kirsher continue; \ 1747adfc5217SJeff Kirsher else 1748adfc5217SJeff Kirsher 1749adfc5217SJeff Kirsher /* Skip OOO FP */ 175055c11941SMerav Sicron #define for_each_valid_tx_queue(bp, var) \ 175155c11941SMerav Sicron for ((var) = 0; \ 175255c11941SMerav Sicron (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 175355c11941SMerav Sicron BNX2X_NUM_ETH_QUEUES(bp)); \ 175455c11941SMerav Sicron (var)++) \ 175555c11941SMerav Sicron if (skip_tx_queue(bp, var)) \ 175655c11941SMerav Sicron continue; \ 175755c11941SMerav Sicron else 175855c11941SMerav Sicron 175955c11941SMerav Sicron #define for_each_tx_queue_cnic(bp, var) \ 176055c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 176155c11941SMerav Sicron (var)++) \ 176255c11941SMerav Sicron if (skip_tx_queue(bp, var)) \ 176355c11941SMerav Sicron continue; \ 176455c11941SMerav Sicron else 176555c11941SMerav Sicron 1766adfc5217SJeff Kirsher #define for_each_tx_queue(bp, var) \ 1767adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1768adfc5217SJeff Kirsher if (skip_tx_queue(bp, var)) \ 1769adfc5217SJeff Kirsher continue; \ 1770adfc5217SJeff Kirsher else 1771adfc5217SJeff Kirsher 1772adfc5217SJeff Kirsher #define for_each_nondefault_queue(bp, var) \ 1773adfc5217SJeff Kirsher for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1774adfc5217SJeff Kirsher if (skip_queue(bp, var)) \ 1775adfc5217SJeff Kirsher continue; \ 1776adfc5217SJeff Kirsher else 1777adfc5217SJeff Kirsher 1778adfc5217SJeff Kirsher #define for_each_cos_in_tx_queue(fp, var) \ 1779adfc5217SJeff Kirsher for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1780adfc5217SJeff Kirsher 1781adfc5217SJeff Kirsher /* skip rx queue 1782adfc5217SJeff Kirsher * if FCOE l2 support is disabled and this is the fcoe L2 queue 1783adfc5217SJeff Kirsher */ 1784adfc5217SJeff Kirsher #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1785adfc5217SJeff Kirsher 1786adfc5217SJeff Kirsher /* skip tx queue 1787adfc5217SJeff Kirsher * if FCOE l2 support is disabled and this is the fcoe L2 queue 1788adfc5217SJeff Kirsher */ 1789adfc5217SJeff Kirsher #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1790adfc5217SJeff Kirsher 1791adfc5217SJeff Kirsher #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1792adfc5217SJeff Kirsher 1793adfc5217SJeff Kirsher 1794adfc5217SJeff Kirsher 1795adfc5217SJeff Kirsher 1796adfc5217SJeff Kirsher /** 1797adfc5217SJeff Kirsher * bnx2x_set_mac_one - configure a single MAC address 1798adfc5217SJeff Kirsher * 1799adfc5217SJeff Kirsher * @bp: driver handle 1800adfc5217SJeff Kirsher * @mac: MAC to configure 1801adfc5217SJeff Kirsher * @obj: MAC object handle 1802adfc5217SJeff Kirsher * @set: if 'true' add a new MAC, otherwise - delete 1803adfc5217SJeff Kirsher * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1804adfc5217SJeff Kirsher * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1805adfc5217SJeff Kirsher * 1806adfc5217SJeff Kirsher * Configures one MAC according to provided parameters or continues the 1807adfc5217SJeff Kirsher * execution of previously scheduled commands if RAMROD_CONT is set in 1808adfc5217SJeff Kirsher * ramrod_flags. 1809adfc5217SJeff Kirsher * 1810adfc5217SJeff Kirsher * Returns zero if operation has successfully completed, a positive value if the 1811adfc5217SJeff Kirsher * operation has been successfully scheduled and a negative - if a requested 1812adfc5217SJeff Kirsher * operations has failed. 1813adfc5217SJeff Kirsher */ 1814adfc5217SJeff Kirsher int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1815adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *obj, bool set, 1816adfc5217SJeff Kirsher int mac_type, unsigned long *ramrod_flags); 1817adfc5217SJeff Kirsher /** 1818adfc5217SJeff Kirsher * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1819adfc5217SJeff Kirsher * 1820adfc5217SJeff Kirsher * @bp: driver handle 1821adfc5217SJeff Kirsher * @mac_obj: MAC object handle 1822adfc5217SJeff Kirsher * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 1823adfc5217SJeff Kirsher * @wait_for_comp: if 'true' block until completion 1824adfc5217SJeff Kirsher * 1825adfc5217SJeff Kirsher * Deletes all MACs of the specific type (e.g. ETH, UC list). 1826adfc5217SJeff Kirsher * 1827adfc5217SJeff Kirsher * Returns zero if operation has successfully completed, a positive value if the 1828adfc5217SJeff Kirsher * operation has been successfully scheduled and a negative - if a requested 1829adfc5217SJeff Kirsher * operations has failed. 1830adfc5217SJeff Kirsher */ 1831adfc5217SJeff Kirsher int bnx2x_del_all_macs(struct bnx2x *bp, 1832adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj, 1833adfc5217SJeff Kirsher int mac_type, bool wait_for_comp); 1834adfc5217SJeff Kirsher 1835adfc5217SJeff Kirsher /* Init Function API */ 1836adfc5217SJeff Kirsher void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 1837adfc5217SJeff Kirsher int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 1838adfc5217SJeff Kirsher int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1839adfc5217SJeff Kirsher int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 1840adfc5217SJeff Kirsher int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1841adfc5217SJeff Kirsher void bnx2x_read_mf_cfg(struct bnx2x *bp); 1842adfc5217SJeff Kirsher 1843adfc5217SJeff Kirsher 1844adfc5217SJeff Kirsher /* dmae */ 1845adfc5217SJeff Kirsher void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 1846adfc5217SJeff Kirsher void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 1847adfc5217SJeff Kirsher u32 len32); 1848adfc5217SJeff Kirsher void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 1849adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 1850adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 1851adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 1852adfc5217SJeff Kirsher bool with_comp, u8 comp_type); 1853adfc5217SJeff Kirsher 1854adfc5217SJeff Kirsher 1855adfc5217SJeff Kirsher void bnx2x_calc_fc_adv(struct bnx2x *bp); 1856adfc5217SJeff Kirsher int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 1857adfc5217SJeff Kirsher u32 data_hi, u32 data_lo, int cmd_type); 1858adfc5217SJeff Kirsher void bnx2x_update_coalesce(struct bnx2x *bp); 1859adfc5217SJeff Kirsher int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 1860adfc5217SJeff Kirsher 1861adfc5217SJeff Kirsher static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 1862adfc5217SJeff Kirsher int wait) 1863adfc5217SJeff Kirsher { 1864adfc5217SJeff Kirsher u32 val; 1865adfc5217SJeff Kirsher 1866adfc5217SJeff Kirsher do { 1867adfc5217SJeff Kirsher val = REG_RD(bp, reg); 1868adfc5217SJeff Kirsher if (val == expected) 1869adfc5217SJeff Kirsher break; 1870adfc5217SJeff Kirsher ms -= wait; 1871adfc5217SJeff Kirsher msleep(wait); 1872adfc5217SJeff Kirsher 1873adfc5217SJeff Kirsher } while (ms > 0); 1874adfc5217SJeff Kirsher 1875adfc5217SJeff Kirsher return val; 1876adfc5217SJeff Kirsher } 1877adfc5217SJeff Kirsher 1878adfc5217SJeff Kirsher #define BNX2X_ILT_ZALLOC(x, y, size) \ 1879adfc5217SJeff Kirsher do { \ 1880adfc5217SJeff Kirsher x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 1881adfc5217SJeff Kirsher if (x) \ 1882adfc5217SJeff Kirsher memset(x, 0, size); \ 1883adfc5217SJeff Kirsher } while (0) 1884adfc5217SJeff Kirsher 1885adfc5217SJeff Kirsher #define BNX2X_ILT_FREE(x, y, size) \ 1886adfc5217SJeff Kirsher do { \ 1887adfc5217SJeff Kirsher if (x) { \ 1888adfc5217SJeff Kirsher dma_free_coherent(&bp->pdev->dev, size, x, y); \ 1889adfc5217SJeff Kirsher x = NULL; \ 1890adfc5217SJeff Kirsher y = 0; \ 1891adfc5217SJeff Kirsher } \ 1892adfc5217SJeff Kirsher } while (0) 1893adfc5217SJeff Kirsher 1894adfc5217SJeff Kirsher #define ILOG2(x) (ilog2((x))) 1895adfc5217SJeff Kirsher 1896adfc5217SJeff Kirsher #define ILT_NUM_PAGE_ENTRIES (3072) 1897adfc5217SJeff Kirsher /* In 57710/11 we use whole table since we have 8 func 1898adfc5217SJeff Kirsher * In 57712 we have only 4 func, but use same size per func, then only half of 1899adfc5217SJeff Kirsher * the table in use 1900adfc5217SJeff Kirsher */ 1901adfc5217SJeff Kirsher #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 1902adfc5217SJeff Kirsher 1903adfc5217SJeff Kirsher #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 1904adfc5217SJeff Kirsher /* 1905adfc5217SJeff Kirsher * the phys address is shifted right 12 bits and has an added 1906adfc5217SJeff Kirsher * 1=valid bit added to the 53rd bit 1907adfc5217SJeff Kirsher * then since this is a wide register(TM) 1908adfc5217SJeff Kirsher * we split it into two 32 bit writes 1909adfc5217SJeff Kirsher */ 1910adfc5217SJeff Kirsher #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 1911adfc5217SJeff Kirsher #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 1912adfc5217SJeff Kirsher 1913adfc5217SJeff Kirsher /* load/unload mode */ 1914adfc5217SJeff Kirsher #define LOAD_NORMAL 0 1915adfc5217SJeff Kirsher #define LOAD_OPEN 1 1916adfc5217SJeff Kirsher #define LOAD_DIAG 2 19178970b2e4SMerav Sicron #define LOAD_LOOPBACK_EXT 3 1918adfc5217SJeff Kirsher #define UNLOAD_NORMAL 0 1919adfc5217SJeff Kirsher #define UNLOAD_CLOSE 1 1920adfc5217SJeff Kirsher #define UNLOAD_RECOVERY 2 1921adfc5217SJeff Kirsher 1922adfc5217SJeff Kirsher 1923adfc5217SJeff Kirsher /* DMAE command defines */ 1924adfc5217SJeff Kirsher #define DMAE_TIMEOUT -1 1925adfc5217SJeff Kirsher #define DMAE_PCI_ERROR -2 /* E2 and onward */ 1926adfc5217SJeff Kirsher #define DMAE_NOT_RDY -3 1927adfc5217SJeff Kirsher #define DMAE_PCI_ERR_FLAG 0x80000000 1928adfc5217SJeff Kirsher 1929adfc5217SJeff Kirsher #define DMAE_SRC_PCI 0 1930adfc5217SJeff Kirsher #define DMAE_SRC_GRC 1 1931adfc5217SJeff Kirsher 1932adfc5217SJeff Kirsher #define DMAE_DST_NONE 0 1933adfc5217SJeff Kirsher #define DMAE_DST_PCI 1 1934adfc5217SJeff Kirsher #define DMAE_DST_GRC 2 1935adfc5217SJeff Kirsher 1936adfc5217SJeff Kirsher #define DMAE_COMP_PCI 0 1937adfc5217SJeff Kirsher #define DMAE_COMP_GRC 1 1938adfc5217SJeff Kirsher 1939adfc5217SJeff Kirsher /* E2 and onward - PCI error handling in the completion */ 1940adfc5217SJeff Kirsher 1941adfc5217SJeff Kirsher #define DMAE_COMP_REGULAR 0 1942adfc5217SJeff Kirsher #define DMAE_COM_SET_ERR 1 1943adfc5217SJeff Kirsher 1944adfc5217SJeff Kirsher #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 1945adfc5217SJeff Kirsher DMAE_COMMAND_SRC_SHIFT) 1946adfc5217SJeff Kirsher #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 1947adfc5217SJeff Kirsher DMAE_COMMAND_SRC_SHIFT) 1948adfc5217SJeff Kirsher 1949adfc5217SJeff Kirsher #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 1950adfc5217SJeff Kirsher DMAE_COMMAND_DST_SHIFT) 1951adfc5217SJeff Kirsher #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 1952adfc5217SJeff Kirsher DMAE_COMMAND_DST_SHIFT) 1953adfc5217SJeff Kirsher 1954adfc5217SJeff Kirsher #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 1955adfc5217SJeff Kirsher DMAE_COMMAND_C_DST_SHIFT) 1956adfc5217SJeff Kirsher #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 1957adfc5217SJeff Kirsher DMAE_COMMAND_C_DST_SHIFT) 1958adfc5217SJeff Kirsher 1959adfc5217SJeff Kirsher #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 1960adfc5217SJeff Kirsher 1961adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 1962adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 1963adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 1964adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 1965adfc5217SJeff Kirsher 1966adfc5217SJeff Kirsher #define DMAE_CMD_PORT_0 0 1967adfc5217SJeff Kirsher #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 1968adfc5217SJeff Kirsher 1969adfc5217SJeff Kirsher #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 1970adfc5217SJeff Kirsher #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 1971adfc5217SJeff Kirsher #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 1972adfc5217SJeff Kirsher 1973adfc5217SJeff Kirsher #define DMAE_SRC_PF 0 1974adfc5217SJeff Kirsher #define DMAE_SRC_VF 1 1975adfc5217SJeff Kirsher 1976adfc5217SJeff Kirsher #define DMAE_DST_PF 0 1977adfc5217SJeff Kirsher #define DMAE_DST_VF 1 1978adfc5217SJeff Kirsher 1979adfc5217SJeff Kirsher #define DMAE_C_SRC 0 1980adfc5217SJeff Kirsher #define DMAE_C_DST 1 1981adfc5217SJeff Kirsher 1982adfc5217SJeff Kirsher #define DMAE_LEN32_RD_MAX 0x80 1983adfc5217SJeff Kirsher #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 1984adfc5217SJeff Kirsher 1985adfc5217SJeff Kirsher #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 1986adfc5217SJeff Kirsher indicates eror */ 1987adfc5217SJeff Kirsher 1988adfc5217SJeff Kirsher #define MAX_DMAE_C_PER_PORT 8 1989adfc5217SJeff Kirsher #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 19908decf868SDavid S. Miller BP_VN(bp)) 1991adfc5217SJeff Kirsher #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1992adfc5217SJeff Kirsher E1HVN_MAX) 1993adfc5217SJeff Kirsher 1994adfc5217SJeff Kirsher /* PCIE link and speed */ 1995adfc5217SJeff Kirsher #define PCICFG_LINK_WIDTH 0x1f00000 1996adfc5217SJeff Kirsher #define PCICFG_LINK_WIDTH_SHIFT 20 1997adfc5217SJeff Kirsher #define PCICFG_LINK_SPEED 0xf0000 1998adfc5217SJeff Kirsher #define PCICFG_LINK_SPEED_SHIFT 16 1999adfc5217SJeff Kirsher 2000cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS_SF 7 2001cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS_MF 3 2002cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 2003cf2c1df6SMerav Sicron BNX2X_NUM_TESTS_SF) 2004adfc5217SJeff Kirsher 2005adfc5217SJeff Kirsher #define BNX2X_PHY_LOOPBACK 0 2006adfc5217SJeff Kirsher #define BNX2X_MAC_LOOPBACK 1 20078970b2e4SMerav Sicron #define BNX2X_EXT_LOOPBACK 2 2008adfc5217SJeff Kirsher #define BNX2X_PHY_LOOPBACK_FAILED 1 2009adfc5217SJeff Kirsher #define BNX2X_MAC_LOOPBACK_FAILED 2 20108970b2e4SMerav Sicron #define BNX2X_EXT_LOOPBACK_FAILED 3 2011adfc5217SJeff Kirsher #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2012adfc5217SJeff Kirsher BNX2X_PHY_LOOPBACK_FAILED) 2013adfc5217SJeff Kirsher 2014adfc5217SJeff Kirsher 2015adfc5217SJeff Kirsher #define STROM_ASSERT_ARRAY_SIZE 50 2016adfc5217SJeff Kirsher 2017adfc5217SJeff Kirsher 2018adfc5217SJeff Kirsher /* must be used on a CID before placing it on a HW ring */ 2019adfc5217SJeff Kirsher #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 20208decf868SDavid S. Miller (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2021adfc5217SJeff Kirsher (x)) 2022adfc5217SJeff Kirsher 2023adfc5217SJeff Kirsher #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2024adfc5217SJeff Kirsher #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2025adfc5217SJeff Kirsher 2026adfc5217SJeff Kirsher 2027adfc5217SJeff Kirsher #define BNX2X_BTR 4 2028adfc5217SJeff Kirsher #define MAX_SPQ_PENDING 8 2029adfc5217SJeff Kirsher 2030adfc5217SJeff Kirsher /* CMNG constants, as derived from system spec calculations */ 2031adfc5217SJeff Kirsher /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2032adfc5217SJeff Kirsher #define DEF_MIN_RATE 100 2033adfc5217SJeff Kirsher /* resolution of the rate shaping timer - 400 usec */ 2034adfc5217SJeff Kirsher #define RS_PERIODIC_TIMEOUT_USEC 400 2035adfc5217SJeff Kirsher /* number of bytes in single QM arbitration cycle - 2036adfc5217SJeff Kirsher * coefficient for calculating the fairness timer */ 2037adfc5217SJeff Kirsher #define QM_ARB_BYTES 160000 2038adfc5217SJeff Kirsher /* resolution of Min algorithm 1:100 */ 2039adfc5217SJeff Kirsher #define MIN_RES 100 2040adfc5217SJeff Kirsher /* how many bytes above threshold for the minimal credit of Min algorithm*/ 2041adfc5217SJeff Kirsher #define MIN_ABOVE_THRESH 32768 2042adfc5217SJeff Kirsher /* Fairness algorithm integration time coefficient - 2043adfc5217SJeff Kirsher * for calculating the actual Tfair */ 2044adfc5217SJeff Kirsher #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2045adfc5217SJeff Kirsher /* Memory of fairness algorithm . 2 cycles */ 2046adfc5217SJeff Kirsher #define FAIR_MEM 2 2047adfc5217SJeff Kirsher 2048adfc5217SJeff Kirsher 2049adfc5217SJeff Kirsher #define ATTN_NIG_FOR_FUNC (1L << 8) 2050adfc5217SJeff Kirsher #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2051adfc5217SJeff Kirsher #define GPIO_2_FUNC (1L << 10) 2052adfc5217SJeff Kirsher #define GPIO_3_FUNC (1L << 11) 2053adfc5217SJeff Kirsher #define GPIO_4_FUNC (1L << 12) 2054adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_1 (1L << 13) 2055adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_2 (1L << 14) 2056adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_3 (1L << 15) 2057adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_4 (1L << 13) 2058adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_5 (1L << 14) 2059adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_6 (1L << 15) 2060adfc5217SJeff Kirsher 2061adfc5217SJeff Kirsher #define ATTN_HARD_WIRED_MASK 0xff00 2062adfc5217SJeff Kirsher #define ATTENTION_ID 4 2063adfc5217SJeff Kirsher 2064adfc5217SJeff Kirsher 2065adfc5217SJeff Kirsher /* stuff added to make the code fit 80Col */ 2066adfc5217SJeff Kirsher 2067adfc5217SJeff Kirsher #define BNX2X_PMF_LINK_ASSERT \ 2068adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2069adfc5217SJeff Kirsher 2070adfc5217SJeff Kirsher #define BNX2X_MC_ASSERT_BITS \ 2071adfc5217SJeff Kirsher (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2072adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2073adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2074adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2075adfc5217SJeff Kirsher 2076adfc5217SJeff Kirsher #define BNX2X_MCP_ASSERT \ 2077adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2078adfc5217SJeff Kirsher 2079adfc5217SJeff Kirsher #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2080adfc5217SJeff Kirsher #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2081adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2082adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2083adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2084adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2085adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2086adfc5217SJeff Kirsher 2087adfc5217SJeff Kirsher #define HW_INTERRUT_ASSERT_SET_0 \ 2088adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2089adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2090adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2091adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2092adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2093adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2094adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2095adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2096adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2097adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2098adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2099adfc5217SJeff Kirsher #define HW_INTERRUT_ASSERT_SET_1 \ 2100adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2101adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2102adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2103adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2104adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2105adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2106adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2107adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2108adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2109adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2110adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2111adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2112adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2113adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2114adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2115adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2116adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2117adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2118adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2119adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2120adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2121adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2122adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2123adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2124adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2125adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2126adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2127adfc5217SJeff Kirsher #define HW_INTERRUT_ASSERT_SET_2 \ 2128adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2129adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2130adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2131adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2132adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2133adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2134adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2135adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2136adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2137adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2138adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2139adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2140adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2141adfc5217SJeff Kirsher 2142adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2143adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2144adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2145adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2146adfc5217SJeff Kirsher 2147adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2148adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2149adfc5217SJeff Kirsher 2150adfc5217SJeff Kirsher #define MULTI_MASK 0x7f 2151adfc5217SJeff Kirsher 2152adfc5217SJeff Kirsher 2153adfc5217SJeff Kirsher #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2154adfc5217SJeff Kirsher #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2155adfc5217SJeff Kirsher #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2156adfc5217SJeff Kirsher #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2157adfc5217SJeff Kirsher 2158adfc5217SJeff Kirsher #define DEF_USB_IGU_INDEX_OFF \ 2159adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_u, igu_index) 2160adfc5217SJeff Kirsher #define DEF_CSB_IGU_INDEX_OFF \ 2161adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_c, igu_index) 2162adfc5217SJeff Kirsher #define DEF_XSB_IGU_INDEX_OFF \ 2163adfc5217SJeff Kirsher offsetof(struct xstorm_def_status_block, igu_index) 2164adfc5217SJeff Kirsher #define DEF_TSB_IGU_INDEX_OFF \ 2165adfc5217SJeff Kirsher offsetof(struct tstorm_def_status_block, igu_index) 2166adfc5217SJeff Kirsher 2167adfc5217SJeff Kirsher #define DEF_USB_SEGMENT_OFF \ 2168adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_u, segment) 2169adfc5217SJeff Kirsher #define DEF_CSB_SEGMENT_OFF \ 2170adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_c, segment) 2171adfc5217SJeff Kirsher #define DEF_XSB_SEGMENT_OFF \ 2172adfc5217SJeff Kirsher offsetof(struct xstorm_def_status_block, segment) 2173adfc5217SJeff Kirsher #define DEF_TSB_SEGMENT_OFF \ 2174adfc5217SJeff Kirsher offsetof(struct tstorm_def_status_block, segment) 2175adfc5217SJeff Kirsher 2176adfc5217SJeff Kirsher #define BNX2X_SP_DSB_INDEX \ 2177adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 2178adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2179adfc5217SJeff Kirsher 2180adfc5217SJeff Kirsher #define SET_FLAG(value, mask, flag) \ 2181adfc5217SJeff Kirsher do {\ 2182adfc5217SJeff Kirsher (value) &= ~(mask);\ 2183adfc5217SJeff Kirsher (value) |= ((flag) << (mask##_SHIFT));\ 2184adfc5217SJeff Kirsher } while (0) 2185adfc5217SJeff Kirsher 2186adfc5217SJeff Kirsher #define GET_FLAG(value, mask) \ 2187adfc5217SJeff Kirsher (((value) & (mask)) >> (mask##_SHIFT)) 2188adfc5217SJeff Kirsher 2189adfc5217SJeff Kirsher #define GET_FIELD(value, fname) \ 2190adfc5217SJeff Kirsher (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2191adfc5217SJeff Kirsher 2192adfc5217SJeff Kirsher #define CAM_IS_INVALID(x) \ 2193adfc5217SJeff Kirsher (GET_FLAG(x.flags, \ 2194adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2195adfc5217SJeff Kirsher (T_ETH_MAC_COMMAND_INVALIDATE)) 2196adfc5217SJeff Kirsher 2197adfc5217SJeff Kirsher /* Number of u32 elements in MC hash array */ 2198adfc5217SJeff Kirsher #define MC_HASH_SIZE 8 2199adfc5217SJeff Kirsher #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2200adfc5217SJeff Kirsher TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2201adfc5217SJeff Kirsher 2202adfc5217SJeff Kirsher 2203adfc5217SJeff Kirsher #ifndef PXP2_REG_PXP2_INT_STS 2204adfc5217SJeff Kirsher #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2205adfc5217SJeff Kirsher #endif 2206adfc5217SJeff Kirsher 2207adfc5217SJeff Kirsher #ifndef ETH_MAX_RX_CLIENTS_E2 2208adfc5217SJeff Kirsher #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2209adfc5217SJeff Kirsher #endif 2210adfc5217SJeff Kirsher 2211adfc5217SJeff Kirsher #define BNX2X_VPD_LEN 128 2212adfc5217SJeff Kirsher #define VENDOR_ID_LEN 4 2213adfc5217SJeff Kirsher 2214be1f1ffaSAriel Elior #define VF_ACQUIRE_THRESH 3 2215be1f1ffaSAriel Elior #define VF_ACQUIRE_MAC_FILTERS 1 2216be1f1ffaSAriel Elior #define VF_ACQUIRE_MC_FILTERS 10 2217be1f1ffaSAriel Elior 2218be1f1ffaSAriel Elior #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2219be1f1ffaSAriel Elior (!((me_reg) & ME_REG_VF_ERR))) 2220be1f1ffaSAriel Elior int bnx2x_get_vf_id(struct bnx2x *bp, u32 *vf_id); 2221be1f1ffaSAriel Elior int bnx2x_send_msg2pf(struct bnx2x *bp, u8 *done, dma_addr_t msg_mapping); 2222be1f1ffaSAriel Elior int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count); 2223adfc5217SJeff Kirsher /* Congestion management fairness mode */ 2224adfc5217SJeff Kirsher #define CMNG_FNS_NONE 0 2225adfc5217SJeff Kirsher #define CMNG_FNS_MINMAX 1 2226adfc5217SJeff Kirsher 2227adfc5217SJeff Kirsher #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2228adfc5217SJeff Kirsher #define HC_SEG_ACCESS_ATTN 4 2229adfc5217SJeff Kirsher #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2230adfc5217SJeff Kirsher 2231adfc5217SJeff Kirsher static const u32 dmae_reg_go_c[] = { 2232adfc5217SJeff Kirsher DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2233adfc5217SJeff Kirsher DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2234adfc5217SJeff Kirsher DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2235adfc5217SJeff Kirsher DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2236adfc5217SJeff Kirsher }; 2237adfc5217SJeff Kirsher 2238adfc5217SJeff Kirsher void bnx2x_set_ethtool_ops(struct net_device *netdev); 2239adfc5217SJeff Kirsher void bnx2x_notify_link_changed(struct bnx2x *bp); 2240614c76dfSDmitry Kravkov 2241614c76dfSDmitry Kravkov 22429e62e912SDmitry Kravkov #define BNX2X_MF_SD_PROTOCOL(bp) \ 2243614c76dfSDmitry Kravkov ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2244614c76dfSDmitry Kravkov 22459e62e912SDmitry Kravkov #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 22469e62e912SDmitry Kravkov (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2247614c76dfSDmitry Kravkov 22489e62e912SDmitry Kravkov #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 22499e62e912SDmitry Kravkov (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 22509e62e912SDmitry Kravkov 22519e62e912SDmitry Kravkov #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 22529e62e912SDmitry Kravkov #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 22539e62e912SDmitry Kravkov 2254a3348722SBarak Witkowski #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2255a3348722SBarak Witkowski MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2256a3348722SBarak Witkowski 2257a3348722SBarak Witkowski #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 22589e62e912SDmitry Kravkov #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 22599e62e912SDmitry Kravkov (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 22609e62e912SDmitry Kravkov BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2261614c76dfSDmitry Kravkov 226255c11941SMerav Sicron enum { 226355c11941SMerav Sicron SWITCH_UPDATE, 226455c11941SMerav Sicron AFEX_UPDATE, 226555c11941SMerav Sicron }; 226655c11941SMerav Sicron 226755c11941SMerav Sicron #define NUM_MACS 8 2268a3348722SBarak Witkowski 2269adfc5217SJeff Kirsher #endif /* bnx2x.h */ 2270