14ad79e13SYuval Mintz /* bnx2x.h: QLogic Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2007-2013 Broadcom Corporation 44ad79e13SYuval Mintz * Copyright (c) 2014 QLogic Corporation 54ad79e13SYuval Mintz * All rights reserved 6adfc5217SJeff Kirsher * 7adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 8adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 9adfc5217SJeff Kirsher * the Free Software Foundation. 10adfc5217SJeff Kirsher * 1108f6dd89SAriel Elior * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12adfc5217SJeff Kirsher * Written by: Eliezer Tamir 13adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 14adfc5217SJeff Kirsher */ 15adfc5217SJeff Kirsher 16adfc5217SJeff Kirsher #ifndef BNX2X_H 17adfc5217SJeff Kirsher #define BNX2X_H 18290ca2bbSAriel Elior 19290ca2bbSAriel Elior #include <linux/pci.h> 20adfc5217SJeff Kirsher #include <linux/netdevice.h> 21adfc5217SJeff Kirsher #include <linux/dma-mapping.h> 22adfc5217SJeff Kirsher #include <linux/types.h> 23290ca2bbSAriel Elior #include <linux/pci_regs.h> 24adfc5217SJeff Kirsher 25eeed018cSMichal Kalderon #include <linux/ptp_clock_kernel.h> 26eeed018cSMichal Kalderon #include <linux/net_tstamp.h> 2774d23cc7SRichard Cochran #include <linux/timecounter.h> 28eeed018cSMichal Kalderon 29adfc5217SJeff Kirsher /* compilation time flags */ 30adfc5217SJeff Kirsher 31adfc5217SJeff Kirsher /* define this to make the driver freeze on error to allow getting debug info 32adfc5217SJeff Kirsher * (you will need to reboot afterwards) */ 33adfc5217SJeff Kirsher /* #define BNX2X_STOP_ON_ERROR */ 34adfc5217SJeff Kirsher 3562604124SYuval Mintz #define DRV_MODULE_VERSION "1.710.51-0" 363156b8ebSDmitry Kravkov #define DRV_MODULE_RELDATE "2014/02/10" 37adfc5217SJeff Kirsher #define BNX2X_BC_VER 0x040200 38adfc5217SJeff Kirsher 39adfc5217SJeff Kirsher #if defined(CONFIG_DCB) 40adfc5217SJeff Kirsher #define BCM_DCBNL 41adfc5217SJeff Kirsher #endif 42b475d78fSYuval Mintz 43b475d78fSYuval Mintz #include "bnx2x_hsi.h" 44b475d78fSYuval Mintz 45adfc5217SJeff Kirsher #include "../cnic_if.h" 46adfc5217SJeff Kirsher 4755c11941SMerav Sicron #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 48adfc5217SJeff Kirsher 49adfc5217SJeff Kirsher #include <linux/mdio.h> 50adfc5217SJeff Kirsher 51adfc5217SJeff Kirsher #include "bnx2x_reg.h" 52adfc5217SJeff Kirsher #include "bnx2x_fw_defs.h" 532e499d3cSBarak Witkowski #include "bnx2x_mfw_req.h" 54adfc5217SJeff Kirsher #include "bnx2x_link.h" 55adfc5217SJeff Kirsher #include "bnx2x_sp.h" 56adfc5217SJeff Kirsher #include "bnx2x_dcb.h" 57adfc5217SJeff Kirsher #include "bnx2x_stats.h" 58be1f1ffaSAriel Elior #include "bnx2x_vfpf.h" 59adfc5217SJeff Kirsher 601ab4434cSAriel Elior enum bnx2x_int_mode { 611ab4434cSAriel Elior BNX2X_INT_MODE_MSIX, 621ab4434cSAriel Elior BNX2X_INT_MODE_INTX, 631ab4434cSAriel Elior BNX2X_INT_MODE_MSI 641ab4434cSAriel Elior }; 651ab4434cSAriel Elior 66adfc5217SJeff Kirsher /* error/debug prints */ 67adfc5217SJeff Kirsher 68adfc5217SJeff Kirsher #define DRV_MODULE_NAME "bnx2x" 69adfc5217SJeff Kirsher 70adfc5217SJeff Kirsher /* for messages that are currently off */ 7151c1a580SMerav Sicron #define BNX2X_MSG_OFF 0x0 7251c1a580SMerav Sicron #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 7351c1a580SMerav Sicron #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 7451c1a580SMerav Sicron #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 7551c1a580SMerav Sicron #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 7651c1a580SMerav Sicron #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 7751c1a580SMerav Sicron #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 7851c1a580SMerav Sicron #define BNX2X_MSG_IOV 0x0800000 79eeed018cSMichal Kalderon #define BNX2X_MSG_PTP 0x1000000 8051c1a580SMerav Sicron #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 8151c1a580SMerav Sicron #define BNX2X_MSG_ETHTOOL 0x4000000 8251c1a580SMerav Sicron #define BNX2X_MSG_DCB 0x8000000 83adfc5217SJeff Kirsher 84adfc5217SJeff Kirsher /* regular debug print */ 8576ca70faSYuval Mintz #define DP_INNER(fmt, ...) \ 86f1deab50SJoe Perches pr_notice("[%s:%d(%s)]" fmt, \ 87adfc5217SJeff Kirsher __func__, __LINE__, \ 88adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 8976ca70faSYuval Mintz ##__VA_ARGS__); 9076ca70faSYuval Mintz 9176ca70faSYuval Mintz #define DP(__mask, fmt, ...) \ 9276ca70faSYuval Mintz do { \ 9376ca70faSYuval Mintz if (unlikely(bp->msg_enable & (__mask))) \ 9476ca70faSYuval Mintz DP_INNER(fmt, ##__VA_ARGS__); \ 9576ca70faSYuval Mintz } while (0) 9676ca70faSYuval Mintz 9776ca70faSYuval Mintz #define DP_AND(__mask, fmt, ...) \ 9876ca70faSYuval Mintz do { \ 9976ca70faSYuval Mintz if (unlikely((bp->msg_enable & (__mask)) == __mask)) \ 10076ca70faSYuval Mintz DP_INNER(fmt, ##__VA_ARGS__); \ 101adfc5217SJeff Kirsher } while (0) 102adfc5217SJeff Kirsher 103f1deab50SJoe Perches #define DP_CONT(__mask, fmt, ...) \ 104adfc5217SJeff Kirsher do { \ 10551c1a580SMerav Sicron if (unlikely(bp->msg_enable & (__mask))) \ 106f1deab50SJoe Perches pr_cont(fmt, ##__VA_ARGS__); \ 107adfc5217SJeff Kirsher } while (0) 108adfc5217SJeff Kirsher 109adfc5217SJeff Kirsher /* errors debug print */ 110f1deab50SJoe Perches #define BNX2X_DBG_ERR(fmt, ...) \ 111adfc5217SJeff Kirsher do { \ 11251c1a580SMerav Sicron if (unlikely(netif_msg_probe(bp))) \ 113f1deab50SJoe Perches pr_err("[%s:%d(%s)]" fmt, \ 114adfc5217SJeff Kirsher __func__, __LINE__, \ 115adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 116f1deab50SJoe Perches ##__VA_ARGS__); \ 117adfc5217SJeff Kirsher } while (0) 118adfc5217SJeff Kirsher 119adfc5217SJeff Kirsher /* for errors (never masked) */ 120f1deab50SJoe Perches #define BNX2X_ERR(fmt, ...) \ 121adfc5217SJeff Kirsher do { \ 122f1deab50SJoe Perches pr_err("[%s:%d(%s)]" fmt, \ 123adfc5217SJeff Kirsher __func__, __LINE__, \ 124adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 125f1deab50SJoe Perches ##__VA_ARGS__); \ 126adfc5217SJeff Kirsher } while (0) 127adfc5217SJeff Kirsher 128f1deab50SJoe Perches #define BNX2X_ERROR(fmt, ...) \ 129f1deab50SJoe Perches pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 130adfc5217SJeff Kirsher 131adfc5217SJeff Kirsher /* before we have a dev->name use dev_info() */ 132f1deab50SJoe Perches #define BNX2X_DEV_INFO(fmt, ...) \ 133adfc5217SJeff Kirsher do { \ 13451c1a580SMerav Sicron if (unlikely(netif_msg_probe(bp))) \ 135f1deab50SJoe Perches dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 136adfc5217SJeff Kirsher } while (0) 137adfc5217SJeff Kirsher 138ca9bdb9bSYuval Mintz /* Error handling */ 139ca9bdb9bSYuval Mintz void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); 140adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 141f1deab50SJoe Perches #define bnx2x_panic() \ 142f1deab50SJoe Perches do { \ 143adfc5217SJeff Kirsher bp->panic = 1; \ 144adfc5217SJeff Kirsher BNX2X_ERR("driver assert\n"); \ 145823e1d90SYuval Mintz bnx2x_panic_dump(bp, true); \ 146adfc5217SJeff Kirsher } while (0) 147adfc5217SJeff Kirsher #else 148f1deab50SJoe Perches #define bnx2x_panic() \ 149f1deab50SJoe Perches do { \ 150adfc5217SJeff Kirsher bp->panic = 1; \ 151adfc5217SJeff Kirsher BNX2X_ERR("driver assert\n"); \ 152823e1d90SYuval Mintz bnx2x_panic_dump(bp, false); \ 153adfc5217SJeff Kirsher } while (0) 154adfc5217SJeff Kirsher #endif 155adfc5217SJeff Kirsher 156adfc5217SJeff Kirsher #define bnx2x_mc_addr(ha) ((ha)->addr) 157adfc5217SJeff Kirsher #define bnx2x_uc_addr(ha) ((ha)->addr) 158adfc5217SJeff Kirsher 1592de67439SYuval Mintz #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 1602de67439SYuval Mintz #define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 161adfc5217SJeff Kirsher #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 162adfc5217SJeff Kirsher 163adfc5217SJeff Kirsher #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 164adfc5217SJeff Kirsher 165adfc5217SJeff Kirsher #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 166adfc5217SJeff Kirsher #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 167adfc5217SJeff Kirsher #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 168adfc5217SJeff Kirsher 169adfc5217SJeff Kirsher #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 170adfc5217SJeff Kirsher #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 171adfc5217SJeff Kirsher #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 172adfc5217SJeff Kirsher 173adfc5217SJeff Kirsher #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 174adfc5217SJeff Kirsher #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 175adfc5217SJeff Kirsher 176adfc5217SJeff Kirsher #define REG_RD_DMAE(bp, offset, valp, len32) \ 177adfc5217SJeff Kirsher do { \ 178adfc5217SJeff Kirsher bnx2x_read_dmae(bp, offset, len32);\ 179adfc5217SJeff Kirsher memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 180adfc5217SJeff Kirsher } while (0) 181adfc5217SJeff Kirsher 182adfc5217SJeff Kirsher #define REG_WR_DMAE(bp, offset, valp, len32) \ 183adfc5217SJeff Kirsher do { \ 184adfc5217SJeff Kirsher memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 185adfc5217SJeff Kirsher bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 186adfc5217SJeff Kirsher offset, len32); \ 187adfc5217SJeff Kirsher } while (0) 188adfc5217SJeff Kirsher 189adfc5217SJeff Kirsher #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 190adfc5217SJeff Kirsher REG_WR_DMAE(bp, offset, valp, len32) 191adfc5217SJeff Kirsher 192adfc5217SJeff Kirsher #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 193adfc5217SJeff Kirsher do { \ 194adfc5217SJeff Kirsher memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 195adfc5217SJeff Kirsher bnx2x_write_big_buf_wb(bp, addr, len32); \ 196adfc5217SJeff Kirsher } while (0) 197adfc5217SJeff Kirsher 198adfc5217SJeff Kirsher #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 199adfc5217SJeff Kirsher offsetof(struct shmem_region, field)) 200adfc5217SJeff Kirsher #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 201adfc5217SJeff Kirsher #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 202adfc5217SJeff Kirsher 203adfc5217SJeff Kirsher #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 204adfc5217SJeff Kirsher offsetof(struct shmem2_region, field)) 205adfc5217SJeff Kirsher #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 206adfc5217SJeff Kirsher #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 207adfc5217SJeff Kirsher #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 208adfc5217SJeff Kirsher offsetof(struct mf_cfg, field)) 209adfc5217SJeff Kirsher #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 210adfc5217SJeff Kirsher offsetof(struct mf2_cfg, field)) 211adfc5217SJeff Kirsher 212adfc5217SJeff Kirsher #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 213adfc5217SJeff Kirsher #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 214adfc5217SJeff Kirsher MF_CFG_ADDR(bp, field), (val)) 215adfc5217SJeff Kirsher #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 216adfc5217SJeff Kirsher 217adfc5217SJeff Kirsher #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 218adfc5217SJeff Kirsher (SHMEM2_RD((bp), size) > \ 219adfc5217SJeff Kirsher offsetof(struct shmem2_region, field))) 220adfc5217SJeff Kirsher 221adfc5217SJeff Kirsher #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 222adfc5217SJeff Kirsher #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 223adfc5217SJeff Kirsher 224adfc5217SJeff Kirsher /* SP SB indices */ 225adfc5217SJeff Kirsher 226adfc5217SJeff Kirsher /* General SP events - stats query, cfc delete, etc */ 227adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_DEF_CONS 3 228adfc5217SJeff Kirsher 229adfc5217SJeff Kirsher /* EQ completions */ 230adfc5217SJeff Kirsher #define HC_SP_INDEX_EQ_CONS 7 231adfc5217SJeff Kirsher 232adfc5217SJeff Kirsher /* FCoE L2 connection completions */ 233adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 234adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 235adfc5217SJeff Kirsher /* iSCSI L2 */ 236adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 237adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 238adfc5217SJeff Kirsher 239adfc5217SJeff Kirsher /* Special clients parameters */ 240adfc5217SJeff Kirsher 241adfc5217SJeff Kirsher /* SB indices */ 242adfc5217SJeff Kirsher /* FCoE L2 */ 243adfc5217SJeff Kirsher #define BNX2X_FCOE_L2_RX_INDEX \ 244adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 245adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 246adfc5217SJeff Kirsher 247adfc5217SJeff Kirsher #define BNX2X_FCOE_L2_TX_INDEX \ 248adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 249adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 250adfc5217SJeff Kirsher 251adfc5217SJeff Kirsher /** 252adfc5217SJeff Kirsher * CIDs and CLIDs: 253adfc5217SJeff Kirsher * CLIDs below is a CLID for func 0, then the CLID for other 254adfc5217SJeff Kirsher * functions will be calculated by the formula: 255adfc5217SJeff Kirsher * 256adfc5217SJeff Kirsher * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 257adfc5217SJeff Kirsher * 258adfc5217SJeff Kirsher */ 2591805b2f0SDavid S. Miller enum { 2601805b2f0SDavid S. Miller BNX2X_ISCSI_ETH_CL_ID_IDX, 2611805b2f0SDavid S. Miller BNX2X_FCOE_ETH_CL_ID_IDX, 2621805b2f0SDavid S. Miller BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 2631805b2f0SDavid S. Miller }; 264adfc5217SJeff Kirsher 265f78afb35SMichael Chan /* use a value high enough to be above all the PFs, which has least significant 266f78afb35SMichael Chan * nibble as 8, so when cnic needs to come up with a CID for UIO to use to 267f78afb35SMichael Chan * calculate doorbell address according to old doorbell configuration scheme 268f78afb35SMichael Chan * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number 269f78afb35SMichael Chan * We must avoid coming up with cid 8 for iscsi since according to this method 270f78afb35SMichael Chan * the designated UIO cid will come out 0 and it has a special handling for that 271f78afb35SMichael Chan * case which doesn't suit us. Therefore will will cieling to closes cid which 272f78afb35SMichael Chan * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18. 273f78afb35SMichael Chan */ 274f78afb35SMichael Chan 275f78afb35SMichael Chan #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \ 27637ae41a9SMerav Sicron (bp)->max_cos) 277f78afb35SMichael Chan /* amount of cids traversed by UIO's DPM addition to doorbell */ 278f78afb35SMichael Chan #define UIO_DPM 8 279f78afb35SMichael Chan /* roundup to DPM offset */ 280f78afb35SMichael Chan #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \ 281f78afb35SMichael Chan UIO_DPM)) 282f78afb35SMichael Chan /* offset to nearest value which has lsb nibble matching DPM */ 283f78afb35SMichael Chan #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \ 284f78afb35SMichael Chan (UIO_DPM * 2)) 285f78afb35SMichael Chan /* add offset to rounded-up cid to get a value which could be used with UIO */ 286f78afb35SMichael Chan #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp)) 287f78afb35SMichael Chan /* but wait - avoid UIO special case for cid 0 */ 288f78afb35SMichael Chan #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \ 289f78afb35SMichael Chan (UIO_DPM_ALIGN(bp) == UIO_DPM)) 290f78afb35SMichael Chan /* Properly DPM aligned CID dajusted to cid 0 secal case */ 291f78afb35SMichael Chan #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \ 292f78afb35SMichael Chan (UIO_DPM_CID0_OFFSET(bp))) 293f78afb35SMichael Chan /* how many cids were wasted - need this value for cid allocation */ 294f78afb35SMichael Chan #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \ 295f78afb35SMichael Chan BNX2X_1st_NON_L2_ETH_CID(bp)) 2961805b2f0SDavid S. Miller /* iSCSI L2 */ 29737ae41a9SMerav Sicron #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 298adfc5217SJeff Kirsher /* FCoE L2 */ 29937ae41a9SMerav Sicron #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 300adfc5217SJeff Kirsher 30155c11941SMerav Sicron #define CNIC_SUPPORT(bp) ((bp)->cnic_support) 30255c11941SMerav Sicron #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 30355c11941SMerav Sicron #define CNIC_LOADED(bp) ((bp)->cnic_loaded) 30455c11941SMerav Sicron #define FCOE_INIT(bp) ((bp)->fcoe_init) 305adfc5217SJeff Kirsher 306adfc5217SJeff Kirsher #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 307adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 308adfc5217SJeff Kirsher 309adfc5217SJeff Kirsher #define SM_RX_ID 0 310adfc5217SJeff Kirsher #define SM_TX_ID 1 311adfc5217SJeff Kirsher 312adfc5217SJeff Kirsher /* defines for multiple tx priority indices */ 313adfc5217SJeff Kirsher #define FIRST_TX_ONLY_COS_INDEX 1 314adfc5217SJeff Kirsher #define FIRST_TX_COS_INDEX 0 315adfc5217SJeff Kirsher 316adfc5217SJeff Kirsher /* rules for calculating the cids of tx-only connections */ 31765565884SMerav Sicron #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 31865565884SMerav Sicron #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 31965565884SMerav Sicron (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 320adfc5217SJeff Kirsher 321adfc5217SJeff Kirsher /* fp index inside class of service range */ 32265565884SMerav Sicron #define FP_COS_TO_TXQ(fp, cos, bp) \ 32365565884SMerav Sicron ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 324adfc5217SJeff Kirsher 32565565884SMerav Sicron /* Indexes for transmission queues array: 32665565884SMerav Sicron * txdata for RSS i CoS j is at location i + (j * num of RSS) 32765565884SMerav Sicron * txdata for FCoE (if exist) is at location max cos * num of RSS 32865565884SMerav Sicron * txdata for FWD (if exist) is one location after FCoE 32965565884SMerav Sicron * txdata for OOO (if exist) is one location after FWD 330adfc5217SJeff Kirsher */ 33165565884SMerav Sicron enum { 33265565884SMerav Sicron FCOE_TXQ_IDX_OFFSET, 33365565884SMerav Sicron FWD_TXQ_IDX_OFFSET, 33465565884SMerav Sicron OOO_TXQ_IDX_OFFSET, 33565565884SMerav Sicron }; 33665565884SMerav Sicron #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 33765565884SMerav Sicron #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 338adfc5217SJeff Kirsher 339adfc5217SJeff Kirsher /* fast path */ 340e52fcb24SEric Dumazet /* 341e52fcb24SEric Dumazet * This driver uses new build_skb() API : 342e52fcb24SEric Dumazet * RX ring buffer contains pointer to kmalloc() data only, 343e52fcb24SEric Dumazet * skb are built only after Hardware filled the frame. 344e52fcb24SEric Dumazet */ 345adfc5217SJeff Kirsher struct sw_rx_bd { 346e52fcb24SEric Dumazet u8 *data; 347adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping); 348adfc5217SJeff Kirsher }; 349adfc5217SJeff Kirsher 350adfc5217SJeff Kirsher struct sw_tx_bd { 351adfc5217SJeff Kirsher struct sk_buff *skb; 352adfc5217SJeff Kirsher u16 first_bd; 353adfc5217SJeff Kirsher u8 flags; 354adfc5217SJeff Kirsher /* Set on the first BD descriptor when there is a split BD */ 355adfc5217SJeff Kirsher #define BNX2X_TSO_SPLIT_BD (1<<0) 356fe26566dSDmitry Kravkov #define BNX2X_HAS_SECOND_PBD (1<<1) 357adfc5217SJeff Kirsher }; 358adfc5217SJeff Kirsher 359adfc5217SJeff Kirsher struct sw_rx_page { 360adfc5217SJeff Kirsher struct page *page; 361adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping); 3624cace675SGabriel Krisman Bertazi unsigned int offset; 363adfc5217SJeff Kirsher }; 364adfc5217SJeff Kirsher 365adfc5217SJeff Kirsher union db_prod { 366adfc5217SJeff Kirsher struct doorbell_set_prod data; 367adfc5217SJeff Kirsher u32 raw; 368adfc5217SJeff Kirsher }; 369adfc5217SJeff Kirsher 3708decf868SDavid S. Miller /* dropless fc FW/HW related params */ 3718decf868SDavid S. Miller #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 3728decf868SDavid S. Miller #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 3738decf868SDavid S. Miller ETH_MAX_AGGREGATION_QUEUES_E1 :\ 3748decf868SDavid S. Miller ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 3758decf868SDavid S. Miller #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 3768decf868SDavid S. Miller #define FW_PREFETCH_CNT 16 3778decf868SDavid S. Miller #define DROPLESS_FC_HEADROOM 100 378adfc5217SJeff Kirsher 379adfc5217SJeff Kirsher /* MC hsi */ 380adfc5217SJeff Kirsher #define BCM_PAGE_SHIFT 12 381adfc5217SJeff Kirsher #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 382adfc5217SJeff Kirsher #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 383adfc5217SJeff Kirsher #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 384adfc5217SJeff Kirsher 385adfc5217SJeff Kirsher #define PAGES_PER_SGE_SHIFT 0 386adfc5217SJeff Kirsher #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 3874cace675SGabriel Krisman Bertazi #define SGE_PAGE_SHIFT 12 3884cace675SGabriel Krisman Bertazi #define SGE_PAGE_SIZE (1 << SGE_PAGE_SHIFT) 3894cace675SGabriel Krisman Bertazi #define SGE_PAGE_MASK (~(SGE_PAGE_SIZE - 1)) 3904cace675SGabriel Krisman Bertazi #define SGE_PAGE_ALIGN(addr) (((addr) + SGE_PAGE_SIZE - 1) & SGE_PAGE_MASK) 3918d9ac297SAriel Elior #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 3928d9ac297SAriel Elior #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 3938d9ac297SAriel Elior SGE_PAGES), 0xffff) 394adfc5217SJeff Kirsher 395adfc5217SJeff Kirsher /* SGE ring related macros */ 396adfc5217SJeff Kirsher #define NUM_RX_SGE_PAGES 2 397adfc5217SJeff Kirsher #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 3988decf868SDavid S. Miller #define NEXT_PAGE_SGE_DESC_CNT 2 3998decf868SDavid S. Miller #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 400adfc5217SJeff Kirsher /* RX_SGE_CNT is promised to be a power of 2 */ 401adfc5217SJeff Kirsher #define RX_SGE_MASK (RX_SGE_CNT - 1) 402adfc5217SJeff Kirsher #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 403adfc5217SJeff Kirsher #define MAX_RX_SGE (NUM_RX_SGE - 1) 404adfc5217SJeff Kirsher #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 4058decf868SDavid S. Miller (MAX_RX_SGE_CNT - 1)) ? \ 4068decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 4078decf868SDavid S. Miller (x) + 1) 408adfc5217SJeff Kirsher #define RX_SGE(x) ((x) & MAX_RX_SGE) 409adfc5217SJeff Kirsher 4108decf868SDavid S. Miller /* 4118decf868SDavid S. Miller * Number of required SGEs is the sum of two: 4128decf868SDavid S. Miller * 1. Number of possible opened aggregations (next packet for 41316a5fd92SYuval Mintz * these aggregations will probably consume SGE immediately) 4148decf868SDavid S. Miller * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 4158decf868SDavid S. Miller * after placement on BD for new TPA aggregation) 4168decf868SDavid S. Miller * 4178decf868SDavid S. Miller * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 4188decf868SDavid S. Miller */ 4198decf868SDavid S. Miller #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 4208decf868SDavid S. Miller (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 4218decf868SDavid S. Miller #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 4228decf868SDavid S. Miller MAX_RX_SGE_CNT) 4238decf868SDavid S. Miller #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 4248decf868SDavid S. Miller NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 4258decf868SDavid S. Miller #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 4268decf868SDavid S. Miller 427adfc5217SJeff Kirsher /* Manipulate a bit vector defined as an array of u64 */ 428adfc5217SJeff Kirsher 429adfc5217SJeff Kirsher /* Number of bits in one sge_mask array element */ 430adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_SZ 64 431adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_SHIFT 6 432adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 433adfc5217SJeff Kirsher 434adfc5217SJeff Kirsher #define __BIT_VEC64_SET_BIT(el, bit) \ 435adfc5217SJeff Kirsher do { \ 436adfc5217SJeff Kirsher el = ((el) | ((u64)0x1 << (bit))); \ 437adfc5217SJeff Kirsher } while (0) 438adfc5217SJeff Kirsher 439adfc5217SJeff Kirsher #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 440adfc5217SJeff Kirsher do { \ 441adfc5217SJeff Kirsher el = ((el) & (~((u64)0x1 << (bit)))); \ 442adfc5217SJeff Kirsher } while (0) 443adfc5217SJeff Kirsher 444adfc5217SJeff Kirsher #define BIT_VEC64_SET_BIT(vec64, idx) \ 445adfc5217SJeff Kirsher __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 446adfc5217SJeff Kirsher (idx) & BIT_VEC64_ELEM_MASK) 447adfc5217SJeff Kirsher 448adfc5217SJeff Kirsher #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 449adfc5217SJeff Kirsher __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 450adfc5217SJeff Kirsher (idx) & BIT_VEC64_ELEM_MASK) 451adfc5217SJeff Kirsher 452adfc5217SJeff Kirsher #define BIT_VEC64_TEST_BIT(vec64, idx) \ 453adfc5217SJeff Kirsher (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 454adfc5217SJeff Kirsher ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 455adfc5217SJeff Kirsher 456adfc5217SJeff Kirsher /* Creates a bitmask of all ones in less significant bits. 457adfc5217SJeff Kirsher idx - index of the most significant bit in the created mask */ 458adfc5217SJeff Kirsher #define BIT_VEC64_ONES_MASK(idx) \ 459adfc5217SJeff Kirsher (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 460adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 461adfc5217SJeff Kirsher 462adfc5217SJeff Kirsher /*******************************************************/ 463adfc5217SJeff Kirsher 464adfc5217SJeff Kirsher /* Number of u64 elements in SGE mask array */ 465b3637827SDmitry Kravkov #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 466adfc5217SJeff Kirsher #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 467adfc5217SJeff Kirsher #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 468adfc5217SJeff Kirsher 469adfc5217SJeff Kirsher union host_hc_status_block { 470adfc5217SJeff Kirsher /* pointer to fp status block e1x */ 471adfc5217SJeff Kirsher struct host_hc_status_block_e1x *e1x_sb; 472adfc5217SJeff Kirsher /* pointer to fp status block e2 */ 473adfc5217SJeff Kirsher struct host_hc_status_block_e2 *e2_sb; 474adfc5217SJeff Kirsher }; 475adfc5217SJeff Kirsher 476adfc5217SJeff Kirsher struct bnx2x_agg_info { 477adfc5217SJeff Kirsher /* 478e52fcb24SEric Dumazet * First aggregation buffer is a data buffer, the following - are pages. 479e52fcb24SEric Dumazet * We will preallocate the data buffer for each aggregation when 480adfc5217SJeff Kirsher * we open the interface and will replace the BD at the consumer 481adfc5217SJeff Kirsher * with this one when we receive the TPA_START CQE in order to 482adfc5217SJeff Kirsher * keep the Rx BD ring consistent. 483adfc5217SJeff Kirsher */ 484adfc5217SJeff Kirsher struct sw_rx_bd first_buf; 485adfc5217SJeff Kirsher u8 tpa_state; 486adfc5217SJeff Kirsher #define BNX2X_TPA_START 1 487adfc5217SJeff Kirsher #define BNX2X_TPA_STOP 2 488adfc5217SJeff Kirsher #define BNX2X_TPA_ERROR 3 489adfc5217SJeff Kirsher u8 placement_offset; 490adfc5217SJeff Kirsher u16 parsing_flags; 491adfc5217SJeff Kirsher u16 vlan_tag; 492adfc5217SJeff Kirsher u16 len_on_bd; 493e52fcb24SEric Dumazet u32 rxhash; 4945495ab75STom Herbert enum pkt_hash_types rxhash_type; 495621b4d66SDmitry Kravkov u16 gro_size; 496621b4d66SDmitry Kravkov u16 full_page; 497adfc5217SJeff Kirsher }; 498adfc5217SJeff Kirsher 499adfc5217SJeff Kirsher #define Q_STATS_OFFSET32(stat_name) \ 500adfc5217SJeff Kirsher (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 501adfc5217SJeff Kirsher 502adfc5217SJeff Kirsher struct bnx2x_fp_txdata { 503adfc5217SJeff Kirsher 504adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf_ring; 505adfc5217SJeff Kirsher 506adfc5217SJeff Kirsher union eth_tx_bd_types *tx_desc_ring; 507adfc5217SJeff Kirsher dma_addr_t tx_desc_mapping; 508adfc5217SJeff Kirsher 509adfc5217SJeff Kirsher u32 cid; 510adfc5217SJeff Kirsher 511adfc5217SJeff Kirsher union db_prod tx_db; 512adfc5217SJeff Kirsher 513adfc5217SJeff Kirsher u16 tx_pkt_prod; 514adfc5217SJeff Kirsher u16 tx_pkt_cons; 515adfc5217SJeff Kirsher u16 tx_bd_prod; 516adfc5217SJeff Kirsher u16 tx_bd_cons; 517adfc5217SJeff Kirsher 518adfc5217SJeff Kirsher unsigned long tx_pkt; 519adfc5217SJeff Kirsher 520adfc5217SJeff Kirsher __le16 *tx_cons_sb; 521adfc5217SJeff Kirsher 522adfc5217SJeff Kirsher int txq_index; 52365565884SMerav Sicron struct bnx2x_fastpath *parent_fp; 52465565884SMerav Sicron int tx_ring_size; 525adfc5217SJeff Kirsher }; 526adfc5217SJeff Kirsher 527621b4d66SDmitry Kravkov enum bnx2x_tpa_mode_t { 5287e6b4d44SMichal Schmidt TPA_MODE_DISABLED, 529621b4d66SDmitry Kravkov TPA_MODE_LRO, 530621b4d66SDmitry Kravkov TPA_MODE_GRO 531621b4d66SDmitry Kravkov }; 532621b4d66SDmitry Kravkov 5334cace675SGabriel Krisman Bertazi struct bnx2x_alloc_pool { 5344cace675SGabriel Krisman Bertazi struct page *page; 5354cace675SGabriel Krisman Bertazi unsigned int offset; 5364cace675SGabriel Krisman Bertazi }; 5374cace675SGabriel Krisman Bertazi 538adfc5217SJeff Kirsher struct bnx2x_fastpath { 539adfc5217SJeff Kirsher struct bnx2x *bp; /* parent */ 540adfc5217SJeff Kirsher 541adfc5217SJeff Kirsher struct napi_struct napi; 5428f20aa57SDmitry Kravkov 543e0d1095aSCong Wang #ifdef CONFIG_NET_RX_BUSY_POLL 544074975d0SEric Dumazet unsigned long busy_poll_state; 545074975d0SEric Dumazet #endif 5468f20aa57SDmitry Kravkov 547adfc5217SJeff Kirsher union host_hc_status_block status_blk; 54816a5fd92SYuval Mintz /* chip independent shortcuts into sb structure */ 549adfc5217SJeff Kirsher __le16 *sb_index_values; 550adfc5217SJeff Kirsher __le16 *sb_running_index; 55116a5fd92SYuval Mintz /* chip independent shortcut into rx_prods_offset memory */ 552adfc5217SJeff Kirsher u32 ustorm_rx_prods_offset; 553adfc5217SJeff Kirsher 554adfc5217SJeff Kirsher u32 rx_buf_size; 555d46d132cSEric Dumazet u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 556adfc5217SJeff Kirsher dma_addr_t status_blk_mapping; 557adfc5217SJeff Kirsher 558621b4d66SDmitry Kravkov enum bnx2x_tpa_mode_t mode; 559621b4d66SDmitry Kravkov 560adfc5217SJeff Kirsher u8 max_cos; /* actual number of active tx coses */ 56165565884SMerav Sicron struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 562adfc5217SJeff Kirsher 563adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 564adfc5217SJeff Kirsher struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 565adfc5217SJeff Kirsher 566adfc5217SJeff Kirsher struct eth_rx_bd *rx_desc_ring; 567adfc5217SJeff Kirsher dma_addr_t rx_desc_mapping; 568adfc5217SJeff Kirsher 569adfc5217SJeff Kirsher union eth_rx_cqe *rx_comp_ring; 570adfc5217SJeff Kirsher dma_addr_t rx_comp_mapping; 571adfc5217SJeff Kirsher 572adfc5217SJeff Kirsher /* SGE ring */ 573adfc5217SJeff Kirsher struct eth_rx_sge *rx_sge_ring; 574adfc5217SJeff Kirsher dma_addr_t rx_sge_mapping; 575adfc5217SJeff Kirsher 576adfc5217SJeff Kirsher u64 sge_mask[RX_SGE_MASK_LEN]; 577adfc5217SJeff Kirsher 578adfc5217SJeff Kirsher u32 cid; 579adfc5217SJeff Kirsher 580adfc5217SJeff Kirsher __le16 fp_hc_idx; 581adfc5217SJeff Kirsher 582adfc5217SJeff Kirsher u8 index; /* number in fp array */ 583f233cafeSDmitry Kravkov u8 rx_queue; /* index for skb_record */ 584adfc5217SJeff Kirsher u8 cl_id; /* eth client id */ 585adfc5217SJeff Kirsher u8 cl_qzone_id; 586adfc5217SJeff Kirsher u8 fw_sb_id; /* status block number in FW */ 587adfc5217SJeff Kirsher u8 igu_sb_id; /* status block number in HW */ 588adfc5217SJeff Kirsher 589adfc5217SJeff Kirsher u16 rx_bd_prod; 590adfc5217SJeff Kirsher u16 rx_bd_cons; 591adfc5217SJeff Kirsher u16 rx_comp_prod; 592adfc5217SJeff Kirsher u16 rx_comp_cons; 593adfc5217SJeff Kirsher u16 rx_sge_prod; 594adfc5217SJeff Kirsher /* The last maximal completed SGE */ 595adfc5217SJeff Kirsher u16 last_max_sge; 596adfc5217SJeff Kirsher __le16 *rx_cons_sb; 597adfc5217SJeff Kirsher unsigned long rx_pkt, 598adfc5217SJeff Kirsher rx_calls; 599adfc5217SJeff Kirsher 600adfc5217SJeff Kirsher /* TPA related */ 60115192a8cSBarak Witkowski struct bnx2x_agg_info *tpa_info; 602adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 603adfc5217SJeff Kirsher u64 tpa_queue_used; 604adfc5217SJeff Kirsher #endif 605adfc5217SJeff Kirsher /* The size is calculated using the following: 606adfc5217SJeff Kirsher sizeof name field from netdev structure + 607adfc5217SJeff Kirsher 4 ('-Xx-' string) + 608adfc5217SJeff Kirsher 4 (for the digits and to make it DWORD aligned) */ 609adfc5217SJeff Kirsher #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 610adfc5217SJeff Kirsher char name[FP_NAME_SIZE]; 6114cace675SGabriel Krisman Bertazi 6124cace675SGabriel Krisman Bertazi struct bnx2x_alloc_pool page_pool; 613adfc5217SJeff Kirsher }; 614adfc5217SJeff Kirsher 61515192a8cSBarak Witkowski #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 61615192a8cSBarak Witkowski #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 61715192a8cSBarak Witkowski #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 61815192a8cSBarak Witkowski #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 619adfc5217SJeff Kirsher 620e0d1095aSCong Wang #ifdef CONFIG_NET_RX_BUSY_POLL 621074975d0SEric Dumazet 622074975d0SEric Dumazet enum bnx2x_fp_state { 623074975d0SEric Dumazet BNX2X_STATE_FP_NAPI = BIT(0), /* NAPI handler owns the queue */ 624074975d0SEric Dumazet 625074975d0SEric Dumazet BNX2X_STATE_FP_NAPI_REQ_BIT = 1, /* NAPI would like to own the queue */ 626074975d0SEric Dumazet BNX2X_STATE_FP_NAPI_REQ = BIT(1), 627074975d0SEric Dumazet 628074975d0SEric Dumazet BNX2X_STATE_FP_POLL_BIT = 2, 629074975d0SEric Dumazet BNX2X_STATE_FP_POLL = BIT(2), /* busy_poll owns the queue */ 630074975d0SEric Dumazet 631074975d0SEric Dumazet BNX2X_STATE_FP_DISABLE_BIT = 3, /* queue is dismantled */ 632074975d0SEric Dumazet }; 633074975d0SEric Dumazet 634074975d0SEric Dumazet static inline void bnx2x_fp_busy_poll_init(struct bnx2x_fastpath *fp) 6358f20aa57SDmitry Kravkov { 636074975d0SEric Dumazet WRITE_ONCE(fp->busy_poll_state, 0); 6378f20aa57SDmitry Kravkov } 6388f20aa57SDmitry Kravkov 6398f20aa57SDmitry Kravkov /* called from the device poll routine to get ownership of a FP */ 6408f20aa57SDmitry Kravkov static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 6418f20aa57SDmitry Kravkov { 642074975d0SEric Dumazet unsigned long prev, old = READ_ONCE(fp->busy_poll_state); 6438f20aa57SDmitry Kravkov 644074975d0SEric Dumazet while (1) { 645074975d0SEric Dumazet switch (old) { 646074975d0SEric Dumazet case BNX2X_STATE_FP_POLL: 647074975d0SEric Dumazet /* make sure bnx2x_fp_lock_poll() wont starve us */ 648074975d0SEric Dumazet set_bit(BNX2X_STATE_FP_NAPI_REQ_BIT, 649074975d0SEric Dumazet &fp->busy_poll_state); 650074975d0SEric Dumazet /* fallthrough */ 651074975d0SEric Dumazet case BNX2X_STATE_FP_POLL | BNX2X_STATE_FP_NAPI_REQ: 652074975d0SEric Dumazet return false; 653074975d0SEric Dumazet default: 654074975d0SEric Dumazet break; 6558f20aa57SDmitry Kravkov } 656074975d0SEric Dumazet prev = cmpxchg(&fp->busy_poll_state, old, BNX2X_STATE_FP_NAPI); 657074975d0SEric Dumazet if (unlikely(prev != old)) { 658074975d0SEric Dumazet old = prev; 659074975d0SEric Dumazet continue; 660074975d0SEric Dumazet } 661074975d0SEric Dumazet return true; 662074975d0SEric Dumazet } 6638f20aa57SDmitry Kravkov } 6648f20aa57SDmitry Kravkov 665074975d0SEric Dumazet static inline void bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 6668f20aa57SDmitry Kravkov { 667074975d0SEric Dumazet smp_wmb(); 668074975d0SEric Dumazet fp->busy_poll_state = 0; 6698f20aa57SDmitry Kravkov } 6708f20aa57SDmitry Kravkov 6718f20aa57SDmitry Kravkov /* called from bnx2x_low_latency_poll() */ 6728f20aa57SDmitry Kravkov static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 6738f20aa57SDmitry Kravkov { 674074975d0SEric Dumazet return cmpxchg(&fp->busy_poll_state, 0, BNX2X_STATE_FP_POLL) == 0; 6758f20aa57SDmitry Kravkov } 6768f20aa57SDmitry Kravkov 677074975d0SEric Dumazet static inline void bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 6788f20aa57SDmitry Kravkov { 679074975d0SEric Dumazet smp_mb__before_atomic(); 680074975d0SEric Dumazet clear_bit(BNX2X_STATE_FP_POLL_BIT, &fp->busy_poll_state); 6818f20aa57SDmitry Kravkov } 6828f20aa57SDmitry Kravkov 683074975d0SEric Dumazet /* true if a socket is polling */ 6848f20aa57SDmitry Kravkov static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 6858f20aa57SDmitry Kravkov { 686074975d0SEric Dumazet return READ_ONCE(fp->busy_poll_state) & BNX2X_STATE_FP_POLL; 6878f20aa57SDmitry Kravkov } 6889a2620c8SYuval Mintz 6899a2620c8SYuval Mintz /* false if fp is currently owned */ 6909a2620c8SYuval Mintz static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) 6919a2620c8SYuval Mintz { 692074975d0SEric Dumazet set_bit(BNX2X_STATE_FP_DISABLE_BIT, &fp->busy_poll_state); 693074975d0SEric Dumazet return !bnx2x_fp_ll_polling(fp); 6949a2620c8SYuval Mintz 6959a2620c8SYuval Mintz } 6968f20aa57SDmitry Kravkov #else 697074975d0SEric Dumazet static inline void bnx2x_fp_busy_poll_init(struct bnx2x_fastpath *fp) 6988f20aa57SDmitry Kravkov { 6998f20aa57SDmitry Kravkov } 7008f20aa57SDmitry Kravkov 7018f20aa57SDmitry Kravkov static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 7028f20aa57SDmitry Kravkov { 7038f20aa57SDmitry Kravkov return true; 7048f20aa57SDmitry Kravkov } 7058f20aa57SDmitry Kravkov 706074975d0SEric Dumazet static inline void bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 7078f20aa57SDmitry Kravkov { 7088f20aa57SDmitry Kravkov } 7098f20aa57SDmitry Kravkov 7108f20aa57SDmitry Kravkov static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 7118f20aa57SDmitry Kravkov { 7128f20aa57SDmitry Kravkov return false; 7138f20aa57SDmitry Kravkov } 7148f20aa57SDmitry Kravkov 715074975d0SEric Dumazet static inline void bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 7168f20aa57SDmitry Kravkov { 7178f20aa57SDmitry Kravkov } 7188f20aa57SDmitry Kravkov 7198f20aa57SDmitry Kravkov static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 7208f20aa57SDmitry Kravkov { 7218f20aa57SDmitry Kravkov return false; 7228f20aa57SDmitry Kravkov } 7239a2620c8SYuval Mintz static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) 7249a2620c8SYuval Mintz { 7259a2620c8SYuval Mintz return true; 7269a2620c8SYuval Mintz } 727e0d1095aSCong Wang #endif /* CONFIG_NET_RX_BUSY_POLL */ 7288f20aa57SDmitry Kravkov 729adfc5217SJeff Kirsher /* Use 2500 as a mini-jumbo MTU for FCoE */ 730adfc5217SJeff Kirsher #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 731adfc5217SJeff Kirsher 73265565884SMerav Sicron #define FCOE_IDX_OFFSET 0 73365565884SMerav Sicron 73465565884SMerav Sicron #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 73565565884SMerav Sicron FCOE_IDX_OFFSET) 73665565884SMerav Sicron #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 737adfc5217SJeff Kirsher #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 73815192a8cSBarak Witkowski #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 73915192a8cSBarak Witkowski #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 740adfc5217SJeff Kirsher #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 74165565884SMerav Sicron txdata_ptr[FIRST_TX_COS_INDEX] \ 74265565884SMerav Sicron ->var) 743adfc5217SJeff Kirsher 74455c11941SMerav Sicron #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 74555c11941SMerav Sicron #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 74665565884SMerav Sicron #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 747adfc5217SJeff Kirsher 748adfc5217SJeff Kirsher /* MC hsi */ 749adfc5217SJeff Kirsher #define MAX_FETCH_BD 13 /* HW max BDs per packet */ 750adfc5217SJeff Kirsher #define RX_COPY_THRESH 92 751adfc5217SJeff Kirsher 752adfc5217SJeff Kirsher #define NUM_TX_RINGS 16 753adfc5217SJeff Kirsher #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 7548decf868SDavid S. Miller #define NEXT_PAGE_TX_DESC_CNT 1 7558decf868SDavid S. Miller #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 756adfc5217SJeff Kirsher #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 757adfc5217SJeff Kirsher #define MAX_TX_BD (NUM_TX_BD - 1) 758adfc5217SJeff Kirsher #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 759adfc5217SJeff Kirsher #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 7608decf868SDavid S. Miller (MAX_TX_DESC_CNT - 1)) ? \ 7618decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 7628decf868SDavid S. Miller (x) + 1) 763adfc5217SJeff Kirsher #define TX_BD(x) ((x) & MAX_TX_BD) 764adfc5217SJeff Kirsher #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 765adfc5217SJeff Kirsher 7667df2dc6bSDmitry Kravkov /* number of NEXT_PAGE descriptors may be required during placement */ 7677df2dc6bSDmitry Kravkov #define NEXT_CNT_PER_TX_PKT(bds) \ 7687df2dc6bSDmitry Kravkov (((bds) + MAX_TX_DESC_CNT - 1) / \ 7697df2dc6bSDmitry Kravkov MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 7707df2dc6bSDmitry Kravkov /* max BDs per tx packet w/o next_pages: 7717df2dc6bSDmitry Kravkov * START_BD - describes packed 7727df2dc6bSDmitry Kravkov * START_BD(splitted) - includes unpaged data segment for GSO 7737df2dc6bSDmitry Kravkov * PARSING_BD - for TSO and CSUM data 774a848ade4SDmitry Kravkov * PARSING_BD2 - for encapsulation data 77516a5fd92SYuval Mintz * Frag BDs - describes pages for frags 7767df2dc6bSDmitry Kravkov */ 777a848ade4SDmitry Kravkov #define BDS_PER_TX_PKT 4 7787df2dc6bSDmitry Kravkov #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 7797df2dc6bSDmitry Kravkov /* max BDs per tx packet including next pages */ 7807df2dc6bSDmitry Kravkov #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 7817df2dc6bSDmitry Kravkov NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 7827df2dc6bSDmitry Kravkov 783adfc5217SJeff Kirsher /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 784adfc5217SJeff Kirsher #define NUM_RX_RINGS 8 785adfc5217SJeff Kirsher #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 7868decf868SDavid S. Miller #define NEXT_PAGE_RX_DESC_CNT 2 7878decf868SDavid S. Miller #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 788adfc5217SJeff Kirsher #define RX_DESC_MASK (RX_DESC_CNT - 1) 789adfc5217SJeff Kirsher #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 790adfc5217SJeff Kirsher #define MAX_RX_BD (NUM_RX_BD - 1) 791adfc5217SJeff Kirsher #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 7928decf868SDavid S. Miller 7938decf868SDavid S. Miller /* dropless fc calculations for BDs 7948decf868SDavid S. Miller * 7958decf868SDavid S. Miller * Number of BDs should as number of buffers in BRB: 7968decf868SDavid S. Miller * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 7978decf868SDavid S. Miller * "next" elements on each page 7988decf868SDavid S. Miller */ 7998decf868SDavid S. Miller #define NUM_BD_REQ BRB_SIZE(bp) 8008decf868SDavid S. Miller #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 8018decf868SDavid S. Miller MAX_RX_DESC_CNT) 8028decf868SDavid S. Miller #define BD_TH_LO(bp) (NUM_BD_REQ + \ 8038decf868SDavid S. Miller NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 8048decf868SDavid S. Miller FW_DROP_LEVEL(bp)) 8058decf868SDavid S. Miller #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 8068decf868SDavid S. Miller 8078decf868SDavid S. Miller #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 808adfc5217SJeff Kirsher 809adfc5217SJeff Kirsher #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 810adfc5217SJeff Kirsher ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 811adfc5217SJeff Kirsher ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 812adfc5217SJeff Kirsher #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 813adfc5217SJeff Kirsher #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 814adfc5217SJeff Kirsher #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 815adfc5217SJeff Kirsher MIN_RX_AVAIL)) 816adfc5217SJeff Kirsher 817adfc5217SJeff Kirsher #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 8188decf868SDavid S. Miller (MAX_RX_DESC_CNT - 1)) ? \ 8198decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 8208decf868SDavid S. Miller (x) + 1) 821adfc5217SJeff Kirsher #define RX_BD(x) ((x) & MAX_RX_BD) 822adfc5217SJeff Kirsher 823adfc5217SJeff Kirsher /* 824adfc5217SJeff Kirsher * As long as CQE is X times bigger than BD entry we have to allocate X times 825adfc5217SJeff Kirsher * more pages for CQ ring in order to keep it balanced with BD ring 826adfc5217SJeff Kirsher */ 827adfc5217SJeff Kirsher #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 828adfc5217SJeff Kirsher #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 829adfc5217SJeff Kirsher #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 8308decf868SDavid S. Miller #define NEXT_PAGE_RCQ_DESC_CNT 1 8318decf868SDavid S. Miller #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 832adfc5217SJeff Kirsher #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 833adfc5217SJeff Kirsher #define MAX_RCQ_BD (NUM_RCQ_BD - 1) 834adfc5217SJeff Kirsher #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 835adfc5217SJeff Kirsher #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 8368decf868SDavid S. Miller (MAX_RCQ_DESC_CNT - 1)) ? \ 8378decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 8388decf868SDavid S. Miller (x) + 1) 839adfc5217SJeff Kirsher #define RCQ_BD(x) ((x) & MAX_RCQ_BD) 840adfc5217SJeff Kirsher 8418decf868SDavid S. Miller /* dropless fc calculations for RCQs 8428decf868SDavid S. Miller * 8438decf868SDavid S. Miller * Number of RCQs should be as number of buffers in BRB: 8448decf868SDavid S. Miller * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 8458decf868SDavid S. Miller * "next" elements on each page 8468decf868SDavid S. Miller */ 8478decf868SDavid S. Miller #define NUM_RCQ_REQ BRB_SIZE(bp) 8488decf868SDavid S. Miller #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 8498decf868SDavid S. Miller MAX_RCQ_DESC_CNT) 8508decf868SDavid S. Miller #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 8518decf868SDavid S. Miller NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 8528decf868SDavid S. Miller FW_DROP_LEVEL(bp)) 8538decf868SDavid S. Miller #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 8548decf868SDavid S. Miller 855adfc5217SJeff Kirsher /* This is needed for determining of last_max */ 856adfc5217SJeff Kirsher #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 857adfc5217SJeff Kirsher #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 858adfc5217SJeff Kirsher 859adfc5217SJeff Kirsher #define BNX2X_SWCID_SHIFT 17 860adfc5217SJeff Kirsher #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 861adfc5217SJeff Kirsher 862adfc5217SJeff Kirsher /* used on a CID received from the HW */ 863adfc5217SJeff Kirsher #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 864adfc5217SJeff Kirsher #define CQE_CMD(x) (le32_to_cpu(x) >> \ 865adfc5217SJeff Kirsher COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 866adfc5217SJeff Kirsher 867adfc5217SJeff Kirsher #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 868adfc5217SJeff Kirsher le32_to_cpu((bd)->addr_lo)) 869adfc5217SJeff Kirsher #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 870adfc5217SJeff Kirsher 871adfc5217SJeff Kirsher #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 872b9871bcfSAriel Elior #define BNX2X_DB_SHIFT 3 /* 8 bytes*/ 873adfc5217SJeff Kirsher #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 874adfc5217SJeff Kirsher #error "Min DB doorbell stride is 8" 875adfc5217SJeff Kirsher #endif 876adfc5217SJeff Kirsher #define DOORBELL(bp, cid, val) \ 877adfc5217SJeff Kirsher do { \ 878b9871bcfSAriel Elior writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \ 879adfc5217SJeff Kirsher } while (0) 880adfc5217SJeff Kirsher 881adfc5217SJeff Kirsher /* TX CSUM helpers */ 882adfc5217SJeff Kirsher #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 883adfc5217SJeff Kirsher skb->csum_offset) 884adfc5217SJeff Kirsher #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 885adfc5217SJeff Kirsher skb->csum_offset)) 886adfc5217SJeff Kirsher 88791226790SDmitry Kravkov #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) 888adfc5217SJeff Kirsher 889adfc5217SJeff Kirsher #define XMIT_PLAIN 0 890a848ade4SDmitry Kravkov #define XMIT_CSUM_V4 (1 << 0) 891a848ade4SDmitry Kravkov #define XMIT_CSUM_V6 (1 << 1) 892a848ade4SDmitry Kravkov #define XMIT_CSUM_TCP (1 << 2) 893a848ade4SDmitry Kravkov #define XMIT_GSO_V4 (1 << 3) 894a848ade4SDmitry Kravkov #define XMIT_GSO_V6 (1 << 4) 895a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC_V4 (1 << 5) 896a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC_V6 (1 << 6) 897a848ade4SDmitry Kravkov #define XMIT_GSO_ENC_V4 (1 << 7) 898a848ade4SDmitry Kravkov #define XMIT_GSO_ENC_V6 (1 << 8) 899adfc5217SJeff Kirsher 900a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) 901a848ade4SDmitry Kravkov #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) 902adfc5217SJeff Kirsher 903a848ade4SDmitry Kravkov #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) 904a848ade4SDmitry Kravkov #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) 905adfc5217SJeff Kirsher 906adfc5217SJeff Kirsher /* stuff added to make the code fit 80Col */ 907adfc5217SJeff Kirsher #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 908adfc5217SJeff Kirsher #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 909adfc5217SJeff Kirsher #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 910adfc5217SJeff Kirsher #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 911adfc5217SJeff Kirsher #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 912adfc5217SJeff Kirsher 913adfc5217SJeff Kirsher #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 914adfc5217SJeff Kirsher 915adfc5217SJeff Kirsher #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 916adfc5217SJeff Kirsher (((le16_to_cpu(flags) & \ 917adfc5217SJeff Kirsher PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 918adfc5217SJeff Kirsher PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 919adfc5217SJeff Kirsher == PRS_FLAG_OVERETH_IPV4) 920adfc5217SJeff Kirsher #define BNX2X_RX_SUM_FIX(cqe) \ 921adfc5217SJeff Kirsher BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 922adfc5217SJeff Kirsher 923adfc5217SJeff Kirsher #define FP_USB_FUNC_OFF \ 924adfc5217SJeff Kirsher offsetof(struct cstorm_status_block_u, func) 925adfc5217SJeff Kirsher #define FP_CSB_FUNC_OFF \ 926adfc5217SJeff Kirsher offsetof(struct cstorm_status_block_c, func) 927adfc5217SJeff Kirsher 9288decf868SDavid S. Miller #define HC_INDEX_ETH_RX_CQ_CONS 1 929adfc5217SJeff Kirsher 9308decf868SDavid S. Miller #define HC_INDEX_OOO_TX_CQ_CONS 4 9318decf868SDavid S. Miller 9328decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 9338decf868SDavid S. Miller 9348decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 9358decf868SDavid S. Miller 9368decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 937adfc5217SJeff Kirsher 938adfc5217SJeff Kirsher #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 939adfc5217SJeff Kirsher 940adfc5217SJeff Kirsher #define BNX2X_RX_SB_INDEX \ 941adfc5217SJeff Kirsher (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 942adfc5217SJeff Kirsher 943adfc5217SJeff Kirsher #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 944adfc5217SJeff Kirsher 945adfc5217SJeff Kirsher #define BNX2X_TX_SB_INDEX_COS0 \ 946adfc5217SJeff Kirsher (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 947adfc5217SJeff Kirsher 948adfc5217SJeff Kirsher /* end of fast path */ 949adfc5217SJeff Kirsher 950adfc5217SJeff Kirsher /* common */ 951adfc5217SJeff Kirsher 952adfc5217SJeff Kirsher struct bnx2x_common { 953adfc5217SJeff Kirsher 954adfc5217SJeff Kirsher u32 chip_id; 955adfc5217SJeff Kirsher /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 956adfc5217SJeff Kirsher #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 957adfc5217SJeff Kirsher 958adfc5217SJeff Kirsher #define CHIP_NUM(bp) (bp->common.chip_id >> 16) 959adfc5217SJeff Kirsher #define CHIP_NUM_57710 0x164e 960adfc5217SJeff Kirsher #define CHIP_NUM_57711 0x164f 961adfc5217SJeff Kirsher #define CHIP_NUM_57711E 0x1650 962adfc5217SJeff Kirsher #define CHIP_NUM_57712 0x1662 963adfc5217SJeff Kirsher #define CHIP_NUM_57712_MF 0x1663 9648395be5eSAriel Elior #define CHIP_NUM_57712_VF 0x166f 965adfc5217SJeff Kirsher #define CHIP_NUM_57713 0x1651 966adfc5217SJeff Kirsher #define CHIP_NUM_57713E 0x1652 967adfc5217SJeff Kirsher #define CHIP_NUM_57800 0x168a 968adfc5217SJeff Kirsher #define CHIP_NUM_57800_MF 0x16a5 9698395be5eSAriel Elior #define CHIP_NUM_57800_VF 0x16a9 970adfc5217SJeff Kirsher #define CHIP_NUM_57810 0x168e 971adfc5217SJeff Kirsher #define CHIP_NUM_57810_MF 0x16ae 9728395be5eSAriel Elior #define CHIP_NUM_57810_VF 0x16af 9737e8e02dfSBarak Witkowski #define CHIP_NUM_57811 0x163d 9747e8e02dfSBarak Witkowski #define CHIP_NUM_57811_MF 0x163e 9758395be5eSAriel Elior #define CHIP_NUM_57811_VF 0x163f 976c3def943SYuval Mintz #define CHIP_NUM_57840_OBSOLETE 0x168d 977c3def943SYuval Mintz #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 978c3def943SYuval Mintz #define CHIP_NUM_57840_4_10 0x16a1 979c3def943SYuval Mintz #define CHIP_NUM_57840_2_20 0x16a2 980c3def943SYuval Mintz #define CHIP_NUM_57840_MF 0x16a4 9818395be5eSAriel Elior #define CHIP_NUM_57840_VF 0x16ad 982adfc5217SJeff Kirsher #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 983adfc5217SJeff Kirsher #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 984adfc5217SJeff Kirsher #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 985adfc5217SJeff Kirsher #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 9868395be5eSAriel Elior #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 987adfc5217SJeff Kirsher #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 988adfc5217SJeff Kirsher #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 989adfc5217SJeff Kirsher #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 9908395be5eSAriel Elior #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 991adfc5217SJeff Kirsher #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 992adfc5217SJeff Kirsher #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 9938395be5eSAriel Elior #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 9947e8e02dfSBarak Witkowski #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 9957e8e02dfSBarak Witkowski #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 9968395be5eSAriel Elior #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 997c3def943SYuval Mintz #define CHIP_IS_57840(bp) \ 998c3def943SYuval Mintz ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 999c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 1000c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 1001c3def943SYuval Mintz #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 1002c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 10038395be5eSAriel Elior #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 1004adfc5217SJeff Kirsher #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 1005adfc5217SJeff Kirsher CHIP_IS_57711E(bp)) 1006edb944d2SDmitry Kravkov #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ 1007edb944d2SDmitry Kravkov CHIP_IS_57811_MF(bp) || \ 1008edb944d2SDmitry Kravkov CHIP_IS_57811_VF(bp)) 1009adfc5217SJeff Kirsher #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 10106ab20355SYuval Mintz CHIP_IS_57712_MF(bp) || \ 10116ab20355SYuval Mintz CHIP_IS_57712_VF(bp)) 1012adfc5217SJeff Kirsher #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 1013adfc5217SJeff Kirsher CHIP_IS_57800_MF(bp) || \ 10146ab20355SYuval Mintz CHIP_IS_57800_VF(bp) || \ 1015adfc5217SJeff Kirsher CHIP_IS_57810(bp) || \ 1016adfc5217SJeff Kirsher CHIP_IS_57810_MF(bp) || \ 10178395be5eSAriel Elior CHIP_IS_57810_VF(bp) || \ 1018edb944d2SDmitry Kravkov CHIP_IS_57811xx(bp) || \ 1019adfc5217SJeff Kirsher CHIP_IS_57840(bp) || \ 10208395be5eSAriel Elior CHIP_IS_57840_MF(bp) || \ 10218395be5eSAriel Elior CHIP_IS_57840_VF(bp)) 1022adfc5217SJeff Kirsher #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 1023adfc5217SJeff Kirsher #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 1024adfc5217SJeff Kirsher #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 1025adfc5217SJeff Kirsher 1026adfc5217SJeff Kirsher #define CHIP_REV_SHIFT 12 1027adfc5217SJeff Kirsher #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1028adfc5217SJeff Kirsher #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 1029adfc5217SJeff Kirsher #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1030adfc5217SJeff Kirsher #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1031adfc5217SJeff Kirsher /* assume maximum 5 revisions */ 1032adfc5217SJeff Kirsher #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 1033adfc5217SJeff Kirsher /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 1034adfc5217SJeff Kirsher #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1035adfc5217SJeff Kirsher !(CHIP_REV_VAL(bp) & 0x00001000)) 1036adfc5217SJeff Kirsher /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 1037adfc5217SJeff Kirsher #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1038adfc5217SJeff Kirsher (CHIP_REV_VAL(bp) & 0x00001000)) 1039adfc5217SJeff Kirsher 1040adfc5217SJeff Kirsher #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 1041adfc5217SJeff Kirsher ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 1042adfc5217SJeff Kirsher 1043adfc5217SJeff Kirsher #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 1044adfc5217SJeff Kirsher #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 1045adfc5217SJeff Kirsher #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 1046adfc5217SJeff Kirsher (CHIP_REV_SHIFT + 1)) \ 1047adfc5217SJeff Kirsher << CHIP_REV_SHIFT) 1048adfc5217SJeff Kirsher #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 1049adfc5217SJeff Kirsher CHIP_REV_SIM(bp) :\ 1050adfc5217SJeff Kirsher CHIP_REV_VAL(bp)) 1051adfc5217SJeff Kirsher #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 1052adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Bx)) 1053adfc5217SJeff Kirsher #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 1054adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Ax)) 105555c11941SMerav Sicron /* This define is used in two main places: 105616a5fd92SYuval Mintz * 1. In the early stages of nic_load, to know if to configure Parser / Searcher 105755c11941SMerav Sicron * to nic-only mode or to offload mode. Offload mode is configured if either the 105855c11941SMerav Sicron * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 105955c11941SMerav Sicron * registered for this port (which means that the user wants storage services). 106055c11941SMerav Sicron * 2. During cnic-related load, to know if offload mode is already configured in 106116a5fd92SYuval Mintz * the HW or needs to be configured. 106255c11941SMerav Sicron * Since the transition from nic-mode to offload-mode in HW causes traffic 106316a5fd92SYuval Mintz * corruption, nic-mode is configured only in ports on which storage services 106455c11941SMerav Sicron * where never requested. 106555c11941SMerav Sicron */ 106655c11941SMerav Sicron #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 1067adfc5217SJeff Kirsher 1068adfc5217SJeff Kirsher int flash_size; 1069adfc5217SJeff Kirsher #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 1070adfc5217SJeff Kirsher #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 1071adfc5217SJeff Kirsher #define BNX2X_NVRAM_PAGE_SIZE 256 1072adfc5217SJeff Kirsher 1073adfc5217SJeff Kirsher u32 shmem_base; 1074adfc5217SJeff Kirsher u32 shmem2_base; 1075adfc5217SJeff Kirsher u32 mf_cfg_base; 1076adfc5217SJeff Kirsher u32 mf2_cfg_base; 1077adfc5217SJeff Kirsher 1078adfc5217SJeff Kirsher u32 hw_config; 1079adfc5217SJeff Kirsher 1080adfc5217SJeff Kirsher u32 bc_ver; 1081adfc5217SJeff Kirsher 1082adfc5217SJeff Kirsher u8 int_block; 1083adfc5217SJeff Kirsher #define INT_BLOCK_HC 0 1084adfc5217SJeff Kirsher #define INT_BLOCK_IGU 1 1085adfc5217SJeff Kirsher #define INT_BLOCK_MODE_NORMAL 0 1086adfc5217SJeff Kirsher #define INT_BLOCK_MODE_BW_COMP 2 1087adfc5217SJeff Kirsher #define CHIP_INT_MODE_IS_NBC(bp) \ 1088adfc5217SJeff Kirsher (!CHIP_IS_E1x(bp) && \ 1089adfc5217SJeff Kirsher !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 1090adfc5217SJeff Kirsher #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 1091adfc5217SJeff Kirsher 1092adfc5217SJeff Kirsher u8 chip_port_mode; 1093adfc5217SJeff Kirsher #define CHIP_4_PORT_MODE 0x0 1094adfc5217SJeff Kirsher #define CHIP_2_PORT_MODE 0x1 1095adfc5217SJeff Kirsher #define CHIP_PORT_MODE_NONE 0x2 1096adfc5217SJeff Kirsher #define CHIP_MODE(bp) (bp->common.chip_port_mode) 1097adfc5217SJeff Kirsher #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 10981d187b34SBarak Witkowski 10991d187b34SBarak Witkowski u32 boot_mode; 1100adfc5217SJeff Kirsher }; 1101adfc5217SJeff Kirsher 1102adfc5217SJeff Kirsher /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 1103adfc5217SJeff Kirsher #define BNX2X_IGU_STAS_MSG_VF_CNT 64 1104adfc5217SJeff Kirsher #define BNX2X_IGU_STAS_MSG_PF_CNT 4 1105adfc5217SJeff Kirsher 110627c1151cSYaniv Rosner #define MAX_IGU_ATTN_ACK_TO 100 1107adfc5217SJeff Kirsher /* end of common */ 1108adfc5217SJeff Kirsher 1109adfc5217SJeff Kirsher /* port */ 1110adfc5217SJeff Kirsher 1111adfc5217SJeff Kirsher struct bnx2x_port { 1112adfc5217SJeff Kirsher u32 pmf; 1113adfc5217SJeff Kirsher 1114adfc5217SJeff Kirsher u32 link_config[LINK_CONFIG_SIZE]; 1115adfc5217SJeff Kirsher 1116adfc5217SJeff Kirsher u32 supported[LINK_CONFIG_SIZE]; 1117adfc5217SJeff Kirsher 1118adfc5217SJeff Kirsher u32 advertising[LINK_CONFIG_SIZE]; 1119adfc5217SJeff Kirsher 1120adfc5217SJeff Kirsher u32 phy_addr; 1121adfc5217SJeff Kirsher 1122adfc5217SJeff Kirsher /* used to synchronize phy accesses */ 1123adfc5217SJeff Kirsher struct mutex phy_mutex; 1124adfc5217SJeff Kirsher 1125adfc5217SJeff Kirsher u32 port_stx; 1126adfc5217SJeff Kirsher 1127adfc5217SJeff Kirsher struct nig_stats old_nig_stats; 1128adfc5217SJeff Kirsher }; 1129adfc5217SJeff Kirsher 1130adfc5217SJeff Kirsher /* end of port */ 1131adfc5217SJeff Kirsher 1132adfc5217SJeff Kirsher #define STATS_OFFSET32(stat_name) \ 1133adfc5217SJeff Kirsher (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 1134adfc5217SJeff Kirsher 1135adfc5217SJeff Kirsher /* slow path */ 1136adfc5217SJeff Kirsher #define BNX2X_MAX_NUM_OF_VFS 64 1137b9871bcfSAriel Elior #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */ 11381ab4434cSAriel Elior #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 1139b9871bcfSAriel Elior 1140b9871bcfSAriel Elior /* We need to reserve doorbell addresses for all VF and queue combinations */ 11411ab4434cSAriel Elior #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 1142b9871bcfSAriel Elior 1143b9871bcfSAriel Elior /* The doorbell is configured to have the same number of CIDs for PFs and for 1144b9871bcfSAriel Elior * VFs. For this reason the PF CID zone is as large as the VF zone. 1145b9871bcfSAriel Elior */ 1146b9871bcfSAriel Elior #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS 1147b9871bcfSAriel Elior #define BNX2X_MAX_NUM_VF_QUEUES 64 1148adfc5217SJeff Kirsher #define BNX2X_VF_ID_INVALID 0xFF 1149adfc5217SJeff Kirsher 1150b9871bcfSAriel Elior /* the number of VF CIDS multiplied by the amount of bytes reserved for each 1151b9871bcfSAriel Elior * cid must not exceed the size of the VF doorbell 1152b9871bcfSAriel Elior */ 1153b9871bcfSAriel Elior #define BNX2X_VF_BAR_SIZE 512 1154b9871bcfSAriel Elior #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT)) 1155b9871bcfSAriel Elior #error "VF doorbell bar size is 512" 1156b9871bcfSAriel Elior #endif 1157b9871bcfSAriel Elior 1158adfc5217SJeff Kirsher /* 1159adfc5217SJeff Kirsher * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 1160adfc5217SJeff Kirsher * control by the number of fast-path status blocks supported by the 1161adfc5217SJeff Kirsher * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 1162adfc5217SJeff Kirsher * status block represents an independent interrupts context that can 1163adfc5217SJeff Kirsher * serve a regular L2 networking queue. However special L2 queues such 1164adfc5217SJeff Kirsher * as the FCoE queue do not require a FP-SB and other components like 1165adfc5217SJeff Kirsher * the CNIC may consume FP-SB reducing the number of possible L2 queues 1166adfc5217SJeff Kirsher * 1167adfc5217SJeff Kirsher * If the maximum number of FP-SB available is X then: 1168adfc5217SJeff Kirsher * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 1169adfc5217SJeff Kirsher * regular L2 queues is Y=X-1 117016a5fd92SYuval Mintz * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1171adfc5217SJeff Kirsher * c. If the FCoE L2 queue is supported the actual number of L2 queues 1172adfc5217SJeff Kirsher * is Y+1 1173adfc5217SJeff Kirsher * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1174adfc5217SJeff Kirsher * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1175adfc5217SJeff Kirsher * FP interrupt context for the CNIC). 1176adfc5217SJeff Kirsher * e. The number of HW context (CID count) is always X or X+1 if FCoE 117716a5fd92SYuval Mintz * L2 queue is supported. The cid for the FCoE L2 queue is always X. 1178adfc5217SJeff Kirsher */ 1179adfc5217SJeff Kirsher 1180adfc5217SJeff Kirsher /* fast-path interrupt contexts E1x */ 1181adfc5217SJeff Kirsher #define FP_SB_MAX_E1x 16 1182adfc5217SJeff Kirsher /* fast-path interrupt contexts E2 */ 1183adfc5217SJeff Kirsher #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1184adfc5217SJeff Kirsher 1185adfc5217SJeff Kirsher union cdu_context { 1186adfc5217SJeff Kirsher struct eth_context eth; 1187adfc5217SJeff Kirsher char pad[1024]; 1188adfc5217SJeff Kirsher }; 1189adfc5217SJeff Kirsher 1190adfc5217SJeff Kirsher /* CDU host DB constants */ 1191a052997eSMerav Sicron #define CDU_ILT_PAGE_SZ_HW 2 1192a052997eSMerav Sicron #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1193adfc5217SJeff Kirsher #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1194adfc5217SJeff Kirsher 1195adfc5217SJeff Kirsher #define CNIC_ISCSI_CID_MAX 256 1196adfc5217SJeff Kirsher #define CNIC_FCOE_CID_MAX 2048 1197adfc5217SJeff Kirsher #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1198adfc5217SJeff Kirsher #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1199adfc5217SJeff Kirsher 1200adfc5217SJeff Kirsher #define QM_ILT_PAGE_SZ_HW 0 1201adfc5217SJeff Kirsher #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1202adfc5217SJeff Kirsher #define QM_CID_ROUND 1024 1203adfc5217SJeff Kirsher 1204adfc5217SJeff Kirsher /* TM (timers) host DB constants */ 1205adfc5217SJeff Kirsher #define TM_ILT_PAGE_SZ_HW 0 1206adfc5217SJeff Kirsher #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 12070907f34cSAriel Elior #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \ 12080907f34cSAriel Elior BNX2X_VF_CIDS + \ 12090907f34cSAriel Elior CNIC_ISCSI_CID_MAX) 1210adfc5217SJeff Kirsher #define TM_ILT_SZ (8 * TM_CONN_NUM) 1211adfc5217SJeff Kirsher #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1212adfc5217SJeff Kirsher 1213adfc5217SJeff Kirsher /* SRC (Searcher) host DB constants */ 1214adfc5217SJeff Kirsher #define SRC_ILT_PAGE_SZ_HW 0 1215adfc5217SJeff Kirsher #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1216adfc5217SJeff Kirsher #define SRC_HASH_BITS 10 1217adfc5217SJeff Kirsher #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1218adfc5217SJeff Kirsher #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1219adfc5217SJeff Kirsher #define SRC_T2_SZ SRC_ILT_SZ 1220adfc5217SJeff Kirsher #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1221adfc5217SJeff Kirsher 1222adfc5217SJeff Kirsher #define MAX_DMAE_C 8 1223adfc5217SJeff Kirsher 1224adfc5217SJeff Kirsher /* DMA memory not used in fastpath */ 1225adfc5217SJeff Kirsher struct bnx2x_slowpath { 1226adfc5217SJeff Kirsher union { 1227adfc5217SJeff Kirsher struct mac_configuration_cmd e1x; 1228adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data e2; 1229adfc5217SJeff Kirsher } mac_rdata; 1230adfc5217SJeff Kirsher 1231adfc5217SJeff Kirsher union { 1232adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config e1x; 1233adfc5217SJeff Kirsher struct eth_filter_rules_ramrod_data e2; 1234adfc5217SJeff Kirsher } rx_mode_rdata; 1235adfc5217SJeff Kirsher 1236adfc5217SJeff Kirsher union { 1237adfc5217SJeff Kirsher struct mac_configuration_cmd e1; 1238adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data e2; 1239adfc5217SJeff Kirsher } mcast_rdata; 1240adfc5217SJeff Kirsher 1241adfc5217SJeff Kirsher struct eth_rss_update_ramrod_data rss_rdata; 1242adfc5217SJeff Kirsher 1243adfc5217SJeff Kirsher /* Queue State related ramrods are always sent under rtnl_lock */ 1244adfc5217SJeff Kirsher union { 1245adfc5217SJeff Kirsher struct client_init_ramrod_data init_data; 1246adfc5217SJeff Kirsher struct client_update_ramrod_data update_data; 124714a94ebdSMichal Kalderon struct tpa_update_ramrod_data tpa_data; 1248adfc5217SJeff Kirsher } q_rdata; 1249adfc5217SJeff Kirsher 1250adfc5217SJeff Kirsher union { 1251adfc5217SJeff Kirsher struct function_start_data func_start; 1252adfc5217SJeff Kirsher /* pfc configuration for DCBX ramrod */ 1253adfc5217SJeff Kirsher struct flow_control_configuration pfc_config; 1254adfc5217SJeff Kirsher } func_rdata; 1255adfc5217SJeff Kirsher 1256a3348722SBarak Witkowski /* afex ramrod can not be a part of func_rdata union because these 1257a3348722SBarak Witkowski * events might arrive in parallel to other events from func_rdata. 1258a3348722SBarak Witkowski * Therefore, if they would have been defined in the same union, 1259a3348722SBarak Witkowski * data can get corrupted. 1260a3348722SBarak Witkowski */ 12619dfef3adSYuval Mintz union { 12629dfef3adSYuval Mintz struct afex_vif_list_ramrod_data viflist_data; 12639dfef3adSYuval Mintz struct function_update_data func_update; 12649dfef3adSYuval Mintz } func_afex_rdata; 1265a3348722SBarak Witkowski 1266adfc5217SJeff Kirsher /* used by dmae command executer */ 1267adfc5217SJeff Kirsher struct dmae_command dmae[MAX_DMAE_C]; 1268adfc5217SJeff Kirsher 1269adfc5217SJeff Kirsher u32 stats_comp; 1270adfc5217SJeff Kirsher union mac_stats mac_stats; 1271adfc5217SJeff Kirsher struct nig_stats nig_stats; 1272adfc5217SJeff Kirsher struct host_port_stats port_stats; 1273adfc5217SJeff Kirsher struct host_func_stats func_stats; 1274adfc5217SJeff Kirsher 1275adfc5217SJeff Kirsher u32 wb_comp; 1276adfc5217SJeff Kirsher u32 wb_data[4]; 12771d187b34SBarak Witkowski 12781d187b34SBarak Witkowski union drv_info_to_mcp drv_info_to_mcp; 1279adfc5217SJeff Kirsher }; 1280adfc5217SJeff Kirsher 1281adfc5217SJeff Kirsher #define bnx2x_sp(bp, var) (&bp->slowpath->var) 1282adfc5217SJeff Kirsher #define bnx2x_sp_mapping(bp, var) \ 1283adfc5217SJeff Kirsher (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1284adfc5217SJeff Kirsher 1285adfc5217SJeff Kirsher /* attn group wiring */ 1286adfc5217SJeff Kirsher #define MAX_DYNAMIC_ATTN_GRPS 8 1287adfc5217SJeff Kirsher 1288adfc5217SJeff Kirsher struct attn_route { 1289adfc5217SJeff Kirsher u32 sig[5]; 1290adfc5217SJeff Kirsher }; 1291adfc5217SJeff Kirsher 1292adfc5217SJeff Kirsher struct iro { 1293adfc5217SJeff Kirsher u32 base; 1294adfc5217SJeff Kirsher u16 m1; 1295adfc5217SJeff Kirsher u16 m2; 1296adfc5217SJeff Kirsher u16 m3; 1297adfc5217SJeff Kirsher u16 size; 1298adfc5217SJeff Kirsher }; 1299adfc5217SJeff Kirsher 1300adfc5217SJeff Kirsher struct hw_context { 1301adfc5217SJeff Kirsher union cdu_context *vcxt; 1302adfc5217SJeff Kirsher dma_addr_t cxt_mapping; 1303adfc5217SJeff Kirsher size_t size; 1304adfc5217SJeff Kirsher }; 1305adfc5217SJeff Kirsher 1306adfc5217SJeff Kirsher /* forward */ 1307adfc5217SJeff Kirsher struct bnx2x_ilt; 1308adfc5217SJeff Kirsher 1309290ca2bbSAriel Elior struct bnx2x_vfdb; 1310adfc5217SJeff Kirsher 1311adfc5217SJeff Kirsher enum bnx2x_recovery_state { 1312adfc5217SJeff Kirsher BNX2X_RECOVERY_DONE, 1313adfc5217SJeff Kirsher BNX2X_RECOVERY_INIT, 1314adfc5217SJeff Kirsher BNX2X_RECOVERY_WAIT, 131595c6c616SAriel Elior BNX2X_RECOVERY_FAILED, 131695c6c616SAriel Elior BNX2X_RECOVERY_NIC_LOADING 1317adfc5217SJeff Kirsher }; 1318adfc5217SJeff Kirsher 1319adfc5217SJeff Kirsher /* 1320adfc5217SJeff Kirsher * Event queue (EQ or event ring) MC hsi 1321adfc5217SJeff Kirsher * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1322adfc5217SJeff Kirsher */ 1323adfc5217SJeff Kirsher #define NUM_EQ_PAGES 1 1324adfc5217SJeff Kirsher #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1325adfc5217SJeff Kirsher #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1326adfc5217SJeff Kirsher #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1327adfc5217SJeff Kirsher #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1328adfc5217SJeff Kirsher #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1329adfc5217SJeff Kirsher 1330adfc5217SJeff Kirsher /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1331adfc5217SJeff Kirsher #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1332adfc5217SJeff Kirsher (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1333adfc5217SJeff Kirsher 1334adfc5217SJeff Kirsher /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1335adfc5217SJeff Kirsher #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1336adfc5217SJeff Kirsher 1337adfc5217SJeff Kirsher #define BNX2X_EQ_INDEX \ 1338adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 1339adfc5217SJeff Kirsher index_values[HC_SP_INDEX_EQ_CONS]) 1340adfc5217SJeff Kirsher 1341adfc5217SJeff Kirsher /* This is a data that will be used to create a link report message. 1342adfc5217SJeff Kirsher * We will keep the data used for the last link report in order 1343adfc5217SJeff Kirsher * to prevent reporting the same link parameters twice. 1344adfc5217SJeff Kirsher */ 1345adfc5217SJeff Kirsher struct bnx2x_link_report_data { 1346adfc5217SJeff Kirsher u16 line_speed; /* Effective line speed */ 1347adfc5217SJeff Kirsher unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1348adfc5217SJeff Kirsher }; 1349adfc5217SJeff Kirsher 1350adfc5217SJeff Kirsher enum { 1351adfc5217SJeff Kirsher BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1352adfc5217SJeff Kirsher BNX2X_LINK_REPORT_LINK_DOWN, 1353adfc5217SJeff Kirsher BNX2X_LINK_REPORT_RX_FC_ON, 1354adfc5217SJeff Kirsher BNX2X_LINK_REPORT_TX_FC_ON, 1355adfc5217SJeff Kirsher }; 1356adfc5217SJeff Kirsher 1357adfc5217SJeff Kirsher enum { 1358adfc5217SJeff Kirsher BNX2X_PORT_QUERY_IDX, 1359adfc5217SJeff Kirsher BNX2X_PF_QUERY_IDX, 136050f0a562SBarak Witkowski BNX2X_FCOE_QUERY_IDX, 1361adfc5217SJeff Kirsher BNX2X_FIRST_QUEUE_QUERY_IDX, 1362adfc5217SJeff Kirsher }; 1363adfc5217SJeff Kirsher 1364adfc5217SJeff Kirsher struct bnx2x_fw_stats_req { 1365adfc5217SJeff Kirsher struct stats_query_header hdr; 136650f0a562SBarak Witkowski struct stats_query_entry query[FP_SB_MAX_E1x+ 136750f0a562SBarak Witkowski BNX2X_FIRST_QUEUE_QUERY_IDX]; 1368adfc5217SJeff Kirsher }; 1369adfc5217SJeff Kirsher 1370adfc5217SJeff Kirsher struct bnx2x_fw_stats_data { 1371adfc5217SJeff Kirsher struct stats_counter storm_counters; 1372adfc5217SJeff Kirsher struct per_port_stats port; 1373adfc5217SJeff Kirsher struct per_pf_stats pf; 137450f0a562SBarak Witkowski struct fcoe_statistics_params fcoe; 1375adfc5217SJeff Kirsher struct per_queue_stats queue_stats[1]; 1376adfc5217SJeff Kirsher }; 1377adfc5217SJeff Kirsher 1378adfc5217SJeff Kirsher /* Public slow path states */ 1379230bb0f3SYuval Mintz enum sp_rtnl_flag { 1380adfc5217SJeff Kirsher BNX2X_SP_RTNL_SETUP_TC, 1381adfc5217SJeff Kirsher BNX2X_SP_RTNL_TX_TIMEOUT, 13828304859aSAriel Elior BNX2X_SP_RTNL_FAN_FAILURE, 13838395be5eSAriel Elior BNX2X_SP_RTNL_AFEX_F_UPDATE, 13848395be5eSAriel Elior BNX2X_SP_RTNL_ENABLE_SRIOV, 1385381ac16bSAriel Elior BNX2X_SP_RTNL_VFPF_MCAST, 138678c3bcc5SAriel Elior BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 13878b09be5fSYuval Mintz BNX2X_SP_RTNL_RX_MODE, 13883ec9f9caSAriel Elior BNX2X_SP_RTNL_HYPERVISOR_VLAN, 138907b4eb3bSDmitry Kravkov BNX2X_SP_RTNL_TX_STOP, 139042f8277fSYuval Mintz BNX2X_SP_RTNL_GET_DRV_VERSION, 1391adfc5217SJeff Kirsher }; 1392adfc5217SJeff Kirsher 1393370d4a26SYuval Mintz enum bnx2x_iov_flag { 1394370d4a26SYuval Mintz BNX2X_IOV_HANDLE_VF_MSG, 1395370d4a26SYuval Mintz BNX2X_IOV_HANDLE_FLR, 1396370d4a26SYuval Mintz }; 1397370d4a26SYuval Mintz 1398452427b0SYuval Mintz struct bnx2x_prev_path_list { 13997fa6f340SYuval Mintz struct list_head list; 1400452427b0SYuval Mintz u8 bus; 1401452427b0SYuval Mintz u8 slot; 1402452427b0SYuval Mintz u8 path; 14037fa6f340SYuval Mintz u8 aer; 1404c63da990SBarak Witkowski u8 undi; 1405452427b0SYuval Mintz }; 1406452427b0SYuval Mintz 140715192a8cSBarak Witkowski struct bnx2x_sp_objs { 140815192a8cSBarak Witkowski /* MACs object */ 140915192a8cSBarak Witkowski struct bnx2x_vlan_mac_obj mac_obj; 141015192a8cSBarak Witkowski 141115192a8cSBarak Witkowski /* Queue State object */ 141215192a8cSBarak Witkowski struct bnx2x_queue_sp_obj q_obj; 141315192a8cSBarak Witkowski }; 141415192a8cSBarak Witkowski 141515192a8cSBarak Witkowski struct bnx2x_fp_stats { 141615192a8cSBarak Witkowski struct tstorm_per_queue_stats old_tclient; 141715192a8cSBarak Witkowski struct ustorm_per_queue_stats old_uclient; 141815192a8cSBarak Witkowski struct xstorm_per_queue_stats old_xclient; 141915192a8cSBarak Witkowski struct bnx2x_eth_q_stats eth_q_stats; 142015192a8cSBarak Witkowski struct bnx2x_eth_q_stats_old eth_q_stats_old; 142115192a8cSBarak Witkowski }; 142215192a8cSBarak Witkowski 14237609647eSYuval Mintz enum { 14247609647eSYuval Mintz SUB_MF_MODE_UNKNOWN = 0, 14257609647eSYuval Mintz SUB_MF_MODE_UFP, 142683bad206SYuval Mintz SUB_MF_MODE_NPAR1_DOT_5, 14277609647eSYuval Mintz }; 14287609647eSYuval Mintz 1429adfc5217SJeff Kirsher struct bnx2x { 1430adfc5217SJeff Kirsher /* Fields used in the tx and intr/napi performance paths 1431adfc5217SJeff Kirsher * are grouped together in the beginning of the structure 1432adfc5217SJeff Kirsher */ 1433adfc5217SJeff Kirsher struct bnx2x_fastpath *fp; 143415192a8cSBarak Witkowski struct bnx2x_sp_objs *sp_objs; 143515192a8cSBarak Witkowski struct bnx2x_fp_stats *fp_stats; 143665565884SMerav Sicron struct bnx2x_fp_txdata *bnx2x_txq; 1437adfc5217SJeff Kirsher void __iomem *regview; 1438adfc5217SJeff Kirsher void __iomem *doorbells; 1439adfc5217SJeff Kirsher u16 db_size; 1440adfc5217SJeff Kirsher 1441adfc5217SJeff Kirsher u8 pf_num; /* absolute PF number */ 1442adfc5217SJeff Kirsher u8 pfid; /* per-path PF number */ 1443adfc5217SJeff Kirsher int base_fw_ndsb; /**/ 1444adfc5217SJeff Kirsher #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1445adfc5217SJeff Kirsher #define BP_PORT(bp) (bp->pfid & 1) 1446adfc5217SJeff Kirsher #define BP_FUNC(bp) (bp->pfid) 1447adfc5217SJeff Kirsher #define BP_ABS_FUNC(bp) (bp->pf_num) 14488decf868SDavid S. Miller #define BP_VN(bp) ((bp)->pfid >> 1) 14498decf868SDavid S. Miller #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 14508decf868SDavid S. Miller #define BP_L_ID(bp) (BP_VN(bp) << 2) 14518decf868SDavid S. Miller #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 14528decf868SDavid S. Miller (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 14538decf868SDavid S. Miller #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1454adfc5217SJeff Kirsher 14556411280aSAriel Elior #ifdef CONFIG_BNX2X_SRIOV 14561d6f3cd8SDmitry Kravkov /* protects vf2pf mailbox from simultaneous access */ 14571d6f3cd8SDmitry Kravkov struct mutex vf2pf_mutex; 14581ab4434cSAriel Elior /* vf pf channel mailbox contains request and response buffers */ 14591ab4434cSAriel Elior struct bnx2x_vf_mbx_msg *vf2pf_mbox; 14601ab4434cSAriel Elior dma_addr_t vf2pf_mbox_mapping; 14611ab4434cSAriel Elior 1462be1f1ffaSAriel Elior /* we set aside a copy of the acquire response */ 1463be1f1ffaSAriel Elior struct pfvf_acquire_resp_tlv acquire_resp; 1464be1f1ffaSAriel Elior 1465abc5a021SAriel Elior /* bulletin board for messages from pf to vf */ 1466abc5a021SAriel Elior union pf_vf_bulletin *pf2vf_bulletin; 1467abc5a021SAriel Elior dma_addr_t pf2vf_bulletin_mapping; 1468abc5a021SAriel Elior 14696495d15aSDmitry Kravkov union pf_vf_bulletin shadow_bulletin; 1470abc5a021SAriel Elior struct pf_vf_bulletin_content old_bulletin; 14713c76feffSAriel Elior 14723c76feffSAriel Elior u16 requested_nr_virtfn; 14736411280aSAriel Elior #endif /* CONFIG_BNX2X_SRIOV */ 1474abc5a021SAriel Elior 1475adfc5217SJeff Kirsher struct net_device *dev; 1476adfc5217SJeff Kirsher struct pci_dev *pdev; 1477adfc5217SJeff Kirsher 1478adfc5217SJeff Kirsher const struct iro *iro_arr; 1479adfc5217SJeff Kirsher #define IRO (bp->iro_arr) 1480adfc5217SJeff Kirsher 1481adfc5217SJeff Kirsher enum bnx2x_recovery_state recovery_state; 1482adfc5217SJeff Kirsher int is_leader; 1483adfc5217SJeff Kirsher struct msix_entry *msix_table; 1484adfc5217SJeff Kirsher 1485adfc5217SJeff Kirsher int tx_ring_size; 1486adfc5217SJeff Kirsher 1487adfc5217SJeff Kirsher /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1488adfc5217SJeff Kirsher #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1489adfc5217SJeff Kirsher #define ETH_MIN_PACKET_SIZE 60 1490adfc5217SJeff Kirsher #define ETH_MAX_PACKET_SIZE 1500 1491adfc5217SJeff Kirsher #define ETH_MAX_JUMBO_PACKET_SIZE 9600 1492621b4d66SDmitry Kravkov /* TCP with Timestamp Option (32) + IPv6 (40) */ 1493621b4d66SDmitry Kravkov #define ETH_MAX_TPA_HEADER_SIZE 72 1494adfc5217SJeff Kirsher 14959927b514SDmitry Kravkov /* Max supported alignment is 256 (8 shift) 14969927b514SDmitry Kravkov * minimal alignment shift 6 is optimal for 57xxx HW performance 14979927b514SDmitry Kravkov */ 14989927b514SDmitry Kravkov #define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT)) 1499e52fcb24SEric Dumazet 1500e52fcb24SEric Dumazet /* FW uses 2 Cache lines Alignment for start packet and size 1501e52fcb24SEric Dumazet * 1502e52fcb24SEric Dumazet * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1503e52fcb24SEric Dumazet * at the end of skb->data, to avoid wasting a full cache line. 1504e52fcb24SEric Dumazet * This reduces memory use (skb->truesize). 1505e52fcb24SEric Dumazet */ 1506e52fcb24SEric Dumazet #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1507e52fcb24SEric Dumazet 1508e52fcb24SEric Dumazet #define BNX2X_FW_RX_ALIGN_END \ 1509f57b07c0SJoren Van Onder max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1510e52fcb24SEric Dumazet SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1511e52fcb24SEric Dumazet 1512adfc5217SJeff Kirsher #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1513adfc5217SJeff Kirsher 1514adfc5217SJeff Kirsher struct host_sp_status_block *def_status_blk; 1515adfc5217SJeff Kirsher #define DEF_SB_IGU_ID 16 1516adfc5217SJeff Kirsher #define DEF_SB_ID HC_SP_SB_ID 1517adfc5217SJeff Kirsher __le16 def_idx; 1518adfc5217SJeff Kirsher __le16 def_att_idx; 1519adfc5217SJeff Kirsher u32 attn_state; 1520adfc5217SJeff Kirsher struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1521adfc5217SJeff Kirsher 1522adfc5217SJeff Kirsher /* slow path ring */ 1523adfc5217SJeff Kirsher struct eth_spe *spq; 1524adfc5217SJeff Kirsher dma_addr_t spq_mapping; 1525adfc5217SJeff Kirsher u16 spq_prod_idx; 1526adfc5217SJeff Kirsher struct eth_spe *spq_prod_bd; 1527adfc5217SJeff Kirsher struct eth_spe *spq_last_bd; 1528adfc5217SJeff Kirsher __le16 *dsb_sp_prod; 1529adfc5217SJeff Kirsher atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1530adfc5217SJeff Kirsher /* used to synchronize spq accesses */ 1531adfc5217SJeff Kirsher spinlock_t spq_lock; 1532adfc5217SJeff Kirsher 1533adfc5217SJeff Kirsher /* event queue */ 1534adfc5217SJeff Kirsher union event_ring_elem *eq_ring; 1535adfc5217SJeff Kirsher dma_addr_t eq_mapping; 1536adfc5217SJeff Kirsher u16 eq_prod; 1537adfc5217SJeff Kirsher u16 eq_cons; 1538adfc5217SJeff Kirsher __le16 *eq_cons_sb; 1539adfc5217SJeff Kirsher atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1540adfc5217SJeff Kirsher 1541adfc5217SJeff Kirsher /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1542adfc5217SJeff Kirsher u16 stats_pending; 1543adfc5217SJeff Kirsher /* Counter for completed statistics ramrods */ 1544adfc5217SJeff Kirsher u16 stats_comp; 1545adfc5217SJeff Kirsher 1546adfc5217SJeff Kirsher /* End of fields used in the performance code paths */ 1547adfc5217SJeff Kirsher 1548adfc5217SJeff Kirsher int panic; 1549adfc5217SJeff Kirsher int msg_enable; 1550adfc5217SJeff Kirsher 1551adfc5217SJeff Kirsher u32 flags; 1552adfc5217SJeff Kirsher #define PCIX_FLAG (1 << 0) 1553adfc5217SJeff Kirsher #define PCI_32BIT_FLAG (1 << 1) 1554adfc5217SJeff Kirsher #define ONE_PORT_FLAG (1 << 2) 1555adfc5217SJeff Kirsher #define NO_WOL_FLAG (1 << 3) 1556adfc5217SJeff Kirsher #define USING_MSIX_FLAG (1 << 5) 1557adfc5217SJeff Kirsher #define USING_MSI_FLAG (1 << 6) 1558adfc5217SJeff Kirsher #define DISABLE_MSI_FLAG (1 << 7) 1559adfc5217SJeff Kirsher #define NO_MCP_FLAG (1 << 9) 1560adfc5217SJeff Kirsher #define MF_FUNC_DIS (1 << 11) 1561adfc5217SJeff Kirsher #define OWN_CNIC_IRQ (1 << 12) 1562adfc5217SJeff Kirsher #define NO_ISCSI_OOO_FLAG (1 << 13) 1563adfc5217SJeff Kirsher #define NO_ISCSI_FLAG (1 << 14) 1564adfc5217SJeff Kirsher #define NO_FCOE_FLAG (1 << 15) 15650e898dd7SBarak Witkowski #define BC_SUPPORTS_PFC_STATS (1 << 17) 1566c14db202SYuval Mintz #define TX_SWITCHING (1 << 18) 15672e499d3cSBarak Witkowski #define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 156830a5de77SDmitry Kravkov #define USING_SINGLE_MSIX_FLAG (1 << 20) 15699876879fSBarak Witkowski #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 15701ab4434cSAriel Elior #define IS_VF_FLAG (1 << 22) 15710c23ad37SYuval Mintz #define BC_SUPPORTS_RMMOD_CMD (1 << 23) 15720c23ad37SYuval Mintz #define HAS_PHYS_PORT_ID (1 << 24) 15730c23ad37SYuval Mintz #define AER_ENABLED (1 << 25) 15740c23ad37SYuval Mintz #define PTP_SUPPORTED (1 << 26) 15750c23ad37SYuval Mintz #define TX_TIMESTAMPING_EN (1 << 27) 15761ab4434cSAriel Elior 15771ab4434cSAriel Elior #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 15786411280aSAriel Elior 15796411280aSAriel Elior #ifdef CONFIG_BNX2X_SRIOV 15801ab4434cSAriel Elior #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 15811ab4434cSAriel Elior #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 15826411280aSAriel Elior #else 15836411280aSAriel Elior #define IS_VF(bp) false 15846411280aSAriel Elior #define IS_PF(bp) true 15856411280aSAriel Elior #endif 1586adfc5217SJeff Kirsher 1587adfc5217SJeff Kirsher #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1588adfc5217SJeff Kirsher #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1589adfc5217SJeff Kirsher #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1590adfc5217SJeff Kirsher 159155c11941SMerav Sicron u8 cnic_support; 159255c11941SMerav Sicron bool cnic_enabled; 159355c11941SMerav Sicron bool cnic_loaded; 15944bd9b0ffSMichael Chan struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 159555c11941SMerav Sicron 159655c11941SMerav Sicron /* Flag that indicates that we can start looking for FCoE L2 queue 159755c11941SMerav Sicron * completions in the default status block. 159855c11941SMerav Sicron */ 159955c11941SMerav Sicron bool fcoe_init; 160055c11941SMerav Sicron 1601adfc5217SJeff Kirsher int mrrs; 1602adfc5217SJeff Kirsher 1603adfc5217SJeff Kirsher struct delayed_work sp_task; 1604370d4a26SYuval Mintz struct delayed_work iov_task; 1605370d4a26SYuval Mintz 1606fd1fc79dSAriel Elior atomic_t interrupt_occurred; 1607adfc5217SJeff Kirsher struct delayed_work sp_rtnl_task; 1608adfc5217SJeff Kirsher 1609adfc5217SJeff Kirsher struct delayed_work period_task; 1610adfc5217SJeff Kirsher struct timer_list timer; 1611adfc5217SJeff Kirsher int current_interval; 1612adfc5217SJeff Kirsher 1613adfc5217SJeff Kirsher u16 fw_seq; 1614adfc5217SJeff Kirsher u16 fw_drv_pulse_wr_seq; 1615adfc5217SJeff Kirsher u32 func_stx; 1616adfc5217SJeff Kirsher 1617adfc5217SJeff Kirsher struct link_params link_params; 1618adfc5217SJeff Kirsher struct link_vars link_vars; 1619adfc5217SJeff Kirsher u32 link_cnt; 1620adfc5217SJeff Kirsher struct bnx2x_link_report_data last_reported_link; 1621adfc5217SJeff Kirsher 1622adfc5217SJeff Kirsher struct mdio_if_info mdio; 1623adfc5217SJeff Kirsher 1624adfc5217SJeff Kirsher struct bnx2x_common common; 1625adfc5217SJeff Kirsher struct bnx2x_port port; 1626adfc5217SJeff Kirsher 1627b475d78fSYuval Mintz struct cmng_init cmng; 1628b475d78fSYuval Mintz 1629adfc5217SJeff Kirsher u32 mf_config[E1HVN_MAX]; 1630a3348722SBarak Witkowski u32 mf_ext_config; 1631adfc5217SJeff Kirsher u32 path_has_ovlan; /* E3 */ 1632adfc5217SJeff Kirsher u16 mf_ov; 1633adfc5217SJeff Kirsher u8 mf_mode; 1634adfc5217SJeff Kirsher #define IS_MF(bp) (bp->mf_mode != 0) 1635adfc5217SJeff Kirsher #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1636adfc5217SJeff Kirsher #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1637a3348722SBarak Witkowski #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 16387609647eSYuval Mintz u8 mf_sub_mode; 16397609647eSYuval Mintz #define IS_MF_UFP(bp) (IS_MF_SD(bp) && \ 16407609647eSYuval Mintz bp->mf_sub_mode == SUB_MF_MODE_UFP) 1641adfc5217SJeff Kirsher 1642adfc5217SJeff Kirsher u8 wol; 1643adfc5217SJeff Kirsher 1644adfc5217SJeff Kirsher int rx_ring_size; 1645adfc5217SJeff Kirsher 1646adfc5217SJeff Kirsher u16 tx_quick_cons_trip_int; 1647adfc5217SJeff Kirsher u16 tx_quick_cons_trip; 1648adfc5217SJeff Kirsher u16 tx_ticks_int; 1649adfc5217SJeff Kirsher u16 tx_ticks; 1650adfc5217SJeff Kirsher 1651adfc5217SJeff Kirsher u16 rx_quick_cons_trip_int; 1652adfc5217SJeff Kirsher u16 rx_quick_cons_trip; 1653adfc5217SJeff Kirsher u16 rx_ticks_int; 1654adfc5217SJeff Kirsher u16 rx_ticks; 1655adfc5217SJeff Kirsher /* Maximal coalescing timeout in us */ 16566802516eSDmitry Kravkov #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR) 1657adfc5217SJeff Kirsher 1658adfc5217SJeff Kirsher u32 lin_cnt; 1659adfc5217SJeff Kirsher 1660adfc5217SJeff Kirsher u16 state; 1661adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSED 0 1662adfc5217SJeff Kirsher #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1663adfc5217SJeff Kirsher #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1664adfc5217SJeff Kirsher #define BNX2X_STATE_OPEN 0x3000 1665adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1666adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1667adfc5217SJeff Kirsher 1668adfc5217SJeff Kirsher #define BNX2X_STATE_DIAG 0xe000 1669adfc5217SJeff Kirsher #define BNX2X_STATE_ERROR 0xf000 1670adfc5217SJeff Kirsher 1671adfc5217SJeff Kirsher #define BNX2X_MAX_PRIORITY 8 1672adfc5217SJeff Kirsher int num_queues; 167355c11941SMerav Sicron uint num_ethernet_queues; 167455c11941SMerav Sicron uint num_cnic_queues; 1675adfc5217SJeff Kirsher int disable_tpa; 1676adfc5217SJeff Kirsher 1677adfc5217SJeff Kirsher u32 rx_mode; 1678adfc5217SJeff Kirsher #define BNX2X_RX_MODE_NONE 0 1679adfc5217SJeff Kirsher #define BNX2X_RX_MODE_NORMAL 1 1680adfc5217SJeff Kirsher #define BNX2X_RX_MODE_ALLMULTI 2 1681adfc5217SJeff Kirsher #define BNX2X_RX_MODE_PROMISC 3 1682adfc5217SJeff Kirsher #define BNX2X_MAX_MULTICAST 64 1683adfc5217SJeff Kirsher 1684adfc5217SJeff Kirsher u8 igu_dsb_id; 1685adfc5217SJeff Kirsher u8 igu_base_sb; 1686adfc5217SJeff Kirsher u8 igu_sb_cnt; 168755c11941SMerav Sicron u8 min_msix_vec_cnt; 168865565884SMerav Sicron 16891ab4434cSAriel Elior u32 igu_base_addr; 1690adfc5217SJeff Kirsher dma_addr_t def_status_blk_mapping; 1691adfc5217SJeff Kirsher 1692adfc5217SJeff Kirsher struct bnx2x_slowpath *slowpath; 1693adfc5217SJeff Kirsher dma_addr_t slowpath_mapping; 1694adfc5217SJeff Kirsher 169542f8277fSYuval Mintz /* Mechanism protecting the drv_info_to_mcp */ 169642f8277fSYuval Mintz struct mutex drv_info_mutex; 169742f8277fSYuval Mintz bool drv_info_mng_owner; 169842f8277fSYuval Mintz 1699adfc5217SJeff Kirsher /* Total number of FW statistics requests */ 1700adfc5217SJeff Kirsher u8 fw_stats_num; 1701adfc5217SJeff Kirsher 1702adfc5217SJeff Kirsher /* 1703adfc5217SJeff Kirsher * This is a memory buffer that will contain both statistics 1704adfc5217SJeff Kirsher * ramrod request and data. 1705adfc5217SJeff Kirsher */ 1706adfc5217SJeff Kirsher void *fw_stats; 1707adfc5217SJeff Kirsher dma_addr_t fw_stats_mapping; 1708adfc5217SJeff Kirsher 1709adfc5217SJeff Kirsher /* 1710adfc5217SJeff Kirsher * FW statistics request shortcut (points at the 1711adfc5217SJeff Kirsher * beginning of fw_stats buffer). 1712adfc5217SJeff Kirsher */ 1713adfc5217SJeff Kirsher struct bnx2x_fw_stats_req *fw_stats_req; 1714adfc5217SJeff Kirsher dma_addr_t fw_stats_req_mapping; 1715adfc5217SJeff Kirsher int fw_stats_req_sz; 1716adfc5217SJeff Kirsher 1717adfc5217SJeff Kirsher /* 17184907cb7bSAnatol Pomozov * FW statistics data shortcut (points at the beginning of 1719adfc5217SJeff Kirsher * fw_stats buffer + fw_stats_req_sz). 1720adfc5217SJeff Kirsher */ 1721adfc5217SJeff Kirsher struct bnx2x_fw_stats_data *fw_stats_data; 1722adfc5217SJeff Kirsher dma_addr_t fw_stats_data_mapping; 1723adfc5217SJeff Kirsher int fw_stats_data_sz; 1724adfc5217SJeff Kirsher 1725b9871bcfSAriel Elior /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB 1726a052997eSMerav Sicron * context size we need 8 ILT entries. 1727a052997eSMerav Sicron */ 1728b9871bcfSAriel Elior #define ILT_MAX_L2_LINES 32 1729a052997eSMerav Sicron struct hw_context context[ILT_MAX_L2_LINES]; 1730adfc5217SJeff Kirsher 1731adfc5217SJeff Kirsher struct bnx2x_ilt *ilt; 1732adfc5217SJeff Kirsher #define BP_ILT(bp) ((bp)->ilt) 1733adfc5217SJeff Kirsher #define ILT_MAX_LINES 256 1734adfc5217SJeff Kirsher /* 1735adfc5217SJeff Kirsher * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1736adfc5217SJeff Kirsher * to CNIC. 1737adfc5217SJeff Kirsher */ 173855c11941SMerav Sicron #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1739adfc5217SJeff Kirsher 1740adfc5217SJeff Kirsher /* 1741adfc5217SJeff Kirsher * Maximum CID count that might be required by the bnx2x: 174237ae41a9SMerav Sicron * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1743adfc5217SJeff Kirsher */ 1744f78afb35SMichael Chan 174537ae41a9SMerav Sicron #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1746f78afb35SMichael Chan + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 174737ae41a9SMerav Sicron #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1748f78afb35SMichael Chan + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1749adfc5217SJeff Kirsher #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1750adfc5217SJeff Kirsher ILT_PAGE_CIDS)) 1751adfc5217SJeff Kirsher 1752adfc5217SJeff Kirsher int qm_cid_count; 1753adfc5217SJeff Kirsher 17547964211dSYuval Mintz bool dropless_fc; 1755adfc5217SJeff Kirsher 1756adfc5217SJeff Kirsher void *t2; 1757adfc5217SJeff Kirsher dma_addr_t t2_mapping; 1758adfc5217SJeff Kirsher struct cnic_ops __rcu *cnic_ops; 1759adfc5217SJeff Kirsher void *cnic_data; 1760adfc5217SJeff Kirsher u32 cnic_tag; 1761adfc5217SJeff Kirsher struct cnic_eth_dev cnic_eth_dev; 1762adfc5217SJeff Kirsher union host_hc_status_block cnic_sb; 1763adfc5217SJeff Kirsher dma_addr_t cnic_sb_mapping; 1764adfc5217SJeff Kirsher struct eth_spe *cnic_kwq; 1765adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_prod; 1766adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_cons; 1767adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_last; 1768adfc5217SJeff Kirsher u16 cnic_kwq_pending; 1769adfc5217SJeff Kirsher u16 cnic_spq_pending; 1770adfc5217SJeff Kirsher u8 fip_mac[ETH_ALEN]; 1771adfc5217SJeff Kirsher struct mutex cnic_mutex; 1772adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1773adfc5217SJeff Kirsher 177416a5fd92SYuval Mintz /* Start index of the "special" (CNIC related) L2 clients */ 1775adfc5217SJeff Kirsher u8 cnic_base_cl_id; 1776adfc5217SJeff Kirsher 1777adfc5217SJeff Kirsher int dmae_ready; 1778adfc5217SJeff Kirsher /* used to synchronize dmae accesses */ 1779adfc5217SJeff Kirsher spinlock_t dmae_lock; 1780adfc5217SJeff Kirsher 1781adfc5217SJeff Kirsher /* used to protect the FW mail box */ 1782adfc5217SJeff Kirsher struct mutex fw_mb_mutex; 1783adfc5217SJeff Kirsher 1784adfc5217SJeff Kirsher /* used to synchronize stats collecting */ 1785adfc5217SJeff Kirsher int stats_state; 1786adfc5217SJeff Kirsher 1787adfc5217SJeff Kirsher /* used for synchronization of concurrent threads statistics handling */ 1788c6e36d8cSYuval Mintz struct semaphore stats_lock; 1789adfc5217SJeff Kirsher 1790adfc5217SJeff Kirsher /* used by dmae command loader */ 1791adfc5217SJeff Kirsher struct dmae_command stats_dmae; 1792adfc5217SJeff Kirsher int executer_idx; 1793adfc5217SJeff Kirsher 1794adfc5217SJeff Kirsher u16 stats_counter; 1795adfc5217SJeff Kirsher struct bnx2x_eth_stats eth_stats; 1796cb4dca27SYuval Mintz struct host_func_stats func_stats; 17971355b704SMintz Yuval struct bnx2x_eth_stats_old eth_stats_old; 17981355b704SMintz Yuval struct bnx2x_net_stats_old net_stats_old; 17991355b704SMintz Yuval struct bnx2x_fw_port_stats_old fw_stats_old; 18001355b704SMintz Yuval bool stats_init; 1801adfc5217SJeff Kirsher 1802adfc5217SJeff Kirsher struct z_stream_s *strm; 1803adfc5217SJeff Kirsher void *gunzip_buf; 1804adfc5217SJeff Kirsher dma_addr_t gunzip_mapping; 1805adfc5217SJeff Kirsher int gunzip_outlen; 1806adfc5217SJeff Kirsher #define FW_BUF_SIZE 0x8000 1807adfc5217SJeff Kirsher #define GUNZIP_BUF(bp) (bp->gunzip_buf) 1808adfc5217SJeff Kirsher #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1809adfc5217SJeff Kirsher #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1810adfc5217SJeff Kirsher 1811adfc5217SJeff Kirsher struct raw_op *init_ops; 1812adfc5217SJeff Kirsher /* Init blocks offsets inside init_ops */ 1813adfc5217SJeff Kirsher u16 *init_ops_offsets; 1814adfc5217SJeff Kirsher /* Data blob - has 32 bit granularity */ 1815adfc5217SJeff Kirsher u32 *init_data; 1816adfc5217SJeff Kirsher u32 init_mode_flags; 1817adfc5217SJeff Kirsher #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1818adfc5217SJeff Kirsher /* Zipped PRAM blobs - raw data */ 1819adfc5217SJeff Kirsher const u8 *tsem_int_table_data; 1820adfc5217SJeff Kirsher const u8 *tsem_pram_data; 1821adfc5217SJeff Kirsher const u8 *usem_int_table_data; 1822adfc5217SJeff Kirsher const u8 *usem_pram_data; 1823adfc5217SJeff Kirsher const u8 *xsem_int_table_data; 1824adfc5217SJeff Kirsher const u8 *xsem_pram_data; 1825adfc5217SJeff Kirsher const u8 *csem_int_table_data; 1826adfc5217SJeff Kirsher const u8 *csem_pram_data; 1827adfc5217SJeff Kirsher #define INIT_OPS(bp) (bp->init_ops) 1828adfc5217SJeff Kirsher #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1829adfc5217SJeff Kirsher #define INIT_DATA(bp) (bp->init_data) 1830adfc5217SJeff Kirsher #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1831adfc5217SJeff Kirsher #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1832adfc5217SJeff Kirsher #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1833adfc5217SJeff Kirsher #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1834adfc5217SJeff Kirsher #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1835adfc5217SJeff Kirsher #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1836adfc5217SJeff Kirsher #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1837adfc5217SJeff Kirsher #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1838adfc5217SJeff Kirsher 1839adfc5217SJeff Kirsher #define PHY_FW_VER_LEN 20 1840adfc5217SJeff Kirsher char fw_ver[32]; 1841adfc5217SJeff Kirsher const struct firmware *firmware; 1842adfc5217SJeff Kirsher 1843290ca2bbSAriel Elior struct bnx2x_vfdb *vfdb; 1844290ca2bbSAriel Elior #define IS_SRIOV(bp) ((bp)->vfdb) 1845290ca2bbSAriel Elior 1846adfc5217SJeff Kirsher /* DCB support on/off */ 1847adfc5217SJeff Kirsher u16 dcb_state; 1848adfc5217SJeff Kirsher #define BNX2X_DCB_STATE_OFF 0 1849adfc5217SJeff Kirsher #define BNX2X_DCB_STATE_ON 1 1850adfc5217SJeff Kirsher 1851adfc5217SJeff Kirsher /* DCBX engine mode */ 1852adfc5217SJeff Kirsher int dcbx_enabled; 1853adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_OFF 0 1854adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1855adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1856adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_INVALID (-1) 1857adfc5217SJeff Kirsher 1858adfc5217SJeff Kirsher bool dcbx_mode_uset; 1859adfc5217SJeff Kirsher 1860adfc5217SJeff Kirsher struct bnx2x_config_dcbx_params dcbx_config_params; 1861adfc5217SJeff Kirsher struct bnx2x_dcbx_port_params dcbx_port_params; 1862adfc5217SJeff Kirsher int dcb_version; 1863adfc5217SJeff Kirsher 1864adfc5217SJeff Kirsher /* CAM credit pools */ 1865b56e9670SAriel Elior 1866b56e9670SAriel Elior /* used only in sriov */ 1867b56e9670SAriel Elior struct bnx2x_credit_pool_obj vlans_pool; 1868b56e9670SAriel Elior 1869adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj macs_pool; 1870adfc5217SJeff Kirsher 1871adfc5217SJeff Kirsher /* RX_MODE object */ 1872adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj rx_mode_obj; 1873adfc5217SJeff Kirsher 1874adfc5217SJeff Kirsher /* MCAST object */ 1875adfc5217SJeff Kirsher struct bnx2x_mcast_obj mcast_obj; 1876adfc5217SJeff Kirsher 1877adfc5217SJeff Kirsher /* RSS configuration object */ 1878adfc5217SJeff Kirsher struct bnx2x_rss_config_obj rss_conf_obj; 1879adfc5217SJeff Kirsher 1880adfc5217SJeff Kirsher /* Function State controlling object */ 1881adfc5217SJeff Kirsher struct bnx2x_func_sp_obj func_obj; 1882adfc5217SJeff Kirsher 1883adfc5217SJeff Kirsher unsigned long sp_state; 1884adfc5217SJeff Kirsher 1885adfc5217SJeff Kirsher /* operation indication for the sp_rtnl task */ 1886adfc5217SJeff Kirsher unsigned long sp_rtnl_state; 1887adfc5217SJeff Kirsher 1888370d4a26SYuval Mintz /* Indication of the IOV tasks */ 1889370d4a26SYuval Mintz unsigned long iov_task_state; 1890370d4a26SYuval Mintz 189116a5fd92SYuval Mintz /* DCBX Negotiation results */ 1892adfc5217SJeff Kirsher struct dcbx_features dcbx_local_feat; 1893adfc5217SJeff Kirsher u32 dcbx_error; 1894adfc5217SJeff Kirsher 1895adfc5217SJeff Kirsher #ifdef BCM_DCBNL 1896adfc5217SJeff Kirsher struct dcbx_features dcbx_remote_feat; 1897adfc5217SJeff Kirsher u32 dcbx_remote_flags; 1898adfc5217SJeff Kirsher #endif 1899a3348722SBarak Witkowski /* AFEX: store default vlan used */ 1900a3348722SBarak Witkowski int afex_def_vlan_tag; 1901a3348722SBarak Witkowski enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1902adfc5217SJeff Kirsher u32 pending_max; 1903adfc5217SJeff Kirsher 1904adfc5217SJeff Kirsher /* multiple tx classes of service */ 1905adfc5217SJeff Kirsher u8 max_cos; 1906adfc5217SJeff Kirsher 1907adfc5217SJeff Kirsher /* priority to cos mapping */ 1908adfc5217SJeff Kirsher u8 prio_to_cos[8]; 1909c3146eb6SDmitry Kravkov 1910c3146eb6SDmitry Kravkov int fp_array_size; 191107ba6af4SMiriam Shitrit u32 dump_preset_idx; 19123d7d562cSYuval Mintz 19133d7d562cSYuval Mintz u8 phys_port_id[ETH_ALEN]; 19146495d15aSDmitry Kravkov 1915eeed018cSMichal Kalderon /* PTP related context */ 1916eeed018cSMichal Kalderon struct ptp_clock *ptp_clock; 1917eeed018cSMichal Kalderon struct ptp_clock_info ptp_clock_info; 1918eeed018cSMichal Kalderon struct work_struct ptp_task; 1919eeed018cSMichal Kalderon struct cyclecounter cyclecounter; 1920eeed018cSMichal Kalderon struct timecounter timecounter; 1921eeed018cSMichal Kalderon bool timecounter_init_done; 1922eeed018cSMichal Kalderon struct sk_buff *ptp_tx_skb; 1923eeed018cSMichal Kalderon unsigned long ptp_tx_start; 1924eeed018cSMichal Kalderon bool hwtstamp_ioctl_called; 1925eeed018cSMichal Kalderon u16 tx_type; 1926eeed018cSMichal Kalderon u16 rx_filter; 1927eeed018cSMichal Kalderon 19286495d15aSDmitry Kravkov struct bnx2x_link_report_data vf_link_vars; 1929adfc5217SJeff Kirsher }; 1930adfc5217SJeff Kirsher 1931adfc5217SJeff Kirsher /* Tx queues may be less or equal to Rx queues */ 1932adfc5217SJeff Kirsher extern int num_queues; 1933adfc5217SJeff Kirsher #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 193455c11941SMerav Sicron #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 193565565884SMerav Sicron #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 193655c11941SMerav Sicron (bp)->num_cnic_queues) 1937adfc5217SJeff Kirsher #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1938adfc5217SJeff Kirsher 1939adfc5217SJeff Kirsher #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1940adfc5217SJeff Kirsher 1941adfc5217SJeff Kirsher #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1942adfc5217SJeff Kirsher /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1943adfc5217SJeff Kirsher 1944adfc5217SJeff Kirsher #define RSS_IPV4_CAP_MASK \ 1945adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1946adfc5217SJeff Kirsher 1947adfc5217SJeff Kirsher #define RSS_IPV4_TCP_CAP_MASK \ 1948adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1949adfc5217SJeff Kirsher 1950adfc5217SJeff Kirsher #define RSS_IPV6_CAP_MASK \ 1951adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1952adfc5217SJeff Kirsher 1953adfc5217SJeff Kirsher #define RSS_IPV6_TCP_CAP_MASK \ 1954adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1955adfc5217SJeff Kirsher 1956adfc5217SJeff Kirsher /* func init flags */ 1957adfc5217SJeff Kirsher #define FUNC_FLG_RSS 0x0001 1958adfc5217SJeff Kirsher #define FUNC_FLG_STATS 0x0002 1959adfc5217SJeff Kirsher /* removed FUNC_FLG_UNMATCHED 0x0004 */ 1960adfc5217SJeff Kirsher #define FUNC_FLG_TPA 0x0008 1961adfc5217SJeff Kirsher #define FUNC_FLG_SPQ 0x0010 1962adfc5217SJeff Kirsher #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1963b9871bcfSAriel Elior #define FUNC_FLG_LEADING_STATS 0x0040 1964adfc5217SJeff Kirsher struct bnx2x_func_init_params { 1965adfc5217SJeff Kirsher /* dma */ 1966adfc5217SJeff Kirsher dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1967adfc5217SJeff Kirsher dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1968adfc5217SJeff Kirsher 1969adfc5217SJeff Kirsher u16 func_flgs; 1970adfc5217SJeff Kirsher u16 func_id; /* abs fid */ 1971adfc5217SJeff Kirsher u16 pf_id; 1972adfc5217SJeff Kirsher u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1973adfc5217SJeff Kirsher }; 1974adfc5217SJeff Kirsher 197555c11941SMerav Sicron #define for_each_cnic_queue(bp, var) \ 197655c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 197755c11941SMerav Sicron (var)++) \ 197855c11941SMerav Sicron if (skip_queue(bp, var)) \ 197955c11941SMerav Sicron continue; \ 198055c11941SMerav Sicron else 198155c11941SMerav Sicron 1982adfc5217SJeff Kirsher #define for_each_eth_queue(bp, var) \ 1983adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1984adfc5217SJeff Kirsher 1985adfc5217SJeff Kirsher #define for_each_nondefault_eth_queue(bp, var) \ 1986adfc5217SJeff Kirsher for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1987adfc5217SJeff Kirsher 1988adfc5217SJeff Kirsher #define for_each_queue(bp, var) \ 1989adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1990adfc5217SJeff Kirsher if (skip_queue(bp, var)) \ 1991adfc5217SJeff Kirsher continue; \ 1992adfc5217SJeff Kirsher else 1993adfc5217SJeff Kirsher 1994adfc5217SJeff Kirsher /* Skip forwarding FP */ 199555c11941SMerav Sicron #define for_each_valid_rx_queue(bp, var) \ 199655c11941SMerav Sicron for ((var) = 0; \ 199755c11941SMerav Sicron (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 199855c11941SMerav Sicron BNX2X_NUM_ETH_QUEUES(bp)); \ 199955c11941SMerav Sicron (var)++) \ 200055c11941SMerav Sicron if (skip_rx_queue(bp, var)) \ 200155c11941SMerav Sicron continue; \ 200255c11941SMerav Sicron else 200355c11941SMerav Sicron 200455c11941SMerav Sicron #define for_each_rx_queue_cnic(bp, var) \ 200555c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 200655c11941SMerav Sicron (var)++) \ 200755c11941SMerav Sicron if (skip_rx_queue(bp, var)) \ 200855c11941SMerav Sicron continue; \ 200955c11941SMerav Sicron else 201055c11941SMerav Sicron 2011adfc5217SJeff Kirsher #define for_each_rx_queue(bp, var) \ 2012adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2013adfc5217SJeff Kirsher if (skip_rx_queue(bp, var)) \ 2014adfc5217SJeff Kirsher continue; \ 2015adfc5217SJeff Kirsher else 2016adfc5217SJeff Kirsher 2017adfc5217SJeff Kirsher /* Skip OOO FP */ 201855c11941SMerav Sicron #define for_each_valid_tx_queue(bp, var) \ 201955c11941SMerav Sicron for ((var) = 0; \ 202055c11941SMerav Sicron (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 202155c11941SMerav Sicron BNX2X_NUM_ETH_QUEUES(bp)); \ 202255c11941SMerav Sicron (var)++) \ 202355c11941SMerav Sicron if (skip_tx_queue(bp, var)) \ 202455c11941SMerav Sicron continue; \ 202555c11941SMerav Sicron else 202655c11941SMerav Sicron 202755c11941SMerav Sicron #define for_each_tx_queue_cnic(bp, var) \ 202855c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 202955c11941SMerav Sicron (var)++) \ 203055c11941SMerav Sicron if (skip_tx_queue(bp, var)) \ 203155c11941SMerav Sicron continue; \ 203255c11941SMerav Sicron else 203355c11941SMerav Sicron 2034adfc5217SJeff Kirsher #define for_each_tx_queue(bp, var) \ 2035adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2036adfc5217SJeff Kirsher if (skip_tx_queue(bp, var)) \ 2037adfc5217SJeff Kirsher continue; \ 2038adfc5217SJeff Kirsher else 2039adfc5217SJeff Kirsher 2040adfc5217SJeff Kirsher #define for_each_nondefault_queue(bp, var) \ 2041adfc5217SJeff Kirsher for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2042adfc5217SJeff Kirsher if (skip_queue(bp, var)) \ 2043adfc5217SJeff Kirsher continue; \ 2044adfc5217SJeff Kirsher else 2045adfc5217SJeff Kirsher 2046adfc5217SJeff Kirsher #define for_each_cos_in_tx_queue(fp, var) \ 2047adfc5217SJeff Kirsher for ((var) = 0; (var) < (fp)->max_cos; (var)++) 2048adfc5217SJeff Kirsher 2049adfc5217SJeff Kirsher /* skip rx queue 2050adfc5217SJeff Kirsher * if FCOE l2 support is disabled and this is the fcoe L2 queue 2051adfc5217SJeff Kirsher */ 2052adfc5217SJeff Kirsher #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2053adfc5217SJeff Kirsher 2054adfc5217SJeff Kirsher /* skip tx queue 2055adfc5217SJeff Kirsher * if FCOE l2 support is disabled and this is the fcoe L2 queue 2056adfc5217SJeff Kirsher */ 2057adfc5217SJeff Kirsher #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2058adfc5217SJeff Kirsher 2059adfc5217SJeff Kirsher #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2060adfc5217SJeff Kirsher 2061adfc5217SJeff Kirsher /** 2062adfc5217SJeff Kirsher * bnx2x_set_mac_one - configure a single MAC address 2063adfc5217SJeff Kirsher * 2064adfc5217SJeff Kirsher * @bp: driver handle 2065adfc5217SJeff Kirsher * @mac: MAC to configure 2066adfc5217SJeff Kirsher * @obj: MAC object handle 2067adfc5217SJeff Kirsher * @set: if 'true' add a new MAC, otherwise - delete 2068adfc5217SJeff Kirsher * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 2069adfc5217SJeff Kirsher * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 2070adfc5217SJeff Kirsher * 2071adfc5217SJeff Kirsher * Configures one MAC according to provided parameters or continues the 2072adfc5217SJeff Kirsher * execution of previously scheduled commands if RAMROD_CONT is set in 2073adfc5217SJeff Kirsher * ramrod_flags. 2074adfc5217SJeff Kirsher * 2075adfc5217SJeff Kirsher * Returns zero if operation has successfully completed, a positive value if the 2076adfc5217SJeff Kirsher * operation has been successfully scheduled and a negative - if a requested 2077adfc5217SJeff Kirsher * operations has failed. 2078adfc5217SJeff Kirsher */ 2079adfc5217SJeff Kirsher int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 2080adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *obj, bool set, 2081adfc5217SJeff Kirsher int mac_type, unsigned long *ramrod_flags); 2082adfc5217SJeff Kirsher /** 2083adfc5217SJeff Kirsher * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 2084adfc5217SJeff Kirsher * 2085adfc5217SJeff Kirsher * @bp: driver handle 2086adfc5217SJeff Kirsher * @mac_obj: MAC object handle 2087adfc5217SJeff Kirsher * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 2088adfc5217SJeff Kirsher * @wait_for_comp: if 'true' block until completion 2089adfc5217SJeff Kirsher * 2090adfc5217SJeff Kirsher * Deletes all MACs of the specific type (e.g. ETH, UC list). 2091adfc5217SJeff Kirsher * 2092adfc5217SJeff Kirsher * Returns zero if operation has successfully completed, a positive value if the 2093adfc5217SJeff Kirsher * operation has been successfully scheduled and a negative - if a requested 2094adfc5217SJeff Kirsher * operations has failed. 2095adfc5217SJeff Kirsher */ 2096adfc5217SJeff Kirsher int bnx2x_del_all_macs(struct bnx2x *bp, 2097adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj, 2098adfc5217SJeff Kirsher int mac_type, bool wait_for_comp); 2099adfc5217SJeff Kirsher 2100adfc5217SJeff Kirsher /* Init Function API */ 2101adfc5217SJeff Kirsher void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 2102b93288d5SAriel Elior void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 2103b93288d5SAriel Elior u8 vf_valid, int fw_sb_id, int igu_sb_id); 2104adfc5217SJeff Kirsher int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 2105adfc5217SJeff Kirsher int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2106adfc5217SJeff Kirsher int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 2107adfc5217SJeff Kirsher int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2108adfc5217SJeff Kirsher void bnx2x_read_mf_cfg(struct bnx2x *bp); 2109adfc5217SJeff Kirsher 2110b56e9670SAriel Elior int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 2111adfc5217SJeff Kirsher 2112adfc5217SJeff Kirsher /* dmae */ 2113adfc5217SJeff Kirsher void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 2114adfc5217SJeff Kirsher void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 2115adfc5217SJeff Kirsher u32 len32); 2116adfc5217SJeff Kirsher void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 2117adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 2118adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 2119adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 2120adfc5217SJeff Kirsher bool with_comp, u8 comp_type); 2121adfc5217SJeff Kirsher 2122fd1fc79dSAriel Elior void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2123fd1fc79dSAriel Elior u8 src_type, u8 dst_type); 212432316a46SAriel Elior int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 212532316a46SAriel Elior u32 *comp); 2126fd1fc79dSAriel Elior 2127d16132ceSAriel Elior /* FLR related routines */ 2128d16132ceSAriel Elior u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 2129d16132ceSAriel Elior void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 2130d16132ceSAriel Elior int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 2131b56e9670SAriel Elior u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 2132d16132ceSAriel Elior int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 2133d16132ceSAriel Elior char *msg, u32 poll_cnt); 2134adfc5217SJeff Kirsher 2135adfc5217SJeff Kirsher void bnx2x_calc_fc_adv(struct bnx2x *bp); 2136adfc5217SJeff Kirsher int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 2137adfc5217SJeff Kirsher u32 data_hi, u32 data_lo, int cmd_type); 2138adfc5217SJeff Kirsher void bnx2x_update_coalesce(struct bnx2x *bp); 2139adfc5217SJeff Kirsher int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 2140adfc5217SJeff Kirsher 2141178135c1SDmitry Kravkov bool bnx2x_port_after_undi(struct bnx2x *bp); 2142178135c1SDmitry Kravkov 2143adfc5217SJeff Kirsher static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 2144adfc5217SJeff Kirsher int wait) 2145adfc5217SJeff Kirsher { 2146adfc5217SJeff Kirsher u32 val; 2147adfc5217SJeff Kirsher 2148adfc5217SJeff Kirsher do { 2149adfc5217SJeff Kirsher val = REG_RD(bp, reg); 2150adfc5217SJeff Kirsher if (val == expected) 2151adfc5217SJeff Kirsher break; 2152adfc5217SJeff Kirsher ms -= wait; 2153adfc5217SJeff Kirsher msleep(wait); 2154adfc5217SJeff Kirsher 2155adfc5217SJeff Kirsher } while (ms > 0); 2156adfc5217SJeff Kirsher 2157adfc5217SJeff Kirsher return val; 2158adfc5217SJeff Kirsher } 2159adfc5217SJeff Kirsher 2160b56e9670SAriel Elior void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 2161b56e9670SAriel Elior bool is_pf); 2162b56e9670SAriel Elior 2163adfc5217SJeff Kirsher #define BNX2X_ILT_ZALLOC(x, y, size) \ 2164ede23fa8SJoe Perches x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL) 2165adfc5217SJeff Kirsher 2166adfc5217SJeff Kirsher #define BNX2X_ILT_FREE(x, y, size) \ 2167adfc5217SJeff Kirsher do { \ 2168adfc5217SJeff Kirsher if (x) { \ 2169adfc5217SJeff Kirsher dma_free_coherent(&bp->pdev->dev, size, x, y); \ 2170adfc5217SJeff Kirsher x = NULL; \ 2171adfc5217SJeff Kirsher y = 0; \ 2172adfc5217SJeff Kirsher } \ 2173adfc5217SJeff Kirsher } while (0) 2174adfc5217SJeff Kirsher 2175adfc5217SJeff Kirsher #define ILOG2(x) (ilog2((x))) 2176adfc5217SJeff Kirsher 2177adfc5217SJeff Kirsher #define ILT_NUM_PAGE_ENTRIES (3072) 2178adfc5217SJeff Kirsher /* In 57710/11 we use whole table since we have 8 func 2179adfc5217SJeff Kirsher * In 57712 we have only 4 func, but use same size per func, then only half of 2180adfc5217SJeff Kirsher * the table in use 2181adfc5217SJeff Kirsher */ 2182adfc5217SJeff Kirsher #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 2183adfc5217SJeff Kirsher 2184adfc5217SJeff Kirsher #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 2185adfc5217SJeff Kirsher /* 2186adfc5217SJeff Kirsher * the phys address is shifted right 12 bits and has an added 2187adfc5217SJeff Kirsher * 1=valid bit added to the 53rd bit 2188adfc5217SJeff Kirsher * then since this is a wide register(TM) 2189adfc5217SJeff Kirsher * we split it into two 32 bit writes 2190adfc5217SJeff Kirsher */ 2191adfc5217SJeff Kirsher #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 2192adfc5217SJeff Kirsher #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 2193adfc5217SJeff Kirsher 2194adfc5217SJeff Kirsher /* load/unload mode */ 2195adfc5217SJeff Kirsher #define LOAD_NORMAL 0 2196adfc5217SJeff Kirsher #define LOAD_OPEN 1 2197adfc5217SJeff Kirsher #define LOAD_DIAG 2 21988970b2e4SMerav Sicron #define LOAD_LOOPBACK_EXT 3 2199adfc5217SJeff Kirsher #define UNLOAD_NORMAL 0 2200adfc5217SJeff Kirsher #define UNLOAD_CLOSE 1 2201adfc5217SJeff Kirsher #define UNLOAD_RECOVERY 2 2202adfc5217SJeff Kirsher 2203adfc5217SJeff Kirsher /* DMAE command defines */ 2204adfc5217SJeff Kirsher #define DMAE_TIMEOUT -1 2205adfc5217SJeff Kirsher #define DMAE_PCI_ERROR -2 /* E2 and onward */ 2206adfc5217SJeff Kirsher #define DMAE_NOT_RDY -3 2207adfc5217SJeff Kirsher #define DMAE_PCI_ERR_FLAG 0x80000000 2208adfc5217SJeff Kirsher 2209adfc5217SJeff Kirsher #define DMAE_SRC_PCI 0 2210adfc5217SJeff Kirsher #define DMAE_SRC_GRC 1 2211adfc5217SJeff Kirsher 2212adfc5217SJeff Kirsher #define DMAE_DST_NONE 0 2213adfc5217SJeff Kirsher #define DMAE_DST_PCI 1 2214adfc5217SJeff Kirsher #define DMAE_DST_GRC 2 2215adfc5217SJeff Kirsher 2216adfc5217SJeff Kirsher #define DMAE_COMP_PCI 0 2217adfc5217SJeff Kirsher #define DMAE_COMP_GRC 1 2218adfc5217SJeff Kirsher 2219adfc5217SJeff Kirsher /* E2 and onward - PCI error handling in the completion */ 2220adfc5217SJeff Kirsher 2221adfc5217SJeff Kirsher #define DMAE_COMP_REGULAR 0 2222adfc5217SJeff Kirsher #define DMAE_COM_SET_ERR 1 2223adfc5217SJeff Kirsher 2224adfc5217SJeff Kirsher #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2225adfc5217SJeff Kirsher DMAE_COMMAND_SRC_SHIFT) 2226adfc5217SJeff Kirsher #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2227adfc5217SJeff Kirsher DMAE_COMMAND_SRC_SHIFT) 2228adfc5217SJeff Kirsher 2229adfc5217SJeff Kirsher #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2230adfc5217SJeff Kirsher DMAE_COMMAND_DST_SHIFT) 2231adfc5217SJeff Kirsher #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2232adfc5217SJeff Kirsher DMAE_COMMAND_DST_SHIFT) 2233adfc5217SJeff Kirsher 2234adfc5217SJeff Kirsher #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2235adfc5217SJeff Kirsher DMAE_COMMAND_C_DST_SHIFT) 2236adfc5217SJeff Kirsher #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2237adfc5217SJeff Kirsher DMAE_COMMAND_C_DST_SHIFT) 2238adfc5217SJeff Kirsher 2239adfc5217SJeff Kirsher #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2240adfc5217SJeff Kirsher 2241adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2242adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2243adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2244adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2245adfc5217SJeff Kirsher 2246adfc5217SJeff Kirsher #define DMAE_CMD_PORT_0 0 2247adfc5217SJeff Kirsher #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2248adfc5217SJeff Kirsher 2249adfc5217SJeff Kirsher #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2250adfc5217SJeff Kirsher #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2251adfc5217SJeff Kirsher #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2252adfc5217SJeff Kirsher 2253adfc5217SJeff Kirsher #define DMAE_SRC_PF 0 2254adfc5217SJeff Kirsher #define DMAE_SRC_VF 1 2255adfc5217SJeff Kirsher 2256adfc5217SJeff Kirsher #define DMAE_DST_PF 0 2257adfc5217SJeff Kirsher #define DMAE_DST_VF 1 2258adfc5217SJeff Kirsher 2259adfc5217SJeff Kirsher #define DMAE_C_SRC 0 2260adfc5217SJeff Kirsher #define DMAE_C_DST 1 2261adfc5217SJeff Kirsher 2262adfc5217SJeff Kirsher #define DMAE_LEN32_RD_MAX 0x80 2263adfc5217SJeff Kirsher #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2264adfc5217SJeff Kirsher 2265adfc5217SJeff Kirsher #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 226616a5fd92SYuval Mintz * indicates error 226716a5fd92SYuval Mintz */ 2268adfc5217SJeff Kirsher 2269adfc5217SJeff Kirsher #define MAX_DMAE_C_PER_PORT 8 2270adfc5217SJeff Kirsher #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 22718decf868SDavid S. Miller BP_VN(bp)) 2272adfc5217SJeff Kirsher #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2273adfc5217SJeff Kirsher E1HVN_MAX) 2274adfc5217SJeff Kirsher 2275adfc5217SJeff Kirsher /* PCIE link and speed */ 2276adfc5217SJeff Kirsher #define PCICFG_LINK_WIDTH 0x1f00000 2277adfc5217SJeff Kirsher #define PCICFG_LINK_WIDTH_SHIFT 20 2278adfc5217SJeff Kirsher #define PCICFG_LINK_SPEED 0xf0000 2279adfc5217SJeff Kirsher #define PCICFG_LINK_SPEED_SHIFT 16 2280adfc5217SJeff Kirsher 2281cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS_SF 7 2282cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS_MF 3 2283cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 228475543741SYuval Mintz IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF) 2285adfc5217SJeff Kirsher 2286adfc5217SJeff Kirsher #define BNX2X_PHY_LOOPBACK 0 2287adfc5217SJeff Kirsher #define BNX2X_MAC_LOOPBACK 1 22888970b2e4SMerav Sicron #define BNX2X_EXT_LOOPBACK 2 2289adfc5217SJeff Kirsher #define BNX2X_PHY_LOOPBACK_FAILED 1 2290adfc5217SJeff Kirsher #define BNX2X_MAC_LOOPBACK_FAILED 2 22918970b2e4SMerav Sicron #define BNX2X_EXT_LOOPBACK_FAILED 3 2292adfc5217SJeff Kirsher #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2293adfc5217SJeff Kirsher BNX2X_PHY_LOOPBACK_FAILED) 2294adfc5217SJeff Kirsher 2295adfc5217SJeff Kirsher #define STROM_ASSERT_ARRAY_SIZE 50 2296adfc5217SJeff Kirsher 2297adfc5217SJeff Kirsher /* must be used on a CID before placing it on a HW ring */ 2298adfc5217SJeff Kirsher #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 22998decf868SDavid S. Miller (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2300adfc5217SJeff Kirsher (x)) 2301adfc5217SJeff Kirsher 2302adfc5217SJeff Kirsher #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2303adfc5217SJeff Kirsher #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2304adfc5217SJeff Kirsher 2305adfc5217SJeff Kirsher #define BNX2X_BTR 4 2306adfc5217SJeff Kirsher #define MAX_SPQ_PENDING 8 2307adfc5217SJeff Kirsher 2308adfc5217SJeff Kirsher /* CMNG constants, as derived from system spec calculations */ 2309adfc5217SJeff Kirsher /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2310adfc5217SJeff Kirsher #define DEF_MIN_RATE 100 2311adfc5217SJeff Kirsher /* resolution of the rate shaping timer - 400 usec */ 2312adfc5217SJeff Kirsher #define RS_PERIODIC_TIMEOUT_USEC 400 2313adfc5217SJeff Kirsher /* number of bytes in single QM arbitration cycle - 2314adfc5217SJeff Kirsher * coefficient for calculating the fairness timer */ 2315adfc5217SJeff Kirsher #define QM_ARB_BYTES 160000 2316adfc5217SJeff Kirsher /* resolution of Min algorithm 1:100 */ 2317adfc5217SJeff Kirsher #define MIN_RES 100 2318adfc5217SJeff Kirsher /* how many bytes above threshold for the minimal credit of Min algorithm*/ 2319adfc5217SJeff Kirsher #define MIN_ABOVE_THRESH 32768 2320adfc5217SJeff Kirsher /* Fairness algorithm integration time coefficient - 2321adfc5217SJeff Kirsher * for calculating the actual Tfair */ 2322adfc5217SJeff Kirsher #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2323adfc5217SJeff Kirsher /* Memory of fairness algorithm . 2 cycles */ 2324adfc5217SJeff Kirsher #define FAIR_MEM 2 2325adfc5217SJeff Kirsher 2326adfc5217SJeff Kirsher #define ATTN_NIG_FOR_FUNC (1L << 8) 2327adfc5217SJeff Kirsher #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2328adfc5217SJeff Kirsher #define GPIO_2_FUNC (1L << 10) 2329adfc5217SJeff Kirsher #define GPIO_3_FUNC (1L << 11) 2330adfc5217SJeff Kirsher #define GPIO_4_FUNC (1L << 12) 2331adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_1 (1L << 13) 2332adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_2 (1L << 14) 2333adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_3 (1L << 15) 2334adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_4 (1L << 13) 2335adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_5 (1L << 14) 2336adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_6 (1L << 15) 2337adfc5217SJeff Kirsher 2338adfc5217SJeff Kirsher #define ATTN_HARD_WIRED_MASK 0xff00 2339adfc5217SJeff Kirsher #define ATTENTION_ID 4 2340adfc5217SJeff Kirsher 23412e98ffc2SDmitry Kravkov #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \ 23423521b419SYuval Mintz IS_MF_FCOE_AFEX(bp)) 2343adfc5217SJeff Kirsher 2344adfc5217SJeff Kirsher /* stuff added to make the code fit 80Col */ 2345adfc5217SJeff Kirsher 2346adfc5217SJeff Kirsher #define BNX2X_PMF_LINK_ASSERT \ 2347adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2348adfc5217SJeff Kirsher 2349adfc5217SJeff Kirsher #define BNX2X_MC_ASSERT_BITS \ 2350adfc5217SJeff Kirsher (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2351adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2352adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2353adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2354adfc5217SJeff Kirsher 2355adfc5217SJeff Kirsher #define BNX2X_MCP_ASSERT \ 2356adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2357adfc5217SJeff Kirsher 2358adfc5217SJeff Kirsher #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2359adfc5217SJeff Kirsher #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2360adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2361adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2362adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2363adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2364adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2365adfc5217SJeff Kirsher 2366adfc5217SJeff Kirsher #define HW_INTERRUT_ASSERT_SET_0 \ 2367adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2368adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2369adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2370c14a09b7SDmitry Kravkov AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2371adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2372adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2373adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2374adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2375adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2376adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2377adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2378adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2379adfc5217SJeff Kirsher #define HW_INTERRUT_ASSERT_SET_1 \ 2380adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2381adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2382adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2383adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2384adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2385adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2386adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2387adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2388adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2389adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2390adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2391adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2392adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2393adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2394adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2395adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2396adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2397adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2398adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2399adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2400adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2401adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2402adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2403adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2404adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2405adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2406adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2407adfc5217SJeff Kirsher #define HW_INTERRUT_ASSERT_SET_2 \ 2408adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2409adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2410adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2411adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2412adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2413adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2414adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2415adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2416adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2417adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2418adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2419adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2420adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2421adfc5217SJeff Kirsher 2422ad6afbe9SManish Chopra #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \ 2423ad6afbe9SManish Chopra (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2424adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2425ad6afbe9SManish Chopra AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY) 2426ad6afbe9SManish Chopra 2427ad6afbe9SManish Chopra #define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \ 2428adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2429adfc5217SJeff Kirsher 2430adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2431adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2432adfc5217SJeff Kirsher 2433adfc5217SJeff Kirsher #define MULTI_MASK 0x7f 2434adfc5217SJeff Kirsher 2435adfc5217SJeff Kirsher #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2436adfc5217SJeff Kirsher #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2437adfc5217SJeff Kirsher #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2438adfc5217SJeff Kirsher #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2439adfc5217SJeff Kirsher 2440adfc5217SJeff Kirsher #define DEF_USB_IGU_INDEX_OFF \ 2441adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_u, igu_index) 2442adfc5217SJeff Kirsher #define DEF_CSB_IGU_INDEX_OFF \ 2443adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_c, igu_index) 2444adfc5217SJeff Kirsher #define DEF_XSB_IGU_INDEX_OFF \ 2445adfc5217SJeff Kirsher offsetof(struct xstorm_def_status_block, igu_index) 2446adfc5217SJeff Kirsher #define DEF_TSB_IGU_INDEX_OFF \ 2447adfc5217SJeff Kirsher offsetof(struct tstorm_def_status_block, igu_index) 2448adfc5217SJeff Kirsher 2449adfc5217SJeff Kirsher #define DEF_USB_SEGMENT_OFF \ 2450adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_u, segment) 2451adfc5217SJeff Kirsher #define DEF_CSB_SEGMENT_OFF \ 2452adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_c, segment) 2453adfc5217SJeff Kirsher #define DEF_XSB_SEGMENT_OFF \ 2454adfc5217SJeff Kirsher offsetof(struct xstorm_def_status_block, segment) 2455adfc5217SJeff Kirsher #define DEF_TSB_SEGMENT_OFF \ 2456adfc5217SJeff Kirsher offsetof(struct tstorm_def_status_block, segment) 2457adfc5217SJeff Kirsher 2458adfc5217SJeff Kirsher #define BNX2X_SP_DSB_INDEX \ 2459adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 2460adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2461adfc5217SJeff Kirsher 2462adfc5217SJeff Kirsher #define CAM_IS_INVALID(x) \ 2463adfc5217SJeff Kirsher (GET_FLAG(x.flags, \ 2464adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2465adfc5217SJeff Kirsher (T_ETH_MAC_COMMAND_INVALIDATE)) 2466adfc5217SJeff Kirsher 2467adfc5217SJeff Kirsher /* Number of u32 elements in MC hash array */ 2468adfc5217SJeff Kirsher #define MC_HASH_SIZE 8 2469adfc5217SJeff Kirsher #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2470adfc5217SJeff Kirsher TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2471adfc5217SJeff Kirsher 2472adfc5217SJeff Kirsher #ifndef PXP2_REG_PXP2_INT_STS 2473adfc5217SJeff Kirsher #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2474adfc5217SJeff Kirsher #endif 2475adfc5217SJeff Kirsher 2476adfc5217SJeff Kirsher #ifndef ETH_MAX_RX_CLIENTS_E2 2477adfc5217SJeff Kirsher #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2478adfc5217SJeff Kirsher #endif 2479adfc5217SJeff Kirsher 2480adfc5217SJeff Kirsher #define BNX2X_VPD_LEN 128 2481adfc5217SJeff Kirsher #define VENDOR_ID_LEN 4 2482adfc5217SJeff Kirsher 2483be1f1ffaSAriel Elior #define VF_ACQUIRE_THRESH 3 2484be1f1ffaSAriel Elior #define VF_ACQUIRE_MAC_FILTERS 1 2485be1f1ffaSAriel Elior #define VF_ACQUIRE_MC_FILTERS 10 2486be1f1ffaSAriel Elior 2487be1f1ffaSAriel Elior #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2488be1f1ffaSAriel Elior (!((me_reg) & ME_REG_VF_ERR))) 248991ebb929SYuval Mintz int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err); 249091ebb929SYuval Mintz 2491adfc5217SJeff Kirsher /* Congestion management fairness mode */ 2492adfc5217SJeff Kirsher #define CMNG_FNS_NONE 0 2493adfc5217SJeff Kirsher #define CMNG_FNS_MINMAX 1 2494adfc5217SJeff Kirsher 2495adfc5217SJeff Kirsher #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2496adfc5217SJeff Kirsher #define HC_SEG_ACCESS_ATTN 4 2497adfc5217SJeff Kirsher #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2498adfc5217SJeff Kirsher 2499adfc5217SJeff Kirsher static const u32 dmae_reg_go_c[] = { 2500adfc5217SJeff Kirsher DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2501adfc5217SJeff Kirsher DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2502adfc5217SJeff Kirsher DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2503adfc5217SJeff Kirsher DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2504adfc5217SJeff Kirsher }; 2505adfc5217SJeff Kirsher 2506005a07baSAriel Elior void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); 2507adfc5217SJeff Kirsher void bnx2x_notify_link_changed(struct bnx2x *bp); 2508614c76dfSDmitry Kravkov 25099e62e912SDmitry Kravkov #define BNX2X_MF_SD_PROTOCOL(bp) \ 2510614c76dfSDmitry Kravkov ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2511614c76dfSDmitry Kravkov 25129e62e912SDmitry Kravkov #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 25139e62e912SDmitry Kravkov (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2514614c76dfSDmitry Kravkov 25159e62e912SDmitry Kravkov #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 25169e62e912SDmitry Kravkov (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 25179e62e912SDmitry Kravkov 25189e62e912SDmitry Kravkov #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 25199e62e912SDmitry Kravkov #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 25202e98ffc2SDmitry Kravkov #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp)) 25219e62e912SDmitry Kravkov 25222e98ffc2SDmitry Kravkov #define IS_MF_ISCSI_ONLY(bp) (IS_MF_ISCSI_SD(bp) || IS_MF_ISCSI_SI(bp)) 25232e98ffc2SDmitry Kravkov 25242e98ffc2SDmitry Kravkov #define BNX2X_MF_EXT_PROTOCOL_MASK \ 25252e98ffc2SDmitry Kravkov (MACP_FUNC_CFG_FLAGS_ETHERNET | \ 25262e98ffc2SDmitry Kravkov MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD | \ 2527a3348722SBarak Witkowski MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2528a3348722SBarak Witkowski 25292e98ffc2SDmitry Kravkov #define BNX2X_MF_EXT_PROT(bp) ((bp)->mf_ext_config & \ 25302e98ffc2SDmitry Kravkov BNX2X_MF_EXT_PROTOCOL_MASK) 25312e98ffc2SDmitry Kravkov 25322e98ffc2SDmitry Kravkov #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) \ 25332e98ffc2SDmitry Kravkov (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 25342e98ffc2SDmitry Kravkov 25352e98ffc2SDmitry Kravkov #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) \ 25362e98ffc2SDmitry Kravkov (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 25372e98ffc2SDmitry Kravkov 25382e98ffc2SDmitry Kravkov #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) \ 25392e98ffc2SDmitry Kravkov (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) 25402e98ffc2SDmitry Kravkov 25412e98ffc2SDmitry Kravkov #define IS_MF_FCOE_AFEX(bp) \ 25422e98ffc2SDmitry Kravkov (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)) 25432e98ffc2SDmitry Kravkov 25442e98ffc2SDmitry Kravkov #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) \ 25452e98ffc2SDmitry Kravkov (IS_MF_SD(bp) && \ 25469e62e912SDmitry Kravkov (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 25479e62e912SDmitry Kravkov BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2548614c76dfSDmitry Kravkov 25492e98ffc2SDmitry Kravkov #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) \ 25502e98ffc2SDmitry Kravkov (IS_MF_SI(bp) && \ 25512e98ffc2SDmitry Kravkov (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \ 25522e98ffc2SDmitry Kravkov BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))) 25532e98ffc2SDmitry Kravkov 25542e98ffc2SDmitry Kravkov #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) \ 25552e98ffc2SDmitry Kravkov (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) || \ 25562e98ffc2SDmitry Kravkov IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp)) 25572e98ffc2SDmitry Kravkov 25582e98ffc2SDmitry Kravkov 25592de67439SYuval Mintz #define SET_FLAG(value, mask, flag) \ 25602de67439SYuval Mintz do {\ 25612de67439SYuval Mintz (value) &= ~(mask);\ 25622de67439SYuval Mintz (value) |= ((flag) << (mask##_SHIFT));\ 25632de67439SYuval Mintz } while (0) 25642de67439SYuval Mintz 25652de67439SYuval Mintz #define GET_FLAG(value, mask) \ 25662de67439SYuval Mintz (((value) & (mask)) >> (mask##_SHIFT)) 25672de67439SYuval Mintz 25682de67439SYuval Mintz #define GET_FIELD(value, fname) \ 25692de67439SYuval Mintz (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 25702de67439SYuval Mintz 257155c11941SMerav Sicron enum { 257255c11941SMerav Sicron SWITCH_UPDATE, 257355c11941SMerav Sicron AFEX_UPDATE, 257455c11941SMerav Sicron }; 257555c11941SMerav Sicron 257655c11941SMerav Sicron #define NUM_MACS 8 2577a3348722SBarak Witkowski 2578568e2426SDmitry Kravkov void bnx2x_set_local_cmng(struct bnx2x *bp); 25791a6974b2SYuval Mintz 258042f8277fSYuval Mintz void bnx2x_update_mng_version(struct bnx2x *bp); 258142f8277fSYuval Mintz 25821a6974b2SYuval Mintz #define MCPR_SCRATCH_BASE(bp) \ 25831a6974b2SYuval Mintz (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 25841a6974b2SYuval Mintz 2585e848582cSDmitry Kravkov #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX)) 2586e848582cSDmitry Kravkov 2587eeed018cSMichal Kalderon void bnx2x_init_ptp(struct bnx2x *bp); 2588eeed018cSMichal Kalderon int bnx2x_configure_ptp_filters(struct bnx2x *bp); 2589eeed018cSMichal Kalderon void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb); 2590eeed018cSMichal Kalderon 2591eeed018cSMichal Kalderon #define BNX2X_MAX_PHC_DRIFT 31000000 2592eeed018cSMichal Kalderon #define BNX2X_PTP_TX_TIMEOUT 2593eeed018cSMichal Kalderon 2594adfc5217SJeff Kirsher #endif /* bnx2x.h */ 2595