1adfc5217SJeff Kirsher /* bnx2x.h: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2007-2013 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7adfc5217SJeff Kirsher * the Free Software Foundation. 8adfc5217SJeff Kirsher * 9adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10adfc5217SJeff Kirsher * Written by: Eliezer Tamir 11adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 12adfc5217SJeff Kirsher */ 13adfc5217SJeff Kirsher 14adfc5217SJeff Kirsher #ifndef BNX2X_H 15adfc5217SJeff Kirsher #define BNX2X_H 16290ca2bbSAriel Elior 17290ca2bbSAriel Elior #include <linux/pci.h> 18adfc5217SJeff Kirsher #include <linux/netdevice.h> 19adfc5217SJeff Kirsher #include <linux/dma-mapping.h> 20adfc5217SJeff Kirsher #include <linux/types.h> 21290ca2bbSAriel Elior #include <linux/pci_regs.h> 22adfc5217SJeff Kirsher 23adfc5217SJeff Kirsher /* compilation time flags */ 24adfc5217SJeff Kirsher 25adfc5217SJeff Kirsher /* define this to make the driver freeze on error to allow getting debug info 26adfc5217SJeff Kirsher * (you will need to reboot afterwards) */ 27adfc5217SJeff Kirsher /* #define BNX2X_STOP_ON_ERROR */ 28adfc5217SJeff Kirsher 293156b8ebSDmitry Kravkov #define DRV_MODULE_VERSION "1.78.19-0" 303156b8ebSDmitry Kravkov #define DRV_MODULE_RELDATE "2014/02/10" 31adfc5217SJeff Kirsher #define BNX2X_BC_VER 0x040200 32adfc5217SJeff Kirsher 33adfc5217SJeff Kirsher #if defined(CONFIG_DCB) 34adfc5217SJeff Kirsher #define BCM_DCBNL 35adfc5217SJeff Kirsher #endif 36b475d78fSYuval Mintz 37b475d78fSYuval Mintz #include "bnx2x_hsi.h" 38b475d78fSYuval Mintz 39adfc5217SJeff Kirsher #include "../cnic_if.h" 40adfc5217SJeff Kirsher 4155c11941SMerav Sicron #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 42adfc5217SJeff Kirsher 43adfc5217SJeff Kirsher #include <linux/mdio.h> 44adfc5217SJeff Kirsher 45adfc5217SJeff Kirsher #include "bnx2x_reg.h" 46adfc5217SJeff Kirsher #include "bnx2x_fw_defs.h" 472e499d3cSBarak Witkowski #include "bnx2x_mfw_req.h" 48adfc5217SJeff Kirsher #include "bnx2x_link.h" 49adfc5217SJeff Kirsher #include "bnx2x_sp.h" 50adfc5217SJeff Kirsher #include "bnx2x_dcb.h" 51adfc5217SJeff Kirsher #include "bnx2x_stats.h" 52be1f1ffaSAriel Elior #include "bnx2x_vfpf.h" 53adfc5217SJeff Kirsher 541ab4434cSAriel Elior enum bnx2x_int_mode { 551ab4434cSAriel Elior BNX2X_INT_MODE_MSIX, 561ab4434cSAriel Elior BNX2X_INT_MODE_INTX, 571ab4434cSAriel Elior BNX2X_INT_MODE_MSI 581ab4434cSAriel Elior }; 591ab4434cSAriel Elior 60adfc5217SJeff Kirsher /* error/debug prints */ 61adfc5217SJeff Kirsher 62adfc5217SJeff Kirsher #define DRV_MODULE_NAME "bnx2x" 63adfc5217SJeff Kirsher 64adfc5217SJeff Kirsher /* for messages that are currently off */ 6551c1a580SMerav Sicron #define BNX2X_MSG_OFF 0x0 6651c1a580SMerav Sicron #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 6751c1a580SMerav Sicron #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 6851c1a580SMerav Sicron #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 6951c1a580SMerav Sicron #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 7051c1a580SMerav Sicron #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 7151c1a580SMerav Sicron #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 7251c1a580SMerav Sicron #define BNX2X_MSG_IOV 0x0800000 7351c1a580SMerav Sicron #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 7451c1a580SMerav Sicron #define BNX2X_MSG_ETHTOOL 0x4000000 7551c1a580SMerav Sicron #define BNX2X_MSG_DCB 0x8000000 76adfc5217SJeff Kirsher 77adfc5217SJeff Kirsher /* regular debug print */ 7876ca70faSYuval Mintz #define DP_INNER(fmt, ...) \ 79f1deab50SJoe Perches pr_notice("[%s:%d(%s)]" fmt, \ 80adfc5217SJeff Kirsher __func__, __LINE__, \ 81adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 8276ca70faSYuval Mintz ##__VA_ARGS__); 8376ca70faSYuval Mintz 8476ca70faSYuval Mintz #define DP(__mask, fmt, ...) \ 8576ca70faSYuval Mintz do { \ 8676ca70faSYuval Mintz if (unlikely(bp->msg_enable & (__mask))) \ 8776ca70faSYuval Mintz DP_INNER(fmt, ##__VA_ARGS__); \ 8876ca70faSYuval Mintz } while (0) 8976ca70faSYuval Mintz 9076ca70faSYuval Mintz #define DP_AND(__mask, fmt, ...) \ 9176ca70faSYuval Mintz do { \ 9276ca70faSYuval Mintz if (unlikely((bp->msg_enable & (__mask)) == __mask)) \ 9376ca70faSYuval Mintz DP_INNER(fmt, ##__VA_ARGS__); \ 94adfc5217SJeff Kirsher } while (0) 95adfc5217SJeff Kirsher 96f1deab50SJoe Perches #define DP_CONT(__mask, fmt, ...) \ 97adfc5217SJeff Kirsher do { \ 9851c1a580SMerav Sicron if (unlikely(bp->msg_enable & (__mask))) \ 99f1deab50SJoe Perches pr_cont(fmt, ##__VA_ARGS__); \ 100adfc5217SJeff Kirsher } while (0) 101adfc5217SJeff Kirsher 102adfc5217SJeff Kirsher /* errors debug print */ 103f1deab50SJoe Perches #define BNX2X_DBG_ERR(fmt, ...) \ 104adfc5217SJeff Kirsher do { \ 10551c1a580SMerav Sicron if (unlikely(netif_msg_probe(bp))) \ 106f1deab50SJoe Perches pr_err("[%s:%d(%s)]" fmt, \ 107adfc5217SJeff Kirsher __func__, __LINE__, \ 108adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 109f1deab50SJoe Perches ##__VA_ARGS__); \ 110adfc5217SJeff Kirsher } while (0) 111adfc5217SJeff Kirsher 112adfc5217SJeff Kirsher /* for errors (never masked) */ 113f1deab50SJoe Perches #define BNX2X_ERR(fmt, ...) \ 114adfc5217SJeff Kirsher do { \ 115f1deab50SJoe Perches pr_err("[%s:%d(%s)]" fmt, \ 116adfc5217SJeff Kirsher __func__, __LINE__, \ 117adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 118f1deab50SJoe Perches ##__VA_ARGS__); \ 119adfc5217SJeff Kirsher } while (0) 120adfc5217SJeff Kirsher 121f1deab50SJoe Perches #define BNX2X_ERROR(fmt, ...) \ 122f1deab50SJoe Perches pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 123adfc5217SJeff Kirsher 124adfc5217SJeff Kirsher /* before we have a dev->name use dev_info() */ 125f1deab50SJoe Perches #define BNX2X_DEV_INFO(fmt, ...) \ 126adfc5217SJeff Kirsher do { \ 12751c1a580SMerav Sicron if (unlikely(netif_msg_probe(bp))) \ 128f1deab50SJoe Perches dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 129adfc5217SJeff Kirsher } while (0) 130adfc5217SJeff Kirsher 131ca9bdb9bSYuval Mintz /* Error handling */ 132ca9bdb9bSYuval Mintz void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); 133adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 134f1deab50SJoe Perches #define bnx2x_panic() \ 135f1deab50SJoe Perches do { \ 136adfc5217SJeff Kirsher bp->panic = 1; \ 137adfc5217SJeff Kirsher BNX2X_ERR("driver assert\n"); \ 138823e1d90SYuval Mintz bnx2x_panic_dump(bp, true); \ 139adfc5217SJeff Kirsher } while (0) 140adfc5217SJeff Kirsher #else 141f1deab50SJoe Perches #define bnx2x_panic() \ 142f1deab50SJoe Perches do { \ 143adfc5217SJeff Kirsher bp->panic = 1; \ 144adfc5217SJeff Kirsher BNX2X_ERR("driver assert\n"); \ 145823e1d90SYuval Mintz bnx2x_panic_dump(bp, false); \ 146adfc5217SJeff Kirsher } while (0) 147adfc5217SJeff Kirsher #endif 148adfc5217SJeff Kirsher 149adfc5217SJeff Kirsher #define bnx2x_mc_addr(ha) ((ha)->addr) 150adfc5217SJeff Kirsher #define bnx2x_uc_addr(ha) ((ha)->addr) 151adfc5217SJeff Kirsher 1522de67439SYuval Mintz #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 1532de67439SYuval Mintz #define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 154adfc5217SJeff Kirsher #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 155adfc5217SJeff Kirsher 156adfc5217SJeff Kirsher #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 157adfc5217SJeff Kirsher 158adfc5217SJeff Kirsher #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 159adfc5217SJeff Kirsher #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 160adfc5217SJeff Kirsher #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 161adfc5217SJeff Kirsher 162adfc5217SJeff Kirsher #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 163adfc5217SJeff Kirsher #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 164adfc5217SJeff Kirsher #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 165adfc5217SJeff Kirsher 166adfc5217SJeff Kirsher #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 167adfc5217SJeff Kirsher #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 168adfc5217SJeff Kirsher 169adfc5217SJeff Kirsher #define REG_RD_DMAE(bp, offset, valp, len32) \ 170adfc5217SJeff Kirsher do { \ 171adfc5217SJeff Kirsher bnx2x_read_dmae(bp, offset, len32);\ 172adfc5217SJeff Kirsher memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 173adfc5217SJeff Kirsher } while (0) 174adfc5217SJeff Kirsher 175adfc5217SJeff Kirsher #define REG_WR_DMAE(bp, offset, valp, len32) \ 176adfc5217SJeff Kirsher do { \ 177adfc5217SJeff Kirsher memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 178adfc5217SJeff Kirsher bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 179adfc5217SJeff Kirsher offset, len32); \ 180adfc5217SJeff Kirsher } while (0) 181adfc5217SJeff Kirsher 182adfc5217SJeff Kirsher #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 183adfc5217SJeff Kirsher REG_WR_DMAE(bp, offset, valp, len32) 184adfc5217SJeff Kirsher 185adfc5217SJeff Kirsher #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 186adfc5217SJeff Kirsher do { \ 187adfc5217SJeff Kirsher memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 188adfc5217SJeff Kirsher bnx2x_write_big_buf_wb(bp, addr, len32); \ 189adfc5217SJeff Kirsher } while (0) 190adfc5217SJeff Kirsher 191adfc5217SJeff Kirsher #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 192adfc5217SJeff Kirsher offsetof(struct shmem_region, field)) 193adfc5217SJeff Kirsher #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 194adfc5217SJeff Kirsher #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 195adfc5217SJeff Kirsher 196adfc5217SJeff Kirsher #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 197adfc5217SJeff Kirsher offsetof(struct shmem2_region, field)) 198adfc5217SJeff Kirsher #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 199adfc5217SJeff Kirsher #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 200adfc5217SJeff Kirsher #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 201adfc5217SJeff Kirsher offsetof(struct mf_cfg, field)) 202adfc5217SJeff Kirsher #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 203adfc5217SJeff Kirsher offsetof(struct mf2_cfg, field)) 204adfc5217SJeff Kirsher 205adfc5217SJeff Kirsher #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 206adfc5217SJeff Kirsher #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 207adfc5217SJeff Kirsher MF_CFG_ADDR(bp, field), (val)) 208adfc5217SJeff Kirsher #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 209adfc5217SJeff Kirsher 210adfc5217SJeff Kirsher #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 211adfc5217SJeff Kirsher (SHMEM2_RD((bp), size) > \ 212adfc5217SJeff Kirsher offsetof(struct shmem2_region, field))) 213adfc5217SJeff Kirsher 214adfc5217SJeff Kirsher #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 215adfc5217SJeff Kirsher #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 216adfc5217SJeff Kirsher 217adfc5217SJeff Kirsher /* SP SB indices */ 218adfc5217SJeff Kirsher 219adfc5217SJeff Kirsher /* General SP events - stats query, cfc delete, etc */ 220adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_DEF_CONS 3 221adfc5217SJeff Kirsher 222adfc5217SJeff Kirsher /* EQ completions */ 223adfc5217SJeff Kirsher #define HC_SP_INDEX_EQ_CONS 7 224adfc5217SJeff Kirsher 225adfc5217SJeff Kirsher /* FCoE L2 connection completions */ 226adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 227adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 228adfc5217SJeff Kirsher /* iSCSI L2 */ 229adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 230adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 231adfc5217SJeff Kirsher 232adfc5217SJeff Kirsher /* Special clients parameters */ 233adfc5217SJeff Kirsher 234adfc5217SJeff Kirsher /* SB indices */ 235adfc5217SJeff Kirsher /* FCoE L2 */ 236adfc5217SJeff Kirsher #define BNX2X_FCOE_L2_RX_INDEX \ 237adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 238adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 239adfc5217SJeff Kirsher 240adfc5217SJeff Kirsher #define BNX2X_FCOE_L2_TX_INDEX \ 241adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 242adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 243adfc5217SJeff Kirsher 244adfc5217SJeff Kirsher /** 245adfc5217SJeff Kirsher * CIDs and CLIDs: 246adfc5217SJeff Kirsher * CLIDs below is a CLID for func 0, then the CLID for other 247adfc5217SJeff Kirsher * functions will be calculated by the formula: 248adfc5217SJeff Kirsher * 249adfc5217SJeff Kirsher * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 250adfc5217SJeff Kirsher * 251adfc5217SJeff Kirsher */ 2521805b2f0SDavid S. Miller enum { 2531805b2f0SDavid S. Miller BNX2X_ISCSI_ETH_CL_ID_IDX, 2541805b2f0SDavid S. Miller BNX2X_FCOE_ETH_CL_ID_IDX, 2551805b2f0SDavid S. Miller BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 2561805b2f0SDavid S. Miller }; 257adfc5217SJeff Kirsher 258f78afb35SMichael Chan /* use a value high enough to be above all the PFs, which has least significant 259f78afb35SMichael Chan * nibble as 8, so when cnic needs to come up with a CID for UIO to use to 260f78afb35SMichael Chan * calculate doorbell address according to old doorbell configuration scheme 261f78afb35SMichael Chan * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number 262f78afb35SMichael Chan * We must avoid coming up with cid 8 for iscsi since according to this method 263f78afb35SMichael Chan * the designated UIO cid will come out 0 and it has a special handling for that 264f78afb35SMichael Chan * case which doesn't suit us. Therefore will will cieling to closes cid which 265f78afb35SMichael Chan * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18. 266f78afb35SMichael Chan */ 267f78afb35SMichael Chan 268f78afb35SMichael Chan #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \ 26937ae41a9SMerav Sicron (bp)->max_cos) 270f78afb35SMichael Chan /* amount of cids traversed by UIO's DPM addition to doorbell */ 271f78afb35SMichael Chan #define UIO_DPM 8 272f78afb35SMichael Chan /* roundup to DPM offset */ 273f78afb35SMichael Chan #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \ 274f78afb35SMichael Chan UIO_DPM)) 275f78afb35SMichael Chan /* offset to nearest value which has lsb nibble matching DPM */ 276f78afb35SMichael Chan #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \ 277f78afb35SMichael Chan (UIO_DPM * 2)) 278f78afb35SMichael Chan /* add offset to rounded-up cid to get a value which could be used with UIO */ 279f78afb35SMichael Chan #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp)) 280f78afb35SMichael Chan /* but wait - avoid UIO special case for cid 0 */ 281f78afb35SMichael Chan #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \ 282f78afb35SMichael Chan (UIO_DPM_ALIGN(bp) == UIO_DPM)) 283f78afb35SMichael Chan /* Properly DPM aligned CID dajusted to cid 0 secal case */ 284f78afb35SMichael Chan #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \ 285f78afb35SMichael Chan (UIO_DPM_CID0_OFFSET(bp))) 286f78afb35SMichael Chan /* how many cids were wasted - need this value for cid allocation */ 287f78afb35SMichael Chan #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \ 288f78afb35SMichael Chan BNX2X_1st_NON_L2_ETH_CID(bp)) 2891805b2f0SDavid S. Miller /* iSCSI L2 */ 29037ae41a9SMerav Sicron #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 291adfc5217SJeff Kirsher /* FCoE L2 */ 29237ae41a9SMerav Sicron #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 293adfc5217SJeff Kirsher 29455c11941SMerav Sicron #define CNIC_SUPPORT(bp) ((bp)->cnic_support) 29555c11941SMerav Sicron #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 29655c11941SMerav Sicron #define CNIC_LOADED(bp) ((bp)->cnic_loaded) 29755c11941SMerav Sicron #define FCOE_INIT(bp) ((bp)->fcoe_init) 298adfc5217SJeff Kirsher 299adfc5217SJeff Kirsher #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 300adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 301adfc5217SJeff Kirsher 302adfc5217SJeff Kirsher #define SM_RX_ID 0 303adfc5217SJeff Kirsher #define SM_TX_ID 1 304adfc5217SJeff Kirsher 305adfc5217SJeff Kirsher /* defines for multiple tx priority indices */ 306adfc5217SJeff Kirsher #define FIRST_TX_ONLY_COS_INDEX 1 307adfc5217SJeff Kirsher #define FIRST_TX_COS_INDEX 0 308adfc5217SJeff Kirsher 309adfc5217SJeff Kirsher /* rules for calculating the cids of tx-only connections */ 31065565884SMerav Sicron #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 31165565884SMerav Sicron #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 31265565884SMerav Sicron (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 313adfc5217SJeff Kirsher 314adfc5217SJeff Kirsher /* fp index inside class of service range */ 31565565884SMerav Sicron #define FP_COS_TO_TXQ(fp, cos, bp) \ 31665565884SMerav Sicron ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 317adfc5217SJeff Kirsher 31865565884SMerav Sicron /* Indexes for transmission queues array: 31965565884SMerav Sicron * txdata for RSS i CoS j is at location i + (j * num of RSS) 32065565884SMerav Sicron * txdata for FCoE (if exist) is at location max cos * num of RSS 32165565884SMerav Sicron * txdata for FWD (if exist) is one location after FCoE 32265565884SMerav Sicron * txdata for OOO (if exist) is one location after FWD 323adfc5217SJeff Kirsher */ 32465565884SMerav Sicron enum { 32565565884SMerav Sicron FCOE_TXQ_IDX_OFFSET, 32665565884SMerav Sicron FWD_TXQ_IDX_OFFSET, 32765565884SMerav Sicron OOO_TXQ_IDX_OFFSET, 32865565884SMerav Sicron }; 32965565884SMerav Sicron #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 33065565884SMerav Sicron #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 331adfc5217SJeff Kirsher 332adfc5217SJeff Kirsher /* fast path */ 333e52fcb24SEric Dumazet /* 334e52fcb24SEric Dumazet * This driver uses new build_skb() API : 335e52fcb24SEric Dumazet * RX ring buffer contains pointer to kmalloc() data only, 336e52fcb24SEric Dumazet * skb are built only after Hardware filled the frame. 337e52fcb24SEric Dumazet */ 338adfc5217SJeff Kirsher struct sw_rx_bd { 339e52fcb24SEric Dumazet u8 *data; 340adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping); 341adfc5217SJeff Kirsher }; 342adfc5217SJeff Kirsher 343adfc5217SJeff Kirsher struct sw_tx_bd { 344adfc5217SJeff Kirsher struct sk_buff *skb; 345adfc5217SJeff Kirsher u16 first_bd; 346adfc5217SJeff Kirsher u8 flags; 347adfc5217SJeff Kirsher /* Set on the first BD descriptor when there is a split BD */ 348adfc5217SJeff Kirsher #define BNX2X_TSO_SPLIT_BD (1<<0) 349adfc5217SJeff Kirsher }; 350adfc5217SJeff Kirsher 351adfc5217SJeff Kirsher struct sw_rx_page { 352adfc5217SJeff Kirsher struct page *page; 353adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping); 354adfc5217SJeff Kirsher }; 355adfc5217SJeff Kirsher 356adfc5217SJeff Kirsher union db_prod { 357adfc5217SJeff Kirsher struct doorbell_set_prod data; 358adfc5217SJeff Kirsher u32 raw; 359adfc5217SJeff Kirsher }; 360adfc5217SJeff Kirsher 3618decf868SDavid S. Miller /* dropless fc FW/HW related params */ 3628decf868SDavid S. Miller #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 3638decf868SDavid S. Miller #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 3648decf868SDavid S. Miller ETH_MAX_AGGREGATION_QUEUES_E1 :\ 3658decf868SDavid S. Miller ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 3668decf868SDavid S. Miller #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 3678decf868SDavid S. Miller #define FW_PREFETCH_CNT 16 3688decf868SDavid S. Miller #define DROPLESS_FC_HEADROOM 100 369adfc5217SJeff Kirsher 370adfc5217SJeff Kirsher /* MC hsi */ 371adfc5217SJeff Kirsher #define BCM_PAGE_SHIFT 12 372adfc5217SJeff Kirsher #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 373adfc5217SJeff Kirsher #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 374adfc5217SJeff Kirsher #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 375adfc5217SJeff Kirsher 376adfc5217SJeff Kirsher #define PAGES_PER_SGE_SHIFT 0 377adfc5217SJeff Kirsher #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 378adfc5217SJeff Kirsher #define SGE_PAGE_SIZE PAGE_SIZE 379adfc5217SJeff Kirsher #define SGE_PAGE_SHIFT PAGE_SHIFT 380adfc5217SJeff Kirsher #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 3818d9ac297SAriel Elior #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 3828d9ac297SAriel Elior #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 3838d9ac297SAriel Elior SGE_PAGES), 0xffff) 384adfc5217SJeff Kirsher 385adfc5217SJeff Kirsher /* SGE ring related macros */ 386adfc5217SJeff Kirsher #define NUM_RX_SGE_PAGES 2 387adfc5217SJeff Kirsher #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 3888decf868SDavid S. Miller #define NEXT_PAGE_SGE_DESC_CNT 2 3898decf868SDavid S. Miller #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 390adfc5217SJeff Kirsher /* RX_SGE_CNT is promised to be a power of 2 */ 391adfc5217SJeff Kirsher #define RX_SGE_MASK (RX_SGE_CNT - 1) 392adfc5217SJeff Kirsher #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 393adfc5217SJeff Kirsher #define MAX_RX_SGE (NUM_RX_SGE - 1) 394adfc5217SJeff Kirsher #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 3958decf868SDavid S. Miller (MAX_RX_SGE_CNT - 1)) ? \ 3968decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 3978decf868SDavid S. Miller (x) + 1) 398adfc5217SJeff Kirsher #define RX_SGE(x) ((x) & MAX_RX_SGE) 399adfc5217SJeff Kirsher 4008decf868SDavid S. Miller /* 4018decf868SDavid S. Miller * Number of required SGEs is the sum of two: 4028decf868SDavid S. Miller * 1. Number of possible opened aggregations (next packet for 40316a5fd92SYuval Mintz * these aggregations will probably consume SGE immediately) 4048decf868SDavid S. Miller * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 4058decf868SDavid S. Miller * after placement on BD for new TPA aggregation) 4068decf868SDavid S. Miller * 4078decf868SDavid S. Miller * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 4088decf868SDavid S. Miller */ 4098decf868SDavid S. Miller #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 4108decf868SDavid S. Miller (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 4118decf868SDavid S. Miller #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 4128decf868SDavid S. Miller MAX_RX_SGE_CNT) 4138decf868SDavid S. Miller #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 4148decf868SDavid S. Miller NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 4158decf868SDavid S. Miller #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 4168decf868SDavid S. Miller 417adfc5217SJeff Kirsher /* Manipulate a bit vector defined as an array of u64 */ 418adfc5217SJeff Kirsher 419adfc5217SJeff Kirsher /* Number of bits in one sge_mask array element */ 420adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_SZ 64 421adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_SHIFT 6 422adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 423adfc5217SJeff Kirsher 424adfc5217SJeff Kirsher #define __BIT_VEC64_SET_BIT(el, bit) \ 425adfc5217SJeff Kirsher do { \ 426adfc5217SJeff Kirsher el = ((el) | ((u64)0x1 << (bit))); \ 427adfc5217SJeff Kirsher } while (0) 428adfc5217SJeff Kirsher 429adfc5217SJeff Kirsher #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 430adfc5217SJeff Kirsher do { \ 431adfc5217SJeff Kirsher el = ((el) & (~((u64)0x1 << (bit)))); \ 432adfc5217SJeff Kirsher } while (0) 433adfc5217SJeff Kirsher 434adfc5217SJeff Kirsher #define BIT_VEC64_SET_BIT(vec64, idx) \ 435adfc5217SJeff Kirsher __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 436adfc5217SJeff Kirsher (idx) & BIT_VEC64_ELEM_MASK) 437adfc5217SJeff Kirsher 438adfc5217SJeff Kirsher #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 439adfc5217SJeff Kirsher __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 440adfc5217SJeff Kirsher (idx) & BIT_VEC64_ELEM_MASK) 441adfc5217SJeff Kirsher 442adfc5217SJeff Kirsher #define BIT_VEC64_TEST_BIT(vec64, idx) \ 443adfc5217SJeff Kirsher (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 444adfc5217SJeff Kirsher ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 445adfc5217SJeff Kirsher 446adfc5217SJeff Kirsher /* Creates a bitmask of all ones in less significant bits. 447adfc5217SJeff Kirsher idx - index of the most significant bit in the created mask */ 448adfc5217SJeff Kirsher #define BIT_VEC64_ONES_MASK(idx) \ 449adfc5217SJeff Kirsher (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 450adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 451adfc5217SJeff Kirsher 452adfc5217SJeff Kirsher /*******************************************************/ 453adfc5217SJeff Kirsher 454adfc5217SJeff Kirsher /* Number of u64 elements in SGE mask array */ 455b3637827SDmitry Kravkov #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 456adfc5217SJeff Kirsher #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 457adfc5217SJeff Kirsher #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 458adfc5217SJeff Kirsher 459adfc5217SJeff Kirsher union host_hc_status_block { 460adfc5217SJeff Kirsher /* pointer to fp status block e1x */ 461adfc5217SJeff Kirsher struct host_hc_status_block_e1x *e1x_sb; 462adfc5217SJeff Kirsher /* pointer to fp status block e2 */ 463adfc5217SJeff Kirsher struct host_hc_status_block_e2 *e2_sb; 464adfc5217SJeff Kirsher }; 465adfc5217SJeff Kirsher 466adfc5217SJeff Kirsher struct bnx2x_agg_info { 467adfc5217SJeff Kirsher /* 468e52fcb24SEric Dumazet * First aggregation buffer is a data buffer, the following - are pages. 469e52fcb24SEric Dumazet * We will preallocate the data buffer for each aggregation when 470adfc5217SJeff Kirsher * we open the interface and will replace the BD at the consumer 471adfc5217SJeff Kirsher * with this one when we receive the TPA_START CQE in order to 472adfc5217SJeff Kirsher * keep the Rx BD ring consistent. 473adfc5217SJeff Kirsher */ 474adfc5217SJeff Kirsher struct sw_rx_bd first_buf; 475adfc5217SJeff Kirsher u8 tpa_state; 476adfc5217SJeff Kirsher #define BNX2X_TPA_START 1 477adfc5217SJeff Kirsher #define BNX2X_TPA_STOP 2 478adfc5217SJeff Kirsher #define BNX2X_TPA_ERROR 3 479adfc5217SJeff Kirsher u8 placement_offset; 480adfc5217SJeff Kirsher u16 parsing_flags; 481adfc5217SJeff Kirsher u16 vlan_tag; 482adfc5217SJeff Kirsher u16 len_on_bd; 483e52fcb24SEric Dumazet u32 rxhash; 4845495ab75STom Herbert enum pkt_hash_types rxhash_type; 485621b4d66SDmitry Kravkov u16 gro_size; 486621b4d66SDmitry Kravkov u16 full_page; 487adfc5217SJeff Kirsher }; 488adfc5217SJeff Kirsher 489adfc5217SJeff Kirsher #define Q_STATS_OFFSET32(stat_name) \ 490adfc5217SJeff Kirsher (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 491adfc5217SJeff Kirsher 492adfc5217SJeff Kirsher struct bnx2x_fp_txdata { 493adfc5217SJeff Kirsher 494adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf_ring; 495adfc5217SJeff Kirsher 496adfc5217SJeff Kirsher union eth_tx_bd_types *tx_desc_ring; 497adfc5217SJeff Kirsher dma_addr_t tx_desc_mapping; 498adfc5217SJeff Kirsher 499adfc5217SJeff Kirsher u32 cid; 500adfc5217SJeff Kirsher 501adfc5217SJeff Kirsher union db_prod tx_db; 502adfc5217SJeff Kirsher 503adfc5217SJeff Kirsher u16 tx_pkt_prod; 504adfc5217SJeff Kirsher u16 tx_pkt_cons; 505adfc5217SJeff Kirsher u16 tx_bd_prod; 506adfc5217SJeff Kirsher u16 tx_bd_cons; 507adfc5217SJeff Kirsher 508adfc5217SJeff Kirsher unsigned long tx_pkt; 509adfc5217SJeff Kirsher 510adfc5217SJeff Kirsher __le16 *tx_cons_sb; 511adfc5217SJeff Kirsher 512adfc5217SJeff Kirsher int txq_index; 51365565884SMerav Sicron struct bnx2x_fastpath *parent_fp; 51465565884SMerav Sicron int tx_ring_size; 515adfc5217SJeff Kirsher }; 516adfc5217SJeff Kirsher 517621b4d66SDmitry Kravkov enum bnx2x_tpa_mode_t { 518621b4d66SDmitry Kravkov TPA_MODE_LRO, 519621b4d66SDmitry Kravkov TPA_MODE_GRO 520621b4d66SDmitry Kravkov }; 521621b4d66SDmitry Kravkov 522adfc5217SJeff Kirsher struct bnx2x_fastpath { 523adfc5217SJeff Kirsher struct bnx2x *bp; /* parent */ 524adfc5217SJeff Kirsher 525adfc5217SJeff Kirsher struct napi_struct napi; 5268f20aa57SDmitry Kravkov 527e0d1095aSCong Wang #ifdef CONFIG_NET_RX_BUSY_POLL 5288f20aa57SDmitry Kravkov unsigned int state; 5298f20aa57SDmitry Kravkov #define BNX2X_FP_STATE_IDLE 0 5308f20aa57SDmitry Kravkov #define BNX2X_FP_STATE_NAPI (1 << 0) /* NAPI owns this FP */ 5318f20aa57SDmitry Kravkov #define BNX2X_FP_STATE_POLL (1 << 1) /* poll owns this FP */ 5329a2620c8SYuval Mintz #define BNX2X_FP_STATE_DISABLED (1 << 2) 5339a2620c8SYuval Mintz #define BNX2X_FP_STATE_NAPI_YIELD (1 << 3) /* NAPI yielded this FP */ 5349a2620c8SYuval Mintz #define BNX2X_FP_STATE_POLL_YIELD (1 << 4) /* poll yielded this FP */ 5359a2620c8SYuval Mintz #define BNX2X_FP_OWNED (BNX2X_FP_STATE_NAPI | BNX2X_FP_STATE_POLL) 5368f20aa57SDmitry Kravkov #define BNX2X_FP_YIELD (BNX2X_FP_STATE_NAPI_YIELD | BNX2X_FP_STATE_POLL_YIELD) 5379a2620c8SYuval Mintz #define BNX2X_FP_LOCKED (BNX2X_FP_OWNED | BNX2X_FP_STATE_DISABLED) 5388f20aa57SDmitry Kravkov #define BNX2X_FP_USER_PEND (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_POLL_YIELD) 5398f20aa57SDmitry Kravkov /* protect state */ 5408f20aa57SDmitry Kravkov spinlock_t lock; 541e0d1095aSCong Wang #endif /* CONFIG_NET_RX_BUSY_POLL */ 5428f20aa57SDmitry Kravkov 543adfc5217SJeff Kirsher union host_hc_status_block status_blk; 54416a5fd92SYuval Mintz /* chip independent shortcuts into sb structure */ 545adfc5217SJeff Kirsher __le16 *sb_index_values; 546adfc5217SJeff Kirsher __le16 *sb_running_index; 54716a5fd92SYuval Mintz /* chip independent shortcut into rx_prods_offset memory */ 548adfc5217SJeff Kirsher u32 ustorm_rx_prods_offset; 549adfc5217SJeff Kirsher 550adfc5217SJeff Kirsher u32 rx_buf_size; 551d46d132cSEric Dumazet u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 552adfc5217SJeff Kirsher dma_addr_t status_blk_mapping; 553adfc5217SJeff Kirsher 554621b4d66SDmitry Kravkov enum bnx2x_tpa_mode_t mode; 555621b4d66SDmitry Kravkov 556adfc5217SJeff Kirsher u8 max_cos; /* actual number of active tx coses */ 55765565884SMerav Sicron struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 558adfc5217SJeff Kirsher 559adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 560adfc5217SJeff Kirsher struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 561adfc5217SJeff Kirsher 562adfc5217SJeff Kirsher struct eth_rx_bd *rx_desc_ring; 563adfc5217SJeff Kirsher dma_addr_t rx_desc_mapping; 564adfc5217SJeff Kirsher 565adfc5217SJeff Kirsher union eth_rx_cqe *rx_comp_ring; 566adfc5217SJeff Kirsher dma_addr_t rx_comp_mapping; 567adfc5217SJeff Kirsher 568adfc5217SJeff Kirsher /* SGE ring */ 569adfc5217SJeff Kirsher struct eth_rx_sge *rx_sge_ring; 570adfc5217SJeff Kirsher dma_addr_t rx_sge_mapping; 571adfc5217SJeff Kirsher 572adfc5217SJeff Kirsher u64 sge_mask[RX_SGE_MASK_LEN]; 573adfc5217SJeff Kirsher 574adfc5217SJeff Kirsher u32 cid; 575adfc5217SJeff Kirsher 576adfc5217SJeff Kirsher __le16 fp_hc_idx; 577adfc5217SJeff Kirsher 578adfc5217SJeff Kirsher u8 index; /* number in fp array */ 579f233cafeSDmitry Kravkov u8 rx_queue; /* index for skb_record */ 580adfc5217SJeff Kirsher u8 cl_id; /* eth client id */ 581adfc5217SJeff Kirsher u8 cl_qzone_id; 582adfc5217SJeff Kirsher u8 fw_sb_id; /* status block number in FW */ 583adfc5217SJeff Kirsher u8 igu_sb_id; /* status block number in HW */ 584adfc5217SJeff Kirsher 585adfc5217SJeff Kirsher u16 rx_bd_prod; 586adfc5217SJeff Kirsher u16 rx_bd_cons; 587adfc5217SJeff Kirsher u16 rx_comp_prod; 588adfc5217SJeff Kirsher u16 rx_comp_cons; 589adfc5217SJeff Kirsher u16 rx_sge_prod; 590adfc5217SJeff Kirsher /* The last maximal completed SGE */ 591adfc5217SJeff Kirsher u16 last_max_sge; 592adfc5217SJeff Kirsher __le16 *rx_cons_sb; 593adfc5217SJeff Kirsher unsigned long rx_pkt, 594adfc5217SJeff Kirsher rx_calls; 595adfc5217SJeff Kirsher 596adfc5217SJeff Kirsher /* TPA related */ 59715192a8cSBarak Witkowski struct bnx2x_agg_info *tpa_info; 598adfc5217SJeff Kirsher u8 disable_tpa; 599adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 600adfc5217SJeff Kirsher u64 tpa_queue_used; 601adfc5217SJeff Kirsher #endif 602adfc5217SJeff Kirsher /* The size is calculated using the following: 603adfc5217SJeff Kirsher sizeof name field from netdev structure + 604adfc5217SJeff Kirsher 4 ('-Xx-' string) + 605adfc5217SJeff Kirsher 4 (for the digits and to make it DWORD aligned) */ 606adfc5217SJeff Kirsher #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 607adfc5217SJeff Kirsher char name[FP_NAME_SIZE]; 608adfc5217SJeff Kirsher }; 609adfc5217SJeff Kirsher 61015192a8cSBarak Witkowski #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 61115192a8cSBarak Witkowski #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 61215192a8cSBarak Witkowski #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 61315192a8cSBarak Witkowski #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 614adfc5217SJeff Kirsher 615e0d1095aSCong Wang #ifdef CONFIG_NET_RX_BUSY_POLL 6168f20aa57SDmitry Kravkov static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp) 6178f20aa57SDmitry Kravkov { 6188f20aa57SDmitry Kravkov spin_lock_init(&fp->lock); 6198f20aa57SDmitry Kravkov fp->state = BNX2X_FP_STATE_IDLE; 6208f20aa57SDmitry Kravkov } 6218f20aa57SDmitry Kravkov 6228f20aa57SDmitry Kravkov /* called from the device poll routine to get ownership of a FP */ 6238f20aa57SDmitry Kravkov static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 6248f20aa57SDmitry Kravkov { 6258f20aa57SDmitry Kravkov bool rc = true; 6268f20aa57SDmitry Kravkov 6279a2620c8SYuval Mintz spin_lock_bh(&fp->lock); 6288f20aa57SDmitry Kravkov if (fp->state & BNX2X_FP_LOCKED) { 6298f20aa57SDmitry Kravkov WARN_ON(fp->state & BNX2X_FP_STATE_NAPI); 6308f20aa57SDmitry Kravkov fp->state |= BNX2X_FP_STATE_NAPI_YIELD; 6318f20aa57SDmitry Kravkov rc = false; 6328f20aa57SDmitry Kravkov } else { 6338f20aa57SDmitry Kravkov /* we don't care if someone yielded */ 6348f20aa57SDmitry Kravkov fp->state = BNX2X_FP_STATE_NAPI; 6358f20aa57SDmitry Kravkov } 6369a2620c8SYuval Mintz spin_unlock_bh(&fp->lock); 6378f20aa57SDmitry Kravkov return rc; 6388f20aa57SDmitry Kravkov } 6398f20aa57SDmitry Kravkov 6408f20aa57SDmitry Kravkov /* returns true is someone tried to get the FP while napi had it */ 6418f20aa57SDmitry Kravkov static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 6428f20aa57SDmitry Kravkov { 6438f20aa57SDmitry Kravkov bool rc = false; 6448f20aa57SDmitry Kravkov 6459a2620c8SYuval Mintz spin_lock_bh(&fp->lock); 6468f20aa57SDmitry Kravkov WARN_ON(fp->state & 6478f20aa57SDmitry Kravkov (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_NAPI_YIELD)); 6488f20aa57SDmitry Kravkov 6498f20aa57SDmitry Kravkov if (fp->state & BNX2X_FP_STATE_POLL_YIELD) 6508f20aa57SDmitry Kravkov rc = true; 6519a2620c8SYuval Mintz 6529a2620c8SYuval Mintz /* state ==> idle, unless currently disabled */ 6539a2620c8SYuval Mintz fp->state &= BNX2X_FP_STATE_DISABLED; 6549a2620c8SYuval Mintz spin_unlock_bh(&fp->lock); 6558f20aa57SDmitry Kravkov return rc; 6568f20aa57SDmitry Kravkov } 6578f20aa57SDmitry Kravkov 6588f20aa57SDmitry Kravkov /* called from bnx2x_low_latency_poll() */ 6598f20aa57SDmitry Kravkov static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 6608f20aa57SDmitry Kravkov { 6618f20aa57SDmitry Kravkov bool rc = true; 6628f20aa57SDmitry Kravkov 6638f20aa57SDmitry Kravkov spin_lock_bh(&fp->lock); 6648f20aa57SDmitry Kravkov if ((fp->state & BNX2X_FP_LOCKED)) { 6658f20aa57SDmitry Kravkov fp->state |= BNX2X_FP_STATE_POLL_YIELD; 6668f20aa57SDmitry Kravkov rc = false; 6678f20aa57SDmitry Kravkov } else { 6688f20aa57SDmitry Kravkov /* preserve yield marks */ 6698f20aa57SDmitry Kravkov fp->state |= BNX2X_FP_STATE_POLL; 6708f20aa57SDmitry Kravkov } 6718f20aa57SDmitry Kravkov spin_unlock_bh(&fp->lock); 6728f20aa57SDmitry Kravkov return rc; 6738f20aa57SDmitry Kravkov } 6748f20aa57SDmitry Kravkov 6758f20aa57SDmitry Kravkov /* returns true if someone tried to get the FP while it was locked */ 6768f20aa57SDmitry Kravkov static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 6778f20aa57SDmitry Kravkov { 6788f20aa57SDmitry Kravkov bool rc = false; 6798f20aa57SDmitry Kravkov 6808f20aa57SDmitry Kravkov spin_lock_bh(&fp->lock); 6818f20aa57SDmitry Kravkov WARN_ON(fp->state & BNX2X_FP_STATE_NAPI); 6828f20aa57SDmitry Kravkov 6838f20aa57SDmitry Kravkov if (fp->state & BNX2X_FP_STATE_POLL_YIELD) 6848f20aa57SDmitry Kravkov rc = true; 6859a2620c8SYuval Mintz 6869a2620c8SYuval Mintz /* state ==> idle, unless currently disabled */ 6879a2620c8SYuval Mintz fp->state &= BNX2X_FP_STATE_DISABLED; 6888f20aa57SDmitry Kravkov spin_unlock_bh(&fp->lock); 6898f20aa57SDmitry Kravkov return rc; 6908f20aa57SDmitry Kravkov } 6918f20aa57SDmitry Kravkov 6928f20aa57SDmitry Kravkov /* true if a socket is polling, even if it did not get the lock */ 6938f20aa57SDmitry Kravkov static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 6948f20aa57SDmitry Kravkov { 6959a2620c8SYuval Mintz WARN_ON(!(fp->state & BNX2X_FP_OWNED)); 6968f20aa57SDmitry Kravkov return fp->state & BNX2X_FP_USER_PEND; 6978f20aa57SDmitry Kravkov } 6989a2620c8SYuval Mintz 6999a2620c8SYuval Mintz /* false if fp is currently owned */ 7009a2620c8SYuval Mintz static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) 7019a2620c8SYuval Mintz { 7029a2620c8SYuval Mintz int rc = true; 7039a2620c8SYuval Mintz 7049a2620c8SYuval Mintz spin_lock_bh(&fp->lock); 7059a2620c8SYuval Mintz if (fp->state & BNX2X_FP_OWNED) 7069a2620c8SYuval Mintz rc = false; 7079a2620c8SYuval Mintz fp->state |= BNX2X_FP_STATE_DISABLED; 7089a2620c8SYuval Mintz spin_unlock_bh(&fp->lock); 7099a2620c8SYuval Mintz 7109a2620c8SYuval Mintz return rc; 7119a2620c8SYuval Mintz } 7128f20aa57SDmitry Kravkov #else 7138f20aa57SDmitry Kravkov static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp) 7148f20aa57SDmitry Kravkov { 7158f20aa57SDmitry Kravkov } 7168f20aa57SDmitry Kravkov 7178f20aa57SDmitry Kravkov static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 7188f20aa57SDmitry Kravkov { 7198f20aa57SDmitry Kravkov return true; 7208f20aa57SDmitry Kravkov } 7218f20aa57SDmitry Kravkov 7228f20aa57SDmitry Kravkov static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 7238f20aa57SDmitry Kravkov { 7248f20aa57SDmitry Kravkov return false; 7258f20aa57SDmitry Kravkov } 7268f20aa57SDmitry Kravkov 7278f20aa57SDmitry Kravkov static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 7288f20aa57SDmitry Kravkov { 7298f20aa57SDmitry Kravkov return false; 7308f20aa57SDmitry Kravkov } 7318f20aa57SDmitry Kravkov 7328f20aa57SDmitry Kravkov static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 7338f20aa57SDmitry Kravkov { 7348f20aa57SDmitry Kravkov return false; 7358f20aa57SDmitry Kravkov } 7368f20aa57SDmitry Kravkov 7378f20aa57SDmitry Kravkov static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 7388f20aa57SDmitry Kravkov { 7398f20aa57SDmitry Kravkov return false; 7408f20aa57SDmitry Kravkov } 7419a2620c8SYuval Mintz static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) 7429a2620c8SYuval Mintz { 7439a2620c8SYuval Mintz return true; 7449a2620c8SYuval Mintz } 745e0d1095aSCong Wang #endif /* CONFIG_NET_RX_BUSY_POLL */ 7468f20aa57SDmitry Kravkov 747adfc5217SJeff Kirsher /* Use 2500 as a mini-jumbo MTU for FCoE */ 748adfc5217SJeff Kirsher #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 749adfc5217SJeff Kirsher 75065565884SMerav Sicron #define FCOE_IDX_OFFSET 0 75165565884SMerav Sicron 75265565884SMerav Sicron #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 75365565884SMerav Sicron FCOE_IDX_OFFSET) 75465565884SMerav Sicron #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 755adfc5217SJeff Kirsher #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 75615192a8cSBarak Witkowski #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 75715192a8cSBarak Witkowski #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 758adfc5217SJeff Kirsher #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 75965565884SMerav Sicron txdata_ptr[FIRST_TX_COS_INDEX] \ 76065565884SMerav Sicron ->var) 761adfc5217SJeff Kirsher 76255c11941SMerav Sicron #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 76355c11941SMerav Sicron #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 76465565884SMerav Sicron #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 765adfc5217SJeff Kirsher 766adfc5217SJeff Kirsher /* MC hsi */ 767adfc5217SJeff Kirsher #define MAX_FETCH_BD 13 /* HW max BDs per packet */ 768adfc5217SJeff Kirsher #define RX_COPY_THRESH 92 769adfc5217SJeff Kirsher 770adfc5217SJeff Kirsher #define NUM_TX_RINGS 16 771adfc5217SJeff Kirsher #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 7728decf868SDavid S. Miller #define NEXT_PAGE_TX_DESC_CNT 1 7738decf868SDavid S. Miller #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 774adfc5217SJeff Kirsher #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 775adfc5217SJeff Kirsher #define MAX_TX_BD (NUM_TX_BD - 1) 776adfc5217SJeff Kirsher #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 777adfc5217SJeff Kirsher #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 7788decf868SDavid S. Miller (MAX_TX_DESC_CNT - 1)) ? \ 7798decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 7808decf868SDavid S. Miller (x) + 1) 781adfc5217SJeff Kirsher #define TX_BD(x) ((x) & MAX_TX_BD) 782adfc5217SJeff Kirsher #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 783adfc5217SJeff Kirsher 7847df2dc6bSDmitry Kravkov /* number of NEXT_PAGE descriptors may be required during placement */ 7857df2dc6bSDmitry Kravkov #define NEXT_CNT_PER_TX_PKT(bds) \ 7867df2dc6bSDmitry Kravkov (((bds) + MAX_TX_DESC_CNT - 1) / \ 7877df2dc6bSDmitry Kravkov MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 7887df2dc6bSDmitry Kravkov /* max BDs per tx packet w/o next_pages: 7897df2dc6bSDmitry Kravkov * START_BD - describes packed 7907df2dc6bSDmitry Kravkov * START_BD(splitted) - includes unpaged data segment for GSO 7917df2dc6bSDmitry Kravkov * PARSING_BD - for TSO and CSUM data 792a848ade4SDmitry Kravkov * PARSING_BD2 - for encapsulation data 79316a5fd92SYuval Mintz * Frag BDs - describes pages for frags 7947df2dc6bSDmitry Kravkov */ 795a848ade4SDmitry Kravkov #define BDS_PER_TX_PKT 4 7967df2dc6bSDmitry Kravkov #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 7977df2dc6bSDmitry Kravkov /* max BDs per tx packet including next pages */ 7987df2dc6bSDmitry Kravkov #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 7997df2dc6bSDmitry Kravkov NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 8007df2dc6bSDmitry Kravkov 801adfc5217SJeff Kirsher /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 802adfc5217SJeff Kirsher #define NUM_RX_RINGS 8 803adfc5217SJeff Kirsher #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 8048decf868SDavid S. Miller #define NEXT_PAGE_RX_DESC_CNT 2 8058decf868SDavid S. Miller #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 806adfc5217SJeff Kirsher #define RX_DESC_MASK (RX_DESC_CNT - 1) 807adfc5217SJeff Kirsher #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 808adfc5217SJeff Kirsher #define MAX_RX_BD (NUM_RX_BD - 1) 809adfc5217SJeff Kirsher #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 8108decf868SDavid S. Miller 8118decf868SDavid S. Miller /* dropless fc calculations for BDs 8128decf868SDavid S. Miller * 8138decf868SDavid S. Miller * Number of BDs should as number of buffers in BRB: 8148decf868SDavid S. Miller * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 8158decf868SDavid S. Miller * "next" elements on each page 8168decf868SDavid S. Miller */ 8178decf868SDavid S. Miller #define NUM_BD_REQ BRB_SIZE(bp) 8188decf868SDavid S. Miller #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 8198decf868SDavid S. Miller MAX_RX_DESC_CNT) 8208decf868SDavid S. Miller #define BD_TH_LO(bp) (NUM_BD_REQ + \ 8218decf868SDavid S. Miller NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 8228decf868SDavid S. Miller FW_DROP_LEVEL(bp)) 8238decf868SDavid S. Miller #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 8248decf868SDavid S. Miller 8258decf868SDavid S. Miller #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 826adfc5217SJeff Kirsher 827adfc5217SJeff Kirsher #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 828adfc5217SJeff Kirsher ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 829adfc5217SJeff Kirsher ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 830adfc5217SJeff Kirsher #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 831adfc5217SJeff Kirsher #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 832adfc5217SJeff Kirsher #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 833adfc5217SJeff Kirsher MIN_RX_AVAIL)) 834adfc5217SJeff Kirsher 835adfc5217SJeff Kirsher #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 8368decf868SDavid S. Miller (MAX_RX_DESC_CNT - 1)) ? \ 8378decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 8388decf868SDavid S. Miller (x) + 1) 839adfc5217SJeff Kirsher #define RX_BD(x) ((x) & MAX_RX_BD) 840adfc5217SJeff Kirsher 841adfc5217SJeff Kirsher /* 842adfc5217SJeff Kirsher * As long as CQE is X times bigger than BD entry we have to allocate X times 843adfc5217SJeff Kirsher * more pages for CQ ring in order to keep it balanced with BD ring 844adfc5217SJeff Kirsher */ 845adfc5217SJeff Kirsher #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 846adfc5217SJeff Kirsher #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 847adfc5217SJeff Kirsher #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 8488decf868SDavid S. Miller #define NEXT_PAGE_RCQ_DESC_CNT 1 8498decf868SDavid S. Miller #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 850adfc5217SJeff Kirsher #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 851adfc5217SJeff Kirsher #define MAX_RCQ_BD (NUM_RCQ_BD - 1) 852adfc5217SJeff Kirsher #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 853adfc5217SJeff Kirsher #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 8548decf868SDavid S. Miller (MAX_RCQ_DESC_CNT - 1)) ? \ 8558decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 8568decf868SDavid S. Miller (x) + 1) 857adfc5217SJeff Kirsher #define RCQ_BD(x) ((x) & MAX_RCQ_BD) 858adfc5217SJeff Kirsher 8598decf868SDavid S. Miller /* dropless fc calculations for RCQs 8608decf868SDavid S. Miller * 8618decf868SDavid S. Miller * Number of RCQs should be as number of buffers in BRB: 8628decf868SDavid S. Miller * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 8638decf868SDavid S. Miller * "next" elements on each page 8648decf868SDavid S. Miller */ 8658decf868SDavid S. Miller #define NUM_RCQ_REQ BRB_SIZE(bp) 8668decf868SDavid S. Miller #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 8678decf868SDavid S. Miller MAX_RCQ_DESC_CNT) 8688decf868SDavid S. Miller #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 8698decf868SDavid S. Miller NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 8708decf868SDavid S. Miller FW_DROP_LEVEL(bp)) 8718decf868SDavid S. Miller #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 8728decf868SDavid S. Miller 873adfc5217SJeff Kirsher /* This is needed for determining of last_max */ 874adfc5217SJeff Kirsher #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 875adfc5217SJeff Kirsher #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 876adfc5217SJeff Kirsher 877adfc5217SJeff Kirsher #define BNX2X_SWCID_SHIFT 17 878adfc5217SJeff Kirsher #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 879adfc5217SJeff Kirsher 880adfc5217SJeff Kirsher /* used on a CID received from the HW */ 881adfc5217SJeff Kirsher #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 882adfc5217SJeff Kirsher #define CQE_CMD(x) (le32_to_cpu(x) >> \ 883adfc5217SJeff Kirsher COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 884adfc5217SJeff Kirsher 885adfc5217SJeff Kirsher #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 886adfc5217SJeff Kirsher le32_to_cpu((bd)->addr_lo)) 887adfc5217SJeff Kirsher #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 888adfc5217SJeff Kirsher 889adfc5217SJeff Kirsher #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 890b9871bcfSAriel Elior #define BNX2X_DB_SHIFT 3 /* 8 bytes*/ 891adfc5217SJeff Kirsher #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 892adfc5217SJeff Kirsher #error "Min DB doorbell stride is 8" 893adfc5217SJeff Kirsher #endif 894adfc5217SJeff Kirsher #define DOORBELL(bp, cid, val) \ 895adfc5217SJeff Kirsher do { \ 896b9871bcfSAriel Elior writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \ 897adfc5217SJeff Kirsher } while (0) 898adfc5217SJeff Kirsher 899adfc5217SJeff Kirsher /* TX CSUM helpers */ 900adfc5217SJeff Kirsher #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 901adfc5217SJeff Kirsher skb->csum_offset) 902adfc5217SJeff Kirsher #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 903adfc5217SJeff Kirsher skb->csum_offset)) 904adfc5217SJeff Kirsher 90591226790SDmitry Kravkov #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) 906adfc5217SJeff Kirsher 907adfc5217SJeff Kirsher #define XMIT_PLAIN 0 908a848ade4SDmitry Kravkov #define XMIT_CSUM_V4 (1 << 0) 909a848ade4SDmitry Kravkov #define XMIT_CSUM_V6 (1 << 1) 910a848ade4SDmitry Kravkov #define XMIT_CSUM_TCP (1 << 2) 911a848ade4SDmitry Kravkov #define XMIT_GSO_V4 (1 << 3) 912a848ade4SDmitry Kravkov #define XMIT_GSO_V6 (1 << 4) 913a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC_V4 (1 << 5) 914a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC_V6 (1 << 6) 915a848ade4SDmitry Kravkov #define XMIT_GSO_ENC_V4 (1 << 7) 916a848ade4SDmitry Kravkov #define XMIT_GSO_ENC_V6 (1 << 8) 917adfc5217SJeff Kirsher 918a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) 919a848ade4SDmitry Kravkov #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) 920adfc5217SJeff Kirsher 921a848ade4SDmitry Kravkov #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) 922a848ade4SDmitry Kravkov #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) 923adfc5217SJeff Kirsher 924adfc5217SJeff Kirsher /* stuff added to make the code fit 80Col */ 925adfc5217SJeff Kirsher #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 926adfc5217SJeff Kirsher #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 927adfc5217SJeff Kirsher #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 928adfc5217SJeff Kirsher #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 929adfc5217SJeff Kirsher #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 930adfc5217SJeff Kirsher 931adfc5217SJeff Kirsher #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 932adfc5217SJeff Kirsher 933adfc5217SJeff Kirsher #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 934adfc5217SJeff Kirsher (((le16_to_cpu(flags) & \ 935adfc5217SJeff Kirsher PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 936adfc5217SJeff Kirsher PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 937adfc5217SJeff Kirsher == PRS_FLAG_OVERETH_IPV4) 938adfc5217SJeff Kirsher #define BNX2X_RX_SUM_FIX(cqe) \ 939adfc5217SJeff Kirsher BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 940adfc5217SJeff Kirsher 941adfc5217SJeff Kirsher #define FP_USB_FUNC_OFF \ 942adfc5217SJeff Kirsher offsetof(struct cstorm_status_block_u, func) 943adfc5217SJeff Kirsher #define FP_CSB_FUNC_OFF \ 944adfc5217SJeff Kirsher offsetof(struct cstorm_status_block_c, func) 945adfc5217SJeff Kirsher 9468decf868SDavid S. Miller #define HC_INDEX_ETH_RX_CQ_CONS 1 947adfc5217SJeff Kirsher 9488decf868SDavid S. Miller #define HC_INDEX_OOO_TX_CQ_CONS 4 9498decf868SDavid S. Miller 9508decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 9518decf868SDavid S. Miller 9528decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 9538decf868SDavid S. Miller 9548decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 955adfc5217SJeff Kirsher 956adfc5217SJeff Kirsher #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 957adfc5217SJeff Kirsher 958adfc5217SJeff Kirsher #define BNX2X_RX_SB_INDEX \ 959adfc5217SJeff Kirsher (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 960adfc5217SJeff Kirsher 961adfc5217SJeff Kirsher #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 962adfc5217SJeff Kirsher 963adfc5217SJeff Kirsher #define BNX2X_TX_SB_INDEX_COS0 \ 964adfc5217SJeff Kirsher (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 965adfc5217SJeff Kirsher 966adfc5217SJeff Kirsher /* end of fast path */ 967adfc5217SJeff Kirsher 968adfc5217SJeff Kirsher /* common */ 969adfc5217SJeff Kirsher 970adfc5217SJeff Kirsher struct bnx2x_common { 971adfc5217SJeff Kirsher 972adfc5217SJeff Kirsher u32 chip_id; 973adfc5217SJeff Kirsher /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 974adfc5217SJeff Kirsher #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 975adfc5217SJeff Kirsher 976adfc5217SJeff Kirsher #define CHIP_NUM(bp) (bp->common.chip_id >> 16) 977adfc5217SJeff Kirsher #define CHIP_NUM_57710 0x164e 978adfc5217SJeff Kirsher #define CHIP_NUM_57711 0x164f 979adfc5217SJeff Kirsher #define CHIP_NUM_57711E 0x1650 980adfc5217SJeff Kirsher #define CHIP_NUM_57712 0x1662 981adfc5217SJeff Kirsher #define CHIP_NUM_57712_MF 0x1663 9828395be5eSAriel Elior #define CHIP_NUM_57712_VF 0x166f 983adfc5217SJeff Kirsher #define CHIP_NUM_57713 0x1651 984adfc5217SJeff Kirsher #define CHIP_NUM_57713E 0x1652 985adfc5217SJeff Kirsher #define CHIP_NUM_57800 0x168a 986adfc5217SJeff Kirsher #define CHIP_NUM_57800_MF 0x16a5 9878395be5eSAriel Elior #define CHIP_NUM_57800_VF 0x16a9 988adfc5217SJeff Kirsher #define CHIP_NUM_57810 0x168e 989adfc5217SJeff Kirsher #define CHIP_NUM_57810_MF 0x16ae 9908395be5eSAriel Elior #define CHIP_NUM_57810_VF 0x16af 9917e8e02dfSBarak Witkowski #define CHIP_NUM_57811 0x163d 9927e8e02dfSBarak Witkowski #define CHIP_NUM_57811_MF 0x163e 9938395be5eSAriel Elior #define CHIP_NUM_57811_VF 0x163f 994c3def943SYuval Mintz #define CHIP_NUM_57840_OBSOLETE 0x168d 995c3def943SYuval Mintz #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 996c3def943SYuval Mintz #define CHIP_NUM_57840_4_10 0x16a1 997c3def943SYuval Mintz #define CHIP_NUM_57840_2_20 0x16a2 998c3def943SYuval Mintz #define CHIP_NUM_57840_MF 0x16a4 9998395be5eSAriel Elior #define CHIP_NUM_57840_VF 0x16ad 1000adfc5217SJeff Kirsher #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 1001adfc5217SJeff Kirsher #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 1002adfc5217SJeff Kirsher #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 1003adfc5217SJeff Kirsher #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 10048395be5eSAriel Elior #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 1005adfc5217SJeff Kirsher #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 1006adfc5217SJeff Kirsher #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 1007adfc5217SJeff Kirsher #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 10088395be5eSAriel Elior #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 1009adfc5217SJeff Kirsher #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 1010adfc5217SJeff Kirsher #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 10118395be5eSAriel Elior #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 10127e8e02dfSBarak Witkowski #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 10137e8e02dfSBarak Witkowski #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 10148395be5eSAriel Elior #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 1015c3def943SYuval Mintz #define CHIP_IS_57840(bp) \ 1016c3def943SYuval Mintz ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 1017c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 1018c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 1019c3def943SYuval Mintz #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 1020c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 10218395be5eSAriel Elior #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 1022adfc5217SJeff Kirsher #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 1023adfc5217SJeff Kirsher CHIP_IS_57711E(bp)) 1024edb944d2SDmitry Kravkov #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ 1025edb944d2SDmitry Kravkov CHIP_IS_57811_MF(bp) || \ 1026edb944d2SDmitry Kravkov CHIP_IS_57811_VF(bp)) 1027adfc5217SJeff Kirsher #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 10286ab20355SYuval Mintz CHIP_IS_57712_MF(bp) || \ 10296ab20355SYuval Mintz CHIP_IS_57712_VF(bp)) 1030adfc5217SJeff Kirsher #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 1031adfc5217SJeff Kirsher CHIP_IS_57800_MF(bp) || \ 10326ab20355SYuval Mintz CHIP_IS_57800_VF(bp) || \ 1033adfc5217SJeff Kirsher CHIP_IS_57810(bp) || \ 1034adfc5217SJeff Kirsher CHIP_IS_57810_MF(bp) || \ 10358395be5eSAriel Elior CHIP_IS_57810_VF(bp) || \ 1036edb944d2SDmitry Kravkov CHIP_IS_57811xx(bp) || \ 1037adfc5217SJeff Kirsher CHIP_IS_57840(bp) || \ 10388395be5eSAriel Elior CHIP_IS_57840_MF(bp) || \ 10398395be5eSAriel Elior CHIP_IS_57840_VF(bp)) 1040adfc5217SJeff Kirsher #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 1041adfc5217SJeff Kirsher #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 1042adfc5217SJeff Kirsher #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 1043adfc5217SJeff Kirsher 1044adfc5217SJeff Kirsher #define CHIP_REV_SHIFT 12 1045adfc5217SJeff Kirsher #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1046adfc5217SJeff Kirsher #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 1047adfc5217SJeff Kirsher #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1048adfc5217SJeff Kirsher #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1049adfc5217SJeff Kirsher /* assume maximum 5 revisions */ 1050adfc5217SJeff Kirsher #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 1051adfc5217SJeff Kirsher /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 1052adfc5217SJeff Kirsher #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1053adfc5217SJeff Kirsher !(CHIP_REV_VAL(bp) & 0x00001000)) 1054adfc5217SJeff Kirsher /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 1055adfc5217SJeff Kirsher #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1056adfc5217SJeff Kirsher (CHIP_REV_VAL(bp) & 0x00001000)) 1057adfc5217SJeff Kirsher 1058adfc5217SJeff Kirsher #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 1059adfc5217SJeff Kirsher ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 1060adfc5217SJeff Kirsher 1061adfc5217SJeff Kirsher #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 1062adfc5217SJeff Kirsher #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 1063adfc5217SJeff Kirsher #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 1064adfc5217SJeff Kirsher (CHIP_REV_SHIFT + 1)) \ 1065adfc5217SJeff Kirsher << CHIP_REV_SHIFT) 1066adfc5217SJeff Kirsher #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 1067adfc5217SJeff Kirsher CHIP_REV_SIM(bp) :\ 1068adfc5217SJeff Kirsher CHIP_REV_VAL(bp)) 1069adfc5217SJeff Kirsher #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 1070adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Bx)) 1071adfc5217SJeff Kirsher #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 1072adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Ax)) 107355c11941SMerav Sicron /* This define is used in two main places: 107416a5fd92SYuval Mintz * 1. In the early stages of nic_load, to know if to configure Parser / Searcher 107555c11941SMerav Sicron * to nic-only mode or to offload mode. Offload mode is configured if either the 107655c11941SMerav Sicron * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 107755c11941SMerav Sicron * registered for this port (which means that the user wants storage services). 107855c11941SMerav Sicron * 2. During cnic-related load, to know if offload mode is already configured in 107916a5fd92SYuval Mintz * the HW or needs to be configured. 108055c11941SMerav Sicron * Since the transition from nic-mode to offload-mode in HW causes traffic 108116a5fd92SYuval Mintz * corruption, nic-mode is configured only in ports on which storage services 108255c11941SMerav Sicron * where never requested. 108355c11941SMerav Sicron */ 108455c11941SMerav Sicron #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 1085adfc5217SJeff Kirsher 1086adfc5217SJeff Kirsher int flash_size; 1087adfc5217SJeff Kirsher #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 1088adfc5217SJeff Kirsher #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 1089adfc5217SJeff Kirsher #define BNX2X_NVRAM_PAGE_SIZE 256 1090adfc5217SJeff Kirsher 1091adfc5217SJeff Kirsher u32 shmem_base; 1092adfc5217SJeff Kirsher u32 shmem2_base; 1093adfc5217SJeff Kirsher u32 mf_cfg_base; 1094adfc5217SJeff Kirsher u32 mf2_cfg_base; 1095adfc5217SJeff Kirsher 1096adfc5217SJeff Kirsher u32 hw_config; 1097adfc5217SJeff Kirsher 1098adfc5217SJeff Kirsher u32 bc_ver; 1099adfc5217SJeff Kirsher 1100adfc5217SJeff Kirsher u8 int_block; 1101adfc5217SJeff Kirsher #define INT_BLOCK_HC 0 1102adfc5217SJeff Kirsher #define INT_BLOCK_IGU 1 1103adfc5217SJeff Kirsher #define INT_BLOCK_MODE_NORMAL 0 1104adfc5217SJeff Kirsher #define INT_BLOCK_MODE_BW_COMP 2 1105adfc5217SJeff Kirsher #define CHIP_INT_MODE_IS_NBC(bp) \ 1106adfc5217SJeff Kirsher (!CHIP_IS_E1x(bp) && \ 1107adfc5217SJeff Kirsher !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 1108adfc5217SJeff Kirsher #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 1109adfc5217SJeff Kirsher 1110adfc5217SJeff Kirsher u8 chip_port_mode; 1111adfc5217SJeff Kirsher #define CHIP_4_PORT_MODE 0x0 1112adfc5217SJeff Kirsher #define CHIP_2_PORT_MODE 0x1 1113adfc5217SJeff Kirsher #define CHIP_PORT_MODE_NONE 0x2 1114adfc5217SJeff Kirsher #define CHIP_MODE(bp) (bp->common.chip_port_mode) 1115adfc5217SJeff Kirsher #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 11161d187b34SBarak Witkowski 11171d187b34SBarak Witkowski u32 boot_mode; 1118adfc5217SJeff Kirsher }; 1119adfc5217SJeff Kirsher 1120adfc5217SJeff Kirsher /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 1121adfc5217SJeff Kirsher #define BNX2X_IGU_STAS_MSG_VF_CNT 64 1122adfc5217SJeff Kirsher #define BNX2X_IGU_STAS_MSG_PF_CNT 4 1123adfc5217SJeff Kirsher 112427c1151cSYaniv Rosner #define MAX_IGU_ATTN_ACK_TO 100 1125adfc5217SJeff Kirsher /* end of common */ 1126adfc5217SJeff Kirsher 1127adfc5217SJeff Kirsher /* port */ 1128adfc5217SJeff Kirsher 1129adfc5217SJeff Kirsher struct bnx2x_port { 1130adfc5217SJeff Kirsher u32 pmf; 1131adfc5217SJeff Kirsher 1132adfc5217SJeff Kirsher u32 link_config[LINK_CONFIG_SIZE]; 1133adfc5217SJeff Kirsher 1134adfc5217SJeff Kirsher u32 supported[LINK_CONFIG_SIZE]; 1135adfc5217SJeff Kirsher /* link settings - missing defines */ 1136adfc5217SJeff Kirsher #define SUPPORTED_2500baseX_Full (1 << 15) 1137adfc5217SJeff Kirsher 1138adfc5217SJeff Kirsher u32 advertising[LINK_CONFIG_SIZE]; 1139adfc5217SJeff Kirsher /* link settings - missing defines */ 1140adfc5217SJeff Kirsher #define ADVERTISED_2500baseX_Full (1 << 15) 1141adfc5217SJeff Kirsher 1142adfc5217SJeff Kirsher u32 phy_addr; 1143adfc5217SJeff Kirsher 1144adfc5217SJeff Kirsher /* used to synchronize phy accesses */ 1145adfc5217SJeff Kirsher struct mutex phy_mutex; 1146adfc5217SJeff Kirsher 1147adfc5217SJeff Kirsher u32 port_stx; 1148adfc5217SJeff Kirsher 1149adfc5217SJeff Kirsher struct nig_stats old_nig_stats; 1150adfc5217SJeff Kirsher }; 1151adfc5217SJeff Kirsher 1152adfc5217SJeff Kirsher /* end of port */ 1153adfc5217SJeff Kirsher 1154adfc5217SJeff Kirsher #define STATS_OFFSET32(stat_name) \ 1155adfc5217SJeff Kirsher (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 1156adfc5217SJeff Kirsher 1157adfc5217SJeff Kirsher /* slow path */ 1158adfc5217SJeff Kirsher 1159adfc5217SJeff Kirsher /* slow path work-queue */ 1160adfc5217SJeff Kirsher extern struct workqueue_struct *bnx2x_wq; 1161adfc5217SJeff Kirsher 1162adfc5217SJeff Kirsher #define BNX2X_MAX_NUM_OF_VFS 64 1163b9871bcfSAriel Elior #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */ 11641ab4434cSAriel Elior #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 1165b9871bcfSAriel Elior 1166b9871bcfSAriel Elior /* We need to reserve doorbell addresses for all VF and queue combinations */ 11671ab4434cSAriel Elior #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 1168b9871bcfSAriel Elior 1169b9871bcfSAriel Elior /* The doorbell is configured to have the same number of CIDs for PFs and for 1170b9871bcfSAriel Elior * VFs. For this reason the PF CID zone is as large as the VF zone. 1171b9871bcfSAriel Elior */ 1172b9871bcfSAriel Elior #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS 1173b9871bcfSAriel Elior #define BNX2X_MAX_NUM_VF_QUEUES 64 1174adfc5217SJeff Kirsher #define BNX2X_VF_ID_INVALID 0xFF 1175adfc5217SJeff Kirsher 1176b9871bcfSAriel Elior /* the number of VF CIDS multiplied by the amount of bytes reserved for each 1177b9871bcfSAriel Elior * cid must not exceed the size of the VF doorbell 1178b9871bcfSAriel Elior */ 1179b9871bcfSAriel Elior #define BNX2X_VF_BAR_SIZE 512 1180b9871bcfSAriel Elior #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT)) 1181b9871bcfSAriel Elior #error "VF doorbell bar size is 512" 1182b9871bcfSAriel Elior #endif 1183b9871bcfSAriel Elior 1184adfc5217SJeff Kirsher /* 1185adfc5217SJeff Kirsher * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 1186adfc5217SJeff Kirsher * control by the number of fast-path status blocks supported by the 1187adfc5217SJeff Kirsher * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 1188adfc5217SJeff Kirsher * status block represents an independent interrupts context that can 1189adfc5217SJeff Kirsher * serve a regular L2 networking queue. However special L2 queues such 1190adfc5217SJeff Kirsher * as the FCoE queue do not require a FP-SB and other components like 1191adfc5217SJeff Kirsher * the CNIC may consume FP-SB reducing the number of possible L2 queues 1192adfc5217SJeff Kirsher * 1193adfc5217SJeff Kirsher * If the maximum number of FP-SB available is X then: 1194adfc5217SJeff Kirsher * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 1195adfc5217SJeff Kirsher * regular L2 queues is Y=X-1 119616a5fd92SYuval Mintz * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1197adfc5217SJeff Kirsher * c. If the FCoE L2 queue is supported the actual number of L2 queues 1198adfc5217SJeff Kirsher * is Y+1 1199adfc5217SJeff Kirsher * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1200adfc5217SJeff Kirsher * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1201adfc5217SJeff Kirsher * FP interrupt context for the CNIC). 1202adfc5217SJeff Kirsher * e. The number of HW context (CID count) is always X or X+1 if FCoE 120316a5fd92SYuval Mintz * L2 queue is supported. The cid for the FCoE L2 queue is always X. 1204adfc5217SJeff Kirsher */ 1205adfc5217SJeff Kirsher 1206adfc5217SJeff Kirsher /* fast-path interrupt contexts E1x */ 1207adfc5217SJeff Kirsher #define FP_SB_MAX_E1x 16 1208adfc5217SJeff Kirsher /* fast-path interrupt contexts E2 */ 1209adfc5217SJeff Kirsher #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1210adfc5217SJeff Kirsher 1211adfc5217SJeff Kirsher union cdu_context { 1212adfc5217SJeff Kirsher struct eth_context eth; 1213adfc5217SJeff Kirsher char pad[1024]; 1214adfc5217SJeff Kirsher }; 1215adfc5217SJeff Kirsher 1216adfc5217SJeff Kirsher /* CDU host DB constants */ 1217a052997eSMerav Sicron #define CDU_ILT_PAGE_SZ_HW 2 1218a052997eSMerav Sicron #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1219adfc5217SJeff Kirsher #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1220adfc5217SJeff Kirsher 1221adfc5217SJeff Kirsher #define CNIC_ISCSI_CID_MAX 256 1222adfc5217SJeff Kirsher #define CNIC_FCOE_CID_MAX 2048 1223adfc5217SJeff Kirsher #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1224adfc5217SJeff Kirsher #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1225adfc5217SJeff Kirsher 1226adfc5217SJeff Kirsher #define QM_ILT_PAGE_SZ_HW 0 1227adfc5217SJeff Kirsher #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1228adfc5217SJeff Kirsher #define QM_CID_ROUND 1024 1229adfc5217SJeff Kirsher 1230adfc5217SJeff Kirsher /* TM (timers) host DB constants */ 1231adfc5217SJeff Kirsher #define TM_ILT_PAGE_SZ_HW 0 1232adfc5217SJeff Kirsher #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 12330907f34cSAriel Elior #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \ 12340907f34cSAriel Elior BNX2X_VF_CIDS + \ 12350907f34cSAriel Elior CNIC_ISCSI_CID_MAX) 1236adfc5217SJeff Kirsher #define TM_ILT_SZ (8 * TM_CONN_NUM) 1237adfc5217SJeff Kirsher #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1238adfc5217SJeff Kirsher 1239adfc5217SJeff Kirsher /* SRC (Searcher) host DB constants */ 1240adfc5217SJeff Kirsher #define SRC_ILT_PAGE_SZ_HW 0 1241adfc5217SJeff Kirsher #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1242adfc5217SJeff Kirsher #define SRC_HASH_BITS 10 1243adfc5217SJeff Kirsher #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1244adfc5217SJeff Kirsher #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1245adfc5217SJeff Kirsher #define SRC_T2_SZ SRC_ILT_SZ 1246adfc5217SJeff Kirsher #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1247adfc5217SJeff Kirsher 1248adfc5217SJeff Kirsher #define MAX_DMAE_C 8 1249adfc5217SJeff Kirsher 1250adfc5217SJeff Kirsher /* DMA memory not used in fastpath */ 1251adfc5217SJeff Kirsher struct bnx2x_slowpath { 1252adfc5217SJeff Kirsher union { 1253adfc5217SJeff Kirsher struct mac_configuration_cmd e1x; 1254adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data e2; 1255adfc5217SJeff Kirsher } mac_rdata; 1256adfc5217SJeff Kirsher 1257adfc5217SJeff Kirsher union { 1258adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config e1x; 1259adfc5217SJeff Kirsher struct eth_filter_rules_ramrod_data e2; 1260adfc5217SJeff Kirsher } rx_mode_rdata; 1261adfc5217SJeff Kirsher 1262adfc5217SJeff Kirsher union { 1263adfc5217SJeff Kirsher struct mac_configuration_cmd e1; 1264adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data e2; 1265adfc5217SJeff Kirsher } mcast_rdata; 1266adfc5217SJeff Kirsher 1267adfc5217SJeff Kirsher struct eth_rss_update_ramrod_data rss_rdata; 1268adfc5217SJeff Kirsher 1269adfc5217SJeff Kirsher /* Queue State related ramrods are always sent under rtnl_lock */ 1270adfc5217SJeff Kirsher union { 1271adfc5217SJeff Kirsher struct client_init_ramrod_data init_data; 1272adfc5217SJeff Kirsher struct client_update_ramrod_data update_data; 127314a94ebdSMichal Kalderon struct tpa_update_ramrod_data tpa_data; 1274adfc5217SJeff Kirsher } q_rdata; 1275adfc5217SJeff Kirsher 1276adfc5217SJeff Kirsher union { 1277adfc5217SJeff Kirsher struct function_start_data func_start; 1278adfc5217SJeff Kirsher /* pfc configuration for DCBX ramrod */ 1279adfc5217SJeff Kirsher struct flow_control_configuration pfc_config; 1280adfc5217SJeff Kirsher } func_rdata; 1281adfc5217SJeff Kirsher 1282a3348722SBarak Witkowski /* afex ramrod can not be a part of func_rdata union because these 1283a3348722SBarak Witkowski * events might arrive in parallel to other events from func_rdata. 1284a3348722SBarak Witkowski * Therefore, if they would have been defined in the same union, 1285a3348722SBarak Witkowski * data can get corrupted. 1286a3348722SBarak Witkowski */ 12879dfef3adSYuval Mintz union { 12889dfef3adSYuval Mintz struct afex_vif_list_ramrod_data viflist_data; 12899dfef3adSYuval Mintz struct function_update_data func_update; 12909dfef3adSYuval Mintz } func_afex_rdata; 1291a3348722SBarak Witkowski 1292adfc5217SJeff Kirsher /* used by dmae command executer */ 1293adfc5217SJeff Kirsher struct dmae_command dmae[MAX_DMAE_C]; 1294adfc5217SJeff Kirsher 1295adfc5217SJeff Kirsher u32 stats_comp; 1296adfc5217SJeff Kirsher union mac_stats mac_stats; 1297adfc5217SJeff Kirsher struct nig_stats nig_stats; 1298adfc5217SJeff Kirsher struct host_port_stats port_stats; 1299adfc5217SJeff Kirsher struct host_func_stats func_stats; 1300adfc5217SJeff Kirsher 1301adfc5217SJeff Kirsher u32 wb_comp; 1302adfc5217SJeff Kirsher u32 wb_data[4]; 13031d187b34SBarak Witkowski 13041d187b34SBarak Witkowski union drv_info_to_mcp drv_info_to_mcp; 1305adfc5217SJeff Kirsher }; 1306adfc5217SJeff Kirsher 1307adfc5217SJeff Kirsher #define bnx2x_sp(bp, var) (&bp->slowpath->var) 1308adfc5217SJeff Kirsher #define bnx2x_sp_mapping(bp, var) \ 1309adfc5217SJeff Kirsher (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1310adfc5217SJeff Kirsher 1311adfc5217SJeff Kirsher /* attn group wiring */ 1312adfc5217SJeff Kirsher #define MAX_DYNAMIC_ATTN_GRPS 8 1313adfc5217SJeff Kirsher 1314adfc5217SJeff Kirsher struct attn_route { 1315adfc5217SJeff Kirsher u32 sig[5]; 1316adfc5217SJeff Kirsher }; 1317adfc5217SJeff Kirsher 1318adfc5217SJeff Kirsher struct iro { 1319adfc5217SJeff Kirsher u32 base; 1320adfc5217SJeff Kirsher u16 m1; 1321adfc5217SJeff Kirsher u16 m2; 1322adfc5217SJeff Kirsher u16 m3; 1323adfc5217SJeff Kirsher u16 size; 1324adfc5217SJeff Kirsher }; 1325adfc5217SJeff Kirsher 1326adfc5217SJeff Kirsher struct hw_context { 1327adfc5217SJeff Kirsher union cdu_context *vcxt; 1328adfc5217SJeff Kirsher dma_addr_t cxt_mapping; 1329adfc5217SJeff Kirsher size_t size; 1330adfc5217SJeff Kirsher }; 1331adfc5217SJeff Kirsher 1332adfc5217SJeff Kirsher /* forward */ 1333adfc5217SJeff Kirsher struct bnx2x_ilt; 1334adfc5217SJeff Kirsher 1335290ca2bbSAriel Elior struct bnx2x_vfdb; 1336adfc5217SJeff Kirsher 1337adfc5217SJeff Kirsher enum bnx2x_recovery_state { 1338adfc5217SJeff Kirsher BNX2X_RECOVERY_DONE, 1339adfc5217SJeff Kirsher BNX2X_RECOVERY_INIT, 1340adfc5217SJeff Kirsher BNX2X_RECOVERY_WAIT, 134195c6c616SAriel Elior BNX2X_RECOVERY_FAILED, 134295c6c616SAriel Elior BNX2X_RECOVERY_NIC_LOADING 1343adfc5217SJeff Kirsher }; 1344adfc5217SJeff Kirsher 1345adfc5217SJeff Kirsher /* 1346adfc5217SJeff Kirsher * Event queue (EQ or event ring) MC hsi 1347adfc5217SJeff Kirsher * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1348adfc5217SJeff Kirsher */ 1349adfc5217SJeff Kirsher #define NUM_EQ_PAGES 1 1350adfc5217SJeff Kirsher #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1351adfc5217SJeff Kirsher #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1352adfc5217SJeff Kirsher #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1353adfc5217SJeff Kirsher #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1354adfc5217SJeff Kirsher #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1355adfc5217SJeff Kirsher 1356adfc5217SJeff Kirsher /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1357adfc5217SJeff Kirsher #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1358adfc5217SJeff Kirsher (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1359adfc5217SJeff Kirsher 1360adfc5217SJeff Kirsher /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1361adfc5217SJeff Kirsher #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1362adfc5217SJeff Kirsher 1363adfc5217SJeff Kirsher #define BNX2X_EQ_INDEX \ 1364adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 1365adfc5217SJeff Kirsher index_values[HC_SP_INDEX_EQ_CONS]) 1366adfc5217SJeff Kirsher 1367adfc5217SJeff Kirsher /* This is a data that will be used to create a link report message. 1368adfc5217SJeff Kirsher * We will keep the data used for the last link report in order 1369adfc5217SJeff Kirsher * to prevent reporting the same link parameters twice. 1370adfc5217SJeff Kirsher */ 1371adfc5217SJeff Kirsher struct bnx2x_link_report_data { 1372adfc5217SJeff Kirsher u16 line_speed; /* Effective line speed */ 1373adfc5217SJeff Kirsher unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1374adfc5217SJeff Kirsher }; 1375adfc5217SJeff Kirsher 1376adfc5217SJeff Kirsher enum { 1377adfc5217SJeff Kirsher BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1378adfc5217SJeff Kirsher BNX2X_LINK_REPORT_LINK_DOWN, 1379adfc5217SJeff Kirsher BNX2X_LINK_REPORT_RX_FC_ON, 1380adfc5217SJeff Kirsher BNX2X_LINK_REPORT_TX_FC_ON, 1381adfc5217SJeff Kirsher }; 1382adfc5217SJeff Kirsher 1383adfc5217SJeff Kirsher enum { 1384adfc5217SJeff Kirsher BNX2X_PORT_QUERY_IDX, 1385adfc5217SJeff Kirsher BNX2X_PF_QUERY_IDX, 138650f0a562SBarak Witkowski BNX2X_FCOE_QUERY_IDX, 1387adfc5217SJeff Kirsher BNX2X_FIRST_QUEUE_QUERY_IDX, 1388adfc5217SJeff Kirsher }; 1389adfc5217SJeff Kirsher 1390adfc5217SJeff Kirsher struct bnx2x_fw_stats_req { 1391adfc5217SJeff Kirsher struct stats_query_header hdr; 139250f0a562SBarak Witkowski struct stats_query_entry query[FP_SB_MAX_E1x+ 139350f0a562SBarak Witkowski BNX2X_FIRST_QUEUE_QUERY_IDX]; 1394adfc5217SJeff Kirsher }; 1395adfc5217SJeff Kirsher 1396adfc5217SJeff Kirsher struct bnx2x_fw_stats_data { 1397adfc5217SJeff Kirsher struct stats_counter storm_counters; 1398adfc5217SJeff Kirsher struct per_port_stats port; 1399adfc5217SJeff Kirsher struct per_pf_stats pf; 140050f0a562SBarak Witkowski struct fcoe_statistics_params fcoe; 1401adfc5217SJeff Kirsher struct per_queue_stats queue_stats[1]; 1402adfc5217SJeff Kirsher }; 1403adfc5217SJeff Kirsher 1404adfc5217SJeff Kirsher /* Public slow path states */ 1405230bb0f3SYuval Mintz enum sp_rtnl_flag { 1406adfc5217SJeff Kirsher BNX2X_SP_RTNL_SETUP_TC, 1407adfc5217SJeff Kirsher BNX2X_SP_RTNL_TX_TIMEOUT, 14088304859aSAriel Elior BNX2X_SP_RTNL_FAN_FAILURE, 14098395be5eSAriel Elior BNX2X_SP_RTNL_AFEX_F_UPDATE, 14108395be5eSAriel Elior BNX2X_SP_RTNL_ENABLE_SRIOV, 1411381ac16bSAriel Elior BNX2X_SP_RTNL_VFPF_MCAST, 141278c3bcc5SAriel Elior BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 14138b09be5fSYuval Mintz BNX2X_SP_RTNL_RX_MODE, 14143ec9f9caSAriel Elior BNX2X_SP_RTNL_HYPERVISOR_VLAN, 141507b4eb3bSDmitry Kravkov BNX2X_SP_RTNL_TX_STOP, 141642f8277fSYuval Mintz BNX2X_SP_RTNL_GET_DRV_VERSION, 1417adfc5217SJeff Kirsher }; 1418adfc5217SJeff Kirsher 1419452427b0SYuval Mintz struct bnx2x_prev_path_list { 14207fa6f340SYuval Mintz struct list_head list; 1421452427b0SYuval Mintz u8 bus; 1422452427b0SYuval Mintz u8 slot; 1423452427b0SYuval Mintz u8 path; 14247fa6f340SYuval Mintz u8 aer; 1425c63da990SBarak Witkowski u8 undi; 1426452427b0SYuval Mintz }; 1427452427b0SYuval Mintz 142815192a8cSBarak Witkowski struct bnx2x_sp_objs { 142915192a8cSBarak Witkowski /* MACs object */ 143015192a8cSBarak Witkowski struct bnx2x_vlan_mac_obj mac_obj; 143115192a8cSBarak Witkowski 143215192a8cSBarak Witkowski /* Queue State object */ 143315192a8cSBarak Witkowski struct bnx2x_queue_sp_obj q_obj; 143415192a8cSBarak Witkowski }; 143515192a8cSBarak Witkowski 143615192a8cSBarak Witkowski struct bnx2x_fp_stats { 143715192a8cSBarak Witkowski struct tstorm_per_queue_stats old_tclient; 143815192a8cSBarak Witkowski struct ustorm_per_queue_stats old_uclient; 143915192a8cSBarak Witkowski struct xstorm_per_queue_stats old_xclient; 144015192a8cSBarak Witkowski struct bnx2x_eth_q_stats eth_q_stats; 144115192a8cSBarak Witkowski struct bnx2x_eth_q_stats_old eth_q_stats_old; 144215192a8cSBarak Witkowski }; 144315192a8cSBarak Witkowski 1444adfc5217SJeff Kirsher struct bnx2x { 1445adfc5217SJeff Kirsher /* Fields used in the tx and intr/napi performance paths 1446adfc5217SJeff Kirsher * are grouped together in the beginning of the structure 1447adfc5217SJeff Kirsher */ 1448adfc5217SJeff Kirsher struct bnx2x_fastpath *fp; 144915192a8cSBarak Witkowski struct bnx2x_sp_objs *sp_objs; 145015192a8cSBarak Witkowski struct bnx2x_fp_stats *fp_stats; 145165565884SMerav Sicron struct bnx2x_fp_txdata *bnx2x_txq; 1452adfc5217SJeff Kirsher void __iomem *regview; 1453adfc5217SJeff Kirsher void __iomem *doorbells; 1454adfc5217SJeff Kirsher u16 db_size; 1455adfc5217SJeff Kirsher 1456adfc5217SJeff Kirsher u8 pf_num; /* absolute PF number */ 1457adfc5217SJeff Kirsher u8 pfid; /* per-path PF number */ 1458adfc5217SJeff Kirsher int base_fw_ndsb; /**/ 1459adfc5217SJeff Kirsher #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1460adfc5217SJeff Kirsher #define BP_PORT(bp) (bp->pfid & 1) 1461adfc5217SJeff Kirsher #define BP_FUNC(bp) (bp->pfid) 1462adfc5217SJeff Kirsher #define BP_ABS_FUNC(bp) (bp->pf_num) 14638decf868SDavid S. Miller #define BP_VN(bp) ((bp)->pfid >> 1) 14648decf868SDavid S. Miller #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 14658decf868SDavid S. Miller #define BP_L_ID(bp) (BP_VN(bp) << 2) 14668decf868SDavid S. Miller #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 14678decf868SDavid S. Miller (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 14688decf868SDavid S. Miller #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1469adfc5217SJeff Kirsher 14706411280aSAriel Elior #ifdef CONFIG_BNX2X_SRIOV 14711d6f3cd8SDmitry Kravkov /* protects vf2pf mailbox from simultaneous access */ 14721d6f3cd8SDmitry Kravkov struct mutex vf2pf_mutex; 14731ab4434cSAriel Elior /* vf pf channel mailbox contains request and response buffers */ 14741ab4434cSAriel Elior struct bnx2x_vf_mbx_msg *vf2pf_mbox; 14751ab4434cSAriel Elior dma_addr_t vf2pf_mbox_mapping; 14761ab4434cSAriel Elior 1477be1f1ffaSAriel Elior /* we set aside a copy of the acquire response */ 1478be1f1ffaSAriel Elior struct pfvf_acquire_resp_tlv acquire_resp; 1479be1f1ffaSAriel Elior 1480abc5a021SAriel Elior /* bulletin board for messages from pf to vf */ 1481abc5a021SAriel Elior union pf_vf_bulletin *pf2vf_bulletin; 1482abc5a021SAriel Elior dma_addr_t pf2vf_bulletin_mapping; 1483abc5a021SAriel Elior 1484abc5a021SAriel Elior struct pf_vf_bulletin_content old_bulletin; 14853c76feffSAriel Elior 14863c76feffSAriel Elior u16 requested_nr_virtfn; 14876411280aSAriel Elior #endif /* CONFIG_BNX2X_SRIOV */ 1488abc5a021SAriel Elior 1489adfc5217SJeff Kirsher struct net_device *dev; 1490adfc5217SJeff Kirsher struct pci_dev *pdev; 1491adfc5217SJeff Kirsher 1492adfc5217SJeff Kirsher const struct iro *iro_arr; 1493adfc5217SJeff Kirsher #define IRO (bp->iro_arr) 1494adfc5217SJeff Kirsher 1495adfc5217SJeff Kirsher enum bnx2x_recovery_state recovery_state; 1496adfc5217SJeff Kirsher int is_leader; 1497adfc5217SJeff Kirsher struct msix_entry *msix_table; 1498adfc5217SJeff Kirsher 1499adfc5217SJeff Kirsher int tx_ring_size; 1500adfc5217SJeff Kirsher 1501adfc5217SJeff Kirsher /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1502adfc5217SJeff Kirsher #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1503adfc5217SJeff Kirsher #define ETH_MIN_PACKET_SIZE 60 1504adfc5217SJeff Kirsher #define ETH_MAX_PACKET_SIZE 1500 1505adfc5217SJeff Kirsher #define ETH_MAX_JUMBO_PACKET_SIZE 9600 1506621b4d66SDmitry Kravkov /* TCP with Timestamp Option (32) + IPv6 (40) */ 1507621b4d66SDmitry Kravkov #define ETH_MAX_TPA_HEADER_SIZE 72 1508adfc5217SJeff Kirsher 1509adfc5217SJeff Kirsher /* Max supported alignment is 256 (8 shift) */ 1510e52fcb24SEric Dumazet #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1511e52fcb24SEric Dumazet 1512e52fcb24SEric Dumazet /* FW uses 2 Cache lines Alignment for start packet and size 1513e52fcb24SEric Dumazet * 1514e52fcb24SEric Dumazet * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1515e52fcb24SEric Dumazet * at the end of skb->data, to avoid wasting a full cache line. 1516e52fcb24SEric Dumazet * This reduces memory use (skb->truesize). 1517e52fcb24SEric Dumazet */ 1518e52fcb24SEric Dumazet #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1519e52fcb24SEric Dumazet 1520e52fcb24SEric Dumazet #define BNX2X_FW_RX_ALIGN_END \ 1521f57b07c0SJoren Van Onder max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1522e52fcb24SEric Dumazet SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1523e52fcb24SEric Dumazet 1524adfc5217SJeff Kirsher #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1525adfc5217SJeff Kirsher 1526adfc5217SJeff Kirsher struct host_sp_status_block *def_status_blk; 1527adfc5217SJeff Kirsher #define DEF_SB_IGU_ID 16 1528adfc5217SJeff Kirsher #define DEF_SB_ID HC_SP_SB_ID 1529adfc5217SJeff Kirsher __le16 def_idx; 1530adfc5217SJeff Kirsher __le16 def_att_idx; 1531adfc5217SJeff Kirsher u32 attn_state; 1532adfc5217SJeff Kirsher struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1533adfc5217SJeff Kirsher 1534adfc5217SJeff Kirsher /* slow path ring */ 1535adfc5217SJeff Kirsher struct eth_spe *spq; 1536adfc5217SJeff Kirsher dma_addr_t spq_mapping; 1537adfc5217SJeff Kirsher u16 spq_prod_idx; 1538adfc5217SJeff Kirsher struct eth_spe *spq_prod_bd; 1539adfc5217SJeff Kirsher struct eth_spe *spq_last_bd; 1540adfc5217SJeff Kirsher __le16 *dsb_sp_prod; 1541adfc5217SJeff Kirsher atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1542adfc5217SJeff Kirsher /* used to synchronize spq accesses */ 1543adfc5217SJeff Kirsher spinlock_t spq_lock; 1544adfc5217SJeff Kirsher 1545adfc5217SJeff Kirsher /* event queue */ 1546adfc5217SJeff Kirsher union event_ring_elem *eq_ring; 1547adfc5217SJeff Kirsher dma_addr_t eq_mapping; 1548adfc5217SJeff Kirsher u16 eq_prod; 1549adfc5217SJeff Kirsher u16 eq_cons; 1550adfc5217SJeff Kirsher __le16 *eq_cons_sb; 1551adfc5217SJeff Kirsher atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1552adfc5217SJeff Kirsher 1553adfc5217SJeff Kirsher /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1554adfc5217SJeff Kirsher u16 stats_pending; 1555adfc5217SJeff Kirsher /* Counter for completed statistics ramrods */ 1556adfc5217SJeff Kirsher u16 stats_comp; 1557adfc5217SJeff Kirsher 1558adfc5217SJeff Kirsher /* End of fields used in the performance code paths */ 1559adfc5217SJeff Kirsher 1560adfc5217SJeff Kirsher int panic; 1561adfc5217SJeff Kirsher int msg_enable; 1562adfc5217SJeff Kirsher 1563adfc5217SJeff Kirsher u32 flags; 1564adfc5217SJeff Kirsher #define PCIX_FLAG (1 << 0) 1565adfc5217SJeff Kirsher #define PCI_32BIT_FLAG (1 << 1) 1566adfc5217SJeff Kirsher #define ONE_PORT_FLAG (1 << 2) 1567adfc5217SJeff Kirsher #define NO_WOL_FLAG (1 << 3) 1568adfc5217SJeff Kirsher #define USING_MSIX_FLAG (1 << 5) 1569adfc5217SJeff Kirsher #define USING_MSI_FLAG (1 << 6) 1570adfc5217SJeff Kirsher #define DISABLE_MSI_FLAG (1 << 7) 1571adfc5217SJeff Kirsher #define TPA_ENABLE_FLAG (1 << 8) 1572adfc5217SJeff Kirsher #define NO_MCP_FLAG (1 << 9) 1573621b4d66SDmitry Kravkov #define GRO_ENABLE_FLAG (1 << 10) 1574adfc5217SJeff Kirsher #define MF_FUNC_DIS (1 << 11) 1575adfc5217SJeff Kirsher #define OWN_CNIC_IRQ (1 << 12) 1576adfc5217SJeff Kirsher #define NO_ISCSI_OOO_FLAG (1 << 13) 1577adfc5217SJeff Kirsher #define NO_ISCSI_FLAG (1 << 14) 1578adfc5217SJeff Kirsher #define NO_FCOE_FLAG (1 << 15) 15790e898dd7SBarak Witkowski #define BC_SUPPORTS_PFC_STATS (1 << 17) 1580c14db202SYuval Mintz #define TX_SWITCHING (1 << 18) 15812e499d3cSBarak Witkowski #define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 158230a5de77SDmitry Kravkov #define USING_SINGLE_MSIX_FLAG (1 << 20) 15839876879fSBarak Witkowski #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 15841ab4434cSAriel Elior #define IS_VF_FLAG (1 << 22) 158578c3bcc5SAriel Elior #define INTERRUPTS_ENABLED_FLAG (1 << 23) 1586a6d3a5baSBarak Witkowsky #define BC_SUPPORTS_RMMOD_CMD (1 << 24) 15873d7d562cSYuval Mintz #define HAS_PHYS_PORT_ID (1 << 25) 158833d8e6a5SYuval Mintz #define AER_ENABLED (1 << 26) 15891ab4434cSAriel Elior 15901ab4434cSAriel Elior #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 15916411280aSAriel Elior 15926411280aSAriel Elior #ifdef CONFIG_BNX2X_SRIOV 15931ab4434cSAriel Elior #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 15941ab4434cSAriel Elior #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 15956411280aSAriel Elior #else 15966411280aSAriel Elior #define IS_VF(bp) false 15976411280aSAriel Elior #define IS_PF(bp) true 15986411280aSAriel Elior #endif 1599adfc5217SJeff Kirsher 1600adfc5217SJeff Kirsher #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1601adfc5217SJeff Kirsher #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1602adfc5217SJeff Kirsher #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1603adfc5217SJeff Kirsher 160455c11941SMerav Sicron u8 cnic_support; 160555c11941SMerav Sicron bool cnic_enabled; 160655c11941SMerav Sicron bool cnic_loaded; 16074bd9b0ffSMichael Chan struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 160855c11941SMerav Sicron 160955c11941SMerav Sicron /* Flag that indicates that we can start looking for FCoE L2 queue 161055c11941SMerav Sicron * completions in the default status block. 161155c11941SMerav Sicron */ 161255c11941SMerav Sicron bool fcoe_init; 161355c11941SMerav Sicron 1614adfc5217SJeff Kirsher int mrrs; 1615adfc5217SJeff Kirsher 1616adfc5217SJeff Kirsher struct delayed_work sp_task; 1617fd1fc79dSAriel Elior atomic_t interrupt_occurred; 1618adfc5217SJeff Kirsher struct delayed_work sp_rtnl_task; 1619adfc5217SJeff Kirsher 1620adfc5217SJeff Kirsher struct delayed_work period_task; 1621adfc5217SJeff Kirsher struct timer_list timer; 1622adfc5217SJeff Kirsher int current_interval; 1623adfc5217SJeff Kirsher 1624adfc5217SJeff Kirsher u16 fw_seq; 1625adfc5217SJeff Kirsher u16 fw_drv_pulse_wr_seq; 1626adfc5217SJeff Kirsher u32 func_stx; 1627adfc5217SJeff Kirsher 1628adfc5217SJeff Kirsher struct link_params link_params; 1629adfc5217SJeff Kirsher struct link_vars link_vars; 1630adfc5217SJeff Kirsher u32 link_cnt; 1631adfc5217SJeff Kirsher struct bnx2x_link_report_data last_reported_link; 1632adfc5217SJeff Kirsher 1633adfc5217SJeff Kirsher struct mdio_if_info mdio; 1634adfc5217SJeff Kirsher 1635adfc5217SJeff Kirsher struct bnx2x_common common; 1636adfc5217SJeff Kirsher struct bnx2x_port port; 1637adfc5217SJeff Kirsher 1638b475d78fSYuval Mintz struct cmng_init cmng; 1639b475d78fSYuval Mintz 1640adfc5217SJeff Kirsher u32 mf_config[E1HVN_MAX]; 1641a3348722SBarak Witkowski u32 mf_ext_config; 1642adfc5217SJeff Kirsher u32 path_has_ovlan; /* E3 */ 1643adfc5217SJeff Kirsher u16 mf_ov; 1644adfc5217SJeff Kirsher u8 mf_mode; 1645adfc5217SJeff Kirsher #define IS_MF(bp) (bp->mf_mode != 0) 1646adfc5217SJeff Kirsher #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1647adfc5217SJeff Kirsher #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1648a3348722SBarak Witkowski #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1649adfc5217SJeff Kirsher 1650adfc5217SJeff Kirsher u8 wol; 1651adfc5217SJeff Kirsher 1652adfc5217SJeff Kirsher int rx_ring_size; 1653adfc5217SJeff Kirsher 1654adfc5217SJeff Kirsher u16 tx_quick_cons_trip_int; 1655adfc5217SJeff Kirsher u16 tx_quick_cons_trip; 1656adfc5217SJeff Kirsher u16 tx_ticks_int; 1657adfc5217SJeff Kirsher u16 tx_ticks; 1658adfc5217SJeff Kirsher 1659adfc5217SJeff Kirsher u16 rx_quick_cons_trip_int; 1660adfc5217SJeff Kirsher u16 rx_quick_cons_trip; 1661adfc5217SJeff Kirsher u16 rx_ticks_int; 1662adfc5217SJeff Kirsher u16 rx_ticks; 1663adfc5217SJeff Kirsher /* Maximal coalescing timeout in us */ 16646802516eSDmitry Kravkov #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR) 1665adfc5217SJeff Kirsher 1666adfc5217SJeff Kirsher u32 lin_cnt; 1667adfc5217SJeff Kirsher 1668adfc5217SJeff Kirsher u16 state; 1669adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSED 0 1670adfc5217SJeff Kirsher #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1671adfc5217SJeff Kirsher #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1672adfc5217SJeff Kirsher #define BNX2X_STATE_OPEN 0x3000 1673adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1674adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1675adfc5217SJeff Kirsher 1676adfc5217SJeff Kirsher #define BNX2X_STATE_DIAG 0xe000 1677adfc5217SJeff Kirsher #define BNX2X_STATE_ERROR 0xf000 1678adfc5217SJeff Kirsher 1679adfc5217SJeff Kirsher #define BNX2X_MAX_PRIORITY 8 1680adfc5217SJeff Kirsher #define BNX2X_MAX_ENTRIES_PER_PRI 16 1681adfc5217SJeff Kirsher #define BNX2X_MAX_COS 3 1682adfc5217SJeff Kirsher #define BNX2X_MAX_TX_COS 2 1683adfc5217SJeff Kirsher int num_queues; 168455c11941SMerav Sicron uint num_ethernet_queues; 168555c11941SMerav Sicron uint num_cnic_queues; 16860e8d2ec5SMerav Sicron int num_napi_queues; 1687adfc5217SJeff Kirsher int disable_tpa; 1688adfc5217SJeff Kirsher 1689adfc5217SJeff Kirsher u32 rx_mode; 1690adfc5217SJeff Kirsher #define BNX2X_RX_MODE_NONE 0 1691adfc5217SJeff Kirsher #define BNX2X_RX_MODE_NORMAL 1 1692adfc5217SJeff Kirsher #define BNX2X_RX_MODE_ALLMULTI 2 1693adfc5217SJeff Kirsher #define BNX2X_RX_MODE_PROMISC 3 1694adfc5217SJeff Kirsher #define BNX2X_MAX_MULTICAST 64 1695adfc5217SJeff Kirsher 1696adfc5217SJeff Kirsher u8 igu_dsb_id; 1697adfc5217SJeff Kirsher u8 igu_base_sb; 1698adfc5217SJeff Kirsher u8 igu_sb_cnt; 169955c11941SMerav Sicron u8 min_msix_vec_cnt; 170065565884SMerav Sicron 17011ab4434cSAriel Elior u32 igu_base_addr; 1702adfc5217SJeff Kirsher dma_addr_t def_status_blk_mapping; 1703adfc5217SJeff Kirsher 1704adfc5217SJeff Kirsher struct bnx2x_slowpath *slowpath; 1705adfc5217SJeff Kirsher dma_addr_t slowpath_mapping; 1706adfc5217SJeff Kirsher 170742f8277fSYuval Mintz /* Mechanism protecting the drv_info_to_mcp */ 170842f8277fSYuval Mintz struct mutex drv_info_mutex; 170942f8277fSYuval Mintz bool drv_info_mng_owner; 171042f8277fSYuval Mintz 1711adfc5217SJeff Kirsher /* Total number of FW statistics requests */ 1712adfc5217SJeff Kirsher u8 fw_stats_num; 1713adfc5217SJeff Kirsher 1714adfc5217SJeff Kirsher /* 1715adfc5217SJeff Kirsher * This is a memory buffer that will contain both statistics 1716adfc5217SJeff Kirsher * ramrod request and data. 1717adfc5217SJeff Kirsher */ 1718adfc5217SJeff Kirsher void *fw_stats; 1719adfc5217SJeff Kirsher dma_addr_t fw_stats_mapping; 1720adfc5217SJeff Kirsher 1721adfc5217SJeff Kirsher /* 1722adfc5217SJeff Kirsher * FW statistics request shortcut (points at the 1723adfc5217SJeff Kirsher * beginning of fw_stats buffer). 1724adfc5217SJeff Kirsher */ 1725adfc5217SJeff Kirsher struct bnx2x_fw_stats_req *fw_stats_req; 1726adfc5217SJeff Kirsher dma_addr_t fw_stats_req_mapping; 1727adfc5217SJeff Kirsher int fw_stats_req_sz; 1728adfc5217SJeff Kirsher 1729adfc5217SJeff Kirsher /* 17304907cb7bSAnatol Pomozov * FW statistics data shortcut (points at the beginning of 1731adfc5217SJeff Kirsher * fw_stats buffer + fw_stats_req_sz). 1732adfc5217SJeff Kirsher */ 1733adfc5217SJeff Kirsher struct bnx2x_fw_stats_data *fw_stats_data; 1734adfc5217SJeff Kirsher dma_addr_t fw_stats_data_mapping; 1735adfc5217SJeff Kirsher int fw_stats_data_sz; 1736adfc5217SJeff Kirsher 1737b9871bcfSAriel Elior /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB 1738a052997eSMerav Sicron * context size we need 8 ILT entries. 1739a052997eSMerav Sicron */ 1740b9871bcfSAriel Elior #define ILT_MAX_L2_LINES 32 1741a052997eSMerav Sicron struct hw_context context[ILT_MAX_L2_LINES]; 1742adfc5217SJeff Kirsher 1743adfc5217SJeff Kirsher struct bnx2x_ilt *ilt; 1744adfc5217SJeff Kirsher #define BP_ILT(bp) ((bp)->ilt) 1745adfc5217SJeff Kirsher #define ILT_MAX_LINES 256 1746adfc5217SJeff Kirsher /* 1747adfc5217SJeff Kirsher * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1748adfc5217SJeff Kirsher * to CNIC. 1749adfc5217SJeff Kirsher */ 175055c11941SMerav Sicron #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1751adfc5217SJeff Kirsher 1752adfc5217SJeff Kirsher /* 1753adfc5217SJeff Kirsher * Maximum CID count that might be required by the bnx2x: 175437ae41a9SMerav Sicron * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1755adfc5217SJeff Kirsher */ 1756f78afb35SMichael Chan 175737ae41a9SMerav Sicron #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1758f78afb35SMichael Chan + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 175937ae41a9SMerav Sicron #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1760f78afb35SMichael Chan + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1761adfc5217SJeff Kirsher #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1762adfc5217SJeff Kirsher ILT_PAGE_CIDS)) 1763adfc5217SJeff Kirsher 1764adfc5217SJeff Kirsher int qm_cid_count; 1765adfc5217SJeff Kirsher 17667964211dSYuval Mintz bool dropless_fc; 1767adfc5217SJeff Kirsher 1768adfc5217SJeff Kirsher void *t2; 1769adfc5217SJeff Kirsher dma_addr_t t2_mapping; 1770adfc5217SJeff Kirsher struct cnic_ops __rcu *cnic_ops; 1771adfc5217SJeff Kirsher void *cnic_data; 1772adfc5217SJeff Kirsher u32 cnic_tag; 1773adfc5217SJeff Kirsher struct cnic_eth_dev cnic_eth_dev; 1774adfc5217SJeff Kirsher union host_hc_status_block cnic_sb; 1775adfc5217SJeff Kirsher dma_addr_t cnic_sb_mapping; 1776adfc5217SJeff Kirsher struct eth_spe *cnic_kwq; 1777adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_prod; 1778adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_cons; 1779adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_last; 1780adfc5217SJeff Kirsher u16 cnic_kwq_pending; 1781adfc5217SJeff Kirsher u16 cnic_spq_pending; 1782adfc5217SJeff Kirsher u8 fip_mac[ETH_ALEN]; 1783adfc5217SJeff Kirsher struct mutex cnic_mutex; 1784adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1785adfc5217SJeff Kirsher 178616a5fd92SYuval Mintz /* Start index of the "special" (CNIC related) L2 clients */ 1787adfc5217SJeff Kirsher u8 cnic_base_cl_id; 1788adfc5217SJeff Kirsher 1789adfc5217SJeff Kirsher int dmae_ready; 1790adfc5217SJeff Kirsher /* used to synchronize dmae accesses */ 1791adfc5217SJeff Kirsher spinlock_t dmae_lock; 1792adfc5217SJeff Kirsher 1793adfc5217SJeff Kirsher /* used to protect the FW mail box */ 1794adfc5217SJeff Kirsher struct mutex fw_mb_mutex; 1795adfc5217SJeff Kirsher 1796adfc5217SJeff Kirsher /* used to synchronize stats collecting */ 1797adfc5217SJeff Kirsher int stats_state; 1798adfc5217SJeff Kirsher 1799adfc5217SJeff Kirsher /* used for synchronization of concurrent threads statistics handling */ 1800adfc5217SJeff Kirsher spinlock_t stats_lock; 1801adfc5217SJeff Kirsher 1802adfc5217SJeff Kirsher /* used by dmae command loader */ 1803adfc5217SJeff Kirsher struct dmae_command stats_dmae; 1804adfc5217SJeff Kirsher int executer_idx; 1805adfc5217SJeff Kirsher 1806adfc5217SJeff Kirsher u16 stats_counter; 1807adfc5217SJeff Kirsher struct bnx2x_eth_stats eth_stats; 1808cb4dca27SYuval Mintz struct host_func_stats func_stats; 18091355b704SMintz Yuval struct bnx2x_eth_stats_old eth_stats_old; 18101355b704SMintz Yuval struct bnx2x_net_stats_old net_stats_old; 18111355b704SMintz Yuval struct bnx2x_fw_port_stats_old fw_stats_old; 18121355b704SMintz Yuval bool stats_init; 1813adfc5217SJeff Kirsher 1814adfc5217SJeff Kirsher struct z_stream_s *strm; 1815adfc5217SJeff Kirsher void *gunzip_buf; 1816adfc5217SJeff Kirsher dma_addr_t gunzip_mapping; 1817adfc5217SJeff Kirsher int gunzip_outlen; 1818adfc5217SJeff Kirsher #define FW_BUF_SIZE 0x8000 1819adfc5217SJeff Kirsher #define GUNZIP_BUF(bp) (bp->gunzip_buf) 1820adfc5217SJeff Kirsher #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1821adfc5217SJeff Kirsher #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1822adfc5217SJeff Kirsher 1823adfc5217SJeff Kirsher struct raw_op *init_ops; 1824adfc5217SJeff Kirsher /* Init blocks offsets inside init_ops */ 1825adfc5217SJeff Kirsher u16 *init_ops_offsets; 1826adfc5217SJeff Kirsher /* Data blob - has 32 bit granularity */ 1827adfc5217SJeff Kirsher u32 *init_data; 1828adfc5217SJeff Kirsher u32 init_mode_flags; 1829adfc5217SJeff Kirsher #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1830adfc5217SJeff Kirsher /* Zipped PRAM blobs - raw data */ 1831adfc5217SJeff Kirsher const u8 *tsem_int_table_data; 1832adfc5217SJeff Kirsher const u8 *tsem_pram_data; 1833adfc5217SJeff Kirsher const u8 *usem_int_table_data; 1834adfc5217SJeff Kirsher const u8 *usem_pram_data; 1835adfc5217SJeff Kirsher const u8 *xsem_int_table_data; 1836adfc5217SJeff Kirsher const u8 *xsem_pram_data; 1837adfc5217SJeff Kirsher const u8 *csem_int_table_data; 1838adfc5217SJeff Kirsher const u8 *csem_pram_data; 1839adfc5217SJeff Kirsher #define INIT_OPS(bp) (bp->init_ops) 1840adfc5217SJeff Kirsher #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1841adfc5217SJeff Kirsher #define INIT_DATA(bp) (bp->init_data) 1842adfc5217SJeff Kirsher #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1843adfc5217SJeff Kirsher #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1844adfc5217SJeff Kirsher #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1845adfc5217SJeff Kirsher #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1846adfc5217SJeff Kirsher #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1847adfc5217SJeff Kirsher #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1848adfc5217SJeff Kirsher #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1849adfc5217SJeff Kirsher #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1850adfc5217SJeff Kirsher 1851adfc5217SJeff Kirsher #define PHY_FW_VER_LEN 20 1852adfc5217SJeff Kirsher char fw_ver[32]; 1853adfc5217SJeff Kirsher const struct firmware *firmware; 1854adfc5217SJeff Kirsher 1855290ca2bbSAriel Elior struct bnx2x_vfdb *vfdb; 1856290ca2bbSAriel Elior #define IS_SRIOV(bp) ((bp)->vfdb) 1857290ca2bbSAriel Elior 1858adfc5217SJeff Kirsher /* DCB support on/off */ 1859adfc5217SJeff Kirsher u16 dcb_state; 1860adfc5217SJeff Kirsher #define BNX2X_DCB_STATE_OFF 0 1861adfc5217SJeff Kirsher #define BNX2X_DCB_STATE_ON 1 1862adfc5217SJeff Kirsher 1863adfc5217SJeff Kirsher /* DCBX engine mode */ 1864adfc5217SJeff Kirsher int dcbx_enabled; 1865adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_OFF 0 1866adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1867adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1868adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_INVALID (-1) 1869adfc5217SJeff Kirsher 1870adfc5217SJeff Kirsher bool dcbx_mode_uset; 1871adfc5217SJeff Kirsher 1872adfc5217SJeff Kirsher struct bnx2x_config_dcbx_params dcbx_config_params; 1873adfc5217SJeff Kirsher struct bnx2x_dcbx_port_params dcbx_port_params; 1874adfc5217SJeff Kirsher int dcb_version; 1875adfc5217SJeff Kirsher 1876adfc5217SJeff Kirsher /* CAM credit pools */ 1877b56e9670SAriel Elior 1878b56e9670SAriel Elior /* used only in sriov */ 1879b56e9670SAriel Elior struct bnx2x_credit_pool_obj vlans_pool; 1880b56e9670SAriel Elior 1881adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj macs_pool; 1882adfc5217SJeff Kirsher 1883adfc5217SJeff Kirsher /* RX_MODE object */ 1884adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj rx_mode_obj; 1885adfc5217SJeff Kirsher 1886adfc5217SJeff Kirsher /* MCAST object */ 1887adfc5217SJeff Kirsher struct bnx2x_mcast_obj mcast_obj; 1888adfc5217SJeff Kirsher 1889adfc5217SJeff Kirsher /* RSS configuration object */ 1890adfc5217SJeff Kirsher struct bnx2x_rss_config_obj rss_conf_obj; 1891adfc5217SJeff Kirsher 1892adfc5217SJeff Kirsher /* Function State controlling object */ 1893adfc5217SJeff Kirsher struct bnx2x_func_sp_obj func_obj; 1894adfc5217SJeff Kirsher 1895adfc5217SJeff Kirsher unsigned long sp_state; 1896adfc5217SJeff Kirsher 1897adfc5217SJeff Kirsher /* operation indication for the sp_rtnl task */ 1898adfc5217SJeff Kirsher unsigned long sp_rtnl_state; 1899adfc5217SJeff Kirsher 190016a5fd92SYuval Mintz /* DCBX Negotiation results */ 1901adfc5217SJeff Kirsher struct dcbx_features dcbx_local_feat; 1902adfc5217SJeff Kirsher u32 dcbx_error; 1903adfc5217SJeff Kirsher 1904adfc5217SJeff Kirsher #ifdef BCM_DCBNL 1905adfc5217SJeff Kirsher struct dcbx_features dcbx_remote_feat; 1906adfc5217SJeff Kirsher u32 dcbx_remote_flags; 1907adfc5217SJeff Kirsher #endif 1908a3348722SBarak Witkowski /* AFEX: store default vlan used */ 1909a3348722SBarak Witkowski int afex_def_vlan_tag; 1910a3348722SBarak Witkowski enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1911adfc5217SJeff Kirsher u32 pending_max; 1912adfc5217SJeff Kirsher 1913adfc5217SJeff Kirsher /* multiple tx classes of service */ 1914adfc5217SJeff Kirsher u8 max_cos; 1915adfc5217SJeff Kirsher 1916adfc5217SJeff Kirsher /* priority to cos mapping */ 1917adfc5217SJeff Kirsher u8 prio_to_cos[8]; 1918c3146eb6SDmitry Kravkov 1919c3146eb6SDmitry Kravkov int fp_array_size; 192007ba6af4SMiriam Shitrit u32 dump_preset_idx; 1921507393ebSDmitry Kravkov bool stats_started; 1922507393ebSDmitry Kravkov struct semaphore stats_sema; 19233d7d562cSYuval Mintz 19243d7d562cSYuval Mintz u8 phys_port_id[ETH_ALEN]; 1925adfc5217SJeff Kirsher }; 1926adfc5217SJeff Kirsher 1927adfc5217SJeff Kirsher /* Tx queues may be less or equal to Rx queues */ 1928adfc5217SJeff Kirsher extern int num_queues; 1929adfc5217SJeff Kirsher #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 193055c11941SMerav Sicron #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 193165565884SMerav Sicron #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 193255c11941SMerav Sicron (bp)->num_cnic_queues) 1933adfc5217SJeff Kirsher #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1934adfc5217SJeff Kirsher 1935adfc5217SJeff Kirsher #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1936adfc5217SJeff Kirsher 1937adfc5217SJeff Kirsher #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1938adfc5217SJeff Kirsher /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1939adfc5217SJeff Kirsher 1940adfc5217SJeff Kirsher #define RSS_IPV4_CAP_MASK \ 1941adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1942adfc5217SJeff Kirsher 1943adfc5217SJeff Kirsher #define RSS_IPV4_TCP_CAP_MASK \ 1944adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1945adfc5217SJeff Kirsher 1946adfc5217SJeff Kirsher #define RSS_IPV6_CAP_MASK \ 1947adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1948adfc5217SJeff Kirsher 1949adfc5217SJeff Kirsher #define RSS_IPV6_TCP_CAP_MASK \ 1950adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1951adfc5217SJeff Kirsher 1952adfc5217SJeff Kirsher /* func init flags */ 1953adfc5217SJeff Kirsher #define FUNC_FLG_RSS 0x0001 1954adfc5217SJeff Kirsher #define FUNC_FLG_STATS 0x0002 1955adfc5217SJeff Kirsher /* removed FUNC_FLG_UNMATCHED 0x0004 */ 1956adfc5217SJeff Kirsher #define FUNC_FLG_TPA 0x0008 1957adfc5217SJeff Kirsher #define FUNC_FLG_SPQ 0x0010 1958adfc5217SJeff Kirsher #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1959b9871bcfSAriel Elior #define FUNC_FLG_LEADING_STATS 0x0040 1960adfc5217SJeff Kirsher struct bnx2x_func_init_params { 1961adfc5217SJeff Kirsher /* dma */ 1962adfc5217SJeff Kirsher dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1963adfc5217SJeff Kirsher dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1964adfc5217SJeff Kirsher 1965adfc5217SJeff Kirsher u16 func_flgs; 1966adfc5217SJeff Kirsher u16 func_id; /* abs fid */ 1967adfc5217SJeff Kirsher u16 pf_id; 1968adfc5217SJeff Kirsher u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1969adfc5217SJeff Kirsher }; 1970adfc5217SJeff Kirsher 197155c11941SMerav Sicron #define for_each_cnic_queue(bp, var) \ 197255c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 197355c11941SMerav Sicron (var)++) \ 197455c11941SMerav Sicron if (skip_queue(bp, var)) \ 197555c11941SMerav Sicron continue; \ 197655c11941SMerav Sicron else 197755c11941SMerav Sicron 1978adfc5217SJeff Kirsher #define for_each_eth_queue(bp, var) \ 1979adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1980adfc5217SJeff Kirsher 1981adfc5217SJeff Kirsher #define for_each_nondefault_eth_queue(bp, var) \ 1982adfc5217SJeff Kirsher for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1983adfc5217SJeff Kirsher 1984adfc5217SJeff Kirsher #define for_each_queue(bp, var) \ 1985adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1986adfc5217SJeff Kirsher if (skip_queue(bp, var)) \ 1987adfc5217SJeff Kirsher continue; \ 1988adfc5217SJeff Kirsher else 1989adfc5217SJeff Kirsher 1990adfc5217SJeff Kirsher /* Skip forwarding FP */ 199155c11941SMerav Sicron #define for_each_valid_rx_queue(bp, var) \ 199255c11941SMerav Sicron for ((var) = 0; \ 199355c11941SMerav Sicron (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 199455c11941SMerav Sicron BNX2X_NUM_ETH_QUEUES(bp)); \ 199555c11941SMerav Sicron (var)++) \ 199655c11941SMerav Sicron if (skip_rx_queue(bp, var)) \ 199755c11941SMerav Sicron continue; \ 199855c11941SMerav Sicron else 199955c11941SMerav Sicron 200055c11941SMerav Sicron #define for_each_rx_queue_cnic(bp, var) \ 200155c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 200255c11941SMerav Sicron (var)++) \ 200355c11941SMerav Sicron if (skip_rx_queue(bp, var)) \ 200455c11941SMerav Sicron continue; \ 200555c11941SMerav Sicron else 200655c11941SMerav Sicron 2007adfc5217SJeff Kirsher #define for_each_rx_queue(bp, var) \ 2008adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2009adfc5217SJeff Kirsher if (skip_rx_queue(bp, var)) \ 2010adfc5217SJeff Kirsher continue; \ 2011adfc5217SJeff Kirsher else 2012adfc5217SJeff Kirsher 2013adfc5217SJeff Kirsher /* Skip OOO FP */ 201455c11941SMerav Sicron #define for_each_valid_tx_queue(bp, var) \ 201555c11941SMerav Sicron for ((var) = 0; \ 201655c11941SMerav Sicron (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 201755c11941SMerav Sicron BNX2X_NUM_ETH_QUEUES(bp)); \ 201855c11941SMerav Sicron (var)++) \ 201955c11941SMerav Sicron if (skip_tx_queue(bp, var)) \ 202055c11941SMerav Sicron continue; \ 202155c11941SMerav Sicron else 202255c11941SMerav Sicron 202355c11941SMerav Sicron #define for_each_tx_queue_cnic(bp, var) \ 202455c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 202555c11941SMerav Sicron (var)++) \ 202655c11941SMerav Sicron if (skip_tx_queue(bp, var)) \ 202755c11941SMerav Sicron continue; \ 202855c11941SMerav Sicron else 202955c11941SMerav Sicron 2030adfc5217SJeff Kirsher #define for_each_tx_queue(bp, var) \ 2031adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2032adfc5217SJeff Kirsher if (skip_tx_queue(bp, var)) \ 2033adfc5217SJeff Kirsher continue; \ 2034adfc5217SJeff Kirsher else 2035adfc5217SJeff Kirsher 2036adfc5217SJeff Kirsher #define for_each_nondefault_queue(bp, var) \ 2037adfc5217SJeff Kirsher for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2038adfc5217SJeff Kirsher if (skip_queue(bp, var)) \ 2039adfc5217SJeff Kirsher continue; \ 2040adfc5217SJeff Kirsher else 2041adfc5217SJeff Kirsher 2042adfc5217SJeff Kirsher #define for_each_cos_in_tx_queue(fp, var) \ 2043adfc5217SJeff Kirsher for ((var) = 0; (var) < (fp)->max_cos; (var)++) 2044adfc5217SJeff Kirsher 2045adfc5217SJeff Kirsher /* skip rx queue 2046adfc5217SJeff Kirsher * if FCOE l2 support is disabled and this is the fcoe L2 queue 2047adfc5217SJeff Kirsher */ 2048adfc5217SJeff Kirsher #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2049adfc5217SJeff Kirsher 2050adfc5217SJeff Kirsher /* skip tx queue 2051adfc5217SJeff Kirsher * if FCOE l2 support is disabled and this is the fcoe L2 queue 2052adfc5217SJeff Kirsher */ 2053adfc5217SJeff Kirsher #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2054adfc5217SJeff Kirsher 2055adfc5217SJeff Kirsher #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2056adfc5217SJeff Kirsher 2057adfc5217SJeff Kirsher /** 2058adfc5217SJeff Kirsher * bnx2x_set_mac_one - configure a single MAC address 2059adfc5217SJeff Kirsher * 2060adfc5217SJeff Kirsher * @bp: driver handle 2061adfc5217SJeff Kirsher * @mac: MAC to configure 2062adfc5217SJeff Kirsher * @obj: MAC object handle 2063adfc5217SJeff Kirsher * @set: if 'true' add a new MAC, otherwise - delete 2064adfc5217SJeff Kirsher * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 2065adfc5217SJeff Kirsher * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 2066adfc5217SJeff Kirsher * 2067adfc5217SJeff Kirsher * Configures one MAC according to provided parameters or continues the 2068adfc5217SJeff Kirsher * execution of previously scheduled commands if RAMROD_CONT is set in 2069adfc5217SJeff Kirsher * ramrod_flags. 2070adfc5217SJeff Kirsher * 2071adfc5217SJeff Kirsher * Returns zero if operation has successfully completed, a positive value if the 2072adfc5217SJeff Kirsher * operation has been successfully scheduled and a negative - if a requested 2073adfc5217SJeff Kirsher * operations has failed. 2074adfc5217SJeff Kirsher */ 2075adfc5217SJeff Kirsher int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 2076adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *obj, bool set, 2077adfc5217SJeff Kirsher int mac_type, unsigned long *ramrod_flags); 2078adfc5217SJeff Kirsher /** 2079adfc5217SJeff Kirsher * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 2080adfc5217SJeff Kirsher * 2081adfc5217SJeff Kirsher * @bp: driver handle 2082adfc5217SJeff Kirsher * @mac_obj: MAC object handle 2083adfc5217SJeff Kirsher * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 2084adfc5217SJeff Kirsher * @wait_for_comp: if 'true' block until completion 2085adfc5217SJeff Kirsher * 2086adfc5217SJeff Kirsher * Deletes all MACs of the specific type (e.g. ETH, UC list). 2087adfc5217SJeff Kirsher * 2088adfc5217SJeff Kirsher * Returns zero if operation has successfully completed, a positive value if the 2089adfc5217SJeff Kirsher * operation has been successfully scheduled and a negative - if a requested 2090adfc5217SJeff Kirsher * operations has failed. 2091adfc5217SJeff Kirsher */ 2092adfc5217SJeff Kirsher int bnx2x_del_all_macs(struct bnx2x *bp, 2093adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj, 2094adfc5217SJeff Kirsher int mac_type, bool wait_for_comp); 2095adfc5217SJeff Kirsher 2096adfc5217SJeff Kirsher /* Init Function API */ 2097adfc5217SJeff Kirsher void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 2098b93288d5SAriel Elior void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 2099b93288d5SAriel Elior u8 vf_valid, int fw_sb_id, int igu_sb_id); 2100adfc5217SJeff Kirsher int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 2101adfc5217SJeff Kirsher int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2102adfc5217SJeff Kirsher int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 2103adfc5217SJeff Kirsher int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2104adfc5217SJeff Kirsher void bnx2x_read_mf_cfg(struct bnx2x *bp); 2105adfc5217SJeff Kirsher 2106b56e9670SAriel Elior int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 2107adfc5217SJeff Kirsher 2108adfc5217SJeff Kirsher /* dmae */ 2109adfc5217SJeff Kirsher void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 2110adfc5217SJeff Kirsher void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 2111adfc5217SJeff Kirsher u32 len32); 2112adfc5217SJeff Kirsher void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 2113adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 2114adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 2115adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 2116adfc5217SJeff Kirsher bool with_comp, u8 comp_type); 2117adfc5217SJeff Kirsher 2118fd1fc79dSAriel Elior void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2119fd1fc79dSAriel Elior u8 src_type, u8 dst_type); 212032316a46SAriel Elior int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 212132316a46SAriel Elior u32 *comp); 2122fd1fc79dSAriel Elior 2123d16132ceSAriel Elior /* FLR related routines */ 2124d16132ceSAriel Elior u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 2125d16132ceSAriel Elior void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 2126d16132ceSAriel Elior int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 2127b56e9670SAriel Elior u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 2128d16132ceSAriel Elior int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 2129d16132ceSAriel Elior char *msg, u32 poll_cnt); 2130adfc5217SJeff Kirsher 2131adfc5217SJeff Kirsher void bnx2x_calc_fc_adv(struct bnx2x *bp); 2132adfc5217SJeff Kirsher int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 2133adfc5217SJeff Kirsher u32 data_hi, u32 data_lo, int cmd_type); 2134adfc5217SJeff Kirsher void bnx2x_update_coalesce(struct bnx2x *bp); 2135adfc5217SJeff Kirsher int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 2136adfc5217SJeff Kirsher 2137178135c1SDmitry Kravkov bool bnx2x_port_after_undi(struct bnx2x *bp); 2138178135c1SDmitry Kravkov 2139adfc5217SJeff Kirsher static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 2140adfc5217SJeff Kirsher int wait) 2141adfc5217SJeff Kirsher { 2142adfc5217SJeff Kirsher u32 val; 2143adfc5217SJeff Kirsher 2144adfc5217SJeff Kirsher do { 2145adfc5217SJeff Kirsher val = REG_RD(bp, reg); 2146adfc5217SJeff Kirsher if (val == expected) 2147adfc5217SJeff Kirsher break; 2148adfc5217SJeff Kirsher ms -= wait; 2149adfc5217SJeff Kirsher msleep(wait); 2150adfc5217SJeff Kirsher 2151adfc5217SJeff Kirsher } while (ms > 0); 2152adfc5217SJeff Kirsher 2153adfc5217SJeff Kirsher return val; 2154adfc5217SJeff Kirsher } 2155adfc5217SJeff Kirsher 2156b56e9670SAriel Elior void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 2157b56e9670SAriel Elior bool is_pf); 2158b56e9670SAriel Elior 2159adfc5217SJeff Kirsher #define BNX2X_ILT_ZALLOC(x, y, size) \ 2160ede23fa8SJoe Perches x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL) 2161adfc5217SJeff Kirsher 2162adfc5217SJeff Kirsher #define BNX2X_ILT_FREE(x, y, size) \ 2163adfc5217SJeff Kirsher do { \ 2164adfc5217SJeff Kirsher if (x) { \ 2165adfc5217SJeff Kirsher dma_free_coherent(&bp->pdev->dev, size, x, y); \ 2166adfc5217SJeff Kirsher x = NULL; \ 2167adfc5217SJeff Kirsher y = 0; \ 2168adfc5217SJeff Kirsher } \ 2169adfc5217SJeff Kirsher } while (0) 2170adfc5217SJeff Kirsher 2171adfc5217SJeff Kirsher #define ILOG2(x) (ilog2((x))) 2172adfc5217SJeff Kirsher 2173adfc5217SJeff Kirsher #define ILT_NUM_PAGE_ENTRIES (3072) 2174adfc5217SJeff Kirsher /* In 57710/11 we use whole table since we have 8 func 2175adfc5217SJeff Kirsher * In 57712 we have only 4 func, but use same size per func, then only half of 2176adfc5217SJeff Kirsher * the table in use 2177adfc5217SJeff Kirsher */ 2178adfc5217SJeff Kirsher #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 2179adfc5217SJeff Kirsher 2180adfc5217SJeff Kirsher #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 2181adfc5217SJeff Kirsher /* 2182adfc5217SJeff Kirsher * the phys address is shifted right 12 bits and has an added 2183adfc5217SJeff Kirsher * 1=valid bit added to the 53rd bit 2184adfc5217SJeff Kirsher * then since this is a wide register(TM) 2185adfc5217SJeff Kirsher * we split it into two 32 bit writes 2186adfc5217SJeff Kirsher */ 2187adfc5217SJeff Kirsher #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 2188adfc5217SJeff Kirsher #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 2189adfc5217SJeff Kirsher 2190adfc5217SJeff Kirsher /* load/unload mode */ 2191adfc5217SJeff Kirsher #define LOAD_NORMAL 0 2192adfc5217SJeff Kirsher #define LOAD_OPEN 1 2193adfc5217SJeff Kirsher #define LOAD_DIAG 2 21948970b2e4SMerav Sicron #define LOAD_LOOPBACK_EXT 3 2195adfc5217SJeff Kirsher #define UNLOAD_NORMAL 0 2196adfc5217SJeff Kirsher #define UNLOAD_CLOSE 1 2197adfc5217SJeff Kirsher #define UNLOAD_RECOVERY 2 2198adfc5217SJeff Kirsher 2199adfc5217SJeff Kirsher /* DMAE command defines */ 2200adfc5217SJeff Kirsher #define DMAE_TIMEOUT -1 2201adfc5217SJeff Kirsher #define DMAE_PCI_ERROR -2 /* E2 and onward */ 2202adfc5217SJeff Kirsher #define DMAE_NOT_RDY -3 2203adfc5217SJeff Kirsher #define DMAE_PCI_ERR_FLAG 0x80000000 2204adfc5217SJeff Kirsher 2205adfc5217SJeff Kirsher #define DMAE_SRC_PCI 0 2206adfc5217SJeff Kirsher #define DMAE_SRC_GRC 1 2207adfc5217SJeff Kirsher 2208adfc5217SJeff Kirsher #define DMAE_DST_NONE 0 2209adfc5217SJeff Kirsher #define DMAE_DST_PCI 1 2210adfc5217SJeff Kirsher #define DMAE_DST_GRC 2 2211adfc5217SJeff Kirsher 2212adfc5217SJeff Kirsher #define DMAE_COMP_PCI 0 2213adfc5217SJeff Kirsher #define DMAE_COMP_GRC 1 2214adfc5217SJeff Kirsher 2215adfc5217SJeff Kirsher /* E2 and onward - PCI error handling in the completion */ 2216adfc5217SJeff Kirsher 2217adfc5217SJeff Kirsher #define DMAE_COMP_REGULAR 0 2218adfc5217SJeff Kirsher #define DMAE_COM_SET_ERR 1 2219adfc5217SJeff Kirsher 2220adfc5217SJeff Kirsher #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2221adfc5217SJeff Kirsher DMAE_COMMAND_SRC_SHIFT) 2222adfc5217SJeff Kirsher #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2223adfc5217SJeff Kirsher DMAE_COMMAND_SRC_SHIFT) 2224adfc5217SJeff Kirsher 2225adfc5217SJeff Kirsher #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2226adfc5217SJeff Kirsher DMAE_COMMAND_DST_SHIFT) 2227adfc5217SJeff Kirsher #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2228adfc5217SJeff Kirsher DMAE_COMMAND_DST_SHIFT) 2229adfc5217SJeff Kirsher 2230adfc5217SJeff Kirsher #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2231adfc5217SJeff Kirsher DMAE_COMMAND_C_DST_SHIFT) 2232adfc5217SJeff Kirsher #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2233adfc5217SJeff Kirsher DMAE_COMMAND_C_DST_SHIFT) 2234adfc5217SJeff Kirsher 2235adfc5217SJeff Kirsher #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2236adfc5217SJeff Kirsher 2237adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2238adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2239adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2240adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2241adfc5217SJeff Kirsher 2242adfc5217SJeff Kirsher #define DMAE_CMD_PORT_0 0 2243adfc5217SJeff Kirsher #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2244adfc5217SJeff Kirsher 2245adfc5217SJeff Kirsher #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2246adfc5217SJeff Kirsher #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2247adfc5217SJeff Kirsher #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2248adfc5217SJeff Kirsher 2249adfc5217SJeff Kirsher #define DMAE_SRC_PF 0 2250adfc5217SJeff Kirsher #define DMAE_SRC_VF 1 2251adfc5217SJeff Kirsher 2252adfc5217SJeff Kirsher #define DMAE_DST_PF 0 2253adfc5217SJeff Kirsher #define DMAE_DST_VF 1 2254adfc5217SJeff Kirsher 2255adfc5217SJeff Kirsher #define DMAE_C_SRC 0 2256adfc5217SJeff Kirsher #define DMAE_C_DST 1 2257adfc5217SJeff Kirsher 2258adfc5217SJeff Kirsher #define DMAE_LEN32_RD_MAX 0x80 2259adfc5217SJeff Kirsher #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2260adfc5217SJeff Kirsher 2261adfc5217SJeff Kirsher #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 226216a5fd92SYuval Mintz * indicates error 226316a5fd92SYuval Mintz */ 2264adfc5217SJeff Kirsher 2265adfc5217SJeff Kirsher #define MAX_DMAE_C_PER_PORT 8 2266adfc5217SJeff Kirsher #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 22678decf868SDavid S. Miller BP_VN(bp)) 2268adfc5217SJeff Kirsher #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2269adfc5217SJeff Kirsher E1HVN_MAX) 2270adfc5217SJeff Kirsher 2271adfc5217SJeff Kirsher /* PCIE link and speed */ 2272adfc5217SJeff Kirsher #define PCICFG_LINK_WIDTH 0x1f00000 2273adfc5217SJeff Kirsher #define PCICFG_LINK_WIDTH_SHIFT 20 2274adfc5217SJeff Kirsher #define PCICFG_LINK_SPEED 0xf0000 2275adfc5217SJeff Kirsher #define PCICFG_LINK_SPEED_SHIFT 16 2276adfc5217SJeff Kirsher 2277cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS_SF 7 2278cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS_MF 3 2279cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 228075543741SYuval Mintz IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF) 2281adfc5217SJeff Kirsher 2282adfc5217SJeff Kirsher #define BNX2X_PHY_LOOPBACK 0 2283adfc5217SJeff Kirsher #define BNX2X_MAC_LOOPBACK 1 22848970b2e4SMerav Sicron #define BNX2X_EXT_LOOPBACK 2 2285adfc5217SJeff Kirsher #define BNX2X_PHY_LOOPBACK_FAILED 1 2286adfc5217SJeff Kirsher #define BNX2X_MAC_LOOPBACK_FAILED 2 22878970b2e4SMerav Sicron #define BNX2X_EXT_LOOPBACK_FAILED 3 2288adfc5217SJeff Kirsher #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2289adfc5217SJeff Kirsher BNX2X_PHY_LOOPBACK_FAILED) 2290adfc5217SJeff Kirsher 2291adfc5217SJeff Kirsher #define STROM_ASSERT_ARRAY_SIZE 50 2292adfc5217SJeff Kirsher 2293adfc5217SJeff Kirsher /* must be used on a CID before placing it on a HW ring */ 2294adfc5217SJeff Kirsher #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 22958decf868SDavid S. Miller (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2296adfc5217SJeff Kirsher (x)) 2297adfc5217SJeff Kirsher 2298adfc5217SJeff Kirsher #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2299adfc5217SJeff Kirsher #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2300adfc5217SJeff Kirsher 2301adfc5217SJeff Kirsher #define BNX2X_BTR 4 2302adfc5217SJeff Kirsher #define MAX_SPQ_PENDING 8 2303adfc5217SJeff Kirsher 2304adfc5217SJeff Kirsher /* CMNG constants, as derived from system spec calculations */ 2305adfc5217SJeff Kirsher /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2306adfc5217SJeff Kirsher #define DEF_MIN_RATE 100 2307adfc5217SJeff Kirsher /* resolution of the rate shaping timer - 400 usec */ 2308adfc5217SJeff Kirsher #define RS_PERIODIC_TIMEOUT_USEC 400 2309adfc5217SJeff Kirsher /* number of bytes in single QM arbitration cycle - 2310adfc5217SJeff Kirsher * coefficient for calculating the fairness timer */ 2311adfc5217SJeff Kirsher #define QM_ARB_BYTES 160000 2312adfc5217SJeff Kirsher /* resolution of Min algorithm 1:100 */ 2313adfc5217SJeff Kirsher #define MIN_RES 100 2314adfc5217SJeff Kirsher /* how many bytes above threshold for the minimal credit of Min algorithm*/ 2315adfc5217SJeff Kirsher #define MIN_ABOVE_THRESH 32768 2316adfc5217SJeff Kirsher /* Fairness algorithm integration time coefficient - 2317adfc5217SJeff Kirsher * for calculating the actual Tfair */ 2318adfc5217SJeff Kirsher #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2319adfc5217SJeff Kirsher /* Memory of fairness algorithm . 2 cycles */ 2320adfc5217SJeff Kirsher #define FAIR_MEM 2 2321adfc5217SJeff Kirsher 2322adfc5217SJeff Kirsher #define ATTN_NIG_FOR_FUNC (1L << 8) 2323adfc5217SJeff Kirsher #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2324adfc5217SJeff Kirsher #define GPIO_2_FUNC (1L << 10) 2325adfc5217SJeff Kirsher #define GPIO_3_FUNC (1L << 11) 2326adfc5217SJeff Kirsher #define GPIO_4_FUNC (1L << 12) 2327adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_1 (1L << 13) 2328adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_2 (1L << 14) 2329adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_3 (1L << 15) 2330adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_4 (1L << 13) 2331adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_5 (1L << 14) 2332adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_6 (1L << 15) 2333adfc5217SJeff Kirsher 2334adfc5217SJeff Kirsher #define ATTN_HARD_WIRED_MASK 0xff00 2335adfc5217SJeff Kirsher #define ATTENTION_ID 4 2336adfc5217SJeff Kirsher 23373521b419SYuval Mintz #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \ 23383521b419SYuval Mintz IS_MF_FCOE_AFEX(bp)) 2339adfc5217SJeff Kirsher 2340adfc5217SJeff Kirsher /* stuff added to make the code fit 80Col */ 2341adfc5217SJeff Kirsher 2342adfc5217SJeff Kirsher #define BNX2X_PMF_LINK_ASSERT \ 2343adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2344adfc5217SJeff Kirsher 2345adfc5217SJeff Kirsher #define BNX2X_MC_ASSERT_BITS \ 2346adfc5217SJeff Kirsher (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2347adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2348adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2349adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2350adfc5217SJeff Kirsher 2351adfc5217SJeff Kirsher #define BNX2X_MCP_ASSERT \ 2352adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2353adfc5217SJeff Kirsher 2354adfc5217SJeff Kirsher #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2355adfc5217SJeff Kirsher #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2356adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2357adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2358adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2359adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2360adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2361adfc5217SJeff Kirsher 2362adfc5217SJeff Kirsher #define HW_INTERRUT_ASSERT_SET_0 \ 2363adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2364adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2365adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2366c14a09b7SDmitry Kravkov AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2367adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2368adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2369adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2370adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2371adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2372adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2373adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2374adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2375adfc5217SJeff Kirsher #define HW_INTERRUT_ASSERT_SET_1 \ 2376adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2377adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2378adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2379adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2380adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2381adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2382adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2383adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2384adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2385adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2386adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2387adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2388adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2389adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2390adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2391adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2392adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2393adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2394adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2395adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2396adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2397adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2398adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2399adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2400adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2401adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2402adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2403adfc5217SJeff Kirsher #define HW_INTERRUT_ASSERT_SET_2 \ 2404adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2405adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2406adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2407adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2408adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2409adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2410adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2411adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2412adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2413adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2414adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2415adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2416adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2417adfc5217SJeff Kirsher 2418adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2419adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2420adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2421adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2422adfc5217SJeff Kirsher 2423adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2424adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2425adfc5217SJeff Kirsher 2426adfc5217SJeff Kirsher #define MULTI_MASK 0x7f 2427adfc5217SJeff Kirsher 2428adfc5217SJeff Kirsher #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2429adfc5217SJeff Kirsher #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2430adfc5217SJeff Kirsher #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2431adfc5217SJeff Kirsher #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2432adfc5217SJeff Kirsher 2433adfc5217SJeff Kirsher #define DEF_USB_IGU_INDEX_OFF \ 2434adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_u, igu_index) 2435adfc5217SJeff Kirsher #define DEF_CSB_IGU_INDEX_OFF \ 2436adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_c, igu_index) 2437adfc5217SJeff Kirsher #define DEF_XSB_IGU_INDEX_OFF \ 2438adfc5217SJeff Kirsher offsetof(struct xstorm_def_status_block, igu_index) 2439adfc5217SJeff Kirsher #define DEF_TSB_IGU_INDEX_OFF \ 2440adfc5217SJeff Kirsher offsetof(struct tstorm_def_status_block, igu_index) 2441adfc5217SJeff Kirsher 2442adfc5217SJeff Kirsher #define DEF_USB_SEGMENT_OFF \ 2443adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_u, segment) 2444adfc5217SJeff Kirsher #define DEF_CSB_SEGMENT_OFF \ 2445adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_c, segment) 2446adfc5217SJeff Kirsher #define DEF_XSB_SEGMENT_OFF \ 2447adfc5217SJeff Kirsher offsetof(struct xstorm_def_status_block, segment) 2448adfc5217SJeff Kirsher #define DEF_TSB_SEGMENT_OFF \ 2449adfc5217SJeff Kirsher offsetof(struct tstorm_def_status_block, segment) 2450adfc5217SJeff Kirsher 2451adfc5217SJeff Kirsher #define BNX2X_SP_DSB_INDEX \ 2452adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 2453adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2454adfc5217SJeff Kirsher 2455adfc5217SJeff Kirsher #define CAM_IS_INVALID(x) \ 2456adfc5217SJeff Kirsher (GET_FLAG(x.flags, \ 2457adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2458adfc5217SJeff Kirsher (T_ETH_MAC_COMMAND_INVALIDATE)) 2459adfc5217SJeff Kirsher 2460adfc5217SJeff Kirsher /* Number of u32 elements in MC hash array */ 2461adfc5217SJeff Kirsher #define MC_HASH_SIZE 8 2462adfc5217SJeff Kirsher #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2463adfc5217SJeff Kirsher TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2464adfc5217SJeff Kirsher 2465adfc5217SJeff Kirsher #ifndef PXP2_REG_PXP2_INT_STS 2466adfc5217SJeff Kirsher #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2467adfc5217SJeff Kirsher #endif 2468adfc5217SJeff Kirsher 2469adfc5217SJeff Kirsher #ifndef ETH_MAX_RX_CLIENTS_E2 2470adfc5217SJeff Kirsher #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2471adfc5217SJeff Kirsher #endif 2472adfc5217SJeff Kirsher 2473adfc5217SJeff Kirsher #define BNX2X_VPD_LEN 128 2474adfc5217SJeff Kirsher #define VENDOR_ID_LEN 4 2475adfc5217SJeff Kirsher 2476be1f1ffaSAriel Elior #define VF_ACQUIRE_THRESH 3 2477be1f1ffaSAriel Elior #define VF_ACQUIRE_MAC_FILTERS 1 2478be1f1ffaSAriel Elior #define VF_ACQUIRE_MC_FILTERS 10 2479be1f1ffaSAriel Elior 2480be1f1ffaSAriel Elior #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2481be1f1ffaSAriel Elior (!((me_reg) & ME_REG_VF_ERR))) 248291ebb929SYuval Mintz int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err); 248391ebb929SYuval Mintz 2484adfc5217SJeff Kirsher /* Congestion management fairness mode */ 2485adfc5217SJeff Kirsher #define CMNG_FNS_NONE 0 2486adfc5217SJeff Kirsher #define CMNG_FNS_MINMAX 1 2487adfc5217SJeff Kirsher 2488adfc5217SJeff Kirsher #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2489adfc5217SJeff Kirsher #define HC_SEG_ACCESS_ATTN 4 2490adfc5217SJeff Kirsher #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2491adfc5217SJeff Kirsher 2492adfc5217SJeff Kirsher static const u32 dmae_reg_go_c[] = { 2493adfc5217SJeff Kirsher DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2494adfc5217SJeff Kirsher DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2495adfc5217SJeff Kirsher DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2496adfc5217SJeff Kirsher DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2497adfc5217SJeff Kirsher }; 2498adfc5217SJeff Kirsher 2499005a07baSAriel Elior void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); 2500adfc5217SJeff Kirsher void bnx2x_notify_link_changed(struct bnx2x *bp); 2501614c76dfSDmitry Kravkov 25029e62e912SDmitry Kravkov #define BNX2X_MF_SD_PROTOCOL(bp) \ 2503614c76dfSDmitry Kravkov ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2504614c76dfSDmitry Kravkov 25059e62e912SDmitry Kravkov #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 25069e62e912SDmitry Kravkov (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2507614c76dfSDmitry Kravkov 25089e62e912SDmitry Kravkov #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 25099e62e912SDmitry Kravkov (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 25109e62e912SDmitry Kravkov 25119e62e912SDmitry Kravkov #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 25129e62e912SDmitry Kravkov #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 25139e62e912SDmitry Kravkov 2514a3348722SBarak Witkowski #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2515a3348722SBarak Witkowski MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2516a3348722SBarak Witkowski 2517a3348722SBarak Witkowski #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 25189e62e912SDmitry Kravkov #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 25199e62e912SDmitry Kravkov (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 25209e62e912SDmitry Kravkov BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2521614c76dfSDmitry Kravkov 25222de67439SYuval Mintz #define SET_FLAG(value, mask, flag) \ 25232de67439SYuval Mintz do {\ 25242de67439SYuval Mintz (value) &= ~(mask);\ 25252de67439SYuval Mintz (value) |= ((flag) << (mask##_SHIFT));\ 25262de67439SYuval Mintz } while (0) 25272de67439SYuval Mintz 25282de67439SYuval Mintz #define GET_FLAG(value, mask) \ 25292de67439SYuval Mintz (((value) & (mask)) >> (mask##_SHIFT)) 25302de67439SYuval Mintz 25312de67439SYuval Mintz #define GET_FIELD(value, fname) \ 25322de67439SYuval Mintz (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 25332de67439SYuval Mintz 253455c11941SMerav Sicron enum { 253555c11941SMerav Sicron SWITCH_UPDATE, 253655c11941SMerav Sicron AFEX_UPDATE, 253755c11941SMerav Sicron }; 253855c11941SMerav Sicron 253955c11941SMerav Sicron #define NUM_MACS 8 2540a3348722SBarak Witkowski 2541568e2426SDmitry Kravkov void bnx2x_set_local_cmng(struct bnx2x *bp); 25421a6974b2SYuval Mintz 254342f8277fSYuval Mintz void bnx2x_update_mng_version(struct bnx2x *bp); 254442f8277fSYuval Mintz 25451a6974b2SYuval Mintz #define MCPR_SCRATCH_BASE(bp) \ 25461a6974b2SYuval Mintz (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 25471a6974b2SYuval Mintz 2548e848582cSDmitry Kravkov #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX)) 2549e848582cSDmitry Kravkov 2550adfc5217SJeff Kirsher #endif /* bnx2x.h */ 2551