1adfc5217SJeff Kirsher /* bnx2x.h: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2007-2013 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7adfc5217SJeff Kirsher * the Free Software Foundation. 8adfc5217SJeff Kirsher * 9adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10adfc5217SJeff Kirsher * Written by: Eliezer Tamir 11adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 12adfc5217SJeff Kirsher */ 13adfc5217SJeff Kirsher 14adfc5217SJeff Kirsher #ifndef BNX2X_H 15adfc5217SJeff Kirsher #define BNX2X_H 16290ca2bbSAriel Elior 17290ca2bbSAriel Elior #include <linux/pci.h> 18adfc5217SJeff Kirsher #include <linux/netdevice.h> 19adfc5217SJeff Kirsher #include <linux/dma-mapping.h> 20adfc5217SJeff Kirsher #include <linux/types.h> 21290ca2bbSAriel Elior #include <linux/pci_regs.h> 22adfc5217SJeff Kirsher 23adfc5217SJeff Kirsher /* compilation time flags */ 24adfc5217SJeff Kirsher 25adfc5217SJeff Kirsher /* define this to make the driver freeze on error to allow getting debug info 26adfc5217SJeff Kirsher * (you will need to reboot afterwards) */ 27adfc5217SJeff Kirsher /* #define BNX2X_STOP_ON_ERROR */ 28adfc5217SJeff Kirsher 2926f26b3aSDmitry Kravkov #define DRV_MODULE_VERSION "1.78.17-0" 3026f26b3aSDmitry Kravkov #define DRV_MODULE_RELDATE "2013/04/11" 31adfc5217SJeff Kirsher #define BNX2X_BC_VER 0x040200 32adfc5217SJeff Kirsher 33adfc5217SJeff Kirsher #if defined(CONFIG_DCB) 34adfc5217SJeff Kirsher #define BCM_DCBNL 35adfc5217SJeff Kirsher #endif 36b475d78fSYuval Mintz 37b475d78fSYuval Mintz #include "bnx2x_hsi.h" 38b475d78fSYuval Mintz 39adfc5217SJeff Kirsher #include "../cnic_if.h" 40adfc5217SJeff Kirsher 4155c11941SMerav Sicron #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 42adfc5217SJeff Kirsher 43adfc5217SJeff Kirsher #include <linux/mdio.h> 44adfc5217SJeff Kirsher 45adfc5217SJeff Kirsher #include "bnx2x_reg.h" 46adfc5217SJeff Kirsher #include "bnx2x_fw_defs.h" 472e499d3cSBarak Witkowski #include "bnx2x_mfw_req.h" 48adfc5217SJeff Kirsher #include "bnx2x_link.h" 49adfc5217SJeff Kirsher #include "bnx2x_sp.h" 50adfc5217SJeff Kirsher #include "bnx2x_dcb.h" 51adfc5217SJeff Kirsher #include "bnx2x_stats.h" 52be1f1ffaSAriel Elior #include "bnx2x_vfpf.h" 53adfc5217SJeff Kirsher 541ab4434cSAriel Elior enum bnx2x_int_mode { 551ab4434cSAriel Elior BNX2X_INT_MODE_MSIX, 561ab4434cSAriel Elior BNX2X_INT_MODE_INTX, 571ab4434cSAriel Elior BNX2X_INT_MODE_MSI 581ab4434cSAriel Elior }; 591ab4434cSAriel Elior 60adfc5217SJeff Kirsher /* error/debug prints */ 61adfc5217SJeff Kirsher 62adfc5217SJeff Kirsher #define DRV_MODULE_NAME "bnx2x" 63adfc5217SJeff Kirsher 64adfc5217SJeff Kirsher /* for messages that are currently off */ 6551c1a580SMerav Sicron #define BNX2X_MSG_OFF 0x0 6651c1a580SMerav Sicron #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 6751c1a580SMerav Sicron #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 6851c1a580SMerav Sicron #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 6951c1a580SMerav Sicron #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 7051c1a580SMerav Sicron #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 7151c1a580SMerav Sicron #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 7251c1a580SMerav Sicron #define BNX2X_MSG_IOV 0x0800000 7351c1a580SMerav Sicron #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 7451c1a580SMerav Sicron #define BNX2X_MSG_ETHTOOL 0x4000000 7551c1a580SMerav Sicron #define BNX2X_MSG_DCB 0x8000000 76adfc5217SJeff Kirsher 77adfc5217SJeff Kirsher /* regular debug print */ 78f1deab50SJoe Perches #define DP(__mask, fmt, ...) \ 79adfc5217SJeff Kirsher do { \ 8051c1a580SMerav Sicron if (unlikely(bp->msg_enable & (__mask))) \ 81f1deab50SJoe Perches pr_notice("[%s:%d(%s)]" fmt, \ 82adfc5217SJeff Kirsher __func__, __LINE__, \ 83adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 84f1deab50SJoe Perches ##__VA_ARGS__); \ 85adfc5217SJeff Kirsher } while (0) 86adfc5217SJeff Kirsher 87f1deab50SJoe Perches #define DP_CONT(__mask, fmt, ...) \ 88adfc5217SJeff Kirsher do { \ 8951c1a580SMerav Sicron if (unlikely(bp->msg_enable & (__mask))) \ 90f1deab50SJoe Perches pr_cont(fmt, ##__VA_ARGS__); \ 91adfc5217SJeff Kirsher } while (0) 92adfc5217SJeff Kirsher 93adfc5217SJeff Kirsher /* errors debug print */ 94f1deab50SJoe Perches #define BNX2X_DBG_ERR(fmt, ...) \ 95adfc5217SJeff Kirsher do { \ 9651c1a580SMerav Sicron if (unlikely(netif_msg_probe(bp))) \ 97f1deab50SJoe Perches pr_err("[%s:%d(%s)]" fmt, \ 98adfc5217SJeff Kirsher __func__, __LINE__, \ 99adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 100f1deab50SJoe Perches ##__VA_ARGS__); \ 101adfc5217SJeff Kirsher } while (0) 102adfc5217SJeff Kirsher 103adfc5217SJeff Kirsher /* for errors (never masked) */ 104f1deab50SJoe Perches #define BNX2X_ERR(fmt, ...) \ 105adfc5217SJeff Kirsher do { \ 106f1deab50SJoe Perches pr_err("[%s:%d(%s)]" fmt, \ 107adfc5217SJeff Kirsher __func__, __LINE__, \ 108adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 109f1deab50SJoe Perches ##__VA_ARGS__); \ 110adfc5217SJeff Kirsher } while (0) 111adfc5217SJeff Kirsher 112f1deab50SJoe Perches #define BNX2X_ERROR(fmt, ...) \ 113f1deab50SJoe Perches pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 114adfc5217SJeff Kirsher 115adfc5217SJeff Kirsher /* before we have a dev->name use dev_info() */ 116f1deab50SJoe Perches #define BNX2X_DEV_INFO(fmt, ...) \ 117adfc5217SJeff Kirsher do { \ 11851c1a580SMerav Sicron if (unlikely(netif_msg_probe(bp))) \ 119f1deab50SJoe Perches dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 120adfc5217SJeff Kirsher } while (0) 121adfc5217SJeff Kirsher 122ca9bdb9bSYuval Mintz /* Error handling */ 123ca9bdb9bSYuval Mintz void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); 124adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 125f1deab50SJoe Perches #define bnx2x_panic() \ 126f1deab50SJoe Perches do { \ 127adfc5217SJeff Kirsher bp->panic = 1; \ 128adfc5217SJeff Kirsher BNX2X_ERR("driver assert\n"); \ 129823e1d90SYuval Mintz bnx2x_panic_dump(bp, true); \ 130adfc5217SJeff Kirsher } while (0) 131adfc5217SJeff Kirsher #else 132f1deab50SJoe Perches #define bnx2x_panic() \ 133f1deab50SJoe Perches do { \ 134adfc5217SJeff Kirsher bp->panic = 1; \ 135adfc5217SJeff Kirsher BNX2X_ERR("driver assert\n"); \ 136823e1d90SYuval Mintz bnx2x_panic_dump(bp, false); \ 137adfc5217SJeff Kirsher } while (0) 138adfc5217SJeff Kirsher #endif 139adfc5217SJeff Kirsher 140adfc5217SJeff Kirsher #define bnx2x_mc_addr(ha) ((ha)->addr) 141adfc5217SJeff Kirsher #define bnx2x_uc_addr(ha) ((ha)->addr) 142adfc5217SJeff Kirsher 1432de67439SYuval Mintz #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 1442de67439SYuval Mintz #define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 145adfc5217SJeff Kirsher #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 146adfc5217SJeff Kirsher 147adfc5217SJeff Kirsher #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 148adfc5217SJeff Kirsher 149adfc5217SJeff Kirsher #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 150adfc5217SJeff Kirsher #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 151adfc5217SJeff Kirsher #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 152adfc5217SJeff Kirsher 153adfc5217SJeff Kirsher #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 154adfc5217SJeff Kirsher #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 155adfc5217SJeff Kirsher #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 156adfc5217SJeff Kirsher 157adfc5217SJeff Kirsher #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 158adfc5217SJeff Kirsher #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 159adfc5217SJeff Kirsher 160adfc5217SJeff Kirsher #define REG_RD_DMAE(bp, offset, valp, len32) \ 161adfc5217SJeff Kirsher do { \ 162adfc5217SJeff Kirsher bnx2x_read_dmae(bp, offset, len32);\ 163adfc5217SJeff Kirsher memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 164adfc5217SJeff Kirsher } while (0) 165adfc5217SJeff Kirsher 166adfc5217SJeff Kirsher #define REG_WR_DMAE(bp, offset, valp, len32) \ 167adfc5217SJeff Kirsher do { \ 168adfc5217SJeff Kirsher memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 169adfc5217SJeff Kirsher bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 170adfc5217SJeff Kirsher offset, len32); \ 171adfc5217SJeff Kirsher } while (0) 172adfc5217SJeff Kirsher 173adfc5217SJeff Kirsher #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 174adfc5217SJeff Kirsher REG_WR_DMAE(bp, offset, valp, len32) 175adfc5217SJeff Kirsher 176adfc5217SJeff Kirsher #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 177adfc5217SJeff Kirsher do { \ 178adfc5217SJeff Kirsher memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 179adfc5217SJeff Kirsher bnx2x_write_big_buf_wb(bp, addr, len32); \ 180adfc5217SJeff Kirsher } while (0) 181adfc5217SJeff Kirsher 182adfc5217SJeff Kirsher #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 183adfc5217SJeff Kirsher offsetof(struct shmem_region, field)) 184adfc5217SJeff Kirsher #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 185adfc5217SJeff Kirsher #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 186adfc5217SJeff Kirsher 187adfc5217SJeff Kirsher #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 188adfc5217SJeff Kirsher offsetof(struct shmem2_region, field)) 189adfc5217SJeff Kirsher #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 190adfc5217SJeff Kirsher #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 191adfc5217SJeff Kirsher #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 192adfc5217SJeff Kirsher offsetof(struct mf_cfg, field)) 193adfc5217SJeff Kirsher #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 194adfc5217SJeff Kirsher offsetof(struct mf2_cfg, field)) 195adfc5217SJeff Kirsher 196adfc5217SJeff Kirsher #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 197adfc5217SJeff Kirsher #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 198adfc5217SJeff Kirsher MF_CFG_ADDR(bp, field), (val)) 199adfc5217SJeff Kirsher #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 200adfc5217SJeff Kirsher 201adfc5217SJeff Kirsher #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 202adfc5217SJeff Kirsher (SHMEM2_RD((bp), size) > \ 203adfc5217SJeff Kirsher offsetof(struct shmem2_region, field))) 204adfc5217SJeff Kirsher 205adfc5217SJeff Kirsher #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 206adfc5217SJeff Kirsher #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 207adfc5217SJeff Kirsher 208adfc5217SJeff Kirsher /* SP SB indices */ 209adfc5217SJeff Kirsher 210adfc5217SJeff Kirsher /* General SP events - stats query, cfc delete, etc */ 211adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_DEF_CONS 3 212adfc5217SJeff Kirsher 213adfc5217SJeff Kirsher /* EQ completions */ 214adfc5217SJeff Kirsher #define HC_SP_INDEX_EQ_CONS 7 215adfc5217SJeff Kirsher 216adfc5217SJeff Kirsher /* FCoE L2 connection completions */ 217adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 218adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 219adfc5217SJeff Kirsher /* iSCSI L2 */ 220adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 221adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 222adfc5217SJeff Kirsher 223adfc5217SJeff Kirsher /* Special clients parameters */ 224adfc5217SJeff Kirsher 225adfc5217SJeff Kirsher /* SB indices */ 226adfc5217SJeff Kirsher /* FCoE L2 */ 227adfc5217SJeff Kirsher #define BNX2X_FCOE_L2_RX_INDEX \ 228adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 229adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 230adfc5217SJeff Kirsher 231adfc5217SJeff Kirsher #define BNX2X_FCOE_L2_TX_INDEX \ 232adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 233adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 234adfc5217SJeff Kirsher 235adfc5217SJeff Kirsher /** 236adfc5217SJeff Kirsher * CIDs and CLIDs: 237adfc5217SJeff Kirsher * CLIDs below is a CLID for func 0, then the CLID for other 238adfc5217SJeff Kirsher * functions will be calculated by the formula: 239adfc5217SJeff Kirsher * 240adfc5217SJeff Kirsher * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 241adfc5217SJeff Kirsher * 242adfc5217SJeff Kirsher */ 2431805b2f0SDavid S. Miller enum { 2441805b2f0SDavid S. Miller BNX2X_ISCSI_ETH_CL_ID_IDX, 2451805b2f0SDavid S. Miller BNX2X_FCOE_ETH_CL_ID_IDX, 2461805b2f0SDavid S. Miller BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 2471805b2f0SDavid S. Miller }; 248adfc5217SJeff Kirsher 249f78afb35SMichael Chan /* use a value high enough to be above all the PFs, which has least significant 250f78afb35SMichael Chan * nibble as 8, so when cnic needs to come up with a CID for UIO to use to 251f78afb35SMichael Chan * calculate doorbell address according to old doorbell configuration scheme 252f78afb35SMichael Chan * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number 253f78afb35SMichael Chan * We must avoid coming up with cid 8 for iscsi since according to this method 254f78afb35SMichael Chan * the designated UIO cid will come out 0 and it has a special handling for that 255f78afb35SMichael Chan * case which doesn't suit us. Therefore will will cieling to closes cid which 256f78afb35SMichael Chan * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18. 257f78afb35SMichael Chan */ 258f78afb35SMichael Chan 259f78afb35SMichael Chan #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \ 26037ae41a9SMerav Sicron (bp)->max_cos) 261f78afb35SMichael Chan /* amount of cids traversed by UIO's DPM addition to doorbell */ 262f78afb35SMichael Chan #define UIO_DPM 8 263f78afb35SMichael Chan /* roundup to DPM offset */ 264f78afb35SMichael Chan #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \ 265f78afb35SMichael Chan UIO_DPM)) 266f78afb35SMichael Chan /* offset to nearest value which has lsb nibble matching DPM */ 267f78afb35SMichael Chan #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \ 268f78afb35SMichael Chan (UIO_DPM * 2)) 269f78afb35SMichael Chan /* add offset to rounded-up cid to get a value which could be used with UIO */ 270f78afb35SMichael Chan #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp)) 271f78afb35SMichael Chan /* but wait - avoid UIO special case for cid 0 */ 272f78afb35SMichael Chan #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \ 273f78afb35SMichael Chan (UIO_DPM_ALIGN(bp) == UIO_DPM)) 274f78afb35SMichael Chan /* Properly DPM aligned CID dajusted to cid 0 secal case */ 275f78afb35SMichael Chan #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \ 276f78afb35SMichael Chan (UIO_DPM_CID0_OFFSET(bp))) 277f78afb35SMichael Chan /* how many cids were wasted - need this value for cid allocation */ 278f78afb35SMichael Chan #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \ 279f78afb35SMichael Chan BNX2X_1st_NON_L2_ETH_CID(bp)) 2801805b2f0SDavid S. Miller /* iSCSI L2 */ 28137ae41a9SMerav Sicron #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 282adfc5217SJeff Kirsher /* FCoE L2 */ 28337ae41a9SMerav Sicron #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 284adfc5217SJeff Kirsher 28555c11941SMerav Sicron #define CNIC_SUPPORT(bp) ((bp)->cnic_support) 28655c11941SMerav Sicron #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 28755c11941SMerav Sicron #define CNIC_LOADED(bp) ((bp)->cnic_loaded) 28855c11941SMerav Sicron #define FCOE_INIT(bp) ((bp)->fcoe_init) 289adfc5217SJeff Kirsher 290adfc5217SJeff Kirsher #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 291adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 292adfc5217SJeff Kirsher 293adfc5217SJeff Kirsher #define SM_RX_ID 0 294adfc5217SJeff Kirsher #define SM_TX_ID 1 295adfc5217SJeff Kirsher 296adfc5217SJeff Kirsher /* defines for multiple tx priority indices */ 297adfc5217SJeff Kirsher #define FIRST_TX_ONLY_COS_INDEX 1 298adfc5217SJeff Kirsher #define FIRST_TX_COS_INDEX 0 299adfc5217SJeff Kirsher 300adfc5217SJeff Kirsher /* rules for calculating the cids of tx-only connections */ 30165565884SMerav Sicron #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 30265565884SMerav Sicron #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 30365565884SMerav Sicron (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 304adfc5217SJeff Kirsher 305adfc5217SJeff Kirsher /* fp index inside class of service range */ 30665565884SMerav Sicron #define FP_COS_TO_TXQ(fp, cos, bp) \ 30765565884SMerav Sicron ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 308adfc5217SJeff Kirsher 30965565884SMerav Sicron /* Indexes for transmission queues array: 31065565884SMerav Sicron * txdata for RSS i CoS j is at location i + (j * num of RSS) 31165565884SMerav Sicron * txdata for FCoE (if exist) is at location max cos * num of RSS 31265565884SMerav Sicron * txdata for FWD (if exist) is one location after FCoE 31365565884SMerav Sicron * txdata for OOO (if exist) is one location after FWD 314adfc5217SJeff Kirsher */ 31565565884SMerav Sicron enum { 31665565884SMerav Sicron FCOE_TXQ_IDX_OFFSET, 31765565884SMerav Sicron FWD_TXQ_IDX_OFFSET, 31865565884SMerav Sicron OOO_TXQ_IDX_OFFSET, 31965565884SMerav Sicron }; 32065565884SMerav Sicron #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 32165565884SMerav Sicron #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 322adfc5217SJeff Kirsher 323adfc5217SJeff Kirsher /* fast path */ 324e52fcb24SEric Dumazet /* 325e52fcb24SEric Dumazet * This driver uses new build_skb() API : 326e52fcb24SEric Dumazet * RX ring buffer contains pointer to kmalloc() data only, 327e52fcb24SEric Dumazet * skb are built only after Hardware filled the frame. 328e52fcb24SEric Dumazet */ 329adfc5217SJeff Kirsher struct sw_rx_bd { 330e52fcb24SEric Dumazet u8 *data; 331adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping); 332adfc5217SJeff Kirsher }; 333adfc5217SJeff Kirsher 334adfc5217SJeff Kirsher struct sw_tx_bd { 335adfc5217SJeff Kirsher struct sk_buff *skb; 336adfc5217SJeff Kirsher u16 first_bd; 337adfc5217SJeff Kirsher u8 flags; 338adfc5217SJeff Kirsher /* Set on the first BD descriptor when there is a split BD */ 339adfc5217SJeff Kirsher #define BNX2X_TSO_SPLIT_BD (1<<0) 340adfc5217SJeff Kirsher }; 341adfc5217SJeff Kirsher 342adfc5217SJeff Kirsher struct sw_rx_page { 343adfc5217SJeff Kirsher struct page *page; 344adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping); 345adfc5217SJeff Kirsher }; 346adfc5217SJeff Kirsher 347adfc5217SJeff Kirsher union db_prod { 348adfc5217SJeff Kirsher struct doorbell_set_prod data; 349adfc5217SJeff Kirsher u32 raw; 350adfc5217SJeff Kirsher }; 351adfc5217SJeff Kirsher 3528decf868SDavid S. Miller /* dropless fc FW/HW related params */ 3538decf868SDavid S. Miller #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 3548decf868SDavid S. Miller #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 3558decf868SDavid S. Miller ETH_MAX_AGGREGATION_QUEUES_E1 :\ 3568decf868SDavid S. Miller ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 3578decf868SDavid S. Miller #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 3588decf868SDavid S. Miller #define FW_PREFETCH_CNT 16 3598decf868SDavid S. Miller #define DROPLESS_FC_HEADROOM 100 360adfc5217SJeff Kirsher 361adfc5217SJeff Kirsher /* MC hsi */ 362adfc5217SJeff Kirsher #define BCM_PAGE_SHIFT 12 363adfc5217SJeff Kirsher #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 364adfc5217SJeff Kirsher #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 365adfc5217SJeff Kirsher #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 366adfc5217SJeff Kirsher 367adfc5217SJeff Kirsher #define PAGES_PER_SGE_SHIFT 0 368adfc5217SJeff Kirsher #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 369adfc5217SJeff Kirsher #define SGE_PAGE_SIZE PAGE_SIZE 370adfc5217SJeff Kirsher #define SGE_PAGE_SHIFT PAGE_SHIFT 371adfc5217SJeff Kirsher #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 3728d9ac297SAriel Elior #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 3738d9ac297SAriel Elior #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 3748d9ac297SAriel Elior SGE_PAGES), 0xffff) 375adfc5217SJeff Kirsher 376adfc5217SJeff Kirsher /* SGE ring related macros */ 377adfc5217SJeff Kirsher #define NUM_RX_SGE_PAGES 2 378adfc5217SJeff Kirsher #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 3798decf868SDavid S. Miller #define NEXT_PAGE_SGE_DESC_CNT 2 3808decf868SDavid S. Miller #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 381adfc5217SJeff Kirsher /* RX_SGE_CNT is promised to be a power of 2 */ 382adfc5217SJeff Kirsher #define RX_SGE_MASK (RX_SGE_CNT - 1) 383adfc5217SJeff Kirsher #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 384adfc5217SJeff Kirsher #define MAX_RX_SGE (NUM_RX_SGE - 1) 385adfc5217SJeff Kirsher #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 3868decf868SDavid S. Miller (MAX_RX_SGE_CNT - 1)) ? \ 3878decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 3888decf868SDavid S. Miller (x) + 1) 389adfc5217SJeff Kirsher #define RX_SGE(x) ((x) & MAX_RX_SGE) 390adfc5217SJeff Kirsher 3918decf868SDavid S. Miller /* 3928decf868SDavid S. Miller * Number of required SGEs is the sum of two: 3938decf868SDavid S. Miller * 1. Number of possible opened aggregations (next packet for 39416a5fd92SYuval Mintz * these aggregations will probably consume SGE immediately) 3958decf868SDavid S. Miller * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 3968decf868SDavid S. Miller * after placement on BD for new TPA aggregation) 3978decf868SDavid S. Miller * 3988decf868SDavid S. Miller * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 3998decf868SDavid S. Miller */ 4008decf868SDavid S. Miller #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 4018decf868SDavid S. Miller (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 4028decf868SDavid S. Miller #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 4038decf868SDavid S. Miller MAX_RX_SGE_CNT) 4048decf868SDavid S. Miller #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 4058decf868SDavid S. Miller NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 4068decf868SDavid S. Miller #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 4078decf868SDavid S. Miller 408adfc5217SJeff Kirsher /* Manipulate a bit vector defined as an array of u64 */ 409adfc5217SJeff Kirsher 410adfc5217SJeff Kirsher /* Number of bits in one sge_mask array element */ 411adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_SZ 64 412adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_SHIFT 6 413adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 414adfc5217SJeff Kirsher 415adfc5217SJeff Kirsher #define __BIT_VEC64_SET_BIT(el, bit) \ 416adfc5217SJeff Kirsher do { \ 417adfc5217SJeff Kirsher el = ((el) | ((u64)0x1 << (bit))); \ 418adfc5217SJeff Kirsher } while (0) 419adfc5217SJeff Kirsher 420adfc5217SJeff Kirsher #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 421adfc5217SJeff Kirsher do { \ 422adfc5217SJeff Kirsher el = ((el) & (~((u64)0x1 << (bit)))); \ 423adfc5217SJeff Kirsher } while (0) 424adfc5217SJeff Kirsher 425adfc5217SJeff Kirsher #define BIT_VEC64_SET_BIT(vec64, idx) \ 426adfc5217SJeff Kirsher __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 427adfc5217SJeff Kirsher (idx) & BIT_VEC64_ELEM_MASK) 428adfc5217SJeff Kirsher 429adfc5217SJeff Kirsher #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 430adfc5217SJeff Kirsher __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 431adfc5217SJeff Kirsher (idx) & BIT_VEC64_ELEM_MASK) 432adfc5217SJeff Kirsher 433adfc5217SJeff Kirsher #define BIT_VEC64_TEST_BIT(vec64, idx) \ 434adfc5217SJeff Kirsher (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 435adfc5217SJeff Kirsher ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 436adfc5217SJeff Kirsher 437adfc5217SJeff Kirsher /* Creates a bitmask of all ones in less significant bits. 438adfc5217SJeff Kirsher idx - index of the most significant bit in the created mask */ 439adfc5217SJeff Kirsher #define BIT_VEC64_ONES_MASK(idx) \ 440adfc5217SJeff Kirsher (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 441adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 442adfc5217SJeff Kirsher 443adfc5217SJeff Kirsher /*******************************************************/ 444adfc5217SJeff Kirsher 445adfc5217SJeff Kirsher /* Number of u64 elements in SGE mask array */ 446b3637827SDmitry Kravkov #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 447adfc5217SJeff Kirsher #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 448adfc5217SJeff Kirsher #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 449adfc5217SJeff Kirsher 450adfc5217SJeff Kirsher union host_hc_status_block { 451adfc5217SJeff Kirsher /* pointer to fp status block e1x */ 452adfc5217SJeff Kirsher struct host_hc_status_block_e1x *e1x_sb; 453adfc5217SJeff Kirsher /* pointer to fp status block e2 */ 454adfc5217SJeff Kirsher struct host_hc_status_block_e2 *e2_sb; 455adfc5217SJeff Kirsher }; 456adfc5217SJeff Kirsher 457adfc5217SJeff Kirsher struct bnx2x_agg_info { 458adfc5217SJeff Kirsher /* 459e52fcb24SEric Dumazet * First aggregation buffer is a data buffer, the following - are pages. 460e52fcb24SEric Dumazet * We will preallocate the data buffer for each aggregation when 461adfc5217SJeff Kirsher * we open the interface and will replace the BD at the consumer 462adfc5217SJeff Kirsher * with this one when we receive the TPA_START CQE in order to 463adfc5217SJeff Kirsher * keep the Rx BD ring consistent. 464adfc5217SJeff Kirsher */ 465adfc5217SJeff Kirsher struct sw_rx_bd first_buf; 466adfc5217SJeff Kirsher u8 tpa_state; 467adfc5217SJeff Kirsher #define BNX2X_TPA_START 1 468adfc5217SJeff Kirsher #define BNX2X_TPA_STOP 2 469adfc5217SJeff Kirsher #define BNX2X_TPA_ERROR 3 470adfc5217SJeff Kirsher u8 placement_offset; 471adfc5217SJeff Kirsher u16 parsing_flags; 472adfc5217SJeff Kirsher u16 vlan_tag; 473adfc5217SJeff Kirsher u16 len_on_bd; 474e52fcb24SEric Dumazet u32 rxhash; 475a334b5fbSEric Dumazet bool l4_rxhash; 476621b4d66SDmitry Kravkov u16 gro_size; 477621b4d66SDmitry Kravkov u16 full_page; 478adfc5217SJeff Kirsher }; 479adfc5217SJeff Kirsher 480adfc5217SJeff Kirsher #define Q_STATS_OFFSET32(stat_name) \ 481adfc5217SJeff Kirsher (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 482adfc5217SJeff Kirsher 483adfc5217SJeff Kirsher struct bnx2x_fp_txdata { 484adfc5217SJeff Kirsher 485adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf_ring; 486adfc5217SJeff Kirsher 487adfc5217SJeff Kirsher union eth_tx_bd_types *tx_desc_ring; 488adfc5217SJeff Kirsher dma_addr_t tx_desc_mapping; 489adfc5217SJeff Kirsher 490adfc5217SJeff Kirsher u32 cid; 491adfc5217SJeff Kirsher 492adfc5217SJeff Kirsher union db_prod tx_db; 493adfc5217SJeff Kirsher 494adfc5217SJeff Kirsher u16 tx_pkt_prod; 495adfc5217SJeff Kirsher u16 tx_pkt_cons; 496adfc5217SJeff Kirsher u16 tx_bd_prod; 497adfc5217SJeff Kirsher u16 tx_bd_cons; 498adfc5217SJeff Kirsher 499adfc5217SJeff Kirsher unsigned long tx_pkt; 500adfc5217SJeff Kirsher 501adfc5217SJeff Kirsher __le16 *tx_cons_sb; 502adfc5217SJeff Kirsher 503adfc5217SJeff Kirsher int txq_index; 50465565884SMerav Sicron struct bnx2x_fastpath *parent_fp; 50565565884SMerav Sicron int tx_ring_size; 506adfc5217SJeff Kirsher }; 507adfc5217SJeff Kirsher 508621b4d66SDmitry Kravkov enum bnx2x_tpa_mode_t { 509621b4d66SDmitry Kravkov TPA_MODE_LRO, 510621b4d66SDmitry Kravkov TPA_MODE_GRO 511621b4d66SDmitry Kravkov }; 512621b4d66SDmitry Kravkov 513adfc5217SJeff Kirsher struct bnx2x_fastpath { 514adfc5217SJeff Kirsher struct bnx2x *bp; /* parent */ 515adfc5217SJeff Kirsher 516adfc5217SJeff Kirsher struct napi_struct napi; 5178f20aa57SDmitry Kravkov 518e0d1095aSCong Wang #ifdef CONFIG_NET_RX_BUSY_POLL 5198f20aa57SDmitry Kravkov unsigned int state; 5208f20aa57SDmitry Kravkov #define BNX2X_FP_STATE_IDLE 0 5218f20aa57SDmitry Kravkov #define BNX2X_FP_STATE_NAPI (1 << 0) /* NAPI owns this FP */ 5228f20aa57SDmitry Kravkov #define BNX2X_FP_STATE_POLL (1 << 1) /* poll owns this FP */ 5238f20aa57SDmitry Kravkov #define BNX2X_FP_STATE_NAPI_YIELD (1 << 2) /* NAPI yielded this FP */ 5248f20aa57SDmitry Kravkov #define BNX2X_FP_STATE_POLL_YIELD (1 << 3) /* poll yielded this FP */ 5258f20aa57SDmitry Kravkov #define BNX2X_FP_YIELD (BNX2X_FP_STATE_NAPI_YIELD | BNX2X_FP_STATE_POLL_YIELD) 5268f20aa57SDmitry Kravkov #define BNX2X_FP_LOCKED (BNX2X_FP_STATE_NAPI | BNX2X_FP_STATE_POLL) 5278f20aa57SDmitry Kravkov #define BNX2X_FP_USER_PEND (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_POLL_YIELD) 5288f20aa57SDmitry Kravkov /* protect state */ 5298f20aa57SDmitry Kravkov spinlock_t lock; 530e0d1095aSCong Wang #endif /* CONFIG_NET_RX_BUSY_POLL */ 5318f20aa57SDmitry Kravkov 532adfc5217SJeff Kirsher union host_hc_status_block status_blk; 53316a5fd92SYuval Mintz /* chip independent shortcuts into sb structure */ 534adfc5217SJeff Kirsher __le16 *sb_index_values; 535adfc5217SJeff Kirsher __le16 *sb_running_index; 53616a5fd92SYuval Mintz /* chip independent shortcut into rx_prods_offset memory */ 537adfc5217SJeff Kirsher u32 ustorm_rx_prods_offset; 538adfc5217SJeff Kirsher 539adfc5217SJeff Kirsher u32 rx_buf_size; 540d46d132cSEric Dumazet u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 541adfc5217SJeff Kirsher dma_addr_t status_blk_mapping; 542adfc5217SJeff Kirsher 543621b4d66SDmitry Kravkov enum bnx2x_tpa_mode_t mode; 544621b4d66SDmitry Kravkov 545adfc5217SJeff Kirsher u8 max_cos; /* actual number of active tx coses */ 54665565884SMerav Sicron struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 547adfc5217SJeff Kirsher 548adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 549adfc5217SJeff Kirsher struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 550adfc5217SJeff Kirsher 551adfc5217SJeff Kirsher struct eth_rx_bd *rx_desc_ring; 552adfc5217SJeff Kirsher dma_addr_t rx_desc_mapping; 553adfc5217SJeff Kirsher 554adfc5217SJeff Kirsher union eth_rx_cqe *rx_comp_ring; 555adfc5217SJeff Kirsher dma_addr_t rx_comp_mapping; 556adfc5217SJeff Kirsher 557adfc5217SJeff Kirsher /* SGE ring */ 558adfc5217SJeff Kirsher struct eth_rx_sge *rx_sge_ring; 559adfc5217SJeff Kirsher dma_addr_t rx_sge_mapping; 560adfc5217SJeff Kirsher 561adfc5217SJeff Kirsher u64 sge_mask[RX_SGE_MASK_LEN]; 562adfc5217SJeff Kirsher 563adfc5217SJeff Kirsher u32 cid; 564adfc5217SJeff Kirsher 565adfc5217SJeff Kirsher __le16 fp_hc_idx; 566adfc5217SJeff Kirsher 567adfc5217SJeff Kirsher u8 index; /* number in fp array */ 568f233cafeSDmitry Kravkov u8 rx_queue; /* index for skb_record */ 569adfc5217SJeff Kirsher u8 cl_id; /* eth client id */ 570adfc5217SJeff Kirsher u8 cl_qzone_id; 571adfc5217SJeff Kirsher u8 fw_sb_id; /* status block number in FW */ 572adfc5217SJeff Kirsher u8 igu_sb_id; /* status block number in HW */ 573adfc5217SJeff Kirsher 574adfc5217SJeff Kirsher u16 rx_bd_prod; 575adfc5217SJeff Kirsher u16 rx_bd_cons; 576adfc5217SJeff Kirsher u16 rx_comp_prod; 577adfc5217SJeff Kirsher u16 rx_comp_cons; 578adfc5217SJeff Kirsher u16 rx_sge_prod; 579adfc5217SJeff Kirsher /* The last maximal completed SGE */ 580adfc5217SJeff Kirsher u16 last_max_sge; 581adfc5217SJeff Kirsher __le16 *rx_cons_sb; 582adfc5217SJeff Kirsher unsigned long rx_pkt, 583adfc5217SJeff Kirsher rx_calls; 584adfc5217SJeff Kirsher 585adfc5217SJeff Kirsher /* TPA related */ 58615192a8cSBarak Witkowski struct bnx2x_agg_info *tpa_info; 587adfc5217SJeff Kirsher u8 disable_tpa; 588adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 589adfc5217SJeff Kirsher u64 tpa_queue_used; 590adfc5217SJeff Kirsher #endif 591adfc5217SJeff Kirsher /* The size is calculated using the following: 592adfc5217SJeff Kirsher sizeof name field from netdev structure + 593adfc5217SJeff Kirsher 4 ('-Xx-' string) + 594adfc5217SJeff Kirsher 4 (for the digits and to make it DWORD aligned) */ 595adfc5217SJeff Kirsher #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 596adfc5217SJeff Kirsher char name[FP_NAME_SIZE]; 597adfc5217SJeff Kirsher }; 598adfc5217SJeff Kirsher 59915192a8cSBarak Witkowski #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 60015192a8cSBarak Witkowski #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 60115192a8cSBarak Witkowski #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 60215192a8cSBarak Witkowski #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 603adfc5217SJeff Kirsher 604e0d1095aSCong Wang #ifdef CONFIG_NET_RX_BUSY_POLL 6058f20aa57SDmitry Kravkov static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp) 6068f20aa57SDmitry Kravkov { 6078f20aa57SDmitry Kravkov spin_lock_init(&fp->lock); 6088f20aa57SDmitry Kravkov fp->state = BNX2X_FP_STATE_IDLE; 6098f20aa57SDmitry Kravkov } 6108f20aa57SDmitry Kravkov 6118f20aa57SDmitry Kravkov /* called from the device poll routine to get ownership of a FP */ 6128f20aa57SDmitry Kravkov static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 6138f20aa57SDmitry Kravkov { 6148f20aa57SDmitry Kravkov bool rc = true; 6158f20aa57SDmitry Kravkov 6168f20aa57SDmitry Kravkov spin_lock(&fp->lock); 6178f20aa57SDmitry Kravkov if (fp->state & BNX2X_FP_LOCKED) { 6188f20aa57SDmitry Kravkov WARN_ON(fp->state & BNX2X_FP_STATE_NAPI); 6198f20aa57SDmitry Kravkov fp->state |= BNX2X_FP_STATE_NAPI_YIELD; 6208f20aa57SDmitry Kravkov rc = false; 6218f20aa57SDmitry Kravkov } else { 6228f20aa57SDmitry Kravkov /* we don't care if someone yielded */ 6238f20aa57SDmitry Kravkov fp->state = BNX2X_FP_STATE_NAPI; 6248f20aa57SDmitry Kravkov } 6258f20aa57SDmitry Kravkov spin_unlock(&fp->lock); 6268f20aa57SDmitry Kravkov return rc; 6278f20aa57SDmitry Kravkov } 6288f20aa57SDmitry Kravkov 6298f20aa57SDmitry Kravkov /* returns true is someone tried to get the FP while napi had it */ 6308f20aa57SDmitry Kravkov static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 6318f20aa57SDmitry Kravkov { 6328f20aa57SDmitry Kravkov bool rc = false; 6338f20aa57SDmitry Kravkov 6348f20aa57SDmitry Kravkov spin_lock(&fp->lock); 6358f20aa57SDmitry Kravkov WARN_ON(fp->state & 6368f20aa57SDmitry Kravkov (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_NAPI_YIELD)); 6378f20aa57SDmitry Kravkov 6388f20aa57SDmitry Kravkov if (fp->state & BNX2X_FP_STATE_POLL_YIELD) 6398f20aa57SDmitry Kravkov rc = true; 6408f20aa57SDmitry Kravkov fp->state = BNX2X_FP_STATE_IDLE; 6418f20aa57SDmitry Kravkov spin_unlock(&fp->lock); 6428f20aa57SDmitry Kravkov return rc; 6438f20aa57SDmitry Kravkov } 6448f20aa57SDmitry Kravkov 6458f20aa57SDmitry Kravkov /* called from bnx2x_low_latency_poll() */ 6468f20aa57SDmitry Kravkov static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 6478f20aa57SDmitry Kravkov { 6488f20aa57SDmitry Kravkov bool rc = true; 6498f20aa57SDmitry Kravkov 6508f20aa57SDmitry Kravkov spin_lock_bh(&fp->lock); 6518f20aa57SDmitry Kravkov if ((fp->state & BNX2X_FP_LOCKED)) { 6528f20aa57SDmitry Kravkov fp->state |= BNX2X_FP_STATE_POLL_YIELD; 6538f20aa57SDmitry Kravkov rc = false; 6548f20aa57SDmitry Kravkov } else { 6558f20aa57SDmitry Kravkov /* preserve yield marks */ 6568f20aa57SDmitry Kravkov fp->state |= BNX2X_FP_STATE_POLL; 6578f20aa57SDmitry Kravkov } 6588f20aa57SDmitry Kravkov spin_unlock_bh(&fp->lock); 6598f20aa57SDmitry Kravkov return rc; 6608f20aa57SDmitry Kravkov } 6618f20aa57SDmitry Kravkov 6628f20aa57SDmitry Kravkov /* returns true if someone tried to get the FP while it was locked */ 6638f20aa57SDmitry Kravkov static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 6648f20aa57SDmitry Kravkov { 6658f20aa57SDmitry Kravkov bool rc = false; 6668f20aa57SDmitry Kravkov 6678f20aa57SDmitry Kravkov spin_lock_bh(&fp->lock); 6688f20aa57SDmitry Kravkov WARN_ON(fp->state & BNX2X_FP_STATE_NAPI); 6698f20aa57SDmitry Kravkov 6708f20aa57SDmitry Kravkov if (fp->state & BNX2X_FP_STATE_POLL_YIELD) 6718f20aa57SDmitry Kravkov rc = true; 6728f20aa57SDmitry Kravkov fp->state = BNX2X_FP_STATE_IDLE; 6738f20aa57SDmitry Kravkov spin_unlock_bh(&fp->lock); 6748f20aa57SDmitry Kravkov return rc; 6758f20aa57SDmitry Kravkov } 6768f20aa57SDmitry Kravkov 6778f20aa57SDmitry Kravkov /* true if a socket is polling, even if it did not get the lock */ 6788f20aa57SDmitry Kravkov static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 6798f20aa57SDmitry Kravkov { 6808f20aa57SDmitry Kravkov WARN_ON(!(fp->state & BNX2X_FP_LOCKED)); 6818f20aa57SDmitry Kravkov return fp->state & BNX2X_FP_USER_PEND; 6828f20aa57SDmitry Kravkov } 6838f20aa57SDmitry Kravkov #else 6848f20aa57SDmitry Kravkov static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp) 6858f20aa57SDmitry Kravkov { 6868f20aa57SDmitry Kravkov } 6878f20aa57SDmitry Kravkov 6888f20aa57SDmitry Kravkov static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 6898f20aa57SDmitry Kravkov { 6908f20aa57SDmitry Kravkov return true; 6918f20aa57SDmitry Kravkov } 6928f20aa57SDmitry Kravkov 6938f20aa57SDmitry Kravkov static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 6948f20aa57SDmitry Kravkov { 6958f20aa57SDmitry Kravkov return false; 6968f20aa57SDmitry Kravkov } 6978f20aa57SDmitry Kravkov 6988f20aa57SDmitry Kravkov static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 6998f20aa57SDmitry Kravkov { 7008f20aa57SDmitry Kravkov return false; 7018f20aa57SDmitry Kravkov } 7028f20aa57SDmitry Kravkov 7038f20aa57SDmitry Kravkov static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 7048f20aa57SDmitry Kravkov { 7058f20aa57SDmitry Kravkov return false; 7068f20aa57SDmitry Kravkov } 7078f20aa57SDmitry Kravkov 7088f20aa57SDmitry Kravkov static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 7098f20aa57SDmitry Kravkov { 7108f20aa57SDmitry Kravkov return false; 7118f20aa57SDmitry Kravkov } 712e0d1095aSCong Wang #endif /* CONFIG_NET_RX_BUSY_POLL */ 7138f20aa57SDmitry Kravkov 714adfc5217SJeff Kirsher /* Use 2500 as a mini-jumbo MTU for FCoE */ 715adfc5217SJeff Kirsher #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 716adfc5217SJeff Kirsher 71765565884SMerav Sicron #define FCOE_IDX_OFFSET 0 71865565884SMerav Sicron 71965565884SMerav Sicron #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 72065565884SMerav Sicron FCOE_IDX_OFFSET) 72165565884SMerav Sicron #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 722adfc5217SJeff Kirsher #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 72315192a8cSBarak Witkowski #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 72415192a8cSBarak Witkowski #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 725adfc5217SJeff Kirsher #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 72665565884SMerav Sicron txdata_ptr[FIRST_TX_COS_INDEX] \ 72765565884SMerav Sicron ->var) 728adfc5217SJeff Kirsher 72955c11941SMerav Sicron #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 73055c11941SMerav Sicron #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 73165565884SMerav Sicron #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 732adfc5217SJeff Kirsher 733adfc5217SJeff Kirsher /* MC hsi */ 734adfc5217SJeff Kirsher #define MAX_FETCH_BD 13 /* HW max BDs per packet */ 735adfc5217SJeff Kirsher #define RX_COPY_THRESH 92 736adfc5217SJeff Kirsher 737adfc5217SJeff Kirsher #define NUM_TX_RINGS 16 738adfc5217SJeff Kirsher #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 7398decf868SDavid S. Miller #define NEXT_PAGE_TX_DESC_CNT 1 7408decf868SDavid S. Miller #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 741adfc5217SJeff Kirsher #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 742adfc5217SJeff Kirsher #define MAX_TX_BD (NUM_TX_BD - 1) 743adfc5217SJeff Kirsher #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 744adfc5217SJeff Kirsher #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 7458decf868SDavid S. Miller (MAX_TX_DESC_CNT - 1)) ? \ 7468decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 7478decf868SDavid S. Miller (x) + 1) 748adfc5217SJeff Kirsher #define TX_BD(x) ((x) & MAX_TX_BD) 749adfc5217SJeff Kirsher #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 750adfc5217SJeff Kirsher 7517df2dc6bSDmitry Kravkov /* number of NEXT_PAGE descriptors may be required during placement */ 7527df2dc6bSDmitry Kravkov #define NEXT_CNT_PER_TX_PKT(bds) \ 7537df2dc6bSDmitry Kravkov (((bds) + MAX_TX_DESC_CNT - 1) / \ 7547df2dc6bSDmitry Kravkov MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 7557df2dc6bSDmitry Kravkov /* max BDs per tx packet w/o next_pages: 7567df2dc6bSDmitry Kravkov * START_BD - describes packed 7577df2dc6bSDmitry Kravkov * START_BD(splitted) - includes unpaged data segment for GSO 7587df2dc6bSDmitry Kravkov * PARSING_BD - for TSO and CSUM data 759a848ade4SDmitry Kravkov * PARSING_BD2 - for encapsulation data 76016a5fd92SYuval Mintz * Frag BDs - describes pages for frags 7617df2dc6bSDmitry Kravkov */ 762a848ade4SDmitry Kravkov #define BDS_PER_TX_PKT 4 7637df2dc6bSDmitry Kravkov #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 7647df2dc6bSDmitry Kravkov /* max BDs per tx packet including next pages */ 7657df2dc6bSDmitry Kravkov #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 7667df2dc6bSDmitry Kravkov NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 7677df2dc6bSDmitry Kravkov 768adfc5217SJeff Kirsher /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 769adfc5217SJeff Kirsher #define NUM_RX_RINGS 8 770adfc5217SJeff Kirsher #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 7718decf868SDavid S. Miller #define NEXT_PAGE_RX_DESC_CNT 2 7728decf868SDavid S. Miller #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 773adfc5217SJeff Kirsher #define RX_DESC_MASK (RX_DESC_CNT - 1) 774adfc5217SJeff Kirsher #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 775adfc5217SJeff Kirsher #define MAX_RX_BD (NUM_RX_BD - 1) 776adfc5217SJeff Kirsher #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 7778decf868SDavid S. Miller 7788decf868SDavid S. Miller /* dropless fc calculations for BDs 7798decf868SDavid S. Miller * 7808decf868SDavid S. Miller * Number of BDs should as number of buffers in BRB: 7818decf868SDavid S. Miller * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 7828decf868SDavid S. Miller * "next" elements on each page 7838decf868SDavid S. Miller */ 7848decf868SDavid S. Miller #define NUM_BD_REQ BRB_SIZE(bp) 7858decf868SDavid S. Miller #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 7868decf868SDavid S. Miller MAX_RX_DESC_CNT) 7878decf868SDavid S. Miller #define BD_TH_LO(bp) (NUM_BD_REQ + \ 7888decf868SDavid S. Miller NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 7898decf868SDavid S. Miller FW_DROP_LEVEL(bp)) 7908decf868SDavid S. Miller #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 7918decf868SDavid S. Miller 7928decf868SDavid S. Miller #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 793adfc5217SJeff Kirsher 794adfc5217SJeff Kirsher #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 795adfc5217SJeff Kirsher ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 796adfc5217SJeff Kirsher ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 797adfc5217SJeff Kirsher #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 798adfc5217SJeff Kirsher #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 799adfc5217SJeff Kirsher #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 800adfc5217SJeff Kirsher MIN_RX_AVAIL)) 801adfc5217SJeff Kirsher 802adfc5217SJeff Kirsher #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 8038decf868SDavid S. Miller (MAX_RX_DESC_CNT - 1)) ? \ 8048decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 8058decf868SDavid S. Miller (x) + 1) 806adfc5217SJeff Kirsher #define RX_BD(x) ((x) & MAX_RX_BD) 807adfc5217SJeff Kirsher 808adfc5217SJeff Kirsher /* 809adfc5217SJeff Kirsher * As long as CQE is X times bigger than BD entry we have to allocate X times 810adfc5217SJeff Kirsher * more pages for CQ ring in order to keep it balanced with BD ring 811adfc5217SJeff Kirsher */ 812adfc5217SJeff Kirsher #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 813adfc5217SJeff Kirsher #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 814adfc5217SJeff Kirsher #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 8158decf868SDavid S. Miller #define NEXT_PAGE_RCQ_DESC_CNT 1 8168decf868SDavid S. Miller #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 817adfc5217SJeff Kirsher #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 818adfc5217SJeff Kirsher #define MAX_RCQ_BD (NUM_RCQ_BD - 1) 819adfc5217SJeff Kirsher #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 820adfc5217SJeff Kirsher #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 8218decf868SDavid S. Miller (MAX_RCQ_DESC_CNT - 1)) ? \ 8228decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 8238decf868SDavid S. Miller (x) + 1) 824adfc5217SJeff Kirsher #define RCQ_BD(x) ((x) & MAX_RCQ_BD) 825adfc5217SJeff Kirsher 8268decf868SDavid S. Miller /* dropless fc calculations for RCQs 8278decf868SDavid S. Miller * 8288decf868SDavid S. Miller * Number of RCQs should be as number of buffers in BRB: 8298decf868SDavid S. Miller * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 8308decf868SDavid S. Miller * "next" elements on each page 8318decf868SDavid S. Miller */ 8328decf868SDavid S. Miller #define NUM_RCQ_REQ BRB_SIZE(bp) 8338decf868SDavid S. Miller #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 8348decf868SDavid S. Miller MAX_RCQ_DESC_CNT) 8358decf868SDavid S. Miller #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 8368decf868SDavid S. Miller NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 8378decf868SDavid S. Miller FW_DROP_LEVEL(bp)) 8388decf868SDavid S. Miller #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 8398decf868SDavid S. Miller 840adfc5217SJeff Kirsher /* This is needed for determining of last_max */ 841adfc5217SJeff Kirsher #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 842adfc5217SJeff Kirsher #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 843adfc5217SJeff Kirsher 844adfc5217SJeff Kirsher #define BNX2X_SWCID_SHIFT 17 845adfc5217SJeff Kirsher #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 846adfc5217SJeff Kirsher 847adfc5217SJeff Kirsher /* used on a CID received from the HW */ 848adfc5217SJeff Kirsher #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 849adfc5217SJeff Kirsher #define CQE_CMD(x) (le32_to_cpu(x) >> \ 850adfc5217SJeff Kirsher COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 851adfc5217SJeff Kirsher 852adfc5217SJeff Kirsher #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 853adfc5217SJeff Kirsher le32_to_cpu((bd)->addr_lo)) 854adfc5217SJeff Kirsher #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 855adfc5217SJeff Kirsher 856adfc5217SJeff Kirsher #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 857b9871bcfSAriel Elior #define BNX2X_DB_SHIFT 3 /* 8 bytes*/ 858adfc5217SJeff Kirsher #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 859adfc5217SJeff Kirsher #error "Min DB doorbell stride is 8" 860adfc5217SJeff Kirsher #endif 861adfc5217SJeff Kirsher #define DOORBELL(bp, cid, val) \ 862adfc5217SJeff Kirsher do { \ 863b9871bcfSAriel Elior writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \ 864adfc5217SJeff Kirsher } while (0) 865adfc5217SJeff Kirsher 866adfc5217SJeff Kirsher /* TX CSUM helpers */ 867adfc5217SJeff Kirsher #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 868adfc5217SJeff Kirsher skb->csum_offset) 869adfc5217SJeff Kirsher #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 870adfc5217SJeff Kirsher skb->csum_offset)) 871adfc5217SJeff Kirsher 87291226790SDmitry Kravkov #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) 873adfc5217SJeff Kirsher 874adfc5217SJeff Kirsher #define XMIT_PLAIN 0 875a848ade4SDmitry Kravkov #define XMIT_CSUM_V4 (1 << 0) 876a848ade4SDmitry Kravkov #define XMIT_CSUM_V6 (1 << 1) 877a848ade4SDmitry Kravkov #define XMIT_CSUM_TCP (1 << 2) 878a848ade4SDmitry Kravkov #define XMIT_GSO_V4 (1 << 3) 879a848ade4SDmitry Kravkov #define XMIT_GSO_V6 (1 << 4) 880a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC_V4 (1 << 5) 881a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC_V6 (1 << 6) 882a848ade4SDmitry Kravkov #define XMIT_GSO_ENC_V4 (1 << 7) 883a848ade4SDmitry Kravkov #define XMIT_GSO_ENC_V6 (1 << 8) 884adfc5217SJeff Kirsher 885a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) 886a848ade4SDmitry Kravkov #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) 887adfc5217SJeff Kirsher 888a848ade4SDmitry Kravkov #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) 889a848ade4SDmitry Kravkov #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) 890adfc5217SJeff Kirsher 891adfc5217SJeff Kirsher /* stuff added to make the code fit 80Col */ 892adfc5217SJeff Kirsher #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 893adfc5217SJeff Kirsher #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 894adfc5217SJeff Kirsher #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 895adfc5217SJeff Kirsher #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 896adfc5217SJeff Kirsher #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 897adfc5217SJeff Kirsher 898adfc5217SJeff Kirsher #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 899adfc5217SJeff Kirsher 900adfc5217SJeff Kirsher #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 901adfc5217SJeff Kirsher (((le16_to_cpu(flags) & \ 902adfc5217SJeff Kirsher PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 903adfc5217SJeff Kirsher PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 904adfc5217SJeff Kirsher == PRS_FLAG_OVERETH_IPV4) 905adfc5217SJeff Kirsher #define BNX2X_RX_SUM_FIX(cqe) \ 906adfc5217SJeff Kirsher BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 907adfc5217SJeff Kirsher 908adfc5217SJeff Kirsher #define FP_USB_FUNC_OFF \ 909adfc5217SJeff Kirsher offsetof(struct cstorm_status_block_u, func) 910adfc5217SJeff Kirsher #define FP_CSB_FUNC_OFF \ 911adfc5217SJeff Kirsher offsetof(struct cstorm_status_block_c, func) 912adfc5217SJeff Kirsher 9138decf868SDavid S. Miller #define HC_INDEX_ETH_RX_CQ_CONS 1 914adfc5217SJeff Kirsher 9158decf868SDavid S. Miller #define HC_INDEX_OOO_TX_CQ_CONS 4 9168decf868SDavid S. Miller 9178decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 9188decf868SDavid S. Miller 9198decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 9208decf868SDavid S. Miller 9218decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 922adfc5217SJeff Kirsher 923adfc5217SJeff Kirsher #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 924adfc5217SJeff Kirsher 925adfc5217SJeff Kirsher #define BNX2X_RX_SB_INDEX \ 926adfc5217SJeff Kirsher (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 927adfc5217SJeff Kirsher 928adfc5217SJeff Kirsher #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 929adfc5217SJeff Kirsher 930adfc5217SJeff Kirsher #define BNX2X_TX_SB_INDEX_COS0 \ 931adfc5217SJeff Kirsher (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 932adfc5217SJeff Kirsher 933adfc5217SJeff Kirsher /* end of fast path */ 934adfc5217SJeff Kirsher 935adfc5217SJeff Kirsher /* common */ 936adfc5217SJeff Kirsher 937adfc5217SJeff Kirsher struct bnx2x_common { 938adfc5217SJeff Kirsher 939adfc5217SJeff Kirsher u32 chip_id; 940adfc5217SJeff Kirsher /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 941adfc5217SJeff Kirsher #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 942adfc5217SJeff Kirsher 943adfc5217SJeff Kirsher #define CHIP_NUM(bp) (bp->common.chip_id >> 16) 944adfc5217SJeff Kirsher #define CHIP_NUM_57710 0x164e 945adfc5217SJeff Kirsher #define CHIP_NUM_57711 0x164f 946adfc5217SJeff Kirsher #define CHIP_NUM_57711E 0x1650 947adfc5217SJeff Kirsher #define CHIP_NUM_57712 0x1662 948adfc5217SJeff Kirsher #define CHIP_NUM_57712_MF 0x1663 9498395be5eSAriel Elior #define CHIP_NUM_57712_VF 0x166f 950adfc5217SJeff Kirsher #define CHIP_NUM_57713 0x1651 951adfc5217SJeff Kirsher #define CHIP_NUM_57713E 0x1652 952adfc5217SJeff Kirsher #define CHIP_NUM_57800 0x168a 953adfc5217SJeff Kirsher #define CHIP_NUM_57800_MF 0x16a5 9548395be5eSAriel Elior #define CHIP_NUM_57800_VF 0x16a9 955adfc5217SJeff Kirsher #define CHIP_NUM_57810 0x168e 956adfc5217SJeff Kirsher #define CHIP_NUM_57810_MF 0x16ae 9578395be5eSAriel Elior #define CHIP_NUM_57810_VF 0x16af 9587e8e02dfSBarak Witkowski #define CHIP_NUM_57811 0x163d 9597e8e02dfSBarak Witkowski #define CHIP_NUM_57811_MF 0x163e 9608395be5eSAriel Elior #define CHIP_NUM_57811_VF 0x163f 961c3def943SYuval Mintz #define CHIP_NUM_57840_OBSOLETE 0x168d 962c3def943SYuval Mintz #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 963c3def943SYuval Mintz #define CHIP_NUM_57840_4_10 0x16a1 964c3def943SYuval Mintz #define CHIP_NUM_57840_2_20 0x16a2 965c3def943SYuval Mintz #define CHIP_NUM_57840_MF 0x16a4 9668395be5eSAriel Elior #define CHIP_NUM_57840_VF 0x16ad 967adfc5217SJeff Kirsher #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 968adfc5217SJeff Kirsher #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 969adfc5217SJeff Kirsher #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 970adfc5217SJeff Kirsher #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 9718395be5eSAriel Elior #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 972adfc5217SJeff Kirsher #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 973adfc5217SJeff Kirsher #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 974adfc5217SJeff Kirsher #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 9758395be5eSAriel Elior #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 976adfc5217SJeff Kirsher #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 977adfc5217SJeff Kirsher #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 9788395be5eSAriel Elior #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 9797e8e02dfSBarak Witkowski #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 9807e8e02dfSBarak Witkowski #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 9818395be5eSAriel Elior #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 982c3def943SYuval Mintz #define CHIP_IS_57840(bp) \ 983c3def943SYuval Mintz ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 984c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 985c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 986c3def943SYuval Mintz #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 987c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 9888395be5eSAriel Elior #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 989adfc5217SJeff Kirsher #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 990adfc5217SJeff Kirsher CHIP_IS_57711E(bp)) 991edb944d2SDmitry Kravkov #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ 992edb944d2SDmitry Kravkov CHIP_IS_57811_MF(bp) || \ 993edb944d2SDmitry Kravkov CHIP_IS_57811_VF(bp)) 994adfc5217SJeff Kirsher #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 9956ab20355SYuval Mintz CHIP_IS_57712_MF(bp) || \ 9966ab20355SYuval Mintz CHIP_IS_57712_VF(bp)) 997adfc5217SJeff Kirsher #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 998adfc5217SJeff Kirsher CHIP_IS_57800_MF(bp) || \ 9996ab20355SYuval Mintz CHIP_IS_57800_VF(bp) || \ 1000adfc5217SJeff Kirsher CHIP_IS_57810(bp) || \ 1001adfc5217SJeff Kirsher CHIP_IS_57810_MF(bp) || \ 10028395be5eSAriel Elior CHIP_IS_57810_VF(bp) || \ 1003edb944d2SDmitry Kravkov CHIP_IS_57811xx(bp) || \ 1004adfc5217SJeff Kirsher CHIP_IS_57840(bp) || \ 10058395be5eSAriel Elior CHIP_IS_57840_MF(bp) || \ 10068395be5eSAriel Elior CHIP_IS_57840_VF(bp)) 1007adfc5217SJeff Kirsher #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 1008adfc5217SJeff Kirsher #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 1009adfc5217SJeff Kirsher #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 1010adfc5217SJeff Kirsher 1011adfc5217SJeff Kirsher #define CHIP_REV_SHIFT 12 1012adfc5217SJeff Kirsher #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1013adfc5217SJeff Kirsher #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 1014adfc5217SJeff Kirsher #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1015adfc5217SJeff Kirsher #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1016adfc5217SJeff Kirsher /* assume maximum 5 revisions */ 1017adfc5217SJeff Kirsher #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 1018adfc5217SJeff Kirsher /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 1019adfc5217SJeff Kirsher #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1020adfc5217SJeff Kirsher !(CHIP_REV_VAL(bp) & 0x00001000)) 1021adfc5217SJeff Kirsher /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 1022adfc5217SJeff Kirsher #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1023adfc5217SJeff Kirsher (CHIP_REV_VAL(bp) & 0x00001000)) 1024adfc5217SJeff Kirsher 1025adfc5217SJeff Kirsher #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 1026adfc5217SJeff Kirsher ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 1027adfc5217SJeff Kirsher 1028adfc5217SJeff Kirsher #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 1029adfc5217SJeff Kirsher #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 1030adfc5217SJeff Kirsher #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 1031adfc5217SJeff Kirsher (CHIP_REV_SHIFT + 1)) \ 1032adfc5217SJeff Kirsher << CHIP_REV_SHIFT) 1033adfc5217SJeff Kirsher #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 1034adfc5217SJeff Kirsher CHIP_REV_SIM(bp) :\ 1035adfc5217SJeff Kirsher CHIP_REV_VAL(bp)) 1036adfc5217SJeff Kirsher #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 1037adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Bx)) 1038adfc5217SJeff Kirsher #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 1039adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Ax)) 104055c11941SMerav Sicron /* This define is used in two main places: 104116a5fd92SYuval Mintz * 1. In the early stages of nic_load, to know if to configure Parser / Searcher 104255c11941SMerav Sicron * to nic-only mode or to offload mode. Offload mode is configured if either the 104355c11941SMerav Sicron * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 104455c11941SMerav Sicron * registered for this port (which means that the user wants storage services). 104555c11941SMerav Sicron * 2. During cnic-related load, to know if offload mode is already configured in 104616a5fd92SYuval Mintz * the HW or needs to be configured. 104755c11941SMerav Sicron * Since the transition from nic-mode to offload-mode in HW causes traffic 104816a5fd92SYuval Mintz * corruption, nic-mode is configured only in ports on which storage services 104955c11941SMerav Sicron * where never requested. 105055c11941SMerav Sicron */ 105155c11941SMerav Sicron #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 1052adfc5217SJeff Kirsher 1053adfc5217SJeff Kirsher int flash_size; 1054adfc5217SJeff Kirsher #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 1055adfc5217SJeff Kirsher #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 1056adfc5217SJeff Kirsher #define BNX2X_NVRAM_PAGE_SIZE 256 1057adfc5217SJeff Kirsher 1058adfc5217SJeff Kirsher u32 shmem_base; 1059adfc5217SJeff Kirsher u32 shmem2_base; 1060adfc5217SJeff Kirsher u32 mf_cfg_base; 1061adfc5217SJeff Kirsher u32 mf2_cfg_base; 1062adfc5217SJeff Kirsher 1063adfc5217SJeff Kirsher u32 hw_config; 1064adfc5217SJeff Kirsher 1065adfc5217SJeff Kirsher u32 bc_ver; 1066adfc5217SJeff Kirsher 1067adfc5217SJeff Kirsher u8 int_block; 1068adfc5217SJeff Kirsher #define INT_BLOCK_HC 0 1069adfc5217SJeff Kirsher #define INT_BLOCK_IGU 1 1070adfc5217SJeff Kirsher #define INT_BLOCK_MODE_NORMAL 0 1071adfc5217SJeff Kirsher #define INT_BLOCK_MODE_BW_COMP 2 1072adfc5217SJeff Kirsher #define CHIP_INT_MODE_IS_NBC(bp) \ 1073adfc5217SJeff Kirsher (!CHIP_IS_E1x(bp) && \ 1074adfc5217SJeff Kirsher !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 1075adfc5217SJeff Kirsher #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 1076adfc5217SJeff Kirsher 1077adfc5217SJeff Kirsher u8 chip_port_mode; 1078adfc5217SJeff Kirsher #define CHIP_4_PORT_MODE 0x0 1079adfc5217SJeff Kirsher #define CHIP_2_PORT_MODE 0x1 1080adfc5217SJeff Kirsher #define CHIP_PORT_MODE_NONE 0x2 1081adfc5217SJeff Kirsher #define CHIP_MODE(bp) (bp->common.chip_port_mode) 1082adfc5217SJeff Kirsher #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 10831d187b34SBarak Witkowski 10841d187b34SBarak Witkowski u32 boot_mode; 1085adfc5217SJeff Kirsher }; 1086adfc5217SJeff Kirsher 1087adfc5217SJeff Kirsher /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 1088adfc5217SJeff Kirsher #define BNX2X_IGU_STAS_MSG_VF_CNT 64 1089adfc5217SJeff Kirsher #define BNX2X_IGU_STAS_MSG_PF_CNT 4 1090adfc5217SJeff Kirsher 109127c1151cSYaniv Rosner #define MAX_IGU_ATTN_ACK_TO 100 1092adfc5217SJeff Kirsher /* end of common */ 1093adfc5217SJeff Kirsher 1094adfc5217SJeff Kirsher /* port */ 1095adfc5217SJeff Kirsher 1096adfc5217SJeff Kirsher struct bnx2x_port { 1097adfc5217SJeff Kirsher u32 pmf; 1098adfc5217SJeff Kirsher 1099adfc5217SJeff Kirsher u32 link_config[LINK_CONFIG_SIZE]; 1100adfc5217SJeff Kirsher 1101adfc5217SJeff Kirsher u32 supported[LINK_CONFIG_SIZE]; 1102adfc5217SJeff Kirsher /* link settings - missing defines */ 1103adfc5217SJeff Kirsher #define SUPPORTED_2500baseX_Full (1 << 15) 1104adfc5217SJeff Kirsher 1105adfc5217SJeff Kirsher u32 advertising[LINK_CONFIG_SIZE]; 1106adfc5217SJeff Kirsher /* link settings - missing defines */ 1107adfc5217SJeff Kirsher #define ADVERTISED_2500baseX_Full (1 << 15) 1108adfc5217SJeff Kirsher 1109adfc5217SJeff Kirsher u32 phy_addr; 1110adfc5217SJeff Kirsher 1111adfc5217SJeff Kirsher /* used to synchronize phy accesses */ 1112adfc5217SJeff Kirsher struct mutex phy_mutex; 1113adfc5217SJeff Kirsher 1114adfc5217SJeff Kirsher u32 port_stx; 1115adfc5217SJeff Kirsher 1116adfc5217SJeff Kirsher struct nig_stats old_nig_stats; 1117adfc5217SJeff Kirsher }; 1118adfc5217SJeff Kirsher 1119adfc5217SJeff Kirsher /* end of port */ 1120adfc5217SJeff Kirsher 1121adfc5217SJeff Kirsher #define STATS_OFFSET32(stat_name) \ 1122adfc5217SJeff Kirsher (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 1123adfc5217SJeff Kirsher 1124adfc5217SJeff Kirsher /* slow path */ 1125adfc5217SJeff Kirsher 1126adfc5217SJeff Kirsher /* slow path work-queue */ 1127adfc5217SJeff Kirsher extern struct workqueue_struct *bnx2x_wq; 1128adfc5217SJeff Kirsher 1129adfc5217SJeff Kirsher #define BNX2X_MAX_NUM_OF_VFS 64 1130b9871bcfSAriel Elior #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */ 11311ab4434cSAriel Elior #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 1132b9871bcfSAriel Elior 1133b9871bcfSAriel Elior /* We need to reserve doorbell addresses for all VF and queue combinations */ 11341ab4434cSAriel Elior #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 1135b9871bcfSAriel Elior 1136b9871bcfSAriel Elior /* The doorbell is configured to have the same number of CIDs for PFs and for 1137b9871bcfSAriel Elior * VFs. For this reason the PF CID zone is as large as the VF zone. 1138b9871bcfSAriel Elior */ 1139b9871bcfSAriel Elior #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS 1140b9871bcfSAriel Elior #define BNX2X_MAX_NUM_VF_QUEUES 64 1141adfc5217SJeff Kirsher #define BNX2X_VF_ID_INVALID 0xFF 1142adfc5217SJeff Kirsher 1143b9871bcfSAriel Elior /* the number of VF CIDS multiplied by the amount of bytes reserved for each 1144b9871bcfSAriel Elior * cid must not exceed the size of the VF doorbell 1145b9871bcfSAriel Elior */ 1146b9871bcfSAriel Elior #define BNX2X_VF_BAR_SIZE 512 1147b9871bcfSAriel Elior #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT)) 1148b9871bcfSAriel Elior #error "VF doorbell bar size is 512" 1149b9871bcfSAriel Elior #endif 1150b9871bcfSAriel Elior 1151adfc5217SJeff Kirsher /* 1152adfc5217SJeff Kirsher * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 1153adfc5217SJeff Kirsher * control by the number of fast-path status blocks supported by the 1154adfc5217SJeff Kirsher * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 1155adfc5217SJeff Kirsher * status block represents an independent interrupts context that can 1156adfc5217SJeff Kirsher * serve a regular L2 networking queue. However special L2 queues such 1157adfc5217SJeff Kirsher * as the FCoE queue do not require a FP-SB and other components like 1158adfc5217SJeff Kirsher * the CNIC may consume FP-SB reducing the number of possible L2 queues 1159adfc5217SJeff Kirsher * 1160adfc5217SJeff Kirsher * If the maximum number of FP-SB available is X then: 1161adfc5217SJeff Kirsher * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 1162adfc5217SJeff Kirsher * regular L2 queues is Y=X-1 116316a5fd92SYuval Mintz * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1164adfc5217SJeff Kirsher * c. If the FCoE L2 queue is supported the actual number of L2 queues 1165adfc5217SJeff Kirsher * is Y+1 1166adfc5217SJeff Kirsher * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1167adfc5217SJeff Kirsher * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1168adfc5217SJeff Kirsher * FP interrupt context for the CNIC). 1169adfc5217SJeff Kirsher * e. The number of HW context (CID count) is always X or X+1 if FCoE 117016a5fd92SYuval Mintz * L2 queue is supported. The cid for the FCoE L2 queue is always X. 1171adfc5217SJeff Kirsher */ 1172adfc5217SJeff Kirsher 1173adfc5217SJeff Kirsher /* fast-path interrupt contexts E1x */ 1174adfc5217SJeff Kirsher #define FP_SB_MAX_E1x 16 1175adfc5217SJeff Kirsher /* fast-path interrupt contexts E2 */ 1176adfc5217SJeff Kirsher #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1177adfc5217SJeff Kirsher 1178adfc5217SJeff Kirsher union cdu_context { 1179adfc5217SJeff Kirsher struct eth_context eth; 1180adfc5217SJeff Kirsher char pad[1024]; 1181adfc5217SJeff Kirsher }; 1182adfc5217SJeff Kirsher 1183adfc5217SJeff Kirsher /* CDU host DB constants */ 1184a052997eSMerav Sicron #define CDU_ILT_PAGE_SZ_HW 2 1185a052997eSMerav Sicron #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1186adfc5217SJeff Kirsher #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1187adfc5217SJeff Kirsher 1188adfc5217SJeff Kirsher #define CNIC_ISCSI_CID_MAX 256 1189adfc5217SJeff Kirsher #define CNIC_FCOE_CID_MAX 2048 1190adfc5217SJeff Kirsher #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1191adfc5217SJeff Kirsher #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1192adfc5217SJeff Kirsher 1193adfc5217SJeff Kirsher #define QM_ILT_PAGE_SZ_HW 0 1194adfc5217SJeff Kirsher #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1195adfc5217SJeff Kirsher #define QM_CID_ROUND 1024 1196adfc5217SJeff Kirsher 1197adfc5217SJeff Kirsher /* TM (timers) host DB constants */ 1198adfc5217SJeff Kirsher #define TM_ILT_PAGE_SZ_HW 0 1199adfc5217SJeff Kirsher #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 12000907f34cSAriel Elior #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \ 12010907f34cSAriel Elior BNX2X_VF_CIDS + \ 12020907f34cSAriel Elior CNIC_ISCSI_CID_MAX) 1203adfc5217SJeff Kirsher #define TM_ILT_SZ (8 * TM_CONN_NUM) 1204adfc5217SJeff Kirsher #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1205adfc5217SJeff Kirsher 1206adfc5217SJeff Kirsher /* SRC (Searcher) host DB constants */ 1207adfc5217SJeff Kirsher #define SRC_ILT_PAGE_SZ_HW 0 1208adfc5217SJeff Kirsher #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1209adfc5217SJeff Kirsher #define SRC_HASH_BITS 10 1210adfc5217SJeff Kirsher #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1211adfc5217SJeff Kirsher #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1212adfc5217SJeff Kirsher #define SRC_T2_SZ SRC_ILT_SZ 1213adfc5217SJeff Kirsher #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1214adfc5217SJeff Kirsher 1215adfc5217SJeff Kirsher #define MAX_DMAE_C 8 1216adfc5217SJeff Kirsher 1217adfc5217SJeff Kirsher /* DMA memory not used in fastpath */ 1218adfc5217SJeff Kirsher struct bnx2x_slowpath { 1219adfc5217SJeff Kirsher union { 1220adfc5217SJeff Kirsher struct mac_configuration_cmd e1x; 1221adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data e2; 1222adfc5217SJeff Kirsher } mac_rdata; 1223adfc5217SJeff Kirsher 1224adfc5217SJeff Kirsher union { 1225adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config e1x; 1226adfc5217SJeff Kirsher struct eth_filter_rules_ramrod_data e2; 1227adfc5217SJeff Kirsher } rx_mode_rdata; 1228adfc5217SJeff Kirsher 1229adfc5217SJeff Kirsher union { 1230adfc5217SJeff Kirsher struct mac_configuration_cmd e1; 1231adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data e2; 1232adfc5217SJeff Kirsher } mcast_rdata; 1233adfc5217SJeff Kirsher 1234adfc5217SJeff Kirsher struct eth_rss_update_ramrod_data rss_rdata; 1235adfc5217SJeff Kirsher 1236adfc5217SJeff Kirsher /* Queue State related ramrods are always sent under rtnl_lock */ 1237adfc5217SJeff Kirsher union { 1238adfc5217SJeff Kirsher struct client_init_ramrod_data init_data; 1239adfc5217SJeff Kirsher struct client_update_ramrod_data update_data; 1240adfc5217SJeff Kirsher } q_rdata; 1241adfc5217SJeff Kirsher 1242adfc5217SJeff Kirsher union { 1243adfc5217SJeff Kirsher struct function_start_data func_start; 1244adfc5217SJeff Kirsher /* pfc configuration for DCBX ramrod */ 1245adfc5217SJeff Kirsher struct flow_control_configuration pfc_config; 1246adfc5217SJeff Kirsher } func_rdata; 1247adfc5217SJeff Kirsher 1248a3348722SBarak Witkowski /* afex ramrod can not be a part of func_rdata union because these 1249a3348722SBarak Witkowski * events might arrive in parallel to other events from func_rdata. 1250a3348722SBarak Witkowski * Therefore, if they would have been defined in the same union, 1251a3348722SBarak Witkowski * data can get corrupted. 1252a3348722SBarak Witkowski */ 1253a3348722SBarak Witkowski struct afex_vif_list_ramrod_data func_afex_rdata; 1254a3348722SBarak Witkowski 1255adfc5217SJeff Kirsher /* used by dmae command executer */ 1256adfc5217SJeff Kirsher struct dmae_command dmae[MAX_DMAE_C]; 1257adfc5217SJeff Kirsher 1258adfc5217SJeff Kirsher u32 stats_comp; 1259adfc5217SJeff Kirsher union mac_stats mac_stats; 1260adfc5217SJeff Kirsher struct nig_stats nig_stats; 1261adfc5217SJeff Kirsher struct host_port_stats port_stats; 1262adfc5217SJeff Kirsher struct host_func_stats func_stats; 1263adfc5217SJeff Kirsher 1264adfc5217SJeff Kirsher u32 wb_comp; 1265adfc5217SJeff Kirsher u32 wb_data[4]; 12661d187b34SBarak Witkowski 12671d187b34SBarak Witkowski union drv_info_to_mcp drv_info_to_mcp; 1268adfc5217SJeff Kirsher }; 1269adfc5217SJeff Kirsher 1270adfc5217SJeff Kirsher #define bnx2x_sp(bp, var) (&bp->slowpath->var) 1271adfc5217SJeff Kirsher #define bnx2x_sp_mapping(bp, var) \ 1272adfc5217SJeff Kirsher (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1273adfc5217SJeff Kirsher 1274adfc5217SJeff Kirsher /* attn group wiring */ 1275adfc5217SJeff Kirsher #define MAX_DYNAMIC_ATTN_GRPS 8 1276adfc5217SJeff Kirsher 1277adfc5217SJeff Kirsher struct attn_route { 1278adfc5217SJeff Kirsher u32 sig[5]; 1279adfc5217SJeff Kirsher }; 1280adfc5217SJeff Kirsher 1281adfc5217SJeff Kirsher struct iro { 1282adfc5217SJeff Kirsher u32 base; 1283adfc5217SJeff Kirsher u16 m1; 1284adfc5217SJeff Kirsher u16 m2; 1285adfc5217SJeff Kirsher u16 m3; 1286adfc5217SJeff Kirsher u16 size; 1287adfc5217SJeff Kirsher }; 1288adfc5217SJeff Kirsher 1289adfc5217SJeff Kirsher struct hw_context { 1290adfc5217SJeff Kirsher union cdu_context *vcxt; 1291adfc5217SJeff Kirsher dma_addr_t cxt_mapping; 1292adfc5217SJeff Kirsher size_t size; 1293adfc5217SJeff Kirsher }; 1294adfc5217SJeff Kirsher 1295adfc5217SJeff Kirsher /* forward */ 1296adfc5217SJeff Kirsher struct bnx2x_ilt; 1297adfc5217SJeff Kirsher 1298290ca2bbSAriel Elior struct bnx2x_vfdb; 1299adfc5217SJeff Kirsher 1300adfc5217SJeff Kirsher enum bnx2x_recovery_state { 1301adfc5217SJeff Kirsher BNX2X_RECOVERY_DONE, 1302adfc5217SJeff Kirsher BNX2X_RECOVERY_INIT, 1303adfc5217SJeff Kirsher BNX2X_RECOVERY_WAIT, 130495c6c616SAriel Elior BNX2X_RECOVERY_FAILED, 130595c6c616SAriel Elior BNX2X_RECOVERY_NIC_LOADING 1306adfc5217SJeff Kirsher }; 1307adfc5217SJeff Kirsher 1308adfc5217SJeff Kirsher /* 1309adfc5217SJeff Kirsher * Event queue (EQ or event ring) MC hsi 1310adfc5217SJeff Kirsher * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1311adfc5217SJeff Kirsher */ 1312adfc5217SJeff Kirsher #define NUM_EQ_PAGES 1 1313adfc5217SJeff Kirsher #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1314adfc5217SJeff Kirsher #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1315adfc5217SJeff Kirsher #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1316adfc5217SJeff Kirsher #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1317adfc5217SJeff Kirsher #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1318adfc5217SJeff Kirsher 1319adfc5217SJeff Kirsher /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1320adfc5217SJeff Kirsher #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1321adfc5217SJeff Kirsher (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1322adfc5217SJeff Kirsher 1323adfc5217SJeff Kirsher /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1324adfc5217SJeff Kirsher #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1325adfc5217SJeff Kirsher 1326adfc5217SJeff Kirsher #define BNX2X_EQ_INDEX \ 1327adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 1328adfc5217SJeff Kirsher index_values[HC_SP_INDEX_EQ_CONS]) 1329adfc5217SJeff Kirsher 1330adfc5217SJeff Kirsher /* This is a data that will be used to create a link report message. 1331adfc5217SJeff Kirsher * We will keep the data used for the last link report in order 1332adfc5217SJeff Kirsher * to prevent reporting the same link parameters twice. 1333adfc5217SJeff Kirsher */ 1334adfc5217SJeff Kirsher struct bnx2x_link_report_data { 1335adfc5217SJeff Kirsher u16 line_speed; /* Effective line speed */ 1336adfc5217SJeff Kirsher unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1337adfc5217SJeff Kirsher }; 1338adfc5217SJeff Kirsher 1339adfc5217SJeff Kirsher enum { 1340adfc5217SJeff Kirsher BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1341adfc5217SJeff Kirsher BNX2X_LINK_REPORT_LINK_DOWN, 1342adfc5217SJeff Kirsher BNX2X_LINK_REPORT_RX_FC_ON, 1343adfc5217SJeff Kirsher BNX2X_LINK_REPORT_TX_FC_ON, 1344adfc5217SJeff Kirsher }; 1345adfc5217SJeff Kirsher 1346adfc5217SJeff Kirsher enum { 1347adfc5217SJeff Kirsher BNX2X_PORT_QUERY_IDX, 1348adfc5217SJeff Kirsher BNX2X_PF_QUERY_IDX, 134950f0a562SBarak Witkowski BNX2X_FCOE_QUERY_IDX, 1350adfc5217SJeff Kirsher BNX2X_FIRST_QUEUE_QUERY_IDX, 1351adfc5217SJeff Kirsher }; 1352adfc5217SJeff Kirsher 1353adfc5217SJeff Kirsher struct bnx2x_fw_stats_req { 1354adfc5217SJeff Kirsher struct stats_query_header hdr; 135550f0a562SBarak Witkowski struct stats_query_entry query[FP_SB_MAX_E1x+ 135650f0a562SBarak Witkowski BNX2X_FIRST_QUEUE_QUERY_IDX]; 1357adfc5217SJeff Kirsher }; 1358adfc5217SJeff Kirsher 1359adfc5217SJeff Kirsher struct bnx2x_fw_stats_data { 1360adfc5217SJeff Kirsher struct stats_counter storm_counters; 1361adfc5217SJeff Kirsher struct per_port_stats port; 1362adfc5217SJeff Kirsher struct per_pf_stats pf; 136350f0a562SBarak Witkowski struct fcoe_statistics_params fcoe; 1364adfc5217SJeff Kirsher struct per_queue_stats queue_stats[1]; 1365adfc5217SJeff Kirsher }; 1366adfc5217SJeff Kirsher 1367adfc5217SJeff Kirsher /* Public slow path states */ 1368adfc5217SJeff Kirsher enum { 1369adfc5217SJeff Kirsher BNX2X_SP_RTNL_SETUP_TC, 1370adfc5217SJeff Kirsher BNX2X_SP_RTNL_TX_TIMEOUT, 13718304859aSAriel Elior BNX2X_SP_RTNL_FAN_FAILURE, 13728395be5eSAriel Elior BNX2X_SP_RTNL_AFEX_F_UPDATE, 13738395be5eSAriel Elior BNX2X_SP_RTNL_ENABLE_SRIOV, 1374381ac16bSAriel Elior BNX2X_SP_RTNL_VFPF_MCAST, 137578c3bcc5SAriel Elior BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 13768b09be5fSYuval Mintz BNX2X_SP_RTNL_RX_MODE, 13773ec9f9caSAriel Elior BNX2X_SP_RTNL_HYPERVISOR_VLAN, 137807b4eb3bSDmitry Kravkov BNX2X_SP_RTNL_TX_STOP, 137907b4eb3bSDmitry Kravkov BNX2X_SP_RTNL_TX_RESUME, 1380adfc5217SJeff Kirsher }; 1381adfc5217SJeff Kirsher 1382452427b0SYuval Mintz struct bnx2x_prev_path_list { 13837fa6f340SYuval Mintz struct list_head list; 1384452427b0SYuval Mintz u8 bus; 1385452427b0SYuval Mintz u8 slot; 1386452427b0SYuval Mintz u8 path; 13877fa6f340SYuval Mintz u8 aer; 1388c63da990SBarak Witkowski u8 undi; 1389452427b0SYuval Mintz }; 1390452427b0SYuval Mintz 139115192a8cSBarak Witkowski struct bnx2x_sp_objs { 139215192a8cSBarak Witkowski /* MACs object */ 139315192a8cSBarak Witkowski struct bnx2x_vlan_mac_obj mac_obj; 139415192a8cSBarak Witkowski 139515192a8cSBarak Witkowski /* Queue State object */ 139615192a8cSBarak Witkowski struct bnx2x_queue_sp_obj q_obj; 139715192a8cSBarak Witkowski }; 139815192a8cSBarak Witkowski 139915192a8cSBarak Witkowski struct bnx2x_fp_stats { 140015192a8cSBarak Witkowski struct tstorm_per_queue_stats old_tclient; 140115192a8cSBarak Witkowski struct ustorm_per_queue_stats old_uclient; 140215192a8cSBarak Witkowski struct xstorm_per_queue_stats old_xclient; 140315192a8cSBarak Witkowski struct bnx2x_eth_q_stats eth_q_stats; 140415192a8cSBarak Witkowski struct bnx2x_eth_q_stats_old eth_q_stats_old; 140515192a8cSBarak Witkowski }; 140615192a8cSBarak Witkowski 1407adfc5217SJeff Kirsher struct bnx2x { 1408adfc5217SJeff Kirsher /* Fields used in the tx and intr/napi performance paths 1409adfc5217SJeff Kirsher * are grouped together in the beginning of the structure 1410adfc5217SJeff Kirsher */ 1411adfc5217SJeff Kirsher struct bnx2x_fastpath *fp; 141215192a8cSBarak Witkowski struct bnx2x_sp_objs *sp_objs; 141315192a8cSBarak Witkowski struct bnx2x_fp_stats *fp_stats; 141465565884SMerav Sicron struct bnx2x_fp_txdata *bnx2x_txq; 1415adfc5217SJeff Kirsher void __iomem *regview; 1416adfc5217SJeff Kirsher void __iomem *doorbells; 1417adfc5217SJeff Kirsher u16 db_size; 1418adfc5217SJeff Kirsher 1419adfc5217SJeff Kirsher u8 pf_num; /* absolute PF number */ 1420adfc5217SJeff Kirsher u8 pfid; /* per-path PF number */ 1421adfc5217SJeff Kirsher int base_fw_ndsb; /**/ 1422adfc5217SJeff Kirsher #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1423adfc5217SJeff Kirsher #define BP_PORT(bp) (bp->pfid & 1) 1424adfc5217SJeff Kirsher #define BP_FUNC(bp) (bp->pfid) 1425adfc5217SJeff Kirsher #define BP_ABS_FUNC(bp) (bp->pf_num) 14268decf868SDavid S. Miller #define BP_VN(bp) ((bp)->pfid >> 1) 14278decf868SDavid S. Miller #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 14288decf868SDavid S. Miller #define BP_L_ID(bp) (BP_VN(bp) << 2) 14298decf868SDavid S. Miller #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 14308decf868SDavid S. Miller (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 14318decf868SDavid S. Miller #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1432adfc5217SJeff Kirsher 14336411280aSAriel Elior #ifdef CONFIG_BNX2X_SRIOV 14341d6f3cd8SDmitry Kravkov /* protects vf2pf mailbox from simultaneous access */ 14351d6f3cd8SDmitry Kravkov struct mutex vf2pf_mutex; 14361ab4434cSAriel Elior /* vf pf channel mailbox contains request and response buffers */ 14371ab4434cSAriel Elior struct bnx2x_vf_mbx_msg *vf2pf_mbox; 14381ab4434cSAriel Elior dma_addr_t vf2pf_mbox_mapping; 14391ab4434cSAriel Elior 1440be1f1ffaSAriel Elior /* we set aside a copy of the acquire response */ 1441be1f1ffaSAriel Elior struct pfvf_acquire_resp_tlv acquire_resp; 1442be1f1ffaSAriel Elior 1443abc5a021SAriel Elior /* bulletin board for messages from pf to vf */ 1444abc5a021SAriel Elior union pf_vf_bulletin *pf2vf_bulletin; 1445abc5a021SAriel Elior dma_addr_t pf2vf_bulletin_mapping; 1446abc5a021SAriel Elior 1447abc5a021SAriel Elior struct pf_vf_bulletin_content old_bulletin; 14483c76feffSAriel Elior 14493c76feffSAriel Elior u16 requested_nr_virtfn; 14506411280aSAriel Elior #endif /* CONFIG_BNX2X_SRIOV */ 1451abc5a021SAriel Elior 1452adfc5217SJeff Kirsher struct net_device *dev; 1453adfc5217SJeff Kirsher struct pci_dev *pdev; 1454adfc5217SJeff Kirsher 1455adfc5217SJeff Kirsher const struct iro *iro_arr; 1456adfc5217SJeff Kirsher #define IRO (bp->iro_arr) 1457adfc5217SJeff Kirsher 1458adfc5217SJeff Kirsher enum bnx2x_recovery_state recovery_state; 1459adfc5217SJeff Kirsher int is_leader; 1460adfc5217SJeff Kirsher struct msix_entry *msix_table; 1461adfc5217SJeff Kirsher 1462adfc5217SJeff Kirsher int tx_ring_size; 1463adfc5217SJeff Kirsher 1464adfc5217SJeff Kirsher /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1465adfc5217SJeff Kirsher #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1466adfc5217SJeff Kirsher #define ETH_MIN_PACKET_SIZE 60 1467adfc5217SJeff Kirsher #define ETH_MAX_PACKET_SIZE 1500 1468adfc5217SJeff Kirsher #define ETH_MAX_JUMBO_PACKET_SIZE 9600 1469621b4d66SDmitry Kravkov /* TCP with Timestamp Option (32) + IPv6 (40) */ 1470621b4d66SDmitry Kravkov #define ETH_MAX_TPA_HEADER_SIZE 72 1471adfc5217SJeff Kirsher 1472adfc5217SJeff Kirsher /* Max supported alignment is 256 (8 shift) */ 1473e52fcb24SEric Dumazet #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1474e52fcb24SEric Dumazet 1475e52fcb24SEric Dumazet /* FW uses 2 Cache lines Alignment for start packet and size 1476e52fcb24SEric Dumazet * 1477e52fcb24SEric Dumazet * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1478e52fcb24SEric Dumazet * at the end of skb->data, to avoid wasting a full cache line. 1479e52fcb24SEric Dumazet * This reduces memory use (skb->truesize). 1480e52fcb24SEric Dumazet */ 1481e52fcb24SEric Dumazet #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1482e52fcb24SEric Dumazet 1483e52fcb24SEric Dumazet #define BNX2X_FW_RX_ALIGN_END \ 1484f57b07c0SJoren Van Onder max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1485e52fcb24SEric Dumazet SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1486e52fcb24SEric Dumazet 1487adfc5217SJeff Kirsher #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1488adfc5217SJeff Kirsher 1489adfc5217SJeff Kirsher struct host_sp_status_block *def_status_blk; 1490adfc5217SJeff Kirsher #define DEF_SB_IGU_ID 16 1491adfc5217SJeff Kirsher #define DEF_SB_ID HC_SP_SB_ID 1492adfc5217SJeff Kirsher __le16 def_idx; 1493adfc5217SJeff Kirsher __le16 def_att_idx; 1494adfc5217SJeff Kirsher u32 attn_state; 1495adfc5217SJeff Kirsher struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1496adfc5217SJeff Kirsher 1497adfc5217SJeff Kirsher /* slow path ring */ 1498adfc5217SJeff Kirsher struct eth_spe *spq; 1499adfc5217SJeff Kirsher dma_addr_t spq_mapping; 1500adfc5217SJeff Kirsher u16 spq_prod_idx; 1501adfc5217SJeff Kirsher struct eth_spe *spq_prod_bd; 1502adfc5217SJeff Kirsher struct eth_spe *spq_last_bd; 1503adfc5217SJeff Kirsher __le16 *dsb_sp_prod; 1504adfc5217SJeff Kirsher atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1505adfc5217SJeff Kirsher /* used to synchronize spq accesses */ 1506adfc5217SJeff Kirsher spinlock_t spq_lock; 1507adfc5217SJeff Kirsher 1508adfc5217SJeff Kirsher /* event queue */ 1509adfc5217SJeff Kirsher union event_ring_elem *eq_ring; 1510adfc5217SJeff Kirsher dma_addr_t eq_mapping; 1511adfc5217SJeff Kirsher u16 eq_prod; 1512adfc5217SJeff Kirsher u16 eq_cons; 1513adfc5217SJeff Kirsher __le16 *eq_cons_sb; 1514adfc5217SJeff Kirsher atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1515adfc5217SJeff Kirsher 1516adfc5217SJeff Kirsher /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1517adfc5217SJeff Kirsher u16 stats_pending; 1518adfc5217SJeff Kirsher /* Counter for completed statistics ramrods */ 1519adfc5217SJeff Kirsher u16 stats_comp; 1520adfc5217SJeff Kirsher 1521adfc5217SJeff Kirsher /* End of fields used in the performance code paths */ 1522adfc5217SJeff Kirsher 1523adfc5217SJeff Kirsher int panic; 1524adfc5217SJeff Kirsher int msg_enable; 1525adfc5217SJeff Kirsher 1526adfc5217SJeff Kirsher u32 flags; 1527adfc5217SJeff Kirsher #define PCIX_FLAG (1 << 0) 1528adfc5217SJeff Kirsher #define PCI_32BIT_FLAG (1 << 1) 1529adfc5217SJeff Kirsher #define ONE_PORT_FLAG (1 << 2) 1530adfc5217SJeff Kirsher #define NO_WOL_FLAG (1 << 3) 1531adfc5217SJeff Kirsher #define USING_DAC_FLAG (1 << 4) 1532adfc5217SJeff Kirsher #define USING_MSIX_FLAG (1 << 5) 1533adfc5217SJeff Kirsher #define USING_MSI_FLAG (1 << 6) 1534adfc5217SJeff Kirsher #define DISABLE_MSI_FLAG (1 << 7) 1535adfc5217SJeff Kirsher #define TPA_ENABLE_FLAG (1 << 8) 1536adfc5217SJeff Kirsher #define NO_MCP_FLAG (1 << 9) 1537621b4d66SDmitry Kravkov #define GRO_ENABLE_FLAG (1 << 10) 1538adfc5217SJeff Kirsher #define MF_FUNC_DIS (1 << 11) 1539adfc5217SJeff Kirsher #define OWN_CNIC_IRQ (1 << 12) 1540adfc5217SJeff Kirsher #define NO_ISCSI_OOO_FLAG (1 << 13) 1541adfc5217SJeff Kirsher #define NO_ISCSI_FLAG (1 << 14) 1542adfc5217SJeff Kirsher #define NO_FCOE_FLAG (1 << 15) 15430e898dd7SBarak Witkowski #define BC_SUPPORTS_PFC_STATS (1 << 17) 15442e499d3cSBarak Witkowski #define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 154530a5de77SDmitry Kravkov #define USING_SINGLE_MSIX_FLAG (1 << 20) 15469876879fSBarak Witkowski #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 15471ab4434cSAriel Elior #define IS_VF_FLAG (1 << 22) 154878c3bcc5SAriel Elior #define INTERRUPTS_ENABLED_FLAG (1 << 23) 1549a6d3a5baSBarak Witkowsky #define BC_SUPPORTS_RMMOD_CMD (1 << 24) 15501ab4434cSAriel Elior 15511ab4434cSAriel Elior #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 15526411280aSAriel Elior 15536411280aSAriel Elior #ifdef CONFIG_BNX2X_SRIOV 15541ab4434cSAriel Elior #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 15551ab4434cSAriel Elior #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 15566411280aSAriel Elior #else 15576411280aSAriel Elior #define IS_VF(bp) false 15586411280aSAriel Elior #define IS_PF(bp) true 15596411280aSAriel Elior #endif 1560adfc5217SJeff Kirsher 1561adfc5217SJeff Kirsher #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1562adfc5217SJeff Kirsher #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1563adfc5217SJeff Kirsher #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1564adfc5217SJeff Kirsher 156555c11941SMerav Sicron u8 cnic_support; 156655c11941SMerav Sicron bool cnic_enabled; 156755c11941SMerav Sicron bool cnic_loaded; 15684bd9b0ffSMichael Chan struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 156955c11941SMerav Sicron 157055c11941SMerav Sicron /* Flag that indicates that we can start looking for FCoE L2 queue 157155c11941SMerav Sicron * completions in the default status block. 157255c11941SMerav Sicron */ 157355c11941SMerav Sicron bool fcoe_init; 157455c11941SMerav Sicron 1575adfc5217SJeff Kirsher int mrrs; 1576adfc5217SJeff Kirsher 1577adfc5217SJeff Kirsher struct delayed_work sp_task; 1578fd1fc79dSAriel Elior atomic_t interrupt_occurred; 1579adfc5217SJeff Kirsher struct delayed_work sp_rtnl_task; 1580adfc5217SJeff Kirsher 1581adfc5217SJeff Kirsher struct delayed_work period_task; 1582adfc5217SJeff Kirsher struct timer_list timer; 1583adfc5217SJeff Kirsher int current_interval; 1584adfc5217SJeff Kirsher 1585adfc5217SJeff Kirsher u16 fw_seq; 1586adfc5217SJeff Kirsher u16 fw_drv_pulse_wr_seq; 1587adfc5217SJeff Kirsher u32 func_stx; 1588adfc5217SJeff Kirsher 1589adfc5217SJeff Kirsher struct link_params link_params; 1590adfc5217SJeff Kirsher struct link_vars link_vars; 1591adfc5217SJeff Kirsher u32 link_cnt; 1592adfc5217SJeff Kirsher struct bnx2x_link_report_data last_reported_link; 1593adfc5217SJeff Kirsher 1594adfc5217SJeff Kirsher struct mdio_if_info mdio; 1595adfc5217SJeff Kirsher 1596adfc5217SJeff Kirsher struct bnx2x_common common; 1597adfc5217SJeff Kirsher struct bnx2x_port port; 1598adfc5217SJeff Kirsher 1599b475d78fSYuval Mintz struct cmng_init cmng; 1600b475d78fSYuval Mintz 1601adfc5217SJeff Kirsher u32 mf_config[E1HVN_MAX]; 1602a3348722SBarak Witkowski u32 mf_ext_config; 1603adfc5217SJeff Kirsher u32 path_has_ovlan; /* E3 */ 1604adfc5217SJeff Kirsher u16 mf_ov; 1605adfc5217SJeff Kirsher u8 mf_mode; 1606adfc5217SJeff Kirsher #define IS_MF(bp) (bp->mf_mode != 0) 1607adfc5217SJeff Kirsher #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1608adfc5217SJeff Kirsher #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1609a3348722SBarak Witkowski #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1610adfc5217SJeff Kirsher 1611adfc5217SJeff Kirsher u8 wol; 1612adfc5217SJeff Kirsher 1613adfc5217SJeff Kirsher int rx_ring_size; 1614adfc5217SJeff Kirsher 1615adfc5217SJeff Kirsher u16 tx_quick_cons_trip_int; 1616adfc5217SJeff Kirsher u16 tx_quick_cons_trip; 1617adfc5217SJeff Kirsher u16 tx_ticks_int; 1618adfc5217SJeff Kirsher u16 tx_ticks; 1619adfc5217SJeff Kirsher 1620adfc5217SJeff Kirsher u16 rx_quick_cons_trip_int; 1621adfc5217SJeff Kirsher u16 rx_quick_cons_trip; 1622adfc5217SJeff Kirsher u16 rx_ticks_int; 1623adfc5217SJeff Kirsher u16 rx_ticks; 1624adfc5217SJeff Kirsher /* Maximal coalescing timeout in us */ 16256802516eSDmitry Kravkov #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR) 1626adfc5217SJeff Kirsher 1627adfc5217SJeff Kirsher u32 lin_cnt; 1628adfc5217SJeff Kirsher 1629adfc5217SJeff Kirsher u16 state; 1630adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSED 0 1631adfc5217SJeff Kirsher #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1632adfc5217SJeff Kirsher #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1633adfc5217SJeff Kirsher #define BNX2X_STATE_OPEN 0x3000 1634adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1635adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1636adfc5217SJeff Kirsher 1637adfc5217SJeff Kirsher #define BNX2X_STATE_DIAG 0xe000 1638adfc5217SJeff Kirsher #define BNX2X_STATE_ERROR 0xf000 1639adfc5217SJeff Kirsher 1640adfc5217SJeff Kirsher #define BNX2X_MAX_PRIORITY 8 1641adfc5217SJeff Kirsher #define BNX2X_MAX_ENTRIES_PER_PRI 16 1642adfc5217SJeff Kirsher #define BNX2X_MAX_COS 3 1643adfc5217SJeff Kirsher #define BNX2X_MAX_TX_COS 2 1644adfc5217SJeff Kirsher int num_queues; 164555c11941SMerav Sicron uint num_ethernet_queues; 164655c11941SMerav Sicron uint num_cnic_queues; 16470e8d2ec5SMerav Sicron int num_napi_queues; 1648adfc5217SJeff Kirsher int disable_tpa; 1649adfc5217SJeff Kirsher 1650adfc5217SJeff Kirsher u32 rx_mode; 1651adfc5217SJeff Kirsher #define BNX2X_RX_MODE_NONE 0 1652adfc5217SJeff Kirsher #define BNX2X_RX_MODE_NORMAL 1 1653adfc5217SJeff Kirsher #define BNX2X_RX_MODE_ALLMULTI 2 1654adfc5217SJeff Kirsher #define BNX2X_RX_MODE_PROMISC 3 1655adfc5217SJeff Kirsher #define BNX2X_MAX_MULTICAST 64 1656adfc5217SJeff Kirsher 1657adfc5217SJeff Kirsher u8 igu_dsb_id; 1658adfc5217SJeff Kirsher u8 igu_base_sb; 1659adfc5217SJeff Kirsher u8 igu_sb_cnt; 166055c11941SMerav Sicron u8 min_msix_vec_cnt; 166165565884SMerav Sicron 16621ab4434cSAriel Elior u32 igu_base_addr; 1663adfc5217SJeff Kirsher dma_addr_t def_status_blk_mapping; 1664adfc5217SJeff Kirsher 1665adfc5217SJeff Kirsher struct bnx2x_slowpath *slowpath; 1666adfc5217SJeff Kirsher dma_addr_t slowpath_mapping; 1667adfc5217SJeff Kirsher 1668adfc5217SJeff Kirsher /* Total number of FW statistics requests */ 1669adfc5217SJeff Kirsher u8 fw_stats_num; 1670adfc5217SJeff Kirsher 1671adfc5217SJeff Kirsher /* 1672adfc5217SJeff Kirsher * This is a memory buffer that will contain both statistics 1673adfc5217SJeff Kirsher * ramrod request and data. 1674adfc5217SJeff Kirsher */ 1675adfc5217SJeff Kirsher void *fw_stats; 1676adfc5217SJeff Kirsher dma_addr_t fw_stats_mapping; 1677adfc5217SJeff Kirsher 1678adfc5217SJeff Kirsher /* 1679adfc5217SJeff Kirsher * FW statistics request shortcut (points at the 1680adfc5217SJeff Kirsher * beginning of fw_stats buffer). 1681adfc5217SJeff Kirsher */ 1682adfc5217SJeff Kirsher struct bnx2x_fw_stats_req *fw_stats_req; 1683adfc5217SJeff Kirsher dma_addr_t fw_stats_req_mapping; 1684adfc5217SJeff Kirsher int fw_stats_req_sz; 1685adfc5217SJeff Kirsher 1686adfc5217SJeff Kirsher /* 16874907cb7bSAnatol Pomozov * FW statistics data shortcut (points at the beginning of 1688adfc5217SJeff Kirsher * fw_stats buffer + fw_stats_req_sz). 1689adfc5217SJeff Kirsher */ 1690adfc5217SJeff Kirsher struct bnx2x_fw_stats_data *fw_stats_data; 1691adfc5217SJeff Kirsher dma_addr_t fw_stats_data_mapping; 1692adfc5217SJeff Kirsher int fw_stats_data_sz; 1693adfc5217SJeff Kirsher 1694b9871bcfSAriel Elior /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB 1695a052997eSMerav Sicron * context size we need 8 ILT entries. 1696a052997eSMerav Sicron */ 1697b9871bcfSAriel Elior #define ILT_MAX_L2_LINES 32 1698a052997eSMerav Sicron struct hw_context context[ILT_MAX_L2_LINES]; 1699adfc5217SJeff Kirsher 1700adfc5217SJeff Kirsher struct bnx2x_ilt *ilt; 1701adfc5217SJeff Kirsher #define BP_ILT(bp) ((bp)->ilt) 1702adfc5217SJeff Kirsher #define ILT_MAX_LINES 256 1703adfc5217SJeff Kirsher /* 1704adfc5217SJeff Kirsher * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1705adfc5217SJeff Kirsher * to CNIC. 1706adfc5217SJeff Kirsher */ 170755c11941SMerav Sicron #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1708adfc5217SJeff Kirsher 1709adfc5217SJeff Kirsher /* 1710adfc5217SJeff Kirsher * Maximum CID count that might be required by the bnx2x: 171137ae41a9SMerav Sicron * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1712adfc5217SJeff Kirsher */ 1713f78afb35SMichael Chan 171437ae41a9SMerav Sicron #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1715f78afb35SMichael Chan + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 171637ae41a9SMerav Sicron #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1717f78afb35SMichael Chan + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1718adfc5217SJeff Kirsher #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1719adfc5217SJeff Kirsher ILT_PAGE_CIDS)) 1720adfc5217SJeff Kirsher 1721adfc5217SJeff Kirsher int qm_cid_count; 1722adfc5217SJeff Kirsher 17237964211dSYuval Mintz bool dropless_fc; 1724adfc5217SJeff Kirsher 1725adfc5217SJeff Kirsher void *t2; 1726adfc5217SJeff Kirsher dma_addr_t t2_mapping; 1727adfc5217SJeff Kirsher struct cnic_ops __rcu *cnic_ops; 1728adfc5217SJeff Kirsher void *cnic_data; 1729adfc5217SJeff Kirsher u32 cnic_tag; 1730adfc5217SJeff Kirsher struct cnic_eth_dev cnic_eth_dev; 1731adfc5217SJeff Kirsher union host_hc_status_block cnic_sb; 1732adfc5217SJeff Kirsher dma_addr_t cnic_sb_mapping; 1733adfc5217SJeff Kirsher struct eth_spe *cnic_kwq; 1734adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_prod; 1735adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_cons; 1736adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_last; 1737adfc5217SJeff Kirsher u16 cnic_kwq_pending; 1738adfc5217SJeff Kirsher u16 cnic_spq_pending; 1739adfc5217SJeff Kirsher u8 fip_mac[ETH_ALEN]; 1740adfc5217SJeff Kirsher struct mutex cnic_mutex; 1741adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1742adfc5217SJeff Kirsher 174316a5fd92SYuval Mintz /* Start index of the "special" (CNIC related) L2 clients */ 1744adfc5217SJeff Kirsher u8 cnic_base_cl_id; 1745adfc5217SJeff Kirsher 1746adfc5217SJeff Kirsher int dmae_ready; 1747adfc5217SJeff Kirsher /* used to synchronize dmae accesses */ 1748adfc5217SJeff Kirsher spinlock_t dmae_lock; 1749adfc5217SJeff Kirsher 1750adfc5217SJeff Kirsher /* used to protect the FW mail box */ 1751adfc5217SJeff Kirsher struct mutex fw_mb_mutex; 1752adfc5217SJeff Kirsher 1753adfc5217SJeff Kirsher /* used to synchronize stats collecting */ 1754adfc5217SJeff Kirsher int stats_state; 1755adfc5217SJeff Kirsher 1756adfc5217SJeff Kirsher /* used for synchronization of concurrent threads statistics handling */ 1757adfc5217SJeff Kirsher spinlock_t stats_lock; 1758adfc5217SJeff Kirsher 1759adfc5217SJeff Kirsher /* used by dmae command loader */ 1760adfc5217SJeff Kirsher struct dmae_command stats_dmae; 1761adfc5217SJeff Kirsher int executer_idx; 1762adfc5217SJeff Kirsher 1763adfc5217SJeff Kirsher u16 stats_counter; 1764adfc5217SJeff Kirsher struct bnx2x_eth_stats eth_stats; 1765cb4dca27SYuval Mintz struct host_func_stats func_stats; 17661355b704SMintz Yuval struct bnx2x_eth_stats_old eth_stats_old; 17671355b704SMintz Yuval struct bnx2x_net_stats_old net_stats_old; 17681355b704SMintz Yuval struct bnx2x_fw_port_stats_old fw_stats_old; 17691355b704SMintz Yuval bool stats_init; 1770adfc5217SJeff Kirsher 1771adfc5217SJeff Kirsher struct z_stream_s *strm; 1772adfc5217SJeff Kirsher void *gunzip_buf; 1773adfc5217SJeff Kirsher dma_addr_t gunzip_mapping; 1774adfc5217SJeff Kirsher int gunzip_outlen; 1775adfc5217SJeff Kirsher #define FW_BUF_SIZE 0x8000 1776adfc5217SJeff Kirsher #define GUNZIP_BUF(bp) (bp->gunzip_buf) 1777adfc5217SJeff Kirsher #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1778adfc5217SJeff Kirsher #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1779adfc5217SJeff Kirsher 1780adfc5217SJeff Kirsher struct raw_op *init_ops; 1781adfc5217SJeff Kirsher /* Init blocks offsets inside init_ops */ 1782adfc5217SJeff Kirsher u16 *init_ops_offsets; 1783adfc5217SJeff Kirsher /* Data blob - has 32 bit granularity */ 1784adfc5217SJeff Kirsher u32 *init_data; 1785adfc5217SJeff Kirsher u32 init_mode_flags; 1786adfc5217SJeff Kirsher #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1787adfc5217SJeff Kirsher /* Zipped PRAM blobs - raw data */ 1788adfc5217SJeff Kirsher const u8 *tsem_int_table_data; 1789adfc5217SJeff Kirsher const u8 *tsem_pram_data; 1790adfc5217SJeff Kirsher const u8 *usem_int_table_data; 1791adfc5217SJeff Kirsher const u8 *usem_pram_data; 1792adfc5217SJeff Kirsher const u8 *xsem_int_table_data; 1793adfc5217SJeff Kirsher const u8 *xsem_pram_data; 1794adfc5217SJeff Kirsher const u8 *csem_int_table_data; 1795adfc5217SJeff Kirsher const u8 *csem_pram_data; 1796adfc5217SJeff Kirsher #define INIT_OPS(bp) (bp->init_ops) 1797adfc5217SJeff Kirsher #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1798adfc5217SJeff Kirsher #define INIT_DATA(bp) (bp->init_data) 1799adfc5217SJeff Kirsher #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1800adfc5217SJeff Kirsher #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1801adfc5217SJeff Kirsher #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1802adfc5217SJeff Kirsher #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1803adfc5217SJeff Kirsher #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1804adfc5217SJeff Kirsher #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1805adfc5217SJeff Kirsher #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1806adfc5217SJeff Kirsher #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1807adfc5217SJeff Kirsher 1808adfc5217SJeff Kirsher #define PHY_FW_VER_LEN 20 1809adfc5217SJeff Kirsher char fw_ver[32]; 1810adfc5217SJeff Kirsher const struct firmware *firmware; 1811adfc5217SJeff Kirsher 1812290ca2bbSAriel Elior struct bnx2x_vfdb *vfdb; 1813290ca2bbSAriel Elior #define IS_SRIOV(bp) ((bp)->vfdb) 1814290ca2bbSAriel Elior 1815adfc5217SJeff Kirsher /* DCB support on/off */ 1816adfc5217SJeff Kirsher u16 dcb_state; 1817adfc5217SJeff Kirsher #define BNX2X_DCB_STATE_OFF 0 1818adfc5217SJeff Kirsher #define BNX2X_DCB_STATE_ON 1 1819adfc5217SJeff Kirsher 1820adfc5217SJeff Kirsher /* DCBX engine mode */ 1821adfc5217SJeff Kirsher int dcbx_enabled; 1822adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_OFF 0 1823adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1824adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1825adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_INVALID (-1) 1826adfc5217SJeff Kirsher 1827adfc5217SJeff Kirsher bool dcbx_mode_uset; 1828adfc5217SJeff Kirsher 1829adfc5217SJeff Kirsher struct bnx2x_config_dcbx_params dcbx_config_params; 1830adfc5217SJeff Kirsher struct bnx2x_dcbx_port_params dcbx_port_params; 1831adfc5217SJeff Kirsher int dcb_version; 1832adfc5217SJeff Kirsher 1833adfc5217SJeff Kirsher /* CAM credit pools */ 1834b56e9670SAriel Elior 1835b56e9670SAriel Elior /* used only in sriov */ 1836b56e9670SAriel Elior struct bnx2x_credit_pool_obj vlans_pool; 1837b56e9670SAriel Elior 1838adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj macs_pool; 1839adfc5217SJeff Kirsher 1840adfc5217SJeff Kirsher /* RX_MODE object */ 1841adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj rx_mode_obj; 1842adfc5217SJeff Kirsher 1843adfc5217SJeff Kirsher /* MCAST object */ 1844adfc5217SJeff Kirsher struct bnx2x_mcast_obj mcast_obj; 1845adfc5217SJeff Kirsher 1846adfc5217SJeff Kirsher /* RSS configuration object */ 1847adfc5217SJeff Kirsher struct bnx2x_rss_config_obj rss_conf_obj; 1848adfc5217SJeff Kirsher 1849adfc5217SJeff Kirsher /* Function State controlling object */ 1850adfc5217SJeff Kirsher struct bnx2x_func_sp_obj func_obj; 1851adfc5217SJeff Kirsher 1852adfc5217SJeff Kirsher unsigned long sp_state; 1853adfc5217SJeff Kirsher 1854adfc5217SJeff Kirsher /* operation indication for the sp_rtnl task */ 1855adfc5217SJeff Kirsher unsigned long sp_rtnl_state; 1856adfc5217SJeff Kirsher 185716a5fd92SYuval Mintz /* DCBX Negotiation results */ 1858adfc5217SJeff Kirsher struct dcbx_features dcbx_local_feat; 1859adfc5217SJeff Kirsher u32 dcbx_error; 1860adfc5217SJeff Kirsher 1861adfc5217SJeff Kirsher #ifdef BCM_DCBNL 1862adfc5217SJeff Kirsher struct dcbx_features dcbx_remote_feat; 1863adfc5217SJeff Kirsher u32 dcbx_remote_flags; 1864adfc5217SJeff Kirsher #endif 1865a3348722SBarak Witkowski /* AFEX: store default vlan used */ 1866a3348722SBarak Witkowski int afex_def_vlan_tag; 1867a3348722SBarak Witkowski enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1868adfc5217SJeff Kirsher u32 pending_max; 1869adfc5217SJeff Kirsher 1870adfc5217SJeff Kirsher /* multiple tx classes of service */ 1871adfc5217SJeff Kirsher u8 max_cos; 1872adfc5217SJeff Kirsher 1873adfc5217SJeff Kirsher /* priority to cos mapping */ 1874adfc5217SJeff Kirsher u8 prio_to_cos[8]; 1875c3146eb6SDmitry Kravkov 1876c3146eb6SDmitry Kravkov int fp_array_size; 187707ba6af4SMiriam Shitrit u32 dump_preset_idx; 1878507393ebSDmitry Kravkov bool stats_started; 1879507393ebSDmitry Kravkov struct semaphore stats_sema; 1880adfc5217SJeff Kirsher }; 1881adfc5217SJeff Kirsher 1882adfc5217SJeff Kirsher /* Tx queues may be less or equal to Rx queues */ 1883adfc5217SJeff Kirsher extern int num_queues; 1884adfc5217SJeff Kirsher #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 188555c11941SMerav Sicron #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 188665565884SMerav Sicron #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 188755c11941SMerav Sicron (bp)->num_cnic_queues) 1888adfc5217SJeff Kirsher #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1889adfc5217SJeff Kirsher 1890adfc5217SJeff Kirsher #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1891adfc5217SJeff Kirsher 1892adfc5217SJeff Kirsher #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1893adfc5217SJeff Kirsher /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1894adfc5217SJeff Kirsher 1895adfc5217SJeff Kirsher #define RSS_IPV4_CAP_MASK \ 1896adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1897adfc5217SJeff Kirsher 1898adfc5217SJeff Kirsher #define RSS_IPV4_TCP_CAP_MASK \ 1899adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1900adfc5217SJeff Kirsher 1901adfc5217SJeff Kirsher #define RSS_IPV6_CAP_MASK \ 1902adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1903adfc5217SJeff Kirsher 1904adfc5217SJeff Kirsher #define RSS_IPV6_TCP_CAP_MASK \ 1905adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1906adfc5217SJeff Kirsher 1907adfc5217SJeff Kirsher /* func init flags */ 1908adfc5217SJeff Kirsher #define FUNC_FLG_RSS 0x0001 1909adfc5217SJeff Kirsher #define FUNC_FLG_STATS 0x0002 1910adfc5217SJeff Kirsher /* removed FUNC_FLG_UNMATCHED 0x0004 */ 1911adfc5217SJeff Kirsher #define FUNC_FLG_TPA 0x0008 1912adfc5217SJeff Kirsher #define FUNC_FLG_SPQ 0x0010 1913adfc5217SJeff Kirsher #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1914b9871bcfSAriel Elior #define FUNC_FLG_LEADING_STATS 0x0040 1915adfc5217SJeff Kirsher struct bnx2x_func_init_params { 1916adfc5217SJeff Kirsher /* dma */ 1917adfc5217SJeff Kirsher dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1918adfc5217SJeff Kirsher dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1919adfc5217SJeff Kirsher 1920adfc5217SJeff Kirsher u16 func_flgs; 1921adfc5217SJeff Kirsher u16 func_id; /* abs fid */ 1922adfc5217SJeff Kirsher u16 pf_id; 1923adfc5217SJeff Kirsher u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1924adfc5217SJeff Kirsher }; 1925adfc5217SJeff Kirsher 192655c11941SMerav Sicron #define for_each_cnic_queue(bp, var) \ 192755c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 192855c11941SMerav Sicron (var)++) \ 192955c11941SMerav Sicron if (skip_queue(bp, var)) \ 193055c11941SMerav Sicron continue; \ 193155c11941SMerav Sicron else 193255c11941SMerav Sicron 1933adfc5217SJeff Kirsher #define for_each_eth_queue(bp, var) \ 1934adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1935adfc5217SJeff Kirsher 1936adfc5217SJeff Kirsher #define for_each_nondefault_eth_queue(bp, var) \ 1937adfc5217SJeff Kirsher for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1938adfc5217SJeff Kirsher 1939adfc5217SJeff Kirsher #define for_each_queue(bp, var) \ 1940adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1941adfc5217SJeff Kirsher if (skip_queue(bp, var)) \ 1942adfc5217SJeff Kirsher continue; \ 1943adfc5217SJeff Kirsher else 1944adfc5217SJeff Kirsher 1945adfc5217SJeff Kirsher /* Skip forwarding FP */ 194655c11941SMerav Sicron #define for_each_valid_rx_queue(bp, var) \ 194755c11941SMerav Sicron for ((var) = 0; \ 194855c11941SMerav Sicron (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 194955c11941SMerav Sicron BNX2X_NUM_ETH_QUEUES(bp)); \ 195055c11941SMerav Sicron (var)++) \ 195155c11941SMerav Sicron if (skip_rx_queue(bp, var)) \ 195255c11941SMerav Sicron continue; \ 195355c11941SMerav Sicron else 195455c11941SMerav Sicron 195555c11941SMerav Sicron #define for_each_rx_queue_cnic(bp, var) \ 195655c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 195755c11941SMerav Sicron (var)++) \ 195855c11941SMerav Sicron if (skip_rx_queue(bp, var)) \ 195955c11941SMerav Sicron continue; \ 196055c11941SMerav Sicron else 196155c11941SMerav Sicron 1962adfc5217SJeff Kirsher #define for_each_rx_queue(bp, var) \ 1963adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1964adfc5217SJeff Kirsher if (skip_rx_queue(bp, var)) \ 1965adfc5217SJeff Kirsher continue; \ 1966adfc5217SJeff Kirsher else 1967adfc5217SJeff Kirsher 1968adfc5217SJeff Kirsher /* Skip OOO FP */ 196955c11941SMerav Sicron #define for_each_valid_tx_queue(bp, var) \ 197055c11941SMerav Sicron for ((var) = 0; \ 197155c11941SMerav Sicron (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 197255c11941SMerav Sicron BNX2X_NUM_ETH_QUEUES(bp)); \ 197355c11941SMerav Sicron (var)++) \ 197455c11941SMerav Sicron if (skip_tx_queue(bp, var)) \ 197555c11941SMerav Sicron continue; \ 197655c11941SMerav Sicron else 197755c11941SMerav Sicron 197855c11941SMerav Sicron #define for_each_tx_queue_cnic(bp, var) \ 197955c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 198055c11941SMerav Sicron (var)++) \ 198155c11941SMerav Sicron if (skip_tx_queue(bp, var)) \ 198255c11941SMerav Sicron continue; \ 198355c11941SMerav Sicron else 198455c11941SMerav Sicron 1985adfc5217SJeff Kirsher #define for_each_tx_queue(bp, var) \ 1986adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1987adfc5217SJeff Kirsher if (skip_tx_queue(bp, var)) \ 1988adfc5217SJeff Kirsher continue; \ 1989adfc5217SJeff Kirsher else 1990adfc5217SJeff Kirsher 1991adfc5217SJeff Kirsher #define for_each_nondefault_queue(bp, var) \ 1992adfc5217SJeff Kirsher for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1993adfc5217SJeff Kirsher if (skip_queue(bp, var)) \ 1994adfc5217SJeff Kirsher continue; \ 1995adfc5217SJeff Kirsher else 1996adfc5217SJeff Kirsher 1997adfc5217SJeff Kirsher #define for_each_cos_in_tx_queue(fp, var) \ 1998adfc5217SJeff Kirsher for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1999adfc5217SJeff Kirsher 2000adfc5217SJeff Kirsher /* skip rx queue 2001adfc5217SJeff Kirsher * if FCOE l2 support is disabled and this is the fcoe L2 queue 2002adfc5217SJeff Kirsher */ 2003adfc5217SJeff Kirsher #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2004adfc5217SJeff Kirsher 2005adfc5217SJeff Kirsher /* skip tx queue 2006adfc5217SJeff Kirsher * if FCOE l2 support is disabled and this is the fcoe L2 queue 2007adfc5217SJeff Kirsher */ 2008adfc5217SJeff Kirsher #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2009adfc5217SJeff Kirsher 2010adfc5217SJeff Kirsher #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2011adfc5217SJeff Kirsher 2012adfc5217SJeff Kirsher /** 2013adfc5217SJeff Kirsher * bnx2x_set_mac_one - configure a single MAC address 2014adfc5217SJeff Kirsher * 2015adfc5217SJeff Kirsher * @bp: driver handle 2016adfc5217SJeff Kirsher * @mac: MAC to configure 2017adfc5217SJeff Kirsher * @obj: MAC object handle 2018adfc5217SJeff Kirsher * @set: if 'true' add a new MAC, otherwise - delete 2019adfc5217SJeff Kirsher * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 2020adfc5217SJeff Kirsher * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 2021adfc5217SJeff Kirsher * 2022adfc5217SJeff Kirsher * Configures one MAC according to provided parameters or continues the 2023adfc5217SJeff Kirsher * execution of previously scheduled commands if RAMROD_CONT is set in 2024adfc5217SJeff Kirsher * ramrod_flags. 2025adfc5217SJeff Kirsher * 2026adfc5217SJeff Kirsher * Returns zero if operation has successfully completed, a positive value if the 2027adfc5217SJeff Kirsher * operation has been successfully scheduled and a negative - if a requested 2028adfc5217SJeff Kirsher * operations has failed. 2029adfc5217SJeff Kirsher */ 2030adfc5217SJeff Kirsher int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 2031adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *obj, bool set, 2032adfc5217SJeff Kirsher int mac_type, unsigned long *ramrod_flags); 2033adfc5217SJeff Kirsher /** 2034adfc5217SJeff Kirsher * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 2035adfc5217SJeff Kirsher * 2036adfc5217SJeff Kirsher * @bp: driver handle 2037adfc5217SJeff Kirsher * @mac_obj: MAC object handle 2038adfc5217SJeff Kirsher * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 2039adfc5217SJeff Kirsher * @wait_for_comp: if 'true' block until completion 2040adfc5217SJeff Kirsher * 2041adfc5217SJeff Kirsher * Deletes all MACs of the specific type (e.g. ETH, UC list). 2042adfc5217SJeff Kirsher * 2043adfc5217SJeff Kirsher * Returns zero if operation has successfully completed, a positive value if the 2044adfc5217SJeff Kirsher * operation has been successfully scheduled and a negative - if a requested 2045adfc5217SJeff Kirsher * operations has failed. 2046adfc5217SJeff Kirsher */ 2047adfc5217SJeff Kirsher int bnx2x_del_all_macs(struct bnx2x *bp, 2048adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj, 2049adfc5217SJeff Kirsher int mac_type, bool wait_for_comp); 2050adfc5217SJeff Kirsher 2051adfc5217SJeff Kirsher /* Init Function API */ 2052adfc5217SJeff Kirsher void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 2053b93288d5SAriel Elior void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 2054b93288d5SAriel Elior u8 vf_valid, int fw_sb_id, int igu_sb_id); 2055b56e9670SAriel Elior u32 bnx2x_get_pretend_reg(struct bnx2x *bp); 2056adfc5217SJeff Kirsher int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 2057adfc5217SJeff Kirsher int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2058adfc5217SJeff Kirsher int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 2059adfc5217SJeff Kirsher int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2060adfc5217SJeff Kirsher void bnx2x_read_mf_cfg(struct bnx2x *bp); 2061adfc5217SJeff Kirsher 2062b56e9670SAriel Elior int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 2063adfc5217SJeff Kirsher 2064adfc5217SJeff Kirsher /* dmae */ 2065adfc5217SJeff Kirsher void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 2066adfc5217SJeff Kirsher void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 2067adfc5217SJeff Kirsher u32 len32); 2068adfc5217SJeff Kirsher void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 2069adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 2070adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 2071adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 2072adfc5217SJeff Kirsher bool with_comp, u8 comp_type); 2073adfc5217SJeff Kirsher 2074fd1fc79dSAriel Elior void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2075fd1fc79dSAriel Elior u8 src_type, u8 dst_type); 2076fd1fc79dSAriel Elior int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae); 2077fd1fc79dSAriel Elior 2078d16132ceSAriel Elior /* FLR related routines */ 2079d16132ceSAriel Elior u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 2080d16132ceSAriel Elior void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 2081d16132ceSAriel Elior int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 2082b56e9670SAriel Elior u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 2083d16132ceSAriel Elior int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 2084d16132ceSAriel Elior char *msg, u32 poll_cnt); 2085adfc5217SJeff Kirsher 2086adfc5217SJeff Kirsher void bnx2x_calc_fc_adv(struct bnx2x *bp); 2087adfc5217SJeff Kirsher int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 2088adfc5217SJeff Kirsher u32 data_hi, u32 data_lo, int cmd_type); 2089adfc5217SJeff Kirsher void bnx2x_update_coalesce(struct bnx2x *bp); 2090adfc5217SJeff Kirsher int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 2091adfc5217SJeff Kirsher 2092178135c1SDmitry Kravkov bool bnx2x_port_after_undi(struct bnx2x *bp); 2093178135c1SDmitry Kravkov 2094adfc5217SJeff Kirsher static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 2095adfc5217SJeff Kirsher int wait) 2096adfc5217SJeff Kirsher { 2097adfc5217SJeff Kirsher u32 val; 2098adfc5217SJeff Kirsher 2099adfc5217SJeff Kirsher do { 2100adfc5217SJeff Kirsher val = REG_RD(bp, reg); 2101adfc5217SJeff Kirsher if (val == expected) 2102adfc5217SJeff Kirsher break; 2103adfc5217SJeff Kirsher ms -= wait; 2104adfc5217SJeff Kirsher msleep(wait); 2105adfc5217SJeff Kirsher 2106adfc5217SJeff Kirsher } while (ms > 0); 2107adfc5217SJeff Kirsher 2108adfc5217SJeff Kirsher return val; 2109adfc5217SJeff Kirsher } 2110adfc5217SJeff Kirsher 2111b56e9670SAriel Elior void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 2112b56e9670SAriel Elior bool is_pf); 2113b56e9670SAriel Elior 2114adfc5217SJeff Kirsher #define BNX2X_ILT_ZALLOC(x, y, size) \ 2115ede23fa8SJoe Perches x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL) 2116adfc5217SJeff Kirsher 2117adfc5217SJeff Kirsher #define BNX2X_ILT_FREE(x, y, size) \ 2118adfc5217SJeff Kirsher do { \ 2119adfc5217SJeff Kirsher if (x) { \ 2120adfc5217SJeff Kirsher dma_free_coherent(&bp->pdev->dev, size, x, y); \ 2121adfc5217SJeff Kirsher x = NULL; \ 2122adfc5217SJeff Kirsher y = 0; \ 2123adfc5217SJeff Kirsher } \ 2124adfc5217SJeff Kirsher } while (0) 2125adfc5217SJeff Kirsher 2126adfc5217SJeff Kirsher #define ILOG2(x) (ilog2((x))) 2127adfc5217SJeff Kirsher 2128adfc5217SJeff Kirsher #define ILT_NUM_PAGE_ENTRIES (3072) 2129adfc5217SJeff Kirsher /* In 57710/11 we use whole table since we have 8 func 2130adfc5217SJeff Kirsher * In 57712 we have only 4 func, but use same size per func, then only half of 2131adfc5217SJeff Kirsher * the table in use 2132adfc5217SJeff Kirsher */ 2133adfc5217SJeff Kirsher #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 2134adfc5217SJeff Kirsher 2135adfc5217SJeff Kirsher #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 2136adfc5217SJeff Kirsher /* 2137adfc5217SJeff Kirsher * the phys address is shifted right 12 bits and has an added 2138adfc5217SJeff Kirsher * 1=valid bit added to the 53rd bit 2139adfc5217SJeff Kirsher * then since this is a wide register(TM) 2140adfc5217SJeff Kirsher * we split it into two 32 bit writes 2141adfc5217SJeff Kirsher */ 2142adfc5217SJeff Kirsher #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 2143adfc5217SJeff Kirsher #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 2144adfc5217SJeff Kirsher 2145adfc5217SJeff Kirsher /* load/unload mode */ 2146adfc5217SJeff Kirsher #define LOAD_NORMAL 0 2147adfc5217SJeff Kirsher #define LOAD_OPEN 1 2148adfc5217SJeff Kirsher #define LOAD_DIAG 2 21498970b2e4SMerav Sicron #define LOAD_LOOPBACK_EXT 3 2150adfc5217SJeff Kirsher #define UNLOAD_NORMAL 0 2151adfc5217SJeff Kirsher #define UNLOAD_CLOSE 1 2152adfc5217SJeff Kirsher #define UNLOAD_RECOVERY 2 2153adfc5217SJeff Kirsher 2154adfc5217SJeff Kirsher /* DMAE command defines */ 2155adfc5217SJeff Kirsher #define DMAE_TIMEOUT -1 2156adfc5217SJeff Kirsher #define DMAE_PCI_ERROR -2 /* E2 and onward */ 2157adfc5217SJeff Kirsher #define DMAE_NOT_RDY -3 2158adfc5217SJeff Kirsher #define DMAE_PCI_ERR_FLAG 0x80000000 2159adfc5217SJeff Kirsher 2160adfc5217SJeff Kirsher #define DMAE_SRC_PCI 0 2161adfc5217SJeff Kirsher #define DMAE_SRC_GRC 1 2162adfc5217SJeff Kirsher 2163adfc5217SJeff Kirsher #define DMAE_DST_NONE 0 2164adfc5217SJeff Kirsher #define DMAE_DST_PCI 1 2165adfc5217SJeff Kirsher #define DMAE_DST_GRC 2 2166adfc5217SJeff Kirsher 2167adfc5217SJeff Kirsher #define DMAE_COMP_PCI 0 2168adfc5217SJeff Kirsher #define DMAE_COMP_GRC 1 2169adfc5217SJeff Kirsher 2170adfc5217SJeff Kirsher /* E2 and onward - PCI error handling in the completion */ 2171adfc5217SJeff Kirsher 2172adfc5217SJeff Kirsher #define DMAE_COMP_REGULAR 0 2173adfc5217SJeff Kirsher #define DMAE_COM_SET_ERR 1 2174adfc5217SJeff Kirsher 2175adfc5217SJeff Kirsher #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2176adfc5217SJeff Kirsher DMAE_COMMAND_SRC_SHIFT) 2177adfc5217SJeff Kirsher #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2178adfc5217SJeff Kirsher DMAE_COMMAND_SRC_SHIFT) 2179adfc5217SJeff Kirsher 2180adfc5217SJeff Kirsher #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2181adfc5217SJeff Kirsher DMAE_COMMAND_DST_SHIFT) 2182adfc5217SJeff Kirsher #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2183adfc5217SJeff Kirsher DMAE_COMMAND_DST_SHIFT) 2184adfc5217SJeff Kirsher 2185adfc5217SJeff Kirsher #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2186adfc5217SJeff Kirsher DMAE_COMMAND_C_DST_SHIFT) 2187adfc5217SJeff Kirsher #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2188adfc5217SJeff Kirsher DMAE_COMMAND_C_DST_SHIFT) 2189adfc5217SJeff Kirsher 2190adfc5217SJeff Kirsher #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2191adfc5217SJeff Kirsher 2192adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2193adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2194adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2195adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2196adfc5217SJeff Kirsher 2197adfc5217SJeff Kirsher #define DMAE_CMD_PORT_0 0 2198adfc5217SJeff Kirsher #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2199adfc5217SJeff Kirsher 2200adfc5217SJeff Kirsher #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2201adfc5217SJeff Kirsher #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2202adfc5217SJeff Kirsher #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2203adfc5217SJeff Kirsher 2204adfc5217SJeff Kirsher #define DMAE_SRC_PF 0 2205adfc5217SJeff Kirsher #define DMAE_SRC_VF 1 2206adfc5217SJeff Kirsher 2207adfc5217SJeff Kirsher #define DMAE_DST_PF 0 2208adfc5217SJeff Kirsher #define DMAE_DST_VF 1 2209adfc5217SJeff Kirsher 2210adfc5217SJeff Kirsher #define DMAE_C_SRC 0 2211adfc5217SJeff Kirsher #define DMAE_C_DST 1 2212adfc5217SJeff Kirsher 2213adfc5217SJeff Kirsher #define DMAE_LEN32_RD_MAX 0x80 2214adfc5217SJeff Kirsher #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2215adfc5217SJeff Kirsher 2216adfc5217SJeff Kirsher #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 221716a5fd92SYuval Mintz * indicates error 221816a5fd92SYuval Mintz */ 2219adfc5217SJeff Kirsher 2220adfc5217SJeff Kirsher #define MAX_DMAE_C_PER_PORT 8 2221adfc5217SJeff Kirsher #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 22228decf868SDavid S. Miller BP_VN(bp)) 2223adfc5217SJeff Kirsher #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2224adfc5217SJeff Kirsher E1HVN_MAX) 2225adfc5217SJeff Kirsher 2226adfc5217SJeff Kirsher /* PCIE link and speed */ 2227adfc5217SJeff Kirsher #define PCICFG_LINK_WIDTH 0x1f00000 2228adfc5217SJeff Kirsher #define PCICFG_LINK_WIDTH_SHIFT 20 2229adfc5217SJeff Kirsher #define PCICFG_LINK_SPEED 0xf0000 2230adfc5217SJeff Kirsher #define PCICFG_LINK_SPEED_SHIFT 16 2231adfc5217SJeff Kirsher 2232cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS_SF 7 2233cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS_MF 3 2234cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 2235cf2c1df6SMerav Sicron BNX2X_NUM_TESTS_SF) 2236adfc5217SJeff Kirsher 2237adfc5217SJeff Kirsher #define BNX2X_PHY_LOOPBACK 0 2238adfc5217SJeff Kirsher #define BNX2X_MAC_LOOPBACK 1 22398970b2e4SMerav Sicron #define BNX2X_EXT_LOOPBACK 2 2240adfc5217SJeff Kirsher #define BNX2X_PHY_LOOPBACK_FAILED 1 2241adfc5217SJeff Kirsher #define BNX2X_MAC_LOOPBACK_FAILED 2 22428970b2e4SMerav Sicron #define BNX2X_EXT_LOOPBACK_FAILED 3 2243adfc5217SJeff Kirsher #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2244adfc5217SJeff Kirsher BNX2X_PHY_LOOPBACK_FAILED) 2245adfc5217SJeff Kirsher 2246adfc5217SJeff Kirsher #define STROM_ASSERT_ARRAY_SIZE 50 2247adfc5217SJeff Kirsher 2248adfc5217SJeff Kirsher /* must be used on a CID before placing it on a HW ring */ 2249adfc5217SJeff Kirsher #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 22508decf868SDavid S. Miller (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2251adfc5217SJeff Kirsher (x)) 2252adfc5217SJeff Kirsher 2253adfc5217SJeff Kirsher #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2254adfc5217SJeff Kirsher #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2255adfc5217SJeff Kirsher 2256adfc5217SJeff Kirsher #define BNX2X_BTR 4 2257adfc5217SJeff Kirsher #define MAX_SPQ_PENDING 8 2258adfc5217SJeff Kirsher 2259adfc5217SJeff Kirsher /* CMNG constants, as derived from system spec calculations */ 2260adfc5217SJeff Kirsher /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2261adfc5217SJeff Kirsher #define DEF_MIN_RATE 100 2262adfc5217SJeff Kirsher /* resolution of the rate shaping timer - 400 usec */ 2263adfc5217SJeff Kirsher #define RS_PERIODIC_TIMEOUT_USEC 400 2264adfc5217SJeff Kirsher /* number of bytes in single QM arbitration cycle - 2265adfc5217SJeff Kirsher * coefficient for calculating the fairness timer */ 2266adfc5217SJeff Kirsher #define QM_ARB_BYTES 160000 2267adfc5217SJeff Kirsher /* resolution of Min algorithm 1:100 */ 2268adfc5217SJeff Kirsher #define MIN_RES 100 2269adfc5217SJeff Kirsher /* how many bytes above threshold for the minimal credit of Min algorithm*/ 2270adfc5217SJeff Kirsher #define MIN_ABOVE_THRESH 32768 2271adfc5217SJeff Kirsher /* Fairness algorithm integration time coefficient - 2272adfc5217SJeff Kirsher * for calculating the actual Tfair */ 2273adfc5217SJeff Kirsher #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2274adfc5217SJeff Kirsher /* Memory of fairness algorithm . 2 cycles */ 2275adfc5217SJeff Kirsher #define FAIR_MEM 2 2276adfc5217SJeff Kirsher 2277adfc5217SJeff Kirsher #define ATTN_NIG_FOR_FUNC (1L << 8) 2278adfc5217SJeff Kirsher #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2279adfc5217SJeff Kirsher #define GPIO_2_FUNC (1L << 10) 2280adfc5217SJeff Kirsher #define GPIO_3_FUNC (1L << 11) 2281adfc5217SJeff Kirsher #define GPIO_4_FUNC (1L << 12) 2282adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_1 (1L << 13) 2283adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_2 (1L << 14) 2284adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_3 (1L << 15) 2285adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_4 (1L << 13) 2286adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_5 (1L << 14) 2287adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_6 (1L << 15) 2288adfc5217SJeff Kirsher 2289adfc5217SJeff Kirsher #define ATTN_HARD_WIRED_MASK 0xff00 2290adfc5217SJeff Kirsher #define ATTENTION_ID 4 2291adfc5217SJeff Kirsher 22923521b419SYuval Mintz #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \ 22933521b419SYuval Mintz IS_MF_FCOE_AFEX(bp)) 2294adfc5217SJeff Kirsher 2295adfc5217SJeff Kirsher /* stuff added to make the code fit 80Col */ 2296adfc5217SJeff Kirsher 2297adfc5217SJeff Kirsher #define BNX2X_PMF_LINK_ASSERT \ 2298adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2299adfc5217SJeff Kirsher 2300adfc5217SJeff Kirsher #define BNX2X_MC_ASSERT_BITS \ 2301adfc5217SJeff Kirsher (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2302adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2303adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2304adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2305adfc5217SJeff Kirsher 2306adfc5217SJeff Kirsher #define BNX2X_MCP_ASSERT \ 2307adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2308adfc5217SJeff Kirsher 2309adfc5217SJeff Kirsher #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2310adfc5217SJeff Kirsher #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2311adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2312adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2313adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2314adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2315adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2316adfc5217SJeff Kirsher 2317adfc5217SJeff Kirsher #define HW_INTERRUT_ASSERT_SET_0 \ 2318adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2319adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2320adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2321c14a09b7SDmitry Kravkov AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2322adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2323adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2324adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2325adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2326adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2327adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2328adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2329adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2330adfc5217SJeff Kirsher #define HW_INTERRUT_ASSERT_SET_1 \ 2331adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2332adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2333adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2334adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2335adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2336adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2337adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2338adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2339adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2340adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2341adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2342adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2343adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2344adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2345adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2346adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2347adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2348adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2349adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2350adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2351adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2352adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2353adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2354adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2355adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2356adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2357adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2358adfc5217SJeff Kirsher #define HW_INTERRUT_ASSERT_SET_2 \ 2359adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2360adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2361adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2362adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2363adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2364adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2365adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2366adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2367adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2368adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2369adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2370adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2371adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2372adfc5217SJeff Kirsher 2373adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2374adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2375adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2376adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2377adfc5217SJeff Kirsher 2378adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2379adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2380adfc5217SJeff Kirsher 2381adfc5217SJeff Kirsher #define MULTI_MASK 0x7f 2382adfc5217SJeff Kirsher 2383adfc5217SJeff Kirsher #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2384adfc5217SJeff Kirsher #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2385adfc5217SJeff Kirsher #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2386adfc5217SJeff Kirsher #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2387adfc5217SJeff Kirsher 2388adfc5217SJeff Kirsher #define DEF_USB_IGU_INDEX_OFF \ 2389adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_u, igu_index) 2390adfc5217SJeff Kirsher #define DEF_CSB_IGU_INDEX_OFF \ 2391adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_c, igu_index) 2392adfc5217SJeff Kirsher #define DEF_XSB_IGU_INDEX_OFF \ 2393adfc5217SJeff Kirsher offsetof(struct xstorm_def_status_block, igu_index) 2394adfc5217SJeff Kirsher #define DEF_TSB_IGU_INDEX_OFF \ 2395adfc5217SJeff Kirsher offsetof(struct tstorm_def_status_block, igu_index) 2396adfc5217SJeff Kirsher 2397adfc5217SJeff Kirsher #define DEF_USB_SEGMENT_OFF \ 2398adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_u, segment) 2399adfc5217SJeff Kirsher #define DEF_CSB_SEGMENT_OFF \ 2400adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_c, segment) 2401adfc5217SJeff Kirsher #define DEF_XSB_SEGMENT_OFF \ 2402adfc5217SJeff Kirsher offsetof(struct xstorm_def_status_block, segment) 2403adfc5217SJeff Kirsher #define DEF_TSB_SEGMENT_OFF \ 2404adfc5217SJeff Kirsher offsetof(struct tstorm_def_status_block, segment) 2405adfc5217SJeff Kirsher 2406adfc5217SJeff Kirsher #define BNX2X_SP_DSB_INDEX \ 2407adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 2408adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2409adfc5217SJeff Kirsher 2410adfc5217SJeff Kirsher #define CAM_IS_INVALID(x) \ 2411adfc5217SJeff Kirsher (GET_FLAG(x.flags, \ 2412adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2413adfc5217SJeff Kirsher (T_ETH_MAC_COMMAND_INVALIDATE)) 2414adfc5217SJeff Kirsher 2415adfc5217SJeff Kirsher /* Number of u32 elements in MC hash array */ 2416adfc5217SJeff Kirsher #define MC_HASH_SIZE 8 2417adfc5217SJeff Kirsher #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2418adfc5217SJeff Kirsher TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2419adfc5217SJeff Kirsher 2420adfc5217SJeff Kirsher #ifndef PXP2_REG_PXP2_INT_STS 2421adfc5217SJeff Kirsher #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2422adfc5217SJeff Kirsher #endif 2423adfc5217SJeff Kirsher 2424adfc5217SJeff Kirsher #ifndef ETH_MAX_RX_CLIENTS_E2 2425adfc5217SJeff Kirsher #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2426adfc5217SJeff Kirsher #endif 2427adfc5217SJeff Kirsher 2428adfc5217SJeff Kirsher #define BNX2X_VPD_LEN 128 2429adfc5217SJeff Kirsher #define VENDOR_ID_LEN 4 2430adfc5217SJeff Kirsher 2431be1f1ffaSAriel Elior #define VF_ACQUIRE_THRESH 3 2432be1f1ffaSAriel Elior #define VF_ACQUIRE_MAC_FILTERS 1 2433be1f1ffaSAriel Elior #define VF_ACQUIRE_MC_FILTERS 10 2434be1f1ffaSAriel Elior 2435be1f1ffaSAriel Elior #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2436be1f1ffaSAriel Elior (!((me_reg) & ME_REG_VF_ERR))) 2437ad5afc89SAriel Elior int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code); 2438adfc5217SJeff Kirsher /* Congestion management fairness mode */ 2439adfc5217SJeff Kirsher #define CMNG_FNS_NONE 0 2440adfc5217SJeff Kirsher #define CMNG_FNS_MINMAX 1 2441adfc5217SJeff Kirsher 2442adfc5217SJeff Kirsher #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2443adfc5217SJeff Kirsher #define HC_SEG_ACCESS_ATTN 4 2444adfc5217SJeff Kirsher #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2445adfc5217SJeff Kirsher 2446adfc5217SJeff Kirsher static const u32 dmae_reg_go_c[] = { 2447adfc5217SJeff Kirsher DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2448adfc5217SJeff Kirsher DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2449adfc5217SJeff Kirsher DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2450adfc5217SJeff Kirsher DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2451adfc5217SJeff Kirsher }; 2452adfc5217SJeff Kirsher 2453005a07baSAriel Elior void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); 2454adfc5217SJeff Kirsher void bnx2x_notify_link_changed(struct bnx2x *bp); 2455614c76dfSDmitry Kravkov 24569e62e912SDmitry Kravkov #define BNX2X_MF_SD_PROTOCOL(bp) \ 2457614c76dfSDmitry Kravkov ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2458614c76dfSDmitry Kravkov 24599e62e912SDmitry Kravkov #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 24609e62e912SDmitry Kravkov (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2461614c76dfSDmitry Kravkov 24629e62e912SDmitry Kravkov #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 24639e62e912SDmitry Kravkov (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 24649e62e912SDmitry Kravkov 24659e62e912SDmitry Kravkov #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 24669e62e912SDmitry Kravkov #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 24679e62e912SDmitry Kravkov 2468a3348722SBarak Witkowski #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2469a3348722SBarak Witkowski MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2470a3348722SBarak Witkowski 2471a3348722SBarak Witkowski #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 24729e62e912SDmitry Kravkov #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 24739e62e912SDmitry Kravkov (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 24749e62e912SDmitry Kravkov BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2475614c76dfSDmitry Kravkov 24762de67439SYuval Mintz #define SET_FLAG(value, mask, flag) \ 24772de67439SYuval Mintz do {\ 24782de67439SYuval Mintz (value) &= ~(mask);\ 24792de67439SYuval Mintz (value) |= ((flag) << (mask##_SHIFT));\ 24802de67439SYuval Mintz } while (0) 24812de67439SYuval Mintz 24822de67439SYuval Mintz #define GET_FLAG(value, mask) \ 24832de67439SYuval Mintz (((value) & (mask)) >> (mask##_SHIFT)) 24842de67439SYuval Mintz 24852de67439SYuval Mintz #define GET_FIELD(value, fname) \ 24862de67439SYuval Mintz (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 24872de67439SYuval Mintz 248855c11941SMerav Sicron enum { 248955c11941SMerav Sicron SWITCH_UPDATE, 249055c11941SMerav Sicron AFEX_UPDATE, 249155c11941SMerav Sicron }; 249255c11941SMerav Sicron 249355c11941SMerav Sicron #define NUM_MACS 8 2494a3348722SBarak Witkowski 2495ca1ee4b2SDmitry Kravkov enum bnx2x_pci_bus_speed { 2496ca1ee4b2SDmitry Kravkov BNX2X_PCI_LINK_SPEED_2500 = 2500, 2497ca1ee4b2SDmitry Kravkov BNX2X_PCI_LINK_SPEED_5000 = 5000, 2498ca1ee4b2SDmitry Kravkov BNX2X_PCI_LINK_SPEED_8000 = 8000 2499ca1ee4b2SDmitry Kravkov }; 2500568e2426SDmitry Kravkov 2501568e2426SDmitry Kravkov void bnx2x_set_local_cmng(struct bnx2x *bp); 25021a6974b2SYuval Mintz 25031a6974b2SYuval Mintz #define MCPR_SCRATCH_BASE(bp) \ 25041a6974b2SYuval Mintz (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 25051a6974b2SYuval Mintz 2506adfc5217SJeff Kirsher #endif /* bnx2x.h */ 2507