14ad79e13SYuval Mintz /* bnx2x.h: QLogic Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2007-2013 Broadcom Corporation 44ad79e13SYuval Mintz * Copyright (c) 2014 QLogic Corporation 54ad79e13SYuval Mintz * All rights reserved 6adfc5217SJeff Kirsher * 7adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 8adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 9adfc5217SJeff Kirsher * the Free Software Foundation. 10adfc5217SJeff Kirsher * 1108f6dd89SAriel Elior * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12adfc5217SJeff Kirsher * Written by: Eliezer Tamir 13adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 14adfc5217SJeff Kirsher */ 15adfc5217SJeff Kirsher 16adfc5217SJeff Kirsher #ifndef BNX2X_H 17adfc5217SJeff Kirsher #define BNX2X_H 18290ca2bbSAriel Elior 19290ca2bbSAriel Elior #include <linux/pci.h> 20adfc5217SJeff Kirsher #include <linux/netdevice.h> 21adfc5217SJeff Kirsher #include <linux/dma-mapping.h> 22adfc5217SJeff Kirsher #include <linux/types.h> 23290ca2bbSAriel Elior #include <linux/pci_regs.h> 24adfc5217SJeff Kirsher 25eeed018cSMichal Kalderon #include <linux/ptp_clock_kernel.h> 26eeed018cSMichal Kalderon #include <linux/net_tstamp.h> 2774d23cc7SRichard Cochran #include <linux/timecounter.h> 28eeed018cSMichal Kalderon 29adfc5217SJeff Kirsher /* compilation time flags */ 30adfc5217SJeff Kirsher 31adfc5217SJeff Kirsher /* define this to make the driver freeze on error to allow getting debug info 32adfc5217SJeff Kirsher * (you will need to reboot afterwards) */ 33adfc5217SJeff Kirsher /* #define BNX2X_STOP_ON_ERROR */ 34adfc5217SJeff Kirsher 353a375e3cSYuval Mintz #define DRV_MODULE_VERSION "1.712.30-0" 363156b8ebSDmitry Kravkov #define DRV_MODULE_RELDATE "2014/02/10" 37adfc5217SJeff Kirsher #define BNX2X_BC_VER 0x040200 38adfc5217SJeff Kirsher 39adfc5217SJeff Kirsher #if defined(CONFIG_DCB) 40adfc5217SJeff Kirsher #define BCM_DCBNL 41adfc5217SJeff Kirsher #endif 42b475d78fSYuval Mintz 43b475d78fSYuval Mintz #include "bnx2x_hsi.h" 44b475d78fSYuval Mintz 45adfc5217SJeff Kirsher #include "../cnic_if.h" 46adfc5217SJeff Kirsher 4755c11941SMerav Sicron #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 48adfc5217SJeff Kirsher 49adfc5217SJeff Kirsher #include <linux/mdio.h> 50adfc5217SJeff Kirsher 51adfc5217SJeff Kirsher #include "bnx2x_reg.h" 52adfc5217SJeff Kirsher #include "bnx2x_fw_defs.h" 532e499d3cSBarak Witkowski #include "bnx2x_mfw_req.h" 54adfc5217SJeff Kirsher #include "bnx2x_link.h" 55adfc5217SJeff Kirsher #include "bnx2x_sp.h" 56adfc5217SJeff Kirsher #include "bnx2x_dcb.h" 57adfc5217SJeff Kirsher #include "bnx2x_stats.h" 58be1f1ffaSAriel Elior #include "bnx2x_vfpf.h" 59adfc5217SJeff Kirsher 601ab4434cSAriel Elior enum bnx2x_int_mode { 611ab4434cSAriel Elior BNX2X_INT_MODE_MSIX, 621ab4434cSAriel Elior BNX2X_INT_MODE_INTX, 631ab4434cSAriel Elior BNX2X_INT_MODE_MSI 641ab4434cSAriel Elior }; 651ab4434cSAriel Elior 66adfc5217SJeff Kirsher /* error/debug prints */ 67adfc5217SJeff Kirsher 68adfc5217SJeff Kirsher #define DRV_MODULE_NAME "bnx2x" 69adfc5217SJeff Kirsher 70adfc5217SJeff Kirsher /* for messages that are currently off */ 7151c1a580SMerav Sicron #define BNX2X_MSG_OFF 0x0 7251c1a580SMerav Sicron #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 7351c1a580SMerav Sicron #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 7451c1a580SMerav Sicron #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 7551c1a580SMerav Sicron #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 7651c1a580SMerav Sicron #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 7751c1a580SMerav Sicron #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 7851c1a580SMerav Sicron #define BNX2X_MSG_IOV 0x0800000 79eeed018cSMichal Kalderon #define BNX2X_MSG_PTP 0x1000000 8051c1a580SMerav Sicron #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 8151c1a580SMerav Sicron #define BNX2X_MSG_ETHTOOL 0x4000000 8251c1a580SMerav Sicron #define BNX2X_MSG_DCB 0x8000000 83adfc5217SJeff Kirsher 84adfc5217SJeff Kirsher /* regular debug print */ 8576ca70faSYuval Mintz #define DP_INNER(fmt, ...) \ 86f1deab50SJoe Perches pr_notice("[%s:%d(%s)]" fmt, \ 87adfc5217SJeff Kirsher __func__, __LINE__, \ 88adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 8976ca70faSYuval Mintz ##__VA_ARGS__); 9076ca70faSYuval Mintz 9176ca70faSYuval Mintz #define DP(__mask, fmt, ...) \ 9276ca70faSYuval Mintz do { \ 9376ca70faSYuval Mintz if (unlikely(bp->msg_enable & (__mask))) \ 9476ca70faSYuval Mintz DP_INNER(fmt, ##__VA_ARGS__); \ 9576ca70faSYuval Mintz } while (0) 9676ca70faSYuval Mintz 9776ca70faSYuval Mintz #define DP_AND(__mask, fmt, ...) \ 9876ca70faSYuval Mintz do { \ 9976ca70faSYuval Mintz if (unlikely((bp->msg_enable & (__mask)) == __mask)) \ 10076ca70faSYuval Mintz DP_INNER(fmt, ##__VA_ARGS__); \ 101adfc5217SJeff Kirsher } while (0) 102adfc5217SJeff Kirsher 103f1deab50SJoe Perches #define DP_CONT(__mask, fmt, ...) \ 104adfc5217SJeff Kirsher do { \ 10551c1a580SMerav Sicron if (unlikely(bp->msg_enable & (__mask))) \ 106f1deab50SJoe Perches pr_cont(fmt, ##__VA_ARGS__); \ 107adfc5217SJeff Kirsher } while (0) 108adfc5217SJeff Kirsher 109adfc5217SJeff Kirsher /* errors debug print */ 110f1deab50SJoe Perches #define BNX2X_DBG_ERR(fmt, ...) \ 111adfc5217SJeff Kirsher do { \ 11251c1a580SMerav Sicron if (unlikely(netif_msg_probe(bp))) \ 113f1deab50SJoe Perches pr_err("[%s:%d(%s)]" fmt, \ 114adfc5217SJeff Kirsher __func__, __LINE__, \ 115adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 116f1deab50SJoe Perches ##__VA_ARGS__); \ 117adfc5217SJeff Kirsher } while (0) 118adfc5217SJeff Kirsher 119adfc5217SJeff Kirsher /* for errors (never masked) */ 120f1deab50SJoe Perches #define BNX2X_ERR(fmt, ...) \ 121adfc5217SJeff Kirsher do { \ 122f1deab50SJoe Perches pr_err("[%s:%d(%s)]" fmt, \ 123adfc5217SJeff Kirsher __func__, __LINE__, \ 124adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \ 125f1deab50SJoe Perches ##__VA_ARGS__); \ 126adfc5217SJeff Kirsher } while (0) 127adfc5217SJeff Kirsher 128f1deab50SJoe Perches #define BNX2X_ERROR(fmt, ...) \ 129f1deab50SJoe Perches pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 130adfc5217SJeff Kirsher 131adfc5217SJeff Kirsher /* before we have a dev->name use dev_info() */ 132f1deab50SJoe Perches #define BNX2X_DEV_INFO(fmt, ...) \ 133adfc5217SJeff Kirsher do { \ 13451c1a580SMerav Sicron if (unlikely(netif_msg_probe(bp))) \ 135f1deab50SJoe Perches dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 136adfc5217SJeff Kirsher } while (0) 137adfc5217SJeff Kirsher 138ca9bdb9bSYuval Mintz /* Error handling */ 139ca9bdb9bSYuval Mintz void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); 140adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 141f1deab50SJoe Perches #define bnx2x_panic() \ 142f1deab50SJoe Perches do { \ 143adfc5217SJeff Kirsher bp->panic = 1; \ 144adfc5217SJeff Kirsher BNX2X_ERR("driver assert\n"); \ 145823e1d90SYuval Mintz bnx2x_panic_dump(bp, true); \ 146adfc5217SJeff Kirsher } while (0) 147adfc5217SJeff Kirsher #else 148f1deab50SJoe Perches #define bnx2x_panic() \ 149f1deab50SJoe Perches do { \ 150adfc5217SJeff Kirsher bp->panic = 1; \ 151adfc5217SJeff Kirsher BNX2X_ERR("driver assert\n"); \ 152823e1d90SYuval Mintz bnx2x_panic_dump(bp, false); \ 153adfc5217SJeff Kirsher } while (0) 154adfc5217SJeff Kirsher #endif 155adfc5217SJeff Kirsher 156adfc5217SJeff Kirsher #define bnx2x_mc_addr(ha) ((ha)->addr) 157adfc5217SJeff Kirsher #define bnx2x_uc_addr(ha) ((ha)->addr) 158adfc5217SJeff Kirsher 1592de67439SYuval Mintz #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 1602de67439SYuval Mintz #define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 161adfc5217SJeff Kirsher #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 162adfc5217SJeff Kirsher 163adfc5217SJeff Kirsher #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 164adfc5217SJeff Kirsher 165adfc5217SJeff Kirsher #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 166adfc5217SJeff Kirsher #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 167adfc5217SJeff Kirsher #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 168adfc5217SJeff Kirsher 1697f883c77SSinan Kaya #define REG_WR_RELAXED(bp, offset, val) \ 1707f883c77SSinan Kaya writel_relaxed((u32)val, REG_ADDR(bp, offset)) 1717f883c77SSinan Kaya 1727f883c77SSinan Kaya #define REG_WR16_RELAXED(bp, offset, val) \ 1737f883c77SSinan Kaya writew_relaxed((u16)val, REG_ADDR(bp, offset)) 1747f883c77SSinan Kaya 175adfc5217SJeff Kirsher #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 176adfc5217SJeff Kirsher #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 177adfc5217SJeff Kirsher #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 178adfc5217SJeff Kirsher 179adfc5217SJeff Kirsher #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 180adfc5217SJeff Kirsher #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 181adfc5217SJeff Kirsher 182adfc5217SJeff Kirsher #define REG_RD_DMAE(bp, offset, valp, len32) \ 183adfc5217SJeff Kirsher do { \ 184adfc5217SJeff Kirsher bnx2x_read_dmae(bp, offset, len32);\ 185adfc5217SJeff Kirsher memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 186adfc5217SJeff Kirsher } while (0) 187adfc5217SJeff Kirsher 188adfc5217SJeff Kirsher #define REG_WR_DMAE(bp, offset, valp, len32) \ 189adfc5217SJeff Kirsher do { \ 190adfc5217SJeff Kirsher memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 191adfc5217SJeff Kirsher bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 192adfc5217SJeff Kirsher offset, len32); \ 193adfc5217SJeff Kirsher } while (0) 194adfc5217SJeff Kirsher 195adfc5217SJeff Kirsher #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 196adfc5217SJeff Kirsher REG_WR_DMAE(bp, offset, valp, len32) 197adfc5217SJeff Kirsher 198adfc5217SJeff Kirsher #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 199adfc5217SJeff Kirsher do { \ 200adfc5217SJeff Kirsher memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 201adfc5217SJeff Kirsher bnx2x_write_big_buf_wb(bp, addr, len32); \ 202adfc5217SJeff Kirsher } while (0) 203adfc5217SJeff Kirsher 204adfc5217SJeff Kirsher #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 205adfc5217SJeff Kirsher offsetof(struct shmem_region, field)) 206adfc5217SJeff Kirsher #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 207adfc5217SJeff Kirsher #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 208adfc5217SJeff Kirsher 209adfc5217SJeff Kirsher #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 210adfc5217SJeff Kirsher offsetof(struct shmem2_region, field)) 211adfc5217SJeff Kirsher #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 212adfc5217SJeff Kirsher #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 213adfc5217SJeff Kirsher #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 214adfc5217SJeff Kirsher offsetof(struct mf_cfg, field)) 215adfc5217SJeff Kirsher #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 216adfc5217SJeff Kirsher offsetof(struct mf2_cfg, field)) 217adfc5217SJeff Kirsher 218adfc5217SJeff Kirsher #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 219adfc5217SJeff Kirsher #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 220adfc5217SJeff Kirsher MF_CFG_ADDR(bp, field), (val)) 221adfc5217SJeff Kirsher #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 222adfc5217SJeff Kirsher 223adfc5217SJeff Kirsher #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 224adfc5217SJeff Kirsher (SHMEM2_RD((bp), size) > \ 225adfc5217SJeff Kirsher offsetof(struct shmem2_region, field))) 226adfc5217SJeff Kirsher 227adfc5217SJeff Kirsher #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 228adfc5217SJeff Kirsher #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 229adfc5217SJeff Kirsher 230adfc5217SJeff Kirsher /* SP SB indices */ 231adfc5217SJeff Kirsher 232adfc5217SJeff Kirsher /* General SP events - stats query, cfc delete, etc */ 233adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_DEF_CONS 3 234adfc5217SJeff Kirsher 235adfc5217SJeff Kirsher /* EQ completions */ 236adfc5217SJeff Kirsher #define HC_SP_INDEX_EQ_CONS 7 237adfc5217SJeff Kirsher 238adfc5217SJeff Kirsher /* FCoE L2 connection completions */ 239adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 240adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 241adfc5217SJeff Kirsher /* iSCSI L2 */ 242adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 243adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 244adfc5217SJeff Kirsher 245adfc5217SJeff Kirsher /* Special clients parameters */ 246adfc5217SJeff Kirsher 247adfc5217SJeff Kirsher /* SB indices */ 248adfc5217SJeff Kirsher /* FCoE L2 */ 249adfc5217SJeff Kirsher #define BNX2X_FCOE_L2_RX_INDEX \ 250adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 251adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 252adfc5217SJeff Kirsher 253adfc5217SJeff Kirsher #define BNX2X_FCOE_L2_TX_INDEX \ 254adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 255adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 256adfc5217SJeff Kirsher 257adfc5217SJeff Kirsher /** 258adfc5217SJeff Kirsher * CIDs and CLIDs: 259adfc5217SJeff Kirsher * CLIDs below is a CLID for func 0, then the CLID for other 260adfc5217SJeff Kirsher * functions will be calculated by the formula: 261adfc5217SJeff Kirsher * 262adfc5217SJeff Kirsher * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 263adfc5217SJeff Kirsher * 264adfc5217SJeff Kirsher */ 2651805b2f0SDavid S. Miller enum { 2661805b2f0SDavid S. Miller BNX2X_ISCSI_ETH_CL_ID_IDX, 2671805b2f0SDavid S. Miller BNX2X_FCOE_ETH_CL_ID_IDX, 2681805b2f0SDavid S. Miller BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 2691805b2f0SDavid S. Miller }; 270adfc5217SJeff Kirsher 271f78afb35SMichael Chan /* use a value high enough to be above all the PFs, which has least significant 272f78afb35SMichael Chan * nibble as 8, so when cnic needs to come up with a CID for UIO to use to 273f78afb35SMichael Chan * calculate doorbell address according to old doorbell configuration scheme 274f78afb35SMichael Chan * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number 275f78afb35SMichael Chan * We must avoid coming up with cid 8 for iscsi since according to this method 276f78afb35SMichael Chan * the designated UIO cid will come out 0 and it has a special handling for that 277f78afb35SMichael Chan * case which doesn't suit us. Therefore will will cieling to closes cid which 278f78afb35SMichael Chan * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18. 279f78afb35SMichael Chan */ 280f78afb35SMichael Chan 281f78afb35SMichael Chan #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \ 28237ae41a9SMerav Sicron (bp)->max_cos) 283f78afb35SMichael Chan /* amount of cids traversed by UIO's DPM addition to doorbell */ 284f78afb35SMichael Chan #define UIO_DPM 8 285f78afb35SMichael Chan /* roundup to DPM offset */ 286f78afb35SMichael Chan #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \ 287f78afb35SMichael Chan UIO_DPM)) 288f78afb35SMichael Chan /* offset to nearest value which has lsb nibble matching DPM */ 289f78afb35SMichael Chan #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \ 290f78afb35SMichael Chan (UIO_DPM * 2)) 291f78afb35SMichael Chan /* add offset to rounded-up cid to get a value which could be used with UIO */ 292f78afb35SMichael Chan #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp)) 293f78afb35SMichael Chan /* but wait - avoid UIO special case for cid 0 */ 294f78afb35SMichael Chan #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \ 295f78afb35SMichael Chan (UIO_DPM_ALIGN(bp) == UIO_DPM)) 296f78afb35SMichael Chan /* Properly DPM aligned CID dajusted to cid 0 secal case */ 297f78afb35SMichael Chan #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \ 298f78afb35SMichael Chan (UIO_DPM_CID0_OFFSET(bp))) 299f78afb35SMichael Chan /* how many cids were wasted - need this value for cid allocation */ 300f78afb35SMichael Chan #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \ 301f78afb35SMichael Chan BNX2X_1st_NON_L2_ETH_CID(bp)) 3021805b2f0SDavid S. Miller /* iSCSI L2 */ 30337ae41a9SMerav Sicron #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 304adfc5217SJeff Kirsher /* FCoE L2 */ 30537ae41a9SMerav Sicron #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 306adfc5217SJeff Kirsher 30755c11941SMerav Sicron #define CNIC_SUPPORT(bp) ((bp)->cnic_support) 30855c11941SMerav Sicron #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 30955c11941SMerav Sicron #define CNIC_LOADED(bp) ((bp)->cnic_loaded) 31055c11941SMerav Sicron #define FCOE_INIT(bp) ((bp)->fcoe_init) 311adfc5217SJeff Kirsher 312adfc5217SJeff Kirsher #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 313adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 314adfc5217SJeff Kirsher 315adfc5217SJeff Kirsher #define SM_RX_ID 0 316adfc5217SJeff Kirsher #define SM_TX_ID 1 317adfc5217SJeff Kirsher 318adfc5217SJeff Kirsher /* defines for multiple tx priority indices */ 319adfc5217SJeff Kirsher #define FIRST_TX_ONLY_COS_INDEX 1 320adfc5217SJeff Kirsher #define FIRST_TX_COS_INDEX 0 321adfc5217SJeff Kirsher 322adfc5217SJeff Kirsher /* rules for calculating the cids of tx-only connections */ 32365565884SMerav Sicron #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 32465565884SMerav Sicron #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 32565565884SMerav Sicron (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 326adfc5217SJeff Kirsher 327adfc5217SJeff Kirsher /* fp index inside class of service range */ 32865565884SMerav Sicron #define FP_COS_TO_TXQ(fp, cos, bp) \ 32965565884SMerav Sicron ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 330adfc5217SJeff Kirsher 33165565884SMerav Sicron /* Indexes for transmission queues array: 33265565884SMerav Sicron * txdata for RSS i CoS j is at location i + (j * num of RSS) 33365565884SMerav Sicron * txdata for FCoE (if exist) is at location max cos * num of RSS 33465565884SMerav Sicron * txdata for FWD (if exist) is one location after FCoE 33565565884SMerav Sicron * txdata for OOO (if exist) is one location after FWD 336adfc5217SJeff Kirsher */ 33765565884SMerav Sicron enum { 33865565884SMerav Sicron FCOE_TXQ_IDX_OFFSET, 33965565884SMerav Sicron FWD_TXQ_IDX_OFFSET, 34065565884SMerav Sicron OOO_TXQ_IDX_OFFSET, 34165565884SMerav Sicron }; 34265565884SMerav Sicron #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 34365565884SMerav Sicron #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 344adfc5217SJeff Kirsher 345adfc5217SJeff Kirsher /* fast path */ 346e52fcb24SEric Dumazet /* 347e52fcb24SEric Dumazet * This driver uses new build_skb() API : 348e52fcb24SEric Dumazet * RX ring buffer contains pointer to kmalloc() data only, 349e52fcb24SEric Dumazet * skb are built only after Hardware filled the frame. 350e52fcb24SEric Dumazet */ 351adfc5217SJeff Kirsher struct sw_rx_bd { 352e52fcb24SEric Dumazet u8 *data; 353adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping); 354adfc5217SJeff Kirsher }; 355adfc5217SJeff Kirsher 356adfc5217SJeff Kirsher struct sw_tx_bd { 357adfc5217SJeff Kirsher struct sk_buff *skb; 358adfc5217SJeff Kirsher u16 first_bd; 359adfc5217SJeff Kirsher u8 flags; 360adfc5217SJeff Kirsher /* Set on the first BD descriptor when there is a split BD */ 361adfc5217SJeff Kirsher #define BNX2X_TSO_SPLIT_BD (1<<0) 362fe26566dSDmitry Kravkov #define BNX2X_HAS_SECOND_PBD (1<<1) 363adfc5217SJeff Kirsher }; 364adfc5217SJeff Kirsher 365adfc5217SJeff Kirsher struct sw_rx_page { 366adfc5217SJeff Kirsher struct page *page; 367adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping); 3684cace675SGabriel Krisman Bertazi unsigned int offset; 369adfc5217SJeff Kirsher }; 370adfc5217SJeff Kirsher 371adfc5217SJeff Kirsher union db_prod { 372adfc5217SJeff Kirsher struct doorbell_set_prod data; 373adfc5217SJeff Kirsher u32 raw; 374adfc5217SJeff Kirsher }; 375adfc5217SJeff Kirsher 3768decf868SDavid S. Miller /* dropless fc FW/HW related params */ 3778decf868SDavid S. Miller #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 3788decf868SDavid S. Miller #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 3798decf868SDavid S. Miller ETH_MAX_AGGREGATION_QUEUES_E1 :\ 3808decf868SDavid S. Miller ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 3818decf868SDavid S. Miller #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 3828decf868SDavid S. Miller #define FW_PREFETCH_CNT 16 3838decf868SDavid S. Miller #define DROPLESS_FC_HEADROOM 100 384adfc5217SJeff Kirsher 385adfc5217SJeff Kirsher /* MC hsi */ 386adfc5217SJeff Kirsher #define BCM_PAGE_SHIFT 12 387adfc5217SJeff Kirsher #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 388adfc5217SJeff Kirsher #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 389adfc5217SJeff Kirsher #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 390adfc5217SJeff Kirsher 391adfc5217SJeff Kirsher #define PAGES_PER_SGE_SHIFT 0 392adfc5217SJeff Kirsher #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 3934cace675SGabriel Krisman Bertazi #define SGE_PAGE_SHIFT 12 3944cace675SGabriel Krisman Bertazi #define SGE_PAGE_SIZE (1 << SGE_PAGE_SHIFT) 3954cace675SGabriel Krisman Bertazi #define SGE_PAGE_MASK (~(SGE_PAGE_SIZE - 1)) 3964cace675SGabriel Krisman Bertazi #define SGE_PAGE_ALIGN(addr) (((addr) + SGE_PAGE_SIZE - 1) & SGE_PAGE_MASK) 3978d9ac297SAriel Elior #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 3988d9ac297SAriel Elior #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 3998d9ac297SAriel Elior SGE_PAGES), 0xffff) 400adfc5217SJeff Kirsher 401adfc5217SJeff Kirsher /* SGE ring related macros */ 402adfc5217SJeff Kirsher #define NUM_RX_SGE_PAGES 2 403adfc5217SJeff Kirsher #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 4048decf868SDavid S. Miller #define NEXT_PAGE_SGE_DESC_CNT 2 4058decf868SDavid S. Miller #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 406adfc5217SJeff Kirsher /* RX_SGE_CNT is promised to be a power of 2 */ 407adfc5217SJeff Kirsher #define RX_SGE_MASK (RX_SGE_CNT - 1) 408adfc5217SJeff Kirsher #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 409adfc5217SJeff Kirsher #define MAX_RX_SGE (NUM_RX_SGE - 1) 410adfc5217SJeff Kirsher #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 4118decf868SDavid S. Miller (MAX_RX_SGE_CNT - 1)) ? \ 4128decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 4138decf868SDavid S. Miller (x) + 1) 414adfc5217SJeff Kirsher #define RX_SGE(x) ((x) & MAX_RX_SGE) 415adfc5217SJeff Kirsher 4168decf868SDavid S. Miller /* 4178decf868SDavid S. Miller * Number of required SGEs is the sum of two: 4188decf868SDavid S. Miller * 1. Number of possible opened aggregations (next packet for 41916a5fd92SYuval Mintz * these aggregations will probably consume SGE immediately) 4208decf868SDavid S. Miller * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 4218decf868SDavid S. Miller * after placement on BD for new TPA aggregation) 4228decf868SDavid S. Miller * 4238decf868SDavid S. Miller * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 4248decf868SDavid S. Miller */ 4258decf868SDavid S. Miller #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 4268decf868SDavid S. Miller (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 4278decf868SDavid S. Miller #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 4288decf868SDavid S. Miller MAX_RX_SGE_CNT) 4298decf868SDavid S. Miller #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 4308decf868SDavid S. Miller NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 4318decf868SDavid S. Miller #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 4328decf868SDavid S. Miller 433adfc5217SJeff Kirsher /* Manipulate a bit vector defined as an array of u64 */ 434adfc5217SJeff Kirsher 435adfc5217SJeff Kirsher /* Number of bits in one sge_mask array element */ 436adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_SZ 64 437adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_SHIFT 6 438adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 439adfc5217SJeff Kirsher 440adfc5217SJeff Kirsher #define __BIT_VEC64_SET_BIT(el, bit) \ 441adfc5217SJeff Kirsher do { \ 442adfc5217SJeff Kirsher el = ((el) | ((u64)0x1 << (bit))); \ 443adfc5217SJeff Kirsher } while (0) 444adfc5217SJeff Kirsher 445adfc5217SJeff Kirsher #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 446adfc5217SJeff Kirsher do { \ 447adfc5217SJeff Kirsher el = ((el) & (~((u64)0x1 << (bit)))); \ 448adfc5217SJeff Kirsher } while (0) 449adfc5217SJeff Kirsher 450adfc5217SJeff Kirsher #define BIT_VEC64_SET_BIT(vec64, idx) \ 451adfc5217SJeff Kirsher __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 452adfc5217SJeff Kirsher (idx) & BIT_VEC64_ELEM_MASK) 453adfc5217SJeff Kirsher 454adfc5217SJeff Kirsher #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 455adfc5217SJeff Kirsher __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 456adfc5217SJeff Kirsher (idx) & BIT_VEC64_ELEM_MASK) 457adfc5217SJeff Kirsher 458adfc5217SJeff Kirsher #define BIT_VEC64_TEST_BIT(vec64, idx) \ 459adfc5217SJeff Kirsher (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 460adfc5217SJeff Kirsher ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 461adfc5217SJeff Kirsher 462adfc5217SJeff Kirsher /* Creates a bitmask of all ones in less significant bits. 463adfc5217SJeff Kirsher idx - index of the most significant bit in the created mask */ 464adfc5217SJeff Kirsher #define BIT_VEC64_ONES_MASK(idx) \ 465adfc5217SJeff Kirsher (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 466adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 467adfc5217SJeff Kirsher 468adfc5217SJeff Kirsher /*******************************************************/ 469adfc5217SJeff Kirsher 470adfc5217SJeff Kirsher /* Number of u64 elements in SGE mask array */ 471b3637827SDmitry Kravkov #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 472adfc5217SJeff Kirsher #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 473adfc5217SJeff Kirsher #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 474adfc5217SJeff Kirsher 475adfc5217SJeff Kirsher union host_hc_status_block { 476adfc5217SJeff Kirsher /* pointer to fp status block e1x */ 477adfc5217SJeff Kirsher struct host_hc_status_block_e1x *e1x_sb; 478adfc5217SJeff Kirsher /* pointer to fp status block e2 */ 479adfc5217SJeff Kirsher struct host_hc_status_block_e2 *e2_sb; 480adfc5217SJeff Kirsher }; 481adfc5217SJeff Kirsher 482adfc5217SJeff Kirsher struct bnx2x_agg_info { 483adfc5217SJeff Kirsher /* 484e52fcb24SEric Dumazet * First aggregation buffer is a data buffer, the following - are pages. 485e52fcb24SEric Dumazet * We will preallocate the data buffer for each aggregation when 486adfc5217SJeff Kirsher * we open the interface and will replace the BD at the consumer 487adfc5217SJeff Kirsher * with this one when we receive the TPA_START CQE in order to 488adfc5217SJeff Kirsher * keep the Rx BD ring consistent. 489adfc5217SJeff Kirsher */ 490adfc5217SJeff Kirsher struct sw_rx_bd first_buf; 491adfc5217SJeff Kirsher u8 tpa_state; 492adfc5217SJeff Kirsher #define BNX2X_TPA_START 1 493adfc5217SJeff Kirsher #define BNX2X_TPA_STOP 2 494adfc5217SJeff Kirsher #define BNX2X_TPA_ERROR 3 495adfc5217SJeff Kirsher u8 placement_offset; 496adfc5217SJeff Kirsher u16 parsing_flags; 497adfc5217SJeff Kirsher u16 vlan_tag; 498adfc5217SJeff Kirsher u16 len_on_bd; 499e52fcb24SEric Dumazet u32 rxhash; 5005495ab75STom Herbert enum pkt_hash_types rxhash_type; 501621b4d66SDmitry Kravkov u16 gro_size; 502621b4d66SDmitry Kravkov u16 full_page; 503adfc5217SJeff Kirsher }; 504adfc5217SJeff Kirsher 505adfc5217SJeff Kirsher #define Q_STATS_OFFSET32(stat_name) \ 506adfc5217SJeff Kirsher (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 507adfc5217SJeff Kirsher 508adfc5217SJeff Kirsher struct bnx2x_fp_txdata { 509adfc5217SJeff Kirsher 510adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf_ring; 511adfc5217SJeff Kirsher 512adfc5217SJeff Kirsher union eth_tx_bd_types *tx_desc_ring; 513adfc5217SJeff Kirsher dma_addr_t tx_desc_mapping; 514adfc5217SJeff Kirsher 515adfc5217SJeff Kirsher u32 cid; 516adfc5217SJeff Kirsher 517adfc5217SJeff Kirsher union db_prod tx_db; 518adfc5217SJeff Kirsher 519adfc5217SJeff Kirsher u16 tx_pkt_prod; 520adfc5217SJeff Kirsher u16 tx_pkt_cons; 521adfc5217SJeff Kirsher u16 tx_bd_prod; 522adfc5217SJeff Kirsher u16 tx_bd_cons; 523adfc5217SJeff Kirsher 524adfc5217SJeff Kirsher unsigned long tx_pkt; 525adfc5217SJeff Kirsher 526adfc5217SJeff Kirsher __le16 *tx_cons_sb; 527adfc5217SJeff Kirsher 528adfc5217SJeff Kirsher int txq_index; 52965565884SMerav Sicron struct bnx2x_fastpath *parent_fp; 53065565884SMerav Sicron int tx_ring_size; 531adfc5217SJeff Kirsher }; 532adfc5217SJeff Kirsher 533621b4d66SDmitry Kravkov enum bnx2x_tpa_mode_t { 5347e6b4d44SMichal Schmidt TPA_MODE_DISABLED, 535621b4d66SDmitry Kravkov TPA_MODE_LRO, 536621b4d66SDmitry Kravkov TPA_MODE_GRO 537621b4d66SDmitry Kravkov }; 538621b4d66SDmitry Kravkov 5394cace675SGabriel Krisman Bertazi struct bnx2x_alloc_pool { 5404cace675SGabriel Krisman Bertazi struct page *page; 5414cace675SGabriel Krisman Bertazi unsigned int offset; 5424cace675SGabriel Krisman Bertazi }; 5434cace675SGabriel Krisman Bertazi 544adfc5217SJeff Kirsher struct bnx2x_fastpath { 545adfc5217SJeff Kirsher struct bnx2x *bp; /* parent */ 546adfc5217SJeff Kirsher 547adfc5217SJeff Kirsher struct napi_struct napi; 5488f20aa57SDmitry Kravkov 549adfc5217SJeff Kirsher union host_hc_status_block status_blk; 55016a5fd92SYuval Mintz /* chip independent shortcuts into sb structure */ 551adfc5217SJeff Kirsher __le16 *sb_index_values; 552adfc5217SJeff Kirsher __le16 *sb_running_index; 55316a5fd92SYuval Mintz /* chip independent shortcut into rx_prods_offset memory */ 554adfc5217SJeff Kirsher u32 ustorm_rx_prods_offset; 555adfc5217SJeff Kirsher 556adfc5217SJeff Kirsher u32 rx_buf_size; 557d46d132cSEric Dumazet u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 558adfc5217SJeff Kirsher dma_addr_t status_blk_mapping; 559adfc5217SJeff Kirsher 560621b4d66SDmitry Kravkov enum bnx2x_tpa_mode_t mode; 561621b4d66SDmitry Kravkov 562adfc5217SJeff Kirsher u8 max_cos; /* actual number of active tx coses */ 56365565884SMerav Sicron struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 564adfc5217SJeff Kirsher 565adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 566adfc5217SJeff Kirsher struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 567adfc5217SJeff Kirsher 568adfc5217SJeff Kirsher struct eth_rx_bd *rx_desc_ring; 569adfc5217SJeff Kirsher dma_addr_t rx_desc_mapping; 570adfc5217SJeff Kirsher 571adfc5217SJeff Kirsher union eth_rx_cqe *rx_comp_ring; 572adfc5217SJeff Kirsher dma_addr_t rx_comp_mapping; 573adfc5217SJeff Kirsher 574adfc5217SJeff Kirsher /* SGE ring */ 575adfc5217SJeff Kirsher struct eth_rx_sge *rx_sge_ring; 576adfc5217SJeff Kirsher dma_addr_t rx_sge_mapping; 577adfc5217SJeff Kirsher 578adfc5217SJeff Kirsher u64 sge_mask[RX_SGE_MASK_LEN]; 579adfc5217SJeff Kirsher 580adfc5217SJeff Kirsher u32 cid; 581adfc5217SJeff Kirsher 582adfc5217SJeff Kirsher __le16 fp_hc_idx; 583adfc5217SJeff Kirsher 584adfc5217SJeff Kirsher u8 index; /* number in fp array */ 585f233cafeSDmitry Kravkov u8 rx_queue; /* index for skb_record */ 586adfc5217SJeff Kirsher u8 cl_id; /* eth client id */ 587adfc5217SJeff Kirsher u8 cl_qzone_id; 588adfc5217SJeff Kirsher u8 fw_sb_id; /* status block number in FW */ 589adfc5217SJeff Kirsher u8 igu_sb_id; /* status block number in HW */ 590adfc5217SJeff Kirsher 591adfc5217SJeff Kirsher u16 rx_bd_prod; 592adfc5217SJeff Kirsher u16 rx_bd_cons; 593adfc5217SJeff Kirsher u16 rx_comp_prod; 594adfc5217SJeff Kirsher u16 rx_comp_cons; 595adfc5217SJeff Kirsher u16 rx_sge_prod; 596adfc5217SJeff Kirsher /* The last maximal completed SGE */ 597adfc5217SJeff Kirsher u16 last_max_sge; 598adfc5217SJeff Kirsher __le16 *rx_cons_sb; 599adfc5217SJeff Kirsher 600adfc5217SJeff Kirsher /* TPA related */ 60115192a8cSBarak Witkowski struct bnx2x_agg_info *tpa_info; 602adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR 603adfc5217SJeff Kirsher u64 tpa_queue_used; 604adfc5217SJeff Kirsher #endif 605adfc5217SJeff Kirsher /* The size is calculated using the following: 606adfc5217SJeff Kirsher sizeof name field from netdev structure + 607adfc5217SJeff Kirsher 4 ('-Xx-' string) + 608adfc5217SJeff Kirsher 4 (for the digits and to make it DWORD aligned) */ 609adfc5217SJeff Kirsher #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 610adfc5217SJeff Kirsher char name[FP_NAME_SIZE]; 6114cace675SGabriel Krisman Bertazi 6124cace675SGabriel Krisman Bertazi struct bnx2x_alloc_pool page_pool; 613adfc5217SJeff Kirsher }; 614adfc5217SJeff Kirsher 61515192a8cSBarak Witkowski #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 61615192a8cSBarak Witkowski #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 61715192a8cSBarak Witkowski #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 61815192a8cSBarak Witkowski #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 619adfc5217SJeff Kirsher 620adfc5217SJeff Kirsher /* Use 2500 as a mini-jumbo MTU for FCoE */ 621adfc5217SJeff Kirsher #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 622adfc5217SJeff Kirsher 62365565884SMerav Sicron #define FCOE_IDX_OFFSET 0 62465565884SMerav Sicron 62565565884SMerav Sicron #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 62665565884SMerav Sicron FCOE_IDX_OFFSET) 62765565884SMerav Sicron #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 628adfc5217SJeff Kirsher #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 62915192a8cSBarak Witkowski #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 63015192a8cSBarak Witkowski #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 631adfc5217SJeff Kirsher #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 63265565884SMerav Sicron txdata_ptr[FIRST_TX_COS_INDEX] \ 63365565884SMerav Sicron ->var) 634adfc5217SJeff Kirsher 63555c11941SMerav Sicron #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 63655c11941SMerav Sicron #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 63765565884SMerav Sicron #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 638adfc5217SJeff Kirsher 639adfc5217SJeff Kirsher /* MC hsi */ 640adfc5217SJeff Kirsher #define MAX_FETCH_BD 13 /* HW max BDs per packet */ 641adfc5217SJeff Kirsher #define RX_COPY_THRESH 92 642adfc5217SJeff Kirsher 643adfc5217SJeff Kirsher #define NUM_TX_RINGS 16 644adfc5217SJeff Kirsher #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 6458decf868SDavid S. Miller #define NEXT_PAGE_TX_DESC_CNT 1 6468decf868SDavid S. Miller #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 647adfc5217SJeff Kirsher #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 648adfc5217SJeff Kirsher #define MAX_TX_BD (NUM_TX_BD - 1) 649adfc5217SJeff Kirsher #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 650adfc5217SJeff Kirsher #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 6518decf868SDavid S. Miller (MAX_TX_DESC_CNT - 1)) ? \ 6528decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 6538decf868SDavid S. Miller (x) + 1) 654adfc5217SJeff Kirsher #define TX_BD(x) ((x) & MAX_TX_BD) 655adfc5217SJeff Kirsher #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 656adfc5217SJeff Kirsher 6577df2dc6bSDmitry Kravkov /* number of NEXT_PAGE descriptors may be required during placement */ 6587df2dc6bSDmitry Kravkov #define NEXT_CNT_PER_TX_PKT(bds) \ 6597df2dc6bSDmitry Kravkov (((bds) + MAX_TX_DESC_CNT - 1) / \ 6607df2dc6bSDmitry Kravkov MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 6617df2dc6bSDmitry Kravkov /* max BDs per tx packet w/o next_pages: 6627df2dc6bSDmitry Kravkov * START_BD - describes packed 6637df2dc6bSDmitry Kravkov * START_BD(splitted) - includes unpaged data segment for GSO 6647df2dc6bSDmitry Kravkov * PARSING_BD - for TSO and CSUM data 665a848ade4SDmitry Kravkov * PARSING_BD2 - for encapsulation data 66616a5fd92SYuval Mintz * Frag BDs - describes pages for frags 6677df2dc6bSDmitry Kravkov */ 668a848ade4SDmitry Kravkov #define BDS_PER_TX_PKT 4 6697df2dc6bSDmitry Kravkov #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 6707df2dc6bSDmitry Kravkov /* max BDs per tx packet including next pages */ 6717df2dc6bSDmitry Kravkov #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 6727df2dc6bSDmitry Kravkov NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 6737df2dc6bSDmitry Kravkov 674adfc5217SJeff Kirsher /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 675adfc5217SJeff Kirsher #define NUM_RX_RINGS 8 676adfc5217SJeff Kirsher #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 6778decf868SDavid S. Miller #define NEXT_PAGE_RX_DESC_CNT 2 6788decf868SDavid S. Miller #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 679adfc5217SJeff Kirsher #define RX_DESC_MASK (RX_DESC_CNT - 1) 680adfc5217SJeff Kirsher #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 681adfc5217SJeff Kirsher #define MAX_RX_BD (NUM_RX_BD - 1) 682adfc5217SJeff Kirsher #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 6838decf868SDavid S. Miller 6848decf868SDavid S. Miller /* dropless fc calculations for BDs 6858decf868SDavid S. Miller * 6868decf868SDavid S. Miller * Number of BDs should as number of buffers in BRB: 6878decf868SDavid S. Miller * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 6888decf868SDavid S. Miller * "next" elements on each page 6898decf868SDavid S. Miller */ 6908decf868SDavid S. Miller #define NUM_BD_REQ BRB_SIZE(bp) 6918decf868SDavid S. Miller #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 6928decf868SDavid S. Miller MAX_RX_DESC_CNT) 6938decf868SDavid S. Miller #define BD_TH_LO(bp) (NUM_BD_REQ + \ 6948decf868SDavid S. Miller NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 6958decf868SDavid S. Miller FW_DROP_LEVEL(bp)) 6968decf868SDavid S. Miller #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 6978decf868SDavid S. Miller 6988decf868SDavid S. Miller #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 699adfc5217SJeff Kirsher 700adfc5217SJeff Kirsher #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 701adfc5217SJeff Kirsher ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 702adfc5217SJeff Kirsher ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 703adfc5217SJeff Kirsher #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 704adfc5217SJeff Kirsher #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 705adfc5217SJeff Kirsher #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 706adfc5217SJeff Kirsher MIN_RX_AVAIL)) 707adfc5217SJeff Kirsher 708adfc5217SJeff Kirsher #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 7098decf868SDavid S. Miller (MAX_RX_DESC_CNT - 1)) ? \ 7108decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 7118decf868SDavid S. Miller (x) + 1) 712adfc5217SJeff Kirsher #define RX_BD(x) ((x) & MAX_RX_BD) 713adfc5217SJeff Kirsher 714adfc5217SJeff Kirsher /* 715adfc5217SJeff Kirsher * As long as CQE is X times bigger than BD entry we have to allocate X times 716adfc5217SJeff Kirsher * more pages for CQ ring in order to keep it balanced with BD ring 717adfc5217SJeff Kirsher */ 718adfc5217SJeff Kirsher #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 719adfc5217SJeff Kirsher #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 720adfc5217SJeff Kirsher #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 7218decf868SDavid S. Miller #define NEXT_PAGE_RCQ_DESC_CNT 1 7228decf868SDavid S. Miller #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 723adfc5217SJeff Kirsher #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 724adfc5217SJeff Kirsher #define MAX_RCQ_BD (NUM_RCQ_BD - 1) 725adfc5217SJeff Kirsher #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 726adfc5217SJeff Kirsher #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 7278decf868SDavid S. Miller (MAX_RCQ_DESC_CNT - 1)) ? \ 7288decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 7298decf868SDavid S. Miller (x) + 1) 730adfc5217SJeff Kirsher #define RCQ_BD(x) ((x) & MAX_RCQ_BD) 731adfc5217SJeff Kirsher 7328decf868SDavid S. Miller /* dropless fc calculations for RCQs 7338decf868SDavid S. Miller * 7348decf868SDavid S. Miller * Number of RCQs should be as number of buffers in BRB: 7358decf868SDavid S. Miller * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 7368decf868SDavid S. Miller * "next" elements on each page 7378decf868SDavid S. Miller */ 7388decf868SDavid S. Miller #define NUM_RCQ_REQ BRB_SIZE(bp) 7398decf868SDavid S. Miller #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 7408decf868SDavid S. Miller MAX_RCQ_DESC_CNT) 7418decf868SDavid S. Miller #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 7428decf868SDavid S. Miller NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 7438decf868SDavid S. Miller FW_DROP_LEVEL(bp)) 7448decf868SDavid S. Miller #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 7458decf868SDavid S. Miller 746adfc5217SJeff Kirsher /* This is needed for determining of last_max */ 747adfc5217SJeff Kirsher #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 748adfc5217SJeff Kirsher #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 749adfc5217SJeff Kirsher 750adfc5217SJeff Kirsher #define BNX2X_SWCID_SHIFT 17 751adfc5217SJeff Kirsher #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 752adfc5217SJeff Kirsher 753adfc5217SJeff Kirsher /* used on a CID received from the HW */ 754adfc5217SJeff Kirsher #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 755adfc5217SJeff Kirsher #define CQE_CMD(x) (le32_to_cpu(x) >> \ 756adfc5217SJeff Kirsher COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 757adfc5217SJeff Kirsher 758adfc5217SJeff Kirsher #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 759adfc5217SJeff Kirsher le32_to_cpu((bd)->addr_lo)) 760adfc5217SJeff Kirsher #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 761adfc5217SJeff Kirsher 762adfc5217SJeff Kirsher #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 763b9871bcfSAriel Elior #define BNX2X_DB_SHIFT 3 /* 8 bytes*/ 764adfc5217SJeff Kirsher #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 765adfc5217SJeff Kirsher #error "Min DB doorbell stride is 8" 766adfc5217SJeff Kirsher #endif 7677f883c77SSinan Kaya #define DOORBELL_RELAXED(bp, cid, val) \ 7687f883c77SSinan Kaya writel_relaxed((u32)(val), (bp)->doorbells + ((bp)->db_size * (cid))) 769adfc5217SJeff Kirsher 770adfc5217SJeff Kirsher /* TX CSUM helpers */ 771adfc5217SJeff Kirsher #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 772adfc5217SJeff Kirsher skb->csum_offset) 773adfc5217SJeff Kirsher #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 774adfc5217SJeff Kirsher skb->csum_offset)) 775adfc5217SJeff Kirsher 77691226790SDmitry Kravkov #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) 777adfc5217SJeff Kirsher 778adfc5217SJeff Kirsher #define XMIT_PLAIN 0 779a848ade4SDmitry Kravkov #define XMIT_CSUM_V4 (1 << 0) 780a848ade4SDmitry Kravkov #define XMIT_CSUM_V6 (1 << 1) 781a848ade4SDmitry Kravkov #define XMIT_CSUM_TCP (1 << 2) 782a848ade4SDmitry Kravkov #define XMIT_GSO_V4 (1 << 3) 783a848ade4SDmitry Kravkov #define XMIT_GSO_V6 (1 << 4) 784a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC_V4 (1 << 5) 785a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC_V6 (1 << 6) 786a848ade4SDmitry Kravkov #define XMIT_GSO_ENC_V4 (1 << 7) 787a848ade4SDmitry Kravkov #define XMIT_GSO_ENC_V6 (1 << 8) 788adfc5217SJeff Kirsher 789a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) 790a848ade4SDmitry Kravkov #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) 791adfc5217SJeff Kirsher 792a848ade4SDmitry Kravkov #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) 793a848ade4SDmitry Kravkov #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) 794adfc5217SJeff Kirsher 795adfc5217SJeff Kirsher /* stuff added to make the code fit 80Col */ 796adfc5217SJeff Kirsher #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 797adfc5217SJeff Kirsher #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 798adfc5217SJeff Kirsher #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 799adfc5217SJeff Kirsher #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 800adfc5217SJeff Kirsher #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 801adfc5217SJeff Kirsher 802adfc5217SJeff Kirsher #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 803adfc5217SJeff Kirsher 804adfc5217SJeff Kirsher #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 805adfc5217SJeff Kirsher (((le16_to_cpu(flags) & \ 806adfc5217SJeff Kirsher PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 807adfc5217SJeff Kirsher PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 808adfc5217SJeff Kirsher == PRS_FLAG_OVERETH_IPV4) 809adfc5217SJeff Kirsher #define BNX2X_RX_SUM_FIX(cqe) \ 810adfc5217SJeff Kirsher BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 811adfc5217SJeff Kirsher 812adfc5217SJeff Kirsher #define FP_USB_FUNC_OFF \ 813adfc5217SJeff Kirsher offsetof(struct cstorm_status_block_u, func) 814adfc5217SJeff Kirsher #define FP_CSB_FUNC_OFF \ 815adfc5217SJeff Kirsher offsetof(struct cstorm_status_block_c, func) 816adfc5217SJeff Kirsher 8178decf868SDavid S. Miller #define HC_INDEX_ETH_RX_CQ_CONS 1 818adfc5217SJeff Kirsher 8198decf868SDavid S. Miller #define HC_INDEX_OOO_TX_CQ_CONS 4 8208decf868SDavid S. Miller 8218decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 8228decf868SDavid S. Miller 8238decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 8248decf868SDavid S. Miller 8258decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 826adfc5217SJeff Kirsher 827adfc5217SJeff Kirsher #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 828adfc5217SJeff Kirsher 829adfc5217SJeff Kirsher #define BNX2X_RX_SB_INDEX \ 830adfc5217SJeff Kirsher (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 831adfc5217SJeff Kirsher 832adfc5217SJeff Kirsher #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 833adfc5217SJeff Kirsher 834adfc5217SJeff Kirsher #define BNX2X_TX_SB_INDEX_COS0 \ 835adfc5217SJeff Kirsher (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 836adfc5217SJeff Kirsher 837adfc5217SJeff Kirsher /* end of fast path */ 838adfc5217SJeff Kirsher 839adfc5217SJeff Kirsher /* common */ 840adfc5217SJeff Kirsher 841adfc5217SJeff Kirsher struct bnx2x_common { 842adfc5217SJeff Kirsher 843adfc5217SJeff Kirsher u32 chip_id; 844adfc5217SJeff Kirsher /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 845adfc5217SJeff Kirsher #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 846adfc5217SJeff Kirsher 847adfc5217SJeff Kirsher #define CHIP_NUM(bp) (bp->common.chip_id >> 16) 848adfc5217SJeff Kirsher #define CHIP_NUM_57710 0x164e 849adfc5217SJeff Kirsher #define CHIP_NUM_57711 0x164f 850adfc5217SJeff Kirsher #define CHIP_NUM_57711E 0x1650 851adfc5217SJeff Kirsher #define CHIP_NUM_57712 0x1662 852adfc5217SJeff Kirsher #define CHIP_NUM_57712_MF 0x1663 8538395be5eSAriel Elior #define CHIP_NUM_57712_VF 0x166f 854adfc5217SJeff Kirsher #define CHIP_NUM_57713 0x1651 855adfc5217SJeff Kirsher #define CHIP_NUM_57713E 0x1652 856adfc5217SJeff Kirsher #define CHIP_NUM_57800 0x168a 857adfc5217SJeff Kirsher #define CHIP_NUM_57800_MF 0x16a5 8588395be5eSAriel Elior #define CHIP_NUM_57800_VF 0x16a9 859adfc5217SJeff Kirsher #define CHIP_NUM_57810 0x168e 860adfc5217SJeff Kirsher #define CHIP_NUM_57810_MF 0x16ae 8618395be5eSAriel Elior #define CHIP_NUM_57810_VF 0x16af 8627e8e02dfSBarak Witkowski #define CHIP_NUM_57811 0x163d 8637e8e02dfSBarak Witkowski #define CHIP_NUM_57811_MF 0x163e 8648395be5eSAriel Elior #define CHIP_NUM_57811_VF 0x163f 865c3def943SYuval Mintz #define CHIP_NUM_57840_OBSOLETE 0x168d 866c3def943SYuval Mintz #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 867c3def943SYuval Mintz #define CHIP_NUM_57840_4_10 0x16a1 868c3def943SYuval Mintz #define CHIP_NUM_57840_2_20 0x16a2 869c3def943SYuval Mintz #define CHIP_NUM_57840_MF 0x16a4 8708395be5eSAriel Elior #define CHIP_NUM_57840_VF 0x16ad 871adfc5217SJeff Kirsher #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 872adfc5217SJeff Kirsher #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 873adfc5217SJeff Kirsher #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 874adfc5217SJeff Kirsher #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 8758395be5eSAriel Elior #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 876adfc5217SJeff Kirsher #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 877adfc5217SJeff Kirsher #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 878adfc5217SJeff Kirsher #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 8798395be5eSAriel Elior #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 880adfc5217SJeff Kirsher #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 881adfc5217SJeff Kirsher #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 8828395be5eSAriel Elior #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 8837e8e02dfSBarak Witkowski #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 8847e8e02dfSBarak Witkowski #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 8858395be5eSAriel Elior #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 886c3def943SYuval Mintz #define CHIP_IS_57840(bp) \ 887c3def943SYuval Mintz ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 888c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 889c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 890c3def943SYuval Mintz #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 891c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 8928395be5eSAriel Elior #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 893adfc5217SJeff Kirsher #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 894adfc5217SJeff Kirsher CHIP_IS_57711E(bp)) 895edb944d2SDmitry Kravkov #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ 896edb944d2SDmitry Kravkov CHIP_IS_57811_MF(bp) || \ 897edb944d2SDmitry Kravkov CHIP_IS_57811_VF(bp)) 898adfc5217SJeff Kirsher #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 8996ab20355SYuval Mintz CHIP_IS_57712_MF(bp) || \ 9006ab20355SYuval Mintz CHIP_IS_57712_VF(bp)) 901adfc5217SJeff Kirsher #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 902adfc5217SJeff Kirsher CHIP_IS_57800_MF(bp) || \ 9036ab20355SYuval Mintz CHIP_IS_57800_VF(bp) || \ 904adfc5217SJeff Kirsher CHIP_IS_57810(bp) || \ 905adfc5217SJeff Kirsher CHIP_IS_57810_MF(bp) || \ 9068395be5eSAriel Elior CHIP_IS_57810_VF(bp) || \ 907edb944d2SDmitry Kravkov CHIP_IS_57811xx(bp) || \ 908adfc5217SJeff Kirsher CHIP_IS_57840(bp) || \ 9098395be5eSAriel Elior CHIP_IS_57840_MF(bp) || \ 9108395be5eSAriel Elior CHIP_IS_57840_VF(bp)) 911adfc5217SJeff Kirsher #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 912adfc5217SJeff Kirsher #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 913adfc5217SJeff Kirsher #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 914adfc5217SJeff Kirsher 915adfc5217SJeff Kirsher #define CHIP_REV_SHIFT 12 916adfc5217SJeff Kirsher #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 917adfc5217SJeff Kirsher #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 918adfc5217SJeff Kirsher #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 919adfc5217SJeff Kirsher #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 920adfc5217SJeff Kirsher /* assume maximum 5 revisions */ 921adfc5217SJeff Kirsher #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 922adfc5217SJeff Kirsher /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 923adfc5217SJeff Kirsher #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 924adfc5217SJeff Kirsher !(CHIP_REV_VAL(bp) & 0x00001000)) 925adfc5217SJeff Kirsher /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 926adfc5217SJeff Kirsher #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 927adfc5217SJeff Kirsher (CHIP_REV_VAL(bp) & 0x00001000)) 928adfc5217SJeff Kirsher 929adfc5217SJeff Kirsher #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 930adfc5217SJeff Kirsher ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 931adfc5217SJeff Kirsher 932adfc5217SJeff Kirsher #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 933adfc5217SJeff Kirsher #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 934adfc5217SJeff Kirsher #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 935adfc5217SJeff Kirsher (CHIP_REV_SHIFT + 1)) \ 936adfc5217SJeff Kirsher << CHIP_REV_SHIFT) 937adfc5217SJeff Kirsher #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 938adfc5217SJeff Kirsher CHIP_REV_SIM(bp) :\ 939adfc5217SJeff Kirsher CHIP_REV_VAL(bp)) 940adfc5217SJeff Kirsher #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 941adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Bx)) 942adfc5217SJeff Kirsher #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 943adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Ax)) 94455c11941SMerav Sicron /* This define is used in two main places: 94516a5fd92SYuval Mintz * 1. In the early stages of nic_load, to know if to configure Parser / Searcher 94655c11941SMerav Sicron * to nic-only mode or to offload mode. Offload mode is configured if either the 94755c11941SMerav Sicron * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 94855c11941SMerav Sicron * registered for this port (which means that the user wants storage services). 94955c11941SMerav Sicron * 2. During cnic-related load, to know if offload mode is already configured in 95016a5fd92SYuval Mintz * the HW or needs to be configured. 95155c11941SMerav Sicron * Since the transition from nic-mode to offload-mode in HW causes traffic 95216a5fd92SYuval Mintz * corruption, nic-mode is configured only in ports on which storage services 95355c11941SMerav Sicron * where never requested. 95455c11941SMerav Sicron */ 95555c11941SMerav Sicron #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 956adfc5217SJeff Kirsher 957adfc5217SJeff Kirsher int flash_size; 958adfc5217SJeff Kirsher #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 959adfc5217SJeff Kirsher #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 960adfc5217SJeff Kirsher #define BNX2X_NVRAM_PAGE_SIZE 256 961adfc5217SJeff Kirsher 962adfc5217SJeff Kirsher u32 shmem_base; 963adfc5217SJeff Kirsher u32 shmem2_base; 964adfc5217SJeff Kirsher u32 mf_cfg_base; 965adfc5217SJeff Kirsher u32 mf2_cfg_base; 966adfc5217SJeff Kirsher 967adfc5217SJeff Kirsher u32 hw_config; 968adfc5217SJeff Kirsher 969adfc5217SJeff Kirsher u32 bc_ver; 970adfc5217SJeff Kirsher 971adfc5217SJeff Kirsher u8 int_block; 972adfc5217SJeff Kirsher #define INT_BLOCK_HC 0 973adfc5217SJeff Kirsher #define INT_BLOCK_IGU 1 974adfc5217SJeff Kirsher #define INT_BLOCK_MODE_NORMAL 0 975adfc5217SJeff Kirsher #define INT_BLOCK_MODE_BW_COMP 2 976adfc5217SJeff Kirsher #define CHIP_INT_MODE_IS_NBC(bp) \ 977adfc5217SJeff Kirsher (!CHIP_IS_E1x(bp) && \ 978adfc5217SJeff Kirsher !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 979adfc5217SJeff Kirsher #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 980adfc5217SJeff Kirsher 981adfc5217SJeff Kirsher u8 chip_port_mode; 982adfc5217SJeff Kirsher #define CHIP_4_PORT_MODE 0x0 983adfc5217SJeff Kirsher #define CHIP_2_PORT_MODE 0x1 984adfc5217SJeff Kirsher #define CHIP_PORT_MODE_NONE 0x2 985adfc5217SJeff Kirsher #define CHIP_MODE(bp) (bp->common.chip_port_mode) 986adfc5217SJeff Kirsher #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 9871d187b34SBarak Witkowski 9881d187b34SBarak Witkowski u32 boot_mode; 989adfc5217SJeff Kirsher }; 990adfc5217SJeff Kirsher 991adfc5217SJeff Kirsher /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 992adfc5217SJeff Kirsher #define BNX2X_IGU_STAS_MSG_VF_CNT 64 993adfc5217SJeff Kirsher #define BNX2X_IGU_STAS_MSG_PF_CNT 4 994adfc5217SJeff Kirsher 99527c1151cSYaniv Rosner #define MAX_IGU_ATTN_ACK_TO 100 996adfc5217SJeff Kirsher /* end of common */ 997adfc5217SJeff Kirsher 998adfc5217SJeff Kirsher /* port */ 999adfc5217SJeff Kirsher 1000adfc5217SJeff Kirsher struct bnx2x_port { 1001adfc5217SJeff Kirsher u32 pmf; 1002adfc5217SJeff Kirsher 1003adfc5217SJeff Kirsher u32 link_config[LINK_CONFIG_SIZE]; 1004adfc5217SJeff Kirsher 1005adfc5217SJeff Kirsher u32 supported[LINK_CONFIG_SIZE]; 1006adfc5217SJeff Kirsher 1007adfc5217SJeff Kirsher u32 advertising[LINK_CONFIG_SIZE]; 1008adfc5217SJeff Kirsher 1009adfc5217SJeff Kirsher u32 phy_addr; 1010adfc5217SJeff Kirsher 1011adfc5217SJeff Kirsher /* used to synchronize phy accesses */ 1012adfc5217SJeff Kirsher struct mutex phy_mutex; 1013adfc5217SJeff Kirsher 1014adfc5217SJeff Kirsher u32 port_stx; 1015adfc5217SJeff Kirsher 1016adfc5217SJeff Kirsher struct nig_stats old_nig_stats; 1017adfc5217SJeff Kirsher }; 1018adfc5217SJeff Kirsher 1019adfc5217SJeff Kirsher /* end of port */ 1020adfc5217SJeff Kirsher 1021adfc5217SJeff Kirsher #define STATS_OFFSET32(stat_name) \ 1022adfc5217SJeff Kirsher (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 1023adfc5217SJeff Kirsher 1024adfc5217SJeff Kirsher /* slow path */ 1025adfc5217SJeff Kirsher #define BNX2X_MAX_NUM_OF_VFS 64 1026b9871bcfSAriel Elior #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */ 10271ab4434cSAriel Elior #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 1028b9871bcfSAriel Elior 1029b9871bcfSAriel Elior /* We need to reserve doorbell addresses for all VF and queue combinations */ 10301ab4434cSAriel Elior #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 1031b9871bcfSAriel Elior 1032b9871bcfSAriel Elior /* The doorbell is configured to have the same number of CIDs for PFs and for 1033b9871bcfSAriel Elior * VFs. For this reason the PF CID zone is as large as the VF zone. 1034b9871bcfSAriel Elior */ 1035b9871bcfSAriel Elior #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS 1036b9871bcfSAriel Elior #define BNX2X_MAX_NUM_VF_QUEUES 64 1037adfc5217SJeff Kirsher #define BNX2X_VF_ID_INVALID 0xFF 1038adfc5217SJeff Kirsher 1039b9871bcfSAriel Elior /* the number of VF CIDS multiplied by the amount of bytes reserved for each 1040b9871bcfSAriel Elior * cid must not exceed the size of the VF doorbell 1041b9871bcfSAriel Elior */ 1042b9871bcfSAriel Elior #define BNX2X_VF_BAR_SIZE 512 1043b9871bcfSAriel Elior #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT)) 1044b9871bcfSAriel Elior #error "VF doorbell bar size is 512" 1045b9871bcfSAriel Elior #endif 1046b9871bcfSAriel Elior 1047adfc5217SJeff Kirsher /* 1048adfc5217SJeff Kirsher * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 1049adfc5217SJeff Kirsher * control by the number of fast-path status blocks supported by the 1050adfc5217SJeff Kirsher * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 1051adfc5217SJeff Kirsher * status block represents an independent interrupts context that can 1052adfc5217SJeff Kirsher * serve a regular L2 networking queue. However special L2 queues such 1053adfc5217SJeff Kirsher * as the FCoE queue do not require a FP-SB and other components like 1054adfc5217SJeff Kirsher * the CNIC may consume FP-SB reducing the number of possible L2 queues 1055adfc5217SJeff Kirsher * 1056adfc5217SJeff Kirsher * If the maximum number of FP-SB available is X then: 1057adfc5217SJeff Kirsher * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 1058adfc5217SJeff Kirsher * regular L2 queues is Y=X-1 105916a5fd92SYuval Mintz * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1060adfc5217SJeff Kirsher * c. If the FCoE L2 queue is supported the actual number of L2 queues 1061adfc5217SJeff Kirsher * is Y+1 1062adfc5217SJeff Kirsher * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1063adfc5217SJeff Kirsher * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1064adfc5217SJeff Kirsher * FP interrupt context for the CNIC). 1065adfc5217SJeff Kirsher * e. The number of HW context (CID count) is always X or X+1 if FCoE 106616a5fd92SYuval Mintz * L2 queue is supported. The cid for the FCoE L2 queue is always X. 1067adfc5217SJeff Kirsher */ 1068adfc5217SJeff Kirsher 1069adfc5217SJeff Kirsher /* fast-path interrupt contexts E1x */ 1070adfc5217SJeff Kirsher #define FP_SB_MAX_E1x 16 1071adfc5217SJeff Kirsher /* fast-path interrupt contexts E2 */ 1072adfc5217SJeff Kirsher #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1073adfc5217SJeff Kirsher 1074adfc5217SJeff Kirsher union cdu_context { 1075adfc5217SJeff Kirsher struct eth_context eth; 1076adfc5217SJeff Kirsher char pad[1024]; 1077adfc5217SJeff Kirsher }; 1078adfc5217SJeff Kirsher 1079adfc5217SJeff Kirsher /* CDU host DB constants */ 1080a052997eSMerav Sicron #define CDU_ILT_PAGE_SZ_HW 2 1081a052997eSMerav Sicron #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1082adfc5217SJeff Kirsher #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1083adfc5217SJeff Kirsher 1084adfc5217SJeff Kirsher #define CNIC_ISCSI_CID_MAX 256 1085adfc5217SJeff Kirsher #define CNIC_FCOE_CID_MAX 2048 1086adfc5217SJeff Kirsher #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1087adfc5217SJeff Kirsher #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1088adfc5217SJeff Kirsher 1089adfc5217SJeff Kirsher #define QM_ILT_PAGE_SZ_HW 0 1090adfc5217SJeff Kirsher #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1091adfc5217SJeff Kirsher #define QM_CID_ROUND 1024 1092adfc5217SJeff Kirsher 1093adfc5217SJeff Kirsher /* TM (timers) host DB constants */ 1094adfc5217SJeff Kirsher #define TM_ILT_PAGE_SZ_HW 0 1095adfc5217SJeff Kirsher #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 10960907f34cSAriel Elior #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \ 10970907f34cSAriel Elior BNX2X_VF_CIDS + \ 10980907f34cSAriel Elior CNIC_ISCSI_CID_MAX) 1099adfc5217SJeff Kirsher #define TM_ILT_SZ (8 * TM_CONN_NUM) 1100adfc5217SJeff Kirsher #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1101adfc5217SJeff Kirsher 1102adfc5217SJeff Kirsher /* SRC (Searcher) host DB constants */ 1103adfc5217SJeff Kirsher #define SRC_ILT_PAGE_SZ_HW 0 1104adfc5217SJeff Kirsher #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1105adfc5217SJeff Kirsher #define SRC_HASH_BITS 10 1106adfc5217SJeff Kirsher #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1107adfc5217SJeff Kirsher #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1108adfc5217SJeff Kirsher #define SRC_T2_SZ SRC_ILT_SZ 1109adfc5217SJeff Kirsher #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1110adfc5217SJeff Kirsher 1111adfc5217SJeff Kirsher #define MAX_DMAE_C 8 1112adfc5217SJeff Kirsher 1113adfc5217SJeff Kirsher /* DMA memory not used in fastpath */ 1114adfc5217SJeff Kirsher struct bnx2x_slowpath { 1115adfc5217SJeff Kirsher union { 1116adfc5217SJeff Kirsher struct mac_configuration_cmd e1x; 1117adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data e2; 1118adfc5217SJeff Kirsher } mac_rdata; 1119adfc5217SJeff Kirsher 1120adfc5217SJeff Kirsher union { 112105cc5a39SYuval Mintz struct eth_classify_rules_ramrod_data e2; 112205cc5a39SYuval Mintz } vlan_rdata; 112305cc5a39SYuval Mintz 112405cc5a39SYuval Mintz union { 1125adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config e1x; 1126adfc5217SJeff Kirsher struct eth_filter_rules_ramrod_data e2; 1127adfc5217SJeff Kirsher } rx_mode_rdata; 1128adfc5217SJeff Kirsher 1129adfc5217SJeff Kirsher union { 1130adfc5217SJeff Kirsher struct mac_configuration_cmd e1; 1131adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data e2; 1132adfc5217SJeff Kirsher } mcast_rdata; 1133adfc5217SJeff Kirsher 1134adfc5217SJeff Kirsher struct eth_rss_update_ramrod_data rss_rdata; 1135adfc5217SJeff Kirsher 1136adfc5217SJeff Kirsher /* Queue State related ramrods are always sent under rtnl_lock */ 1137adfc5217SJeff Kirsher union { 1138adfc5217SJeff Kirsher struct client_init_ramrod_data init_data; 1139adfc5217SJeff Kirsher struct client_update_ramrod_data update_data; 114014a94ebdSMichal Kalderon struct tpa_update_ramrod_data tpa_data; 1141adfc5217SJeff Kirsher } q_rdata; 1142adfc5217SJeff Kirsher 1143adfc5217SJeff Kirsher union { 1144adfc5217SJeff Kirsher struct function_start_data func_start; 1145adfc5217SJeff Kirsher /* pfc configuration for DCBX ramrod */ 1146adfc5217SJeff Kirsher struct flow_control_configuration pfc_config; 1147adfc5217SJeff Kirsher } func_rdata; 1148adfc5217SJeff Kirsher 1149a3348722SBarak Witkowski /* afex ramrod can not be a part of func_rdata union because these 1150a3348722SBarak Witkowski * events might arrive in parallel to other events from func_rdata. 1151a3348722SBarak Witkowski * Therefore, if they would have been defined in the same union, 1152a3348722SBarak Witkowski * data can get corrupted. 1153a3348722SBarak Witkowski */ 11549dfef3adSYuval Mintz union { 11559dfef3adSYuval Mintz struct afex_vif_list_ramrod_data viflist_data; 11569dfef3adSYuval Mintz struct function_update_data func_update; 11579dfef3adSYuval Mintz } func_afex_rdata; 1158a3348722SBarak Witkowski 1159adfc5217SJeff Kirsher /* used by dmae command executer */ 1160adfc5217SJeff Kirsher struct dmae_command dmae[MAX_DMAE_C]; 1161adfc5217SJeff Kirsher 1162adfc5217SJeff Kirsher u32 stats_comp; 1163adfc5217SJeff Kirsher union mac_stats mac_stats; 1164adfc5217SJeff Kirsher struct nig_stats nig_stats; 1165adfc5217SJeff Kirsher struct host_port_stats port_stats; 1166adfc5217SJeff Kirsher struct host_func_stats func_stats; 1167adfc5217SJeff Kirsher 1168adfc5217SJeff Kirsher u32 wb_comp; 1169adfc5217SJeff Kirsher u32 wb_data[4]; 11701d187b34SBarak Witkowski 11711d187b34SBarak Witkowski union drv_info_to_mcp drv_info_to_mcp; 1172adfc5217SJeff Kirsher }; 1173adfc5217SJeff Kirsher 1174adfc5217SJeff Kirsher #define bnx2x_sp(bp, var) (&bp->slowpath->var) 1175adfc5217SJeff Kirsher #define bnx2x_sp_mapping(bp, var) \ 1176adfc5217SJeff Kirsher (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1177adfc5217SJeff Kirsher 1178adfc5217SJeff Kirsher /* attn group wiring */ 1179adfc5217SJeff Kirsher #define MAX_DYNAMIC_ATTN_GRPS 8 1180adfc5217SJeff Kirsher 1181adfc5217SJeff Kirsher struct attn_route { 1182adfc5217SJeff Kirsher u32 sig[5]; 1183adfc5217SJeff Kirsher }; 1184adfc5217SJeff Kirsher 1185adfc5217SJeff Kirsher struct iro { 1186adfc5217SJeff Kirsher u32 base; 1187adfc5217SJeff Kirsher u16 m1; 1188adfc5217SJeff Kirsher u16 m2; 1189adfc5217SJeff Kirsher u16 m3; 1190adfc5217SJeff Kirsher u16 size; 1191adfc5217SJeff Kirsher }; 1192adfc5217SJeff Kirsher 1193adfc5217SJeff Kirsher struct hw_context { 1194adfc5217SJeff Kirsher union cdu_context *vcxt; 1195adfc5217SJeff Kirsher dma_addr_t cxt_mapping; 1196adfc5217SJeff Kirsher size_t size; 1197adfc5217SJeff Kirsher }; 1198adfc5217SJeff Kirsher 1199adfc5217SJeff Kirsher /* forward */ 1200adfc5217SJeff Kirsher struct bnx2x_ilt; 1201adfc5217SJeff Kirsher 1202290ca2bbSAriel Elior struct bnx2x_vfdb; 1203adfc5217SJeff Kirsher 1204adfc5217SJeff Kirsher enum bnx2x_recovery_state { 1205adfc5217SJeff Kirsher BNX2X_RECOVERY_DONE, 1206adfc5217SJeff Kirsher BNX2X_RECOVERY_INIT, 1207adfc5217SJeff Kirsher BNX2X_RECOVERY_WAIT, 120895c6c616SAriel Elior BNX2X_RECOVERY_FAILED, 120995c6c616SAriel Elior BNX2X_RECOVERY_NIC_LOADING 1210adfc5217SJeff Kirsher }; 1211adfc5217SJeff Kirsher 1212adfc5217SJeff Kirsher /* 1213adfc5217SJeff Kirsher * Event queue (EQ or event ring) MC hsi 1214adfc5217SJeff Kirsher * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1215adfc5217SJeff Kirsher */ 1216adfc5217SJeff Kirsher #define NUM_EQ_PAGES 1 1217adfc5217SJeff Kirsher #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1218adfc5217SJeff Kirsher #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1219adfc5217SJeff Kirsher #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1220adfc5217SJeff Kirsher #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1221adfc5217SJeff Kirsher #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1222adfc5217SJeff Kirsher 1223adfc5217SJeff Kirsher /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1224adfc5217SJeff Kirsher #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1225adfc5217SJeff Kirsher (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1226adfc5217SJeff Kirsher 1227adfc5217SJeff Kirsher /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1228adfc5217SJeff Kirsher #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1229adfc5217SJeff Kirsher 1230adfc5217SJeff Kirsher #define BNX2X_EQ_INDEX \ 1231adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 1232adfc5217SJeff Kirsher index_values[HC_SP_INDEX_EQ_CONS]) 1233adfc5217SJeff Kirsher 1234adfc5217SJeff Kirsher /* This is a data that will be used to create a link report message. 1235adfc5217SJeff Kirsher * We will keep the data used for the last link report in order 1236adfc5217SJeff Kirsher * to prevent reporting the same link parameters twice. 1237adfc5217SJeff Kirsher */ 1238adfc5217SJeff Kirsher struct bnx2x_link_report_data { 1239adfc5217SJeff Kirsher u16 line_speed; /* Effective line speed */ 1240adfc5217SJeff Kirsher unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1241adfc5217SJeff Kirsher }; 1242adfc5217SJeff Kirsher 1243adfc5217SJeff Kirsher enum { 1244adfc5217SJeff Kirsher BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1245adfc5217SJeff Kirsher BNX2X_LINK_REPORT_LINK_DOWN, 1246adfc5217SJeff Kirsher BNX2X_LINK_REPORT_RX_FC_ON, 1247adfc5217SJeff Kirsher BNX2X_LINK_REPORT_TX_FC_ON, 1248adfc5217SJeff Kirsher }; 1249adfc5217SJeff Kirsher 1250adfc5217SJeff Kirsher enum { 1251adfc5217SJeff Kirsher BNX2X_PORT_QUERY_IDX, 1252adfc5217SJeff Kirsher BNX2X_PF_QUERY_IDX, 125350f0a562SBarak Witkowski BNX2X_FCOE_QUERY_IDX, 1254adfc5217SJeff Kirsher BNX2X_FIRST_QUEUE_QUERY_IDX, 1255adfc5217SJeff Kirsher }; 1256adfc5217SJeff Kirsher 1257adfc5217SJeff Kirsher struct bnx2x_fw_stats_req { 1258adfc5217SJeff Kirsher struct stats_query_header hdr; 125950f0a562SBarak Witkowski struct stats_query_entry query[FP_SB_MAX_E1x+ 126050f0a562SBarak Witkowski BNX2X_FIRST_QUEUE_QUERY_IDX]; 1261adfc5217SJeff Kirsher }; 1262adfc5217SJeff Kirsher 1263adfc5217SJeff Kirsher struct bnx2x_fw_stats_data { 1264adfc5217SJeff Kirsher struct stats_counter storm_counters; 1265adfc5217SJeff Kirsher struct per_port_stats port; 1266adfc5217SJeff Kirsher struct per_pf_stats pf; 126750f0a562SBarak Witkowski struct fcoe_statistics_params fcoe; 1268adfc5217SJeff Kirsher struct per_queue_stats queue_stats[1]; 1269adfc5217SJeff Kirsher }; 1270adfc5217SJeff Kirsher 1271adfc5217SJeff Kirsher /* Public slow path states */ 1272230bb0f3SYuval Mintz enum sp_rtnl_flag { 1273adfc5217SJeff Kirsher BNX2X_SP_RTNL_SETUP_TC, 1274adfc5217SJeff Kirsher BNX2X_SP_RTNL_TX_TIMEOUT, 12758304859aSAriel Elior BNX2X_SP_RTNL_FAN_FAILURE, 12768395be5eSAriel Elior BNX2X_SP_RTNL_AFEX_F_UPDATE, 12778395be5eSAriel Elior BNX2X_SP_RTNL_ENABLE_SRIOV, 1278381ac16bSAriel Elior BNX2X_SP_RTNL_VFPF_MCAST, 127978c3bcc5SAriel Elior BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 12808b09be5fSYuval Mintz BNX2X_SP_RTNL_RX_MODE, 12813ec9f9caSAriel Elior BNX2X_SP_RTNL_HYPERVISOR_VLAN, 128207b4eb3bSDmitry Kravkov BNX2X_SP_RTNL_TX_STOP, 128342f8277fSYuval Mintz BNX2X_SP_RTNL_GET_DRV_VERSION, 1284883ce97dSYuval Mintz BNX2X_SP_RTNL_CHANGE_UDP_PORT, 1285adfc5217SJeff Kirsher }; 1286adfc5217SJeff Kirsher 1287370d4a26SYuval Mintz enum bnx2x_iov_flag { 1288370d4a26SYuval Mintz BNX2X_IOV_HANDLE_VF_MSG, 1289370d4a26SYuval Mintz BNX2X_IOV_HANDLE_FLR, 1290370d4a26SYuval Mintz }; 1291370d4a26SYuval Mintz 1292452427b0SYuval Mintz struct bnx2x_prev_path_list { 12937fa6f340SYuval Mintz struct list_head list; 1294452427b0SYuval Mintz u8 bus; 1295452427b0SYuval Mintz u8 slot; 1296452427b0SYuval Mintz u8 path; 12977fa6f340SYuval Mintz u8 aer; 1298c63da990SBarak Witkowski u8 undi; 1299452427b0SYuval Mintz }; 1300452427b0SYuval Mintz 130115192a8cSBarak Witkowski struct bnx2x_sp_objs { 130215192a8cSBarak Witkowski /* MACs object */ 130315192a8cSBarak Witkowski struct bnx2x_vlan_mac_obj mac_obj; 130415192a8cSBarak Witkowski 130515192a8cSBarak Witkowski /* Queue State object */ 130615192a8cSBarak Witkowski struct bnx2x_queue_sp_obj q_obj; 130705cc5a39SYuval Mintz 130805cc5a39SYuval Mintz /* VLANs object */ 130905cc5a39SYuval Mintz struct bnx2x_vlan_mac_obj vlan_obj; 131015192a8cSBarak Witkowski }; 131115192a8cSBarak Witkowski 131215192a8cSBarak Witkowski struct bnx2x_fp_stats { 131315192a8cSBarak Witkowski struct tstorm_per_queue_stats old_tclient; 131415192a8cSBarak Witkowski struct ustorm_per_queue_stats old_uclient; 131515192a8cSBarak Witkowski struct xstorm_per_queue_stats old_xclient; 131615192a8cSBarak Witkowski struct bnx2x_eth_q_stats eth_q_stats; 131715192a8cSBarak Witkowski struct bnx2x_eth_q_stats_old eth_q_stats_old; 131815192a8cSBarak Witkowski }; 131915192a8cSBarak Witkowski 13207609647eSYuval Mintz enum { 13217609647eSYuval Mintz SUB_MF_MODE_UNKNOWN = 0, 13227609647eSYuval Mintz SUB_MF_MODE_UFP, 132383bad206SYuval Mintz SUB_MF_MODE_NPAR1_DOT_5, 1324230d00ebSYuval Mintz SUB_MF_MODE_BD, 13257609647eSYuval Mintz }; 13267609647eSYuval Mintz 132705cc5a39SYuval Mintz struct bnx2x_vlan_entry { 132805cc5a39SYuval Mintz struct list_head link; 132905cc5a39SYuval Mintz u16 vid; 133005cc5a39SYuval Mintz bool hw; 133105cc5a39SYuval Mintz }; 133205cc5a39SYuval Mintz 1333883ce97dSYuval Mintz enum bnx2x_udp_port_type { 1334883ce97dSYuval Mintz BNX2X_UDP_PORT_VXLAN, 1335883ce97dSYuval Mintz BNX2X_UDP_PORT_GENEVE, 1336883ce97dSYuval Mintz BNX2X_UDP_PORT_MAX, 1337883ce97dSYuval Mintz }; 1338883ce97dSYuval Mintz 1339883ce97dSYuval Mintz struct bnx2x_udp_tunnel { 1340883ce97dSYuval Mintz u16 dst_port; 1341883ce97dSYuval Mintz u8 count; 1342883ce97dSYuval Mintz }; 1343883ce97dSYuval Mintz 1344adfc5217SJeff Kirsher struct bnx2x { 1345adfc5217SJeff Kirsher /* Fields used in the tx and intr/napi performance paths 1346adfc5217SJeff Kirsher * are grouped together in the beginning of the structure 1347adfc5217SJeff Kirsher */ 1348adfc5217SJeff Kirsher struct bnx2x_fastpath *fp; 134915192a8cSBarak Witkowski struct bnx2x_sp_objs *sp_objs; 135015192a8cSBarak Witkowski struct bnx2x_fp_stats *fp_stats; 135165565884SMerav Sicron struct bnx2x_fp_txdata *bnx2x_txq; 1352adfc5217SJeff Kirsher void __iomem *regview; 1353adfc5217SJeff Kirsher void __iomem *doorbells; 1354adfc5217SJeff Kirsher u16 db_size; 1355adfc5217SJeff Kirsher 1356adfc5217SJeff Kirsher u8 pf_num; /* absolute PF number */ 1357adfc5217SJeff Kirsher u8 pfid; /* per-path PF number */ 1358adfc5217SJeff Kirsher int base_fw_ndsb; /**/ 1359adfc5217SJeff Kirsher #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1360adfc5217SJeff Kirsher #define BP_PORT(bp) (bp->pfid & 1) 1361adfc5217SJeff Kirsher #define BP_FUNC(bp) (bp->pfid) 1362adfc5217SJeff Kirsher #define BP_ABS_FUNC(bp) (bp->pf_num) 13638decf868SDavid S. Miller #define BP_VN(bp) ((bp)->pfid >> 1) 13648decf868SDavid S. Miller #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 13658decf868SDavid S. Miller #define BP_L_ID(bp) (BP_VN(bp) << 2) 13668decf868SDavid S. Miller #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 13678decf868SDavid S. Miller (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 13688decf868SDavid S. Miller #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1369adfc5217SJeff Kirsher 13706411280aSAriel Elior #ifdef CONFIG_BNX2X_SRIOV 13711d6f3cd8SDmitry Kravkov /* protects vf2pf mailbox from simultaneous access */ 13721d6f3cd8SDmitry Kravkov struct mutex vf2pf_mutex; 13731ab4434cSAriel Elior /* vf pf channel mailbox contains request and response buffers */ 13741ab4434cSAriel Elior struct bnx2x_vf_mbx_msg *vf2pf_mbox; 13751ab4434cSAriel Elior dma_addr_t vf2pf_mbox_mapping; 13761ab4434cSAriel Elior 1377be1f1ffaSAriel Elior /* we set aside a copy of the acquire response */ 1378be1f1ffaSAriel Elior struct pfvf_acquire_resp_tlv acquire_resp; 1379be1f1ffaSAriel Elior 1380abc5a021SAriel Elior /* bulletin board for messages from pf to vf */ 1381abc5a021SAriel Elior union pf_vf_bulletin *pf2vf_bulletin; 1382abc5a021SAriel Elior dma_addr_t pf2vf_bulletin_mapping; 1383abc5a021SAriel Elior 13846495d15aSDmitry Kravkov union pf_vf_bulletin shadow_bulletin; 1385abc5a021SAriel Elior struct pf_vf_bulletin_content old_bulletin; 13863c76feffSAriel Elior 13873c76feffSAriel Elior u16 requested_nr_virtfn; 13886411280aSAriel Elior #endif /* CONFIG_BNX2X_SRIOV */ 1389abc5a021SAriel Elior 1390adfc5217SJeff Kirsher struct net_device *dev; 1391adfc5217SJeff Kirsher struct pci_dev *pdev; 1392adfc5217SJeff Kirsher 1393adfc5217SJeff Kirsher const struct iro *iro_arr; 1394adfc5217SJeff Kirsher #define IRO (bp->iro_arr) 1395adfc5217SJeff Kirsher 1396adfc5217SJeff Kirsher enum bnx2x_recovery_state recovery_state; 1397adfc5217SJeff Kirsher int is_leader; 1398adfc5217SJeff Kirsher struct msix_entry *msix_table; 1399adfc5217SJeff Kirsher 1400adfc5217SJeff Kirsher int tx_ring_size; 1401adfc5217SJeff Kirsher 1402adfc5217SJeff Kirsher /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1403e1c6dccaSJarod Wilson #define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 1404e1c6dccaSJarod Wilson #define ETH_MIN_PACKET_SIZE (ETH_ZLEN - ETH_HLEN) 1405e1c6dccaSJarod Wilson #define ETH_MAX_PACKET_SIZE ETH_DATA_LEN 1406adfc5217SJeff Kirsher #define ETH_MAX_JUMBO_PACKET_SIZE 9600 1407621b4d66SDmitry Kravkov /* TCP with Timestamp Option (32) + IPv6 (40) */ 1408621b4d66SDmitry Kravkov #define ETH_MAX_TPA_HEADER_SIZE 72 1409adfc5217SJeff Kirsher 14109927b514SDmitry Kravkov /* Max supported alignment is 256 (8 shift) 14119927b514SDmitry Kravkov * minimal alignment shift 6 is optimal for 57xxx HW performance 14129927b514SDmitry Kravkov */ 14139927b514SDmitry Kravkov #define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT)) 1414e52fcb24SEric Dumazet 1415e52fcb24SEric Dumazet /* FW uses 2 Cache lines Alignment for start packet and size 1416e52fcb24SEric Dumazet * 1417e52fcb24SEric Dumazet * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1418e52fcb24SEric Dumazet * at the end of skb->data, to avoid wasting a full cache line. 1419e52fcb24SEric Dumazet * This reduces memory use (skb->truesize). 1420e52fcb24SEric Dumazet */ 1421e52fcb24SEric Dumazet #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1422e52fcb24SEric Dumazet 1423e52fcb24SEric Dumazet #define BNX2X_FW_RX_ALIGN_END \ 1424f57b07c0SJoren Van Onder max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1425e52fcb24SEric Dumazet SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1426e52fcb24SEric Dumazet 1427adfc5217SJeff Kirsher #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1428adfc5217SJeff Kirsher 1429adfc5217SJeff Kirsher struct host_sp_status_block *def_status_blk; 1430adfc5217SJeff Kirsher #define DEF_SB_IGU_ID 16 1431adfc5217SJeff Kirsher #define DEF_SB_ID HC_SP_SB_ID 1432adfc5217SJeff Kirsher __le16 def_idx; 1433adfc5217SJeff Kirsher __le16 def_att_idx; 1434adfc5217SJeff Kirsher u32 attn_state; 1435adfc5217SJeff Kirsher struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1436adfc5217SJeff Kirsher 1437adfc5217SJeff Kirsher /* slow path ring */ 1438adfc5217SJeff Kirsher struct eth_spe *spq; 1439adfc5217SJeff Kirsher dma_addr_t spq_mapping; 1440adfc5217SJeff Kirsher u16 spq_prod_idx; 1441adfc5217SJeff Kirsher struct eth_spe *spq_prod_bd; 1442adfc5217SJeff Kirsher struct eth_spe *spq_last_bd; 1443adfc5217SJeff Kirsher __le16 *dsb_sp_prod; 1444adfc5217SJeff Kirsher atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1445adfc5217SJeff Kirsher /* used to synchronize spq accesses */ 1446adfc5217SJeff Kirsher spinlock_t spq_lock; 1447adfc5217SJeff Kirsher 1448adfc5217SJeff Kirsher /* event queue */ 1449adfc5217SJeff Kirsher union event_ring_elem *eq_ring; 1450adfc5217SJeff Kirsher dma_addr_t eq_mapping; 1451adfc5217SJeff Kirsher u16 eq_prod; 1452adfc5217SJeff Kirsher u16 eq_cons; 1453adfc5217SJeff Kirsher __le16 *eq_cons_sb; 1454adfc5217SJeff Kirsher atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1455adfc5217SJeff Kirsher 1456adfc5217SJeff Kirsher /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1457adfc5217SJeff Kirsher u16 stats_pending; 1458adfc5217SJeff Kirsher /* Counter for completed statistics ramrods */ 1459adfc5217SJeff Kirsher u16 stats_comp; 1460adfc5217SJeff Kirsher 1461adfc5217SJeff Kirsher /* End of fields used in the performance code paths */ 1462adfc5217SJeff Kirsher 1463adfc5217SJeff Kirsher int panic; 1464adfc5217SJeff Kirsher int msg_enable; 1465adfc5217SJeff Kirsher 1466adfc5217SJeff Kirsher u32 flags; 1467adfc5217SJeff Kirsher #define PCIX_FLAG (1 << 0) 1468adfc5217SJeff Kirsher #define PCI_32BIT_FLAG (1 << 1) 1469adfc5217SJeff Kirsher #define ONE_PORT_FLAG (1 << 2) 1470adfc5217SJeff Kirsher #define NO_WOL_FLAG (1 << 3) 1471adfc5217SJeff Kirsher #define USING_MSIX_FLAG (1 << 5) 1472adfc5217SJeff Kirsher #define USING_MSI_FLAG (1 << 6) 1473adfc5217SJeff Kirsher #define DISABLE_MSI_FLAG (1 << 7) 1474adfc5217SJeff Kirsher #define NO_MCP_FLAG (1 << 9) 1475adfc5217SJeff Kirsher #define MF_FUNC_DIS (1 << 11) 1476adfc5217SJeff Kirsher #define OWN_CNIC_IRQ (1 << 12) 1477adfc5217SJeff Kirsher #define NO_ISCSI_OOO_FLAG (1 << 13) 1478adfc5217SJeff Kirsher #define NO_ISCSI_FLAG (1 << 14) 1479adfc5217SJeff Kirsher #define NO_FCOE_FLAG (1 << 15) 14800e898dd7SBarak Witkowski #define BC_SUPPORTS_PFC_STATS (1 << 17) 1481c14db202SYuval Mintz #define TX_SWITCHING (1 << 18) 14822e499d3cSBarak Witkowski #define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 148330a5de77SDmitry Kravkov #define USING_SINGLE_MSIX_FLAG (1 << 20) 14849876879fSBarak Witkowski #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 14851ab4434cSAriel Elior #define IS_VF_FLAG (1 << 22) 14860c23ad37SYuval Mintz #define BC_SUPPORTS_RMMOD_CMD (1 << 23) 14870c23ad37SYuval Mintz #define HAS_PHYS_PORT_ID (1 << 24) 14880c23ad37SYuval Mintz #define AER_ENABLED (1 << 25) 14890c23ad37SYuval Mintz #define PTP_SUPPORTED (1 << 26) 14900c23ad37SYuval Mintz #define TX_TIMESTAMPING_EN (1 << 27) 14911ab4434cSAriel Elior 14921ab4434cSAriel Elior #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 14936411280aSAriel Elior 14946411280aSAriel Elior #ifdef CONFIG_BNX2X_SRIOV 14951ab4434cSAriel Elior #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 14961ab4434cSAriel Elior #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 14976411280aSAriel Elior #else 14986411280aSAriel Elior #define IS_VF(bp) false 14996411280aSAriel Elior #define IS_PF(bp) true 15006411280aSAriel Elior #endif 1501adfc5217SJeff Kirsher 1502adfc5217SJeff Kirsher #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1503adfc5217SJeff Kirsher #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1504adfc5217SJeff Kirsher #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1505adfc5217SJeff Kirsher 150655c11941SMerav Sicron u8 cnic_support; 150755c11941SMerav Sicron bool cnic_enabled; 150855c11941SMerav Sicron bool cnic_loaded; 15094bd9b0ffSMichael Chan struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 151055c11941SMerav Sicron 151155c11941SMerav Sicron /* Flag that indicates that we can start looking for FCoE L2 queue 151255c11941SMerav Sicron * completions in the default status block. 151355c11941SMerav Sicron */ 151455c11941SMerav Sicron bool fcoe_init; 151555c11941SMerav Sicron 1516adfc5217SJeff Kirsher int mrrs; 1517adfc5217SJeff Kirsher 1518adfc5217SJeff Kirsher struct delayed_work sp_task; 1519370d4a26SYuval Mintz struct delayed_work iov_task; 1520370d4a26SYuval Mintz 1521fd1fc79dSAriel Elior atomic_t interrupt_occurred; 1522adfc5217SJeff Kirsher struct delayed_work sp_rtnl_task; 1523adfc5217SJeff Kirsher 1524adfc5217SJeff Kirsher struct delayed_work period_task; 1525adfc5217SJeff Kirsher struct timer_list timer; 1526adfc5217SJeff Kirsher int current_interval; 1527adfc5217SJeff Kirsher 1528adfc5217SJeff Kirsher u16 fw_seq; 1529adfc5217SJeff Kirsher u16 fw_drv_pulse_wr_seq; 1530adfc5217SJeff Kirsher u32 func_stx; 1531adfc5217SJeff Kirsher 1532adfc5217SJeff Kirsher struct link_params link_params; 1533adfc5217SJeff Kirsher struct link_vars link_vars; 1534adfc5217SJeff Kirsher u32 link_cnt; 1535adfc5217SJeff Kirsher struct bnx2x_link_report_data last_reported_link; 1536484c016dSSudarsana Reddy Kalluru bool force_link_down; 1537adfc5217SJeff Kirsher 1538adfc5217SJeff Kirsher struct mdio_if_info mdio; 1539adfc5217SJeff Kirsher 1540adfc5217SJeff Kirsher struct bnx2x_common common; 1541adfc5217SJeff Kirsher struct bnx2x_port port; 1542adfc5217SJeff Kirsher 1543b475d78fSYuval Mintz struct cmng_init cmng; 1544b475d78fSYuval Mintz 1545adfc5217SJeff Kirsher u32 mf_config[E1HVN_MAX]; 1546a3348722SBarak Witkowski u32 mf_ext_config; 1547adfc5217SJeff Kirsher u32 path_has_ovlan; /* E3 */ 1548adfc5217SJeff Kirsher u16 mf_ov; 1549adfc5217SJeff Kirsher u8 mf_mode; 1550adfc5217SJeff Kirsher #define IS_MF(bp) (bp->mf_mode != 0) 1551adfc5217SJeff Kirsher #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1552adfc5217SJeff Kirsher #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1553a3348722SBarak Witkowski #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 15547609647eSYuval Mintz u8 mf_sub_mode; 15557609647eSYuval Mintz #define IS_MF_UFP(bp) (IS_MF_SD(bp) && \ 15567609647eSYuval Mintz bp->mf_sub_mode == SUB_MF_MODE_UFP) 1557230d00ebSYuval Mintz #define IS_MF_BD(bp) (IS_MF_SD(bp) && \ 1558230d00ebSYuval Mintz bp->mf_sub_mode == SUB_MF_MODE_BD) 1559adfc5217SJeff Kirsher 1560adfc5217SJeff Kirsher u8 wol; 1561adfc5217SJeff Kirsher 1562adfc5217SJeff Kirsher int rx_ring_size; 1563adfc5217SJeff Kirsher 1564adfc5217SJeff Kirsher u16 tx_quick_cons_trip_int; 1565adfc5217SJeff Kirsher u16 tx_quick_cons_trip; 1566adfc5217SJeff Kirsher u16 tx_ticks_int; 1567adfc5217SJeff Kirsher u16 tx_ticks; 1568adfc5217SJeff Kirsher 1569adfc5217SJeff Kirsher u16 rx_quick_cons_trip_int; 1570adfc5217SJeff Kirsher u16 rx_quick_cons_trip; 1571adfc5217SJeff Kirsher u16 rx_ticks_int; 1572adfc5217SJeff Kirsher u16 rx_ticks; 1573adfc5217SJeff Kirsher /* Maximal coalescing timeout in us */ 15746802516eSDmitry Kravkov #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR) 1575adfc5217SJeff Kirsher 1576adfc5217SJeff Kirsher u32 lin_cnt; 1577adfc5217SJeff Kirsher 1578adfc5217SJeff Kirsher u16 state; 1579adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSED 0 1580adfc5217SJeff Kirsher #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1581adfc5217SJeff Kirsher #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1582adfc5217SJeff Kirsher #define BNX2X_STATE_OPEN 0x3000 1583adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1584adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1585adfc5217SJeff Kirsher 1586adfc5217SJeff Kirsher #define BNX2X_STATE_DIAG 0xe000 1587adfc5217SJeff Kirsher #define BNX2X_STATE_ERROR 0xf000 1588adfc5217SJeff Kirsher 1589adfc5217SJeff Kirsher #define BNX2X_MAX_PRIORITY 8 1590adfc5217SJeff Kirsher int num_queues; 159155c11941SMerav Sicron uint num_ethernet_queues; 159255c11941SMerav Sicron uint num_cnic_queues; 1593adfc5217SJeff Kirsher int disable_tpa; 1594adfc5217SJeff Kirsher 1595adfc5217SJeff Kirsher u32 rx_mode; 1596adfc5217SJeff Kirsher #define BNX2X_RX_MODE_NONE 0 1597adfc5217SJeff Kirsher #define BNX2X_RX_MODE_NORMAL 1 1598adfc5217SJeff Kirsher #define BNX2X_RX_MODE_ALLMULTI 2 1599adfc5217SJeff Kirsher #define BNX2X_RX_MODE_PROMISC 3 1600adfc5217SJeff Kirsher #define BNX2X_MAX_MULTICAST 64 1601adfc5217SJeff Kirsher 1602adfc5217SJeff Kirsher u8 igu_dsb_id; 1603adfc5217SJeff Kirsher u8 igu_base_sb; 1604adfc5217SJeff Kirsher u8 igu_sb_cnt; 160555c11941SMerav Sicron u8 min_msix_vec_cnt; 160665565884SMerav Sicron 16071ab4434cSAriel Elior u32 igu_base_addr; 1608adfc5217SJeff Kirsher dma_addr_t def_status_blk_mapping; 1609adfc5217SJeff Kirsher 1610adfc5217SJeff Kirsher struct bnx2x_slowpath *slowpath; 1611adfc5217SJeff Kirsher dma_addr_t slowpath_mapping; 1612adfc5217SJeff Kirsher 161342f8277fSYuval Mintz /* Mechanism protecting the drv_info_to_mcp */ 161442f8277fSYuval Mintz struct mutex drv_info_mutex; 161542f8277fSYuval Mintz bool drv_info_mng_owner; 161642f8277fSYuval Mintz 1617adfc5217SJeff Kirsher /* Total number of FW statistics requests */ 1618adfc5217SJeff Kirsher u8 fw_stats_num; 1619adfc5217SJeff Kirsher 1620adfc5217SJeff Kirsher /* 1621adfc5217SJeff Kirsher * This is a memory buffer that will contain both statistics 1622adfc5217SJeff Kirsher * ramrod request and data. 1623adfc5217SJeff Kirsher */ 1624adfc5217SJeff Kirsher void *fw_stats; 1625adfc5217SJeff Kirsher dma_addr_t fw_stats_mapping; 1626adfc5217SJeff Kirsher 1627adfc5217SJeff Kirsher /* 1628adfc5217SJeff Kirsher * FW statistics request shortcut (points at the 1629adfc5217SJeff Kirsher * beginning of fw_stats buffer). 1630adfc5217SJeff Kirsher */ 1631adfc5217SJeff Kirsher struct bnx2x_fw_stats_req *fw_stats_req; 1632adfc5217SJeff Kirsher dma_addr_t fw_stats_req_mapping; 1633adfc5217SJeff Kirsher int fw_stats_req_sz; 1634adfc5217SJeff Kirsher 1635adfc5217SJeff Kirsher /* 16364907cb7bSAnatol Pomozov * FW statistics data shortcut (points at the beginning of 1637adfc5217SJeff Kirsher * fw_stats buffer + fw_stats_req_sz). 1638adfc5217SJeff Kirsher */ 1639adfc5217SJeff Kirsher struct bnx2x_fw_stats_data *fw_stats_data; 1640adfc5217SJeff Kirsher dma_addr_t fw_stats_data_mapping; 1641adfc5217SJeff Kirsher int fw_stats_data_sz; 1642adfc5217SJeff Kirsher 1643b9871bcfSAriel Elior /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB 1644a052997eSMerav Sicron * context size we need 8 ILT entries. 1645a052997eSMerav Sicron */ 1646b9871bcfSAriel Elior #define ILT_MAX_L2_LINES 32 1647a052997eSMerav Sicron struct hw_context context[ILT_MAX_L2_LINES]; 1648adfc5217SJeff Kirsher 1649adfc5217SJeff Kirsher struct bnx2x_ilt *ilt; 1650adfc5217SJeff Kirsher #define BP_ILT(bp) ((bp)->ilt) 1651adfc5217SJeff Kirsher #define ILT_MAX_LINES 256 1652adfc5217SJeff Kirsher /* 1653adfc5217SJeff Kirsher * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1654adfc5217SJeff Kirsher * to CNIC. 1655adfc5217SJeff Kirsher */ 165655c11941SMerav Sicron #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1657adfc5217SJeff Kirsher 1658adfc5217SJeff Kirsher /* 1659adfc5217SJeff Kirsher * Maximum CID count that might be required by the bnx2x: 166037ae41a9SMerav Sicron * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1661adfc5217SJeff Kirsher */ 1662f78afb35SMichael Chan 166337ae41a9SMerav Sicron #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1664f78afb35SMichael Chan + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 166537ae41a9SMerav Sicron #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1666f78afb35SMichael Chan + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1667adfc5217SJeff Kirsher #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1668adfc5217SJeff Kirsher ILT_PAGE_CIDS)) 1669adfc5217SJeff Kirsher 1670adfc5217SJeff Kirsher int qm_cid_count; 1671adfc5217SJeff Kirsher 16727964211dSYuval Mintz bool dropless_fc; 1673adfc5217SJeff Kirsher 1674adfc5217SJeff Kirsher void *t2; 1675adfc5217SJeff Kirsher dma_addr_t t2_mapping; 1676adfc5217SJeff Kirsher struct cnic_ops __rcu *cnic_ops; 1677adfc5217SJeff Kirsher void *cnic_data; 1678adfc5217SJeff Kirsher u32 cnic_tag; 1679adfc5217SJeff Kirsher struct cnic_eth_dev cnic_eth_dev; 1680adfc5217SJeff Kirsher union host_hc_status_block cnic_sb; 1681adfc5217SJeff Kirsher dma_addr_t cnic_sb_mapping; 1682adfc5217SJeff Kirsher struct eth_spe *cnic_kwq; 1683adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_prod; 1684adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_cons; 1685adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_last; 1686adfc5217SJeff Kirsher u16 cnic_kwq_pending; 1687adfc5217SJeff Kirsher u16 cnic_spq_pending; 1688adfc5217SJeff Kirsher u8 fip_mac[ETH_ALEN]; 1689adfc5217SJeff Kirsher struct mutex cnic_mutex; 1690adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1691adfc5217SJeff Kirsher 169216a5fd92SYuval Mintz /* Start index of the "special" (CNIC related) L2 clients */ 1693adfc5217SJeff Kirsher u8 cnic_base_cl_id; 1694adfc5217SJeff Kirsher 1695adfc5217SJeff Kirsher int dmae_ready; 1696adfc5217SJeff Kirsher /* used to synchronize dmae accesses */ 1697adfc5217SJeff Kirsher spinlock_t dmae_lock; 1698adfc5217SJeff Kirsher 1699adfc5217SJeff Kirsher /* used to protect the FW mail box */ 1700adfc5217SJeff Kirsher struct mutex fw_mb_mutex; 1701adfc5217SJeff Kirsher 1702adfc5217SJeff Kirsher /* used to synchronize stats collecting */ 1703adfc5217SJeff Kirsher int stats_state; 1704adfc5217SJeff Kirsher 1705adfc5217SJeff Kirsher /* used for synchronization of concurrent threads statistics handling */ 1706c6e36d8cSYuval Mintz struct semaphore stats_lock; 1707adfc5217SJeff Kirsher 1708adfc5217SJeff Kirsher /* used by dmae command loader */ 1709adfc5217SJeff Kirsher struct dmae_command stats_dmae; 1710adfc5217SJeff Kirsher int executer_idx; 1711adfc5217SJeff Kirsher 1712adfc5217SJeff Kirsher u16 stats_counter; 1713adfc5217SJeff Kirsher struct bnx2x_eth_stats eth_stats; 1714cb4dca27SYuval Mintz struct host_func_stats func_stats; 17151355b704SMintz Yuval struct bnx2x_eth_stats_old eth_stats_old; 17161355b704SMintz Yuval struct bnx2x_net_stats_old net_stats_old; 17171355b704SMintz Yuval struct bnx2x_fw_port_stats_old fw_stats_old; 17181355b704SMintz Yuval bool stats_init; 1719adfc5217SJeff Kirsher 1720adfc5217SJeff Kirsher struct z_stream_s *strm; 1721adfc5217SJeff Kirsher void *gunzip_buf; 1722adfc5217SJeff Kirsher dma_addr_t gunzip_mapping; 1723adfc5217SJeff Kirsher int gunzip_outlen; 1724adfc5217SJeff Kirsher #define FW_BUF_SIZE 0x8000 1725adfc5217SJeff Kirsher #define GUNZIP_BUF(bp) (bp->gunzip_buf) 1726adfc5217SJeff Kirsher #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1727adfc5217SJeff Kirsher #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1728adfc5217SJeff Kirsher 1729adfc5217SJeff Kirsher struct raw_op *init_ops; 1730adfc5217SJeff Kirsher /* Init blocks offsets inside init_ops */ 1731adfc5217SJeff Kirsher u16 *init_ops_offsets; 1732adfc5217SJeff Kirsher /* Data blob - has 32 bit granularity */ 1733adfc5217SJeff Kirsher u32 *init_data; 1734adfc5217SJeff Kirsher u32 init_mode_flags; 1735adfc5217SJeff Kirsher #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1736adfc5217SJeff Kirsher /* Zipped PRAM blobs - raw data */ 1737adfc5217SJeff Kirsher const u8 *tsem_int_table_data; 1738adfc5217SJeff Kirsher const u8 *tsem_pram_data; 1739adfc5217SJeff Kirsher const u8 *usem_int_table_data; 1740adfc5217SJeff Kirsher const u8 *usem_pram_data; 1741adfc5217SJeff Kirsher const u8 *xsem_int_table_data; 1742adfc5217SJeff Kirsher const u8 *xsem_pram_data; 1743adfc5217SJeff Kirsher const u8 *csem_int_table_data; 1744adfc5217SJeff Kirsher const u8 *csem_pram_data; 1745adfc5217SJeff Kirsher #define INIT_OPS(bp) (bp->init_ops) 1746adfc5217SJeff Kirsher #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1747adfc5217SJeff Kirsher #define INIT_DATA(bp) (bp->init_data) 1748adfc5217SJeff Kirsher #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1749adfc5217SJeff Kirsher #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1750adfc5217SJeff Kirsher #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1751adfc5217SJeff Kirsher #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1752adfc5217SJeff Kirsher #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1753adfc5217SJeff Kirsher #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1754adfc5217SJeff Kirsher #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1755adfc5217SJeff Kirsher #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1756adfc5217SJeff Kirsher 1757adfc5217SJeff Kirsher #define PHY_FW_VER_LEN 20 1758adfc5217SJeff Kirsher char fw_ver[32]; 1759adfc5217SJeff Kirsher const struct firmware *firmware; 1760adfc5217SJeff Kirsher 1761290ca2bbSAriel Elior struct bnx2x_vfdb *vfdb; 1762290ca2bbSAriel Elior #define IS_SRIOV(bp) ((bp)->vfdb) 1763290ca2bbSAriel Elior 1764adfc5217SJeff Kirsher /* DCB support on/off */ 1765adfc5217SJeff Kirsher u16 dcb_state; 1766adfc5217SJeff Kirsher #define BNX2X_DCB_STATE_OFF 0 1767adfc5217SJeff Kirsher #define BNX2X_DCB_STATE_ON 1 1768adfc5217SJeff Kirsher 1769adfc5217SJeff Kirsher /* DCBX engine mode */ 1770adfc5217SJeff Kirsher int dcbx_enabled; 1771adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_OFF 0 1772adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1773adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1774adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_INVALID (-1) 1775adfc5217SJeff Kirsher 1776adfc5217SJeff Kirsher bool dcbx_mode_uset; 1777adfc5217SJeff Kirsher 1778adfc5217SJeff Kirsher struct bnx2x_config_dcbx_params dcbx_config_params; 1779adfc5217SJeff Kirsher struct bnx2x_dcbx_port_params dcbx_port_params; 1780adfc5217SJeff Kirsher int dcb_version; 1781adfc5217SJeff Kirsher 1782adfc5217SJeff Kirsher /* CAM credit pools */ 1783b56e9670SAriel Elior struct bnx2x_credit_pool_obj vlans_pool; 1784b56e9670SAriel Elior 1785adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj macs_pool; 1786adfc5217SJeff Kirsher 1787adfc5217SJeff Kirsher /* RX_MODE object */ 1788adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj rx_mode_obj; 1789adfc5217SJeff Kirsher 1790adfc5217SJeff Kirsher /* MCAST object */ 1791adfc5217SJeff Kirsher struct bnx2x_mcast_obj mcast_obj; 1792adfc5217SJeff Kirsher 1793adfc5217SJeff Kirsher /* RSS configuration object */ 1794adfc5217SJeff Kirsher struct bnx2x_rss_config_obj rss_conf_obj; 1795adfc5217SJeff Kirsher 1796adfc5217SJeff Kirsher /* Function State controlling object */ 1797adfc5217SJeff Kirsher struct bnx2x_func_sp_obj func_obj; 1798adfc5217SJeff Kirsher 1799adfc5217SJeff Kirsher unsigned long sp_state; 1800adfc5217SJeff Kirsher 1801adfc5217SJeff Kirsher /* operation indication for the sp_rtnl task */ 1802adfc5217SJeff Kirsher unsigned long sp_rtnl_state; 1803adfc5217SJeff Kirsher 1804370d4a26SYuval Mintz /* Indication of the IOV tasks */ 1805370d4a26SYuval Mintz unsigned long iov_task_state; 1806370d4a26SYuval Mintz 180716a5fd92SYuval Mintz /* DCBX Negotiation results */ 1808adfc5217SJeff Kirsher struct dcbx_features dcbx_local_feat; 1809adfc5217SJeff Kirsher u32 dcbx_error; 1810adfc5217SJeff Kirsher 1811adfc5217SJeff Kirsher #ifdef BCM_DCBNL 1812adfc5217SJeff Kirsher struct dcbx_features dcbx_remote_feat; 1813adfc5217SJeff Kirsher u32 dcbx_remote_flags; 1814adfc5217SJeff Kirsher #endif 1815a3348722SBarak Witkowski /* AFEX: store default vlan used */ 1816a3348722SBarak Witkowski int afex_def_vlan_tag; 1817a3348722SBarak Witkowski enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1818adfc5217SJeff Kirsher u32 pending_max; 1819adfc5217SJeff Kirsher 1820adfc5217SJeff Kirsher /* multiple tx classes of service */ 1821adfc5217SJeff Kirsher u8 max_cos; 1822adfc5217SJeff Kirsher 1823adfc5217SJeff Kirsher /* priority to cos mapping */ 1824adfc5217SJeff Kirsher u8 prio_to_cos[8]; 1825c3146eb6SDmitry Kravkov 1826c3146eb6SDmitry Kravkov int fp_array_size; 182707ba6af4SMiriam Shitrit u32 dump_preset_idx; 18283d7d562cSYuval Mintz 18293d7d562cSYuval Mintz u8 phys_port_id[ETH_ALEN]; 18306495d15aSDmitry Kravkov 1831eeed018cSMichal Kalderon /* PTP related context */ 1832eeed018cSMichal Kalderon struct ptp_clock *ptp_clock; 1833eeed018cSMichal Kalderon struct ptp_clock_info ptp_clock_info; 1834eeed018cSMichal Kalderon struct work_struct ptp_task; 1835eeed018cSMichal Kalderon struct cyclecounter cyclecounter; 1836eeed018cSMichal Kalderon struct timecounter timecounter; 1837eeed018cSMichal Kalderon bool timecounter_init_done; 1838eeed018cSMichal Kalderon struct sk_buff *ptp_tx_skb; 1839eeed018cSMichal Kalderon unsigned long ptp_tx_start; 1840eeed018cSMichal Kalderon bool hwtstamp_ioctl_called; 1841eeed018cSMichal Kalderon u16 tx_type; 1842eeed018cSMichal Kalderon u16 rx_filter; 1843eeed018cSMichal Kalderon 18446495d15aSDmitry Kravkov struct bnx2x_link_report_data vf_link_vars; 184505cc5a39SYuval Mintz struct list_head vlan_reg; 184605cc5a39SYuval Mintz u16 vlan_cnt; 184705cc5a39SYuval Mintz u16 vlan_credit; 184805cc5a39SYuval Mintz bool accept_any_vlan; 1849883ce97dSYuval Mintz 1850883ce97dSYuval Mintz /* Vxlan/Geneve related information */ 1851883ce97dSYuval Mintz struct bnx2x_udp_tunnel udp_tunnel_ports[BNX2X_UDP_PORT_MAX]; 1852adfc5217SJeff Kirsher }; 1853adfc5217SJeff Kirsher 1854adfc5217SJeff Kirsher /* Tx queues may be less or equal to Rx queues */ 1855adfc5217SJeff Kirsher extern int num_queues; 1856adfc5217SJeff Kirsher #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 185755c11941SMerav Sicron #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 185865565884SMerav Sicron #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 185955c11941SMerav Sicron (bp)->num_cnic_queues) 1860adfc5217SJeff Kirsher #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1861adfc5217SJeff Kirsher 1862adfc5217SJeff Kirsher #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1863adfc5217SJeff Kirsher 1864adfc5217SJeff Kirsher #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1865adfc5217SJeff Kirsher /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1866adfc5217SJeff Kirsher 1867adfc5217SJeff Kirsher #define RSS_IPV4_CAP_MASK \ 1868adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1869adfc5217SJeff Kirsher 1870adfc5217SJeff Kirsher #define RSS_IPV4_TCP_CAP_MASK \ 1871adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1872adfc5217SJeff Kirsher 1873adfc5217SJeff Kirsher #define RSS_IPV6_CAP_MASK \ 1874adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1875adfc5217SJeff Kirsher 1876adfc5217SJeff Kirsher #define RSS_IPV6_TCP_CAP_MASK \ 1877adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1878adfc5217SJeff Kirsher 1879adfc5217SJeff Kirsher struct bnx2x_func_init_params { 1880adfc5217SJeff Kirsher /* dma */ 188105cc5a39SYuval Mintz bool spq_active; 188205cc5a39SYuval Mintz dma_addr_t spq_map; 188305cc5a39SYuval Mintz u16 spq_prod; 1884adfc5217SJeff Kirsher 1885adfc5217SJeff Kirsher u16 func_id; /* abs fid */ 1886adfc5217SJeff Kirsher u16 pf_id; 1887adfc5217SJeff Kirsher }; 1888adfc5217SJeff Kirsher 188955c11941SMerav Sicron #define for_each_cnic_queue(bp, var) \ 189055c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 189155c11941SMerav Sicron (var)++) \ 189255c11941SMerav Sicron if (skip_queue(bp, var)) \ 189355c11941SMerav Sicron continue; \ 189455c11941SMerav Sicron else 189555c11941SMerav Sicron 1896adfc5217SJeff Kirsher #define for_each_eth_queue(bp, var) \ 1897adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1898adfc5217SJeff Kirsher 1899adfc5217SJeff Kirsher #define for_each_nondefault_eth_queue(bp, var) \ 1900adfc5217SJeff Kirsher for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1901adfc5217SJeff Kirsher 1902adfc5217SJeff Kirsher #define for_each_queue(bp, var) \ 1903adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1904adfc5217SJeff Kirsher if (skip_queue(bp, var)) \ 1905adfc5217SJeff Kirsher continue; \ 1906adfc5217SJeff Kirsher else 1907adfc5217SJeff Kirsher 1908adfc5217SJeff Kirsher /* Skip forwarding FP */ 190955c11941SMerav Sicron #define for_each_valid_rx_queue(bp, var) \ 191055c11941SMerav Sicron for ((var) = 0; \ 191155c11941SMerav Sicron (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 191255c11941SMerav Sicron BNX2X_NUM_ETH_QUEUES(bp)); \ 191355c11941SMerav Sicron (var)++) \ 191455c11941SMerav Sicron if (skip_rx_queue(bp, var)) \ 191555c11941SMerav Sicron continue; \ 191655c11941SMerav Sicron else 191755c11941SMerav Sicron 191855c11941SMerav Sicron #define for_each_rx_queue_cnic(bp, var) \ 191955c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 192055c11941SMerav Sicron (var)++) \ 192155c11941SMerav Sicron if (skip_rx_queue(bp, var)) \ 192255c11941SMerav Sicron continue; \ 192355c11941SMerav Sicron else 192455c11941SMerav Sicron 1925adfc5217SJeff Kirsher #define for_each_rx_queue(bp, var) \ 1926adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1927adfc5217SJeff Kirsher if (skip_rx_queue(bp, var)) \ 1928adfc5217SJeff Kirsher continue; \ 1929adfc5217SJeff Kirsher else 1930adfc5217SJeff Kirsher 1931adfc5217SJeff Kirsher /* Skip OOO FP */ 193255c11941SMerav Sicron #define for_each_valid_tx_queue(bp, var) \ 193355c11941SMerav Sicron for ((var) = 0; \ 193455c11941SMerav Sicron (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 193555c11941SMerav Sicron BNX2X_NUM_ETH_QUEUES(bp)); \ 193655c11941SMerav Sicron (var)++) \ 193755c11941SMerav Sicron if (skip_tx_queue(bp, var)) \ 193855c11941SMerav Sicron continue; \ 193955c11941SMerav Sicron else 194055c11941SMerav Sicron 194155c11941SMerav Sicron #define for_each_tx_queue_cnic(bp, var) \ 194255c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 194355c11941SMerav Sicron (var)++) \ 194455c11941SMerav Sicron if (skip_tx_queue(bp, var)) \ 194555c11941SMerav Sicron continue; \ 194655c11941SMerav Sicron else 194755c11941SMerav Sicron 1948adfc5217SJeff Kirsher #define for_each_tx_queue(bp, var) \ 1949adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1950adfc5217SJeff Kirsher if (skip_tx_queue(bp, var)) \ 1951adfc5217SJeff Kirsher continue; \ 1952adfc5217SJeff Kirsher else 1953adfc5217SJeff Kirsher 1954adfc5217SJeff Kirsher #define for_each_nondefault_queue(bp, var) \ 1955adfc5217SJeff Kirsher for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1956adfc5217SJeff Kirsher if (skip_queue(bp, var)) \ 1957adfc5217SJeff Kirsher continue; \ 1958adfc5217SJeff Kirsher else 1959adfc5217SJeff Kirsher 1960adfc5217SJeff Kirsher #define for_each_cos_in_tx_queue(fp, var) \ 1961adfc5217SJeff Kirsher for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1962adfc5217SJeff Kirsher 1963adfc5217SJeff Kirsher /* skip rx queue 1964adfc5217SJeff Kirsher * if FCOE l2 support is disabled and this is the fcoe L2 queue 1965adfc5217SJeff Kirsher */ 1966adfc5217SJeff Kirsher #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1967adfc5217SJeff Kirsher 1968adfc5217SJeff Kirsher /* skip tx queue 1969adfc5217SJeff Kirsher * if FCOE l2 support is disabled and this is the fcoe L2 queue 1970adfc5217SJeff Kirsher */ 1971adfc5217SJeff Kirsher #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1972adfc5217SJeff Kirsher 1973adfc5217SJeff Kirsher #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1974adfc5217SJeff Kirsher 1975adfc5217SJeff Kirsher /** 1976adfc5217SJeff Kirsher * bnx2x_set_mac_one - configure a single MAC address 1977adfc5217SJeff Kirsher * 1978adfc5217SJeff Kirsher * @bp: driver handle 1979adfc5217SJeff Kirsher * @mac: MAC to configure 1980adfc5217SJeff Kirsher * @obj: MAC object handle 1981adfc5217SJeff Kirsher * @set: if 'true' add a new MAC, otherwise - delete 1982adfc5217SJeff Kirsher * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1983adfc5217SJeff Kirsher * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1984adfc5217SJeff Kirsher * 1985adfc5217SJeff Kirsher * Configures one MAC according to provided parameters or continues the 1986adfc5217SJeff Kirsher * execution of previously scheduled commands if RAMROD_CONT is set in 1987adfc5217SJeff Kirsher * ramrod_flags. 1988adfc5217SJeff Kirsher * 1989adfc5217SJeff Kirsher * Returns zero if operation has successfully completed, a positive value if the 1990adfc5217SJeff Kirsher * operation has been successfully scheduled and a negative - if a requested 1991adfc5217SJeff Kirsher * operations has failed. 1992adfc5217SJeff Kirsher */ 1993adfc5217SJeff Kirsher int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1994adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *obj, bool set, 1995adfc5217SJeff Kirsher int mac_type, unsigned long *ramrod_flags); 199605cc5a39SYuval Mintz 199705cc5a39SYuval Mintz int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan, 199805cc5a39SYuval Mintz struct bnx2x_vlan_mac_obj *obj, bool set, 199905cc5a39SYuval Mintz unsigned long *ramrod_flags); 200005cc5a39SYuval Mintz 2001adfc5217SJeff Kirsher /** 2002adfc5217SJeff Kirsher * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 2003adfc5217SJeff Kirsher * 2004adfc5217SJeff Kirsher * @bp: driver handle 2005adfc5217SJeff Kirsher * @mac_obj: MAC object handle 2006adfc5217SJeff Kirsher * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 2007adfc5217SJeff Kirsher * @wait_for_comp: if 'true' block until completion 2008adfc5217SJeff Kirsher * 2009adfc5217SJeff Kirsher * Deletes all MACs of the specific type (e.g. ETH, UC list). 2010adfc5217SJeff Kirsher * 2011adfc5217SJeff Kirsher * Returns zero if operation has successfully completed, a positive value if the 2012adfc5217SJeff Kirsher * operation has been successfully scheduled and a negative - if a requested 2013adfc5217SJeff Kirsher * operations has failed. 2014adfc5217SJeff Kirsher */ 2015adfc5217SJeff Kirsher int bnx2x_del_all_macs(struct bnx2x *bp, 2016adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj, 2017adfc5217SJeff Kirsher int mac_type, bool wait_for_comp); 2018adfc5217SJeff Kirsher 2019adfc5217SJeff Kirsher /* Init Function API */ 2020adfc5217SJeff Kirsher void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 2021b93288d5SAriel Elior void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 2022b93288d5SAriel Elior u8 vf_valid, int fw_sb_id, int igu_sb_id); 2023adfc5217SJeff Kirsher int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 2024adfc5217SJeff Kirsher int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2025adfc5217SJeff Kirsher int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 2026adfc5217SJeff Kirsher int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2027adfc5217SJeff Kirsher void bnx2x_read_mf_cfg(struct bnx2x *bp); 2028adfc5217SJeff Kirsher 2029b56e9670SAriel Elior int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 2030adfc5217SJeff Kirsher 2031adfc5217SJeff Kirsher /* dmae */ 2032adfc5217SJeff Kirsher void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 2033adfc5217SJeff Kirsher void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 2034adfc5217SJeff Kirsher u32 len32); 2035adfc5217SJeff Kirsher void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 2036adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 2037adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 2038adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 2039adfc5217SJeff Kirsher bool with_comp, u8 comp_type); 2040adfc5217SJeff Kirsher 2041fd1fc79dSAriel Elior void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2042fd1fc79dSAriel Elior u8 src_type, u8 dst_type); 204332316a46SAriel Elior int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 204432316a46SAriel Elior u32 *comp); 2045fd1fc79dSAriel Elior 2046d16132ceSAriel Elior /* FLR related routines */ 2047d16132ceSAriel Elior u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 2048d16132ceSAriel Elior void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 2049d16132ceSAriel Elior int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 2050b56e9670SAriel Elior u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 2051d16132ceSAriel Elior int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 2052d16132ceSAriel Elior char *msg, u32 poll_cnt); 2053adfc5217SJeff Kirsher 2054adfc5217SJeff Kirsher void bnx2x_calc_fc_adv(struct bnx2x *bp); 2055adfc5217SJeff Kirsher int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 2056adfc5217SJeff Kirsher u32 data_hi, u32 data_lo, int cmd_type); 2057adfc5217SJeff Kirsher void bnx2x_update_coalesce(struct bnx2x *bp); 2058adfc5217SJeff Kirsher int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 2059adfc5217SJeff Kirsher 2060178135c1SDmitry Kravkov bool bnx2x_port_after_undi(struct bnx2x *bp); 2061178135c1SDmitry Kravkov 2062adfc5217SJeff Kirsher static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 2063adfc5217SJeff Kirsher int wait) 2064adfc5217SJeff Kirsher { 2065adfc5217SJeff Kirsher u32 val; 2066adfc5217SJeff Kirsher 2067adfc5217SJeff Kirsher do { 2068adfc5217SJeff Kirsher val = REG_RD(bp, reg); 2069adfc5217SJeff Kirsher if (val == expected) 2070adfc5217SJeff Kirsher break; 2071adfc5217SJeff Kirsher ms -= wait; 2072adfc5217SJeff Kirsher msleep(wait); 2073adfc5217SJeff Kirsher 2074adfc5217SJeff Kirsher } while (ms > 0); 2075adfc5217SJeff Kirsher 2076adfc5217SJeff Kirsher return val; 2077adfc5217SJeff Kirsher } 2078adfc5217SJeff Kirsher 2079b56e9670SAriel Elior void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 2080b56e9670SAriel Elior bool is_pf); 2081b56e9670SAriel Elior 2082adfc5217SJeff Kirsher #define BNX2X_ILT_ZALLOC(x, y, size) \ 2083ede23fa8SJoe Perches x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL) 2084adfc5217SJeff Kirsher 2085adfc5217SJeff Kirsher #define BNX2X_ILT_FREE(x, y, size) \ 2086adfc5217SJeff Kirsher do { \ 2087adfc5217SJeff Kirsher if (x) { \ 2088adfc5217SJeff Kirsher dma_free_coherent(&bp->pdev->dev, size, x, y); \ 2089adfc5217SJeff Kirsher x = NULL; \ 2090adfc5217SJeff Kirsher y = 0; \ 2091adfc5217SJeff Kirsher } \ 2092adfc5217SJeff Kirsher } while (0) 2093adfc5217SJeff Kirsher 2094adfc5217SJeff Kirsher #define ILOG2(x) (ilog2((x))) 2095adfc5217SJeff Kirsher 2096adfc5217SJeff Kirsher #define ILT_NUM_PAGE_ENTRIES (3072) 2097adfc5217SJeff Kirsher /* In 57710/11 we use whole table since we have 8 func 2098adfc5217SJeff Kirsher * In 57712 we have only 4 func, but use same size per func, then only half of 2099adfc5217SJeff Kirsher * the table in use 2100adfc5217SJeff Kirsher */ 2101adfc5217SJeff Kirsher #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 2102adfc5217SJeff Kirsher 2103adfc5217SJeff Kirsher #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 2104adfc5217SJeff Kirsher /* 2105adfc5217SJeff Kirsher * the phys address is shifted right 12 bits and has an added 2106adfc5217SJeff Kirsher * 1=valid bit added to the 53rd bit 2107adfc5217SJeff Kirsher * then since this is a wide register(TM) 2108adfc5217SJeff Kirsher * we split it into two 32 bit writes 2109adfc5217SJeff Kirsher */ 2110adfc5217SJeff Kirsher #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 2111adfc5217SJeff Kirsher #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 2112adfc5217SJeff Kirsher 2113adfc5217SJeff Kirsher /* load/unload mode */ 2114adfc5217SJeff Kirsher #define LOAD_NORMAL 0 2115adfc5217SJeff Kirsher #define LOAD_OPEN 1 2116adfc5217SJeff Kirsher #define LOAD_DIAG 2 21178970b2e4SMerav Sicron #define LOAD_LOOPBACK_EXT 3 2118adfc5217SJeff Kirsher #define UNLOAD_NORMAL 0 2119adfc5217SJeff Kirsher #define UNLOAD_CLOSE 1 2120adfc5217SJeff Kirsher #define UNLOAD_RECOVERY 2 2121adfc5217SJeff Kirsher 2122adfc5217SJeff Kirsher /* DMAE command defines */ 2123adfc5217SJeff Kirsher #define DMAE_TIMEOUT -1 2124adfc5217SJeff Kirsher #define DMAE_PCI_ERROR -2 /* E2 and onward */ 2125adfc5217SJeff Kirsher #define DMAE_NOT_RDY -3 2126adfc5217SJeff Kirsher #define DMAE_PCI_ERR_FLAG 0x80000000 2127adfc5217SJeff Kirsher 2128adfc5217SJeff Kirsher #define DMAE_SRC_PCI 0 2129adfc5217SJeff Kirsher #define DMAE_SRC_GRC 1 2130adfc5217SJeff Kirsher 2131adfc5217SJeff Kirsher #define DMAE_DST_NONE 0 2132adfc5217SJeff Kirsher #define DMAE_DST_PCI 1 2133adfc5217SJeff Kirsher #define DMAE_DST_GRC 2 2134adfc5217SJeff Kirsher 2135adfc5217SJeff Kirsher #define DMAE_COMP_PCI 0 2136adfc5217SJeff Kirsher #define DMAE_COMP_GRC 1 2137adfc5217SJeff Kirsher 2138adfc5217SJeff Kirsher /* E2 and onward - PCI error handling in the completion */ 2139adfc5217SJeff Kirsher 2140adfc5217SJeff Kirsher #define DMAE_COMP_REGULAR 0 2141adfc5217SJeff Kirsher #define DMAE_COM_SET_ERR 1 2142adfc5217SJeff Kirsher 2143adfc5217SJeff Kirsher #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2144adfc5217SJeff Kirsher DMAE_COMMAND_SRC_SHIFT) 2145adfc5217SJeff Kirsher #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2146adfc5217SJeff Kirsher DMAE_COMMAND_SRC_SHIFT) 2147adfc5217SJeff Kirsher 2148adfc5217SJeff Kirsher #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2149adfc5217SJeff Kirsher DMAE_COMMAND_DST_SHIFT) 2150adfc5217SJeff Kirsher #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2151adfc5217SJeff Kirsher DMAE_COMMAND_DST_SHIFT) 2152adfc5217SJeff Kirsher 2153adfc5217SJeff Kirsher #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2154adfc5217SJeff Kirsher DMAE_COMMAND_C_DST_SHIFT) 2155adfc5217SJeff Kirsher #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2156adfc5217SJeff Kirsher DMAE_COMMAND_C_DST_SHIFT) 2157adfc5217SJeff Kirsher 2158adfc5217SJeff Kirsher #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2159adfc5217SJeff Kirsher 2160adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2161adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2162adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2163adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2164adfc5217SJeff Kirsher 2165adfc5217SJeff Kirsher #define DMAE_CMD_PORT_0 0 2166adfc5217SJeff Kirsher #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2167adfc5217SJeff Kirsher 2168adfc5217SJeff Kirsher #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2169adfc5217SJeff Kirsher #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2170adfc5217SJeff Kirsher #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2171adfc5217SJeff Kirsher 2172adfc5217SJeff Kirsher #define DMAE_SRC_PF 0 2173adfc5217SJeff Kirsher #define DMAE_SRC_VF 1 2174adfc5217SJeff Kirsher 2175adfc5217SJeff Kirsher #define DMAE_DST_PF 0 2176adfc5217SJeff Kirsher #define DMAE_DST_VF 1 2177adfc5217SJeff Kirsher 2178adfc5217SJeff Kirsher #define DMAE_C_SRC 0 2179adfc5217SJeff Kirsher #define DMAE_C_DST 1 2180adfc5217SJeff Kirsher 2181adfc5217SJeff Kirsher #define DMAE_LEN32_RD_MAX 0x80 2182adfc5217SJeff Kirsher #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2183adfc5217SJeff Kirsher 2184adfc5217SJeff Kirsher #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 218516a5fd92SYuval Mintz * indicates error 218616a5fd92SYuval Mintz */ 2187adfc5217SJeff Kirsher 2188adfc5217SJeff Kirsher #define MAX_DMAE_C_PER_PORT 8 2189adfc5217SJeff Kirsher #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 21908decf868SDavid S. Miller BP_VN(bp)) 2191adfc5217SJeff Kirsher #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2192adfc5217SJeff Kirsher E1HVN_MAX) 2193adfc5217SJeff Kirsher 219477e461d1SSudarsana Reddy Kalluru /* Following is the DMAE channel number allocation for the clients. 219577e461d1SSudarsana Reddy Kalluru * MFW: OCBB/OCSD implementations use DMAE channels 14/15 respectively. 219677e461d1SSudarsana Reddy Kalluru * Driver: 0-3 and 8-11 (for PF dmae operations) 219777e461d1SSudarsana Reddy Kalluru * 4 and 12 (for stats requests) 219877e461d1SSudarsana Reddy Kalluru */ 219977e461d1SSudarsana Reddy Kalluru #define BNX2X_FW_DMAE_C 13 /* Channel for FW DMAE operations */ 220077e461d1SSudarsana Reddy Kalluru 2201adfc5217SJeff Kirsher /* PCIE link and speed */ 2202adfc5217SJeff Kirsher #define PCICFG_LINK_WIDTH 0x1f00000 2203adfc5217SJeff Kirsher #define PCICFG_LINK_WIDTH_SHIFT 20 2204adfc5217SJeff Kirsher #define PCICFG_LINK_SPEED 0xf0000 2205adfc5217SJeff Kirsher #define PCICFG_LINK_SPEED_SHIFT 16 2206adfc5217SJeff Kirsher 2207cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS_SF 7 2208cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS_MF 3 2209cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 221075543741SYuval Mintz IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF) 2211adfc5217SJeff Kirsher 2212adfc5217SJeff Kirsher #define BNX2X_PHY_LOOPBACK 0 2213adfc5217SJeff Kirsher #define BNX2X_MAC_LOOPBACK 1 22148970b2e4SMerav Sicron #define BNX2X_EXT_LOOPBACK 2 2215adfc5217SJeff Kirsher #define BNX2X_PHY_LOOPBACK_FAILED 1 2216adfc5217SJeff Kirsher #define BNX2X_MAC_LOOPBACK_FAILED 2 22178970b2e4SMerav Sicron #define BNX2X_EXT_LOOPBACK_FAILED 3 2218adfc5217SJeff Kirsher #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2219adfc5217SJeff Kirsher BNX2X_PHY_LOOPBACK_FAILED) 2220adfc5217SJeff Kirsher 2221adfc5217SJeff Kirsher #define STROM_ASSERT_ARRAY_SIZE 50 2222adfc5217SJeff Kirsher 2223adfc5217SJeff Kirsher /* must be used on a CID before placing it on a HW ring */ 2224adfc5217SJeff Kirsher #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 22258decf868SDavid S. Miller (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2226adfc5217SJeff Kirsher (x)) 2227adfc5217SJeff Kirsher 2228adfc5217SJeff Kirsher #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2229adfc5217SJeff Kirsher #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2230adfc5217SJeff Kirsher 2231adfc5217SJeff Kirsher #define BNX2X_BTR 4 2232adfc5217SJeff Kirsher #define MAX_SPQ_PENDING 8 2233adfc5217SJeff Kirsher 2234adfc5217SJeff Kirsher /* CMNG constants, as derived from system spec calculations */ 2235adfc5217SJeff Kirsher /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2236adfc5217SJeff Kirsher #define DEF_MIN_RATE 100 2237adfc5217SJeff Kirsher /* resolution of the rate shaping timer - 400 usec */ 2238adfc5217SJeff Kirsher #define RS_PERIODIC_TIMEOUT_USEC 400 2239adfc5217SJeff Kirsher /* number of bytes in single QM arbitration cycle - 2240adfc5217SJeff Kirsher * coefficient for calculating the fairness timer */ 2241adfc5217SJeff Kirsher #define QM_ARB_BYTES 160000 2242adfc5217SJeff Kirsher /* resolution of Min algorithm 1:100 */ 2243adfc5217SJeff Kirsher #define MIN_RES 100 2244adfc5217SJeff Kirsher /* how many bytes above threshold for the minimal credit of Min algorithm*/ 2245adfc5217SJeff Kirsher #define MIN_ABOVE_THRESH 32768 2246adfc5217SJeff Kirsher /* Fairness algorithm integration time coefficient - 2247adfc5217SJeff Kirsher * for calculating the actual Tfair */ 2248adfc5217SJeff Kirsher #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2249adfc5217SJeff Kirsher /* Memory of fairness algorithm . 2 cycles */ 2250adfc5217SJeff Kirsher #define FAIR_MEM 2 2251adfc5217SJeff Kirsher 2252adfc5217SJeff Kirsher #define ATTN_NIG_FOR_FUNC (1L << 8) 2253adfc5217SJeff Kirsher #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2254adfc5217SJeff Kirsher #define GPIO_2_FUNC (1L << 10) 2255adfc5217SJeff Kirsher #define GPIO_3_FUNC (1L << 11) 2256adfc5217SJeff Kirsher #define GPIO_4_FUNC (1L << 12) 2257adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_1 (1L << 13) 2258adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_2 (1L << 14) 2259adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_3 (1L << 15) 2260adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_4 (1L << 13) 2261adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_5 (1L << 14) 2262adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_6 (1L << 15) 2263adfc5217SJeff Kirsher 2264adfc5217SJeff Kirsher #define ATTN_HARD_WIRED_MASK 0xff00 2265adfc5217SJeff Kirsher #define ATTENTION_ID 4 2266adfc5217SJeff Kirsher 22672e98ffc2SDmitry Kravkov #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \ 22683521b419SYuval Mintz IS_MF_FCOE_AFEX(bp)) 2269adfc5217SJeff Kirsher 2270adfc5217SJeff Kirsher /* stuff added to make the code fit 80Col */ 2271adfc5217SJeff Kirsher 2272adfc5217SJeff Kirsher #define BNX2X_PMF_LINK_ASSERT \ 2273adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2274adfc5217SJeff Kirsher 2275adfc5217SJeff Kirsher #define BNX2X_MC_ASSERT_BITS \ 2276adfc5217SJeff Kirsher (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2277adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2278adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2279adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2280adfc5217SJeff Kirsher 2281adfc5217SJeff Kirsher #define BNX2X_MCP_ASSERT \ 2282adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2283adfc5217SJeff Kirsher 2284adfc5217SJeff Kirsher #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2285adfc5217SJeff Kirsher #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2286adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2287adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2288adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2289adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2290adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2291adfc5217SJeff Kirsher 2292a8919661SColin Ian King #define HW_INTERRUPT_ASSERT_SET_0 \ 2293adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2294adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2295adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2296c14a09b7SDmitry Kravkov AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2297adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2298adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2299adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2300adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2301adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2302adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2303adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2304adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2305a8919661SColin Ian King #define HW_INTERRUPT_ASSERT_SET_1 \ 2306adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2307adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2308adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2309adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2310adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2311adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2312adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2313adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2314adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2315adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2316adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2317adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2318adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2319adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2320adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2321adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2322adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2323adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2324adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2325adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2326adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2327adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2328adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2329adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2330adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2331adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2332adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2333a8919661SColin Ian King #define HW_INTERRUPT_ASSERT_SET_2 \ 2334adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2335adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2336adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2337adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2338adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2339adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2340adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2341adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2342adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2343adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2344adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2345adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2346adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2347adfc5217SJeff Kirsher 2348ad6afbe9SManish Chopra #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \ 2349ad6afbe9SManish Chopra (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2350adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2351ad6afbe9SManish Chopra AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY) 2352ad6afbe9SManish Chopra 2353ad6afbe9SManish Chopra #define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \ 2354adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2355adfc5217SJeff Kirsher 2356adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2357adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2358adfc5217SJeff Kirsher 2359adfc5217SJeff Kirsher #define MULTI_MASK 0x7f 2360adfc5217SJeff Kirsher 2361adfc5217SJeff Kirsher #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2362adfc5217SJeff Kirsher #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2363adfc5217SJeff Kirsher #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2364adfc5217SJeff Kirsher #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2365adfc5217SJeff Kirsher 2366adfc5217SJeff Kirsher #define DEF_USB_IGU_INDEX_OFF \ 2367adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_u, igu_index) 2368adfc5217SJeff Kirsher #define DEF_CSB_IGU_INDEX_OFF \ 2369adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_c, igu_index) 2370adfc5217SJeff Kirsher #define DEF_XSB_IGU_INDEX_OFF \ 2371adfc5217SJeff Kirsher offsetof(struct xstorm_def_status_block, igu_index) 2372adfc5217SJeff Kirsher #define DEF_TSB_IGU_INDEX_OFF \ 2373adfc5217SJeff Kirsher offsetof(struct tstorm_def_status_block, igu_index) 2374adfc5217SJeff Kirsher 2375adfc5217SJeff Kirsher #define DEF_USB_SEGMENT_OFF \ 2376adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_u, segment) 2377adfc5217SJeff Kirsher #define DEF_CSB_SEGMENT_OFF \ 2378adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_c, segment) 2379adfc5217SJeff Kirsher #define DEF_XSB_SEGMENT_OFF \ 2380adfc5217SJeff Kirsher offsetof(struct xstorm_def_status_block, segment) 2381adfc5217SJeff Kirsher #define DEF_TSB_SEGMENT_OFF \ 2382adfc5217SJeff Kirsher offsetof(struct tstorm_def_status_block, segment) 2383adfc5217SJeff Kirsher 2384adfc5217SJeff Kirsher #define BNX2X_SP_DSB_INDEX \ 2385adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\ 2386adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2387adfc5217SJeff Kirsher 2388adfc5217SJeff Kirsher #define CAM_IS_INVALID(x) \ 2389adfc5217SJeff Kirsher (GET_FLAG(x.flags, \ 2390adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2391adfc5217SJeff Kirsher (T_ETH_MAC_COMMAND_INVALIDATE)) 2392adfc5217SJeff Kirsher 2393adfc5217SJeff Kirsher /* Number of u32 elements in MC hash array */ 2394adfc5217SJeff Kirsher #define MC_HASH_SIZE 8 2395adfc5217SJeff Kirsher #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2396adfc5217SJeff Kirsher TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2397adfc5217SJeff Kirsher 2398adfc5217SJeff Kirsher #ifndef PXP2_REG_PXP2_INT_STS 2399adfc5217SJeff Kirsher #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2400adfc5217SJeff Kirsher #endif 2401adfc5217SJeff Kirsher 2402adfc5217SJeff Kirsher #ifndef ETH_MAX_RX_CLIENTS_E2 2403adfc5217SJeff Kirsher #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2404adfc5217SJeff Kirsher #endif 2405adfc5217SJeff Kirsher 2406adfc5217SJeff Kirsher #define BNX2X_VPD_LEN 128 2407adfc5217SJeff Kirsher #define VENDOR_ID_LEN 4 2408adfc5217SJeff Kirsher 2409be1f1ffaSAriel Elior #define VF_ACQUIRE_THRESH 3 2410be1f1ffaSAriel Elior #define VF_ACQUIRE_MAC_FILTERS 1 2411be1f1ffaSAriel Elior #define VF_ACQUIRE_MC_FILTERS 10 241205cc5a39SYuval Mintz #define VF_ACQUIRE_VLAN_FILTERS 2 /* VLAN0 + 'real' VLAN */ 2413be1f1ffaSAriel Elior 2414be1f1ffaSAriel Elior #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2415be1f1ffaSAriel Elior (!((me_reg) & ME_REG_VF_ERR))) 241691ebb929SYuval Mintz int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err); 241791ebb929SYuval Mintz 2418adfc5217SJeff Kirsher /* Congestion management fairness mode */ 2419adfc5217SJeff Kirsher #define CMNG_FNS_NONE 0 2420adfc5217SJeff Kirsher #define CMNG_FNS_MINMAX 1 2421adfc5217SJeff Kirsher 2422adfc5217SJeff Kirsher #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2423adfc5217SJeff Kirsher #define HC_SEG_ACCESS_ATTN 4 2424adfc5217SJeff Kirsher #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2425adfc5217SJeff Kirsher 2426adfc5217SJeff Kirsher static const u32 dmae_reg_go_c[] = { 2427adfc5217SJeff Kirsher DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2428adfc5217SJeff Kirsher DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2429adfc5217SJeff Kirsher DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2430adfc5217SJeff Kirsher DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2431adfc5217SJeff Kirsher }; 2432adfc5217SJeff Kirsher 2433005a07baSAriel Elior void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); 2434adfc5217SJeff Kirsher void bnx2x_notify_link_changed(struct bnx2x *bp); 2435614c76dfSDmitry Kravkov 24369e62e912SDmitry Kravkov #define BNX2X_MF_SD_PROTOCOL(bp) \ 2437614c76dfSDmitry Kravkov ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2438614c76dfSDmitry Kravkov 24399e62e912SDmitry Kravkov #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 24409e62e912SDmitry Kravkov (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2441614c76dfSDmitry Kravkov 24429e62e912SDmitry Kravkov #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 24439e62e912SDmitry Kravkov (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 24449e62e912SDmitry Kravkov 24459e62e912SDmitry Kravkov #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 24469e62e912SDmitry Kravkov #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 24472e98ffc2SDmitry Kravkov #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp)) 24489e62e912SDmitry Kravkov 24492e98ffc2SDmitry Kravkov #define IS_MF_ISCSI_ONLY(bp) (IS_MF_ISCSI_SD(bp) || IS_MF_ISCSI_SI(bp)) 24502e98ffc2SDmitry Kravkov 24512e98ffc2SDmitry Kravkov #define BNX2X_MF_EXT_PROTOCOL_MASK \ 24522e98ffc2SDmitry Kravkov (MACP_FUNC_CFG_FLAGS_ETHERNET | \ 24532e98ffc2SDmitry Kravkov MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD | \ 2454a3348722SBarak Witkowski MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2455a3348722SBarak Witkowski 24562e98ffc2SDmitry Kravkov #define BNX2X_MF_EXT_PROT(bp) ((bp)->mf_ext_config & \ 24572e98ffc2SDmitry Kravkov BNX2X_MF_EXT_PROTOCOL_MASK) 24582e98ffc2SDmitry Kravkov 24592e98ffc2SDmitry Kravkov #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) \ 24602e98ffc2SDmitry Kravkov (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 24612e98ffc2SDmitry Kravkov 24622e98ffc2SDmitry Kravkov #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) \ 24632e98ffc2SDmitry Kravkov (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 24642e98ffc2SDmitry Kravkov 24652e98ffc2SDmitry Kravkov #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) \ 24662e98ffc2SDmitry Kravkov (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) 24672e98ffc2SDmitry Kravkov 24682e98ffc2SDmitry Kravkov #define IS_MF_FCOE_AFEX(bp) \ 24692e98ffc2SDmitry Kravkov (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)) 24702e98ffc2SDmitry Kravkov 24712e98ffc2SDmitry Kravkov #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) \ 24722e98ffc2SDmitry Kravkov (IS_MF_SD(bp) && \ 24739e62e912SDmitry Kravkov (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 24749e62e912SDmitry Kravkov BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2475614c76dfSDmitry Kravkov 24762e98ffc2SDmitry Kravkov #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) \ 24772e98ffc2SDmitry Kravkov (IS_MF_SI(bp) && \ 24782e98ffc2SDmitry Kravkov (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \ 24792e98ffc2SDmitry Kravkov BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))) 24802e98ffc2SDmitry Kravkov 24812e98ffc2SDmitry Kravkov #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) \ 24822e98ffc2SDmitry Kravkov (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) || \ 24832e98ffc2SDmitry Kravkov IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp)) 24842e98ffc2SDmitry Kravkov 2485da3cc2daSYuval Mintz /* Determines whether BW configuration arrives in 100Mb units or in 2486da3cc2daSYuval Mintz * percentages from actual physical link speed. 2487da3cc2daSYuval Mintz */ 2488da3cc2daSYuval Mintz #define IS_MF_PERCENT_BW(bp) (IS_MF_SI(bp) || IS_MF_UFP(bp) || IS_MF_BD(bp)) 24892e98ffc2SDmitry Kravkov 24902de67439SYuval Mintz #define SET_FLAG(value, mask, flag) \ 24912de67439SYuval Mintz do {\ 24922de67439SYuval Mintz (value) &= ~(mask);\ 24932de67439SYuval Mintz (value) |= ((flag) << (mask##_SHIFT));\ 24942de67439SYuval Mintz } while (0) 24952de67439SYuval Mintz 24962de67439SYuval Mintz #define GET_FLAG(value, mask) \ 24972de67439SYuval Mintz (((value) & (mask)) >> (mask##_SHIFT)) 24982de67439SYuval Mintz 24992de67439SYuval Mintz #define GET_FIELD(value, fname) \ 25002de67439SYuval Mintz (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 25012de67439SYuval Mintz 250255c11941SMerav Sicron enum { 250355c11941SMerav Sicron SWITCH_UPDATE, 250455c11941SMerav Sicron AFEX_UPDATE, 250555c11941SMerav Sicron }; 250655c11941SMerav Sicron 250755c11941SMerav Sicron #define NUM_MACS 8 2508a3348722SBarak Witkowski 2509568e2426SDmitry Kravkov void bnx2x_set_local_cmng(struct bnx2x *bp); 25101a6974b2SYuval Mintz 251142f8277fSYuval Mintz void bnx2x_update_mng_version(struct bnx2x *bp); 251242f8277fSYuval Mintz 2513c48f350fSYuval Mintz void bnx2x_update_mfw_dump(struct bnx2x *bp); 2514c48f350fSYuval Mintz 25151a6974b2SYuval Mintz #define MCPR_SCRATCH_BASE(bp) \ 25161a6974b2SYuval Mintz (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 25171a6974b2SYuval Mintz 2518e848582cSDmitry Kravkov #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX)) 2519e848582cSDmitry Kravkov 2520eeed018cSMichal Kalderon void bnx2x_init_ptp(struct bnx2x *bp); 2521eeed018cSMichal Kalderon int bnx2x_configure_ptp_filters(struct bnx2x *bp); 2522eeed018cSMichal Kalderon void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb); 252307f12622SSudarsana Reddy Kalluru void bnx2x_register_phc(struct bnx2x *bp); 2524eeed018cSMichal Kalderon 2525eeed018cSMichal Kalderon #define BNX2X_MAX_PHC_DRIFT 31000000 2526eeed018cSMichal Kalderon #define BNX2X_PTP_TX_TIMEOUT 2527eeed018cSMichal Kalderon 252805cc5a39SYuval Mintz /* Re-configure all previously configured vlan filters. 252905cc5a39SYuval Mintz * Meant for implicit re-load flows. 253005cc5a39SYuval Mintz */ 253105cc5a39SYuval Mintz int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp); 253205cc5a39SYuval Mintz 2533adfc5217SJeff Kirsher #endif /* bnx2x.h */ 2534