14ad79e13SYuval Mintz /* bnx2x.h: QLogic Everest network driver.
2adfc5217SJeff Kirsher *
3247fa82bSYuval Mintz * Copyright (c) 2007-2013 Broadcom Corporation
44ad79e13SYuval Mintz * Copyright (c) 2014 QLogic Corporation
54ad79e13SYuval Mintz * All rights reserved
6adfc5217SJeff Kirsher *
7adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify
8adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by
9adfc5217SJeff Kirsher * the Free Software Foundation.
10adfc5217SJeff Kirsher *
1108f6dd89SAriel Elior * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12adfc5217SJeff Kirsher * Written by: Eliezer Tamir
13adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver
14adfc5217SJeff Kirsher */
15adfc5217SJeff Kirsher
16adfc5217SJeff Kirsher #ifndef BNX2X_H
17adfc5217SJeff Kirsher #define BNX2X_H
18290ca2bbSAriel Elior
19290ca2bbSAriel Elior #include <linux/pci.h>
20adfc5217SJeff Kirsher #include <linux/netdevice.h>
21adfc5217SJeff Kirsher #include <linux/dma-mapping.h>
22adfc5217SJeff Kirsher #include <linux/types.h>
23290ca2bbSAriel Elior #include <linux/pci_regs.h>
24adfc5217SJeff Kirsher
25eeed018cSMichal Kalderon #include <linux/ptp_clock_kernel.h>
26eeed018cSMichal Kalderon #include <linux/net_tstamp.h>
2774d23cc7SRichard Cochran #include <linux/timecounter.h>
28eeed018cSMichal Kalderon
29adfc5217SJeff Kirsher /* compilation time flags */
30adfc5217SJeff Kirsher
31adfc5217SJeff Kirsher /* define this to make the driver freeze on error to allow getting debug info
32adfc5217SJeff Kirsher * (you will need to reboot afterwards) */
33adfc5217SJeff Kirsher /* #define BNX2X_STOP_ON_ERROR */
34adfc5217SJeff Kirsher
35e3c0a635SLeon Romanovsky /* FIXME: Delete the DRV_MODULE_VERSION below, but please be warned
36e3c0a635SLeon Romanovsky * that it is not an easy task because such change has all chances
37e3c0a635SLeon Romanovsky * to break this driver due to amount of abuse of in-kernel interfaces
38e3c0a635SLeon Romanovsky * between modules and FW.
39e3c0a635SLeon Romanovsky *
40e3c0a635SLeon Romanovsky * DO NOT UPDATE DRV_MODULE_VERSION below.
41e3c0a635SLeon Romanovsky */
42f1164653SSudarsana Reddy Kalluru #define DRV_MODULE_VERSION "1.713.36-0"
43adfc5217SJeff Kirsher #define BNX2X_BC_VER 0x040200
44adfc5217SJeff Kirsher
45adfc5217SJeff Kirsher #if defined(CONFIG_DCB)
46adfc5217SJeff Kirsher #define BCM_DCBNL
47adfc5217SJeff Kirsher #endif
48b475d78fSYuval Mintz
49b475d78fSYuval Mintz #include "bnx2x_hsi.h"
50b475d78fSYuval Mintz
51adfc5217SJeff Kirsher #include "../cnic_if.h"
52adfc5217SJeff Kirsher
5355c11941SMerav Sicron #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
54adfc5217SJeff Kirsher
55adfc5217SJeff Kirsher #include <linux/mdio.h>
56adfc5217SJeff Kirsher
57adfc5217SJeff Kirsher #include "bnx2x_reg.h"
58adfc5217SJeff Kirsher #include "bnx2x_fw_defs.h"
592e499d3cSBarak Witkowski #include "bnx2x_mfw_req.h"
60adfc5217SJeff Kirsher #include "bnx2x_link.h"
61adfc5217SJeff Kirsher #include "bnx2x_sp.h"
62adfc5217SJeff Kirsher #include "bnx2x_dcb.h"
63adfc5217SJeff Kirsher #include "bnx2x_stats.h"
64be1f1ffaSAriel Elior #include "bnx2x_vfpf.h"
65adfc5217SJeff Kirsher
661ab4434cSAriel Elior enum bnx2x_int_mode {
671ab4434cSAriel Elior BNX2X_INT_MODE_MSIX,
681ab4434cSAriel Elior BNX2X_INT_MODE_INTX,
691ab4434cSAriel Elior BNX2X_INT_MODE_MSI
701ab4434cSAriel Elior };
711ab4434cSAriel Elior
72adfc5217SJeff Kirsher /* error/debug prints */
73adfc5217SJeff Kirsher
74adfc5217SJeff Kirsher #define DRV_MODULE_NAME "bnx2x"
75adfc5217SJeff Kirsher
76adfc5217SJeff Kirsher /* for messages that are currently off */
7751c1a580SMerav Sicron #define BNX2X_MSG_OFF 0x0
7851c1a580SMerav Sicron #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
7951c1a580SMerav Sicron #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
8051c1a580SMerav Sicron #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
8151c1a580SMerav Sicron #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
8251c1a580SMerav Sicron #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
8351c1a580SMerav Sicron #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
8451c1a580SMerav Sicron #define BNX2X_MSG_IOV 0x0800000
85eeed018cSMichal Kalderon #define BNX2X_MSG_PTP 0x1000000
8651c1a580SMerav Sicron #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
8751c1a580SMerav Sicron #define BNX2X_MSG_ETHTOOL 0x4000000
8851c1a580SMerav Sicron #define BNX2X_MSG_DCB 0x8000000
89adfc5217SJeff Kirsher
90adfc5217SJeff Kirsher /* regular debug print */
9176ca70faSYuval Mintz #define DP_INNER(fmt, ...) \
92f1deab50SJoe Perches pr_notice("[%s:%d(%s)]" fmt, \
93adfc5217SJeff Kirsher __func__, __LINE__, \
94adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \
9576ca70faSYuval Mintz ##__VA_ARGS__);
9676ca70faSYuval Mintz
9776ca70faSYuval Mintz #define DP(__mask, fmt, ...) \
9876ca70faSYuval Mintz do { \
9976ca70faSYuval Mintz if (unlikely(bp->msg_enable & (__mask))) \
10076ca70faSYuval Mintz DP_INNER(fmt, ##__VA_ARGS__); \
10176ca70faSYuval Mintz } while (0)
10276ca70faSYuval Mintz
10376ca70faSYuval Mintz #define DP_AND(__mask, fmt, ...) \
10476ca70faSYuval Mintz do { \
10576ca70faSYuval Mintz if (unlikely((bp->msg_enable & (__mask)) == __mask)) \
10676ca70faSYuval Mintz DP_INNER(fmt, ##__VA_ARGS__); \
107adfc5217SJeff Kirsher } while (0)
108adfc5217SJeff Kirsher
109f1deab50SJoe Perches #define DP_CONT(__mask, fmt, ...) \
110adfc5217SJeff Kirsher do { \
11151c1a580SMerav Sicron if (unlikely(bp->msg_enable & (__mask))) \
112f1deab50SJoe Perches pr_cont(fmt, ##__VA_ARGS__); \
113adfc5217SJeff Kirsher } while (0)
114adfc5217SJeff Kirsher
115adfc5217SJeff Kirsher /* errors debug print */
116f1deab50SJoe Perches #define BNX2X_DBG_ERR(fmt, ...) \
117adfc5217SJeff Kirsher do { \
11851c1a580SMerav Sicron if (unlikely(netif_msg_probe(bp))) \
119f1deab50SJoe Perches pr_err("[%s:%d(%s)]" fmt, \
120adfc5217SJeff Kirsher __func__, __LINE__, \
121adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \
122f1deab50SJoe Perches ##__VA_ARGS__); \
123adfc5217SJeff Kirsher } while (0)
124adfc5217SJeff Kirsher
125adfc5217SJeff Kirsher /* for errors (never masked) */
126f1deab50SJoe Perches #define BNX2X_ERR(fmt, ...) \
127adfc5217SJeff Kirsher do { \
128f1deab50SJoe Perches pr_err("[%s:%d(%s)]" fmt, \
129adfc5217SJeff Kirsher __func__, __LINE__, \
130adfc5217SJeff Kirsher bp->dev ? (bp->dev->name) : "?", \
131f1deab50SJoe Perches ##__VA_ARGS__); \
132adfc5217SJeff Kirsher } while (0)
133adfc5217SJeff Kirsher
134f1deab50SJoe Perches #define BNX2X_ERROR(fmt, ...) \
135f1deab50SJoe Perches pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
136adfc5217SJeff Kirsher
137adfc5217SJeff Kirsher /* before we have a dev->name use dev_info() */
138f1deab50SJoe Perches #define BNX2X_DEV_INFO(fmt, ...) \
139adfc5217SJeff Kirsher do { \
14051c1a580SMerav Sicron if (unlikely(netif_msg_probe(bp))) \
141f1deab50SJoe Perches dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
142adfc5217SJeff Kirsher } while (0)
143adfc5217SJeff Kirsher
144ca9bdb9bSYuval Mintz /* Error handling */
145ca9bdb9bSYuval Mintz void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
146adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR
147f1deab50SJoe Perches #define bnx2x_panic() \
148f1deab50SJoe Perches do { \
149adfc5217SJeff Kirsher bp->panic = 1; \
150adfc5217SJeff Kirsher BNX2X_ERR("driver assert\n"); \
151823e1d90SYuval Mintz bnx2x_panic_dump(bp, true); \
152adfc5217SJeff Kirsher } while (0)
153adfc5217SJeff Kirsher #else
154f1deab50SJoe Perches #define bnx2x_panic() \
155f1deab50SJoe Perches do { \
156adfc5217SJeff Kirsher bp->panic = 1; \
157adfc5217SJeff Kirsher BNX2X_ERR("driver assert\n"); \
158823e1d90SYuval Mintz bnx2x_panic_dump(bp, false); \
159adfc5217SJeff Kirsher } while (0)
160adfc5217SJeff Kirsher #endif
161adfc5217SJeff Kirsher
162adfc5217SJeff Kirsher #define bnx2x_mc_addr(ha) ((ha)->addr)
163adfc5217SJeff Kirsher #define bnx2x_uc_addr(ha) ((ha)->addr)
164adfc5217SJeff Kirsher
1652de67439SYuval Mintz #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff))
1662de67439SYuval Mintz #define U64_HI(x) ((u32)(((u64)(x)) >> 32))
167adfc5217SJeff Kirsher #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
168adfc5217SJeff Kirsher
169adfc5217SJeff Kirsher #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
170adfc5217SJeff Kirsher
171adfc5217SJeff Kirsher #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
172adfc5217SJeff Kirsher #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
173adfc5217SJeff Kirsher #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
174adfc5217SJeff Kirsher
1757f883c77SSinan Kaya #define REG_WR_RELAXED(bp, offset, val) \
1767f883c77SSinan Kaya writel_relaxed((u32)val, REG_ADDR(bp, offset))
1777f883c77SSinan Kaya
1787f883c77SSinan Kaya #define REG_WR16_RELAXED(bp, offset, val) \
1797f883c77SSinan Kaya writew_relaxed((u16)val, REG_ADDR(bp, offset))
1807f883c77SSinan Kaya
181adfc5217SJeff Kirsher #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
182adfc5217SJeff Kirsher #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
183adfc5217SJeff Kirsher #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
184adfc5217SJeff Kirsher
185adfc5217SJeff Kirsher #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
186adfc5217SJeff Kirsher #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
187adfc5217SJeff Kirsher
188adfc5217SJeff Kirsher #define REG_RD_DMAE(bp, offset, valp, len32) \
189adfc5217SJeff Kirsher do { \
190adfc5217SJeff Kirsher bnx2x_read_dmae(bp, offset, len32);\
191adfc5217SJeff Kirsher memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
192adfc5217SJeff Kirsher } while (0)
193adfc5217SJeff Kirsher
194adfc5217SJeff Kirsher #define REG_WR_DMAE(bp, offset, valp, len32) \
195adfc5217SJeff Kirsher do { \
196adfc5217SJeff Kirsher memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
197adfc5217SJeff Kirsher bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
198adfc5217SJeff Kirsher offset, len32); \
199adfc5217SJeff Kirsher } while (0)
200adfc5217SJeff Kirsher
201adfc5217SJeff Kirsher #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
202adfc5217SJeff Kirsher REG_WR_DMAE(bp, offset, valp, len32)
203adfc5217SJeff Kirsher
204adfc5217SJeff Kirsher #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
205adfc5217SJeff Kirsher do { \
206adfc5217SJeff Kirsher memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
207adfc5217SJeff Kirsher bnx2x_write_big_buf_wb(bp, addr, len32); \
208adfc5217SJeff Kirsher } while (0)
209adfc5217SJeff Kirsher
210adfc5217SJeff Kirsher #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
211adfc5217SJeff Kirsher offsetof(struct shmem_region, field))
212adfc5217SJeff Kirsher #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
213adfc5217SJeff Kirsher #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
214adfc5217SJeff Kirsher
215adfc5217SJeff Kirsher #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
216adfc5217SJeff Kirsher offsetof(struct shmem2_region, field))
217adfc5217SJeff Kirsher #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
218adfc5217SJeff Kirsher #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
219adfc5217SJeff Kirsher #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
220adfc5217SJeff Kirsher offsetof(struct mf_cfg, field))
221adfc5217SJeff Kirsher #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
222adfc5217SJeff Kirsher offsetof(struct mf2_cfg, field))
223adfc5217SJeff Kirsher
224adfc5217SJeff Kirsher #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
225adfc5217SJeff Kirsher #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
226adfc5217SJeff Kirsher MF_CFG_ADDR(bp, field), (val))
227adfc5217SJeff Kirsher #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
228adfc5217SJeff Kirsher
229adfc5217SJeff Kirsher #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
230adfc5217SJeff Kirsher (SHMEM2_RD((bp), size) > \
231adfc5217SJeff Kirsher offsetof(struct shmem2_region, field)))
232adfc5217SJeff Kirsher
233adfc5217SJeff Kirsher #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
234adfc5217SJeff Kirsher #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
235adfc5217SJeff Kirsher
236adfc5217SJeff Kirsher /* SP SB indices */
237adfc5217SJeff Kirsher
238adfc5217SJeff Kirsher /* General SP events - stats query, cfc delete, etc */
239adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_DEF_CONS 3
240adfc5217SJeff Kirsher
241adfc5217SJeff Kirsher /* EQ completions */
242adfc5217SJeff Kirsher #define HC_SP_INDEX_EQ_CONS 7
243adfc5217SJeff Kirsher
244adfc5217SJeff Kirsher /* FCoE L2 connection completions */
245adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
246adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
247adfc5217SJeff Kirsher /* iSCSI L2 */
248adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
249adfc5217SJeff Kirsher #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
250adfc5217SJeff Kirsher
251adfc5217SJeff Kirsher /* Special clients parameters */
252adfc5217SJeff Kirsher
253adfc5217SJeff Kirsher /* SB indices */
254adfc5217SJeff Kirsher /* FCoE L2 */
255adfc5217SJeff Kirsher #define BNX2X_FCOE_L2_RX_INDEX \
256adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\
257adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
258adfc5217SJeff Kirsher
259adfc5217SJeff Kirsher #define BNX2X_FCOE_L2_TX_INDEX \
260adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\
261adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
262adfc5217SJeff Kirsher
263adfc5217SJeff Kirsher /**
264adfc5217SJeff Kirsher * CIDs and CLIDs:
265adfc5217SJeff Kirsher * CLIDs below is a CLID for func 0, then the CLID for other
266adfc5217SJeff Kirsher * functions will be calculated by the formula:
267adfc5217SJeff Kirsher *
268adfc5217SJeff Kirsher * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
269adfc5217SJeff Kirsher *
270adfc5217SJeff Kirsher */
2711805b2f0SDavid S. Miller enum {
2721805b2f0SDavid S. Miller BNX2X_ISCSI_ETH_CL_ID_IDX,
2731805b2f0SDavid S. Miller BNX2X_FCOE_ETH_CL_ID_IDX,
2741805b2f0SDavid S. Miller BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
2751805b2f0SDavid S. Miller };
276adfc5217SJeff Kirsher
277f78afb35SMichael Chan /* use a value high enough to be above all the PFs, which has least significant
278f78afb35SMichael Chan * nibble as 8, so when cnic needs to come up with a CID for UIO to use to
279f78afb35SMichael Chan * calculate doorbell address according to old doorbell configuration scheme
280f78afb35SMichael Chan * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number
281f78afb35SMichael Chan * We must avoid coming up with cid 8 for iscsi since according to this method
282f78afb35SMichael Chan * the designated UIO cid will come out 0 and it has a special handling for that
283f78afb35SMichael Chan * case which doesn't suit us. Therefore will will cieling to closes cid which
284f78afb35SMichael Chan * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18.
285f78afb35SMichael Chan */
286f78afb35SMichael Chan
287f78afb35SMichael Chan #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \
28837ae41a9SMerav Sicron (bp)->max_cos)
289f78afb35SMichael Chan /* amount of cids traversed by UIO's DPM addition to doorbell */
290f78afb35SMichael Chan #define UIO_DPM 8
291f78afb35SMichael Chan /* roundup to DPM offset */
292f78afb35SMichael Chan #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \
293f78afb35SMichael Chan UIO_DPM))
294f78afb35SMichael Chan /* offset to nearest value which has lsb nibble matching DPM */
295f78afb35SMichael Chan #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \
296f78afb35SMichael Chan (UIO_DPM * 2))
297f78afb35SMichael Chan /* add offset to rounded-up cid to get a value which could be used with UIO */
298f78afb35SMichael Chan #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp))
299f78afb35SMichael Chan /* but wait - avoid UIO special case for cid 0 */
300f78afb35SMichael Chan #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \
301f78afb35SMichael Chan (UIO_DPM_ALIGN(bp) == UIO_DPM))
302f78afb35SMichael Chan /* Properly DPM aligned CID dajusted to cid 0 secal case */
303f78afb35SMichael Chan #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \
304f78afb35SMichael Chan (UIO_DPM_CID0_OFFSET(bp)))
305f78afb35SMichael Chan /* how many cids were wasted - need this value for cid allocation */
306f78afb35SMichael Chan #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \
307f78afb35SMichael Chan BNX2X_1st_NON_L2_ETH_CID(bp))
3081805b2f0SDavid S. Miller /* iSCSI L2 */
30937ae41a9SMerav Sicron #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
310adfc5217SJeff Kirsher /* FCoE L2 */
31137ae41a9SMerav Sicron #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
312adfc5217SJeff Kirsher
31355c11941SMerav Sicron #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
31455c11941SMerav Sicron #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
31555c11941SMerav Sicron #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
31655c11941SMerav Sicron #define FCOE_INIT(bp) ((bp)->fcoe_init)
317adfc5217SJeff Kirsher
318adfc5217SJeff Kirsher #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
319adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
320adfc5217SJeff Kirsher
321adfc5217SJeff Kirsher #define SM_RX_ID 0
322adfc5217SJeff Kirsher #define SM_TX_ID 1
323adfc5217SJeff Kirsher
324adfc5217SJeff Kirsher /* defines for multiple tx priority indices */
325adfc5217SJeff Kirsher #define FIRST_TX_ONLY_COS_INDEX 1
326adfc5217SJeff Kirsher #define FIRST_TX_COS_INDEX 0
327adfc5217SJeff Kirsher
328adfc5217SJeff Kirsher /* rules for calculating the cids of tx-only connections */
32965565884SMerav Sicron #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
33065565884SMerav Sicron #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
33165565884SMerav Sicron (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
332adfc5217SJeff Kirsher
333adfc5217SJeff Kirsher /* fp index inside class of service range */
33465565884SMerav Sicron #define FP_COS_TO_TXQ(fp, cos, bp) \
33565565884SMerav Sicron ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
336adfc5217SJeff Kirsher
33765565884SMerav Sicron /* Indexes for transmission queues array:
33865565884SMerav Sicron * txdata for RSS i CoS j is at location i + (j * num of RSS)
33965565884SMerav Sicron * txdata for FCoE (if exist) is at location max cos * num of RSS
34065565884SMerav Sicron * txdata for FWD (if exist) is one location after FCoE
34165565884SMerav Sicron * txdata for OOO (if exist) is one location after FWD
342adfc5217SJeff Kirsher */
34365565884SMerav Sicron enum {
34465565884SMerav Sicron FCOE_TXQ_IDX_OFFSET,
34565565884SMerav Sicron FWD_TXQ_IDX_OFFSET,
34665565884SMerav Sicron OOO_TXQ_IDX_OFFSET,
34765565884SMerav Sicron };
34865565884SMerav Sicron #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
34965565884SMerav Sicron #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
350adfc5217SJeff Kirsher
351adfc5217SJeff Kirsher /* fast path */
352e52fcb24SEric Dumazet /*
353e52fcb24SEric Dumazet * This driver uses new build_skb() API :
354e52fcb24SEric Dumazet * RX ring buffer contains pointer to kmalloc() data only,
355e52fcb24SEric Dumazet * skb are built only after Hardware filled the frame.
356e52fcb24SEric Dumazet */
357adfc5217SJeff Kirsher struct sw_rx_bd {
358e52fcb24SEric Dumazet u8 *data;
359adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping);
360adfc5217SJeff Kirsher };
361adfc5217SJeff Kirsher
362adfc5217SJeff Kirsher struct sw_tx_bd {
363adfc5217SJeff Kirsher struct sk_buff *skb;
364adfc5217SJeff Kirsher u16 first_bd;
365adfc5217SJeff Kirsher u8 flags;
366adfc5217SJeff Kirsher /* Set on the first BD descriptor when there is a split BD */
367adfc5217SJeff Kirsher #define BNX2X_TSO_SPLIT_BD (1<<0)
368fe26566dSDmitry Kravkov #define BNX2X_HAS_SECOND_PBD (1<<1)
369adfc5217SJeff Kirsher };
370adfc5217SJeff Kirsher
371adfc5217SJeff Kirsher struct sw_rx_page {
372adfc5217SJeff Kirsher struct page *page;
373adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping);
3744cace675SGabriel Krisman Bertazi unsigned int offset;
375adfc5217SJeff Kirsher };
376adfc5217SJeff Kirsher
377adfc5217SJeff Kirsher union db_prod {
378adfc5217SJeff Kirsher struct doorbell_set_prod data;
379adfc5217SJeff Kirsher u32 raw;
380adfc5217SJeff Kirsher };
381adfc5217SJeff Kirsher
3828decf868SDavid S. Miller /* dropless fc FW/HW related params */
3838decf868SDavid S. Miller #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
3848decf868SDavid S. Miller #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
3858decf868SDavid S. Miller ETH_MAX_AGGREGATION_QUEUES_E1 :\
3868decf868SDavid S. Miller ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
3878decf868SDavid S. Miller #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
3888decf868SDavid S. Miller #define FW_PREFETCH_CNT 16
3898decf868SDavid S. Miller #define DROPLESS_FC_HEADROOM 100
390adfc5217SJeff Kirsher
391adfc5217SJeff Kirsher /* MC hsi */
392adfc5217SJeff Kirsher #define BCM_PAGE_SHIFT 12
393adfc5217SJeff Kirsher #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
394adfc5217SJeff Kirsher #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
395adfc5217SJeff Kirsher #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
396adfc5217SJeff Kirsher
397adfc5217SJeff Kirsher #define PAGES_PER_SGE_SHIFT 0
398adfc5217SJeff Kirsher #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
3994cace675SGabriel Krisman Bertazi #define SGE_PAGE_SHIFT 12
4004cace675SGabriel Krisman Bertazi #define SGE_PAGE_SIZE (1 << SGE_PAGE_SHIFT)
4014cace675SGabriel Krisman Bertazi #define SGE_PAGE_MASK (~(SGE_PAGE_SIZE - 1))
4024cace675SGabriel Krisman Bertazi #define SGE_PAGE_ALIGN(addr) (((addr) + SGE_PAGE_SIZE - 1) & SGE_PAGE_MASK)
4038d9ac297SAriel Elior #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
4048d9ac297SAriel Elior #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
4058d9ac297SAriel Elior SGE_PAGES), 0xffff)
406adfc5217SJeff Kirsher
407adfc5217SJeff Kirsher /* SGE ring related macros */
408adfc5217SJeff Kirsher #define NUM_RX_SGE_PAGES 2
409adfc5217SJeff Kirsher #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
4108decf868SDavid S. Miller #define NEXT_PAGE_SGE_DESC_CNT 2
4118decf868SDavid S. Miller #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
412adfc5217SJeff Kirsher /* RX_SGE_CNT is promised to be a power of 2 */
413adfc5217SJeff Kirsher #define RX_SGE_MASK (RX_SGE_CNT - 1)
414adfc5217SJeff Kirsher #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
415adfc5217SJeff Kirsher #define MAX_RX_SGE (NUM_RX_SGE - 1)
416adfc5217SJeff Kirsher #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
4178decf868SDavid S. Miller (MAX_RX_SGE_CNT - 1)) ? \
4188decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
4198decf868SDavid S. Miller (x) + 1)
420adfc5217SJeff Kirsher #define RX_SGE(x) ((x) & MAX_RX_SGE)
421adfc5217SJeff Kirsher
4228decf868SDavid S. Miller /*
4238decf868SDavid S. Miller * Number of required SGEs is the sum of two:
4248decf868SDavid S. Miller * 1. Number of possible opened aggregations (next packet for
42516a5fd92SYuval Mintz * these aggregations will probably consume SGE immediately)
4268decf868SDavid S. Miller * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
4278decf868SDavid S. Miller * after placement on BD for new TPA aggregation)
4288decf868SDavid S. Miller *
4298decf868SDavid S. Miller * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
4308decf868SDavid S. Miller */
4318decf868SDavid S. Miller #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
4328decf868SDavid S. Miller (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
4338decf868SDavid S. Miller #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
4348decf868SDavid S. Miller MAX_RX_SGE_CNT)
4358decf868SDavid S. Miller #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
4368decf868SDavid S. Miller NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
4378decf868SDavid S. Miller #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
4388decf868SDavid S. Miller
439adfc5217SJeff Kirsher /* Manipulate a bit vector defined as an array of u64 */
440adfc5217SJeff Kirsher
441adfc5217SJeff Kirsher /* Number of bits in one sge_mask array element */
442adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_SZ 64
443adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_SHIFT 6
444adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
445adfc5217SJeff Kirsher
446adfc5217SJeff Kirsher #define __BIT_VEC64_SET_BIT(el, bit) \
447adfc5217SJeff Kirsher do { \
448adfc5217SJeff Kirsher el = ((el) | ((u64)0x1 << (bit))); \
449adfc5217SJeff Kirsher } while (0)
450adfc5217SJeff Kirsher
451adfc5217SJeff Kirsher #define __BIT_VEC64_CLEAR_BIT(el, bit) \
452adfc5217SJeff Kirsher do { \
453adfc5217SJeff Kirsher el = ((el) & (~((u64)0x1 << (bit)))); \
454adfc5217SJeff Kirsher } while (0)
455adfc5217SJeff Kirsher
456adfc5217SJeff Kirsher #define BIT_VEC64_SET_BIT(vec64, idx) \
457adfc5217SJeff Kirsher __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
458adfc5217SJeff Kirsher (idx) & BIT_VEC64_ELEM_MASK)
459adfc5217SJeff Kirsher
460adfc5217SJeff Kirsher #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
461adfc5217SJeff Kirsher __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
462adfc5217SJeff Kirsher (idx) & BIT_VEC64_ELEM_MASK)
463adfc5217SJeff Kirsher
464adfc5217SJeff Kirsher #define BIT_VEC64_TEST_BIT(vec64, idx) \
465adfc5217SJeff Kirsher (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
466adfc5217SJeff Kirsher ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
467adfc5217SJeff Kirsher
468adfc5217SJeff Kirsher /* Creates a bitmask of all ones in less significant bits.
469adfc5217SJeff Kirsher idx - index of the most significant bit in the created mask */
470adfc5217SJeff Kirsher #define BIT_VEC64_ONES_MASK(idx) \
471adfc5217SJeff Kirsher (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
472adfc5217SJeff Kirsher #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
473adfc5217SJeff Kirsher
474adfc5217SJeff Kirsher /*******************************************************/
475adfc5217SJeff Kirsher
476adfc5217SJeff Kirsher /* Number of u64 elements in SGE mask array */
477b3637827SDmitry Kravkov #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
478adfc5217SJeff Kirsher #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
479adfc5217SJeff Kirsher #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
480adfc5217SJeff Kirsher
481adfc5217SJeff Kirsher union host_hc_status_block {
482adfc5217SJeff Kirsher /* pointer to fp status block e1x */
483adfc5217SJeff Kirsher struct host_hc_status_block_e1x *e1x_sb;
484adfc5217SJeff Kirsher /* pointer to fp status block e2 */
485adfc5217SJeff Kirsher struct host_hc_status_block_e2 *e2_sb;
486adfc5217SJeff Kirsher };
487adfc5217SJeff Kirsher
488adfc5217SJeff Kirsher struct bnx2x_agg_info {
489adfc5217SJeff Kirsher /*
490e52fcb24SEric Dumazet * First aggregation buffer is a data buffer, the following - are pages.
491e52fcb24SEric Dumazet * We will preallocate the data buffer for each aggregation when
492adfc5217SJeff Kirsher * we open the interface and will replace the BD at the consumer
493adfc5217SJeff Kirsher * with this one when we receive the TPA_START CQE in order to
494adfc5217SJeff Kirsher * keep the Rx BD ring consistent.
495adfc5217SJeff Kirsher */
496adfc5217SJeff Kirsher struct sw_rx_bd first_buf;
497adfc5217SJeff Kirsher u8 tpa_state;
498adfc5217SJeff Kirsher #define BNX2X_TPA_START 1
499adfc5217SJeff Kirsher #define BNX2X_TPA_STOP 2
500adfc5217SJeff Kirsher #define BNX2X_TPA_ERROR 3
501adfc5217SJeff Kirsher u8 placement_offset;
502adfc5217SJeff Kirsher u16 parsing_flags;
503adfc5217SJeff Kirsher u16 vlan_tag;
504adfc5217SJeff Kirsher u16 len_on_bd;
505e52fcb24SEric Dumazet u32 rxhash;
5065495ab75STom Herbert enum pkt_hash_types rxhash_type;
507621b4d66SDmitry Kravkov u16 gro_size;
508621b4d66SDmitry Kravkov u16 full_page;
509adfc5217SJeff Kirsher };
510adfc5217SJeff Kirsher
511adfc5217SJeff Kirsher #define Q_STATS_OFFSET32(stat_name) \
512adfc5217SJeff Kirsher (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
513adfc5217SJeff Kirsher
514adfc5217SJeff Kirsher struct bnx2x_fp_txdata {
515adfc5217SJeff Kirsher
516adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf_ring;
517adfc5217SJeff Kirsher
518adfc5217SJeff Kirsher union eth_tx_bd_types *tx_desc_ring;
519adfc5217SJeff Kirsher dma_addr_t tx_desc_mapping;
520adfc5217SJeff Kirsher
521adfc5217SJeff Kirsher u32 cid;
522adfc5217SJeff Kirsher
523adfc5217SJeff Kirsher union db_prod tx_db;
524adfc5217SJeff Kirsher
525adfc5217SJeff Kirsher u16 tx_pkt_prod;
526adfc5217SJeff Kirsher u16 tx_pkt_cons;
527adfc5217SJeff Kirsher u16 tx_bd_prod;
528adfc5217SJeff Kirsher u16 tx_bd_cons;
529adfc5217SJeff Kirsher
530adfc5217SJeff Kirsher unsigned long tx_pkt;
531adfc5217SJeff Kirsher
532adfc5217SJeff Kirsher __le16 *tx_cons_sb;
533adfc5217SJeff Kirsher
534adfc5217SJeff Kirsher int txq_index;
53565565884SMerav Sicron struct bnx2x_fastpath *parent_fp;
53665565884SMerav Sicron int tx_ring_size;
537adfc5217SJeff Kirsher };
538adfc5217SJeff Kirsher
539621b4d66SDmitry Kravkov enum bnx2x_tpa_mode_t {
5407e6b4d44SMichal Schmidt TPA_MODE_DISABLED,
541621b4d66SDmitry Kravkov TPA_MODE_LRO,
542621b4d66SDmitry Kravkov TPA_MODE_GRO
543621b4d66SDmitry Kravkov };
544621b4d66SDmitry Kravkov
5454cace675SGabriel Krisman Bertazi struct bnx2x_alloc_pool {
5464cace675SGabriel Krisman Bertazi struct page *page;
5474cace675SGabriel Krisman Bertazi unsigned int offset;
5484cace675SGabriel Krisman Bertazi };
5494cace675SGabriel Krisman Bertazi
550adfc5217SJeff Kirsher struct bnx2x_fastpath {
551adfc5217SJeff Kirsher struct bnx2x *bp; /* parent */
552adfc5217SJeff Kirsher
553adfc5217SJeff Kirsher struct napi_struct napi;
5548f20aa57SDmitry Kravkov
555adfc5217SJeff Kirsher union host_hc_status_block status_blk;
55616a5fd92SYuval Mintz /* chip independent shortcuts into sb structure */
557adfc5217SJeff Kirsher __le16 *sb_index_values;
558adfc5217SJeff Kirsher __le16 *sb_running_index;
55916a5fd92SYuval Mintz /* chip independent shortcut into rx_prods_offset memory */
560adfc5217SJeff Kirsher u32 ustorm_rx_prods_offset;
561adfc5217SJeff Kirsher
562adfc5217SJeff Kirsher u32 rx_buf_size;
563d46d132cSEric Dumazet u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
564adfc5217SJeff Kirsher dma_addr_t status_blk_mapping;
565adfc5217SJeff Kirsher
566621b4d66SDmitry Kravkov enum bnx2x_tpa_mode_t mode;
567621b4d66SDmitry Kravkov
568adfc5217SJeff Kirsher u8 max_cos; /* actual number of active tx coses */
56965565884SMerav Sicron struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
570adfc5217SJeff Kirsher
571adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
572adfc5217SJeff Kirsher struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
573adfc5217SJeff Kirsher
574adfc5217SJeff Kirsher struct eth_rx_bd *rx_desc_ring;
575adfc5217SJeff Kirsher dma_addr_t rx_desc_mapping;
576adfc5217SJeff Kirsher
577adfc5217SJeff Kirsher union eth_rx_cqe *rx_comp_ring;
578adfc5217SJeff Kirsher dma_addr_t rx_comp_mapping;
579adfc5217SJeff Kirsher
580adfc5217SJeff Kirsher /* SGE ring */
581adfc5217SJeff Kirsher struct eth_rx_sge *rx_sge_ring;
582adfc5217SJeff Kirsher dma_addr_t rx_sge_mapping;
583adfc5217SJeff Kirsher
584adfc5217SJeff Kirsher u64 sge_mask[RX_SGE_MASK_LEN];
585adfc5217SJeff Kirsher
586adfc5217SJeff Kirsher u32 cid;
587adfc5217SJeff Kirsher
588adfc5217SJeff Kirsher __le16 fp_hc_idx;
589adfc5217SJeff Kirsher
590adfc5217SJeff Kirsher u8 index; /* number in fp array */
591f233cafeSDmitry Kravkov u8 rx_queue; /* index for skb_record */
592adfc5217SJeff Kirsher u8 cl_id; /* eth client id */
593adfc5217SJeff Kirsher u8 cl_qzone_id;
594adfc5217SJeff Kirsher u8 fw_sb_id; /* status block number in FW */
595adfc5217SJeff Kirsher u8 igu_sb_id; /* status block number in HW */
596adfc5217SJeff Kirsher
597adfc5217SJeff Kirsher u16 rx_bd_prod;
598adfc5217SJeff Kirsher u16 rx_bd_cons;
599adfc5217SJeff Kirsher u16 rx_comp_prod;
600adfc5217SJeff Kirsher u16 rx_comp_cons;
601adfc5217SJeff Kirsher u16 rx_sge_prod;
602adfc5217SJeff Kirsher /* The last maximal completed SGE */
603adfc5217SJeff Kirsher u16 last_max_sge;
604adfc5217SJeff Kirsher __le16 *rx_cons_sb;
605adfc5217SJeff Kirsher
606adfc5217SJeff Kirsher /* TPA related */
60715192a8cSBarak Witkowski struct bnx2x_agg_info *tpa_info;
608adfc5217SJeff Kirsher #ifdef BNX2X_STOP_ON_ERROR
609adfc5217SJeff Kirsher u64 tpa_queue_used;
610adfc5217SJeff Kirsher #endif
611adfc5217SJeff Kirsher /* The size is calculated using the following:
612adfc5217SJeff Kirsher sizeof name field from netdev structure +
613adfc5217SJeff Kirsher 4 ('-Xx-' string) +
614adfc5217SJeff Kirsher 4 (for the digits and to make it DWORD aligned) */
615adfc5217SJeff Kirsher #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
616adfc5217SJeff Kirsher char name[FP_NAME_SIZE];
6174cace675SGabriel Krisman Bertazi
6184cace675SGabriel Krisman Bertazi struct bnx2x_alloc_pool page_pool;
619adfc5217SJeff Kirsher };
620adfc5217SJeff Kirsher
62115192a8cSBarak Witkowski #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
62215192a8cSBarak Witkowski #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
62315192a8cSBarak Witkowski #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
62415192a8cSBarak Witkowski #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
625adfc5217SJeff Kirsher
626adfc5217SJeff Kirsher /* Use 2500 as a mini-jumbo MTU for FCoE */
627adfc5217SJeff Kirsher #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
628adfc5217SJeff Kirsher
62965565884SMerav Sicron #define FCOE_IDX_OFFSET 0
63065565884SMerav Sicron
63165565884SMerav Sicron #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
63265565884SMerav Sicron FCOE_IDX_OFFSET)
63365565884SMerav Sicron #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
634adfc5217SJeff Kirsher #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
63515192a8cSBarak Witkowski #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
63615192a8cSBarak Witkowski #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
637adfc5217SJeff Kirsher #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
63865565884SMerav Sicron txdata_ptr[FIRST_TX_COS_INDEX] \
63965565884SMerav Sicron ->var)
640adfc5217SJeff Kirsher
64155c11941SMerav Sicron #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
64255c11941SMerav Sicron #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
64365565884SMerav Sicron #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
644adfc5217SJeff Kirsher
645adfc5217SJeff Kirsher /* MC hsi */
646adfc5217SJeff Kirsher #define MAX_FETCH_BD 13 /* HW max BDs per packet */
647adfc5217SJeff Kirsher #define RX_COPY_THRESH 92
648adfc5217SJeff Kirsher
649adfc5217SJeff Kirsher #define NUM_TX_RINGS 16
650adfc5217SJeff Kirsher #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
6518decf868SDavid S. Miller #define NEXT_PAGE_TX_DESC_CNT 1
6528decf868SDavid S. Miller #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
653adfc5217SJeff Kirsher #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
654adfc5217SJeff Kirsher #define MAX_TX_BD (NUM_TX_BD - 1)
655adfc5217SJeff Kirsher #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
656adfc5217SJeff Kirsher #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
6578decf868SDavid S. Miller (MAX_TX_DESC_CNT - 1)) ? \
6588decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
6598decf868SDavid S. Miller (x) + 1)
660adfc5217SJeff Kirsher #define TX_BD(x) ((x) & MAX_TX_BD)
661adfc5217SJeff Kirsher #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
662adfc5217SJeff Kirsher
6637df2dc6bSDmitry Kravkov /* number of NEXT_PAGE descriptors may be required during placement */
6647df2dc6bSDmitry Kravkov #define NEXT_CNT_PER_TX_PKT(bds) \
6657df2dc6bSDmitry Kravkov (((bds) + MAX_TX_DESC_CNT - 1) / \
6667df2dc6bSDmitry Kravkov MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
6677df2dc6bSDmitry Kravkov /* max BDs per tx packet w/o next_pages:
6687df2dc6bSDmitry Kravkov * START_BD - describes packed
6697df2dc6bSDmitry Kravkov * START_BD(splitted) - includes unpaged data segment for GSO
6707df2dc6bSDmitry Kravkov * PARSING_BD - for TSO and CSUM data
671a848ade4SDmitry Kravkov * PARSING_BD2 - for encapsulation data
67216a5fd92SYuval Mintz * Frag BDs - describes pages for frags
6737df2dc6bSDmitry Kravkov */
674a848ade4SDmitry Kravkov #define BDS_PER_TX_PKT 4
6757df2dc6bSDmitry Kravkov #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
6767df2dc6bSDmitry Kravkov /* max BDs per tx packet including next pages */
6777df2dc6bSDmitry Kravkov #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
6787df2dc6bSDmitry Kravkov NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
6797df2dc6bSDmitry Kravkov
680adfc5217SJeff Kirsher /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
681adfc5217SJeff Kirsher #define NUM_RX_RINGS 8
682adfc5217SJeff Kirsher #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
6838decf868SDavid S. Miller #define NEXT_PAGE_RX_DESC_CNT 2
6848decf868SDavid S. Miller #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
685adfc5217SJeff Kirsher #define RX_DESC_MASK (RX_DESC_CNT - 1)
686adfc5217SJeff Kirsher #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
687adfc5217SJeff Kirsher #define MAX_RX_BD (NUM_RX_BD - 1)
688adfc5217SJeff Kirsher #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
6898decf868SDavid S. Miller
6908decf868SDavid S. Miller /* dropless fc calculations for BDs
6918decf868SDavid S. Miller *
6928decf868SDavid S. Miller * Number of BDs should as number of buffers in BRB:
6938decf868SDavid S. Miller * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
6948decf868SDavid S. Miller * "next" elements on each page
6958decf868SDavid S. Miller */
6968decf868SDavid S. Miller #define NUM_BD_REQ BRB_SIZE(bp)
6978decf868SDavid S. Miller #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
6988decf868SDavid S. Miller MAX_RX_DESC_CNT)
6998decf868SDavid S. Miller #define BD_TH_LO(bp) (NUM_BD_REQ + \
7008decf868SDavid S. Miller NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
7018decf868SDavid S. Miller FW_DROP_LEVEL(bp))
7028decf868SDavid S. Miller #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
7038decf868SDavid S. Miller
7048decf868SDavid S. Miller #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
705adfc5217SJeff Kirsher
706adfc5217SJeff Kirsher #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
707adfc5217SJeff Kirsher ETH_MIN_RX_CQES_WITH_TPA_E1 : \
708adfc5217SJeff Kirsher ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
709adfc5217SJeff Kirsher #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
710adfc5217SJeff Kirsher #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
711adfc5217SJeff Kirsher #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
712adfc5217SJeff Kirsher MIN_RX_AVAIL))
713adfc5217SJeff Kirsher
714adfc5217SJeff Kirsher #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
7158decf868SDavid S. Miller (MAX_RX_DESC_CNT - 1)) ? \
7168decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
7178decf868SDavid S. Miller (x) + 1)
718adfc5217SJeff Kirsher #define RX_BD(x) ((x) & MAX_RX_BD)
719adfc5217SJeff Kirsher
720adfc5217SJeff Kirsher /*
721adfc5217SJeff Kirsher * As long as CQE is X times bigger than BD entry we have to allocate X times
722adfc5217SJeff Kirsher * more pages for CQ ring in order to keep it balanced with BD ring
723adfc5217SJeff Kirsher */
724adfc5217SJeff Kirsher #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
725adfc5217SJeff Kirsher #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
726adfc5217SJeff Kirsher #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
7278decf868SDavid S. Miller #define NEXT_PAGE_RCQ_DESC_CNT 1
7288decf868SDavid S. Miller #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
729adfc5217SJeff Kirsher #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
730adfc5217SJeff Kirsher #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
731adfc5217SJeff Kirsher #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
732adfc5217SJeff Kirsher #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
7338decf868SDavid S. Miller (MAX_RCQ_DESC_CNT - 1)) ? \
7348decf868SDavid S. Miller (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
7358decf868SDavid S. Miller (x) + 1)
736adfc5217SJeff Kirsher #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
737adfc5217SJeff Kirsher
7388decf868SDavid S. Miller /* dropless fc calculations for RCQs
7398decf868SDavid S. Miller *
7408decf868SDavid S. Miller * Number of RCQs should be as number of buffers in BRB:
7418decf868SDavid S. Miller * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
7428decf868SDavid S. Miller * "next" elements on each page
7438decf868SDavid S. Miller */
7448decf868SDavid S. Miller #define NUM_RCQ_REQ BRB_SIZE(bp)
7458decf868SDavid S. Miller #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
7468decf868SDavid S. Miller MAX_RCQ_DESC_CNT)
7478decf868SDavid S. Miller #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
7488decf868SDavid S. Miller NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
7498decf868SDavid S. Miller FW_DROP_LEVEL(bp))
7508decf868SDavid S. Miller #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
7518decf868SDavid S. Miller
752adfc5217SJeff Kirsher /* This is needed for determining of last_max */
753adfc5217SJeff Kirsher #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
754adfc5217SJeff Kirsher #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
755adfc5217SJeff Kirsher
756adfc5217SJeff Kirsher #define BNX2X_SWCID_SHIFT 17
757adfc5217SJeff Kirsher #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
758adfc5217SJeff Kirsher
759adfc5217SJeff Kirsher /* used on a CID received from the HW */
760adfc5217SJeff Kirsher #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
761adfc5217SJeff Kirsher #define CQE_CMD(x) (le32_to_cpu(x) >> \
762adfc5217SJeff Kirsher COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
763adfc5217SJeff Kirsher
764adfc5217SJeff Kirsher #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
765adfc5217SJeff Kirsher le32_to_cpu((bd)->addr_lo))
766adfc5217SJeff Kirsher #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
767adfc5217SJeff Kirsher
768adfc5217SJeff Kirsher #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
769b9871bcfSAriel Elior #define BNX2X_DB_SHIFT 3 /* 8 bytes*/
770adfc5217SJeff Kirsher #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
771adfc5217SJeff Kirsher #error "Min DB doorbell stride is 8"
772adfc5217SJeff Kirsher #endif
7737f883c77SSinan Kaya #define DOORBELL_RELAXED(bp, cid, val) \
7747f883c77SSinan Kaya writel_relaxed((u32)(val), (bp)->doorbells + ((bp)->db_size * (cid)))
775adfc5217SJeff Kirsher
776adfc5217SJeff Kirsher /* TX CSUM helpers */
777adfc5217SJeff Kirsher #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
778adfc5217SJeff Kirsher skb->csum_offset)
779adfc5217SJeff Kirsher #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
780adfc5217SJeff Kirsher skb->csum_offset))
781adfc5217SJeff Kirsher
78291226790SDmitry Kravkov #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
783adfc5217SJeff Kirsher
784adfc5217SJeff Kirsher #define XMIT_PLAIN 0
785a848ade4SDmitry Kravkov #define XMIT_CSUM_V4 (1 << 0)
786a848ade4SDmitry Kravkov #define XMIT_CSUM_V6 (1 << 1)
787a848ade4SDmitry Kravkov #define XMIT_CSUM_TCP (1 << 2)
788a848ade4SDmitry Kravkov #define XMIT_GSO_V4 (1 << 3)
789a848ade4SDmitry Kravkov #define XMIT_GSO_V6 (1 << 4)
790a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC_V4 (1 << 5)
791a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC_V6 (1 << 6)
792a848ade4SDmitry Kravkov #define XMIT_GSO_ENC_V4 (1 << 7)
793a848ade4SDmitry Kravkov #define XMIT_GSO_ENC_V6 (1 << 8)
794adfc5217SJeff Kirsher
795a848ade4SDmitry Kravkov #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
796a848ade4SDmitry Kravkov #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
797adfc5217SJeff Kirsher
798a848ade4SDmitry Kravkov #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
799a848ade4SDmitry Kravkov #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
800adfc5217SJeff Kirsher
801adfc5217SJeff Kirsher /* stuff added to make the code fit 80Col */
802adfc5217SJeff Kirsher #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
803adfc5217SJeff Kirsher #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
804adfc5217SJeff Kirsher #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
805adfc5217SJeff Kirsher #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
806adfc5217SJeff Kirsher #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
807adfc5217SJeff Kirsher
808adfc5217SJeff Kirsher #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
809adfc5217SJeff Kirsher
810adfc5217SJeff Kirsher #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
811adfc5217SJeff Kirsher (((le16_to_cpu(flags) & \
812adfc5217SJeff Kirsher PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
813adfc5217SJeff Kirsher PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
814adfc5217SJeff Kirsher == PRS_FLAG_OVERETH_IPV4)
815adfc5217SJeff Kirsher #define BNX2X_RX_SUM_FIX(cqe) \
816adfc5217SJeff Kirsher BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
817adfc5217SJeff Kirsher
818adfc5217SJeff Kirsher #define FP_USB_FUNC_OFF \
819adfc5217SJeff Kirsher offsetof(struct cstorm_status_block_u, func)
820adfc5217SJeff Kirsher #define FP_CSB_FUNC_OFF \
821adfc5217SJeff Kirsher offsetof(struct cstorm_status_block_c, func)
822adfc5217SJeff Kirsher
8238decf868SDavid S. Miller #define HC_INDEX_ETH_RX_CQ_CONS 1
824adfc5217SJeff Kirsher
8258decf868SDavid S. Miller #define HC_INDEX_OOO_TX_CQ_CONS 4
8268decf868SDavid S. Miller
8278decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
8288decf868SDavid S. Miller
8298decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
8308decf868SDavid S. Miller
8318decf868SDavid S. Miller #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
832adfc5217SJeff Kirsher
833adfc5217SJeff Kirsher #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
834adfc5217SJeff Kirsher
835adfc5217SJeff Kirsher #define BNX2X_RX_SB_INDEX \
836adfc5217SJeff Kirsher (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
837adfc5217SJeff Kirsher
838adfc5217SJeff Kirsher #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
839adfc5217SJeff Kirsher
840adfc5217SJeff Kirsher #define BNX2X_TX_SB_INDEX_COS0 \
841adfc5217SJeff Kirsher (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
842adfc5217SJeff Kirsher
843adfc5217SJeff Kirsher /* end of fast path */
844adfc5217SJeff Kirsher
845adfc5217SJeff Kirsher /* common */
846adfc5217SJeff Kirsher
847adfc5217SJeff Kirsher struct bnx2x_common {
848adfc5217SJeff Kirsher
849adfc5217SJeff Kirsher u32 chip_id;
850adfc5217SJeff Kirsher /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
851adfc5217SJeff Kirsher #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
852adfc5217SJeff Kirsher
853adfc5217SJeff Kirsher #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
854adfc5217SJeff Kirsher #define CHIP_NUM_57710 0x164e
855adfc5217SJeff Kirsher #define CHIP_NUM_57711 0x164f
856adfc5217SJeff Kirsher #define CHIP_NUM_57711E 0x1650
857adfc5217SJeff Kirsher #define CHIP_NUM_57712 0x1662
858adfc5217SJeff Kirsher #define CHIP_NUM_57712_MF 0x1663
8598395be5eSAriel Elior #define CHIP_NUM_57712_VF 0x166f
860adfc5217SJeff Kirsher #define CHIP_NUM_57713 0x1651
861adfc5217SJeff Kirsher #define CHIP_NUM_57713E 0x1652
862adfc5217SJeff Kirsher #define CHIP_NUM_57800 0x168a
863adfc5217SJeff Kirsher #define CHIP_NUM_57800_MF 0x16a5
8648395be5eSAriel Elior #define CHIP_NUM_57800_VF 0x16a9
865adfc5217SJeff Kirsher #define CHIP_NUM_57810 0x168e
866adfc5217SJeff Kirsher #define CHIP_NUM_57810_MF 0x16ae
8678395be5eSAriel Elior #define CHIP_NUM_57810_VF 0x16af
8687e8e02dfSBarak Witkowski #define CHIP_NUM_57811 0x163d
8697e8e02dfSBarak Witkowski #define CHIP_NUM_57811_MF 0x163e
8708395be5eSAriel Elior #define CHIP_NUM_57811_VF 0x163f
871c3def943SYuval Mintz #define CHIP_NUM_57840_OBSOLETE 0x168d
872c3def943SYuval Mintz #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
873c3def943SYuval Mintz #define CHIP_NUM_57840_4_10 0x16a1
874c3def943SYuval Mintz #define CHIP_NUM_57840_2_20 0x16a2
875c3def943SYuval Mintz #define CHIP_NUM_57840_MF 0x16a4
8768395be5eSAriel Elior #define CHIP_NUM_57840_VF 0x16ad
877adfc5217SJeff Kirsher #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
878adfc5217SJeff Kirsher #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
879adfc5217SJeff Kirsher #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
880adfc5217SJeff Kirsher #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
8818395be5eSAriel Elior #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
882adfc5217SJeff Kirsher #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
883adfc5217SJeff Kirsher #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
884adfc5217SJeff Kirsher #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
8858395be5eSAriel Elior #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
886adfc5217SJeff Kirsher #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
887adfc5217SJeff Kirsher #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
8888395be5eSAriel Elior #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
8897e8e02dfSBarak Witkowski #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
8907e8e02dfSBarak Witkowski #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
8918395be5eSAriel Elior #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
892c3def943SYuval Mintz #define CHIP_IS_57840(bp) \
893c3def943SYuval Mintz ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
894c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
895c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
896c3def943SYuval Mintz #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
897c3def943SYuval Mintz (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
8988395be5eSAriel Elior #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
899adfc5217SJeff Kirsher #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
900adfc5217SJeff Kirsher CHIP_IS_57711E(bp))
901edb944d2SDmitry Kravkov #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \
902edb944d2SDmitry Kravkov CHIP_IS_57811_MF(bp) || \
903edb944d2SDmitry Kravkov CHIP_IS_57811_VF(bp))
904adfc5217SJeff Kirsher #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
9056ab20355SYuval Mintz CHIP_IS_57712_MF(bp) || \
9066ab20355SYuval Mintz CHIP_IS_57712_VF(bp))
907adfc5217SJeff Kirsher #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
908adfc5217SJeff Kirsher CHIP_IS_57800_MF(bp) || \
9096ab20355SYuval Mintz CHIP_IS_57800_VF(bp) || \
910adfc5217SJeff Kirsher CHIP_IS_57810(bp) || \
911adfc5217SJeff Kirsher CHIP_IS_57810_MF(bp) || \
9128395be5eSAriel Elior CHIP_IS_57810_VF(bp) || \
913edb944d2SDmitry Kravkov CHIP_IS_57811xx(bp) || \
914adfc5217SJeff Kirsher CHIP_IS_57840(bp) || \
9158395be5eSAriel Elior CHIP_IS_57840_MF(bp) || \
9168395be5eSAriel Elior CHIP_IS_57840_VF(bp))
917adfc5217SJeff Kirsher #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
918adfc5217SJeff Kirsher #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
919adfc5217SJeff Kirsher #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
920adfc5217SJeff Kirsher
921adfc5217SJeff Kirsher #define CHIP_REV_SHIFT 12
922adfc5217SJeff Kirsher #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
923adfc5217SJeff Kirsher #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
924adfc5217SJeff Kirsher #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
925adfc5217SJeff Kirsher #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
926adfc5217SJeff Kirsher /* assume maximum 5 revisions */
927adfc5217SJeff Kirsher #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
928adfc5217SJeff Kirsher /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
929adfc5217SJeff Kirsher #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
930adfc5217SJeff Kirsher !(CHIP_REV_VAL(bp) & 0x00001000))
931adfc5217SJeff Kirsher /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
932adfc5217SJeff Kirsher #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
933adfc5217SJeff Kirsher (CHIP_REV_VAL(bp) & 0x00001000))
934adfc5217SJeff Kirsher
935adfc5217SJeff Kirsher #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
936adfc5217SJeff Kirsher ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
937adfc5217SJeff Kirsher
938adfc5217SJeff Kirsher #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
939adfc5217SJeff Kirsher #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
940adfc5217SJeff Kirsher #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
941adfc5217SJeff Kirsher (CHIP_REV_SHIFT + 1)) \
942adfc5217SJeff Kirsher << CHIP_REV_SHIFT)
943adfc5217SJeff Kirsher #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
944adfc5217SJeff Kirsher CHIP_REV_SIM(bp) :\
945adfc5217SJeff Kirsher CHIP_REV_VAL(bp))
946adfc5217SJeff Kirsher #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
947adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Bx))
948adfc5217SJeff Kirsher #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
949adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Ax))
95055c11941SMerav Sicron /* This define is used in two main places:
95116a5fd92SYuval Mintz * 1. In the early stages of nic_load, to know if to configure Parser / Searcher
95255c11941SMerav Sicron * to nic-only mode or to offload mode. Offload mode is configured if either the
95355c11941SMerav Sicron * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
95455c11941SMerav Sicron * registered for this port (which means that the user wants storage services).
95555c11941SMerav Sicron * 2. During cnic-related load, to know if offload mode is already configured in
95616a5fd92SYuval Mintz * the HW or needs to be configured.
95755c11941SMerav Sicron * Since the transition from nic-mode to offload-mode in HW causes traffic
95816a5fd92SYuval Mintz * corruption, nic-mode is configured only in ports on which storage services
95955c11941SMerav Sicron * where never requested.
96055c11941SMerav Sicron */
96155c11941SMerav Sicron #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
962adfc5217SJeff Kirsher
963adfc5217SJeff Kirsher int flash_size;
964adfc5217SJeff Kirsher #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
965adfc5217SJeff Kirsher #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
966adfc5217SJeff Kirsher #define BNX2X_NVRAM_PAGE_SIZE 256
967adfc5217SJeff Kirsher
968adfc5217SJeff Kirsher u32 shmem_base;
969adfc5217SJeff Kirsher u32 shmem2_base;
970adfc5217SJeff Kirsher u32 mf_cfg_base;
971adfc5217SJeff Kirsher u32 mf2_cfg_base;
972adfc5217SJeff Kirsher
973adfc5217SJeff Kirsher u32 hw_config;
974adfc5217SJeff Kirsher
975adfc5217SJeff Kirsher u32 bc_ver;
976adfc5217SJeff Kirsher
977adfc5217SJeff Kirsher u8 int_block;
978adfc5217SJeff Kirsher #define INT_BLOCK_HC 0
979adfc5217SJeff Kirsher #define INT_BLOCK_IGU 1
980adfc5217SJeff Kirsher #define INT_BLOCK_MODE_NORMAL 0
981adfc5217SJeff Kirsher #define INT_BLOCK_MODE_BW_COMP 2
982adfc5217SJeff Kirsher #define CHIP_INT_MODE_IS_NBC(bp) \
983adfc5217SJeff Kirsher (!CHIP_IS_E1x(bp) && \
984adfc5217SJeff Kirsher !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
985adfc5217SJeff Kirsher #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
986adfc5217SJeff Kirsher
987adfc5217SJeff Kirsher u8 chip_port_mode;
988adfc5217SJeff Kirsher #define CHIP_4_PORT_MODE 0x0
989adfc5217SJeff Kirsher #define CHIP_2_PORT_MODE 0x1
990adfc5217SJeff Kirsher #define CHIP_PORT_MODE_NONE 0x2
991adfc5217SJeff Kirsher #define CHIP_MODE(bp) (bp->common.chip_port_mode)
992adfc5217SJeff Kirsher #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
9931d187b34SBarak Witkowski
9941d187b34SBarak Witkowski u32 boot_mode;
995adfc5217SJeff Kirsher };
996adfc5217SJeff Kirsher
997adfc5217SJeff Kirsher /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
998adfc5217SJeff Kirsher #define BNX2X_IGU_STAS_MSG_VF_CNT 64
999adfc5217SJeff Kirsher #define BNX2X_IGU_STAS_MSG_PF_CNT 4
1000adfc5217SJeff Kirsher
100127c1151cSYaniv Rosner #define MAX_IGU_ATTN_ACK_TO 100
1002adfc5217SJeff Kirsher /* end of common */
1003adfc5217SJeff Kirsher
1004adfc5217SJeff Kirsher /* port */
1005adfc5217SJeff Kirsher
1006adfc5217SJeff Kirsher struct bnx2x_port {
1007adfc5217SJeff Kirsher u32 pmf;
1008adfc5217SJeff Kirsher
1009adfc5217SJeff Kirsher u32 link_config[LINK_CONFIG_SIZE];
1010adfc5217SJeff Kirsher
1011adfc5217SJeff Kirsher u32 supported[LINK_CONFIG_SIZE];
1012adfc5217SJeff Kirsher
1013adfc5217SJeff Kirsher u32 advertising[LINK_CONFIG_SIZE];
1014adfc5217SJeff Kirsher
1015adfc5217SJeff Kirsher u32 phy_addr;
1016adfc5217SJeff Kirsher
1017adfc5217SJeff Kirsher /* used to synchronize phy accesses */
1018adfc5217SJeff Kirsher struct mutex phy_mutex;
1019adfc5217SJeff Kirsher
1020adfc5217SJeff Kirsher u32 port_stx;
1021adfc5217SJeff Kirsher
1022adfc5217SJeff Kirsher struct nig_stats old_nig_stats;
1023adfc5217SJeff Kirsher };
1024adfc5217SJeff Kirsher
1025adfc5217SJeff Kirsher /* end of port */
1026adfc5217SJeff Kirsher
1027adfc5217SJeff Kirsher #define STATS_OFFSET32(stat_name) \
1028adfc5217SJeff Kirsher (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
1029adfc5217SJeff Kirsher
1030adfc5217SJeff Kirsher /* slow path */
1031adfc5217SJeff Kirsher #define BNX2X_MAX_NUM_OF_VFS 64
1032b9871bcfSAriel Elior #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */
10331ab4434cSAriel Elior #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
1034b9871bcfSAriel Elior
1035b9871bcfSAriel Elior /* We need to reserve doorbell addresses for all VF and queue combinations */
10361ab4434cSAriel Elior #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
1037b9871bcfSAriel Elior
1038b9871bcfSAriel Elior /* The doorbell is configured to have the same number of CIDs for PFs and for
1039b9871bcfSAriel Elior * VFs. For this reason the PF CID zone is as large as the VF zone.
1040b9871bcfSAriel Elior */
1041b9871bcfSAriel Elior #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS
1042b9871bcfSAriel Elior #define BNX2X_MAX_NUM_VF_QUEUES 64
1043adfc5217SJeff Kirsher #define BNX2X_VF_ID_INVALID 0xFF
1044adfc5217SJeff Kirsher
1045b9871bcfSAriel Elior /* the number of VF CIDS multiplied by the amount of bytes reserved for each
1046b9871bcfSAriel Elior * cid must not exceed the size of the VF doorbell
1047b9871bcfSAriel Elior */
1048b9871bcfSAriel Elior #define BNX2X_VF_BAR_SIZE 512
1049b9871bcfSAriel Elior #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT))
1050b9871bcfSAriel Elior #error "VF doorbell bar size is 512"
1051b9871bcfSAriel Elior #endif
1052b9871bcfSAriel Elior
1053adfc5217SJeff Kirsher /*
1054adfc5217SJeff Kirsher * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
1055adfc5217SJeff Kirsher * control by the number of fast-path status blocks supported by the
1056adfc5217SJeff Kirsher * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
1057adfc5217SJeff Kirsher * status block represents an independent interrupts context that can
1058adfc5217SJeff Kirsher * serve a regular L2 networking queue. However special L2 queues such
1059adfc5217SJeff Kirsher * as the FCoE queue do not require a FP-SB and other components like
1060adfc5217SJeff Kirsher * the CNIC may consume FP-SB reducing the number of possible L2 queues
1061adfc5217SJeff Kirsher *
1062adfc5217SJeff Kirsher * If the maximum number of FP-SB available is X then:
1063adfc5217SJeff Kirsher * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
1064adfc5217SJeff Kirsher * regular L2 queues is Y=X-1
106516a5fd92SYuval Mintz * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1066adfc5217SJeff Kirsher * c. If the FCoE L2 queue is supported the actual number of L2 queues
1067adfc5217SJeff Kirsher * is Y+1
1068adfc5217SJeff Kirsher * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1069adfc5217SJeff Kirsher * slow-path interrupts) or Y+2 if CNIC is supported (one additional
1070adfc5217SJeff Kirsher * FP interrupt context for the CNIC).
1071adfc5217SJeff Kirsher * e. The number of HW context (CID count) is always X or X+1 if FCoE
107216a5fd92SYuval Mintz * L2 queue is supported. The cid for the FCoE L2 queue is always X.
1073adfc5217SJeff Kirsher */
1074adfc5217SJeff Kirsher
1075adfc5217SJeff Kirsher /* fast-path interrupt contexts E1x */
1076adfc5217SJeff Kirsher #define FP_SB_MAX_E1x 16
1077adfc5217SJeff Kirsher /* fast-path interrupt contexts E2 */
1078adfc5217SJeff Kirsher #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
1079adfc5217SJeff Kirsher
1080adfc5217SJeff Kirsher union cdu_context {
1081adfc5217SJeff Kirsher struct eth_context eth;
1082adfc5217SJeff Kirsher char pad[1024];
1083adfc5217SJeff Kirsher };
1084adfc5217SJeff Kirsher
1085adfc5217SJeff Kirsher /* CDU host DB constants */
1086a052997eSMerav Sicron #define CDU_ILT_PAGE_SZ_HW 2
1087a052997eSMerav Sicron #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1088adfc5217SJeff Kirsher #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1089adfc5217SJeff Kirsher
1090adfc5217SJeff Kirsher #define CNIC_ISCSI_CID_MAX 256
1091adfc5217SJeff Kirsher #define CNIC_FCOE_CID_MAX 2048
1092adfc5217SJeff Kirsher #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1093adfc5217SJeff Kirsher #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1094adfc5217SJeff Kirsher
1095adfc5217SJeff Kirsher #define QM_ILT_PAGE_SZ_HW 0
1096adfc5217SJeff Kirsher #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1097adfc5217SJeff Kirsher #define QM_CID_ROUND 1024
1098adfc5217SJeff Kirsher
1099adfc5217SJeff Kirsher /* TM (timers) host DB constants */
1100adfc5217SJeff Kirsher #define TM_ILT_PAGE_SZ_HW 0
1101adfc5217SJeff Kirsher #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
11020907f34cSAriel Elior #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \
11030907f34cSAriel Elior BNX2X_VF_CIDS + \
11040907f34cSAriel Elior CNIC_ISCSI_CID_MAX)
1105adfc5217SJeff Kirsher #define TM_ILT_SZ (8 * TM_CONN_NUM)
1106adfc5217SJeff Kirsher #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1107adfc5217SJeff Kirsher
1108adfc5217SJeff Kirsher /* SRC (Searcher) host DB constants */
1109adfc5217SJeff Kirsher #define SRC_ILT_PAGE_SZ_HW 0
1110adfc5217SJeff Kirsher #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1111adfc5217SJeff Kirsher #define SRC_HASH_BITS 10
1112adfc5217SJeff Kirsher #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1113adfc5217SJeff Kirsher #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1114adfc5217SJeff Kirsher #define SRC_T2_SZ SRC_ILT_SZ
1115adfc5217SJeff Kirsher #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1116adfc5217SJeff Kirsher
1117adfc5217SJeff Kirsher #define MAX_DMAE_C 8
1118adfc5217SJeff Kirsher
1119adfc5217SJeff Kirsher /* DMA memory not used in fastpath */
1120adfc5217SJeff Kirsher struct bnx2x_slowpath {
1121adfc5217SJeff Kirsher union {
1122adfc5217SJeff Kirsher struct mac_configuration_cmd e1x;
1123adfc5217SJeff Kirsher struct eth_classify_rules_ramrod_data e2;
1124adfc5217SJeff Kirsher } mac_rdata;
1125adfc5217SJeff Kirsher
1126adfc5217SJeff Kirsher union {
112705cc5a39SYuval Mintz struct eth_classify_rules_ramrod_data e2;
112805cc5a39SYuval Mintz } vlan_rdata;
112905cc5a39SYuval Mintz
113005cc5a39SYuval Mintz union {
1131adfc5217SJeff Kirsher struct tstorm_eth_mac_filter_config e1x;
1132adfc5217SJeff Kirsher struct eth_filter_rules_ramrod_data e2;
1133adfc5217SJeff Kirsher } rx_mode_rdata;
1134adfc5217SJeff Kirsher
1135adfc5217SJeff Kirsher union {
1136adfc5217SJeff Kirsher struct mac_configuration_cmd e1;
1137adfc5217SJeff Kirsher struct eth_multicast_rules_ramrod_data e2;
1138adfc5217SJeff Kirsher } mcast_rdata;
1139adfc5217SJeff Kirsher
1140adfc5217SJeff Kirsher struct eth_rss_update_ramrod_data rss_rdata;
1141adfc5217SJeff Kirsher
1142adfc5217SJeff Kirsher /* Queue State related ramrods are always sent under rtnl_lock */
1143adfc5217SJeff Kirsher union {
1144adfc5217SJeff Kirsher struct client_init_ramrod_data init_data;
1145adfc5217SJeff Kirsher struct client_update_ramrod_data update_data;
114614a94ebdSMichal Kalderon struct tpa_update_ramrod_data tpa_data;
1147adfc5217SJeff Kirsher } q_rdata;
1148adfc5217SJeff Kirsher
1149adfc5217SJeff Kirsher union {
1150adfc5217SJeff Kirsher struct function_start_data func_start;
1151adfc5217SJeff Kirsher /* pfc configuration for DCBX ramrod */
1152adfc5217SJeff Kirsher struct flow_control_configuration pfc_config;
1153adfc5217SJeff Kirsher } func_rdata;
1154adfc5217SJeff Kirsher
1155a3348722SBarak Witkowski /* afex ramrod can not be a part of func_rdata union because these
1156a3348722SBarak Witkowski * events might arrive in parallel to other events from func_rdata.
1157a3348722SBarak Witkowski * Therefore, if they would have been defined in the same union,
1158a3348722SBarak Witkowski * data can get corrupted.
1159a3348722SBarak Witkowski */
11609dfef3adSYuval Mintz union {
11619dfef3adSYuval Mintz struct afex_vif_list_ramrod_data viflist_data;
11629dfef3adSYuval Mintz struct function_update_data func_update;
11639dfef3adSYuval Mintz } func_afex_rdata;
1164a3348722SBarak Witkowski
1165adfc5217SJeff Kirsher /* used by dmae command executer */
1166adfc5217SJeff Kirsher struct dmae_command dmae[MAX_DMAE_C];
1167adfc5217SJeff Kirsher
1168adfc5217SJeff Kirsher u32 stats_comp;
1169adfc5217SJeff Kirsher union mac_stats mac_stats;
1170adfc5217SJeff Kirsher struct nig_stats nig_stats;
1171adfc5217SJeff Kirsher struct host_port_stats port_stats;
1172adfc5217SJeff Kirsher struct host_func_stats func_stats;
1173adfc5217SJeff Kirsher
1174adfc5217SJeff Kirsher u32 wb_comp;
1175adfc5217SJeff Kirsher u32 wb_data[4];
11761d187b34SBarak Witkowski
11771d187b34SBarak Witkowski union drv_info_to_mcp drv_info_to_mcp;
1178adfc5217SJeff Kirsher };
1179adfc5217SJeff Kirsher
1180adfc5217SJeff Kirsher #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1181adfc5217SJeff Kirsher #define bnx2x_sp_mapping(bp, var) \
1182adfc5217SJeff Kirsher (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1183adfc5217SJeff Kirsher
1184adfc5217SJeff Kirsher /* attn group wiring */
1185adfc5217SJeff Kirsher #define MAX_DYNAMIC_ATTN_GRPS 8
1186adfc5217SJeff Kirsher
1187adfc5217SJeff Kirsher struct attn_route {
1188adfc5217SJeff Kirsher u32 sig[5];
1189adfc5217SJeff Kirsher };
1190adfc5217SJeff Kirsher
1191adfc5217SJeff Kirsher struct iro {
1192adfc5217SJeff Kirsher u32 base;
1193adfc5217SJeff Kirsher u16 m1;
1194adfc5217SJeff Kirsher u16 m2;
1195adfc5217SJeff Kirsher u16 m3;
1196adfc5217SJeff Kirsher u16 size;
1197adfc5217SJeff Kirsher };
1198adfc5217SJeff Kirsher
1199adfc5217SJeff Kirsher struct hw_context {
1200adfc5217SJeff Kirsher union cdu_context *vcxt;
1201adfc5217SJeff Kirsher dma_addr_t cxt_mapping;
1202adfc5217SJeff Kirsher size_t size;
1203adfc5217SJeff Kirsher };
1204adfc5217SJeff Kirsher
1205adfc5217SJeff Kirsher /* forward */
1206adfc5217SJeff Kirsher struct bnx2x_ilt;
1207adfc5217SJeff Kirsher
1208290ca2bbSAriel Elior struct bnx2x_vfdb;
1209adfc5217SJeff Kirsher
1210adfc5217SJeff Kirsher enum bnx2x_recovery_state {
1211adfc5217SJeff Kirsher BNX2X_RECOVERY_DONE,
1212adfc5217SJeff Kirsher BNX2X_RECOVERY_INIT,
1213adfc5217SJeff Kirsher BNX2X_RECOVERY_WAIT,
121495c6c616SAriel Elior BNX2X_RECOVERY_FAILED,
121595c6c616SAriel Elior BNX2X_RECOVERY_NIC_LOADING
1216adfc5217SJeff Kirsher };
1217adfc5217SJeff Kirsher
1218adfc5217SJeff Kirsher /*
1219adfc5217SJeff Kirsher * Event queue (EQ or event ring) MC hsi
1220adfc5217SJeff Kirsher * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1221adfc5217SJeff Kirsher */
1222adfc5217SJeff Kirsher #define NUM_EQ_PAGES 1
1223adfc5217SJeff Kirsher #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1224adfc5217SJeff Kirsher #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1225adfc5217SJeff Kirsher #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1226adfc5217SJeff Kirsher #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1227adfc5217SJeff Kirsher #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1228adfc5217SJeff Kirsher
1229adfc5217SJeff Kirsher /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1230adfc5217SJeff Kirsher #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1231adfc5217SJeff Kirsher (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1232adfc5217SJeff Kirsher
1233adfc5217SJeff Kirsher /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1234adfc5217SJeff Kirsher #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1235adfc5217SJeff Kirsher
1236adfc5217SJeff Kirsher #define BNX2X_EQ_INDEX \
1237adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\
1238adfc5217SJeff Kirsher index_values[HC_SP_INDEX_EQ_CONS])
1239adfc5217SJeff Kirsher
1240adfc5217SJeff Kirsher /* This is a data that will be used to create a link report message.
1241adfc5217SJeff Kirsher * We will keep the data used for the last link report in order
1242adfc5217SJeff Kirsher * to prevent reporting the same link parameters twice.
1243adfc5217SJeff Kirsher */
1244adfc5217SJeff Kirsher struct bnx2x_link_report_data {
1245adfc5217SJeff Kirsher u16 line_speed; /* Effective line speed */
1246adfc5217SJeff Kirsher unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1247adfc5217SJeff Kirsher };
1248adfc5217SJeff Kirsher
1249adfc5217SJeff Kirsher enum {
1250adfc5217SJeff Kirsher BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1251adfc5217SJeff Kirsher BNX2X_LINK_REPORT_LINK_DOWN,
1252adfc5217SJeff Kirsher BNX2X_LINK_REPORT_RX_FC_ON,
1253adfc5217SJeff Kirsher BNX2X_LINK_REPORT_TX_FC_ON,
1254adfc5217SJeff Kirsher };
1255adfc5217SJeff Kirsher
1256adfc5217SJeff Kirsher enum {
1257adfc5217SJeff Kirsher BNX2X_PORT_QUERY_IDX,
1258adfc5217SJeff Kirsher BNX2X_PF_QUERY_IDX,
125950f0a562SBarak Witkowski BNX2X_FCOE_QUERY_IDX,
1260adfc5217SJeff Kirsher BNX2X_FIRST_QUEUE_QUERY_IDX,
1261adfc5217SJeff Kirsher };
1262adfc5217SJeff Kirsher
1263adfc5217SJeff Kirsher struct bnx2x_fw_stats_req {
1264adfc5217SJeff Kirsher struct stats_query_header hdr;
126550f0a562SBarak Witkowski struct stats_query_entry query[FP_SB_MAX_E1x+
126650f0a562SBarak Witkowski BNX2X_FIRST_QUEUE_QUERY_IDX];
1267adfc5217SJeff Kirsher };
1268adfc5217SJeff Kirsher
1269adfc5217SJeff Kirsher struct bnx2x_fw_stats_data {
1270adfc5217SJeff Kirsher struct stats_counter storm_counters;
1271adfc5217SJeff Kirsher struct per_port_stats port;
1272adfc5217SJeff Kirsher struct per_pf_stats pf;
127350f0a562SBarak Witkowski struct fcoe_statistics_params fcoe;
127476ad950cSGustavo A. R. Silva struct per_queue_stats queue_stats[];
1275adfc5217SJeff Kirsher };
1276adfc5217SJeff Kirsher
1277adfc5217SJeff Kirsher /* Public slow path states */
1278230bb0f3SYuval Mintz enum sp_rtnl_flag {
1279adfc5217SJeff Kirsher BNX2X_SP_RTNL_SETUP_TC,
1280adfc5217SJeff Kirsher BNX2X_SP_RTNL_TX_TIMEOUT,
12818304859aSAriel Elior BNX2X_SP_RTNL_FAN_FAILURE,
12828395be5eSAriel Elior BNX2X_SP_RTNL_AFEX_F_UPDATE,
12838395be5eSAriel Elior BNX2X_SP_RTNL_ENABLE_SRIOV,
1284381ac16bSAriel Elior BNX2X_SP_RTNL_VFPF_MCAST,
128578c3bcc5SAriel Elior BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
12868b09be5fSYuval Mintz BNX2X_SP_RTNL_RX_MODE,
12873ec9f9caSAriel Elior BNX2X_SP_RTNL_HYPERVISOR_VLAN,
128807b4eb3bSDmitry Kravkov BNX2X_SP_RTNL_TX_STOP,
128942f8277fSYuval Mintz BNX2X_SP_RTNL_GET_DRV_VERSION,
12909061193cSSudarsana Reddy Kalluru BNX2X_SP_RTNL_UPDATE_SVID,
1291adfc5217SJeff Kirsher };
1292adfc5217SJeff Kirsher
1293370d4a26SYuval Mintz enum bnx2x_iov_flag {
1294370d4a26SYuval Mintz BNX2X_IOV_HANDLE_VF_MSG,
1295370d4a26SYuval Mintz BNX2X_IOV_HANDLE_FLR,
1296370d4a26SYuval Mintz };
1297370d4a26SYuval Mintz
1298452427b0SYuval Mintz struct bnx2x_prev_path_list {
12997fa6f340SYuval Mintz struct list_head list;
1300452427b0SYuval Mintz u8 bus;
1301452427b0SYuval Mintz u8 slot;
1302452427b0SYuval Mintz u8 path;
13037fa6f340SYuval Mintz u8 aer;
1304c63da990SBarak Witkowski u8 undi;
1305452427b0SYuval Mintz };
1306452427b0SYuval Mintz
130715192a8cSBarak Witkowski struct bnx2x_sp_objs {
130815192a8cSBarak Witkowski /* MACs object */
130915192a8cSBarak Witkowski struct bnx2x_vlan_mac_obj mac_obj;
131015192a8cSBarak Witkowski
131115192a8cSBarak Witkowski /* Queue State object */
131215192a8cSBarak Witkowski struct bnx2x_queue_sp_obj q_obj;
131305cc5a39SYuval Mintz
131405cc5a39SYuval Mintz /* VLANs object */
131505cc5a39SYuval Mintz struct bnx2x_vlan_mac_obj vlan_obj;
131615192a8cSBarak Witkowski };
131715192a8cSBarak Witkowski
131815192a8cSBarak Witkowski struct bnx2x_fp_stats {
131915192a8cSBarak Witkowski struct tstorm_per_queue_stats old_tclient;
132015192a8cSBarak Witkowski struct ustorm_per_queue_stats old_uclient;
132115192a8cSBarak Witkowski struct xstorm_per_queue_stats old_xclient;
132215192a8cSBarak Witkowski struct bnx2x_eth_q_stats eth_q_stats;
132315192a8cSBarak Witkowski struct bnx2x_eth_q_stats_old eth_q_stats_old;
132415192a8cSBarak Witkowski };
132515192a8cSBarak Witkowski
13267609647eSYuval Mintz enum {
13277609647eSYuval Mintz SUB_MF_MODE_UNKNOWN = 0,
13287609647eSYuval Mintz SUB_MF_MODE_UFP,
132983bad206SYuval Mintz SUB_MF_MODE_NPAR1_DOT_5,
1330230d00ebSYuval Mintz SUB_MF_MODE_BD,
13317609647eSYuval Mintz };
13327609647eSYuval Mintz
133305cc5a39SYuval Mintz struct bnx2x_vlan_entry {
133405cc5a39SYuval Mintz struct list_head link;
133505cc5a39SYuval Mintz u16 vid;
133605cc5a39SYuval Mintz bool hw;
133705cc5a39SYuval Mintz };
133805cc5a39SYuval Mintz
1339883ce97dSYuval Mintz enum bnx2x_udp_port_type {
1340883ce97dSYuval Mintz BNX2X_UDP_PORT_VXLAN,
1341883ce97dSYuval Mintz BNX2X_UDP_PORT_GENEVE,
1342883ce97dSYuval Mintz BNX2X_UDP_PORT_MAX,
1343883ce97dSYuval Mintz };
1344883ce97dSYuval Mintz
1345adfc5217SJeff Kirsher struct bnx2x {
1346adfc5217SJeff Kirsher /* Fields used in the tx and intr/napi performance paths
1347adfc5217SJeff Kirsher * are grouped together in the beginning of the structure
1348adfc5217SJeff Kirsher */
1349adfc5217SJeff Kirsher struct bnx2x_fastpath *fp;
135015192a8cSBarak Witkowski struct bnx2x_sp_objs *sp_objs;
135115192a8cSBarak Witkowski struct bnx2x_fp_stats *fp_stats;
135265565884SMerav Sicron struct bnx2x_fp_txdata *bnx2x_txq;
1353adfc5217SJeff Kirsher void __iomem *regview;
1354adfc5217SJeff Kirsher void __iomem *doorbells;
1355adfc5217SJeff Kirsher u16 db_size;
1356adfc5217SJeff Kirsher
1357adfc5217SJeff Kirsher u8 pf_num; /* absolute PF number */
1358adfc5217SJeff Kirsher u8 pfid; /* per-path PF number */
1359adfc5217SJeff Kirsher int base_fw_ndsb; /**/
1360adfc5217SJeff Kirsher #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1361adfc5217SJeff Kirsher #define BP_PORT(bp) (bp->pfid & 1)
1362adfc5217SJeff Kirsher #define BP_FUNC(bp) (bp->pfid)
1363adfc5217SJeff Kirsher #define BP_ABS_FUNC(bp) (bp->pf_num)
13648decf868SDavid S. Miller #define BP_VN(bp) ((bp)->pfid >> 1)
13658decf868SDavid S. Miller #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
13668decf868SDavid S. Miller #define BP_L_ID(bp) (BP_VN(bp) << 2)
13678decf868SDavid S. Miller #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
13688decf868SDavid S. Miller (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
13698decf868SDavid S. Miller #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1370adfc5217SJeff Kirsher
13716411280aSAriel Elior #ifdef CONFIG_BNX2X_SRIOV
13721d6f3cd8SDmitry Kravkov /* protects vf2pf mailbox from simultaneous access */
13731d6f3cd8SDmitry Kravkov struct mutex vf2pf_mutex;
13741ab4434cSAriel Elior /* vf pf channel mailbox contains request and response buffers */
13751ab4434cSAriel Elior struct bnx2x_vf_mbx_msg *vf2pf_mbox;
13761ab4434cSAriel Elior dma_addr_t vf2pf_mbox_mapping;
13771ab4434cSAriel Elior
1378be1f1ffaSAriel Elior /* we set aside a copy of the acquire response */
1379be1f1ffaSAriel Elior struct pfvf_acquire_resp_tlv acquire_resp;
1380be1f1ffaSAriel Elior
1381abc5a021SAriel Elior /* bulletin board for messages from pf to vf */
1382abc5a021SAriel Elior union pf_vf_bulletin *pf2vf_bulletin;
1383abc5a021SAriel Elior dma_addr_t pf2vf_bulletin_mapping;
1384abc5a021SAriel Elior
13856495d15aSDmitry Kravkov union pf_vf_bulletin shadow_bulletin;
1386abc5a021SAriel Elior struct pf_vf_bulletin_content old_bulletin;
13873c76feffSAriel Elior
13883c76feffSAriel Elior u16 requested_nr_virtfn;
13896411280aSAriel Elior #endif /* CONFIG_BNX2X_SRIOV */
1390abc5a021SAriel Elior
1391adfc5217SJeff Kirsher struct net_device *dev;
1392adfc5217SJeff Kirsher struct pci_dev *pdev;
1393adfc5217SJeff Kirsher
1394adfc5217SJeff Kirsher const struct iro *iro_arr;
1395adfc5217SJeff Kirsher #define IRO (bp->iro_arr)
1396adfc5217SJeff Kirsher
1397adfc5217SJeff Kirsher enum bnx2x_recovery_state recovery_state;
1398adfc5217SJeff Kirsher int is_leader;
1399adfc5217SJeff Kirsher struct msix_entry *msix_table;
1400adfc5217SJeff Kirsher
1401adfc5217SJeff Kirsher int tx_ring_size;
1402adfc5217SJeff Kirsher
1403adfc5217SJeff Kirsher /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1404e1c6dccaSJarod Wilson #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
1405e1c6dccaSJarod Wilson #define ETH_MIN_PACKET_SIZE (ETH_ZLEN - ETH_HLEN)
1406e1c6dccaSJarod Wilson #define ETH_MAX_PACKET_SIZE ETH_DATA_LEN
1407adfc5217SJeff Kirsher #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1408621b4d66SDmitry Kravkov /* TCP with Timestamp Option (32) + IPv6 (40) */
1409621b4d66SDmitry Kravkov #define ETH_MAX_TPA_HEADER_SIZE 72
1410adfc5217SJeff Kirsher
14119927b514SDmitry Kravkov /* Max supported alignment is 256 (8 shift)
14129927b514SDmitry Kravkov * minimal alignment shift 6 is optimal for 57xxx HW performance
14139927b514SDmitry Kravkov */
14149927b514SDmitry Kravkov #define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
1415e52fcb24SEric Dumazet
1416e52fcb24SEric Dumazet /* FW uses 2 Cache lines Alignment for start packet and size
1417e52fcb24SEric Dumazet *
1418e52fcb24SEric Dumazet * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1419e52fcb24SEric Dumazet * at the end of skb->data, to avoid wasting a full cache line.
1420e52fcb24SEric Dumazet * This reduces memory use (skb->truesize).
1421e52fcb24SEric Dumazet */
1422e52fcb24SEric Dumazet #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1423e52fcb24SEric Dumazet
1424e52fcb24SEric Dumazet #define BNX2X_FW_RX_ALIGN_END \
1425f57b07c0SJoren Van Onder max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1426e52fcb24SEric Dumazet SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1427e52fcb24SEric Dumazet
1428adfc5217SJeff Kirsher #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1429adfc5217SJeff Kirsher
1430adfc5217SJeff Kirsher struct host_sp_status_block *def_status_blk;
1431adfc5217SJeff Kirsher #define DEF_SB_IGU_ID 16
1432adfc5217SJeff Kirsher #define DEF_SB_ID HC_SP_SB_ID
1433adfc5217SJeff Kirsher __le16 def_idx;
1434adfc5217SJeff Kirsher __le16 def_att_idx;
1435adfc5217SJeff Kirsher u32 attn_state;
1436adfc5217SJeff Kirsher struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1437adfc5217SJeff Kirsher
1438adfc5217SJeff Kirsher /* slow path ring */
1439adfc5217SJeff Kirsher struct eth_spe *spq;
1440adfc5217SJeff Kirsher dma_addr_t spq_mapping;
1441adfc5217SJeff Kirsher u16 spq_prod_idx;
1442adfc5217SJeff Kirsher struct eth_spe *spq_prod_bd;
1443adfc5217SJeff Kirsher struct eth_spe *spq_last_bd;
1444adfc5217SJeff Kirsher __le16 *dsb_sp_prod;
1445adfc5217SJeff Kirsher atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1446adfc5217SJeff Kirsher /* used to synchronize spq accesses */
1447adfc5217SJeff Kirsher spinlock_t spq_lock;
1448adfc5217SJeff Kirsher
1449adfc5217SJeff Kirsher /* event queue */
1450adfc5217SJeff Kirsher union event_ring_elem *eq_ring;
1451adfc5217SJeff Kirsher dma_addr_t eq_mapping;
1452adfc5217SJeff Kirsher u16 eq_prod;
1453adfc5217SJeff Kirsher u16 eq_cons;
1454adfc5217SJeff Kirsher __le16 *eq_cons_sb;
1455adfc5217SJeff Kirsher atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1456adfc5217SJeff Kirsher
1457adfc5217SJeff Kirsher /* Counter for marking that there is a STAT_QUERY ramrod pending */
1458adfc5217SJeff Kirsher u16 stats_pending;
1459adfc5217SJeff Kirsher /* Counter for completed statistics ramrods */
1460adfc5217SJeff Kirsher u16 stats_comp;
1461adfc5217SJeff Kirsher
1462adfc5217SJeff Kirsher /* End of fields used in the performance code paths */
1463adfc5217SJeff Kirsher
1464adfc5217SJeff Kirsher int panic;
1465adfc5217SJeff Kirsher int msg_enable;
1466adfc5217SJeff Kirsher
1467adfc5217SJeff Kirsher u32 flags;
1468adfc5217SJeff Kirsher #define PCIX_FLAG (1 << 0)
1469adfc5217SJeff Kirsher #define PCI_32BIT_FLAG (1 << 1)
1470adfc5217SJeff Kirsher #define ONE_PORT_FLAG (1 << 2)
1471adfc5217SJeff Kirsher #define NO_WOL_FLAG (1 << 3)
1472adfc5217SJeff Kirsher #define USING_MSIX_FLAG (1 << 5)
1473adfc5217SJeff Kirsher #define USING_MSI_FLAG (1 << 6)
1474adfc5217SJeff Kirsher #define DISABLE_MSI_FLAG (1 << 7)
1475adfc5217SJeff Kirsher #define NO_MCP_FLAG (1 << 9)
1476adfc5217SJeff Kirsher #define MF_FUNC_DIS (1 << 11)
1477adfc5217SJeff Kirsher #define OWN_CNIC_IRQ (1 << 12)
1478adfc5217SJeff Kirsher #define NO_ISCSI_OOO_FLAG (1 << 13)
1479adfc5217SJeff Kirsher #define NO_ISCSI_FLAG (1 << 14)
1480adfc5217SJeff Kirsher #define NO_FCOE_FLAG (1 << 15)
14810e898dd7SBarak Witkowski #define BC_SUPPORTS_PFC_STATS (1 << 17)
1482c14db202SYuval Mintz #define TX_SWITCHING (1 << 18)
14832e499d3cSBarak Witkowski #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
148430a5de77SDmitry Kravkov #define USING_SINGLE_MSIX_FLAG (1 << 20)
14859876879fSBarak Witkowski #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
14861ab4434cSAriel Elior #define IS_VF_FLAG (1 << 22)
14870c23ad37SYuval Mintz #define BC_SUPPORTS_RMMOD_CMD (1 << 23)
14880c23ad37SYuval Mintz #define HAS_PHYS_PORT_ID (1 << 24)
14890c23ad37SYuval Mintz #define PTP_SUPPORTED (1 << 26)
14900c23ad37SYuval Mintz #define TX_TIMESTAMPING_EN (1 << 27)
14911ab4434cSAriel Elior
14921ab4434cSAriel Elior #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
14936411280aSAriel Elior
14946411280aSAriel Elior #ifdef CONFIG_BNX2X_SRIOV
14951ab4434cSAriel Elior #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
14961ab4434cSAriel Elior #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
14976411280aSAriel Elior #else
14986411280aSAriel Elior #define IS_VF(bp) false
14996411280aSAriel Elior #define IS_PF(bp) true
15006411280aSAriel Elior #endif
1501adfc5217SJeff Kirsher
1502adfc5217SJeff Kirsher #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1503adfc5217SJeff Kirsher #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1504adfc5217SJeff Kirsher #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1505adfc5217SJeff Kirsher
150655c11941SMerav Sicron u8 cnic_support;
150755c11941SMerav Sicron bool cnic_enabled;
150855c11941SMerav Sicron bool cnic_loaded;
15094bd9b0ffSMichael Chan struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
151055c11941SMerav Sicron
1511*bf23ffc8SThinh Tran bool nic_stopped;
1512*bf23ffc8SThinh Tran
151355c11941SMerav Sicron /* Flag that indicates that we can start looking for FCoE L2 queue
151455c11941SMerav Sicron * completions in the default status block.
151555c11941SMerav Sicron */
151655c11941SMerav Sicron bool fcoe_init;
151755c11941SMerav Sicron
1518adfc5217SJeff Kirsher int mrrs;
1519adfc5217SJeff Kirsher
1520adfc5217SJeff Kirsher struct delayed_work sp_task;
1521370d4a26SYuval Mintz struct delayed_work iov_task;
1522370d4a26SYuval Mintz
1523fd1fc79dSAriel Elior atomic_t interrupt_occurred;
1524adfc5217SJeff Kirsher struct delayed_work sp_rtnl_task;
1525adfc5217SJeff Kirsher
1526adfc5217SJeff Kirsher struct delayed_work period_task;
1527adfc5217SJeff Kirsher struct timer_list timer;
1528adfc5217SJeff Kirsher int current_interval;
1529adfc5217SJeff Kirsher
1530adfc5217SJeff Kirsher u16 fw_seq;
1531adfc5217SJeff Kirsher u16 fw_drv_pulse_wr_seq;
1532adfc5217SJeff Kirsher u32 func_stx;
1533adfc5217SJeff Kirsher
1534adfc5217SJeff Kirsher struct link_params link_params;
1535adfc5217SJeff Kirsher struct link_vars link_vars;
1536adfc5217SJeff Kirsher u32 link_cnt;
1537adfc5217SJeff Kirsher struct bnx2x_link_report_data last_reported_link;
1538484c016dSSudarsana Reddy Kalluru bool force_link_down;
1539adfc5217SJeff Kirsher
1540adfc5217SJeff Kirsher struct mdio_if_info mdio;
1541adfc5217SJeff Kirsher
1542adfc5217SJeff Kirsher struct bnx2x_common common;
1543adfc5217SJeff Kirsher struct bnx2x_port port;
1544adfc5217SJeff Kirsher
1545b475d78fSYuval Mintz struct cmng_init cmng;
1546b475d78fSYuval Mintz
1547adfc5217SJeff Kirsher u32 mf_config[E1HVN_MAX];
1548a3348722SBarak Witkowski u32 mf_ext_config;
1549adfc5217SJeff Kirsher u32 path_has_ovlan; /* E3 */
1550adfc5217SJeff Kirsher u16 mf_ov;
1551adfc5217SJeff Kirsher u8 mf_mode;
1552adfc5217SJeff Kirsher #define IS_MF(bp) (bp->mf_mode != 0)
1553adfc5217SJeff Kirsher #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1554adfc5217SJeff Kirsher #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1555a3348722SBarak Witkowski #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
15567609647eSYuval Mintz u8 mf_sub_mode;
15577609647eSYuval Mintz #define IS_MF_UFP(bp) (IS_MF_SD(bp) && \
15587609647eSYuval Mintz bp->mf_sub_mode == SUB_MF_MODE_UFP)
1559230d00ebSYuval Mintz #define IS_MF_BD(bp) (IS_MF_SD(bp) && \
1560230d00ebSYuval Mintz bp->mf_sub_mode == SUB_MF_MODE_BD)
1561adfc5217SJeff Kirsher
1562adfc5217SJeff Kirsher u8 wol;
1563adfc5217SJeff Kirsher
1564adfc5217SJeff Kirsher int rx_ring_size;
1565adfc5217SJeff Kirsher
1566adfc5217SJeff Kirsher u16 tx_quick_cons_trip_int;
1567adfc5217SJeff Kirsher u16 tx_quick_cons_trip;
1568adfc5217SJeff Kirsher u16 tx_ticks_int;
1569adfc5217SJeff Kirsher u16 tx_ticks;
1570adfc5217SJeff Kirsher
1571adfc5217SJeff Kirsher u16 rx_quick_cons_trip_int;
1572adfc5217SJeff Kirsher u16 rx_quick_cons_trip;
1573adfc5217SJeff Kirsher u16 rx_ticks_int;
1574adfc5217SJeff Kirsher u16 rx_ticks;
1575adfc5217SJeff Kirsher /* Maximal coalescing timeout in us */
15766802516eSDmitry Kravkov #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR)
1577adfc5217SJeff Kirsher
1578adfc5217SJeff Kirsher u32 lin_cnt;
1579adfc5217SJeff Kirsher
1580adfc5217SJeff Kirsher u16 state;
1581adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSED 0
1582adfc5217SJeff Kirsher #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1583adfc5217SJeff Kirsher #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1584adfc5217SJeff Kirsher #define BNX2X_STATE_OPEN 0x3000
1585adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1586adfc5217SJeff Kirsher #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1587adfc5217SJeff Kirsher
1588adfc5217SJeff Kirsher #define BNX2X_STATE_DIAG 0xe000
1589adfc5217SJeff Kirsher #define BNX2X_STATE_ERROR 0xf000
1590adfc5217SJeff Kirsher
1591adfc5217SJeff Kirsher #define BNX2X_MAX_PRIORITY 8
1592adfc5217SJeff Kirsher int num_queues;
159355c11941SMerav Sicron uint num_ethernet_queues;
159455c11941SMerav Sicron uint num_cnic_queues;
1595adfc5217SJeff Kirsher int disable_tpa;
1596adfc5217SJeff Kirsher
1597adfc5217SJeff Kirsher u32 rx_mode;
1598adfc5217SJeff Kirsher #define BNX2X_RX_MODE_NONE 0
1599adfc5217SJeff Kirsher #define BNX2X_RX_MODE_NORMAL 1
1600adfc5217SJeff Kirsher #define BNX2X_RX_MODE_ALLMULTI 2
1601adfc5217SJeff Kirsher #define BNX2X_RX_MODE_PROMISC 3
1602adfc5217SJeff Kirsher #define BNX2X_MAX_MULTICAST 64
1603adfc5217SJeff Kirsher
1604adfc5217SJeff Kirsher u8 igu_dsb_id;
1605adfc5217SJeff Kirsher u8 igu_base_sb;
1606adfc5217SJeff Kirsher u8 igu_sb_cnt;
160755c11941SMerav Sicron u8 min_msix_vec_cnt;
160865565884SMerav Sicron
16091ab4434cSAriel Elior u32 igu_base_addr;
1610adfc5217SJeff Kirsher dma_addr_t def_status_blk_mapping;
1611adfc5217SJeff Kirsher
1612adfc5217SJeff Kirsher struct bnx2x_slowpath *slowpath;
1613adfc5217SJeff Kirsher dma_addr_t slowpath_mapping;
1614adfc5217SJeff Kirsher
161542f8277fSYuval Mintz /* Mechanism protecting the drv_info_to_mcp */
161642f8277fSYuval Mintz struct mutex drv_info_mutex;
161742f8277fSYuval Mintz bool drv_info_mng_owner;
161842f8277fSYuval Mintz
1619adfc5217SJeff Kirsher /* Total number of FW statistics requests */
1620adfc5217SJeff Kirsher u8 fw_stats_num;
1621adfc5217SJeff Kirsher
1622adfc5217SJeff Kirsher /*
1623adfc5217SJeff Kirsher * This is a memory buffer that will contain both statistics
1624adfc5217SJeff Kirsher * ramrod request and data.
1625adfc5217SJeff Kirsher */
1626adfc5217SJeff Kirsher void *fw_stats;
1627adfc5217SJeff Kirsher dma_addr_t fw_stats_mapping;
1628adfc5217SJeff Kirsher
1629adfc5217SJeff Kirsher /*
1630adfc5217SJeff Kirsher * FW statistics request shortcut (points at the
1631adfc5217SJeff Kirsher * beginning of fw_stats buffer).
1632adfc5217SJeff Kirsher */
1633adfc5217SJeff Kirsher struct bnx2x_fw_stats_req *fw_stats_req;
1634adfc5217SJeff Kirsher dma_addr_t fw_stats_req_mapping;
1635adfc5217SJeff Kirsher int fw_stats_req_sz;
1636adfc5217SJeff Kirsher
1637adfc5217SJeff Kirsher /*
16384907cb7bSAnatol Pomozov * FW statistics data shortcut (points at the beginning of
1639adfc5217SJeff Kirsher * fw_stats buffer + fw_stats_req_sz).
1640adfc5217SJeff Kirsher */
1641adfc5217SJeff Kirsher struct bnx2x_fw_stats_data *fw_stats_data;
1642adfc5217SJeff Kirsher dma_addr_t fw_stats_data_mapping;
1643adfc5217SJeff Kirsher int fw_stats_data_sz;
1644adfc5217SJeff Kirsher
1645b9871bcfSAriel Elior /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB
1646a052997eSMerav Sicron * context size we need 8 ILT entries.
1647a052997eSMerav Sicron */
1648b9871bcfSAriel Elior #define ILT_MAX_L2_LINES 32
1649a052997eSMerav Sicron struct hw_context context[ILT_MAX_L2_LINES];
1650adfc5217SJeff Kirsher
1651adfc5217SJeff Kirsher struct bnx2x_ilt *ilt;
1652adfc5217SJeff Kirsher #define BP_ILT(bp) ((bp)->ilt)
1653adfc5217SJeff Kirsher #define ILT_MAX_LINES 256
1654adfc5217SJeff Kirsher /*
1655adfc5217SJeff Kirsher * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1656adfc5217SJeff Kirsher * to CNIC.
1657adfc5217SJeff Kirsher */
165855c11941SMerav Sicron #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1659adfc5217SJeff Kirsher
1660adfc5217SJeff Kirsher /*
1661adfc5217SJeff Kirsher * Maximum CID count that might be required by the bnx2x:
166237ae41a9SMerav Sicron * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1663adfc5217SJeff Kirsher */
1664f78afb35SMichael Chan
166537ae41a9SMerav Sicron #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1666f78afb35SMichael Chan + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
166737ae41a9SMerav Sicron #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1668f78afb35SMichael Chan + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1669adfc5217SJeff Kirsher #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1670adfc5217SJeff Kirsher ILT_PAGE_CIDS))
1671adfc5217SJeff Kirsher
1672adfc5217SJeff Kirsher int qm_cid_count;
1673adfc5217SJeff Kirsher
16747964211dSYuval Mintz bool dropless_fc;
1675adfc5217SJeff Kirsher
1676adfc5217SJeff Kirsher void *t2;
1677adfc5217SJeff Kirsher dma_addr_t t2_mapping;
1678adfc5217SJeff Kirsher struct cnic_ops __rcu *cnic_ops;
1679adfc5217SJeff Kirsher void *cnic_data;
1680adfc5217SJeff Kirsher u32 cnic_tag;
1681adfc5217SJeff Kirsher struct cnic_eth_dev cnic_eth_dev;
1682adfc5217SJeff Kirsher union host_hc_status_block cnic_sb;
1683adfc5217SJeff Kirsher dma_addr_t cnic_sb_mapping;
1684adfc5217SJeff Kirsher struct eth_spe *cnic_kwq;
1685adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_prod;
1686adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_cons;
1687adfc5217SJeff Kirsher struct eth_spe *cnic_kwq_last;
1688adfc5217SJeff Kirsher u16 cnic_kwq_pending;
1689adfc5217SJeff Kirsher u16 cnic_spq_pending;
1690adfc5217SJeff Kirsher u8 fip_mac[ETH_ALEN];
1691adfc5217SJeff Kirsher struct mutex cnic_mutex;
1692adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1693adfc5217SJeff Kirsher
169416a5fd92SYuval Mintz /* Start index of the "special" (CNIC related) L2 clients */
1695adfc5217SJeff Kirsher u8 cnic_base_cl_id;
1696adfc5217SJeff Kirsher
1697adfc5217SJeff Kirsher int dmae_ready;
1698adfc5217SJeff Kirsher /* used to synchronize dmae accesses */
1699adfc5217SJeff Kirsher spinlock_t dmae_lock;
1700adfc5217SJeff Kirsher
1701adfc5217SJeff Kirsher /* used to protect the FW mail box */
1702adfc5217SJeff Kirsher struct mutex fw_mb_mutex;
1703adfc5217SJeff Kirsher
1704adfc5217SJeff Kirsher /* used to synchronize stats collecting */
1705adfc5217SJeff Kirsher int stats_state;
1706adfc5217SJeff Kirsher
1707adfc5217SJeff Kirsher /* used for synchronization of concurrent threads statistics handling */
1708c6e36d8cSYuval Mintz struct semaphore stats_lock;
1709adfc5217SJeff Kirsher
1710adfc5217SJeff Kirsher /* used by dmae command loader */
1711adfc5217SJeff Kirsher struct dmae_command stats_dmae;
1712adfc5217SJeff Kirsher int executer_idx;
1713adfc5217SJeff Kirsher
1714adfc5217SJeff Kirsher u16 stats_counter;
1715adfc5217SJeff Kirsher struct bnx2x_eth_stats eth_stats;
1716cb4dca27SYuval Mintz struct host_func_stats func_stats;
17171355b704SMintz Yuval struct bnx2x_eth_stats_old eth_stats_old;
17181355b704SMintz Yuval struct bnx2x_net_stats_old net_stats_old;
17191355b704SMintz Yuval struct bnx2x_fw_port_stats_old fw_stats_old;
17201355b704SMintz Yuval bool stats_init;
1721adfc5217SJeff Kirsher
1722adfc5217SJeff Kirsher struct z_stream_s *strm;
1723adfc5217SJeff Kirsher void *gunzip_buf;
1724adfc5217SJeff Kirsher dma_addr_t gunzip_mapping;
1725adfc5217SJeff Kirsher int gunzip_outlen;
1726adfc5217SJeff Kirsher #define FW_BUF_SIZE 0x8000
1727adfc5217SJeff Kirsher #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1728adfc5217SJeff Kirsher #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1729adfc5217SJeff Kirsher #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1730adfc5217SJeff Kirsher
1731adfc5217SJeff Kirsher struct raw_op *init_ops;
1732adfc5217SJeff Kirsher /* Init blocks offsets inside init_ops */
1733adfc5217SJeff Kirsher u16 *init_ops_offsets;
1734adfc5217SJeff Kirsher /* Data blob - has 32 bit granularity */
1735adfc5217SJeff Kirsher u32 *init_data;
1736adfc5217SJeff Kirsher u32 init_mode_flags;
1737adfc5217SJeff Kirsher #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1738adfc5217SJeff Kirsher /* Zipped PRAM blobs - raw data */
1739adfc5217SJeff Kirsher const u8 *tsem_int_table_data;
1740adfc5217SJeff Kirsher const u8 *tsem_pram_data;
1741adfc5217SJeff Kirsher const u8 *usem_int_table_data;
1742adfc5217SJeff Kirsher const u8 *usem_pram_data;
1743adfc5217SJeff Kirsher const u8 *xsem_int_table_data;
1744adfc5217SJeff Kirsher const u8 *xsem_pram_data;
1745adfc5217SJeff Kirsher const u8 *csem_int_table_data;
1746adfc5217SJeff Kirsher const u8 *csem_pram_data;
1747adfc5217SJeff Kirsher #define INIT_OPS(bp) (bp->init_ops)
1748adfc5217SJeff Kirsher #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1749adfc5217SJeff Kirsher #define INIT_DATA(bp) (bp->init_data)
1750adfc5217SJeff Kirsher #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1751adfc5217SJeff Kirsher #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1752adfc5217SJeff Kirsher #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1753adfc5217SJeff Kirsher #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1754adfc5217SJeff Kirsher #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1755adfc5217SJeff Kirsher #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1756adfc5217SJeff Kirsher #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1757adfc5217SJeff Kirsher #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1758adfc5217SJeff Kirsher
1759adfc5217SJeff Kirsher #define PHY_FW_VER_LEN 20
1760adfc5217SJeff Kirsher char fw_ver[32];
1761adfc5217SJeff Kirsher const struct firmware *firmware;
1762adfc5217SJeff Kirsher
1763290ca2bbSAriel Elior struct bnx2x_vfdb *vfdb;
1764290ca2bbSAriel Elior #define IS_SRIOV(bp) ((bp)->vfdb)
1765290ca2bbSAriel Elior
1766adfc5217SJeff Kirsher /* DCB support on/off */
1767adfc5217SJeff Kirsher u16 dcb_state;
1768adfc5217SJeff Kirsher #define BNX2X_DCB_STATE_OFF 0
1769adfc5217SJeff Kirsher #define BNX2X_DCB_STATE_ON 1
1770adfc5217SJeff Kirsher
1771adfc5217SJeff Kirsher /* DCBX engine mode */
1772adfc5217SJeff Kirsher int dcbx_enabled;
1773adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_OFF 0
1774adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1775adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1776adfc5217SJeff Kirsher #define BNX2X_DCBX_ENABLED_INVALID (-1)
1777adfc5217SJeff Kirsher
1778adfc5217SJeff Kirsher bool dcbx_mode_uset;
1779adfc5217SJeff Kirsher
1780adfc5217SJeff Kirsher struct bnx2x_config_dcbx_params dcbx_config_params;
1781adfc5217SJeff Kirsher struct bnx2x_dcbx_port_params dcbx_port_params;
1782adfc5217SJeff Kirsher int dcb_version;
1783adfc5217SJeff Kirsher
1784adfc5217SJeff Kirsher /* CAM credit pools */
1785b56e9670SAriel Elior struct bnx2x_credit_pool_obj vlans_pool;
1786b56e9670SAriel Elior
1787adfc5217SJeff Kirsher struct bnx2x_credit_pool_obj macs_pool;
1788adfc5217SJeff Kirsher
1789adfc5217SJeff Kirsher /* RX_MODE object */
1790adfc5217SJeff Kirsher struct bnx2x_rx_mode_obj rx_mode_obj;
1791adfc5217SJeff Kirsher
1792adfc5217SJeff Kirsher /* MCAST object */
1793adfc5217SJeff Kirsher struct bnx2x_mcast_obj mcast_obj;
1794adfc5217SJeff Kirsher
1795adfc5217SJeff Kirsher /* RSS configuration object */
1796adfc5217SJeff Kirsher struct bnx2x_rss_config_obj rss_conf_obj;
1797adfc5217SJeff Kirsher
1798adfc5217SJeff Kirsher /* Function State controlling object */
1799adfc5217SJeff Kirsher struct bnx2x_func_sp_obj func_obj;
1800adfc5217SJeff Kirsher
1801adfc5217SJeff Kirsher unsigned long sp_state;
1802adfc5217SJeff Kirsher
1803adfc5217SJeff Kirsher /* operation indication for the sp_rtnl task */
1804adfc5217SJeff Kirsher unsigned long sp_rtnl_state;
1805adfc5217SJeff Kirsher
1806370d4a26SYuval Mintz /* Indication of the IOV tasks */
1807370d4a26SYuval Mintz unsigned long iov_task_state;
1808370d4a26SYuval Mintz
180916a5fd92SYuval Mintz /* DCBX Negotiation results */
1810adfc5217SJeff Kirsher struct dcbx_features dcbx_local_feat;
1811adfc5217SJeff Kirsher u32 dcbx_error;
1812adfc5217SJeff Kirsher
1813adfc5217SJeff Kirsher #ifdef BCM_DCBNL
1814adfc5217SJeff Kirsher struct dcbx_features dcbx_remote_feat;
1815adfc5217SJeff Kirsher u32 dcbx_remote_flags;
1816adfc5217SJeff Kirsher #endif
1817a3348722SBarak Witkowski /* AFEX: store default vlan used */
1818a3348722SBarak Witkowski int afex_def_vlan_tag;
1819a3348722SBarak Witkowski enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1820adfc5217SJeff Kirsher u32 pending_max;
1821adfc5217SJeff Kirsher
1822adfc5217SJeff Kirsher /* multiple tx classes of service */
1823adfc5217SJeff Kirsher u8 max_cos;
1824adfc5217SJeff Kirsher
1825adfc5217SJeff Kirsher /* priority to cos mapping */
1826adfc5217SJeff Kirsher u8 prio_to_cos[8];
1827c3146eb6SDmitry Kravkov
1828c3146eb6SDmitry Kravkov int fp_array_size;
182907ba6af4SMiriam Shitrit u32 dump_preset_idx;
18303d7d562cSYuval Mintz
18313d7d562cSYuval Mintz u8 phys_port_id[ETH_ALEN];
18326495d15aSDmitry Kravkov
1833eeed018cSMichal Kalderon /* PTP related context */
1834eeed018cSMichal Kalderon struct ptp_clock *ptp_clock;
1835eeed018cSMichal Kalderon struct ptp_clock_info ptp_clock_info;
1836eeed018cSMichal Kalderon struct work_struct ptp_task;
1837eeed018cSMichal Kalderon struct cyclecounter cyclecounter;
1838eeed018cSMichal Kalderon struct timecounter timecounter;
1839eeed018cSMichal Kalderon bool timecounter_init_done;
1840eeed018cSMichal Kalderon struct sk_buff *ptp_tx_skb;
1841eeed018cSMichal Kalderon unsigned long ptp_tx_start;
1842eeed018cSMichal Kalderon bool hwtstamp_ioctl_called;
1843eeed018cSMichal Kalderon u16 tx_type;
1844eeed018cSMichal Kalderon u16 rx_filter;
1845eeed018cSMichal Kalderon
18466495d15aSDmitry Kravkov struct bnx2x_link_report_data vf_link_vars;
184705cc5a39SYuval Mintz struct list_head vlan_reg;
184805cc5a39SYuval Mintz u16 vlan_cnt;
184905cc5a39SYuval Mintz u16 vlan_credit;
185005cc5a39SYuval Mintz bool accept_any_vlan;
1851883ce97dSYuval Mintz
1852883ce97dSYuval Mintz /* Vxlan/Geneve related information */
1853085c5c42SJakub Kicinski u16 udp_tunnel_ports[BNX2X_UDP_PORT_MAX];
1854b7a49f73SManish Chopra
1855b7a49f73SManish Chopra #define FW_CAP_INVALIDATE_VF_FP_HSI BIT(0)
1856b7a49f73SManish Chopra u32 fw_cap;
1857b7a49f73SManish Chopra
1858b7a49f73SManish Chopra u32 fw_major;
1859b7a49f73SManish Chopra u32 fw_minor;
1860b7a49f73SManish Chopra u32 fw_rev;
1861b7a49f73SManish Chopra u32 fw_eng;
1862adfc5217SJeff Kirsher };
1863adfc5217SJeff Kirsher
1864adfc5217SJeff Kirsher /* Tx queues may be less or equal to Rx queues */
1865adfc5217SJeff Kirsher extern int num_queues;
1866adfc5217SJeff Kirsher #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
186755c11941SMerav Sicron #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
186865565884SMerav Sicron #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
186955c11941SMerav Sicron (bp)->num_cnic_queues)
1870adfc5217SJeff Kirsher #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1871adfc5217SJeff Kirsher
1872adfc5217SJeff Kirsher #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1873adfc5217SJeff Kirsher
1874adfc5217SJeff Kirsher #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1875adfc5217SJeff Kirsher /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1876adfc5217SJeff Kirsher
1877adfc5217SJeff Kirsher #define RSS_IPV4_CAP_MASK \
1878adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1879adfc5217SJeff Kirsher
1880adfc5217SJeff Kirsher #define RSS_IPV4_TCP_CAP_MASK \
1881adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1882adfc5217SJeff Kirsher
1883adfc5217SJeff Kirsher #define RSS_IPV6_CAP_MASK \
1884adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1885adfc5217SJeff Kirsher
1886adfc5217SJeff Kirsher #define RSS_IPV6_TCP_CAP_MASK \
1887adfc5217SJeff Kirsher TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1888adfc5217SJeff Kirsher
1889adfc5217SJeff Kirsher struct bnx2x_func_init_params {
1890adfc5217SJeff Kirsher /* dma */
189105cc5a39SYuval Mintz bool spq_active;
189205cc5a39SYuval Mintz dma_addr_t spq_map;
189305cc5a39SYuval Mintz u16 spq_prod;
1894adfc5217SJeff Kirsher
1895adfc5217SJeff Kirsher u16 func_id; /* abs fid */
1896adfc5217SJeff Kirsher u16 pf_id;
1897adfc5217SJeff Kirsher };
1898adfc5217SJeff Kirsher
189955c11941SMerav Sicron #define for_each_cnic_queue(bp, var) \
190055c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
190155c11941SMerav Sicron (var)++) \
190255c11941SMerav Sicron if (skip_queue(bp, var)) \
190355c11941SMerav Sicron continue; \
190455c11941SMerav Sicron else
190555c11941SMerav Sicron
1906adfc5217SJeff Kirsher #define for_each_eth_queue(bp, var) \
1907adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1908adfc5217SJeff Kirsher
1909adfc5217SJeff Kirsher #define for_each_nondefault_eth_queue(bp, var) \
1910adfc5217SJeff Kirsher for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1911adfc5217SJeff Kirsher
1912adfc5217SJeff Kirsher #define for_each_queue(bp, var) \
1913adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1914adfc5217SJeff Kirsher if (skip_queue(bp, var)) \
1915adfc5217SJeff Kirsher continue; \
1916adfc5217SJeff Kirsher else
1917adfc5217SJeff Kirsher
1918adfc5217SJeff Kirsher /* Skip forwarding FP */
191955c11941SMerav Sicron #define for_each_valid_rx_queue(bp, var) \
192055c11941SMerav Sicron for ((var) = 0; \
192155c11941SMerav Sicron (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
192255c11941SMerav Sicron BNX2X_NUM_ETH_QUEUES(bp)); \
192355c11941SMerav Sicron (var)++) \
192455c11941SMerav Sicron if (skip_rx_queue(bp, var)) \
192555c11941SMerav Sicron continue; \
192655c11941SMerav Sicron else
192755c11941SMerav Sicron
192855c11941SMerav Sicron #define for_each_rx_queue_cnic(bp, var) \
192955c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
193055c11941SMerav Sicron (var)++) \
193155c11941SMerav Sicron if (skip_rx_queue(bp, var)) \
193255c11941SMerav Sicron continue; \
193355c11941SMerav Sicron else
193455c11941SMerav Sicron
1935adfc5217SJeff Kirsher #define for_each_rx_queue(bp, var) \
1936adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1937adfc5217SJeff Kirsher if (skip_rx_queue(bp, var)) \
1938adfc5217SJeff Kirsher continue; \
1939adfc5217SJeff Kirsher else
1940adfc5217SJeff Kirsher
1941adfc5217SJeff Kirsher /* Skip OOO FP */
194255c11941SMerav Sicron #define for_each_valid_tx_queue(bp, var) \
194355c11941SMerav Sicron for ((var) = 0; \
194455c11941SMerav Sicron (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
194555c11941SMerav Sicron BNX2X_NUM_ETH_QUEUES(bp)); \
194655c11941SMerav Sicron (var)++) \
194755c11941SMerav Sicron if (skip_tx_queue(bp, var)) \
194855c11941SMerav Sicron continue; \
194955c11941SMerav Sicron else
195055c11941SMerav Sicron
195155c11941SMerav Sicron #define for_each_tx_queue_cnic(bp, var) \
195255c11941SMerav Sicron for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
195355c11941SMerav Sicron (var)++) \
195455c11941SMerav Sicron if (skip_tx_queue(bp, var)) \
195555c11941SMerav Sicron continue; \
195655c11941SMerav Sicron else
195755c11941SMerav Sicron
1958adfc5217SJeff Kirsher #define for_each_tx_queue(bp, var) \
1959adfc5217SJeff Kirsher for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1960adfc5217SJeff Kirsher if (skip_tx_queue(bp, var)) \
1961adfc5217SJeff Kirsher continue; \
1962adfc5217SJeff Kirsher else
1963adfc5217SJeff Kirsher
1964adfc5217SJeff Kirsher #define for_each_nondefault_queue(bp, var) \
1965adfc5217SJeff Kirsher for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1966adfc5217SJeff Kirsher if (skip_queue(bp, var)) \
1967adfc5217SJeff Kirsher continue; \
1968adfc5217SJeff Kirsher else
1969adfc5217SJeff Kirsher
1970adfc5217SJeff Kirsher #define for_each_cos_in_tx_queue(fp, var) \
1971adfc5217SJeff Kirsher for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1972adfc5217SJeff Kirsher
1973adfc5217SJeff Kirsher /* skip rx queue
1974adfc5217SJeff Kirsher * if FCOE l2 support is disabled and this is the fcoe L2 queue
1975adfc5217SJeff Kirsher */
1976adfc5217SJeff Kirsher #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1977adfc5217SJeff Kirsher
1978adfc5217SJeff Kirsher /* skip tx queue
1979adfc5217SJeff Kirsher * if FCOE l2 support is disabled and this is the fcoe L2 queue
1980adfc5217SJeff Kirsher */
1981adfc5217SJeff Kirsher #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1982adfc5217SJeff Kirsher
1983adfc5217SJeff Kirsher #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1984adfc5217SJeff Kirsher
1985cdf711f2SSudarsana Reddy Kalluru /*self test*/
1986cdf711f2SSudarsana Reddy Kalluru int bnx2x_idle_chk(struct bnx2x *bp);
1987cdf711f2SSudarsana Reddy Kalluru
1988adfc5217SJeff Kirsher /**
1989adfc5217SJeff Kirsher * bnx2x_set_mac_one - configure a single MAC address
1990adfc5217SJeff Kirsher *
1991adfc5217SJeff Kirsher * @bp: driver handle
1992adfc5217SJeff Kirsher * @mac: MAC to configure
1993adfc5217SJeff Kirsher * @obj: MAC object handle
1994adfc5217SJeff Kirsher * @set: if 'true' add a new MAC, otherwise - delete
1995adfc5217SJeff Kirsher * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1996adfc5217SJeff Kirsher * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1997adfc5217SJeff Kirsher *
1998adfc5217SJeff Kirsher * Configures one MAC according to provided parameters or continues the
1999adfc5217SJeff Kirsher * execution of previously scheduled commands if RAMROD_CONT is set in
2000adfc5217SJeff Kirsher * ramrod_flags.
2001adfc5217SJeff Kirsher *
2002adfc5217SJeff Kirsher * Returns zero if operation has successfully completed, a positive value if the
2003adfc5217SJeff Kirsher * operation has been successfully scheduled and a negative - if a requested
2004adfc5217SJeff Kirsher * operations has failed.
2005adfc5217SJeff Kirsher */
200676660757SJakub Kicinski int bnx2x_set_mac_one(struct bnx2x *bp, const u8 *mac,
2007adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *obj, bool set,
2008adfc5217SJeff Kirsher int mac_type, unsigned long *ramrod_flags);
200905cc5a39SYuval Mintz
201005cc5a39SYuval Mintz int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
201105cc5a39SYuval Mintz struct bnx2x_vlan_mac_obj *obj, bool set,
201205cc5a39SYuval Mintz unsigned long *ramrod_flags);
201305cc5a39SYuval Mintz
2014adfc5217SJeff Kirsher /**
2015adfc5217SJeff Kirsher * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
2016adfc5217SJeff Kirsher *
2017adfc5217SJeff Kirsher * @bp: driver handle
2018adfc5217SJeff Kirsher * @mac_obj: MAC object handle
2019adfc5217SJeff Kirsher * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
2020adfc5217SJeff Kirsher * @wait_for_comp: if 'true' block until completion
2021adfc5217SJeff Kirsher *
2022adfc5217SJeff Kirsher * Deletes all MACs of the specific type (e.g. ETH, UC list).
2023adfc5217SJeff Kirsher *
2024adfc5217SJeff Kirsher * Returns zero if operation has successfully completed, a positive value if the
2025adfc5217SJeff Kirsher * operation has been successfully scheduled and a negative - if a requested
2026adfc5217SJeff Kirsher * operations has failed.
2027adfc5217SJeff Kirsher */
2028adfc5217SJeff Kirsher int bnx2x_del_all_macs(struct bnx2x *bp,
2029adfc5217SJeff Kirsher struct bnx2x_vlan_mac_obj *mac_obj,
2030adfc5217SJeff Kirsher int mac_type, bool wait_for_comp);
2031adfc5217SJeff Kirsher
2032adfc5217SJeff Kirsher /* Init Function API */
2033adfc5217SJeff Kirsher void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
2034b93288d5SAriel Elior void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2035b93288d5SAriel Elior u8 vf_valid, int fw_sb_id, int igu_sb_id);
2036adfc5217SJeff Kirsher int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
2037adfc5217SJeff Kirsher int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2038adfc5217SJeff Kirsher int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
2039adfc5217SJeff Kirsher int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2040adfc5217SJeff Kirsher void bnx2x_read_mf_cfg(struct bnx2x *bp);
2041adfc5217SJeff Kirsher
2042b56e9670SAriel Elior int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
2043adfc5217SJeff Kirsher
2044adfc5217SJeff Kirsher /* dmae */
2045adfc5217SJeff Kirsher void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
2046adfc5217SJeff Kirsher void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
2047adfc5217SJeff Kirsher u32 len32);
2048adfc5217SJeff Kirsher void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2049adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
2050adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
2051adfc5217SJeff Kirsher u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
2052adfc5217SJeff Kirsher bool with_comp, u8 comp_type);
2053adfc5217SJeff Kirsher
2054fd1fc79dSAriel Elior void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2055fd1fc79dSAriel Elior u8 src_type, u8 dst_type);
205632316a46SAriel Elior int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
205732316a46SAriel Elior u32 *comp);
2058fd1fc79dSAriel Elior
2059d16132ceSAriel Elior /* FLR related routines */
2060d16132ceSAriel Elior u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2061d16132ceSAriel Elior void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
2062d16132ceSAriel Elior int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
2063b56e9670SAriel Elior u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
2064d16132ceSAriel Elior int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
2065d16132ceSAriel Elior char *msg, u32 poll_cnt);
2066adfc5217SJeff Kirsher
2067adfc5217SJeff Kirsher void bnx2x_calc_fc_adv(struct bnx2x *bp);
2068adfc5217SJeff Kirsher int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2069adfc5217SJeff Kirsher u32 data_hi, u32 data_lo, int cmd_type);
2070adfc5217SJeff Kirsher void bnx2x_update_coalesce(struct bnx2x *bp);
2071adfc5217SJeff Kirsher int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
2072adfc5217SJeff Kirsher
2073178135c1SDmitry Kravkov bool bnx2x_port_after_undi(struct bnx2x *bp);
2074178135c1SDmitry Kravkov
reg_poll(struct bnx2x * bp,u32 reg,u32 expected,int ms,int wait)2075adfc5217SJeff Kirsher static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
2076adfc5217SJeff Kirsher int wait)
2077adfc5217SJeff Kirsher {
2078adfc5217SJeff Kirsher u32 val;
2079adfc5217SJeff Kirsher
2080adfc5217SJeff Kirsher do {
2081adfc5217SJeff Kirsher val = REG_RD(bp, reg);
2082adfc5217SJeff Kirsher if (val == expected)
2083adfc5217SJeff Kirsher break;
2084adfc5217SJeff Kirsher ms -= wait;
2085adfc5217SJeff Kirsher msleep(wait);
2086adfc5217SJeff Kirsher
2087adfc5217SJeff Kirsher } while (ms > 0);
2088adfc5217SJeff Kirsher
2089adfc5217SJeff Kirsher return val;
2090adfc5217SJeff Kirsher }
2091adfc5217SJeff Kirsher
2092b56e9670SAriel Elior void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
2093b56e9670SAriel Elior bool is_pf);
2094b56e9670SAriel Elior
2095adfc5217SJeff Kirsher #define BNX2X_ILT_ZALLOC(x, y, size) \
209607a85fe1SLuis Chamberlain x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL)
2097adfc5217SJeff Kirsher
2098adfc5217SJeff Kirsher #define BNX2X_ILT_FREE(x, y, size) \
2099adfc5217SJeff Kirsher do { \
2100adfc5217SJeff Kirsher if (x) { \
2101adfc5217SJeff Kirsher dma_free_coherent(&bp->pdev->dev, size, x, y); \
2102adfc5217SJeff Kirsher x = NULL; \
2103adfc5217SJeff Kirsher y = 0; \
2104adfc5217SJeff Kirsher } \
2105adfc5217SJeff Kirsher } while (0)
2106adfc5217SJeff Kirsher
2107adfc5217SJeff Kirsher #define ILOG2(x) (ilog2((x)))
2108adfc5217SJeff Kirsher
2109adfc5217SJeff Kirsher #define ILT_NUM_PAGE_ENTRIES (3072)
2110adfc5217SJeff Kirsher /* In 57710/11 we use whole table since we have 8 func
2111adfc5217SJeff Kirsher * In 57712 we have only 4 func, but use same size per func, then only half of
2112adfc5217SJeff Kirsher * the table in use
2113adfc5217SJeff Kirsher */
2114adfc5217SJeff Kirsher #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
2115adfc5217SJeff Kirsher
2116adfc5217SJeff Kirsher #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
2117adfc5217SJeff Kirsher /*
2118adfc5217SJeff Kirsher * the phys address is shifted right 12 bits and has an added
2119adfc5217SJeff Kirsher * 1=valid bit added to the 53rd bit
2120adfc5217SJeff Kirsher * then since this is a wide register(TM)
2121adfc5217SJeff Kirsher * we split it into two 32 bit writes
2122adfc5217SJeff Kirsher */
2123adfc5217SJeff Kirsher #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
2124adfc5217SJeff Kirsher #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
2125adfc5217SJeff Kirsher
2126adfc5217SJeff Kirsher /* load/unload mode */
2127adfc5217SJeff Kirsher #define LOAD_NORMAL 0
2128adfc5217SJeff Kirsher #define LOAD_OPEN 1
2129adfc5217SJeff Kirsher #define LOAD_DIAG 2
21308970b2e4SMerav Sicron #define LOAD_LOOPBACK_EXT 3
2131adfc5217SJeff Kirsher #define UNLOAD_NORMAL 0
2132adfc5217SJeff Kirsher #define UNLOAD_CLOSE 1
2133adfc5217SJeff Kirsher #define UNLOAD_RECOVERY 2
2134adfc5217SJeff Kirsher
2135adfc5217SJeff Kirsher /* DMAE command defines */
2136adfc5217SJeff Kirsher #define DMAE_TIMEOUT -1
2137adfc5217SJeff Kirsher #define DMAE_PCI_ERROR -2 /* E2 and onward */
2138adfc5217SJeff Kirsher #define DMAE_NOT_RDY -3
2139adfc5217SJeff Kirsher #define DMAE_PCI_ERR_FLAG 0x80000000
2140adfc5217SJeff Kirsher
2141adfc5217SJeff Kirsher #define DMAE_SRC_PCI 0
2142adfc5217SJeff Kirsher #define DMAE_SRC_GRC 1
2143adfc5217SJeff Kirsher
2144adfc5217SJeff Kirsher #define DMAE_DST_NONE 0
2145adfc5217SJeff Kirsher #define DMAE_DST_PCI 1
2146adfc5217SJeff Kirsher #define DMAE_DST_GRC 2
2147adfc5217SJeff Kirsher
2148adfc5217SJeff Kirsher #define DMAE_COMP_PCI 0
2149adfc5217SJeff Kirsher #define DMAE_COMP_GRC 1
2150adfc5217SJeff Kirsher
2151adfc5217SJeff Kirsher /* E2 and onward - PCI error handling in the completion */
2152adfc5217SJeff Kirsher
2153adfc5217SJeff Kirsher #define DMAE_COMP_REGULAR 0
2154adfc5217SJeff Kirsher #define DMAE_COM_SET_ERR 1
2155adfc5217SJeff Kirsher
2156adfc5217SJeff Kirsher #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
2157adfc5217SJeff Kirsher DMAE_COMMAND_SRC_SHIFT)
2158adfc5217SJeff Kirsher #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
2159adfc5217SJeff Kirsher DMAE_COMMAND_SRC_SHIFT)
2160adfc5217SJeff Kirsher
2161adfc5217SJeff Kirsher #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
2162adfc5217SJeff Kirsher DMAE_COMMAND_DST_SHIFT)
2163adfc5217SJeff Kirsher #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
2164adfc5217SJeff Kirsher DMAE_COMMAND_DST_SHIFT)
2165adfc5217SJeff Kirsher
2166adfc5217SJeff Kirsher #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
2167adfc5217SJeff Kirsher DMAE_COMMAND_C_DST_SHIFT)
2168adfc5217SJeff Kirsher #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
2169adfc5217SJeff Kirsher DMAE_COMMAND_C_DST_SHIFT)
2170adfc5217SJeff Kirsher
2171adfc5217SJeff Kirsher #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
2172adfc5217SJeff Kirsher
2173adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2174adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2175adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2176adfc5217SJeff Kirsher #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2177adfc5217SJeff Kirsher
2178adfc5217SJeff Kirsher #define DMAE_CMD_PORT_0 0
2179adfc5217SJeff Kirsher #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2180adfc5217SJeff Kirsher
2181adfc5217SJeff Kirsher #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
2182adfc5217SJeff Kirsher #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
2183adfc5217SJeff Kirsher #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
2184adfc5217SJeff Kirsher
2185adfc5217SJeff Kirsher #define DMAE_SRC_PF 0
2186adfc5217SJeff Kirsher #define DMAE_SRC_VF 1
2187adfc5217SJeff Kirsher
2188adfc5217SJeff Kirsher #define DMAE_DST_PF 0
2189adfc5217SJeff Kirsher #define DMAE_DST_VF 1
2190adfc5217SJeff Kirsher
2191adfc5217SJeff Kirsher #define DMAE_C_SRC 0
2192adfc5217SJeff Kirsher #define DMAE_C_DST 1
2193adfc5217SJeff Kirsher
2194adfc5217SJeff Kirsher #define DMAE_LEN32_RD_MAX 0x80
2195adfc5217SJeff Kirsher #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2196adfc5217SJeff Kirsher
2197adfc5217SJeff Kirsher #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
219816a5fd92SYuval Mintz * indicates error
219916a5fd92SYuval Mintz */
2200adfc5217SJeff Kirsher
2201adfc5217SJeff Kirsher #define MAX_DMAE_C_PER_PORT 8
2202adfc5217SJeff Kirsher #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
22038decf868SDavid S. Miller BP_VN(bp))
2204adfc5217SJeff Kirsher #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2205adfc5217SJeff Kirsher E1HVN_MAX)
2206adfc5217SJeff Kirsher
220777e461d1SSudarsana Reddy Kalluru /* Following is the DMAE channel number allocation for the clients.
220877e461d1SSudarsana Reddy Kalluru * MFW: OCBB/OCSD implementations use DMAE channels 14/15 respectively.
220977e461d1SSudarsana Reddy Kalluru * Driver: 0-3 and 8-11 (for PF dmae operations)
221077e461d1SSudarsana Reddy Kalluru * 4 and 12 (for stats requests)
221177e461d1SSudarsana Reddy Kalluru */
221277e461d1SSudarsana Reddy Kalluru #define BNX2X_FW_DMAE_C 13 /* Channel for FW DMAE operations */
221377e461d1SSudarsana Reddy Kalluru
2214adfc5217SJeff Kirsher /* PCIE link and speed */
2215adfc5217SJeff Kirsher #define PCICFG_LINK_WIDTH 0x1f00000
2216adfc5217SJeff Kirsher #define PCICFG_LINK_WIDTH_SHIFT 20
2217adfc5217SJeff Kirsher #define PCICFG_LINK_SPEED 0xf0000
2218adfc5217SJeff Kirsher #define PCICFG_LINK_SPEED_SHIFT 16
2219adfc5217SJeff Kirsher
2220cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS_SF 7
2221cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS_MF 3
2222cf2c1df6SMerav Sicron #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
222375543741SYuval Mintz IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
2224adfc5217SJeff Kirsher
2225adfc5217SJeff Kirsher #define BNX2X_PHY_LOOPBACK 0
2226adfc5217SJeff Kirsher #define BNX2X_MAC_LOOPBACK 1
22278970b2e4SMerav Sicron #define BNX2X_EXT_LOOPBACK 2
2228adfc5217SJeff Kirsher #define BNX2X_PHY_LOOPBACK_FAILED 1
2229adfc5217SJeff Kirsher #define BNX2X_MAC_LOOPBACK_FAILED 2
22308970b2e4SMerav Sicron #define BNX2X_EXT_LOOPBACK_FAILED 3
2231adfc5217SJeff Kirsher #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2232adfc5217SJeff Kirsher BNX2X_PHY_LOOPBACK_FAILED)
2233adfc5217SJeff Kirsher
2234adfc5217SJeff Kirsher #define STROM_ASSERT_ARRAY_SIZE 50
2235adfc5217SJeff Kirsher
2236adfc5217SJeff Kirsher /* must be used on a CID before placing it on a HW ring */
2237adfc5217SJeff Kirsher #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
22388decf868SDavid S. Miller (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2239adfc5217SJeff Kirsher (x))
2240adfc5217SJeff Kirsher
2241adfc5217SJeff Kirsher #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2242adfc5217SJeff Kirsher #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2243adfc5217SJeff Kirsher
2244adfc5217SJeff Kirsher #define BNX2X_BTR 4
2245adfc5217SJeff Kirsher #define MAX_SPQ_PENDING 8
2246adfc5217SJeff Kirsher
2247adfc5217SJeff Kirsher /* CMNG constants, as derived from system spec calculations */
2248adfc5217SJeff Kirsher /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2249adfc5217SJeff Kirsher #define DEF_MIN_RATE 100
2250adfc5217SJeff Kirsher /* resolution of the rate shaping timer - 400 usec */
2251adfc5217SJeff Kirsher #define RS_PERIODIC_TIMEOUT_USEC 400
2252adfc5217SJeff Kirsher /* number of bytes in single QM arbitration cycle -
2253adfc5217SJeff Kirsher * coefficient for calculating the fairness timer */
2254adfc5217SJeff Kirsher #define QM_ARB_BYTES 160000
2255adfc5217SJeff Kirsher /* resolution of Min algorithm 1:100 */
2256adfc5217SJeff Kirsher #define MIN_RES 100
2257adfc5217SJeff Kirsher /* how many bytes above threshold for the minimal credit of Min algorithm*/
2258adfc5217SJeff Kirsher #define MIN_ABOVE_THRESH 32768
2259adfc5217SJeff Kirsher /* Fairness algorithm integration time coefficient -
2260adfc5217SJeff Kirsher * for calculating the actual Tfair */
2261adfc5217SJeff Kirsher #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2262adfc5217SJeff Kirsher /* Memory of fairness algorithm . 2 cycles */
2263adfc5217SJeff Kirsher #define FAIR_MEM 2
2264adfc5217SJeff Kirsher
2265adfc5217SJeff Kirsher #define ATTN_NIG_FOR_FUNC (1L << 8)
2266adfc5217SJeff Kirsher #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2267adfc5217SJeff Kirsher #define GPIO_2_FUNC (1L << 10)
2268adfc5217SJeff Kirsher #define GPIO_3_FUNC (1L << 11)
2269adfc5217SJeff Kirsher #define GPIO_4_FUNC (1L << 12)
2270adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_1 (1L << 13)
2271adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_2 (1L << 14)
2272adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_3 (1L << 15)
2273adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_4 (1L << 13)
2274adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_5 (1L << 14)
2275adfc5217SJeff Kirsher #define ATTN_GENERAL_ATTN_6 (1L << 15)
2276adfc5217SJeff Kirsher
2277adfc5217SJeff Kirsher #define ATTN_HARD_WIRED_MASK 0xff00
2278adfc5217SJeff Kirsher #define ATTENTION_ID 4
2279adfc5217SJeff Kirsher
22802e98ffc2SDmitry Kravkov #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \
22813521b419SYuval Mintz IS_MF_FCOE_AFEX(bp))
2282adfc5217SJeff Kirsher
2283adfc5217SJeff Kirsher /* stuff added to make the code fit 80Col */
2284adfc5217SJeff Kirsher
2285adfc5217SJeff Kirsher #define BNX2X_PMF_LINK_ASSERT \
2286adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2287adfc5217SJeff Kirsher
2288adfc5217SJeff Kirsher #define BNX2X_MC_ASSERT_BITS \
2289adfc5217SJeff Kirsher (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2290adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2291adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2292adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2293adfc5217SJeff Kirsher
2294adfc5217SJeff Kirsher #define BNX2X_MCP_ASSERT \
2295adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2296adfc5217SJeff Kirsher
2297adfc5217SJeff Kirsher #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2298adfc5217SJeff Kirsher #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2299adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2300adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2301adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2302adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2303adfc5217SJeff Kirsher GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2304adfc5217SJeff Kirsher
2305a8919661SColin Ian King #define HW_INTERRUPT_ASSERT_SET_0 \
2306adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2307adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2308adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2309c14a09b7SDmitry Kravkov AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2310adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2311adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2312adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2313adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2314adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2315adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2316adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2317adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2318a8919661SColin Ian King #define HW_INTERRUPT_ASSERT_SET_1 \
2319adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2320adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2321adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2322adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2323adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2324adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2325adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2326adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2327adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2328adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2329adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2330adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2331adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2332adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2333adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2334adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2335adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2336adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2337adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2338adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2339adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2340adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2341adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2342adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2343adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2344adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2345adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2346a8919661SColin Ian King #define HW_INTERRUPT_ASSERT_SET_2 \
2347adfc5217SJeff Kirsher (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2348adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2349adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2350adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2351adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2352adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2353adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2354adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2355adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2356adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2357adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2358adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2359adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2360adfc5217SJeff Kirsher
2361ad6afbe9SManish Chopra #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \
2362ad6afbe9SManish Chopra (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2363adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2364ad6afbe9SManish Chopra AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
2365ad6afbe9SManish Chopra
2366ad6afbe9SManish Chopra #define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \
2367adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2368adfc5217SJeff Kirsher
2369adfc5217SJeff Kirsher #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2370adfc5217SJeff Kirsher AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2371adfc5217SJeff Kirsher
2372adfc5217SJeff Kirsher #define MULTI_MASK 0x7f
2373adfc5217SJeff Kirsher
2374adfc5217SJeff Kirsher #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2375adfc5217SJeff Kirsher #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2376adfc5217SJeff Kirsher #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2377adfc5217SJeff Kirsher #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2378adfc5217SJeff Kirsher
2379adfc5217SJeff Kirsher #define DEF_USB_IGU_INDEX_OFF \
2380adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_u, igu_index)
2381adfc5217SJeff Kirsher #define DEF_CSB_IGU_INDEX_OFF \
2382adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_c, igu_index)
2383adfc5217SJeff Kirsher #define DEF_XSB_IGU_INDEX_OFF \
2384adfc5217SJeff Kirsher offsetof(struct xstorm_def_status_block, igu_index)
2385adfc5217SJeff Kirsher #define DEF_TSB_IGU_INDEX_OFF \
2386adfc5217SJeff Kirsher offsetof(struct tstorm_def_status_block, igu_index)
2387adfc5217SJeff Kirsher
2388adfc5217SJeff Kirsher #define DEF_USB_SEGMENT_OFF \
2389adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_u, segment)
2390adfc5217SJeff Kirsher #define DEF_CSB_SEGMENT_OFF \
2391adfc5217SJeff Kirsher offsetof(struct cstorm_def_status_block_c, segment)
2392adfc5217SJeff Kirsher #define DEF_XSB_SEGMENT_OFF \
2393adfc5217SJeff Kirsher offsetof(struct xstorm_def_status_block, segment)
2394adfc5217SJeff Kirsher #define DEF_TSB_SEGMENT_OFF \
2395adfc5217SJeff Kirsher offsetof(struct tstorm_def_status_block, segment)
2396adfc5217SJeff Kirsher
2397adfc5217SJeff Kirsher #define BNX2X_SP_DSB_INDEX \
2398adfc5217SJeff Kirsher (&bp->def_status_blk->sp_sb.\
2399adfc5217SJeff Kirsher index_values[HC_SP_INDEX_ETH_DEF_CONS])
2400adfc5217SJeff Kirsher
2401adfc5217SJeff Kirsher #define CAM_IS_INVALID(x) \
2402adfc5217SJeff Kirsher (GET_FLAG(x.flags, \
2403adfc5217SJeff Kirsher MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2404adfc5217SJeff Kirsher (T_ETH_MAC_COMMAND_INVALIDATE))
2405adfc5217SJeff Kirsher
2406adfc5217SJeff Kirsher /* Number of u32 elements in MC hash array */
2407adfc5217SJeff Kirsher #define MC_HASH_SIZE 8
2408adfc5217SJeff Kirsher #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2409adfc5217SJeff Kirsher TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2410adfc5217SJeff Kirsher
2411adfc5217SJeff Kirsher #ifndef PXP2_REG_PXP2_INT_STS
2412adfc5217SJeff Kirsher #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2413adfc5217SJeff Kirsher #endif
2414adfc5217SJeff Kirsher
2415adfc5217SJeff Kirsher #ifndef ETH_MAX_RX_CLIENTS_E2
2416adfc5217SJeff Kirsher #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2417adfc5217SJeff Kirsher #endif
2418adfc5217SJeff Kirsher
2419adfc5217SJeff Kirsher #define VENDOR_ID_LEN 4
2420adfc5217SJeff Kirsher
2421be1f1ffaSAriel Elior #define VF_ACQUIRE_THRESH 3
2422be1f1ffaSAriel Elior #define VF_ACQUIRE_MAC_FILTERS 1
2423be1f1ffaSAriel Elior #define VF_ACQUIRE_MC_FILTERS 10
242405cc5a39SYuval Mintz #define VF_ACQUIRE_VLAN_FILTERS 2 /* VLAN0 + 'real' VLAN */
2425be1f1ffaSAriel Elior
2426be1f1ffaSAriel Elior #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2427be1f1ffaSAriel Elior (!((me_reg) & ME_REG_VF_ERR)))
242891ebb929SYuval Mintz int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err);
242991ebb929SYuval Mintz
2430adfc5217SJeff Kirsher /* Congestion management fairness mode */
2431adfc5217SJeff Kirsher #define CMNG_FNS_NONE 0
2432adfc5217SJeff Kirsher #define CMNG_FNS_MINMAX 1
2433adfc5217SJeff Kirsher
2434adfc5217SJeff Kirsher #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2435adfc5217SJeff Kirsher #define HC_SEG_ACCESS_ATTN 4
2436adfc5217SJeff Kirsher #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2437adfc5217SJeff Kirsher
2438005a07baSAriel Elior void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2439adfc5217SJeff Kirsher void bnx2x_notify_link_changed(struct bnx2x *bp);
2440614c76dfSDmitry Kravkov
24419e62e912SDmitry Kravkov #define BNX2X_MF_SD_PROTOCOL(bp) \
2442614c76dfSDmitry Kravkov ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2443614c76dfSDmitry Kravkov
24449e62e912SDmitry Kravkov #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
24459e62e912SDmitry Kravkov (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2446614c76dfSDmitry Kravkov
24479e62e912SDmitry Kravkov #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
24489e62e912SDmitry Kravkov (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
24499e62e912SDmitry Kravkov
24509e62e912SDmitry Kravkov #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
24519e62e912SDmitry Kravkov #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
24522e98ffc2SDmitry Kravkov #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp))
24539e62e912SDmitry Kravkov
24542e98ffc2SDmitry Kravkov #define IS_MF_ISCSI_ONLY(bp) (IS_MF_ISCSI_SD(bp) || IS_MF_ISCSI_SI(bp))
24552e98ffc2SDmitry Kravkov
24562e98ffc2SDmitry Kravkov #define BNX2X_MF_EXT_PROTOCOL_MASK \
24572e98ffc2SDmitry Kravkov (MACP_FUNC_CFG_FLAGS_ETHERNET | \
24582e98ffc2SDmitry Kravkov MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD | \
2459a3348722SBarak Witkowski MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2460a3348722SBarak Witkowski
24612e98ffc2SDmitry Kravkov #define BNX2X_MF_EXT_PROT(bp) ((bp)->mf_ext_config & \
24622e98ffc2SDmitry Kravkov BNX2X_MF_EXT_PROTOCOL_MASK)
24632e98ffc2SDmitry Kravkov
24642e98ffc2SDmitry Kravkov #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) \
24652e98ffc2SDmitry Kravkov (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
24662e98ffc2SDmitry Kravkov
24672e98ffc2SDmitry Kravkov #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) \
24682e98ffc2SDmitry Kravkov (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
24692e98ffc2SDmitry Kravkov
24702e98ffc2SDmitry Kravkov #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) \
24712e98ffc2SDmitry Kravkov (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD)
24722e98ffc2SDmitry Kravkov
24732e98ffc2SDmitry Kravkov #define IS_MF_FCOE_AFEX(bp) \
24742e98ffc2SDmitry Kravkov (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))
24752e98ffc2SDmitry Kravkov
24762e98ffc2SDmitry Kravkov #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) \
24772e98ffc2SDmitry Kravkov (IS_MF_SD(bp) && \
24789e62e912SDmitry Kravkov (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
24799e62e912SDmitry Kravkov BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2480614c76dfSDmitry Kravkov
24812e98ffc2SDmitry Kravkov #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) \
24822e98ffc2SDmitry Kravkov (IS_MF_SI(bp) && \
24832e98ffc2SDmitry Kravkov (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \
24842e98ffc2SDmitry Kravkov BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)))
24852e98ffc2SDmitry Kravkov
24862e98ffc2SDmitry Kravkov #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) \
24872e98ffc2SDmitry Kravkov (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) || \
24882e98ffc2SDmitry Kravkov IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp))
24892e98ffc2SDmitry Kravkov
2490da3cc2daSYuval Mintz /* Determines whether BW configuration arrives in 100Mb units or in
2491da3cc2daSYuval Mintz * percentages from actual physical link speed.
2492da3cc2daSYuval Mintz */
2493da3cc2daSYuval Mintz #define IS_MF_PERCENT_BW(bp) (IS_MF_SI(bp) || IS_MF_UFP(bp) || IS_MF_BD(bp))
24942e98ffc2SDmitry Kravkov
24952de67439SYuval Mintz #define SET_FLAG(value, mask, flag) \
24962de67439SYuval Mintz do {\
24972de67439SYuval Mintz (value) &= ~(mask);\
24982de67439SYuval Mintz (value) |= ((flag) << (mask##_SHIFT));\
24992de67439SYuval Mintz } while (0)
25002de67439SYuval Mintz
25012de67439SYuval Mintz #define GET_FLAG(value, mask) \
25022de67439SYuval Mintz (((value) & (mask)) >> (mask##_SHIFT))
25032de67439SYuval Mintz
25042de67439SYuval Mintz #define GET_FIELD(value, fname) \
25052de67439SYuval Mintz (((value) & (fname##_MASK)) >> (fname##_SHIFT))
25062de67439SYuval Mintz
250755c11941SMerav Sicron enum {
250855c11941SMerav Sicron SWITCH_UPDATE,
250955c11941SMerav Sicron AFEX_UPDATE,
251055c11941SMerav Sicron };
251155c11941SMerav Sicron
251255c11941SMerav Sicron #define NUM_MACS 8
2513a3348722SBarak Witkowski
2514568e2426SDmitry Kravkov void bnx2x_set_local_cmng(struct bnx2x *bp);
25151a6974b2SYuval Mintz
251642f8277fSYuval Mintz void bnx2x_update_mng_version(struct bnx2x *bp);
251742f8277fSYuval Mintz
2518c48f350fSYuval Mintz void bnx2x_update_mfw_dump(struct bnx2x *bp);
2519c48f350fSYuval Mintz
25201a6974b2SYuval Mintz #define MCPR_SCRATCH_BASE(bp) \
25211a6974b2SYuval Mintz (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
25221a6974b2SYuval Mintz
2523e848582cSDmitry Kravkov #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX))
2524e848582cSDmitry Kravkov
2525eeed018cSMichal Kalderon void bnx2x_init_ptp(struct bnx2x *bp);
2526eeed018cSMichal Kalderon int bnx2x_configure_ptp_filters(struct bnx2x *bp);
2527eeed018cSMichal Kalderon void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb);
252807f12622SSudarsana Reddy Kalluru void bnx2x_register_phc(struct bnx2x *bp);
2529eeed018cSMichal Kalderon
2530eeed018cSMichal Kalderon #define BNX2X_MAX_PHC_DRIFT 31000000
2531eeed018cSMichal Kalderon #define BNX2X_PTP_TX_TIMEOUT
2532eeed018cSMichal Kalderon
253305cc5a39SYuval Mintz /* Re-configure all previously configured vlan filters.
253405cc5a39SYuval Mintz * Meant for implicit re-load flows.
253505cc5a39SYuval Mintz */
253605cc5a39SYuval Mintz int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp);
2537adfc5217SJeff Kirsher #endif /* bnx2x.h */
2538