1adfc5217SJeff Kirsher /* bnx2.c: Broadcom NX2 network driver. 2adfc5217SJeff Kirsher * 3adfc5217SJeff Kirsher * Copyright (c) 2004-2011 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7adfc5217SJeff Kirsher * the Free Software Foundation. 8adfc5217SJeff Kirsher * 9adfc5217SJeff Kirsher * Written by: Michael Chan (mchan@broadcom.com) 10adfc5217SJeff Kirsher */ 11adfc5217SJeff Kirsher 12adfc5217SJeff Kirsher #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 13adfc5217SJeff Kirsher 14adfc5217SJeff Kirsher #include <linux/module.h> 15adfc5217SJeff Kirsher #include <linux/moduleparam.h> 16adfc5217SJeff Kirsher 17adfc5217SJeff Kirsher #include <linux/kernel.h> 18adfc5217SJeff Kirsher #include <linux/timer.h> 19adfc5217SJeff Kirsher #include <linux/errno.h> 20adfc5217SJeff Kirsher #include <linux/ioport.h> 21adfc5217SJeff Kirsher #include <linux/slab.h> 22adfc5217SJeff Kirsher #include <linux/vmalloc.h> 23adfc5217SJeff Kirsher #include <linux/interrupt.h> 24adfc5217SJeff Kirsher #include <linux/pci.h> 25adfc5217SJeff Kirsher #include <linux/init.h> 26adfc5217SJeff Kirsher #include <linux/netdevice.h> 27adfc5217SJeff Kirsher #include <linux/etherdevice.h> 28adfc5217SJeff Kirsher #include <linux/skbuff.h> 29adfc5217SJeff Kirsher #include <linux/dma-mapping.h> 30adfc5217SJeff Kirsher #include <linux/bitops.h> 31adfc5217SJeff Kirsher #include <asm/io.h> 32adfc5217SJeff Kirsher #include <asm/irq.h> 33adfc5217SJeff Kirsher #include <linux/delay.h> 34adfc5217SJeff Kirsher #include <asm/byteorder.h> 35adfc5217SJeff Kirsher #include <asm/page.h> 36adfc5217SJeff Kirsher #include <linux/time.h> 37adfc5217SJeff Kirsher #include <linux/ethtool.h> 38adfc5217SJeff Kirsher #include <linux/mii.h> 3901789349SJiri Pirko #include <linux/if.h> 40adfc5217SJeff Kirsher #include <linux/if_vlan.h> 41adfc5217SJeff Kirsher #include <net/ip.h> 42adfc5217SJeff Kirsher #include <net/tcp.h> 43adfc5217SJeff Kirsher #include <net/checksum.h> 44adfc5217SJeff Kirsher #include <linux/workqueue.h> 45adfc5217SJeff Kirsher #include <linux/crc32.h> 46adfc5217SJeff Kirsher #include <linux/prefetch.h> 47adfc5217SJeff Kirsher #include <linux/cache.h> 48adfc5217SJeff Kirsher #include <linux/firmware.h> 49adfc5217SJeff Kirsher #include <linux/log2.h> 50adfc5217SJeff Kirsher #include <linux/aer.h> 51adfc5217SJeff Kirsher 52adfc5217SJeff Kirsher #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) 53adfc5217SJeff Kirsher #define BCM_CNIC 1 54adfc5217SJeff Kirsher #include "cnic_if.h" 55adfc5217SJeff Kirsher #endif 56adfc5217SJeff Kirsher #include "bnx2.h" 57adfc5217SJeff Kirsher #include "bnx2_fw.h" 58adfc5217SJeff Kirsher 59adfc5217SJeff Kirsher #define DRV_MODULE_NAME "bnx2" 60c2c20ef4SMichael Chan #define DRV_MODULE_VERSION "2.2.1" 61c2c20ef4SMichael Chan #define DRV_MODULE_RELDATE "Dec 18, 2011" 62c2c20ef4SMichael Chan #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw" 63adfc5217SJeff Kirsher #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw" 64c2c20ef4SMichael Chan #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw" 65adfc5217SJeff Kirsher #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw" 66adfc5217SJeff Kirsher #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw" 67adfc5217SJeff Kirsher 68adfc5217SJeff Kirsher #define RUN_AT(x) (jiffies + (x)) 69adfc5217SJeff Kirsher 70adfc5217SJeff Kirsher /* Time in jiffies before concluding the transmitter is hung. */ 71adfc5217SJeff Kirsher #define TX_TIMEOUT (5*HZ) 72adfc5217SJeff Kirsher 73adfc5217SJeff Kirsher static char version[] __devinitdata = 74adfc5217SJeff Kirsher "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 75adfc5217SJeff Kirsher 76adfc5217SJeff Kirsher MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); 77adfc5217SJeff Kirsher MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver"); 78adfc5217SJeff Kirsher MODULE_LICENSE("GPL"); 79adfc5217SJeff Kirsher MODULE_VERSION(DRV_MODULE_VERSION); 80adfc5217SJeff Kirsher MODULE_FIRMWARE(FW_MIPS_FILE_06); 81adfc5217SJeff Kirsher MODULE_FIRMWARE(FW_RV2P_FILE_06); 82adfc5217SJeff Kirsher MODULE_FIRMWARE(FW_MIPS_FILE_09); 83adfc5217SJeff Kirsher MODULE_FIRMWARE(FW_RV2P_FILE_09); 84adfc5217SJeff Kirsher MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax); 85adfc5217SJeff Kirsher 86adfc5217SJeff Kirsher static int disable_msi = 0; 87adfc5217SJeff Kirsher 88adfc5217SJeff Kirsher module_param(disable_msi, int, 0); 89adfc5217SJeff Kirsher MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 90adfc5217SJeff Kirsher 91adfc5217SJeff Kirsher typedef enum { 92adfc5217SJeff Kirsher BCM5706 = 0, 93adfc5217SJeff Kirsher NC370T, 94adfc5217SJeff Kirsher NC370I, 95adfc5217SJeff Kirsher BCM5706S, 96adfc5217SJeff Kirsher NC370F, 97adfc5217SJeff Kirsher BCM5708, 98adfc5217SJeff Kirsher BCM5708S, 99adfc5217SJeff Kirsher BCM5709, 100adfc5217SJeff Kirsher BCM5709S, 101adfc5217SJeff Kirsher BCM5716, 102adfc5217SJeff Kirsher BCM5716S, 103adfc5217SJeff Kirsher } board_t; 104adfc5217SJeff Kirsher 105adfc5217SJeff Kirsher /* indexed by board_t, above */ 106adfc5217SJeff Kirsher static struct { 107adfc5217SJeff Kirsher char *name; 108adfc5217SJeff Kirsher } board_info[] __devinitdata = { 109adfc5217SJeff Kirsher { "Broadcom NetXtreme II BCM5706 1000Base-T" }, 110adfc5217SJeff Kirsher { "HP NC370T Multifunction Gigabit Server Adapter" }, 111adfc5217SJeff Kirsher { "HP NC370i Multifunction Gigabit Server Adapter" }, 112adfc5217SJeff Kirsher { "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 113adfc5217SJeff Kirsher { "HP NC370F Multifunction Gigabit Server Adapter" }, 114adfc5217SJeff Kirsher { "Broadcom NetXtreme II BCM5708 1000Base-T" }, 115adfc5217SJeff Kirsher { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 116adfc5217SJeff Kirsher { "Broadcom NetXtreme II BCM5709 1000Base-T" }, 117adfc5217SJeff Kirsher { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 118adfc5217SJeff Kirsher { "Broadcom NetXtreme II BCM5716 1000Base-T" }, 119adfc5217SJeff Kirsher { "Broadcom NetXtreme II BCM5716 1000Base-SX" }, 120adfc5217SJeff Kirsher }; 121adfc5217SJeff Kirsher 122adfc5217SJeff Kirsher static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = { 123adfc5217SJeff Kirsher { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, 124adfc5217SJeff Kirsher PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T }, 125adfc5217SJeff Kirsher { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, 126adfc5217SJeff Kirsher PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I }, 127adfc5217SJeff Kirsher { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, 128adfc5217SJeff Kirsher PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 }, 129adfc5217SJeff Kirsher { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708, 130adfc5217SJeff Kirsher PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 }, 131adfc5217SJeff Kirsher { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, 132adfc5217SJeff Kirsher PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F }, 133adfc5217SJeff Kirsher { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, 134adfc5217SJeff Kirsher PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S }, 135adfc5217SJeff Kirsher { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S, 136adfc5217SJeff Kirsher PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S }, 137adfc5217SJeff Kirsher { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709, 138adfc5217SJeff Kirsher PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 }, 139adfc5217SJeff Kirsher { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S, 140adfc5217SJeff Kirsher PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S }, 141adfc5217SJeff Kirsher { PCI_VENDOR_ID_BROADCOM, 0x163b, 142adfc5217SJeff Kirsher PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 }, 143adfc5217SJeff Kirsher { PCI_VENDOR_ID_BROADCOM, 0x163c, 144adfc5217SJeff Kirsher PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S }, 145adfc5217SJeff Kirsher { 0, } 146adfc5217SJeff Kirsher }; 147adfc5217SJeff Kirsher 148adfc5217SJeff Kirsher static const struct flash_spec flash_table[] = 149adfc5217SJeff Kirsher { 150adfc5217SJeff Kirsher #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE) 151adfc5217SJeff Kirsher #define NONBUFFERED_FLAGS (BNX2_NV_WREN) 152adfc5217SJeff Kirsher /* Slow EEPROM */ 153adfc5217SJeff Kirsher {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 154adfc5217SJeff Kirsher BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 155adfc5217SJeff Kirsher SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 156adfc5217SJeff Kirsher "EEPROM - slow"}, 157adfc5217SJeff Kirsher /* Expansion entry 0001 */ 158adfc5217SJeff Kirsher {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 159adfc5217SJeff Kirsher NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 160adfc5217SJeff Kirsher SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 161adfc5217SJeff Kirsher "Entry 0001"}, 162adfc5217SJeff Kirsher /* Saifun SA25F010 (non-buffered flash) */ 163adfc5217SJeff Kirsher /* strap, cfg1, & write1 need updates */ 164adfc5217SJeff Kirsher {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 165adfc5217SJeff Kirsher NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 166adfc5217SJeff Kirsher SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 167adfc5217SJeff Kirsher "Non-buffered flash (128kB)"}, 168adfc5217SJeff Kirsher /* Saifun SA25F020 (non-buffered flash) */ 169adfc5217SJeff Kirsher /* strap, cfg1, & write1 need updates */ 170adfc5217SJeff Kirsher {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 171adfc5217SJeff Kirsher NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 172adfc5217SJeff Kirsher SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 173adfc5217SJeff Kirsher "Non-buffered flash (256kB)"}, 174adfc5217SJeff Kirsher /* Expansion entry 0100 */ 175adfc5217SJeff Kirsher {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 176adfc5217SJeff Kirsher NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 177adfc5217SJeff Kirsher SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 178adfc5217SJeff Kirsher "Entry 0100"}, 179adfc5217SJeff Kirsher /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 180adfc5217SJeff Kirsher {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 181adfc5217SJeff Kirsher NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 182adfc5217SJeff Kirsher ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 183adfc5217SJeff Kirsher "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 184adfc5217SJeff Kirsher /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 185adfc5217SJeff Kirsher {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 186adfc5217SJeff Kirsher NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 187adfc5217SJeff Kirsher ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 188adfc5217SJeff Kirsher "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 189adfc5217SJeff Kirsher /* Saifun SA25F005 (non-buffered flash) */ 190adfc5217SJeff Kirsher /* strap, cfg1, & write1 need updates */ 191adfc5217SJeff Kirsher {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 192adfc5217SJeff Kirsher NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 193adfc5217SJeff Kirsher SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 194adfc5217SJeff Kirsher "Non-buffered flash (64kB)"}, 195adfc5217SJeff Kirsher /* Fast EEPROM */ 196adfc5217SJeff Kirsher {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 197adfc5217SJeff Kirsher BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 198adfc5217SJeff Kirsher SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 199adfc5217SJeff Kirsher "EEPROM - fast"}, 200adfc5217SJeff Kirsher /* Expansion entry 1001 */ 201adfc5217SJeff Kirsher {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 202adfc5217SJeff Kirsher NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 203adfc5217SJeff Kirsher SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 204adfc5217SJeff Kirsher "Entry 1001"}, 205adfc5217SJeff Kirsher /* Expansion entry 1010 */ 206adfc5217SJeff Kirsher {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 207adfc5217SJeff Kirsher NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 208adfc5217SJeff Kirsher SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 209adfc5217SJeff Kirsher "Entry 1010"}, 210adfc5217SJeff Kirsher /* ATMEL AT45DB011B (buffered flash) */ 211adfc5217SJeff Kirsher {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 212adfc5217SJeff Kirsher BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 213adfc5217SJeff Kirsher BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 214adfc5217SJeff Kirsher "Buffered flash (128kB)"}, 215adfc5217SJeff Kirsher /* Expansion entry 1100 */ 216adfc5217SJeff Kirsher {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 217adfc5217SJeff Kirsher NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 218adfc5217SJeff Kirsher SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 219adfc5217SJeff Kirsher "Entry 1100"}, 220adfc5217SJeff Kirsher /* Expansion entry 1101 */ 221adfc5217SJeff Kirsher {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 222adfc5217SJeff Kirsher NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 223adfc5217SJeff Kirsher SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 224adfc5217SJeff Kirsher "Entry 1101"}, 225adfc5217SJeff Kirsher /* Ateml Expansion entry 1110 */ 226adfc5217SJeff Kirsher {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 227adfc5217SJeff Kirsher BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 228adfc5217SJeff Kirsher BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 229adfc5217SJeff Kirsher "Entry 1110 (Atmel)"}, 230adfc5217SJeff Kirsher /* ATMEL AT45DB021B (buffered flash) */ 231adfc5217SJeff Kirsher {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 232adfc5217SJeff Kirsher BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 233adfc5217SJeff Kirsher BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 234adfc5217SJeff Kirsher "Buffered flash (256kB)"}, 235adfc5217SJeff Kirsher }; 236adfc5217SJeff Kirsher 237adfc5217SJeff Kirsher static const struct flash_spec flash_5709 = { 238adfc5217SJeff Kirsher .flags = BNX2_NV_BUFFERED, 239adfc5217SJeff Kirsher .page_bits = BCM5709_FLASH_PAGE_BITS, 240adfc5217SJeff Kirsher .page_size = BCM5709_FLASH_PAGE_SIZE, 241adfc5217SJeff Kirsher .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 242adfc5217SJeff Kirsher .total_size = BUFFERED_FLASH_TOTAL_SIZE*2, 243adfc5217SJeff Kirsher .name = "5709 Buffered flash (256kB)", 244adfc5217SJeff Kirsher }; 245adfc5217SJeff Kirsher 246adfc5217SJeff Kirsher MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); 247adfc5217SJeff Kirsher 248adfc5217SJeff Kirsher static void bnx2_init_napi(struct bnx2 *bp); 249adfc5217SJeff Kirsher static void bnx2_del_napi(struct bnx2 *bp); 250adfc5217SJeff Kirsher 251adfc5217SJeff Kirsher static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr) 252adfc5217SJeff Kirsher { 253adfc5217SJeff Kirsher u32 diff; 254adfc5217SJeff Kirsher 255adfc5217SJeff Kirsher /* Tell compiler to fetch tx_prod and tx_cons from memory. */ 256adfc5217SJeff Kirsher barrier(); 257adfc5217SJeff Kirsher 258adfc5217SJeff Kirsher /* The ring uses 256 indices for 255 entries, one of them 259adfc5217SJeff Kirsher * needs to be skipped. 260adfc5217SJeff Kirsher */ 261adfc5217SJeff Kirsher diff = txr->tx_prod - txr->tx_cons; 262adfc5217SJeff Kirsher if (unlikely(diff >= TX_DESC_CNT)) { 263adfc5217SJeff Kirsher diff &= 0xffff; 264adfc5217SJeff Kirsher if (diff == TX_DESC_CNT) 265adfc5217SJeff Kirsher diff = MAX_TX_DESC_CNT; 266adfc5217SJeff Kirsher } 267adfc5217SJeff Kirsher return bp->tx_ring_size - diff; 268adfc5217SJeff Kirsher } 269adfc5217SJeff Kirsher 270adfc5217SJeff Kirsher static u32 271adfc5217SJeff Kirsher bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) 272adfc5217SJeff Kirsher { 273adfc5217SJeff Kirsher u32 val; 274adfc5217SJeff Kirsher 275adfc5217SJeff Kirsher spin_lock_bh(&bp->indirect_lock); 276adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); 277adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW); 278adfc5217SJeff Kirsher spin_unlock_bh(&bp->indirect_lock); 279adfc5217SJeff Kirsher return val; 280adfc5217SJeff Kirsher } 281adfc5217SJeff Kirsher 282adfc5217SJeff Kirsher static void 283adfc5217SJeff Kirsher bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) 284adfc5217SJeff Kirsher { 285adfc5217SJeff Kirsher spin_lock_bh(&bp->indirect_lock); 286adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); 287adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val); 288adfc5217SJeff Kirsher spin_unlock_bh(&bp->indirect_lock); 289adfc5217SJeff Kirsher } 290adfc5217SJeff Kirsher 291adfc5217SJeff Kirsher static void 292adfc5217SJeff Kirsher bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val) 293adfc5217SJeff Kirsher { 294adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val); 295adfc5217SJeff Kirsher } 296adfc5217SJeff Kirsher 297adfc5217SJeff Kirsher static u32 298adfc5217SJeff Kirsher bnx2_shmem_rd(struct bnx2 *bp, u32 offset) 299adfc5217SJeff Kirsher { 300adfc5217SJeff Kirsher return bnx2_reg_rd_ind(bp, bp->shmem_base + offset); 301adfc5217SJeff Kirsher } 302adfc5217SJeff Kirsher 303adfc5217SJeff Kirsher static void 304adfc5217SJeff Kirsher bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) 305adfc5217SJeff Kirsher { 306adfc5217SJeff Kirsher offset += cid_addr; 307adfc5217SJeff Kirsher spin_lock_bh(&bp->indirect_lock); 308adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 309adfc5217SJeff Kirsher int i; 310adfc5217SJeff Kirsher 311adfc5217SJeff Kirsher REG_WR(bp, BNX2_CTX_CTX_DATA, val); 312adfc5217SJeff Kirsher REG_WR(bp, BNX2_CTX_CTX_CTRL, 313adfc5217SJeff Kirsher offset | BNX2_CTX_CTX_CTRL_WRITE_REQ); 314adfc5217SJeff Kirsher for (i = 0; i < 5; i++) { 315adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_CTX_CTX_CTRL); 316adfc5217SJeff Kirsher if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) 317adfc5217SJeff Kirsher break; 318adfc5217SJeff Kirsher udelay(5); 319adfc5217SJeff Kirsher } 320adfc5217SJeff Kirsher } else { 321adfc5217SJeff Kirsher REG_WR(bp, BNX2_CTX_DATA_ADR, offset); 322adfc5217SJeff Kirsher REG_WR(bp, BNX2_CTX_DATA, val); 323adfc5217SJeff Kirsher } 324adfc5217SJeff Kirsher spin_unlock_bh(&bp->indirect_lock); 325adfc5217SJeff Kirsher } 326adfc5217SJeff Kirsher 327adfc5217SJeff Kirsher #ifdef BCM_CNIC 328adfc5217SJeff Kirsher static int 329adfc5217SJeff Kirsher bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info) 330adfc5217SJeff Kirsher { 331adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 332adfc5217SJeff Kirsher struct drv_ctl_io *io = &info->data.io; 333adfc5217SJeff Kirsher 334adfc5217SJeff Kirsher switch (info->cmd) { 335adfc5217SJeff Kirsher case DRV_CTL_IO_WR_CMD: 336adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, io->offset, io->data); 337adfc5217SJeff Kirsher break; 338adfc5217SJeff Kirsher case DRV_CTL_IO_RD_CMD: 339adfc5217SJeff Kirsher io->data = bnx2_reg_rd_ind(bp, io->offset); 340adfc5217SJeff Kirsher break; 341adfc5217SJeff Kirsher case DRV_CTL_CTX_WR_CMD: 342adfc5217SJeff Kirsher bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data); 343adfc5217SJeff Kirsher break; 344adfc5217SJeff Kirsher default: 345adfc5217SJeff Kirsher return -EINVAL; 346adfc5217SJeff Kirsher } 347adfc5217SJeff Kirsher return 0; 348adfc5217SJeff Kirsher } 349adfc5217SJeff Kirsher 350adfc5217SJeff Kirsher static void bnx2_setup_cnic_irq_info(struct bnx2 *bp) 351adfc5217SJeff Kirsher { 352adfc5217SJeff Kirsher struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 353adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 354adfc5217SJeff Kirsher int sb_id; 355adfc5217SJeff Kirsher 356adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_USING_MSIX) { 357adfc5217SJeff Kirsher cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 358adfc5217SJeff Kirsher bnapi->cnic_present = 0; 359adfc5217SJeff Kirsher sb_id = bp->irq_nvecs; 360adfc5217SJeff Kirsher cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 361adfc5217SJeff Kirsher } else { 362adfc5217SJeff Kirsher cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 363adfc5217SJeff Kirsher bnapi->cnic_tag = bnapi->last_status_idx; 364adfc5217SJeff Kirsher bnapi->cnic_present = 1; 365adfc5217SJeff Kirsher sb_id = 0; 366adfc5217SJeff Kirsher cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 367adfc5217SJeff Kirsher } 368adfc5217SJeff Kirsher 369adfc5217SJeff Kirsher cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector; 370adfc5217SJeff Kirsher cp->irq_arr[0].status_blk = (void *) 371adfc5217SJeff Kirsher ((unsigned long) bnapi->status_blk.msi + 372adfc5217SJeff Kirsher (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id)); 373adfc5217SJeff Kirsher cp->irq_arr[0].status_blk_num = sb_id; 374adfc5217SJeff Kirsher cp->num_irq = 1; 375adfc5217SJeff Kirsher } 376adfc5217SJeff Kirsher 377adfc5217SJeff Kirsher static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops, 378adfc5217SJeff Kirsher void *data) 379adfc5217SJeff Kirsher { 380adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 381adfc5217SJeff Kirsher struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 382adfc5217SJeff Kirsher 383adfc5217SJeff Kirsher if (ops == NULL) 384adfc5217SJeff Kirsher return -EINVAL; 385adfc5217SJeff Kirsher 386adfc5217SJeff Kirsher if (cp->drv_state & CNIC_DRV_STATE_REGD) 387adfc5217SJeff Kirsher return -EBUSY; 388adfc5217SJeff Kirsher 389adfc5217SJeff Kirsher if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN)) 390adfc5217SJeff Kirsher return -ENODEV; 391adfc5217SJeff Kirsher 392adfc5217SJeff Kirsher bp->cnic_data = data; 393adfc5217SJeff Kirsher rcu_assign_pointer(bp->cnic_ops, ops); 394adfc5217SJeff Kirsher 395adfc5217SJeff Kirsher cp->num_irq = 0; 396adfc5217SJeff Kirsher cp->drv_state = CNIC_DRV_STATE_REGD; 397adfc5217SJeff Kirsher 398adfc5217SJeff Kirsher bnx2_setup_cnic_irq_info(bp); 399adfc5217SJeff Kirsher 400adfc5217SJeff Kirsher return 0; 401adfc5217SJeff Kirsher } 402adfc5217SJeff Kirsher 403adfc5217SJeff Kirsher static int bnx2_unregister_cnic(struct net_device *dev) 404adfc5217SJeff Kirsher { 405adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 406adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 407adfc5217SJeff Kirsher struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 408adfc5217SJeff Kirsher 409adfc5217SJeff Kirsher mutex_lock(&bp->cnic_lock); 410adfc5217SJeff Kirsher cp->drv_state = 0; 411adfc5217SJeff Kirsher bnapi->cnic_present = 0; 4122cfa5a04SEric Dumazet RCU_INIT_POINTER(bp->cnic_ops, NULL); 413adfc5217SJeff Kirsher mutex_unlock(&bp->cnic_lock); 414adfc5217SJeff Kirsher synchronize_rcu(); 415adfc5217SJeff Kirsher return 0; 416adfc5217SJeff Kirsher } 417adfc5217SJeff Kirsher 418adfc5217SJeff Kirsher struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev) 419adfc5217SJeff Kirsher { 420adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 421adfc5217SJeff Kirsher struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 422adfc5217SJeff Kirsher 423adfc5217SJeff Kirsher if (!cp->max_iscsi_conn) 424adfc5217SJeff Kirsher return NULL; 425adfc5217SJeff Kirsher 426adfc5217SJeff Kirsher cp->drv_owner = THIS_MODULE; 427adfc5217SJeff Kirsher cp->chip_id = bp->chip_id; 428adfc5217SJeff Kirsher cp->pdev = bp->pdev; 429adfc5217SJeff Kirsher cp->io_base = bp->regview; 430adfc5217SJeff Kirsher cp->drv_ctl = bnx2_drv_ctl; 431adfc5217SJeff Kirsher cp->drv_register_cnic = bnx2_register_cnic; 432adfc5217SJeff Kirsher cp->drv_unregister_cnic = bnx2_unregister_cnic; 433adfc5217SJeff Kirsher 434adfc5217SJeff Kirsher return cp; 435adfc5217SJeff Kirsher } 436adfc5217SJeff Kirsher EXPORT_SYMBOL(bnx2_cnic_probe); 437adfc5217SJeff Kirsher 438adfc5217SJeff Kirsher static void 439adfc5217SJeff Kirsher bnx2_cnic_stop(struct bnx2 *bp) 440adfc5217SJeff Kirsher { 441adfc5217SJeff Kirsher struct cnic_ops *c_ops; 442adfc5217SJeff Kirsher struct cnic_ctl_info info; 443adfc5217SJeff Kirsher 444adfc5217SJeff Kirsher mutex_lock(&bp->cnic_lock); 445adfc5217SJeff Kirsher c_ops = rcu_dereference_protected(bp->cnic_ops, 446adfc5217SJeff Kirsher lockdep_is_held(&bp->cnic_lock)); 447adfc5217SJeff Kirsher if (c_ops) { 448adfc5217SJeff Kirsher info.cmd = CNIC_CTL_STOP_CMD; 449adfc5217SJeff Kirsher c_ops->cnic_ctl(bp->cnic_data, &info); 450adfc5217SJeff Kirsher } 451adfc5217SJeff Kirsher mutex_unlock(&bp->cnic_lock); 452adfc5217SJeff Kirsher } 453adfc5217SJeff Kirsher 454adfc5217SJeff Kirsher static void 455adfc5217SJeff Kirsher bnx2_cnic_start(struct bnx2 *bp) 456adfc5217SJeff Kirsher { 457adfc5217SJeff Kirsher struct cnic_ops *c_ops; 458adfc5217SJeff Kirsher struct cnic_ctl_info info; 459adfc5217SJeff Kirsher 460adfc5217SJeff Kirsher mutex_lock(&bp->cnic_lock); 461adfc5217SJeff Kirsher c_ops = rcu_dereference_protected(bp->cnic_ops, 462adfc5217SJeff Kirsher lockdep_is_held(&bp->cnic_lock)); 463adfc5217SJeff Kirsher if (c_ops) { 464adfc5217SJeff Kirsher if (!(bp->flags & BNX2_FLAG_USING_MSIX)) { 465adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 466adfc5217SJeff Kirsher 467adfc5217SJeff Kirsher bnapi->cnic_tag = bnapi->last_status_idx; 468adfc5217SJeff Kirsher } 469adfc5217SJeff Kirsher info.cmd = CNIC_CTL_START_CMD; 470adfc5217SJeff Kirsher c_ops->cnic_ctl(bp->cnic_data, &info); 471adfc5217SJeff Kirsher } 472adfc5217SJeff Kirsher mutex_unlock(&bp->cnic_lock); 473adfc5217SJeff Kirsher } 474adfc5217SJeff Kirsher 475adfc5217SJeff Kirsher #else 476adfc5217SJeff Kirsher 477adfc5217SJeff Kirsher static void 478adfc5217SJeff Kirsher bnx2_cnic_stop(struct bnx2 *bp) 479adfc5217SJeff Kirsher { 480adfc5217SJeff Kirsher } 481adfc5217SJeff Kirsher 482adfc5217SJeff Kirsher static void 483adfc5217SJeff Kirsher bnx2_cnic_start(struct bnx2 *bp) 484adfc5217SJeff Kirsher { 485adfc5217SJeff Kirsher } 486adfc5217SJeff Kirsher 487adfc5217SJeff Kirsher #endif 488adfc5217SJeff Kirsher 489adfc5217SJeff Kirsher static int 490adfc5217SJeff Kirsher bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) 491adfc5217SJeff Kirsher { 492adfc5217SJeff Kirsher u32 val1; 493adfc5217SJeff Kirsher int i, ret; 494adfc5217SJeff Kirsher 495adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 496adfc5217SJeff Kirsher val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); 497adfc5217SJeff Kirsher val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; 498adfc5217SJeff Kirsher 499adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 500adfc5217SJeff Kirsher REG_RD(bp, BNX2_EMAC_MDIO_MODE); 501adfc5217SJeff Kirsher 502adfc5217SJeff Kirsher udelay(40); 503adfc5217SJeff Kirsher } 504adfc5217SJeff Kirsher 505adfc5217SJeff Kirsher val1 = (bp->phy_addr << 21) | (reg << 16) | 506adfc5217SJeff Kirsher BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT | 507adfc5217SJeff Kirsher BNX2_EMAC_MDIO_COMM_START_BUSY; 508adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); 509adfc5217SJeff Kirsher 510adfc5217SJeff Kirsher for (i = 0; i < 50; i++) { 511adfc5217SJeff Kirsher udelay(10); 512adfc5217SJeff Kirsher 513adfc5217SJeff Kirsher val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); 514adfc5217SJeff Kirsher if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { 515adfc5217SJeff Kirsher udelay(5); 516adfc5217SJeff Kirsher 517adfc5217SJeff Kirsher val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); 518adfc5217SJeff Kirsher val1 &= BNX2_EMAC_MDIO_COMM_DATA; 519adfc5217SJeff Kirsher 520adfc5217SJeff Kirsher break; 521adfc5217SJeff Kirsher } 522adfc5217SJeff Kirsher } 523adfc5217SJeff Kirsher 524adfc5217SJeff Kirsher if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) { 525adfc5217SJeff Kirsher *val = 0x0; 526adfc5217SJeff Kirsher ret = -EBUSY; 527adfc5217SJeff Kirsher } 528adfc5217SJeff Kirsher else { 529adfc5217SJeff Kirsher *val = val1; 530adfc5217SJeff Kirsher ret = 0; 531adfc5217SJeff Kirsher } 532adfc5217SJeff Kirsher 533adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 534adfc5217SJeff Kirsher val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); 535adfc5217SJeff Kirsher val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; 536adfc5217SJeff Kirsher 537adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 538adfc5217SJeff Kirsher REG_RD(bp, BNX2_EMAC_MDIO_MODE); 539adfc5217SJeff Kirsher 540adfc5217SJeff Kirsher udelay(40); 541adfc5217SJeff Kirsher } 542adfc5217SJeff Kirsher 543adfc5217SJeff Kirsher return ret; 544adfc5217SJeff Kirsher } 545adfc5217SJeff Kirsher 546adfc5217SJeff Kirsher static int 547adfc5217SJeff Kirsher bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) 548adfc5217SJeff Kirsher { 549adfc5217SJeff Kirsher u32 val1; 550adfc5217SJeff Kirsher int i, ret; 551adfc5217SJeff Kirsher 552adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 553adfc5217SJeff Kirsher val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); 554adfc5217SJeff Kirsher val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; 555adfc5217SJeff Kirsher 556adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 557adfc5217SJeff Kirsher REG_RD(bp, BNX2_EMAC_MDIO_MODE); 558adfc5217SJeff Kirsher 559adfc5217SJeff Kirsher udelay(40); 560adfc5217SJeff Kirsher } 561adfc5217SJeff Kirsher 562adfc5217SJeff Kirsher val1 = (bp->phy_addr << 21) | (reg << 16) | val | 563adfc5217SJeff Kirsher BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | 564adfc5217SJeff Kirsher BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; 565adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); 566adfc5217SJeff Kirsher 567adfc5217SJeff Kirsher for (i = 0; i < 50; i++) { 568adfc5217SJeff Kirsher udelay(10); 569adfc5217SJeff Kirsher 570adfc5217SJeff Kirsher val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); 571adfc5217SJeff Kirsher if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { 572adfc5217SJeff Kirsher udelay(5); 573adfc5217SJeff Kirsher break; 574adfc5217SJeff Kirsher } 575adfc5217SJeff Kirsher } 576adfc5217SJeff Kirsher 577adfc5217SJeff Kirsher if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) 578adfc5217SJeff Kirsher ret = -EBUSY; 579adfc5217SJeff Kirsher else 580adfc5217SJeff Kirsher ret = 0; 581adfc5217SJeff Kirsher 582adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 583adfc5217SJeff Kirsher val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); 584adfc5217SJeff Kirsher val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; 585adfc5217SJeff Kirsher 586adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 587adfc5217SJeff Kirsher REG_RD(bp, BNX2_EMAC_MDIO_MODE); 588adfc5217SJeff Kirsher 589adfc5217SJeff Kirsher udelay(40); 590adfc5217SJeff Kirsher } 591adfc5217SJeff Kirsher 592adfc5217SJeff Kirsher return ret; 593adfc5217SJeff Kirsher } 594adfc5217SJeff Kirsher 595adfc5217SJeff Kirsher static void 596adfc5217SJeff Kirsher bnx2_disable_int(struct bnx2 *bp) 597adfc5217SJeff Kirsher { 598adfc5217SJeff Kirsher int i; 599adfc5217SJeff Kirsher struct bnx2_napi *bnapi; 600adfc5217SJeff Kirsher 601adfc5217SJeff Kirsher for (i = 0; i < bp->irq_nvecs; i++) { 602adfc5217SJeff Kirsher bnapi = &bp->bnx2_napi[i]; 603adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 604adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 605adfc5217SJeff Kirsher } 606adfc5217SJeff Kirsher REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD); 607adfc5217SJeff Kirsher } 608adfc5217SJeff Kirsher 609adfc5217SJeff Kirsher static void 610adfc5217SJeff Kirsher bnx2_enable_int(struct bnx2 *bp) 611adfc5217SJeff Kirsher { 612adfc5217SJeff Kirsher int i; 613adfc5217SJeff Kirsher struct bnx2_napi *bnapi; 614adfc5217SJeff Kirsher 615adfc5217SJeff Kirsher for (i = 0; i < bp->irq_nvecs; i++) { 616adfc5217SJeff Kirsher bnapi = &bp->bnx2_napi[i]; 617adfc5217SJeff Kirsher 618adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 619adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 620adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_MASK_INT | 621adfc5217SJeff Kirsher bnapi->last_status_idx); 622adfc5217SJeff Kirsher 623adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 624adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 625adfc5217SJeff Kirsher bnapi->last_status_idx); 626adfc5217SJeff Kirsher } 627adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); 628adfc5217SJeff Kirsher } 629adfc5217SJeff Kirsher 630adfc5217SJeff Kirsher static void 631adfc5217SJeff Kirsher bnx2_disable_int_sync(struct bnx2 *bp) 632adfc5217SJeff Kirsher { 633adfc5217SJeff Kirsher int i; 634adfc5217SJeff Kirsher 635adfc5217SJeff Kirsher atomic_inc(&bp->intr_sem); 636adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 637adfc5217SJeff Kirsher return; 638adfc5217SJeff Kirsher 639adfc5217SJeff Kirsher bnx2_disable_int(bp); 640adfc5217SJeff Kirsher for (i = 0; i < bp->irq_nvecs; i++) 641adfc5217SJeff Kirsher synchronize_irq(bp->irq_tbl[i].vector); 642adfc5217SJeff Kirsher } 643adfc5217SJeff Kirsher 644adfc5217SJeff Kirsher static void 645adfc5217SJeff Kirsher bnx2_napi_disable(struct bnx2 *bp) 646adfc5217SJeff Kirsher { 647adfc5217SJeff Kirsher int i; 648adfc5217SJeff Kirsher 649adfc5217SJeff Kirsher for (i = 0; i < bp->irq_nvecs; i++) 650adfc5217SJeff Kirsher napi_disable(&bp->bnx2_napi[i].napi); 651adfc5217SJeff Kirsher } 652adfc5217SJeff Kirsher 653adfc5217SJeff Kirsher static void 654adfc5217SJeff Kirsher bnx2_napi_enable(struct bnx2 *bp) 655adfc5217SJeff Kirsher { 656adfc5217SJeff Kirsher int i; 657adfc5217SJeff Kirsher 658adfc5217SJeff Kirsher for (i = 0; i < bp->irq_nvecs; i++) 659adfc5217SJeff Kirsher napi_enable(&bp->bnx2_napi[i].napi); 660adfc5217SJeff Kirsher } 661adfc5217SJeff Kirsher 662adfc5217SJeff Kirsher static void 663adfc5217SJeff Kirsher bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic) 664adfc5217SJeff Kirsher { 665adfc5217SJeff Kirsher if (stop_cnic) 666adfc5217SJeff Kirsher bnx2_cnic_stop(bp); 667adfc5217SJeff Kirsher if (netif_running(bp->dev)) { 668adfc5217SJeff Kirsher bnx2_napi_disable(bp); 669adfc5217SJeff Kirsher netif_tx_disable(bp->dev); 670adfc5217SJeff Kirsher } 671adfc5217SJeff Kirsher bnx2_disable_int_sync(bp); 672adfc5217SJeff Kirsher netif_carrier_off(bp->dev); /* prevent tx timeout */ 673adfc5217SJeff Kirsher } 674adfc5217SJeff Kirsher 675adfc5217SJeff Kirsher static void 676adfc5217SJeff Kirsher bnx2_netif_start(struct bnx2 *bp, bool start_cnic) 677adfc5217SJeff Kirsher { 678adfc5217SJeff Kirsher if (atomic_dec_and_test(&bp->intr_sem)) { 679adfc5217SJeff Kirsher if (netif_running(bp->dev)) { 680adfc5217SJeff Kirsher netif_tx_wake_all_queues(bp->dev); 681adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 682adfc5217SJeff Kirsher if (bp->link_up) 683adfc5217SJeff Kirsher netif_carrier_on(bp->dev); 684adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 685adfc5217SJeff Kirsher bnx2_napi_enable(bp); 686adfc5217SJeff Kirsher bnx2_enable_int(bp); 687adfc5217SJeff Kirsher if (start_cnic) 688adfc5217SJeff Kirsher bnx2_cnic_start(bp); 689adfc5217SJeff Kirsher } 690adfc5217SJeff Kirsher } 691adfc5217SJeff Kirsher } 692adfc5217SJeff Kirsher 693adfc5217SJeff Kirsher static void 694adfc5217SJeff Kirsher bnx2_free_tx_mem(struct bnx2 *bp) 695adfc5217SJeff Kirsher { 696adfc5217SJeff Kirsher int i; 697adfc5217SJeff Kirsher 698adfc5217SJeff Kirsher for (i = 0; i < bp->num_tx_rings; i++) { 699adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 700adfc5217SJeff Kirsher struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 701adfc5217SJeff Kirsher 702adfc5217SJeff Kirsher if (txr->tx_desc_ring) { 703adfc5217SJeff Kirsher dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE, 704adfc5217SJeff Kirsher txr->tx_desc_ring, 705adfc5217SJeff Kirsher txr->tx_desc_mapping); 706adfc5217SJeff Kirsher txr->tx_desc_ring = NULL; 707adfc5217SJeff Kirsher } 708adfc5217SJeff Kirsher kfree(txr->tx_buf_ring); 709adfc5217SJeff Kirsher txr->tx_buf_ring = NULL; 710adfc5217SJeff Kirsher } 711adfc5217SJeff Kirsher } 712adfc5217SJeff Kirsher 713adfc5217SJeff Kirsher static void 714adfc5217SJeff Kirsher bnx2_free_rx_mem(struct bnx2 *bp) 715adfc5217SJeff Kirsher { 716adfc5217SJeff Kirsher int i; 717adfc5217SJeff Kirsher 718adfc5217SJeff Kirsher for (i = 0; i < bp->num_rx_rings; i++) { 719adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 720adfc5217SJeff Kirsher struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 721adfc5217SJeff Kirsher int j; 722adfc5217SJeff Kirsher 723adfc5217SJeff Kirsher for (j = 0; j < bp->rx_max_ring; j++) { 724adfc5217SJeff Kirsher if (rxr->rx_desc_ring[j]) 725adfc5217SJeff Kirsher dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, 726adfc5217SJeff Kirsher rxr->rx_desc_ring[j], 727adfc5217SJeff Kirsher rxr->rx_desc_mapping[j]); 728adfc5217SJeff Kirsher rxr->rx_desc_ring[j] = NULL; 729adfc5217SJeff Kirsher } 730adfc5217SJeff Kirsher vfree(rxr->rx_buf_ring); 731adfc5217SJeff Kirsher rxr->rx_buf_ring = NULL; 732adfc5217SJeff Kirsher 733adfc5217SJeff Kirsher for (j = 0; j < bp->rx_max_pg_ring; j++) { 734adfc5217SJeff Kirsher if (rxr->rx_pg_desc_ring[j]) 735adfc5217SJeff Kirsher dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, 736adfc5217SJeff Kirsher rxr->rx_pg_desc_ring[j], 737adfc5217SJeff Kirsher rxr->rx_pg_desc_mapping[j]); 738adfc5217SJeff Kirsher rxr->rx_pg_desc_ring[j] = NULL; 739adfc5217SJeff Kirsher } 740adfc5217SJeff Kirsher vfree(rxr->rx_pg_ring); 741adfc5217SJeff Kirsher rxr->rx_pg_ring = NULL; 742adfc5217SJeff Kirsher } 743adfc5217SJeff Kirsher } 744adfc5217SJeff Kirsher 745adfc5217SJeff Kirsher static int 746adfc5217SJeff Kirsher bnx2_alloc_tx_mem(struct bnx2 *bp) 747adfc5217SJeff Kirsher { 748adfc5217SJeff Kirsher int i; 749adfc5217SJeff Kirsher 750adfc5217SJeff Kirsher for (i = 0; i < bp->num_tx_rings; i++) { 751adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 752adfc5217SJeff Kirsher struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 753adfc5217SJeff Kirsher 754adfc5217SJeff Kirsher txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); 755adfc5217SJeff Kirsher if (txr->tx_buf_ring == NULL) 756adfc5217SJeff Kirsher return -ENOMEM; 757adfc5217SJeff Kirsher 758adfc5217SJeff Kirsher txr->tx_desc_ring = 759adfc5217SJeff Kirsher dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE, 760adfc5217SJeff Kirsher &txr->tx_desc_mapping, GFP_KERNEL); 761adfc5217SJeff Kirsher if (txr->tx_desc_ring == NULL) 762adfc5217SJeff Kirsher return -ENOMEM; 763adfc5217SJeff Kirsher } 764adfc5217SJeff Kirsher return 0; 765adfc5217SJeff Kirsher } 766adfc5217SJeff Kirsher 767adfc5217SJeff Kirsher static int 768adfc5217SJeff Kirsher bnx2_alloc_rx_mem(struct bnx2 *bp) 769adfc5217SJeff Kirsher { 770adfc5217SJeff Kirsher int i; 771adfc5217SJeff Kirsher 772adfc5217SJeff Kirsher for (i = 0; i < bp->num_rx_rings; i++) { 773adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 774adfc5217SJeff Kirsher struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 775adfc5217SJeff Kirsher int j; 776adfc5217SJeff Kirsher 777adfc5217SJeff Kirsher rxr->rx_buf_ring = 778adfc5217SJeff Kirsher vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring); 779adfc5217SJeff Kirsher if (rxr->rx_buf_ring == NULL) 780adfc5217SJeff Kirsher return -ENOMEM; 781adfc5217SJeff Kirsher 782adfc5217SJeff Kirsher for (j = 0; j < bp->rx_max_ring; j++) { 783adfc5217SJeff Kirsher rxr->rx_desc_ring[j] = 784adfc5217SJeff Kirsher dma_alloc_coherent(&bp->pdev->dev, 785adfc5217SJeff Kirsher RXBD_RING_SIZE, 786adfc5217SJeff Kirsher &rxr->rx_desc_mapping[j], 787adfc5217SJeff Kirsher GFP_KERNEL); 788adfc5217SJeff Kirsher if (rxr->rx_desc_ring[j] == NULL) 789adfc5217SJeff Kirsher return -ENOMEM; 790adfc5217SJeff Kirsher 791adfc5217SJeff Kirsher } 792adfc5217SJeff Kirsher 793adfc5217SJeff Kirsher if (bp->rx_pg_ring_size) { 794adfc5217SJeff Kirsher rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE * 795adfc5217SJeff Kirsher bp->rx_max_pg_ring); 796adfc5217SJeff Kirsher if (rxr->rx_pg_ring == NULL) 797adfc5217SJeff Kirsher return -ENOMEM; 798adfc5217SJeff Kirsher 799adfc5217SJeff Kirsher } 800adfc5217SJeff Kirsher 801adfc5217SJeff Kirsher for (j = 0; j < bp->rx_max_pg_ring; j++) { 802adfc5217SJeff Kirsher rxr->rx_pg_desc_ring[j] = 803adfc5217SJeff Kirsher dma_alloc_coherent(&bp->pdev->dev, 804adfc5217SJeff Kirsher RXBD_RING_SIZE, 805adfc5217SJeff Kirsher &rxr->rx_pg_desc_mapping[j], 806adfc5217SJeff Kirsher GFP_KERNEL); 807adfc5217SJeff Kirsher if (rxr->rx_pg_desc_ring[j] == NULL) 808adfc5217SJeff Kirsher return -ENOMEM; 809adfc5217SJeff Kirsher 810adfc5217SJeff Kirsher } 811adfc5217SJeff Kirsher } 812adfc5217SJeff Kirsher return 0; 813adfc5217SJeff Kirsher } 814adfc5217SJeff Kirsher 815adfc5217SJeff Kirsher static void 816adfc5217SJeff Kirsher bnx2_free_mem(struct bnx2 *bp) 817adfc5217SJeff Kirsher { 818adfc5217SJeff Kirsher int i; 819adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 820adfc5217SJeff Kirsher 821adfc5217SJeff Kirsher bnx2_free_tx_mem(bp); 822adfc5217SJeff Kirsher bnx2_free_rx_mem(bp); 823adfc5217SJeff Kirsher 824adfc5217SJeff Kirsher for (i = 0; i < bp->ctx_pages; i++) { 825adfc5217SJeff Kirsher if (bp->ctx_blk[i]) { 826adfc5217SJeff Kirsher dma_free_coherent(&bp->pdev->dev, BCM_PAGE_SIZE, 827adfc5217SJeff Kirsher bp->ctx_blk[i], 828adfc5217SJeff Kirsher bp->ctx_blk_mapping[i]); 829adfc5217SJeff Kirsher bp->ctx_blk[i] = NULL; 830adfc5217SJeff Kirsher } 831adfc5217SJeff Kirsher } 832adfc5217SJeff Kirsher if (bnapi->status_blk.msi) { 833adfc5217SJeff Kirsher dma_free_coherent(&bp->pdev->dev, bp->status_stats_size, 834adfc5217SJeff Kirsher bnapi->status_blk.msi, 835adfc5217SJeff Kirsher bp->status_blk_mapping); 836adfc5217SJeff Kirsher bnapi->status_blk.msi = NULL; 837adfc5217SJeff Kirsher bp->stats_blk = NULL; 838adfc5217SJeff Kirsher } 839adfc5217SJeff Kirsher } 840adfc5217SJeff Kirsher 841adfc5217SJeff Kirsher static int 842adfc5217SJeff Kirsher bnx2_alloc_mem(struct bnx2 *bp) 843adfc5217SJeff Kirsher { 844adfc5217SJeff Kirsher int i, status_blk_size, err; 845adfc5217SJeff Kirsher struct bnx2_napi *bnapi; 846adfc5217SJeff Kirsher void *status_blk; 847adfc5217SJeff Kirsher 848adfc5217SJeff Kirsher /* Combine status and statistics blocks into one allocation. */ 849adfc5217SJeff Kirsher status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); 850adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_MSIX_CAP) 851adfc5217SJeff Kirsher status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC * 852adfc5217SJeff Kirsher BNX2_SBLK_MSIX_ALIGN_SIZE); 853adfc5217SJeff Kirsher bp->status_stats_size = status_blk_size + 854adfc5217SJeff Kirsher sizeof(struct statistics_block); 855adfc5217SJeff Kirsher 856adfc5217SJeff Kirsher status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size, 857adfc5217SJeff Kirsher &bp->status_blk_mapping, GFP_KERNEL); 858adfc5217SJeff Kirsher if (status_blk == NULL) 859adfc5217SJeff Kirsher goto alloc_mem_err; 860adfc5217SJeff Kirsher 861adfc5217SJeff Kirsher memset(status_blk, 0, bp->status_stats_size); 862adfc5217SJeff Kirsher 863adfc5217SJeff Kirsher bnapi = &bp->bnx2_napi[0]; 864adfc5217SJeff Kirsher bnapi->status_blk.msi = status_blk; 865adfc5217SJeff Kirsher bnapi->hw_tx_cons_ptr = 866adfc5217SJeff Kirsher &bnapi->status_blk.msi->status_tx_quick_consumer_index0; 867adfc5217SJeff Kirsher bnapi->hw_rx_cons_ptr = 868adfc5217SJeff Kirsher &bnapi->status_blk.msi->status_rx_quick_consumer_index0; 869adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_MSIX_CAP) { 870adfc5217SJeff Kirsher for (i = 1; i < bp->irq_nvecs; i++) { 871adfc5217SJeff Kirsher struct status_block_msix *sblk; 872adfc5217SJeff Kirsher 873adfc5217SJeff Kirsher bnapi = &bp->bnx2_napi[i]; 874adfc5217SJeff Kirsher 875adfc5217SJeff Kirsher sblk = (void *) (status_blk + 876adfc5217SJeff Kirsher BNX2_SBLK_MSIX_ALIGN_SIZE * i); 877adfc5217SJeff Kirsher bnapi->status_blk.msix = sblk; 878adfc5217SJeff Kirsher bnapi->hw_tx_cons_ptr = 879adfc5217SJeff Kirsher &sblk->status_tx_quick_consumer_index; 880adfc5217SJeff Kirsher bnapi->hw_rx_cons_ptr = 881adfc5217SJeff Kirsher &sblk->status_rx_quick_consumer_index; 882adfc5217SJeff Kirsher bnapi->int_num = i << 24; 883adfc5217SJeff Kirsher } 884adfc5217SJeff Kirsher } 885adfc5217SJeff Kirsher 886adfc5217SJeff Kirsher bp->stats_blk = status_blk + status_blk_size; 887adfc5217SJeff Kirsher 888adfc5217SJeff Kirsher bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; 889adfc5217SJeff Kirsher 890adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 891adfc5217SJeff Kirsher bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 892adfc5217SJeff Kirsher if (bp->ctx_pages == 0) 893adfc5217SJeff Kirsher bp->ctx_pages = 1; 894adfc5217SJeff Kirsher for (i = 0; i < bp->ctx_pages; i++) { 895adfc5217SJeff Kirsher bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev, 896adfc5217SJeff Kirsher BCM_PAGE_SIZE, 897adfc5217SJeff Kirsher &bp->ctx_blk_mapping[i], 898adfc5217SJeff Kirsher GFP_KERNEL); 899adfc5217SJeff Kirsher if (bp->ctx_blk[i] == NULL) 900adfc5217SJeff Kirsher goto alloc_mem_err; 901adfc5217SJeff Kirsher } 902adfc5217SJeff Kirsher } 903adfc5217SJeff Kirsher 904adfc5217SJeff Kirsher err = bnx2_alloc_rx_mem(bp); 905adfc5217SJeff Kirsher if (err) 906adfc5217SJeff Kirsher goto alloc_mem_err; 907adfc5217SJeff Kirsher 908adfc5217SJeff Kirsher err = bnx2_alloc_tx_mem(bp); 909adfc5217SJeff Kirsher if (err) 910adfc5217SJeff Kirsher goto alloc_mem_err; 911adfc5217SJeff Kirsher 912adfc5217SJeff Kirsher return 0; 913adfc5217SJeff Kirsher 914adfc5217SJeff Kirsher alloc_mem_err: 915adfc5217SJeff Kirsher bnx2_free_mem(bp); 916adfc5217SJeff Kirsher return -ENOMEM; 917adfc5217SJeff Kirsher } 918adfc5217SJeff Kirsher 919adfc5217SJeff Kirsher static void 920adfc5217SJeff Kirsher bnx2_report_fw_link(struct bnx2 *bp) 921adfc5217SJeff Kirsher { 922adfc5217SJeff Kirsher u32 fw_link_status = 0; 923adfc5217SJeff Kirsher 924adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 925adfc5217SJeff Kirsher return; 926adfc5217SJeff Kirsher 927adfc5217SJeff Kirsher if (bp->link_up) { 928adfc5217SJeff Kirsher u32 bmsr; 929adfc5217SJeff Kirsher 930adfc5217SJeff Kirsher switch (bp->line_speed) { 931adfc5217SJeff Kirsher case SPEED_10: 932adfc5217SJeff Kirsher if (bp->duplex == DUPLEX_HALF) 933adfc5217SJeff Kirsher fw_link_status = BNX2_LINK_STATUS_10HALF; 934adfc5217SJeff Kirsher else 935adfc5217SJeff Kirsher fw_link_status = BNX2_LINK_STATUS_10FULL; 936adfc5217SJeff Kirsher break; 937adfc5217SJeff Kirsher case SPEED_100: 938adfc5217SJeff Kirsher if (bp->duplex == DUPLEX_HALF) 939adfc5217SJeff Kirsher fw_link_status = BNX2_LINK_STATUS_100HALF; 940adfc5217SJeff Kirsher else 941adfc5217SJeff Kirsher fw_link_status = BNX2_LINK_STATUS_100FULL; 942adfc5217SJeff Kirsher break; 943adfc5217SJeff Kirsher case SPEED_1000: 944adfc5217SJeff Kirsher if (bp->duplex == DUPLEX_HALF) 945adfc5217SJeff Kirsher fw_link_status = BNX2_LINK_STATUS_1000HALF; 946adfc5217SJeff Kirsher else 947adfc5217SJeff Kirsher fw_link_status = BNX2_LINK_STATUS_1000FULL; 948adfc5217SJeff Kirsher break; 949adfc5217SJeff Kirsher case SPEED_2500: 950adfc5217SJeff Kirsher if (bp->duplex == DUPLEX_HALF) 951adfc5217SJeff Kirsher fw_link_status = BNX2_LINK_STATUS_2500HALF; 952adfc5217SJeff Kirsher else 953adfc5217SJeff Kirsher fw_link_status = BNX2_LINK_STATUS_2500FULL; 954adfc5217SJeff Kirsher break; 955adfc5217SJeff Kirsher } 956adfc5217SJeff Kirsher 957adfc5217SJeff Kirsher fw_link_status |= BNX2_LINK_STATUS_LINK_UP; 958adfc5217SJeff Kirsher 959adfc5217SJeff Kirsher if (bp->autoneg) { 960adfc5217SJeff Kirsher fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED; 961adfc5217SJeff Kirsher 962adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 963adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 964adfc5217SJeff Kirsher 965adfc5217SJeff Kirsher if (!(bmsr & BMSR_ANEGCOMPLETE) || 966adfc5217SJeff Kirsher bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) 967adfc5217SJeff Kirsher fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET; 968adfc5217SJeff Kirsher else 969adfc5217SJeff Kirsher fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE; 970adfc5217SJeff Kirsher } 971adfc5217SJeff Kirsher } 972adfc5217SJeff Kirsher else 973adfc5217SJeff Kirsher fw_link_status = BNX2_LINK_STATUS_LINK_DOWN; 974adfc5217SJeff Kirsher 975adfc5217SJeff Kirsher bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status); 976adfc5217SJeff Kirsher } 977adfc5217SJeff Kirsher 978adfc5217SJeff Kirsher static char * 979adfc5217SJeff Kirsher bnx2_xceiver_str(struct bnx2 *bp) 980adfc5217SJeff Kirsher { 981adfc5217SJeff Kirsher return (bp->phy_port == PORT_FIBRE) ? "SerDes" : 982adfc5217SJeff Kirsher ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" : 983adfc5217SJeff Kirsher "Copper"); 984adfc5217SJeff Kirsher } 985adfc5217SJeff Kirsher 986adfc5217SJeff Kirsher static void 987adfc5217SJeff Kirsher bnx2_report_link(struct bnx2 *bp) 988adfc5217SJeff Kirsher { 989adfc5217SJeff Kirsher if (bp->link_up) { 990adfc5217SJeff Kirsher netif_carrier_on(bp->dev); 991adfc5217SJeff Kirsher netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex", 992adfc5217SJeff Kirsher bnx2_xceiver_str(bp), 993adfc5217SJeff Kirsher bp->line_speed, 994adfc5217SJeff Kirsher bp->duplex == DUPLEX_FULL ? "full" : "half"); 995adfc5217SJeff Kirsher 996adfc5217SJeff Kirsher if (bp->flow_ctrl) { 997adfc5217SJeff Kirsher if (bp->flow_ctrl & FLOW_CTRL_RX) { 998adfc5217SJeff Kirsher pr_cont(", receive "); 999adfc5217SJeff Kirsher if (bp->flow_ctrl & FLOW_CTRL_TX) 1000adfc5217SJeff Kirsher pr_cont("& transmit "); 1001adfc5217SJeff Kirsher } 1002adfc5217SJeff Kirsher else { 1003adfc5217SJeff Kirsher pr_cont(", transmit "); 1004adfc5217SJeff Kirsher } 1005adfc5217SJeff Kirsher pr_cont("flow control ON"); 1006adfc5217SJeff Kirsher } 1007adfc5217SJeff Kirsher pr_cont("\n"); 1008adfc5217SJeff Kirsher } else { 1009adfc5217SJeff Kirsher netif_carrier_off(bp->dev); 1010adfc5217SJeff Kirsher netdev_err(bp->dev, "NIC %s Link is Down\n", 1011adfc5217SJeff Kirsher bnx2_xceiver_str(bp)); 1012adfc5217SJeff Kirsher } 1013adfc5217SJeff Kirsher 1014adfc5217SJeff Kirsher bnx2_report_fw_link(bp); 1015adfc5217SJeff Kirsher } 1016adfc5217SJeff Kirsher 1017adfc5217SJeff Kirsher static void 1018adfc5217SJeff Kirsher bnx2_resolve_flow_ctrl(struct bnx2 *bp) 1019adfc5217SJeff Kirsher { 1020adfc5217SJeff Kirsher u32 local_adv, remote_adv; 1021adfc5217SJeff Kirsher 1022adfc5217SJeff Kirsher bp->flow_ctrl = 0; 1023adfc5217SJeff Kirsher if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != 1024adfc5217SJeff Kirsher (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { 1025adfc5217SJeff Kirsher 1026adfc5217SJeff Kirsher if (bp->duplex == DUPLEX_FULL) { 1027adfc5217SJeff Kirsher bp->flow_ctrl = bp->req_flow_ctrl; 1028adfc5217SJeff Kirsher } 1029adfc5217SJeff Kirsher return; 1030adfc5217SJeff Kirsher } 1031adfc5217SJeff Kirsher 1032adfc5217SJeff Kirsher if (bp->duplex != DUPLEX_FULL) { 1033adfc5217SJeff Kirsher return; 1034adfc5217SJeff Kirsher } 1035adfc5217SJeff Kirsher 1036adfc5217SJeff Kirsher if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1037adfc5217SJeff Kirsher (CHIP_NUM(bp) == CHIP_NUM_5708)) { 1038adfc5217SJeff Kirsher u32 val; 1039adfc5217SJeff Kirsher 1040adfc5217SJeff Kirsher bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); 1041adfc5217SJeff Kirsher if (val & BCM5708S_1000X_STAT1_TX_PAUSE) 1042adfc5217SJeff Kirsher bp->flow_ctrl |= FLOW_CTRL_TX; 1043adfc5217SJeff Kirsher if (val & BCM5708S_1000X_STAT1_RX_PAUSE) 1044adfc5217SJeff Kirsher bp->flow_ctrl |= FLOW_CTRL_RX; 1045adfc5217SJeff Kirsher return; 1046adfc5217SJeff Kirsher } 1047adfc5217SJeff Kirsher 1048adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_adv, &local_adv); 1049adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); 1050adfc5217SJeff Kirsher 1051adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1052adfc5217SJeff Kirsher u32 new_local_adv = 0; 1053adfc5217SJeff Kirsher u32 new_remote_adv = 0; 1054adfc5217SJeff Kirsher 1055adfc5217SJeff Kirsher if (local_adv & ADVERTISE_1000XPAUSE) 1056adfc5217SJeff Kirsher new_local_adv |= ADVERTISE_PAUSE_CAP; 1057adfc5217SJeff Kirsher if (local_adv & ADVERTISE_1000XPSE_ASYM) 1058adfc5217SJeff Kirsher new_local_adv |= ADVERTISE_PAUSE_ASYM; 1059adfc5217SJeff Kirsher if (remote_adv & ADVERTISE_1000XPAUSE) 1060adfc5217SJeff Kirsher new_remote_adv |= ADVERTISE_PAUSE_CAP; 1061adfc5217SJeff Kirsher if (remote_adv & ADVERTISE_1000XPSE_ASYM) 1062adfc5217SJeff Kirsher new_remote_adv |= ADVERTISE_PAUSE_ASYM; 1063adfc5217SJeff Kirsher 1064adfc5217SJeff Kirsher local_adv = new_local_adv; 1065adfc5217SJeff Kirsher remote_adv = new_remote_adv; 1066adfc5217SJeff Kirsher } 1067adfc5217SJeff Kirsher 1068adfc5217SJeff Kirsher /* See Table 28B-3 of 802.3ab-1999 spec. */ 1069adfc5217SJeff Kirsher if (local_adv & ADVERTISE_PAUSE_CAP) { 1070adfc5217SJeff Kirsher if(local_adv & ADVERTISE_PAUSE_ASYM) { 1071adfc5217SJeff Kirsher if (remote_adv & ADVERTISE_PAUSE_CAP) { 1072adfc5217SJeff Kirsher bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; 1073adfc5217SJeff Kirsher } 1074adfc5217SJeff Kirsher else if (remote_adv & ADVERTISE_PAUSE_ASYM) { 1075adfc5217SJeff Kirsher bp->flow_ctrl = FLOW_CTRL_RX; 1076adfc5217SJeff Kirsher } 1077adfc5217SJeff Kirsher } 1078adfc5217SJeff Kirsher else { 1079adfc5217SJeff Kirsher if (remote_adv & ADVERTISE_PAUSE_CAP) { 1080adfc5217SJeff Kirsher bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; 1081adfc5217SJeff Kirsher } 1082adfc5217SJeff Kirsher } 1083adfc5217SJeff Kirsher } 1084adfc5217SJeff Kirsher else if (local_adv & ADVERTISE_PAUSE_ASYM) { 1085adfc5217SJeff Kirsher if ((remote_adv & ADVERTISE_PAUSE_CAP) && 1086adfc5217SJeff Kirsher (remote_adv & ADVERTISE_PAUSE_ASYM)) { 1087adfc5217SJeff Kirsher 1088adfc5217SJeff Kirsher bp->flow_ctrl = FLOW_CTRL_TX; 1089adfc5217SJeff Kirsher } 1090adfc5217SJeff Kirsher } 1091adfc5217SJeff Kirsher } 1092adfc5217SJeff Kirsher 1093adfc5217SJeff Kirsher static int 1094adfc5217SJeff Kirsher bnx2_5709s_linkup(struct bnx2 *bp) 1095adfc5217SJeff Kirsher { 1096adfc5217SJeff Kirsher u32 val, speed; 1097adfc5217SJeff Kirsher 1098adfc5217SJeff Kirsher bp->link_up = 1; 1099adfc5217SJeff Kirsher 1100adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); 1101adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val); 1102adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1103adfc5217SJeff Kirsher 1104adfc5217SJeff Kirsher if ((bp->autoneg & AUTONEG_SPEED) == 0) { 1105adfc5217SJeff Kirsher bp->line_speed = bp->req_line_speed; 1106adfc5217SJeff Kirsher bp->duplex = bp->req_duplex; 1107adfc5217SJeff Kirsher return 0; 1108adfc5217SJeff Kirsher } 1109adfc5217SJeff Kirsher speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK; 1110adfc5217SJeff Kirsher switch (speed) { 1111adfc5217SJeff Kirsher case MII_BNX2_GP_TOP_AN_SPEED_10: 1112adfc5217SJeff Kirsher bp->line_speed = SPEED_10; 1113adfc5217SJeff Kirsher break; 1114adfc5217SJeff Kirsher case MII_BNX2_GP_TOP_AN_SPEED_100: 1115adfc5217SJeff Kirsher bp->line_speed = SPEED_100; 1116adfc5217SJeff Kirsher break; 1117adfc5217SJeff Kirsher case MII_BNX2_GP_TOP_AN_SPEED_1G: 1118adfc5217SJeff Kirsher case MII_BNX2_GP_TOP_AN_SPEED_1GKV: 1119adfc5217SJeff Kirsher bp->line_speed = SPEED_1000; 1120adfc5217SJeff Kirsher break; 1121adfc5217SJeff Kirsher case MII_BNX2_GP_TOP_AN_SPEED_2_5G: 1122adfc5217SJeff Kirsher bp->line_speed = SPEED_2500; 1123adfc5217SJeff Kirsher break; 1124adfc5217SJeff Kirsher } 1125adfc5217SJeff Kirsher if (val & MII_BNX2_GP_TOP_AN_FD) 1126adfc5217SJeff Kirsher bp->duplex = DUPLEX_FULL; 1127adfc5217SJeff Kirsher else 1128adfc5217SJeff Kirsher bp->duplex = DUPLEX_HALF; 1129adfc5217SJeff Kirsher return 0; 1130adfc5217SJeff Kirsher } 1131adfc5217SJeff Kirsher 1132adfc5217SJeff Kirsher static int 1133adfc5217SJeff Kirsher bnx2_5708s_linkup(struct bnx2 *bp) 1134adfc5217SJeff Kirsher { 1135adfc5217SJeff Kirsher u32 val; 1136adfc5217SJeff Kirsher 1137adfc5217SJeff Kirsher bp->link_up = 1; 1138adfc5217SJeff Kirsher bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); 1139adfc5217SJeff Kirsher switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) { 1140adfc5217SJeff Kirsher case BCM5708S_1000X_STAT1_SPEED_10: 1141adfc5217SJeff Kirsher bp->line_speed = SPEED_10; 1142adfc5217SJeff Kirsher break; 1143adfc5217SJeff Kirsher case BCM5708S_1000X_STAT1_SPEED_100: 1144adfc5217SJeff Kirsher bp->line_speed = SPEED_100; 1145adfc5217SJeff Kirsher break; 1146adfc5217SJeff Kirsher case BCM5708S_1000X_STAT1_SPEED_1G: 1147adfc5217SJeff Kirsher bp->line_speed = SPEED_1000; 1148adfc5217SJeff Kirsher break; 1149adfc5217SJeff Kirsher case BCM5708S_1000X_STAT1_SPEED_2G5: 1150adfc5217SJeff Kirsher bp->line_speed = SPEED_2500; 1151adfc5217SJeff Kirsher break; 1152adfc5217SJeff Kirsher } 1153adfc5217SJeff Kirsher if (val & BCM5708S_1000X_STAT1_FD) 1154adfc5217SJeff Kirsher bp->duplex = DUPLEX_FULL; 1155adfc5217SJeff Kirsher else 1156adfc5217SJeff Kirsher bp->duplex = DUPLEX_HALF; 1157adfc5217SJeff Kirsher 1158adfc5217SJeff Kirsher return 0; 1159adfc5217SJeff Kirsher } 1160adfc5217SJeff Kirsher 1161adfc5217SJeff Kirsher static int 1162adfc5217SJeff Kirsher bnx2_5706s_linkup(struct bnx2 *bp) 1163adfc5217SJeff Kirsher { 1164adfc5217SJeff Kirsher u32 bmcr, local_adv, remote_adv, common; 1165adfc5217SJeff Kirsher 1166adfc5217SJeff Kirsher bp->link_up = 1; 1167adfc5217SJeff Kirsher bp->line_speed = SPEED_1000; 1168adfc5217SJeff Kirsher 1169adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1170adfc5217SJeff Kirsher if (bmcr & BMCR_FULLDPLX) { 1171adfc5217SJeff Kirsher bp->duplex = DUPLEX_FULL; 1172adfc5217SJeff Kirsher } 1173adfc5217SJeff Kirsher else { 1174adfc5217SJeff Kirsher bp->duplex = DUPLEX_HALF; 1175adfc5217SJeff Kirsher } 1176adfc5217SJeff Kirsher 1177adfc5217SJeff Kirsher if (!(bmcr & BMCR_ANENABLE)) { 1178adfc5217SJeff Kirsher return 0; 1179adfc5217SJeff Kirsher } 1180adfc5217SJeff Kirsher 1181adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_adv, &local_adv); 1182adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); 1183adfc5217SJeff Kirsher 1184adfc5217SJeff Kirsher common = local_adv & remote_adv; 1185adfc5217SJeff Kirsher if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { 1186adfc5217SJeff Kirsher 1187adfc5217SJeff Kirsher if (common & ADVERTISE_1000XFULL) { 1188adfc5217SJeff Kirsher bp->duplex = DUPLEX_FULL; 1189adfc5217SJeff Kirsher } 1190adfc5217SJeff Kirsher else { 1191adfc5217SJeff Kirsher bp->duplex = DUPLEX_HALF; 1192adfc5217SJeff Kirsher } 1193adfc5217SJeff Kirsher } 1194adfc5217SJeff Kirsher 1195adfc5217SJeff Kirsher return 0; 1196adfc5217SJeff Kirsher } 1197adfc5217SJeff Kirsher 1198adfc5217SJeff Kirsher static int 1199adfc5217SJeff Kirsher bnx2_copper_linkup(struct bnx2 *bp) 1200adfc5217SJeff Kirsher { 1201adfc5217SJeff Kirsher u32 bmcr; 1202adfc5217SJeff Kirsher 1203adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1204adfc5217SJeff Kirsher if (bmcr & BMCR_ANENABLE) { 1205adfc5217SJeff Kirsher u32 local_adv, remote_adv, common; 1206adfc5217SJeff Kirsher 1207adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_CTRL1000, &local_adv); 1208adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_STAT1000, &remote_adv); 1209adfc5217SJeff Kirsher 1210adfc5217SJeff Kirsher common = local_adv & (remote_adv >> 2); 1211adfc5217SJeff Kirsher if (common & ADVERTISE_1000FULL) { 1212adfc5217SJeff Kirsher bp->line_speed = SPEED_1000; 1213adfc5217SJeff Kirsher bp->duplex = DUPLEX_FULL; 1214adfc5217SJeff Kirsher } 1215adfc5217SJeff Kirsher else if (common & ADVERTISE_1000HALF) { 1216adfc5217SJeff Kirsher bp->line_speed = SPEED_1000; 1217adfc5217SJeff Kirsher bp->duplex = DUPLEX_HALF; 1218adfc5217SJeff Kirsher } 1219adfc5217SJeff Kirsher else { 1220adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_adv, &local_adv); 1221adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); 1222adfc5217SJeff Kirsher 1223adfc5217SJeff Kirsher common = local_adv & remote_adv; 1224adfc5217SJeff Kirsher if (common & ADVERTISE_100FULL) { 1225adfc5217SJeff Kirsher bp->line_speed = SPEED_100; 1226adfc5217SJeff Kirsher bp->duplex = DUPLEX_FULL; 1227adfc5217SJeff Kirsher } 1228adfc5217SJeff Kirsher else if (common & ADVERTISE_100HALF) { 1229adfc5217SJeff Kirsher bp->line_speed = SPEED_100; 1230adfc5217SJeff Kirsher bp->duplex = DUPLEX_HALF; 1231adfc5217SJeff Kirsher } 1232adfc5217SJeff Kirsher else if (common & ADVERTISE_10FULL) { 1233adfc5217SJeff Kirsher bp->line_speed = SPEED_10; 1234adfc5217SJeff Kirsher bp->duplex = DUPLEX_FULL; 1235adfc5217SJeff Kirsher } 1236adfc5217SJeff Kirsher else if (common & ADVERTISE_10HALF) { 1237adfc5217SJeff Kirsher bp->line_speed = SPEED_10; 1238adfc5217SJeff Kirsher bp->duplex = DUPLEX_HALF; 1239adfc5217SJeff Kirsher } 1240adfc5217SJeff Kirsher else { 1241adfc5217SJeff Kirsher bp->line_speed = 0; 1242adfc5217SJeff Kirsher bp->link_up = 0; 1243adfc5217SJeff Kirsher } 1244adfc5217SJeff Kirsher } 1245adfc5217SJeff Kirsher } 1246adfc5217SJeff Kirsher else { 1247adfc5217SJeff Kirsher if (bmcr & BMCR_SPEED100) { 1248adfc5217SJeff Kirsher bp->line_speed = SPEED_100; 1249adfc5217SJeff Kirsher } 1250adfc5217SJeff Kirsher else { 1251adfc5217SJeff Kirsher bp->line_speed = SPEED_10; 1252adfc5217SJeff Kirsher } 1253adfc5217SJeff Kirsher if (bmcr & BMCR_FULLDPLX) { 1254adfc5217SJeff Kirsher bp->duplex = DUPLEX_FULL; 1255adfc5217SJeff Kirsher } 1256adfc5217SJeff Kirsher else { 1257adfc5217SJeff Kirsher bp->duplex = DUPLEX_HALF; 1258adfc5217SJeff Kirsher } 1259adfc5217SJeff Kirsher } 1260adfc5217SJeff Kirsher 1261adfc5217SJeff Kirsher return 0; 1262adfc5217SJeff Kirsher } 1263adfc5217SJeff Kirsher 1264adfc5217SJeff Kirsher static void 1265adfc5217SJeff Kirsher bnx2_init_rx_context(struct bnx2 *bp, u32 cid) 1266adfc5217SJeff Kirsher { 1267adfc5217SJeff Kirsher u32 val, rx_cid_addr = GET_CID_ADDR(cid); 1268adfc5217SJeff Kirsher 1269adfc5217SJeff Kirsher val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 1270adfc5217SJeff Kirsher val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; 1271adfc5217SJeff Kirsher val |= 0x02 << 8; 1272adfc5217SJeff Kirsher 1273adfc5217SJeff Kirsher if (bp->flow_ctrl & FLOW_CTRL_TX) 1274adfc5217SJeff Kirsher val |= BNX2_L2CTX_FLOW_CTRL_ENABLE; 1275adfc5217SJeff Kirsher 1276adfc5217SJeff Kirsher bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); 1277adfc5217SJeff Kirsher } 1278adfc5217SJeff Kirsher 1279adfc5217SJeff Kirsher static void 1280adfc5217SJeff Kirsher bnx2_init_all_rx_contexts(struct bnx2 *bp) 1281adfc5217SJeff Kirsher { 1282adfc5217SJeff Kirsher int i; 1283adfc5217SJeff Kirsher u32 cid; 1284adfc5217SJeff Kirsher 1285adfc5217SJeff Kirsher for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) { 1286adfc5217SJeff Kirsher if (i == 1) 1287adfc5217SJeff Kirsher cid = RX_RSS_CID; 1288adfc5217SJeff Kirsher bnx2_init_rx_context(bp, cid); 1289adfc5217SJeff Kirsher } 1290adfc5217SJeff Kirsher } 1291adfc5217SJeff Kirsher 1292adfc5217SJeff Kirsher static void 1293adfc5217SJeff Kirsher bnx2_set_mac_link(struct bnx2 *bp) 1294adfc5217SJeff Kirsher { 1295adfc5217SJeff Kirsher u32 val; 1296adfc5217SJeff Kirsher 1297adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); 1298adfc5217SJeff Kirsher if (bp->link_up && (bp->line_speed == SPEED_1000) && 1299adfc5217SJeff Kirsher (bp->duplex == DUPLEX_HALF)) { 1300adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); 1301adfc5217SJeff Kirsher } 1302adfc5217SJeff Kirsher 1303adfc5217SJeff Kirsher /* Configure the EMAC mode register. */ 1304adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_EMAC_MODE); 1305adfc5217SJeff Kirsher 1306adfc5217SJeff Kirsher val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | 1307adfc5217SJeff Kirsher BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | 1308adfc5217SJeff Kirsher BNX2_EMAC_MODE_25G_MODE); 1309adfc5217SJeff Kirsher 1310adfc5217SJeff Kirsher if (bp->link_up) { 1311adfc5217SJeff Kirsher switch (bp->line_speed) { 1312adfc5217SJeff Kirsher case SPEED_10: 1313adfc5217SJeff Kirsher if (CHIP_NUM(bp) != CHIP_NUM_5706) { 1314adfc5217SJeff Kirsher val |= BNX2_EMAC_MODE_PORT_MII_10M; 1315adfc5217SJeff Kirsher break; 1316adfc5217SJeff Kirsher } 1317adfc5217SJeff Kirsher /* fall through */ 1318adfc5217SJeff Kirsher case SPEED_100: 1319adfc5217SJeff Kirsher val |= BNX2_EMAC_MODE_PORT_MII; 1320adfc5217SJeff Kirsher break; 1321adfc5217SJeff Kirsher case SPEED_2500: 1322adfc5217SJeff Kirsher val |= BNX2_EMAC_MODE_25G_MODE; 1323adfc5217SJeff Kirsher /* fall through */ 1324adfc5217SJeff Kirsher case SPEED_1000: 1325adfc5217SJeff Kirsher val |= BNX2_EMAC_MODE_PORT_GMII; 1326adfc5217SJeff Kirsher break; 1327adfc5217SJeff Kirsher } 1328adfc5217SJeff Kirsher } 1329adfc5217SJeff Kirsher else { 1330adfc5217SJeff Kirsher val |= BNX2_EMAC_MODE_PORT_GMII; 1331adfc5217SJeff Kirsher } 1332adfc5217SJeff Kirsher 1333adfc5217SJeff Kirsher /* Set the MAC to operate in the appropriate duplex mode. */ 1334adfc5217SJeff Kirsher if (bp->duplex == DUPLEX_HALF) 1335adfc5217SJeff Kirsher val |= BNX2_EMAC_MODE_HALF_DUPLEX; 1336adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MODE, val); 1337adfc5217SJeff Kirsher 1338adfc5217SJeff Kirsher /* Enable/disable rx PAUSE. */ 1339adfc5217SJeff Kirsher bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; 1340adfc5217SJeff Kirsher 1341adfc5217SJeff Kirsher if (bp->flow_ctrl & FLOW_CTRL_RX) 1342adfc5217SJeff Kirsher bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; 1343adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); 1344adfc5217SJeff Kirsher 1345adfc5217SJeff Kirsher /* Enable/disable tx PAUSE. */ 1346adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_EMAC_TX_MODE); 1347adfc5217SJeff Kirsher val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; 1348adfc5217SJeff Kirsher 1349adfc5217SJeff Kirsher if (bp->flow_ctrl & FLOW_CTRL_TX) 1350adfc5217SJeff Kirsher val |= BNX2_EMAC_TX_MODE_FLOW_EN; 1351adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_TX_MODE, val); 1352adfc5217SJeff Kirsher 1353adfc5217SJeff Kirsher /* Acknowledge the interrupt. */ 1354adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); 1355adfc5217SJeff Kirsher 1356adfc5217SJeff Kirsher bnx2_init_all_rx_contexts(bp); 1357adfc5217SJeff Kirsher } 1358adfc5217SJeff Kirsher 1359adfc5217SJeff Kirsher static void 1360adfc5217SJeff Kirsher bnx2_enable_bmsr1(struct bnx2 *bp) 1361adfc5217SJeff Kirsher { 1362adfc5217SJeff Kirsher if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1363adfc5217SJeff Kirsher (CHIP_NUM(bp) == CHIP_NUM_5709)) 1364adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1365adfc5217SJeff Kirsher MII_BNX2_BLK_ADDR_GP_STATUS); 1366adfc5217SJeff Kirsher } 1367adfc5217SJeff Kirsher 1368adfc5217SJeff Kirsher static void 1369adfc5217SJeff Kirsher bnx2_disable_bmsr1(struct bnx2 *bp) 1370adfc5217SJeff Kirsher { 1371adfc5217SJeff Kirsher if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1372adfc5217SJeff Kirsher (CHIP_NUM(bp) == CHIP_NUM_5709)) 1373adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1374adfc5217SJeff Kirsher MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1375adfc5217SJeff Kirsher } 1376adfc5217SJeff Kirsher 1377adfc5217SJeff Kirsher static int 1378adfc5217SJeff Kirsher bnx2_test_and_enable_2g5(struct bnx2 *bp) 1379adfc5217SJeff Kirsher { 1380adfc5217SJeff Kirsher u32 up1; 1381adfc5217SJeff Kirsher int ret = 1; 1382adfc5217SJeff Kirsher 1383adfc5217SJeff Kirsher if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1384adfc5217SJeff Kirsher return 0; 1385adfc5217SJeff Kirsher 1386adfc5217SJeff Kirsher if (bp->autoneg & AUTONEG_SPEED) 1387adfc5217SJeff Kirsher bp->advertising |= ADVERTISED_2500baseX_Full; 1388adfc5217SJeff Kirsher 1389adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) 1390adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); 1391adfc5217SJeff Kirsher 1392adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_up1, &up1); 1393adfc5217SJeff Kirsher if (!(up1 & BCM5708S_UP1_2G5)) { 1394adfc5217SJeff Kirsher up1 |= BCM5708S_UP1_2G5; 1395adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_up1, up1); 1396adfc5217SJeff Kirsher ret = 0; 1397adfc5217SJeff Kirsher } 1398adfc5217SJeff Kirsher 1399adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) 1400adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1401adfc5217SJeff Kirsher MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1402adfc5217SJeff Kirsher 1403adfc5217SJeff Kirsher return ret; 1404adfc5217SJeff Kirsher } 1405adfc5217SJeff Kirsher 1406adfc5217SJeff Kirsher static int 1407adfc5217SJeff Kirsher bnx2_test_and_disable_2g5(struct bnx2 *bp) 1408adfc5217SJeff Kirsher { 1409adfc5217SJeff Kirsher u32 up1; 1410adfc5217SJeff Kirsher int ret = 0; 1411adfc5217SJeff Kirsher 1412adfc5217SJeff Kirsher if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1413adfc5217SJeff Kirsher return 0; 1414adfc5217SJeff Kirsher 1415adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) 1416adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); 1417adfc5217SJeff Kirsher 1418adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_up1, &up1); 1419adfc5217SJeff Kirsher if (up1 & BCM5708S_UP1_2G5) { 1420adfc5217SJeff Kirsher up1 &= ~BCM5708S_UP1_2G5; 1421adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_up1, up1); 1422adfc5217SJeff Kirsher ret = 1; 1423adfc5217SJeff Kirsher } 1424adfc5217SJeff Kirsher 1425adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) 1426adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1427adfc5217SJeff Kirsher MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1428adfc5217SJeff Kirsher 1429adfc5217SJeff Kirsher return ret; 1430adfc5217SJeff Kirsher } 1431adfc5217SJeff Kirsher 1432adfc5217SJeff Kirsher static void 1433adfc5217SJeff Kirsher bnx2_enable_forced_2g5(struct bnx2 *bp) 1434adfc5217SJeff Kirsher { 1435adfc5217SJeff Kirsher u32 uninitialized_var(bmcr); 1436adfc5217SJeff Kirsher int err; 1437adfc5217SJeff Kirsher 1438adfc5217SJeff Kirsher if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1439adfc5217SJeff Kirsher return; 1440adfc5217SJeff Kirsher 1441adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 1442adfc5217SJeff Kirsher u32 val; 1443adfc5217SJeff Kirsher 1444adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1445adfc5217SJeff Kirsher MII_BNX2_BLK_ADDR_SERDES_DIG); 1446adfc5217SJeff Kirsher if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { 1447adfc5217SJeff Kirsher val &= ~MII_BNX2_SD_MISC1_FORCE_MSK; 1448adfc5217SJeff Kirsher val |= MII_BNX2_SD_MISC1_FORCE | 1449adfc5217SJeff Kirsher MII_BNX2_SD_MISC1_FORCE_2_5G; 1450adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); 1451adfc5217SJeff Kirsher } 1452adfc5217SJeff Kirsher 1453adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1454adfc5217SJeff Kirsher MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1455adfc5217SJeff Kirsher err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1456adfc5217SJeff Kirsher 1457adfc5217SJeff Kirsher } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { 1458adfc5217SJeff Kirsher err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1459adfc5217SJeff Kirsher if (!err) 1460adfc5217SJeff Kirsher bmcr |= BCM5708S_BMCR_FORCE_2500; 1461adfc5217SJeff Kirsher } else { 1462adfc5217SJeff Kirsher return; 1463adfc5217SJeff Kirsher } 1464adfc5217SJeff Kirsher 1465adfc5217SJeff Kirsher if (err) 1466adfc5217SJeff Kirsher return; 1467adfc5217SJeff Kirsher 1468adfc5217SJeff Kirsher if (bp->autoneg & AUTONEG_SPEED) { 1469adfc5217SJeff Kirsher bmcr &= ~BMCR_ANENABLE; 1470adfc5217SJeff Kirsher if (bp->req_duplex == DUPLEX_FULL) 1471adfc5217SJeff Kirsher bmcr |= BMCR_FULLDPLX; 1472adfc5217SJeff Kirsher } 1473adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 1474adfc5217SJeff Kirsher } 1475adfc5217SJeff Kirsher 1476adfc5217SJeff Kirsher static void 1477adfc5217SJeff Kirsher bnx2_disable_forced_2g5(struct bnx2 *bp) 1478adfc5217SJeff Kirsher { 1479adfc5217SJeff Kirsher u32 uninitialized_var(bmcr); 1480adfc5217SJeff Kirsher int err; 1481adfc5217SJeff Kirsher 1482adfc5217SJeff Kirsher if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1483adfc5217SJeff Kirsher return; 1484adfc5217SJeff Kirsher 1485adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 1486adfc5217SJeff Kirsher u32 val; 1487adfc5217SJeff Kirsher 1488adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1489adfc5217SJeff Kirsher MII_BNX2_BLK_ADDR_SERDES_DIG); 1490adfc5217SJeff Kirsher if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { 1491adfc5217SJeff Kirsher val &= ~MII_BNX2_SD_MISC1_FORCE; 1492adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); 1493adfc5217SJeff Kirsher } 1494adfc5217SJeff Kirsher 1495adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1496adfc5217SJeff Kirsher MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1497adfc5217SJeff Kirsher err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1498adfc5217SJeff Kirsher 1499adfc5217SJeff Kirsher } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { 1500adfc5217SJeff Kirsher err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1501adfc5217SJeff Kirsher if (!err) 1502adfc5217SJeff Kirsher bmcr &= ~BCM5708S_BMCR_FORCE_2500; 1503adfc5217SJeff Kirsher } else { 1504adfc5217SJeff Kirsher return; 1505adfc5217SJeff Kirsher } 1506adfc5217SJeff Kirsher 1507adfc5217SJeff Kirsher if (err) 1508adfc5217SJeff Kirsher return; 1509adfc5217SJeff Kirsher 1510adfc5217SJeff Kirsher if (bp->autoneg & AUTONEG_SPEED) 1511adfc5217SJeff Kirsher bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART; 1512adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 1513adfc5217SJeff Kirsher } 1514adfc5217SJeff Kirsher 1515adfc5217SJeff Kirsher static void 1516adfc5217SJeff Kirsher bnx2_5706s_force_link_dn(struct bnx2 *bp, int start) 1517adfc5217SJeff Kirsher { 1518adfc5217SJeff Kirsher u32 val; 1519adfc5217SJeff Kirsher 1520adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL); 1521adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); 1522adfc5217SJeff Kirsher if (start) 1523adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); 1524adfc5217SJeff Kirsher else 1525adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); 1526adfc5217SJeff Kirsher } 1527adfc5217SJeff Kirsher 1528adfc5217SJeff Kirsher static int 1529adfc5217SJeff Kirsher bnx2_set_link(struct bnx2 *bp) 1530adfc5217SJeff Kirsher { 1531adfc5217SJeff Kirsher u32 bmsr; 1532adfc5217SJeff Kirsher u8 link_up; 1533adfc5217SJeff Kirsher 1534adfc5217SJeff Kirsher if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) { 1535adfc5217SJeff Kirsher bp->link_up = 1; 1536adfc5217SJeff Kirsher return 0; 1537adfc5217SJeff Kirsher } 1538adfc5217SJeff Kirsher 1539adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 1540adfc5217SJeff Kirsher return 0; 1541adfc5217SJeff Kirsher 1542adfc5217SJeff Kirsher link_up = bp->link_up; 1543adfc5217SJeff Kirsher 1544adfc5217SJeff Kirsher bnx2_enable_bmsr1(bp); 1545adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 1546adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 1547adfc5217SJeff Kirsher bnx2_disable_bmsr1(bp); 1548adfc5217SJeff Kirsher 1549adfc5217SJeff Kirsher if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1550adfc5217SJeff Kirsher (CHIP_NUM(bp) == CHIP_NUM_5706)) { 1551adfc5217SJeff Kirsher u32 val, an_dbg; 1552adfc5217SJeff Kirsher 1553adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { 1554adfc5217SJeff Kirsher bnx2_5706s_force_link_dn(bp, 0); 1555adfc5217SJeff Kirsher bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; 1556adfc5217SJeff Kirsher } 1557adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_EMAC_STATUS); 1558adfc5217SJeff Kirsher 1559adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); 1560adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 1561adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 1562adfc5217SJeff Kirsher 1563adfc5217SJeff Kirsher if ((val & BNX2_EMAC_STATUS_LINK) && 1564adfc5217SJeff Kirsher !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC)) 1565adfc5217SJeff Kirsher bmsr |= BMSR_LSTATUS; 1566adfc5217SJeff Kirsher else 1567adfc5217SJeff Kirsher bmsr &= ~BMSR_LSTATUS; 1568adfc5217SJeff Kirsher } 1569adfc5217SJeff Kirsher 1570adfc5217SJeff Kirsher if (bmsr & BMSR_LSTATUS) { 1571adfc5217SJeff Kirsher bp->link_up = 1; 1572adfc5217SJeff Kirsher 1573adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1574adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5706) 1575adfc5217SJeff Kirsher bnx2_5706s_linkup(bp); 1576adfc5217SJeff Kirsher else if (CHIP_NUM(bp) == CHIP_NUM_5708) 1577adfc5217SJeff Kirsher bnx2_5708s_linkup(bp); 1578adfc5217SJeff Kirsher else if (CHIP_NUM(bp) == CHIP_NUM_5709) 1579adfc5217SJeff Kirsher bnx2_5709s_linkup(bp); 1580adfc5217SJeff Kirsher } 1581adfc5217SJeff Kirsher else { 1582adfc5217SJeff Kirsher bnx2_copper_linkup(bp); 1583adfc5217SJeff Kirsher } 1584adfc5217SJeff Kirsher bnx2_resolve_flow_ctrl(bp); 1585adfc5217SJeff Kirsher } 1586adfc5217SJeff Kirsher else { 1587adfc5217SJeff Kirsher if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1588adfc5217SJeff Kirsher (bp->autoneg & AUTONEG_SPEED)) 1589adfc5217SJeff Kirsher bnx2_disable_forced_2g5(bp); 1590adfc5217SJeff Kirsher 1591adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) { 1592adfc5217SJeff Kirsher u32 bmcr; 1593adfc5217SJeff Kirsher 1594adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1595adfc5217SJeff Kirsher bmcr |= BMCR_ANENABLE; 1596adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 1597adfc5217SJeff Kirsher 1598adfc5217SJeff Kirsher bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; 1599adfc5217SJeff Kirsher } 1600adfc5217SJeff Kirsher bp->link_up = 0; 1601adfc5217SJeff Kirsher } 1602adfc5217SJeff Kirsher 1603adfc5217SJeff Kirsher if (bp->link_up != link_up) { 1604adfc5217SJeff Kirsher bnx2_report_link(bp); 1605adfc5217SJeff Kirsher } 1606adfc5217SJeff Kirsher 1607adfc5217SJeff Kirsher bnx2_set_mac_link(bp); 1608adfc5217SJeff Kirsher 1609adfc5217SJeff Kirsher return 0; 1610adfc5217SJeff Kirsher } 1611adfc5217SJeff Kirsher 1612adfc5217SJeff Kirsher static int 1613adfc5217SJeff Kirsher bnx2_reset_phy(struct bnx2 *bp) 1614adfc5217SJeff Kirsher { 1615adfc5217SJeff Kirsher int i; 1616adfc5217SJeff Kirsher u32 reg; 1617adfc5217SJeff Kirsher 1618adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); 1619adfc5217SJeff Kirsher 1620adfc5217SJeff Kirsher #define PHY_RESET_MAX_WAIT 100 1621adfc5217SJeff Kirsher for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { 1622adfc5217SJeff Kirsher udelay(10); 1623adfc5217SJeff Kirsher 1624adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmcr, ®); 1625adfc5217SJeff Kirsher if (!(reg & BMCR_RESET)) { 1626adfc5217SJeff Kirsher udelay(20); 1627adfc5217SJeff Kirsher break; 1628adfc5217SJeff Kirsher } 1629adfc5217SJeff Kirsher } 1630adfc5217SJeff Kirsher if (i == PHY_RESET_MAX_WAIT) { 1631adfc5217SJeff Kirsher return -EBUSY; 1632adfc5217SJeff Kirsher } 1633adfc5217SJeff Kirsher return 0; 1634adfc5217SJeff Kirsher } 1635adfc5217SJeff Kirsher 1636adfc5217SJeff Kirsher static u32 1637adfc5217SJeff Kirsher bnx2_phy_get_pause_adv(struct bnx2 *bp) 1638adfc5217SJeff Kirsher { 1639adfc5217SJeff Kirsher u32 adv = 0; 1640adfc5217SJeff Kirsher 1641adfc5217SJeff Kirsher if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == 1642adfc5217SJeff Kirsher (FLOW_CTRL_RX | FLOW_CTRL_TX)) { 1643adfc5217SJeff Kirsher 1644adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1645adfc5217SJeff Kirsher adv = ADVERTISE_1000XPAUSE; 1646adfc5217SJeff Kirsher } 1647adfc5217SJeff Kirsher else { 1648adfc5217SJeff Kirsher adv = ADVERTISE_PAUSE_CAP; 1649adfc5217SJeff Kirsher } 1650adfc5217SJeff Kirsher } 1651adfc5217SJeff Kirsher else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { 1652adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1653adfc5217SJeff Kirsher adv = ADVERTISE_1000XPSE_ASYM; 1654adfc5217SJeff Kirsher } 1655adfc5217SJeff Kirsher else { 1656adfc5217SJeff Kirsher adv = ADVERTISE_PAUSE_ASYM; 1657adfc5217SJeff Kirsher } 1658adfc5217SJeff Kirsher } 1659adfc5217SJeff Kirsher else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { 1660adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1661adfc5217SJeff Kirsher adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; 1662adfc5217SJeff Kirsher } 1663adfc5217SJeff Kirsher else { 1664adfc5217SJeff Kirsher adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1665adfc5217SJeff Kirsher } 1666adfc5217SJeff Kirsher } 1667adfc5217SJeff Kirsher return adv; 1668adfc5217SJeff Kirsher } 1669adfc5217SJeff Kirsher 1670adfc5217SJeff Kirsher static int bnx2_fw_sync(struct bnx2 *, u32, int, int); 1671adfc5217SJeff Kirsher 1672adfc5217SJeff Kirsher static int 1673adfc5217SJeff Kirsher bnx2_setup_remote_phy(struct bnx2 *bp, u8 port) 1674adfc5217SJeff Kirsher __releases(&bp->phy_lock) 1675adfc5217SJeff Kirsher __acquires(&bp->phy_lock) 1676adfc5217SJeff Kirsher { 1677adfc5217SJeff Kirsher u32 speed_arg = 0, pause_adv; 1678adfc5217SJeff Kirsher 1679adfc5217SJeff Kirsher pause_adv = bnx2_phy_get_pause_adv(bp); 1680adfc5217SJeff Kirsher 1681adfc5217SJeff Kirsher if (bp->autoneg & AUTONEG_SPEED) { 1682adfc5217SJeff Kirsher speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG; 1683adfc5217SJeff Kirsher if (bp->advertising & ADVERTISED_10baseT_Half) 1684adfc5217SJeff Kirsher speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF; 1685adfc5217SJeff Kirsher if (bp->advertising & ADVERTISED_10baseT_Full) 1686adfc5217SJeff Kirsher speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL; 1687adfc5217SJeff Kirsher if (bp->advertising & ADVERTISED_100baseT_Half) 1688adfc5217SJeff Kirsher speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF; 1689adfc5217SJeff Kirsher if (bp->advertising & ADVERTISED_100baseT_Full) 1690adfc5217SJeff Kirsher speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL; 1691adfc5217SJeff Kirsher if (bp->advertising & ADVERTISED_1000baseT_Full) 1692adfc5217SJeff Kirsher speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL; 1693adfc5217SJeff Kirsher if (bp->advertising & ADVERTISED_2500baseX_Full) 1694adfc5217SJeff Kirsher speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; 1695adfc5217SJeff Kirsher } else { 1696adfc5217SJeff Kirsher if (bp->req_line_speed == SPEED_2500) 1697adfc5217SJeff Kirsher speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; 1698adfc5217SJeff Kirsher else if (bp->req_line_speed == SPEED_1000) 1699adfc5217SJeff Kirsher speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL; 1700adfc5217SJeff Kirsher else if (bp->req_line_speed == SPEED_100) { 1701adfc5217SJeff Kirsher if (bp->req_duplex == DUPLEX_FULL) 1702adfc5217SJeff Kirsher speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL; 1703adfc5217SJeff Kirsher else 1704adfc5217SJeff Kirsher speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF; 1705adfc5217SJeff Kirsher } else if (bp->req_line_speed == SPEED_10) { 1706adfc5217SJeff Kirsher if (bp->req_duplex == DUPLEX_FULL) 1707adfc5217SJeff Kirsher speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL; 1708adfc5217SJeff Kirsher else 1709adfc5217SJeff Kirsher speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF; 1710adfc5217SJeff Kirsher } 1711adfc5217SJeff Kirsher } 1712adfc5217SJeff Kirsher 1713adfc5217SJeff Kirsher if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP)) 1714adfc5217SJeff Kirsher speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE; 1715adfc5217SJeff Kirsher if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM)) 1716adfc5217SJeff Kirsher speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE; 1717adfc5217SJeff Kirsher 1718adfc5217SJeff Kirsher if (port == PORT_TP) 1719adfc5217SJeff Kirsher speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE | 1720adfc5217SJeff Kirsher BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED; 1721adfc5217SJeff Kirsher 1722adfc5217SJeff Kirsher bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg); 1723adfc5217SJeff Kirsher 1724adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 1725adfc5217SJeff Kirsher bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0); 1726adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 1727adfc5217SJeff Kirsher 1728adfc5217SJeff Kirsher return 0; 1729adfc5217SJeff Kirsher } 1730adfc5217SJeff Kirsher 1731adfc5217SJeff Kirsher static int 1732adfc5217SJeff Kirsher bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port) 1733adfc5217SJeff Kirsher __releases(&bp->phy_lock) 1734adfc5217SJeff Kirsher __acquires(&bp->phy_lock) 1735adfc5217SJeff Kirsher { 1736adfc5217SJeff Kirsher u32 adv, bmcr; 1737adfc5217SJeff Kirsher u32 new_adv = 0; 1738adfc5217SJeff Kirsher 1739adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 1740adfc5217SJeff Kirsher return bnx2_setup_remote_phy(bp, port); 1741adfc5217SJeff Kirsher 1742adfc5217SJeff Kirsher if (!(bp->autoneg & AUTONEG_SPEED)) { 1743adfc5217SJeff Kirsher u32 new_bmcr; 1744adfc5217SJeff Kirsher int force_link_down = 0; 1745adfc5217SJeff Kirsher 1746adfc5217SJeff Kirsher if (bp->req_line_speed == SPEED_2500) { 1747adfc5217SJeff Kirsher if (!bnx2_test_and_enable_2g5(bp)) 1748adfc5217SJeff Kirsher force_link_down = 1; 1749adfc5217SJeff Kirsher } else if (bp->req_line_speed == SPEED_1000) { 1750adfc5217SJeff Kirsher if (bnx2_test_and_disable_2g5(bp)) 1751adfc5217SJeff Kirsher force_link_down = 1; 1752adfc5217SJeff Kirsher } 1753adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_adv, &adv); 1754adfc5217SJeff Kirsher adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); 1755adfc5217SJeff Kirsher 1756adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1757adfc5217SJeff Kirsher new_bmcr = bmcr & ~BMCR_ANENABLE; 1758adfc5217SJeff Kirsher new_bmcr |= BMCR_SPEED1000; 1759adfc5217SJeff Kirsher 1760adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 1761adfc5217SJeff Kirsher if (bp->req_line_speed == SPEED_2500) 1762adfc5217SJeff Kirsher bnx2_enable_forced_2g5(bp); 1763adfc5217SJeff Kirsher else if (bp->req_line_speed == SPEED_1000) { 1764adfc5217SJeff Kirsher bnx2_disable_forced_2g5(bp); 1765adfc5217SJeff Kirsher new_bmcr &= ~0x2000; 1766adfc5217SJeff Kirsher } 1767adfc5217SJeff Kirsher 1768adfc5217SJeff Kirsher } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { 1769adfc5217SJeff Kirsher if (bp->req_line_speed == SPEED_2500) 1770adfc5217SJeff Kirsher new_bmcr |= BCM5708S_BMCR_FORCE_2500; 1771adfc5217SJeff Kirsher else 1772adfc5217SJeff Kirsher new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500; 1773adfc5217SJeff Kirsher } 1774adfc5217SJeff Kirsher 1775adfc5217SJeff Kirsher if (bp->req_duplex == DUPLEX_FULL) { 1776adfc5217SJeff Kirsher adv |= ADVERTISE_1000XFULL; 1777adfc5217SJeff Kirsher new_bmcr |= BMCR_FULLDPLX; 1778adfc5217SJeff Kirsher } 1779adfc5217SJeff Kirsher else { 1780adfc5217SJeff Kirsher adv |= ADVERTISE_1000XHALF; 1781adfc5217SJeff Kirsher new_bmcr &= ~BMCR_FULLDPLX; 1782adfc5217SJeff Kirsher } 1783adfc5217SJeff Kirsher if ((new_bmcr != bmcr) || (force_link_down)) { 1784adfc5217SJeff Kirsher /* Force a link down visible on the other side */ 1785adfc5217SJeff Kirsher if (bp->link_up) { 1786adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_adv, adv & 1787adfc5217SJeff Kirsher ~(ADVERTISE_1000XFULL | 1788adfc5217SJeff Kirsher ADVERTISE_1000XHALF)); 1789adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, bmcr | 1790adfc5217SJeff Kirsher BMCR_ANRESTART | BMCR_ANENABLE); 1791adfc5217SJeff Kirsher 1792adfc5217SJeff Kirsher bp->link_up = 0; 1793adfc5217SJeff Kirsher netif_carrier_off(bp->dev); 1794adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); 1795adfc5217SJeff Kirsher bnx2_report_link(bp); 1796adfc5217SJeff Kirsher } 1797adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_adv, adv); 1798adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); 1799adfc5217SJeff Kirsher } else { 1800adfc5217SJeff Kirsher bnx2_resolve_flow_ctrl(bp); 1801adfc5217SJeff Kirsher bnx2_set_mac_link(bp); 1802adfc5217SJeff Kirsher } 1803adfc5217SJeff Kirsher return 0; 1804adfc5217SJeff Kirsher } 1805adfc5217SJeff Kirsher 1806adfc5217SJeff Kirsher bnx2_test_and_enable_2g5(bp); 1807adfc5217SJeff Kirsher 1808adfc5217SJeff Kirsher if (bp->advertising & ADVERTISED_1000baseT_Full) 1809adfc5217SJeff Kirsher new_adv |= ADVERTISE_1000XFULL; 1810adfc5217SJeff Kirsher 1811adfc5217SJeff Kirsher new_adv |= bnx2_phy_get_pause_adv(bp); 1812adfc5217SJeff Kirsher 1813adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_adv, &adv); 1814adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1815adfc5217SJeff Kirsher 1816adfc5217SJeff Kirsher bp->serdes_an_pending = 0; 1817adfc5217SJeff Kirsher if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { 1818adfc5217SJeff Kirsher /* Force a link down visible on the other side */ 1819adfc5217SJeff Kirsher if (bp->link_up) { 1820adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); 1821adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 1822adfc5217SJeff Kirsher msleep(20); 1823adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 1824adfc5217SJeff Kirsher } 1825adfc5217SJeff Kirsher 1826adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_adv, new_adv); 1827adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | 1828adfc5217SJeff Kirsher BMCR_ANENABLE); 1829adfc5217SJeff Kirsher /* Speed up link-up time when the link partner 1830adfc5217SJeff Kirsher * does not autonegotiate which is very common 1831adfc5217SJeff Kirsher * in blade servers. Some blade servers use 1832adfc5217SJeff Kirsher * IPMI for kerboard input and it's important 1833adfc5217SJeff Kirsher * to minimize link disruptions. Autoneg. involves 1834adfc5217SJeff Kirsher * exchanging base pages plus 3 next pages and 1835adfc5217SJeff Kirsher * normally completes in about 120 msec. 1836adfc5217SJeff Kirsher */ 1837adfc5217SJeff Kirsher bp->current_interval = BNX2_SERDES_AN_TIMEOUT; 1838adfc5217SJeff Kirsher bp->serdes_an_pending = 1; 1839adfc5217SJeff Kirsher mod_timer(&bp->timer, jiffies + bp->current_interval); 1840adfc5217SJeff Kirsher } else { 1841adfc5217SJeff Kirsher bnx2_resolve_flow_ctrl(bp); 1842adfc5217SJeff Kirsher bnx2_set_mac_link(bp); 1843adfc5217SJeff Kirsher } 1844adfc5217SJeff Kirsher 1845adfc5217SJeff Kirsher return 0; 1846adfc5217SJeff Kirsher } 1847adfc5217SJeff Kirsher 1848adfc5217SJeff Kirsher #define ETHTOOL_ALL_FIBRE_SPEED \ 1849adfc5217SJeff Kirsher (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \ 1850adfc5217SJeff Kirsher (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\ 1851adfc5217SJeff Kirsher (ADVERTISED_1000baseT_Full) 1852adfc5217SJeff Kirsher 1853adfc5217SJeff Kirsher #define ETHTOOL_ALL_COPPER_SPEED \ 1854adfc5217SJeff Kirsher (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ 1855adfc5217SJeff Kirsher ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ 1856adfc5217SJeff Kirsher ADVERTISED_1000baseT_Full) 1857adfc5217SJeff Kirsher 1858adfc5217SJeff Kirsher #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 1859adfc5217SJeff Kirsher ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) 1860adfc5217SJeff Kirsher 1861adfc5217SJeff Kirsher #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) 1862adfc5217SJeff Kirsher 1863adfc5217SJeff Kirsher static void 1864adfc5217SJeff Kirsher bnx2_set_default_remote_link(struct bnx2 *bp) 1865adfc5217SJeff Kirsher { 1866adfc5217SJeff Kirsher u32 link; 1867adfc5217SJeff Kirsher 1868adfc5217SJeff Kirsher if (bp->phy_port == PORT_TP) 1869adfc5217SJeff Kirsher link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK); 1870adfc5217SJeff Kirsher else 1871adfc5217SJeff Kirsher link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK); 1872adfc5217SJeff Kirsher 1873adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) { 1874adfc5217SJeff Kirsher bp->req_line_speed = 0; 1875adfc5217SJeff Kirsher bp->autoneg |= AUTONEG_SPEED; 1876adfc5217SJeff Kirsher bp->advertising = ADVERTISED_Autoneg; 1877adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) 1878adfc5217SJeff Kirsher bp->advertising |= ADVERTISED_10baseT_Half; 1879adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL) 1880adfc5217SJeff Kirsher bp->advertising |= ADVERTISED_10baseT_Full; 1881adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) 1882adfc5217SJeff Kirsher bp->advertising |= ADVERTISED_100baseT_Half; 1883adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL) 1884adfc5217SJeff Kirsher bp->advertising |= ADVERTISED_100baseT_Full; 1885adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) 1886adfc5217SJeff Kirsher bp->advertising |= ADVERTISED_1000baseT_Full; 1887adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) 1888adfc5217SJeff Kirsher bp->advertising |= ADVERTISED_2500baseX_Full; 1889adfc5217SJeff Kirsher } else { 1890adfc5217SJeff Kirsher bp->autoneg = 0; 1891adfc5217SJeff Kirsher bp->advertising = 0; 1892adfc5217SJeff Kirsher bp->req_duplex = DUPLEX_FULL; 1893adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_SPEED_10) { 1894adfc5217SJeff Kirsher bp->req_line_speed = SPEED_10; 1895adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) 1896adfc5217SJeff Kirsher bp->req_duplex = DUPLEX_HALF; 1897adfc5217SJeff Kirsher } 1898adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_SPEED_100) { 1899adfc5217SJeff Kirsher bp->req_line_speed = SPEED_100; 1900adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) 1901adfc5217SJeff Kirsher bp->req_duplex = DUPLEX_HALF; 1902adfc5217SJeff Kirsher } 1903adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) 1904adfc5217SJeff Kirsher bp->req_line_speed = SPEED_1000; 1905adfc5217SJeff Kirsher if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) 1906adfc5217SJeff Kirsher bp->req_line_speed = SPEED_2500; 1907adfc5217SJeff Kirsher } 1908adfc5217SJeff Kirsher } 1909adfc5217SJeff Kirsher 1910adfc5217SJeff Kirsher static void 1911adfc5217SJeff Kirsher bnx2_set_default_link(struct bnx2 *bp) 1912adfc5217SJeff Kirsher { 1913adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 1914adfc5217SJeff Kirsher bnx2_set_default_remote_link(bp); 1915adfc5217SJeff Kirsher return; 1916adfc5217SJeff Kirsher } 1917adfc5217SJeff Kirsher 1918adfc5217SJeff Kirsher bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; 1919adfc5217SJeff Kirsher bp->req_line_speed = 0; 1920adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1921adfc5217SJeff Kirsher u32 reg; 1922adfc5217SJeff Kirsher 1923adfc5217SJeff Kirsher bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; 1924adfc5217SJeff Kirsher 1925adfc5217SJeff Kirsher reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG); 1926adfc5217SJeff Kirsher reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; 1927adfc5217SJeff Kirsher if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { 1928adfc5217SJeff Kirsher bp->autoneg = 0; 1929adfc5217SJeff Kirsher bp->req_line_speed = bp->line_speed = SPEED_1000; 1930adfc5217SJeff Kirsher bp->req_duplex = DUPLEX_FULL; 1931adfc5217SJeff Kirsher } 1932adfc5217SJeff Kirsher } else 1933adfc5217SJeff Kirsher bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; 1934adfc5217SJeff Kirsher } 1935adfc5217SJeff Kirsher 1936adfc5217SJeff Kirsher static void 1937adfc5217SJeff Kirsher bnx2_send_heart_beat(struct bnx2 *bp) 1938adfc5217SJeff Kirsher { 1939adfc5217SJeff Kirsher u32 msg; 1940adfc5217SJeff Kirsher u32 addr; 1941adfc5217SJeff Kirsher 1942adfc5217SJeff Kirsher spin_lock(&bp->indirect_lock); 1943adfc5217SJeff Kirsher msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK); 1944adfc5217SJeff Kirsher addr = bp->shmem_base + BNX2_DRV_PULSE_MB; 1945adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr); 1946adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg); 1947adfc5217SJeff Kirsher spin_unlock(&bp->indirect_lock); 1948adfc5217SJeff Kirsher } 1949adfc5217SJeff Kirsher 1950adfc5217SJeff Kirsher static void 1951adfc5217SJeff Kirsher bnx2_remote_phy_event(struct bnx2 *bp) 1952adfc5217SJeff Kirsher { 1953adfc5217SJeff Kirsher u32 msg; 1954adfc5217SJeff Kirsher u8 link_up = bp->link_up; 1955adfc5217SJeff Kirsher u8 old_port; 1956adfc5217SJeff Kirsher 1957adfc5217SJeff Kirsher msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); 1958adfc5217SJeff Kirsher 1959adfc5217SJeff Kirsher if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED) 1960adfc5217SJeff Kirsher bnx2_send_heart_beat(bp); 1961adfc5217SJeff Kirsher 1962adfc5217SJeff Kirsher msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED; 1963adfc5217SJeff Kirsher 1964adfc5217SJeff Kirsher if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN) 1965adfc5217SJeff Kirsher bp->link_up = 0; 1966adfc5217SJeff Kirsher else { 1967adfc5217SJeff Kirsher u32 speed; 1968adfc5217SJeff Kirsher 1969adfc5217SJeff Kirsher bp->link_up = 1; 1970adfc5217SJeff Kirsher speed = msg & BNX2_LINK_STATUS_SPEED_MASK; 1971adfc5217SJeff Kirsher bp->duplex = DUPLEX_FULL; 1972adfc5217SJeff Kirsher switch (speed) { 1973adfc5217SJeff Kirsher case BNX2_LINK_STATUS_10HALF: 1974adfc5217SJeff Kirsher bp->duplex = DUPLEX_HALF; 1975adfc5217SJeff Kirsher case BNX2_LINK_STATUS_10FULL: 1976adfc5217SJeff Kirsher bp->line_speed = SPEED_10; 1977adfc5217SJeff Kirsher break; 1978adfc5217SJeff Kirsher case BNX2_LINK_STATUS_100HALF: 1979adfc5217SJeff Kirsher bp->duplex = DUPLEX_HALF; 1980adfc5217SJeff Kirsher case BNX2_LINK_STATUS_100BASE_T4: 1981adfc5217SJeff Kirsher case BNX2_LINK_STATUS_100FULL: 1982adfc5217SJeff Kirsher bp->line_speed = SPEED_100; 1983adfc5217SJeff Kirsher break; 1984adfc5217SJeff Kirsher case BNX2_LINK_STATUS_1000HALF: 1985adfc5217SJeff Kirsher bp->duplex = DUPLEX_HALF; 1986adfc5217SJeff Kirsher case BNX2_LINK_STATUS_1000FULL: 1987adfc5217SJeff Kirsher bp->line_speed = SPEED_1000; 1988adfc5217SJeff Kirsher break; 1989adfc5217SJeff Kirsher case BNX2_LINK_STATUS_2500HALF: 1990adfc5217SJeff Kirsher bp->duplex = DUPLEX_HALF; 1991adfc5217SJeff Kirsher case BNX2_LINK_STATUS_2500FULL: 1992adfc5217SJeff Kirsher bp->line_speed = SPEED_2500; 1993adfc5217SJeff Kirsher break; 1994adfc5217SJeff Kirsher default: 1995adfc5217SJeff Kirsher bp->line_speed = 0; 1996adfc5217SJeff Kirsher break; 1997adfc5217SJeff Kirsher } 1998adfc5217SJeff Kirsher 1999adfc5217SJeff Kirsher bp->flow_ctrl = 0; 2000adfc5217SJeff Kirsher if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != 2001adfc5217SJeff Kirsher (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { 2002adfc5217SJeff Kirsher if (bp->duplex == DUPLEX_FULL) 2003adfc5217SJeff Kirsher bp->flow_ctrl = bp->req_flow_ctrl; 2004adfc5217SJeff Kirsher } else { 2005adfc5217SJeff Kirsher if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED) 2006adfc5217SJeff Kirsher bp->flow_ctrl |= FLOW_CTRL_TX; 2007adfc5217SJeff Kirsher if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED) 2008adfc5217SJeff Kirsher bp->flow_ctrl |= FLOW_CTRL_RX; 2009adfc5217SJeff Kirsher } 2010adfc5217SJeff Kirsher 2011adfc5217SJeff Kirsher old_port = bp->phy_port; 2012adfc5217SJeff Kirsher if (msg & BNX2_LINK_STATUS_SERDES_LINK) 2013adfc5217SJeff Kirsher bp->phy_port = PORT_FIBRE; 2014adfc5217SJeff Kirsher else 2015adfc5217SJeff Kirsher bp->phy_port = PORT_TP; 2016adfc5217SJeff Kirsher 2017adfc5217SJeff Kirsher if (old_port != bp->phy_port) 2018adfc5217SJeff Kirsher bnx2_set_default_link(bp); 2019adfc5217SJeff Kirsher 2020adfc5217SJeff Kirsher } 2021adfc5217SJeff Kirsher if (bp->link_up != link_up) 2022adfc5217SJeff Kirsher bnx2_report_link(bp); 2023adfc5217SJeff Kirsher 2024adfc5217SJeff Kirsher bnx2_set_mac_link(bp); 2025adfc5217SJeff Kirsher } 2026adfc5217SJeff Kirsher 2027adfc5217SJeff Kirsher static int 2028adfc5217SJeff Kirsher bnx2_set_remote_link(struct bnx2 *bp) 2029adfc5217SJeff Kirsher { 2030adfc5217SJeff Kirsher u32 evt_code; 2031adfc5217SJeff Kirsher 2032adfc5217SJeff Kirsher evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB); 2033adfc5217SJeff Kirsher switch (evt_code) { 2034adfc5217SJeff Kirsher case BNX2_FW_EVT_CODE_LINK_EVENT: 2035adfc5217SJeff Kirsher bnx2_remote_phy_event(bp); 2036adfc5217SJeff Kirsher break; 2037adfc5217SJeff Kirsher case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT: 2038adfc5217SJeff Kirsher default: 2039adfc5217SJeff Kirsher bnx2_send_heart_beat(bp); 2040adfc5217SJeff Kirsher break; 2041adfc5217SJeff Kirsher } 2042adfc5217SJeff Kirsher return 0; 2043adfc5217SJeff Kirsher } 2044adfc5217SJeff Kirsher 2045adfc5217SJeff Kirsher static int 2046adfc5217SJeff Kirsher bnx2_setup_copper_phy(struct bnx2 *bp) 2047adfc5217SJeff Kirsher __releases(&bp->phy_lock) 2048adfc5217SJeff Kirsher __acquires(&bp->phy_lock) 2049adfc5217SJeff Kirsher { 2050adfc5217SJeff Kirsher u32 bmcr; 2051adfc5217SJeff Kirsher u32 new_bmcr; 2052adfc5217SJeff Kirsher 2053adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 2054adfc5217SJeff Kirsher 2055adfc5217SJeff Kirsher if (bp->autoneg & AUTONEG_SPEED) { 2056adfc5217SJeff Kirsher u32 adv_reg, adv1000_reg; 205737f07023SMatt Carlson u32 new_adv = 0; 205837f07023SMatt Carlson u32 new_adv1000 = 0; 2059adfc5217SJeff Kirsher 2060adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_adv, &adv_reg); 2061adfc5217SJeff Kirsher adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP | 2062adfc5217SJeff Kirsher ADVERTISE_PAUSE_ASYM); 2063adfc5217SJeff Kirsher 2064adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg); 2065adfc5217SJeff Kirsher adv1000_reg &= PHY_ALL_1000_SPEED; 2066adfc5217SJeff Kirsher 206737f07023SMatt Carlson new_adv = ethtool_adv_to_mii_adv_t(bp->advertising); 206837f07023SMatt Carlson new_adv |= ADVERTISE_CSMA; 206937f07023SMatt Carlson new_adv |= bnx2_phy_get_pause_adv(bp); 2070adfc5217SJeff Kirsher 207137f07023SMatt Carlson new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising); 207228011cf1SMatt Carlson 207337f07023SMatt Carlson if ((adv1000_reg != new_adv1000) || 207437f07023SMatt Carlson (adv_reg != new_adv) || 2075adfc5217SJeff Kirsher ((bmcr & BMCR_ANENABLE) == 0)) { 2076adfc5217SJeff Kirsher 207737f07023SMatt Carlson bnx2_write_phy(bp, bp->mii_adv, new_adv); 207837f07023SMatt Carlson bnx2_write_phy(bp, MII_CTRL1000, new_adv1000); 2079adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | 2080adfc5217SJeff Kirsher BMCR_ANENABLE); 2081adfc5217SJeff Kirsher } 2082adfc5217SJeff Kirsher else if (bp->link_up) { 2083adfc5217SJeff Kirsher /* Flow ctrl may have changed from auto to forced */ 2084adfc5217SJeff Kirsher /* or vice-versa. */ 2085adfc5217SJeff Kirsher 2086adfc5217SJeff Kirsher bnx2_resolve_flow_ctrl(bp); 2087adfc5217SJeff Kirsher bnx2_set_mac_link(bp); 2088adfc5217SJeff Kirsher } 2089adfc5217SJeff Kirsher return 0; 2090adfc5217SJeff Kirsher } 2091adfc5217SJeff Kirsher 2092adfc5217SJeff Kirsher new_bmcr = 0; 2093adfc5217SJeff Kirsher if (bp->req_line_speed == SPEED_100) { 2094adfc5217SJeff Kirsher new_bmcr |= BMCR_SPEED100; 2095adfc5217SJeff Kirsher } 2096adfc5217SJeff Kirsher if (bp->req_duplex == DUPLEX_FULL) { 2097adfc5217SJeff Kirsher new_bmcr |= BMCR_FULLDPLX; 2098adfc5217SJeff Kirsher } 2099adfc5217SJeff Kirsher if (new_bmcr != bmcr) { 2100adfc5217SJeff Kirsher u32 bmsr; 2101adfc5217SJeff Kirsher 2102adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 2103adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 2104adfc5217SJeff Kirsher 2105adfc5217SJeff Kirsher if (bmsr & BMSR_LSTATUS) { 2106adfc5217SJeff Kirsher /* Force link down */ 2107adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); 2108adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 2109adfc5217SJeff Kirsher msleep(50); 2110adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 2111adfc5217SJeff Kirsher 2112adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 2113adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 2114adfc5217SJeff Kirsher } 2115adfc5217SJeff Kirsher 2116adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); 2117adfc5217SJeff Kirsher 2118adfc5217SJeff Kirsher /* Normally, the new speed is setup after the link has 2119adfc5217SJeff Kirsher * gone down and up again. In some cases, link will not go 2120adfc5217SJeff Kirsher * down so we need to set up the new speed here. 2121adfc5217SJeff Kirsher */ 2122adfc5217SJeff Kirsher if (bmsr & BMSR_LSTATUS) { 2123adfc5217SJeff Kirsher bp->line_speed = bp->req_line_speed; 2124adfc5217SJeff Kirsher bp->duplex = bp->req_duplex; 2125adfc5217SJeff Kirsher bnx2_resolve_flow_ctrl(bp); 2126adfc5217SJeff Kirsher bnx2_set_mac_link(bp); 2127adfc5217SJeff Kirsher } 2128adfc5217SJeff Kirsher } else { 2129adfc5217SJeff Kirsher bnx2_resolve_flow_ctrl(bp); 2130adfc5217SJeff Kirsher bnx2_set_mac_link(bp); 2131adfc5217SJeff Kirsher } 2132adfc5217SJeff Kirsher return 0; 2133adfc5217SJeff Kirsher } 2134adfc5217SJeff Kirsher 2135adfc5217SJeff Kirsher static int 2136adfc5217SJeff Kirsher bnx2_setup_phy(struct bnx2 *bp, u8 port) 2137adfc5217SJeff Kirsher __releases(&bp->phy_lock) 2138adfc5217SJeff Kirsher __acquires(&bp->phy_lock) 2139adfc5217SJeff Kirsher { 2140adfc5217SJeff Kirsher if (bp->loopback == MAC_LOOPBACK) 2141adfc5217SJeff Kirsher return 0; 2142adfc5217SJeff Kirsher 2143adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 2144adfc5217SJeff Kirsher return bnx2_setup_serdes_phy(bp, port); 2145adfc5217SJeff Kirsher } 2146adfc5217SJeff Kirsher else { 2147adfc5217SJeff Kirsher return bnx2_setup_copper_phy(bp); 2148adfc5217SJeff Kirsher } 2149adfc5217SJeff Kirsher } 2150adfc5217SJeff Kirsher 2151adfc5217SJeff Kirsher static int 2152adfc5217SJeff Kirsher bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy) 2153adfc5217SJeff Kirsher { 2154adfc5217SJeff Kirsher u32 val; 2155adfc5217SJeff Kirsher 2156adfc5217SJeff Kirsher bp->mii_bmcr = MII_BMCR + 0x10; 2157adfc5217SJeff Kirsher bp->mii_bmsr = MII_BMSR + 0x10; 2158adfc5217SJeff Kirsher bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1; 2159adfc5217SJeff Kirsher bp->mii_adv = MII_ADVERTISE + 0x10; 2160adfc5217SJeff Kirsher bp->mii_lpa = MII_LPA + 0x10; 2161adfc5217SJeff Kirsher bp->mii_up1 = MII_BNX2_OVER1G_UP1; 2162adfc5217SJeff Kirsher 2163adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER); 2164adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); 2165adfc5217SJeff Kirsher 2166adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 2167adfc5217SJeff Kirsher if (reset_phy) 2168adfc5217SJeff Kirsher bnx2_reset_phy(bp); 2169adfc5217SJeff Kirsher 2170adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); 2171adfc5217SJeff Kirsher 2172adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val); 2173adfc5217SJeff Kirsher val &= ~MII_BNX2_SD_1000XCTL1_AUTODET; 2174adfc5217SJeff Kirsher val |= MII_BNX2_SD_1000XCTL1_FIBER; 2175adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); 2176adfc5217SJeff Kirsher 2177adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); 2178adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val); 2179adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) 2180adfc5217SJeff Kirsher val |= BCM5708S_UP1_2G5; 2181adfc5217SJeff Kirsher else 2182adfc5217SJeff Kirsher val &= ~BCM5708S_UP1_2G5; 2183adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); 2184adfc5217SJeff Kirsher 2185adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG); 2186adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val); 2187adfc5217SJeff Kirsher val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM; 2188adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); 2189adfc5217SJeff Kirsher 2190adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0); 2191adfc5217SJeff Kirsher 2192adfc5217SJeff Kirsher val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN | 2193adfc5217SJeff Kirsher MII_BNX2_CL73_BAM_NP_AFT_BP_EN; 2194adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); 2195adfc5217SJeff Kirsher 2196adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 2197adfc5217SJeff Kirsher 2198adfc5217SJeff Kirsher return 0; 2199adfc5217SJeff Kirsher } 2200adfc5217SJeff Kirsher 2201adfc5217SJeff Kirsher static int 2202adfc5217SJeff Kirsher bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy) 2203adfc5217SJeff Kirsher { 2204adfc5217SJeff Kirsher u32 val; 2205adfc5217SJeff Kirsher 2206adfc5217SJeff Kirsher if (reset_phy) 2207adfc5217SJeff Kirsher bnx2_reset_phy(bp); 2208adfc5217SJeff Kirsher 2209adfc5217SJeff Kirsher bp->mii_up1 = BCM5708S_UP1; 2210adfc5217SJeff Kirsher 2211adfc5217SJeff Kirsher bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); 2212adfc5217SJeff Kirsher bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); 2213adfc5217SJeff Kirsher bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); 2214adfc5217SJeff Kirsher 2215adfc5217SJeff Kirsher bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val); 2216adfc5217SJeff Kirsher val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN; 2217adfc5217SJeff Kirsher bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); 2218adfc5217SJeff Kirsher 2219adfc5217SJeff Kirsher bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val); 2220adfc5217SJeff Kirsher val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN; 2221adfc5217SJeff Kirsher bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); 2222adfc5217SJeff Kirsher 2223adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) { 2224adfc5217SJeff Kirsher bnx2_read_phy(bp, BCM5708S_UP1, &val); 2225adfc5217SJeff Kirsher val |= BCM5708S_UP1_2G5; 2226adfc5217SJeff Kirsher bnx2_write_phy(bp, BCM5708S_UP1, val); 2227adfc5217SJeff Kirsher } 2228adfc5217SJeff Kirsher 2229adfc5217SJeff Kirsher if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || 2230adfc5217SJeff Kirsher (CHIP_ID(bp) == CHIP_ID_5708_B0) || 2231adfc5217SJeff Kirsher (CHIP_ID(bp) == CHIP_ID_5708_B1)) { 2232adfc5217SJeff Kirsher /* increase tx signal amplitude */ 2233adfc5217SJeff Kirsher bnx2_write_phy(bp, BCM5708S_BLK_ADDR, 2234adfc5217SJeff Kirsher BCM5708S_BLK_ADDR_TX_MISC); 2235adfc5217SJeff Kirsher bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val); 2236adfc5217SJeff Kirsher val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM; 2237adfc5217SJeff Kirsher bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); 2238adfc5217SJeff Kirsher bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); 2239adfc5217SJeff Kirsher } 2240adfc5217SJeff Kirsher 2241adfc5217SJeff Kirsher val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) & 2242adfc5217SJeff Kirsher BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK; 2243adfc5217SJeff Kirsher 2244adfc5217SJeff Kirsher if (val) { 2245adfc5217SJeff Kirsher u32 is_backplane; 2246adfc5217SJeff Kirsher 2247adfc5217SJeff Kirsher is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); 2248adfc5217SJeff Kirsher if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) { 2249adfc5217SJeff Kirsher bnx2_write_phy(bp, BCM5708S_BLK_ADDR, 2250adfc5217SJeff Kirsher BCM5708S_BLK_ADDR_TX_MISC); 2251adfc5217SJeff Kirsher bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); 2252adfc5217SJeff Kirsher bnx2_write_phy(bp, BCM5708S_BLK_ADDR, 2253adfc5217SJeff Kirsher BCM5708S_BLK_ADDR_DIG); 2254adfc5217SJeff Kirsher } 2255adfc5217SJeff Kirsher } 2256adfc5217SJeff Kirsher return 0; 2257adfc5217SJeff Kirsher } 2258adfc5217SJeff Kirsher 2259adfc5217SJeff Kirsher static int 2260adfc5217SJeff Kirsher bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy) 2261adfc5217SJeff Kirsher { 2262adfc5217SJeff Kirsher if (reset_phy) 2263adfc5217SJeff Kirsher bnx2_reset_phy(bp); 2264adfc5217SJeff Kirsher 2265adfc5217SJeff Kirsher bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; 2266adfc5217SJeff Kirsher 2267adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5706) 2268adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); 2269adfc5217SJeff Kirsher 2270adfc5217SJeff Kirsher if (bp->dev->mtu > 1500) { 2271adfc5217SJeff Kirsher u32 val; 2272adfc5217SJeff Kirsher 2273adfc5217SJeff Kirsher /* Set extended packet length bit */ 2274adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x18, 0x7); 2275adfc5217SJeff Kirsher bnx2_read_phy(bp, 0x18, &val); 2276adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); 2277adfc5217SJeff Kirsher 2278adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x1c, 0x6c00); 2279adfc5217SJeff Kirsher bnx2_read_phy(bp, 0x1c, &val); 2280adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); 2281adfc5217SJeff Kirsher } 2282adfc5217SJeff Kirsher else { 2283adfc5217SJeff Kirsher u32 val; 2284adfc5217SJeff Kirsher 2285adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x18, 0x7); 2286adfc5217SJeff Kirsher bnx2_read_phy(bp, 0x18, &val); 2287adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x18, val & ~0x4007); 2288adfc5217SJeff Kirsher 2289adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x1c, 0x6c00); 2290adfc5217SJeff Kirsher bnx2_read_phy(bp, 0x1c, &val); 2291adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); 2292adfc5217SJeff Kirsher } 2293adfc5217SJeff Kirsher 2294adfc5217SJeff Kirsher return 0; 2295adfc5217SJeff Kirsher } 2296adfc5217SJeff Kirsher 2297adfc5217SJeff Kirsher static int 2298adfc5217SJeff Kirsher bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy) 2299adfc5217SJeff Kirsher { 2300adfc5217SJeff Kirsher u32 val; 2301adfc5217SJeff Kirsher 2302adfc5217SJeff Kirsher if (reset_phy) 2303adfc5217SJeff Kirsher bnx2_reset_phy(bp); 2304adfc5217SJeff Kirsher 2305adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) { 2306adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x18, 0x0c00); 2307adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x17, 0x000a); 2308adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x15, 0x310b); 2309adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x17, 0x201f); 2310adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x15, 0x9506); 2311adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x17, 0x401f); 2312adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x15, 0x14e2); 2313adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x18, 0x0400); 2314adfc5217SJeff Kirsher } 2315adfc5217SJeff Kirsher 2316adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) { 2317adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, 2318adfc5217SJeff Kirsher MII_BNX2_DSP_EXPAND_REG | 0x8); 2319adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); 2320adfc5217SJeff Kirsher val &= ~(1 << 8); 2321adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); 2322adfc5217SJeff Kirsher } 2323adfc5217SJeff Kirsher 2324adfc5217SJeff Kirsher if (bp->dev->mtu > 1500) { 2325adfc5217SJeff Kirsher /* Set extended packet length bit */ 2326adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x18, 0x7); 2327adfc5217SJeff Kirsher bnx2_read_phy(bp, 0x18, &val); 2328adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x18, val | 0x4000); 2329adfc5217SJeff Kirsher 2330adfc5217SJeff Kirsher bnx2_read_phy(bp, 0x10, &val); 2331adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x10, val | 0x1); 2332adfc5217SJeff Kirsher } 2333adfc5217SJeff Kirsher else { 2334adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x18, 0x7); 2335adfc5217SJeff Kirsher bnx2_read_phy(bp, 0x18, &val); 2336adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x18, val & ~0x4007); 2337adfc5217SJeff Kirsher 2338adfc5217SJeff Kirsher bnx2_read_phy(bp, 0x10, &val); 2339adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x10, val & ~0x1); 2340adfc5217SJeff Kirsher } 2341adfc5217SJeff Kirsher 2342adfc5217SJeff Kirsher /* ethernet@wirespeed */ 2343adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x18, 0x7007); 2344adfc5217SJeff Kirsher bnx2_read_phy(bp, 0x18, &val); 2345adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4)); 2346adfc5217SJeff Kirsher return 0; 2347adfc5217SJeff Kirsher } 2348adfc5217SJeff Kirsher 2349adfc5217SJeff Kirsher 2350adfc5217SJeff Kirsher static int 2351adfc5217SJeff Kirsher bnx2_init_phy(struct bnx2 *bp, int reset_phy) 2352adfc5217SJeff Kirsher __releases(&bp->phy_lock) 2353adfc5217SJeff Kirsher __acquires(&bp->phy_lock) 2354adfc5217SJeff Kirsher { 2355adfc5217SJeff Kirsher u32 val; 2356adfc5217SJeff Kirsher int rc = 0; 2357adfc5217SJeff Kirsher 2358adfc5217SJeff Kirsher bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK; 2359adfc5217SJeff Kirsher bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY; 2360adfc5217SJeff Kirsher 2361adfc5217SJeff Kirsher bp->mii_bmcr = MII_BMCR; 2362adfc5217SJeff Kirsher bp->mii_bmsr = MII_BMSR; 2363adfc5217SJeff Kirsher bp->mii_bmsr1 = MII_BMSR; 2364adfc5217SJeff Kirsher bp->mii_adv = MII_ADVERTISE; 2365adfc5217SJeff Kirsher bp->mii_lpa = MII_LPA; 2366adfc5217SJeff Kirsher 2367adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); 2368adfc5217SJeff Kirsher 2369adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 2370adfc5217SJeff Kirsher goto setup_phy; 2371adfc5217SJeff Kirsher 2372adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_PHYSID1, &val); 2373adfc5217SJeff Kirsher bp->phy_id = val << 16; 2374adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_PHYSID2, &val); 2375adfc5217SJeff Kirsher bp->phy_id |= val & 0xffff; 2376adfc5217SJeff Kirsher 2377adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 2378adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5706) 2379adfc5217SJeff Kirsher rc = bnx2_init_5706s_phy(bp, reset_phy); 2380adfc5217SJeff Kirsher else if (CHIP_NUM(bp) == CHIP_NUM_5708) 2381adfc5217SJeff Kirsher rc = bnx2_init_5708s_phy(bp, reset_phy); 2382adfc5217SJeff Kirsher else if (CHIP_NUM(bp) == CHIP_NUM_5709) 2383adfc5217SJeff Kirsher rc = bnx2_init_5709s_phy(bp, reset_phy); 2384adfc5217SJeff Kirsher } 2385adfc5217SJeff Kirsher else { 2386adfc5217SJeff Kirsher rc = bnx2_init_copper_phy(bp, reset_phy); 2387adfc5217SJeff Kirsher } 2388adfc5217SJeff Kirsher 2389adfc5217SJeff Kirsher setup_phy: 2390adfc5217SJeff Kirsher if (!rc) 2391adfc5217SJeff Kirsher rc = bnx2_setup_phy(bp, bp->phy_port); 2392adfc5217SJeff Kirsher 2393adfc5217SJeff Kirsher return rc; 2394adfc5217SJeff Kirsher } 2395adfc5217SJeff Kirsher 2396adfc5217SJeff Kirsher static int 2397adfc5217SJeff Kirsher bnx2_set_mac_loopback(struct bnx2 *bp) 2398adfc5217SJeff Kirsher { 2399adfc5217SJeff Kirsher u32 mac_mode; 2400adfc5217SJeff Kirsher 2401adfc5217SJeff Kirsher mac_mode = REG_RD(bp, BNX2_EMAC_MODE); 2402adfc5217SJeff Kirsher mac_mode &= ~BNX2_EMAC_MODE_PORT; 2403adfc5217SJeff Kirsher mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK; 2404adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MODE, mac_mode); 2405adfc5217SJeff Kirsher bp->link_up = 1; 2406adfc5217SJeff Kirsher return 0; 2407adfc5217SJeff Kirsher } 2408adfc5217SJeff Kirsher 2409adfc5217SJeff Kirsher static int bnx2_test_link(struct bnx2 *); 2410adfc5217SJeff Kirsher 2411adfc5217SJeff Kirsher static int 2412adfc5217SJeff Kirsher bnx2_set_phy_loopback(struct bnx2 *bp) 2413adfc5217SJeff Kirsher { 2414adfc5217SJeff Kirsher u32 mac_mode; 2415adfc5217SJeff Kirsher int rc, i; 2416adfc5217SJeff Kirsher 2417adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 2418adfc5217SJeff Kirsher rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | 2419adfc5217SJeff Kirsher BMCR_SPEED1000); 2420adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 2421adfc5217SJeff Kirsher if (rc) 2422adfc5217SJeff Kirsher return rc; 2423adfc5217SJeff Kirsher 2424adfc5217SJeff Kirsher for (i = 0; i < 10; i++) { 2425adfc5217SJeff Kirsher if (bnx2_test_link(bp) == 0) 2426adfc5217SJeff Kirsher break; 2427adfc5217SJeff Kirsher msleep(100); 2428adfc5217SJeff Kirsher } 2429adfc5217SJeff Kirsher 2430adfc5217SJeff Kirsher mac_mode = REG_RD(bp, BNX2_EMAC_MODE); 2431adfc5217SJeff Kirsher mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | 2432adfc5217SJeff Kirsher BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | 2433adfc5217SJeff Kirsher BNX2_EMAC_MODE_25G_MODE); 2434adfc5217SJeff Kirsher 2435adfc5217SJeff Kirsher mac_mode |= BNX2_EMAC_MODE_PORT_GMII; 2436adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MODE, mac_mode); 2437adfc5217SJeff Kirsher bp->link_up = 1; 2438adfc5217SJeff Kirsher return 0; 2439adfc5217SJeff Kirsher } 2440adfc5217SJeff Kirsher 2441adfc5217SJeff Kirsher static void 2442adfc5217SJeff Kirsher bnx2_dump_mcp_state(struct bnx2 *bp) 2443adfc5217SJeff Kirsher { 2444adfc5217SJeff Kirsher struct net_device *dev = bp->dev; 2445adfc5217SJeff Kirsher u32 mcp_p0, mcp_p1; 2446adfc5217SJeff Kirsher 2447adfc5217SJeff Kirsher netdev_err(dev, "<--- start MCP states dump --->\n"); 2448adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 2449adfc5217SJeff Kirsher mcp_p0 = BNX2_MCP_STATE_P0; 2450adfc5217SJeff Kirsher mcp_p1 = BNX2_MCP_STATE_P1; 2451adfc5217SJeff Kirsher } else { 2452adfc5217SJeff Kirsher mcp_p0 = BNX2_MCP_STATE_P0_5708; 2453adfc5217SJeff Kirsher mcp_p1 = BNX2_MCP_STATE_P1_5708; 2454adfc5217SJeff Kirsher } 2455adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n", 2456adfc5217SJeff Kirsher bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1)); 2457adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n", 2458adfc5217SJeff Kirsher bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE), 2459adfc5217SJeff Kirsher bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE), 2460adfc5217SJeff Kirsher bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK)); 2461adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n", 2462adfc5217SJeff Kirsher bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER), 2463adfc5217SJeff Kirsher bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER), 2464adfc5217SJeff Kirsher bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION)); 2465adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: shmem states:\n"); 2466adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]", 2467adfc5217SJeff Kirsher bnx2_shmem_rd(bp, BNX2_DRV_MB), 2468adfc5217SJeff Kirsher bnx2_shmem_rd(bp, BNX2_FW_MB), 2469adfc5217SJeff Kirsher bnx2_shmem_rd(bp, BNX2_LINK_STATUS)); 2470adfc5217SJeff Kirsher pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB)); 2471adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]", 2472adfc5217SJeff Kirsher bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE), 2473adfc5217SJeff Kirsher bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE)); 2474adfc5217SJeff Kirsher pr_cont(" condition[%08x]\n", 2475adfc5217SJeff Kirsher bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION)); 2476adfc5217SJeff Kirsher DP_SHMEM_LINE(bp, 0x3cc); 2477adfc5217SJeff Kirsher DP_SHMEM_LINE(bp, 0x3dc); 2478adfc5217SJeff Kirsher DP_SHMEM_LINE(bp, 0x3ec); 2479adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc)); 2480adfc5217SJeff Kirsher netdev_err(dev, "<--- end MCP states dump --->\n"); 2481adfc5217SJeff Kirsher } 2482adfc5217SJeff Kirsher 2483adfc5217SJeff Kirsher static int 2484adfc5217SJeff Kirsher bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent) 2485adfc5217SJeff Kirsher { 2486adfc5217SJeff Kirsher int i; 2487adfc5217SJeff Kirsher u32 val; 2488adfc5217SJeff Kirsher 2489adfc5217SJeff Kirsher bp->fw_wr_seq++; 2490adfc5217SJeff Kirsher msg_data |= bp->fw_wr_seq; 2491adfc5217SJeff Kirsher 2492adfc5217SJeff Kirsher bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); 2493adfc5217SJeff Kirsher 2494adfc5217SJeff Kirsher if (!ack) 2495adfc5217SJeff Kirsher return 0; 2496adfc5217SJeff Kirsher 2497adfc5217SJeff Kirsher /* wait for an acknowledgement. */ 2498adfc5217SJeff Kirsher for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) { 2499adfc5217SJeff Kirsher msleep(10); 2500adfc5217SJeff Kirsher 2501adfc5217SJeff Kirsher val = bnx2_shmem_rd(bp, BNX2_FW_MB); 2502adfc5217SJeff Kirsher 2503adfc5217SJeff Kirsher if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) 2504adfc5217SJeff Kirsher break; 2505adfc5217SJeff Kirsher } 2506adfc5217SJeff Kirsher if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0) 2507adfc5217SJeff Kirsher return 0; 2508adfc5217SJeff Kirsher 2509adfc5217SJeff Kirsher /* If we timed out, inform the firmware that this is the case. */ 2510adfc5217SJeff Kirsher if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) { 2511adfc5217SJeff Kirsher msg_data &= ~BNX2_DRV_MSG_CODE; 2512adfc5217SJeff Kirsher msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; 2513adfc5217SJeff Kirsher 2514adfc5217SJeff Kirsher bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); 2515adfc5217SJeff Kirsher if (!silent) { 2516adfc5217SJeff Kirsher pr_err("fw sync timeout, reset code = %x\n", msg_data); 2517adfc5217SJeff Kirsher bnx2_dump_mcp_state(bp); 2518adfc5217SJeff Kirsher } 2519adfc5217SJeff Kirsher 2520adfc5217SJeff Kirsher return -EBUSY; 2521adfc5217SJeff Kirsher } 2522adfc5217SJeff Kirsher 2523adfc5217SJeff Kirsher if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK) 2524adfc5217SJeff Kirsher return -EIO; 2525adfc5217SJeff Kirsher 2526adfc5217SJeff Kirsher return 0; 2527adfc5217SJeff Kirsher } 2528adfc5217SJeff Kirsher 2529adfc5217SJeff Kirsher static int 2530adfc5217SJeff Kirsher bnx2_init_5709_context(struct bnx2 *bp) 2531adfc5217SJeff Kirsher { 2532adfc5217SJeff Kirsher int i, ret = 0; 2533adfc5217SJeff Kirsher u32 val; 2534adfc5217SJeff Kirsher 2535adfc5217SJeff Kirsher val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12); 2536adfc5217SJeff Kirsher val |= (BCM_PAGE_BITS - 8) << 16; 2537adfc5217SJeff Kirsher REG_WR(bp, BNX2_CTX_COMMAND, val); 2538adfc5217SJeff Kirsher for (i = 0; i < 10; i++) { 2539adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_CTX_COMMAND); 2540adfc5217SJeff Kirsher if (!(val & BNX2_CTX_COMMAND_MEM_INIT)) 2541adfc5217SJeff Kirsher break; 2542adfc5217SJeff Kirsher udelay(2); 2543adfc5217SJeff Kirsher } 2544adfc5217SJeff Kirsher if (val & BNX2_CTX_COMMAND_MEM_INIT) 2545adfc5217SJeff Kirsher return -EBUSY; 2546adfc5217SJeff Kirsher 2547adfc5217SJeff Kirsher for (i = 0; i < bp->ctx_pages; i++) { 2548adfc5217SJeff Kirsher int j; 2549adfc5217SJeff Kirsher 2550adfc5217SJeff Kirsher if (bp->ctx_blk[i]) 2551adfc5217SJeff Kirsher memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE); 2552adfc5217SJeff Kirsher else 2553adfc5217SJeff Kirsher return -ENOMEM; 2554adfc5217SJeff Kirsher 2555adfc5217SJeff Kirsher REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0, 2556adfc5217SJeff Kirsher (bp->ctx_blk_mapping[i] & 0xffffffff) | 2557adfc5217SJeff Kirsher BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID); 2558adfc5217SJeff Kirsher REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1, 2559adfc5217SJeff Kirsher (u64) bp->ctx_blk_mapping[i] >> 32); 2560adfc5217SJeff Kirsher REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i | 2561adfc5217SJeff Kirsher BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 2562adfc5217SJeff Kirsher for (j = 0; j < 10; j++) { 2563adfc5217SJeff Kirsher 2564adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL); 2565adfc5217SJeff Kirsher if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) 2566adfc5217SJeff Kirsher break; 2567adfc5217SJeff Kirsher udelay(5); 2568adfc5217SJeff Kirsher } 2569adfc5217SJeff Kirsher if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) { 2570adfc5217SJeff Kirsher ret = -EBUSY; 2571adfc5217SJeff Kirsher break; 2572adfc5217SJeff Kirsher } 2573adfc5217SJeff Kirsher } 2574adfc5217SJeff Kirsher return ret; 2575adfc5217SJeff Kirsher } 2576adfc5217SJeff Kirsher 2577adfc5217SJeff Kirsher static void 2578adfc5217SJeff Kirsher bnx2_init_context(struct bnx2 *bp) 2579adfc5217SJeff Kirsher { 2580adfc5217SJeff Kirsher u32 vcid; 2581adfc5217SJeff Kirsher 2582adfc5217SJeff Kirsher vcid = 96; 2583adfc5217SJeff Kirsher while (vcid) { 2584adfc5217SJeff Kirsher u32 vcid_addr, pcid_addr, offset; 2585adfc5217SJeff Kirsher int i; 2586adfc5217SJeff Kirsher 2587adfc5217SJeff Kirsher vcid--; 2588adfc5217SJeff Kirsher 2589adfc5217SJeff Kirsher if (CHIP_ID(bp) == CHIP_ID_5706_A0) { 2590adfc5217SJeff Kirsher u32 new_vcid; 2591adfc5217SJeff Kirsher 2592adfc5217SJeff Kirsher vcid_addr = GET_PCID_ADDR(vcid); 2593adfc5217SJeff Kirsher if (vcid & 0x8) { 2594adfc5217SJeff Kirsher new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7); 2595adfc5217SJeff Kirsher } 2596adfc5217SJeff Kirsher else { 2597adfc5217SJeff Kirsher new_vcid = vcid; 2598adfc5217SJeff Kirsher } 2599adfc5217SJeff Kirsher pcid_addr = GET_PCID_ADDR(new_vcid); 2600adfc5217SJeff Kirsher } 2601adfc5217SJeff Kirsher else { 2602adfc5217SJeff Kirsher vcid_addr = GET_CID_ADDR(vcid); 2603adfc5217SJeff Kirsher pcid_addr = vcid_addr; 2604adfc5217SJeff Kirsher } 2605adfc5217SJeff Kirsher 2606adfc5217SJeff Kirsher for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) { 2607adfc5217SJeff Kirsher vcid_addr += (i << PHY_CTX_SHIFT); 2608adfc5217SJeff Kirsher pcid_addr += (i << PHY_CTX_SHIFT); 2609adfc5217SJeff Kirsher 2610adfc5217SJeff Kirsher REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); 2611adfc5217SJeff Kirsher REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); 2612adfc5217SJeff Kirsher 2613adfc5217SJeff Kirsher /* Zero out the context. */ 2614adfc5217SJeff Kirsher for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) 2615adfc5217SJeff Kirsher bnx2_ctx_wr(bp, vcid_addr, offset, 0); 2616adfc5217SJeff Kirsher } 2617adfc5217SJeff Kirsher } 2618adfc5217SJeff Kirsher } 2619adfc5217SJeff Kirsher 2620adfc5217SJeff Kirsher static int 2621adfc5217SJeff Kirsher bnx2_alloc_bad_rbuf(struct bnx2 *bp) 2622adfc5217SJeff Kirsher { 2623adfc5217SJeff Kirsher u16 *good_mbuf; 2624adfc5217SJeff Kirsher u32 good_mbuf_cnt; 2625adfc5217SJeff Kirsher u32 val; 2626adfc5217SJeff Kirsher 2627adfc5217SJeff Kirsher good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL); 2628adfc5217SJeff Kirsher if (good_mbuf == NULL) { 2629adfc5217SJeff Kirsher pr_err("Failed to allocate memory in %s\n", __func__); 2630adfc5217SJeff Kirsher return -ENOMEM; 2631adfc5217SJeff Kirsher } 2632adfc5217SJeff Kirsher 2633adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 2634adfc5217SJeff Kirsher BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); 2635adfc5217SJeff Kirsher 2636adfc5217SJeff Kirsher good_mbuf_cnt = 0; 2637adfc5217SJeff Kirsher 2638adfc5217SJeff Kirsher /* Allocate a bunch of mbufs and save the good ones in an array. */ 2639adfc5217SJeff Kirsher val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); 2640adfc5217SJeff Kirsher while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { 2641adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND, 2642adfc5217SJeff Kirsher BNX2_RBUF_COMMAND_ALLOC_REQ); 2643adfc5217SJeff Kirsher 2644adfc5217SJeff Kirsher val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC); 2645adfc5217SJeff Kirsher 2646adfc5217SJeff Kirsher val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; 2647adfc5217SJeff Kirsher 2648adfc5217SJeff Kirsher /* The addresses with Bit 9 set are bad memory blocks. */ 2649adfc5217SJeff Kirsher if (!(val & (1 << 9))) { 2650adfc5217SJeff Kirsher good_mbuf[good_mbuf_cnt] = (u16) val; 2651adfc5217SJeff Kirsher good_mbuf_cnt++; 2652adfc5217SJeff Kirsher } 2653adfc5217SJeff Kirsher 2654adfc5217SJeff Kirsher val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); 2655adfc5217SJeff Kirsher } 2656adfc5217SJeff Kirsher 2657adfc5217SJeff Kirsher /* Free the good ones back to the mbuf pool thus discarding 2658adfc5217SJeff Kirsher * all the bad ones. */ 2659adfc5217SJeff Kirsher while (good_mbuf_cnt) { 2660adfc5217SJeff Kirsher good_mbuf_cnt--; 2661adfc5217SJeff Kirsher 2662adfc5217SJeff Kirsher val = good_mbuf[good_mbuf_cnt]; 2663adfc5217SJeff Kirsher val = (val << 9) | val | 1; 2664adfc5217SJeff Kirsher 2665adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val); 2666adfc5217SJeff Kirsher } 2667adfc5217SJeff Kirsher kfree(good_mbuf); 2668adfc5217SJeff Kirsher return 0; 2669adfc5217SJeff Kirsher } 2670adfc5217SJeff Kirsher 2671adfc5217SJeff Kirsher static void 2672adfc5217SJeff Kirsher bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos) 2673adfc5217SJeff Kirsher { 2674adfc5217SJeff Kirsher u32 val; 2675adfc5217SJeff Kirsher 2676adfc5217SJeff Kirsher val = (mac_addr[0] << 8) | mac_addr[1]; 2677adfc5217SJeff Kirsher 2678adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val); 2679adfc5217SJeff Kirsher 2680adfc5217SJeff Kirsher val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 2681adfc5217SJeff Kirsher (mac_addr[4] << 8) | mac_addr[5]; 2682adfc5217SJeff Kirsher 2683adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val); 2684adfc5217SJeff Kirsher } 2685adfc5217SJeff Kirsher 2686adfc5217SJeff Kirsher static inline int 2687adfc5217SJeff Kirsher bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp) 2688adfc5217SJeff Kirsher { 2689adfc5217SJeff Kirsher dma_addr_t mapping; 2690adfc5217SJeff Kirsher struct sw_pg *rx_pg = &rxr->rx_pg_ring[index]; 2691adfc5217SJeff Kirsher struct rx_bd *rxbd = 2692adfc5217SJeff Kirsher &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)]; 2693adfc5217SJeff Kirsher struct page *page = alloc_page(gfp); 2694adfc5217SJeff Kirsher 2695adfc5217SJeff Kirsher if (!page) 2696adfc5217SJeff Kirsher return -ENOMEM; 2697adfc5217SJeff Kirsher mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE, 2698adfc5217SJeff Kirsher PCI_DMA_FROMDEVICE); 2699adfc5217SJeff Kirsher if (dma_mapping_error(&bp->pdev->dev, mapping)) { 2700adfc5217SJeff Kirsher __free_page(page); 2701adfc5217SJeff Kirsher return -EIO; 2702adfc5217SJeff Kirsher } 2703adfc5217SJeff Kirsher 2704adfc5217SJeff Kirsher rx_pg->page = page; 2705adfc5217SJeff Kirsher dma_unmap_addr_set(rx_pg, mapping, mapping); 2706adfc5217SJeff Kirsher rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; 2707adfc5217SJeff Kirsher rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; 2708adfc5217SJeff Kirsher return 0; 2709adfc5217SJeff Kirsher } 2710adfc5217SJeff Kirsher 2711adfc5217SJeff Kirsher static void 2712adfc5217SJeff Kirsher bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index) 2713adfc5217SJeff Kirsher { 2714adfc5217SJeff Kirsher struct sw_pg *rx_pg = &rxr->rx_pg_ring[index]; 2715adfc5217SJeff Kirsher struct page *page = rx_pg->page; 2716adfc5217SJeff Kirsher 2717adfc5217SJeff Kirsher if (!page) 2718adfc5217SJeff Kirsher return; 2719adfc5217SJeff Kirsher 2720adfc5217SJeff Kirsher dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping), 2721adfc5217SJeff Kirsher PAGE_SIZE, PCI_DMA_FROMDEVICE); 2722adfc5217SJeff Kirsher 2723adfc5217SJeff Kirsher __free_page(page); 2724adfc5217SJeff Kirsher rx_pg->page = NULL; 2725adfc5217SJeff Kirsher } 2726adfc5217SJeff Kirsher 2727adfc5217SJeff Kirsher static inline int 2728dd2bc8e9SEric Dumazet bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp) 2729adfc5217SJeff Kirsher { 2730dd2bc8e9SEric Dumazet u8 *data; 2731adfc5217SJeff Kirsher struct sw_bd *rx_buf = &rxr->rx_buf_ring[index]; 2732adfc5217SJeff Kirsher dma_addr_t mapping; 2733adfc5217SJeff Kirsher struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)]; 2734adfc5217SJeff Kirsher 2735dd2bc8e9SEric Dumazet data = kmalloc(bp->rx_buf_size, gfp); 2736dd2bc8e9SEric Dumazet if (!data) 2737adfc5217SJeff Kirsher return -ENOMEM; 2738adfc5217SJeff Kirsher 2739dd2bc8e9SEric Dumazet mapping = dma_map_single(&bp->pdev->dev, 2740dd2bc8e9SEric Dumazet get_l2_fhdr(data), 2741dd2bc8e9SEric Dumazet bp->rx_buf_use_size, 2742adfc5217SJeff Kirsher PCI_DMA_FROMDEVICE); 2743adfc5217SJeff Kirsher if (dma_mapping_error(&bp->pdev->dev, mapping)) { 2744dd2bc8e9SEric Dumazet kfree(data); 2745adfc5217SJeff Kirsher return -EIO; 2746adfc5217SJeff Kirsher } 2747adfc5217SJeff Kirsher 2748dd2bc8e9SEric Dumazet rx_buf->data = data; 2749adfc5217SJeff Kirsher dma_unmap_addr_set(rx_buf, mapping, mapping); 2750adfc5217SJeff Kirsher 2751adfc5217SJeff Kirsher rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; 2752adfc5217SJeff Kirsher rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; 2753adfc5217SJeff Kirsher 2754adfc5217SJeff Kirsher rxr->rx_prod_bseq += bp->rx_buf_use_size; 2755adfc5217SJeff Kirsher 2756adfc5217SJeff Kirsher return 0; 2757adfc5217SJeff Kirsher } 2758adfc5217SJeff Kirsher 2759adfc5217SJeff Kirsher static int 2760adfc5217SJeff Kirsher bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event) 2761adfc5217SJeff Kirsher { 2762adfc5217SJeff Kirsher struct status_block *sblk = bnapi->status_blk.msi; 2763adfc5217SJeff Kirsher u32 new_link_state, old_link_state; 2764adfc5217SJeff Kirsher int is_set = 1; 2765adfc5217SJeff Kirsher 2766adfc5217SJeff Kirsher new_link_state = sblk->status_attn_bits & event; 2767adfc5217SJeff Kirsher old_link_state = sblk->status_attn_bits_ack & event; 2768adfc5217SJeff Kirsher if (new_link_state != old_link_state) { 2769adfc5217SJeff Kirsher if (new_link_state) 2770adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event); 2771adfc5217SJeff Kirsher else 2772adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event); 2773adfc5217SJeff Kirsher } else 2774adfc5217SJeff Kirsher is_set = 0; 2775adfc5217SJeff Kirsher 2776adfc5217SJeff Kirsher return is_set; 2777adfc5217SJeff Kirsher } 2778adfc5217SJeff Kirsher 2779adfc5217SJeff Kirsher static void 2780adfc5217SJeff Kirsher bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi) 2781adfc5217SJeff Kirsher { 2782adfc5217SJeff Kirsher spin_lock(&bp->phy_lock); 2783adfc5217SJeff Kirsher 2784adfc5217SJeff Kirsher if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) 2785adfc5217SJeff Kirsher bnx2_set_link(bp); 2786adfc5217SJeff Kirsher if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT)) 2787adfc5217SJeff Kirsher bnx2_set_remote_link(bp); 2788adfc5217SJeff Kirsher 2789adfc5217SJeff Kirsher spin_unlock(&bp->phy_lock); 2790adfc5217SJeff Kirsher 2791adfc5217SJeff Kirsher } 2792adfc5217SJeff Kirsher 2793adfc5217SJeff Kirsher static inline u16 2794adfc5217SJeff Kirsher bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi) 2795adfc5217SJeff Kirsher { 2796adfc5217SJeff Kirsher u16 cons; 2797adfc5217SJeff Kirsher 2798adfc5217SJeff Kirsher /* Tell compiler that status block fields can change. */ 2799adfc5217SJeff Kirsher barrier(); 2800adfc5217SJeff Kirsher cons = *bnapi->hw_tx_cons_ptr; 2801adfc5217SJeff Kirsher barrier(); 2802adfc5217SJeff Kirsher if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT)) 2803adfc5217SJeff Kirsher cons++; 2804adfc5217SJeff Kirsher return cons; 2805adfc5217SJeff Kirsher } 2806adfc5217SJeff Kirsher 2807adfc5217SJeff Kirsher static int 2808adfc5217SJeff Kirsher bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) 2809adfc5217SJeff Kirsher { 2810adfc5217SJeff Kirsher struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 2811adfc5217SJeff Kirsher u16 hw_cons, sw_cons, sw_ring_cons; 2812adfc5217SJeff Kirsher int tx_pkt = 0, index; 2813e9831909SEric Dumazet unsigned int tx_bytes = 0; 2814adfc5217SJeff Kirsher struct netdev_queue *txq; 2815adfc5217SJeff Kirsher 2816adfc5217SJeff Kirsher index = (bnapi - bp->bnx2_napi); 2817adfc5217SJeff Kirsher txq = netdev_get_tx_queue(bp->dev, index); 2818adfc5217SJeff Kirsher 2819adfc5217SJeff Kirsher hw_cons = bnx2_get_hw_tx_cons(bnapi); 2820adfc5217SJeff Kirsher sw_cons = txr->tx_cons; 2821adfc5217SJeff Kirsher 2822adfc5217SJeff Kirsher while (sw_cons != hw_cons) { 2823adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 2824adfc5217SJeff Kirsher struct sk_buff *skb; 2825adfc5217SJeff Kirsher int i, last; 2826adfc5217SJeff Kirsher 2827adfc5217SJeff Kirsher sw_ring_cons = TX_RING_IDX(sw_cons); 2828adfc5217SJeff Kirsher 2829adfc5217SJeff Kirsher tx_buf = &txr->tx_buf_ring[sw_ring_cons]; 2830adfc5217SJeff Kirsher skb = tx_buf->skb; 2831adfc5217SJeff Kirsher 2832adfc5217SJeff Kirsher /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */ 2833adfc5217SJeff Kirsher prefetch(&skb->end); 2834adfc5217SJeff Kirsher 2835adfc5217SJeff Kirsher /* partial BD completions possible with TSO packets */ 2836adfc5217SJeff Kirsher if (tx_buf->is_gso) { 2837adfc5217SJeff Kirsher u16 last_idx, last_ring_idx; 2838adfc5217SJeff Kirsher 2839adfc5217SJeff Kirsher last_idx = sw_cons + tx_buf->nr_frags + 1; 2840adfc5217SJeff Kirsher last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1; 2841adfc5217SJeff Kirsher if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) { 2842adfc5217SJeff Kirsher last_idx++; 2843adfc5217SJeff Kirsher } 2844adfc5217SJeff Kirsher if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { 2845adfc5217SJeff Kirsher break; 2846adfc5217SJeff Kirsher } 2847adfc5217SJeff Kirsher } 2848adfc5217SJeff Kirsher 2849adfc5217SJeff Kirsher dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), 2850adfc5217SJeff Kirsher skb_headlen(skb), PCI_DMA_TODEVICE); 2851adfc5217SJeff Kirsher 2852adfc5217SJeff Kirsher tx_buf->skb = NULL; 2853adfc5217SJeff Kirsher last = tx_buf->nr_frags; 2854adfc5217SJeff Kirsher 2855adfc5217SJeff Kirsher for (i = 0; i < last; i++) { 2856adfc5217SJeff Kirsher sw_cons = NEXT_TX_BD(sw_cons); 2857adfc5217SJeff Kirsher 2858adfc5217SJeff Kirsher dma_unmap_page(&bp->pdev->dev, 2859adfc5217SJeff Kirsher dma_unmap_addr( 2860adfc5217SJeff Kirsher &txr->tx_buf_ring[TX_RING_IDX(sw_cons)], 2861adfc5217SJeff Kirsher mapping), 28629e903e08SEric Dumazet skb_frag_size(&skb_shinfo(skb)->frags[i]), 2863adfc5217SJeff Kirsher PCI_DMA_TODEVICE); 2864adfc5217SJeff Kirsher } 2865adfc5217SJeff Kirsher 2866adfc5217SJeff Kirsher sw_cons = NEXT_TX_BD(sw_cons); 2867adfc5217SJeff Kirsher 2868e9831909SEric Dumazet tx_bytes += skb->len; 2869adfc5217SJeff Kirsher dev_kfree_skb(skb); 2870adfc5217SJeff Kirsher tx_pkt++; 2871adfc5217SJeff Kirsher if (tx_pkt == budget) 2872adfc5217SJeff Kirsher break; 2873adfc5217SJeff Kirsher 2874adfc5217SJeff Kirsher if (hw_cons == sw_cons) 2875adfc5217SJeff Kirsher hw_cons = bnx2_get_hw_tx_cons(bnapi); 2876adfc5217SJeff Kirsher } 2877adfc5217SJeff Kirsher 2878e9831909SEric Dumazet netdev_tx_completed_queue(txq, tx_pkt, tx_bytes); 2879adfc5217SJeff Kirsher txr->hw_tx_cons = hw_cons; 2880adfc5217SJeff Kirsher txr->tx_cons = sw_cons; 2881adfc5217SJeff Kirsher 2882adfc5217SJeff Kirsher /* Need to make the tx_cons update visible to bnx2_start_xmit() 2883adfc5217SJeff Kirsher * before checking for netif_tx_queue_stopped(). Without the 2884adfc5217SJeff Kirsher * memory barrier, there is a small possibility that bnx2_start_xmit() 2885adfc5217SJeff Kirsher * will miss it and cause the queue to be stopped forever. 2886adfc5217SJeff Kirsher */ 2887adfc5217SJeff Kirsher smp_mb(); 2888adfc5217SJeff Kirsher 2889adfc5217SJeff Kirsher if (unlikely(netif_tx_queue_stopped(txq)) && 2890adfc5217SJeff Kirsher (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 2891adfc5217SJeff Kirsher __netif_tx_lock(txq, smp_processor_id()); 2892adfc5217SJeff Kirsher if ((netif_tx_queue_stopped(txq)) && 2893adfc5217SJeff Kirsher (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) 2894adfc5217SJeff Kirsher netif_tx_wake_queue(txq); 2895adfc5217SJeff Kirsher __netif_tx_unlock(txq); 2896adfc5217SJeff Kirsher } 2897adfc5217SJeff Kirsher 2898adfc5217SJeff Kirsher return tx_pkt; 2899adfc5217SJeff Kirsher } 2900adfc5217SJeff Kirsher 2901adfc5217SJeff Kirsher static void 2902adfc5217SJeff Kirsher bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, 2903adfc5217SJeff Kirsher struct sk_buff *skb, int count) 2904adfc5217SJeff Kirsher { 2905adfc5217SJeff Kirsher struct sw_pg *cons_rx_pg, *prod_rx_pg; 2906adfc5217SJeff Kirsher struct rx_bd *cons_bd, *prod_bd; 2907adfc5217SJeff Kirsher int i; 2908adfc5217SJeff Kirsher u16 hw_prod, prod; 2909adfc5217SJeff Kirsher u16 cons = rxr->rx_pg_cons; 2910adfc5217SJeff Kirsher 2911adfc5217SJeff Kirsher cons_rx_pg = &rxr->rx_pg_ring[cons]; 2912adfc5217SJeff Kirsher 2913adfc5217SJeff Kirsher /* The caller was unable to allocate a new page to replace the 2914adfc5217SJeff Kirsher * last one in the frags array, so we need to recycle that page 2915adfc5217SJeff Kirsher * and then free the skb. 2916adfc5217SJeff Kirsher */ 2917adfc5217SJeff Kirsher if (skb) { 2918adfc5217SJeff Kirsher struct page *page; 2919adfc5217SJeff Kirsher struct skb_shared_info *shinfo; 2920adfc5217SJeff Kirsher 2921adfc5217SJeff Kirsher shinfo = skb_shinfo(skb); 2922adfc5217SJeff Kirsher shinfo->nr_frags--; 2923b7b6a688SIan Campbell page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]); 2924b7b6a688SIan Campbell __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL); 2925adfc5217SJeff Kirsher 2926adfc5217SJeff Kirsher cons_rx_pg->page = page; 2927adfc5217SJeff Kirsher dev_kfree_skb(skb); 2928adfc5217SJeff Kirsher } 2929adfc5217SJeff Kirsher 2930adfc5217SJeff Kirsher hw_prod = rxr->rx_pg_prod; 2931adfc5217SJeff Kirsher 2932adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 2933adfc5217SJeff Kirsher prod = RX_PG_RING_IDX(hw_prod); 2934adfc5217SJeff Kirsher 2935adfc5217SJeff Kirsher prod_rx_pg = &rxr->rx_pg_ring[prod]; 2936adfc5217SJeff Kirsher cons_rx_pg = &rxr->rx_pg_ring[cons]; 2937adfc5217SJeff Kirsher cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 2938adfc5217SJeff Kirsher prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 2939adfc5217SJeff Kirsher 2940adfc5217SJeff Kirsher if (prod != cons) { 2941adfc5217SJeff Kirsher prod_rx_pg->page = cons_rx_pg->page; 2942adfc5217SJeff Kirsher cons_rx_pg->page = NULL; 2943adfc5217SJeff Kirsher dma_unmap_addr_set(prod_rx_pg, mapping, 2944adfc5217SJeff Kirsher dma_unmap_addr(cons_rx_pg, mapping)); 2945adfc5217SJeff Kirsher 2946adfc5217SJeff Kirsher prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; 2947adfc5217SJeff Kirsher prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; 2948adfc5217SJeff Kirsher 2949adfc5217SJeff Kirsher } 2950adfc5217SJeff Kirsher cons = RX_PG_RING_IDX(NEXT_RX_BD(cons)); 2951adfc5217SJeff Kirsher hw_prod = NEXT_RX_BD(hw_prod); 2952adfc5217SJeff Kirsher } 2953adfc5217SJeff Kirsher rxr->rx_pg_prod = hw_prod; 2954adfc5217SJeff Kirsher rxr->rx_pg_cons = cons; 2955adfc5217SJeff Kirsher } 2956adfc5217SJeff Kirsher 2957adfc5217SJeff Kirsher static inline void 2958dd2bc8e9SEric Dumazet bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, 2959dd2bc8e9SEric Dumazet u8 *data, u16 cons, u16 prod) 2960adfc5217SJeff Kirsher { 2961adfc5217SJeff Kirsher struct sw_bd *cons_rx_buf, *prod_rx_buf; 2962adfc5217SJeff Kirsher struct rx_bd *cons_bd, *prod_bd; 2963adfc5217SJeff Kirsher 2964adfc5217SJeff Kirsher cons_rx_buf = &rxr->rx_buf_ring[cons]; 2965adfc5217SJeff Kirsher prod_rx_buf = &rxr->rx_buf_ring[prod]; 2966adfc5217SJeff Kirsher 2967adfc5217SJeff Kirsher dma_sync_single_for_device(&bp->pdev->dev, 2968adfc5217SJeff Kirsher dma_unmap_addr(cons_rx_buf, mapping), 2969adfc5217SJeff Kirsher BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE); 2970adfc5217SJeff Kirsher 2971adfc5217SJeff Kirsher rxr->rx_prod_bseq += bp->rx_buf_use_size; 2972adfc5217SJeff Kirsher 2973dd2bc8e9SEric Dumazet prod_rx_buf->data = data; 2974adfc5217SJeff Kirsher 2975adfc5217SJeff Kirsher if (cons == prod) 2976adfc5217SJeff Kirsher return; 2977adfc5217SJeff Kirsher 2978adfc5217SJeff Kirsher dma_unmap_addr_set(prod_rx_buf, mapping, 2979adfc5217SJeff Kirsher dma_unmap_addr(cons_rx_buf, mapping)); 2980adfc5217SJeff Kirsher 2981adfc5217SJeff Kirsher cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 2982adfc5217SJeff Kirsher prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 2983adfc5217SJeff Kirsher prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; 2984adfc5217SJeff Kirsher prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; 2985adfc5217SJeff Kirsher } 2986adfc5217SJeff Kirsher 2987dd2bc8e9SEric Dumazet static struct sk_buff * 2988dd2bc8e9SEric Dumazet bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data, 2989adfc5217SJeff Kirsher unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr, 2990adfc5217SJeff Kirsher u32 ring_idx) 2991adfc5217SJeff Kirsher { 2992adfc5217SJeff Kirsher int err; 2993adfc5217SJeff Kirsher u16 prod = ring_idx & 0xffff; 2994dd2bc8e9SEric Dumazet struct sk_buff *skb; 2995adfc5217SJeff Kirsher 2996dd2bc8e9SEric Dumazet err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 2997adfc5217SJeff Kirsher if (unlikely(err)) { 2998dd2bc8e9SEric Dumazet bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod); 2999dd2bc8e9SEric Dumazet error: 3000adfc5217SJeff Kirsher if (hdr_len) { 3001adfc5217SJeff Kirsher unsigned int raw_len = len + 4; 3002adfc5217SJeff Kirsher int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT; 3003adfc5217SJeff Kirsher 3004adfc5217SJeff Kirsher bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); 3005adfc5217SJeff Kirsher } 3006dd2bc8e9SEric Dumazet return NULL; 3007adfc5217SJeff Kirsher } 3008adfc5217SJeff Kirsher 3009adfc5217SJeff Kirsher dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 3010adfc5217SJeff Kirsher PCI_DMA_FROMDEVICE); 3011dd2bc8e9SEric Dumazet skb = build_skb(data); 3012dd2bc8e9SEric Dumazet if (!skb) { 3013dd2bc8e9SEric Dumazet kfree(data); 3014dd2bc8e9SEric Dumazet goto error; 3015dd2bc8e9SEric Dumazet } 3016dd2bc8e9SEric Dumazet skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET); 3017adfc5217SJeff Kirsher if (hdr_len == 0) { 3018adfc5217SJeff Kirsher skb_put(skb, len); 3019dd2bc8e9SEric Dumazet return skb; 3020adfc5217SJeff Kirsher } else { 3021adfc5217SJeff Kirsher unsigned int i, frag_len, frag_size, pages; 3022adfc5217SJeff Kirsher struct sw_pg *rx_pg; 3023adfc5217SJeff Kirsher u16 pg_cons = rxr->rx_pg_cons; 3024adfc5217SJeff Kirsher u16 pg_prod = rxr->rx_pg_prod; 3025adfc5217SJeff Kirsher 3026adfc5217SJeff Kirsher frag_size = len + 4 - hdr_len; 3027adfc5217SJeff Kirsher pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT; 3028adfc5217SJeff Kirsher skb_put(skb, hdr_len); 3029adfc5217SJeff Kirsher 3030adfc5217SJeff Kirsher for (i = 0; i < pages; i++) { 3031adfc5217SJeff Kirsher dma_addr_t mapping_old; 3032adfc5217SJeff Kirsher 3033adfc5217SJeff Kirsher frag_len = min(frag_size, (unsigned int) PAGE_SIZE); 3034adfc5217SJeff Kirsher if (unlikely(frag_len <= 4)) { 3035adfc5217SJeff Kirsher unsigned int tail = 4 - frag_len; 3036adfc5217SJeff Kirsher 3037adfc5217SJeff Kirsher rxr->rx_pg_cons = pg_cons; 3038adfc5217SJeff Kirsher rxr->rx_pg_prod = pg_prod; 3039adfc5217SJeff Kirsher bnx2_reuse_rx_skb_pages(bp, rxr, NULL, 3040adfc5217SJeff Kirsher pages - i); 3041adfc5217SJeff Kirsher skb->len -= tail; 3042adfc5217SJeff Kirsher if (i == 0) { 3043adfc5217SJeff Kirsher skb->tail -= tail; 3044adfc5217SJeff Kirsher } else { 3045adfc5217SJeff Kirsher skb_frag_t *frag = 3046adfc5217SJeff Kirsher &skb_shinfo(skb)->frags[i - 1]; 30479e903e08SEric Dumazet skb_frag_size_sub(frag, tail); 3048adfc5217SJeff Kirsher skb->data_len -= tail; 3049adfc5217SJeff Kirsher } 3050dd2bc8e9SEric Dumazet return skb; 3051adfc5217SJeff Kirsher } 3052adfc5217SJeff Kirsher rx_pg = &rxr->rx_pg_ring[pg_cons]; 3053adfc5217SJeff Kirsher 3054adfc5217SJeff Kirsher /* Don't unmap yet. If we're unable to allocate a new 3055adfc5217SJeff Kirsher * page, we need to recycle the page and the DMA addr. 3056adfc5217SJeff Kirsher */ 3057adfc5217SJeff Kirsher mapping_old = dma_unmap_addr(rx_pg, mapping); 3058adfc5217SJeff Kirsher if (i == pages - 1) 3059adfc5217SJeff Kirsher frag_len -= 4; 3060adfc5217SJeff Kirsher 3061adfc5217SJeff Kirsher skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); 3062adfc5217SJeff Kirsher rx_pg->page = NULL; 3063adfc5217SJeff Kirsher 3064adfc5217SJeff Kirsher err = bnx2_alloc_rx_page(bp, rxr, 3065adfc5217SJeff Kirsher RX_PG_RING_IDX(pg_prod), 3066adfc5217SJeff Kirsher GFP_ATOMIC); 3067adfc5217SJeff Kirsher if (unlikely(err)) { 3068adfc5217SJeff Kirsher rxr->rx_pg_cons = pg_cons; 3069adfc5217SJeff Kirsher rxr->rx_pg_prod = pg_prod; 3070adfc5217SJeff Kirsher bnx2_reuse_rx_skb_pages(bp, rxr, skb, 3071adfc5217SJeff Kirsher pages - i); 3072dd2bc8e9SEric Dumazet return NULL; 3073adfc5217SJeff Kirsher } 3074adfc5217SJeff Kirsher 3075adfc5217SJeff Kirsher dma_unmap_page(&bp->pdev->dev, mapping_old, 3076adfc5217SJeff Kirsher PAGE_SIZE, PCI_DMA_FROMDEVICE); 3077adfc5217SJeff Kirsher 3078adfc5217SJeff Kirsher frag_size -= frag_len; 3079adfc5217SJeff Kirsher skb->data_len += frag_len; 3080a1f4e8bcSEric Dumazet skb->truesize += PAGE_SIZE; 3081adfc5217SJeff Kirsher skb->len += frag_len; 3082adfc5217SJeff Kirsher 3083adfc5217SJeff Kirsher pg_prod = NEXT_RX_BD(pg_prod); 3084adfc5217SJeff Kirsher pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons)); 3085adfc5217SJeff Kirsher } 3086adfc5217SJeff Kirsher rxr->rx_pg_prod = pg_prod; 3087adfc5217SJeff Kirsher rxr->rx_pg_cons = pg_cons; 3088adfc5217SJeff Kirsher } 3089dd2bc8e9SEric Dumazet return skb; 3090adfc5217SJeff Kirsher } 3091adfc5217SJeff Kirsher 3092adfc5217SJeff Kirsher static inline u16 3093adfc5217SJeff Kirsher bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi) 3094adfc5217SJeff Kirsher { 3095adfc5217SJeff Kirsher u16 cons; 3096adfc5217SJeff Kirsher 3097adfc5217SJeff Kirsher /* Tell compiler that status block fields can change. */ 3098adfc5217SJeff Kirsher barrier(); 3099adfc5217SJeff Kirsher cons = *bnapi->hw_rx_cons_ptr; 3100adfc5217SJeff Kirsher barrier(); 3101adfc5217SJeff Kirsher if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)) 3102adfc5217SJeff Kirsher cons++; 3103adfc5217SJeff Kirsher return cons; 3104adfc5217SJeff Kirsher } 3105adfc5217SJeff Kirsher 3106adfc5217SJeff Kirsher static int 3107adfc5217SJeff Kirsher bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) 3108adfc5217SJeff Kirsher { 3109adfc5217SJeff Kirsher struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 3110adfc5217SJeff Kirsher u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; 3111adfc5217SJeff Kirsher struct l2_fhdr *rx_hdr; 3112adfc5217SJeff Kirsher int rx_pkt = 0, pg_ring_used = 0; 3113adfc5217SJeff Kirsher 3114adfc5217SJeff Kirsher hw_cons = bnx2_get_hw_rx_cons(bnapi); 3115adfc5217SJeff Kirsher sw_cons = rxr->rx_cons; 3116adfc5217SJeff Kirsher sw_prod = rxr->rx_prod; 3117adfc5217SJeff Kirsher 3118adfc5217SJeff Kirsher /* Memory barrier necessary as speculative reads of the rx 3119adfc5217SJeff Kirsher * buffer can be ahead of the index in the status block 3120adfc5217SJeff Kirsher */ 3121adfc5217SJeff Kirsher rmb(); 3122adfc5217SJeff Kirsher while (sw_cons != hw_cons) { 3123adfc5217SJeff Kirsher unsigned int len, hdr_len; 3124adfc5217SJeff Kirsher u32 status; 3125adfc5217SJeff Kirsher struct sw_bd *rx_buf, *next_rx_buf; 3126adfc5217SJeff Kirsher struct sk_buff *skb; 3127adfc5217SJeff Kirsher dma_addr_t dma_addr; 3128dd2bc8e9SEric Dumazet u8 *data; 3129adfc5217SJeff Kirsher 3130adfc5217SJeff Kirsher sw_ring_cons = RX_RING_IDX(sw_cons); 3131adfc5217SJeff Kirsher sw_ring_prod = RX_RING_IDX(sw_prod); 3132adfc5217SJeff Kirsher 3133adfc5217SJeff Kirsher rx_buf = &rxr->rx_buf_ring[sw_ring_cons]; 3134dd2bc8e9SEric Dumazet data = rx_buf->data; 3135dd2bc8e9SEric Dumazet rx_buf->data = NULL; 3136adfc5217SJeff Kirsher 3137dd2bc8e9SEric Dumazet rx_hdr = get_l2_fhdr(data); 3138dd2bc8e9SEric Dumazet prefetch(rx_hdr); 3139adfc5217SJeff Kirsher 3140adfc5217SJeff Kirsher dma_addr = dma_unmap_addr(rx_buf, mapping); 3141adfc5217SJeff Kirsher 3142adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr, 3143adfc5217SJeff Kirsher BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, 3144adfc5217SJeff Kirsher PCI_DMA_FROMDEVICE); 3145adfc5217SJeff Kirsher 3146dd2bc8e9SEric Dumazet next_rx_buf = 3147dd2bc8e9SEric Dumazet &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))]; 3148dd2bc8e9SEric Dumazet prefetch(get_l2_fhdr(next_rx_buf->data)); 3149dd2bc8e9SEric Dumazet 3150adfc5217SJeff Kirsher len = rx_hdr->l2_fhdr_pkt_len; 3151adfc5217SJeff Kirsher status = rx_hdr->l2_fhdr_status; 3152adfc5217SJeff Kirsher 3153adfc5217SJeff Kirsher hdr_len = 0; 3154adfc5217SJeff Kirsher if (status & L2_FHDR_STATUS_SPLIT) { 3155adfc5217SJeff Kirsher hdr_len = rx_hdr->l2_fhdr_ip_xsum; 3156adfc5217SJeff Kirsher pg_ring_used = 1; 3157adfc5217SJeff Kirsher } else if (len > bp->rx_jumbo_thresh) { 3158adfc5217SJeff Kirsher hdr_len = bp->rx_jumbo_thresh; 3159adfc5217SJeff Kirsher pg_ring_used = 1; 3160adfc5217SJeff Kirsher } 3161adfc5217SJeff Kirsher 3162adfc5217SJeff Kirsher if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC | 3163adfc5217SJeff Kirsher L2_FHDR_ERRORS_PHY_DECODE | 3164adfc5217SJeff Kirsher L2_FHDR_ERRORS_ALIGNMENT | 3165adfc5217SJeff Kirsher L2_FHDR_ERRORS_TOO_SHORT | 3166adfc5217SJeff Kirsher L2_FHDR_ERRORS_GIANT_FRAME))) { 3167adfc5217SJeff Kirsher 3168dd2bc8e9SEric Dumazet bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons, 3169adfc5217SJeff Kirsher sw_ring_prod); 3170adfc5217SJeff Kirsher if (pg_ring_used) { 3171adfc5217SJeff Kirsher int pages; 3172adfc5217SJeff Kirsher 3173adfc5217SJeff Kirsher pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT; 3174adfc5217SJeff Kirsher 3175adfc5217SJeff Kirsher bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); 3176adfc5217SJeff Kirsher } 3177adfc5217SJeff Kirsher goto next_rx; 3178adfc5217SJeff Kirsher } 3179adfc5217SJeff Kirsher 3180adfc5217SJeff Kirsher len -= 4; 3181adfc5217SJeff Kirsher 3182adfc5217SJeff Kirsher if (len <= bp->rx_copy_thresh) { 3183dd2bc8e9SEric Dumazet skb = netdev_alloc_skb(bp->dev, len + 6); 3184dd2bc8e9SEric Dumazet if (skb == NULL) { 3185dd2bc8e9SEric Dumazet bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons, 3186adfc5217SJeff Kirsher sw_ring_prod); 3187adfc5217SJeff Kirsher goto next_rx; 3188adfc5217SJeff Kirsher } 3189adfc5217SJeff Kirsher 3190adfc5217SJeff Kirsher /* aligned copy */ 3191dd2bc8e9SEric Dumazet memcpy(skb->data, 3192dd2bc8e9SEric Dumazet (u8 *)rx_hdr + BNX2_RX_OFFSET - 6, 3193dd2bc8e9SEric Dumazet len + 6); 3194dd2bc8e9SEric Dumazet skb_reserve(skb, 6); 3195dd2bc8e9SEric Dumazet skb_put(skb, len); 3196adfc5217SJeff Kirsher 3197dd2bc8e9SEric Dumazet bnx2_reuse_rx_data(bp, rxr, data, 3198adfc5217SJeff Kirsher sw_ring_cons, sw_ring_prod); 3199adfc5217SJeff Kirsher 3200dd2bc8e9SEric Dumazet } else { 3201dd2bc8e9SEric Dumazet skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr, 3202dd2bc8e9SEric Dumazet (sw_ring_cons << 16) | sw_ring_prod); 3203dd2bc8e9SEric Dumazet if (!skb) 3204adfc5217SJeff Kirsher goto next_rx; 3205dd2bc8e9SEric Dumazet } 3206adfc5217SJeff Kirsher if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 3207adfc5217SJeff Kirsher !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) 3208adfc5217SJeff Kirsher __vlan_hwaccel_put_tag(skb, rx_hdr->l2_fhdr_vlan_tag); 3209adfc5217SJeff Kirsher 3210adfc5217SJeff Kirsher skb->protocol = eth_type_trans(skb, bp->dev); 3211adfc5217SJeff Kirsher 3212adfc5217SJeff Kirsher if ((len > (bp->dev->mtu + ETH_HLEN)) && 3213adfc5217SJeff Kirsher (ntohs(skb->protocol) != 0x8100)) { 3214adfc5217SJeff Kirsher 3215adfc5217SJeff Kirsher dev_kfree_skb(skb); 3216adfc5217SJeff Kirsher goto next_rx; 3217adfc5217SJeff Kirsher 3218adfc5217SJeff Kirsher } 3219adfc5217SJeff Kirsher 3220adfc5217SJeff Kirsher skb_checksum_none_assert(skb); 3221adfc5217SJeff Kirsher if ((bp->dev->features & NETIF_F_RXCSUM) && 3222adfc5217SJeff Kirsher (status & (L2_FHDR_STATUS_TCP_SEGMENT | 3223adfc5217SJeff Kirsher L2_FHDR_STATUS_UDP_DATAGRAM))) { 3224adfc5217SJeff Kirsher 3225adfc5217SJeff Kirsher if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM | 3226adfc5217SJeff Kirsher L2_FHDR_ERRORS_UDP_XSUM)) == 0)) 3227adfc5217SJeff Kirsher skb->ip_summed = CHECKSUM_UNNECESSARY; 3228adfc5217SJeff Kirsher } 3229adfc5217SJeff Kirsher if ((bp->dev->features & NETIF_F_RXHASH) && 3230adfc5217SJeff Kirsher ((status & L2_FHDR_STATUS_USE_RXHASH) == 3231adfc5217SJeff Kirsher L2_FHDR_STATUS_USE_RXHASH)) 3232adfc5217SJeff Kirsher skb->rxhash = rx_hdr->l2_fhdr_hash; 3233adfc5217SJeff Kirsher 3234adfc5217SJeff Kirsher skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]); 3235adfc5217SJeff Kirsher napi_gro_receive(&bnapi->napi, skb); 3236adfc5217SJeff Kirsher rx_pkt++; 3237adfc5217SJeff Kirsher 3238adfc5217SJeff Kirsher next_rx: 3239adfc5217SJeff Kirsher sw_cons = NEXT_RX_BD(sw_cons); 3240adfc5217SJeff Kirsher sw_prod = NEXT_RX_BD(sw_prod); 3241adfc5217SJeff Kirsher 3242adfc5217SJeff Kirsher if ((rx_pkt == budget)) 3243adfc5217SJeff Kirsher break; 3244adfc5217SJeff Kirsher 3245adfc5217SJeff Kirsher /* Refresh hw_cons to see if there is new work */ 3246adfc5217SJeff Kirsher if (sw_cons == hw_cons) { 3247adfc5217SJeff Kirsher hw_cons = bnx2_get_hw_rx_cons(bnapi); 3248adfc5217SJeff Kirsher rmb(); 3249adfc5217SJeff Kirsher } 3250adfc5217SJeff Kirsher } 3251adfc5217SJeff Kirsher rxr->rx_cons = sw_cons; 3252adfc5217SJeff Kirsher rxr->rx_prod = sw_prod; 3253adfc5217SJeff Kirsher 3254adfc5217SJeff Kirsher if (pg_ring_used) 3255adfc5217SJeff Kirsher REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); 3256adfc5217SJeff Kirsher 3257adfc5217SJeff Kirsher REG_WR16(bp, rxr->rx_bidx_addr, sw_prod); 3258adfc5217SJeff Kirsher 3259adfc5217SJeff Kirsher REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); 3260adfc5217SJeff Kirsher 3261adfc5217SJeff Kirsher mmiowb(); 3262adfc5217SJeff Kirsher 3263adfc5217SJeff Kirsher return rx_pkt; 3264adfc5217SJeff Kirsher 3265adfc5217SJeff Kirsher } 3266adfc5217SJeff Kirsher 3267adfc5217SJeff Kirsher /* MSI ISR - The only difference between this and the INTx ISR 3268adfc5217SJeff Kirsher * is that the MSI interrupt is always serviced. 3269adfc5217SJeff Kirsher */ 3270adfc5217SJeff Kirsher static irqreturn_t 3271adfc5217SJeff Kirsher bnx2_msi(int irq, void *dev_instance) 3272adfc5217SJeff Kirsher { 3273adfc5217SJeff Kirsher struct bnx2_napi *bnapi = dev_instance; 3274adfc5217SJeff Kirsher struct bnx2 *bp = bnapi->bp; 3275adfc5217SJeff Kirsher 3276adfc5217SJeff Kirsher prefetch(bnapi->status_blk.msi); 3277adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3278adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 3279adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 3280adfc5217SJeff Kirsher 3281adfc5217SJeff Kirsher /* Return here if interrupt is disabled. */ 3282adfc5217SJeff Kirsher if (unlikely(atomic_read(&bp->intr_sem) != 0)) 3283adfc5217SJeff Kirsher return IRQ_HANDLED; 3284adfc5217SJeff Kirsher 3285adfc5217SJeff Kirsher napi_schedule(&bnapi->napi); 3286adfc5217SJeff Kirsher 3287adfc5217SJeff Kirsher return IRQ_HANDLED; 3288adfc5217SJeff Kirsher } 3289adfc5217SJeff Kirsher 3290adfc5217SJeff Kirsher static irqreturn_t 3291adfc5217SJeff Kirsher bnx2_msi_1shot(int irq, void *dev_instance) 3292adfc5217SJeff Kirsher { 3293adfc5217SJeff Kirsher struct bnx2_napi *bnapi = dev_instance; 3294adfc5217SJeff Kirsher struct bnx2 *bp = bnapi->bp; 3295adfc5217SJeff Kirsher 3296adfc5217SJeff Kirsher prefetch(bnapi->status_blk.msi); 3297adfc5217SJeff Kirsher 3298adfc5217SJeff Kirsher /* Return here if interrupt is disabled. */ 3299adfc5217SJeff Kirsher if (unlikely(atomic_read(&bp->intr_sem) != 0)) 3300adfc5217SJeff Kirsher return IRQ_HANDLED; 3301adfc5217SJeff Kirsher 3302adfc5217SJeff Kirsher napi_schedule(&bnapi->napi); 3303adfc5217SJeff Kirsher 3304adfc5217SJeff Kirsher return IRQ_HANDLED; 3305adfc5217SJeff Kirsher } 3306adfc5217SJeff Kirsher 3307adfc5217SJeff Kirsher static irqreturn_t 3308adfc5217SJeff Kirsher bnx2_interrupt(int irq, void *dev_instance) 3309adfc5217SJeff Kirsher { 3310adfc5217SJeff Kirsher struct bnx2_napi *bnapi = dev_instance; 3311adfc5217SJeff Kirsher struct bnx2 *bp = bnapi->bp; 3312adfc5217SJeff Kirsher struct status_block *sblk = bnapi->status_blk.msi; 3313adfc5217SJeff Kirsher 3314adfc5217SJeff Kirsher /* When using INTx, it is possible for the interrupt to arrive 3315adfc5217SJeff Kirsher * at the CPU before the status block posted prior to the 3316adfc5217SJeff Kirsher * interrupt. Reading a register will flush the status block. 3317adfc5217SJeff Kirsher * When using MSI, the MSI message will always complete after 3318adfc5217SJeff Kirsher * the status block write. 3319adfc5217SJeff Kirsher */ 3320adfc5217SJeff Kirsher if ((sblk->status_idx == bnapi->last_status_idx) && 3321adfc5217SJeff Kirsher (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) & 3322adfc5217SJeff Kirsher BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) 3323adfc5217SJeff Kirsher return IRQ_NONE; 3324adfc5217SJeff Kirsher 3325adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3326adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 3327adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 3328adfc5217SJeff Kirsher 3329adfc5217SJeff Kirsher /* Read back to deassert IRQ immediately to avoid too many 3330adfc5217SJeff Kirsher * spurious interrupts. 3331adfc5217SJeff Kirsher */ 3332adfc5217SJeff Kirsher REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD); 3333adfc5217SJeff Kirsher 3334adfc5217SJeff Kirsher /* Return here if interrupt is shared and is disabled. */ 3335adfc5217SJeff Kirsher if (unlikely(atomic_read(&bp->intr_sem) != 0)) 3336adfc5217SJeff Kirsher return IRQ_HANDLED; 3337adfc5217SJeff Kirsher 3338adfc5217SJeff Kirsher if (napi_schedule_prep(&bnapi->napi)) { 3339adfc5217SJeff Kirsher bnapi->last_status_idx = sblk->status_idx; 3340adfc5217SJeff Kirsher __napi_schedule(&bnapi->napi); 3341adfc5217SJeff Kirsher } 3342adfc5217SJeff Kirsher 3343adfc5217SJeff Kirsher return IRQ_HANDLED; 3344adfc5217SJeff Kirsher } 3345adfc5217SJeff Kirsher 3346adfc5217SJeff Kirsher static inline int 3347adfc5217SJeff Kirsher bnx2_has_fast_work(struct bnx2_napi *bnapi) 3348adfc5217SJeff Kirsher { 3349adfc5217SJeff Kirsher struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 3350adfc5217SJeff Kirsher struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 3351adfc5217SJeff Kirsher 3352adfc5217SJeff Kirsher if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) || 3353adfc5217SJeff Kirsher (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)) 3354adfc5217SJeff Kirsher return 1; 3355adfc5217SJeff Kirsher return 0; 3356adfc5217SJeff Kirsher } 3357adfc5217SJeff Kirsher 3358adfc5217SJeff Kirsher #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \ 3359adfc5217SJeff Kirsher STATUS_ATTN_BITS_TIMER_ABORT) 3360adfc5217SJeff Kirsher 3361adfc5217SJeff Kirsher static inline int 3362adfc5217SJeff Kirsher bnx2_has_work(struct bnx2_napi *bnapi) 3363adfc5217SJeff Kirsher { 3364adfc5217SJeff Kirsher struct status_block *sblk = bnapi->status_blk.msi; 3365adfc5217SJeff Kirsher 3366adfc5217SJeff Kirsher if (bnx2_has_fast_work(bnapi)) 3367adfc5217SJeff Kirsher return 1; 3368adfc5217SJeff Kirsher 3369adfc5217SJeff Kirsher #ifdef BCM_CNIC 3370adfc5217SJeff Kirsher if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx)) 3371adfc5217SJeff Kirsher return 1; 3372adfc5217SJeff Kirsher #endif 3373adfc5217SJeff Kirsher 3374adfc5217SJeff Kirsher if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != 3375adfc5217SJeff Kirsher (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS)) 3376adfc5217SJeff Kirsher return 1; 3377adfc5217SJeff Kirsher 3378adfc5217SJeff Kirsher return 0; 3379adfc5217SJeff Kirsher } 3380adfc5217SJeff Kirsher 3381adfc5217SJeff Kirsher static void 3382adfc5217SJeff Kirsher bnx2_chk_missed_msi(struct bnx2 *bp) 3383adfc5217SJeff Kirsher { 3384adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 3385adfc5217SJeff Kirsher u32 msi_ctrl; 3386adfc5217SJeff Kirsher 3387adfc5217SJeff Kirsher if (bnx2_has_work(bnapi)) { 3388adfc5217SJeff Kirsher msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL); 3389adfc5217SJeff Kirsher if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE)) 3390adfc5217SJeff Kirsher return; 3391adfc5217SJeff Kirsher 3392adfc5217SJeff Kirsher if (bnapi->last_status_idx == bp->idle_chk_status_idx) { 3393adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl & 3394adfc5217SJeff Kirsher ~BNX2_PCICFG_MSI_CONTROL_ENABLE); 3395adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl); 3396adfc5217SJeff Kirsher bnx2_msi(bp->irq_tbl[0].vector, bnapi); 3397adfc5217SJeff Kirsher } 3398adfc5217SJeff Kirsher } 3399adfc5217SJeff Kirsher 3400adfc5217SJeff Kirsher bp->idle_chk_status_idx = bnapi->last_status_idx; 3401adfc5217SJeff Kirsher } 3402adfc5217SJeff Kirsher 3403adfc5217SJeff Kirsher #ifdef BCM_CNIC 3404adfc5217SJeff Kirsher static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi) 3405adfc5217SJeff Kirsher { 3406adfc5217SJeff Kirsher struct cnic_ops *c_ops; 3407adfc5217SJeff Kirsher 3408adfc5217SJeff Kirsher if (!bnapi->cnic_present) 3409adfc5217SJeff Kirsher return; 3410adfc5217SJeff Kirsher 3411adfc5217SJeff Kirsher rcu_read_lock(); 3412adfc5217SJeff Kirsher c_ops = rcu_dereference(bp->cnic_ops); 3413adfc5217SJeff Kirsher if (c_ops) 3414adfc5217SJeff Kirsher bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data, 3415adfc5217SJeff Kirsher bnapi->status_blk.msi); 3416adfc5217SJeff Kirsher rcu_read_unlock(); 3417adfc5217SJeff Kirsher } 3418adfc5217SJeff Kirsher #endif 3419adfc5217SJeff Kirsher 3420adfc5217SJeff Kirsher static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi) 3421adfc5217SJeff Kirsher { 3422adfc5217SJeff Kirsher struct status_block *sblk = bnapi->status_blk.msi; 3423adfc5217SJeff Kirsher u32 status_attn_bits = sblk->status_attn_bits; 3424adfc5217SJeff Kirsher u32 status_attn_bits_ack = sblk->status_attn_bits_ack; 3425adfc5217SJeff Kirsher 3426adfc5217SJeff Kirsher if ((status_attn_bits & STATUS_ATTN_EVENTS) != 3427adfc5217SJeff Kirsher (status_attn_bits_ack & STATUS_ATTN_EVENTS)) { 3428adfc5217SJeff Kirsher 3429adfc5217SJeff Kirsher bnx2_phy_int(bp, bnapi); 3430adfc5217SJeff Kirsher 3431adfc5217SJeff Kirsher /* This is needed to take care of transient status 3432adfc5217SJeff Kirsher * during link changes. 3433adfc5217SJeff Kirsher */ 3434adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_COMMAND, 3435adfc5217SJeff Kirsher bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); 3436adfc5217SJeff Kirsher REG_RD(bp, BNX2_HC_COMMAND); 3437adfc5217SJeff Kirsher } 3438adfc5217SJeff Kirsher } 3439adfc5217SJeff Kirsher 3440adfc5217SJeff Kirsher static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi, 3441adfc5217SJeff Kirsher int work_done, int budget) 3442adfc5217SJeff Kirsher { 3443adfc5217SJeff Kirsher struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 3444adfc5217SJeff Kirsher struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 3445adfc5217SJeff Kirsher 3446adfc5217SJeff Kirsher if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons) 3447adfc5217SJeff Kirsher bnx2_tx_int(bp, bnapi, 0); 3448adfc5217SJeff Kirsher 3449adfc5217SJeff Kirsher if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) 3450adfc5217SJeff Kirsher work_done += bnx2_rx_int(bp, bnapi, budget - work_done); 3451adfc5217SJeff Kirsher 3452adfc5217SJeff Kirsher return work_done; 3453adfc5217SJeff Kirsher } 3454adfc5217SJeff Kirsher 3455adfc5217SJeff Kirsher static int bnx2_poll_msix(struct napi_struct *napi, int budget) 3456adfc5217SJeff Kirsher { 3457adfc5217SJeff Kirsher struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); 3458adfc5217SJeff Kirsher struct bnx2 *bp = bnapi->bp; 3459adfc5217SJeff Kirsher int work_done = 0; 3460adfc5217SJeff Kirsher struct status_block_msix *sblk = bnapi->status_blk.msix; 3461adfc5217SJeff Kirsher 3462adfc5217SJeff Kirsher while (1) { 3463adfc5217SJeff Kirsher work_done = bnx2_poll_work(bp, bnapi, work_done, budget); 3464adfc5217SJeff Kirsher if (unlikely(work_done >= budget)) 3465adfc5217SJeff Kirsher break; 3466adfc5217SJeff Kirsher 3467adfc5217SJeff Kirsher bnapi->last_status_idx = sblk->status_idx; 3468adfc5217SJeff Kirsher /* status idx must be read before checking for more work. */ 3469adfc5217SJeff Kirsher rmb(); 3470adfc5217SJeff Kirsher if (likely(!bnx2_has_fast_work(bnapi))) { 3471adfc5217SJeff Kirsher 3472adfc5217SJeff Kirsher napi_complete(napi); 3473adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 3474adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3475adfc5217SJeff Kirsher bnapi->last_status_idx); 3476adfc5217SJeff Kirsher break; 3477adfc5217SJeff Kirsher } 3478adfc5217SJeff Kirsher } 3479adfc5217SJeff Kirsher return work_done; 3480adfc5217SJeff Kirsher } 3481adfc5217SJeff Kirsher 3482adfc5217SJeff Kirsher static int bnx2_poll(struct napi_struct *napi, int budget) 3483adfc5217SJeff Kirsher { 3484adfc5217SJeff Kirsher struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); 3485adfc5217SJeff Kirsher struct bnx2 *bp = bnapi->bp; 3486adfc5217SJeff Kirsher int work_done = 0; 3487adfc5217SJeff Kirsher struct status_block *sblk = bnapi->status_blk.msi; 3488adfc5217SJeff Kirsher 3489adfc5217SJeff Kirsher while (1) { 3490adfc5217SJeff Kirsher bnx2_poll_link(bp, bnapi); 3491adfc5217SJeff Kirsher 3492adfc5217SJeff Kirsher work_done = bnx2_poll_work(bp, bnapi, work_done, budget); 3493adfc5217SJeff Kirsher 3494adfc5217SJeff Kirsher #ifdef BCM_CNIC 3495adfc5217SJeff Kirsher bnx2_poll_cnic(bp, bnapi); 3496adfc5217SJeff Kirsher #endif 3497adfc5217SJeff Kirsher 3498adfc5217SJeff Kirsher /* bnapi->last_status_idx is used below to tell the hw how 3499adfc5217SJeff Kirsher * much work has been processed, so we must read it before 3500adfc5217SJeff Kirsher * checking for more work. 3501adfc5217SJeff Kirsher */ 3502adfc5217SJeff Kirsher bnapi->last_status_idx = sblk->status_idx; 3503adfc5217SJeff Kirsher 3504adfc5217SJeff Kirsher if (unlikely(work_done >= budget)) 3505adfc5217SJeff Kirsher break; 3506adfc5217SJeff Kirsher 3507adfc5217SJeff Kirsher rmb(); 3508adfc5217SJeff Kirsher if (likely(!bnx2_has_work(bnapi))) { 3509adfc5217SJeff Kirsher napi_complete(napi); 3510adfc5217SJeff Kirsher if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { 3511adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3512adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3513adfc5217SJeff Kirsher bnapi->last_status_idx); 3514adfc5217SJeff Kirsher break; 3515adfc5217SJeff Kirsher } 3516adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3517adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3518adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_MASK_INT | 3519adfc5217SJeff Kirsher bnapi->last_status_idx); 3520adfc5217SJeff Kirsher 3521adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3522adfc5217SJeff Kirsher BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3523adfc5217SJeff Kirsher bnapi->last_status_idx); 3524adfc5217SJeff Kirsher break; 3525adfc5217SJeff Kirsher } 3526adfc5217SJeff Kirsher } 3527adfc5217SJeff Kirsher 3528adfc5217SJeff Kirsher return work_done; 3529adfc5217SJeff Kirsher } 3530adfc5217SJeff Kirsher 3531adfc5217SJeff Kirsher /* Called with rtnl_lock from vlan functions and also netif_tx_lock 3532adfc5217SJeff Kirsher * from set_multicast. 3533adfc5217SJeff Kirsher */ 3534adfc5217SJeff Kirsher static void 3535adfc5217SJeff Kirsher bnx2_set_rx_mode(struct net_device *dev) 3536adfc5217SJeff Kirsher { 3537adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 3538adfc5217SJeff Kirsher u32 rx_mode, sort_mode; 3539adfc5217SJeff Kirsher struct netdev_hw_addr *ha; 3540adfc5217SJeff Kirsher int i; 3541adfc5217SJeff Kirsher 3542adfc5217SJeff Kirsher if (!netif_running(dev)) 3543adfc5217SJeff Kirsher return; 3544adfc5217SJeff Kirsher 3545adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 3546adfc5217SJeff Kirsher 3547adfc5217SJeff Kirsher rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | 3548adfc5217SJeff Kirsher BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); 3549adfc5217SJeff Kirsher sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; 3550adfc5217SJeff Kirsher if (!(dev->features & NETIF_F_HW_VLAN_RX) && 3551adfc5217SJeff Kirsher (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) 3552adfc5217SJeff Kirsher rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; 3553adfc5217SJeff Kirsher if (dev->flags & IFF_PROMISC) { 3554adfc5217SJeff Kirsher /* Promiscuous mode. */ 3555adfc5217SJeff Kirsher rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; 3556adfc5217SJeff Kirsher sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | 3557adfc5217SJeff Kirsher BNX2_RPM_SORT_USER0_PROM_VLAN; 3558adfc5217SJeff Kirsher } 3559adfc5217SJeff Kirsher else if (dev->flags & IFF_ALLMULTI) { 3560adfc5217SJeff Kirsher for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 3561adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), 3562adfc5217SJeff Kirsher 0xffffffff); 3563adfc5217SJeff Kirsher } 3564adfc5217SJeff Kirsher sort_mode |= BNX2_RPM_SORT_USER0_MC_EN; 3565adfc5217SJeff Kirsher } 3566adfc5217SJeff Kirsher else { 3567adfc5217SJeff Kirsher /* Accept one or more multicast(s). */ 3568adfc5217SJeff Kirsher u32 mc_filter[NUM_MC_HASH_REGISTERS]; 3569adfc5217SJeff Kirsher u32 regidx; 3570adfc5217SJeff Kirsher u32 bit; 3571adfc5217SJeff Kirsher u32 crc; 3572adfc5217SJeff Kirsher 3573adfc5217SJeff Kirsher memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS); 3574adfc5217SJeff Kirsher 3575adfc5217SJeff Kirsher netdev_for_each_mc_addr(ha, dev) { 3576adfc5217SJeff Kirsher crc = ether_crc_le(ETH_ALEN, ha->addr); 3577adfc5217SJeff Kirsher bit = crc & 0xff; 3578adfc5217SJeff Kirsher regidx = (bit & 0xe0) >> 5; 3579adfc5217SJeff Kirsher bit &= 0x1f; 3580adfc5217SJeff Kirsher mc_filter[regidx] |= (1 << bit); 3581adfc5217SJeff Kirsher } 3582adfc5217SJeff Kirsher 3583adfc5217SJeff Kirsher for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 3584adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), 3585adfc5217SJeff Kirsher mc_filter[i]); 3586adfc5217SJeff Kirsher } 3587adfc5217SJeff Kirsher 3588adfc5217SJeff Kirsher sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN; 3589adfc5217SJeff Kirsher } 3590adfc5217SJeff Kirsher 3591adfc5217SJeff Kirsher if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) { 3592adfc5217SJeff Kirsher rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; 3593adfc5217SJeff Kirsher sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | 3594adfc5217SJeff Kirsher BNX2_RPM_SORT_USER0_PROM_VLAN; 3595adfc5217SJeff Kirsher } else if (!(dev->flags & IFF_PROMISC)) { 3596adfc5217SJeff Kirsher /* Add all entries into to the match filter list */ 3597adfc5217SJeff Kirsher i = 0; 3598adfc5217SJeff Kirsher netdev_for_each_uc_addr(ha, dev) { 3599adfc5217SJeff Kirsher bnx2_set_mac_addr(bp, ha->addr, 3600adfc5217SJeff Kirsher i + BNX2_START_UNICAST_ADDRESS_INDEX); 3601adfc5217SJeff Kirsher sort_mode |= (1 << 3602adfc5217SJeff Kirsher (i + BNX2_START_UNICAST_ADDRESS_INDEX)); 3603adfc5217SJeff Kirsher i++; 3604adfc5217SJeff Kirsher } 3605adfc5217SJeff Kirsher 3606adfc5217SJeff Kirsher } 3607adfc5217SJeff Kirsher 3608adfc5217SJeff Kirsher if (rx_mode != bp->rx_mode) { 3609adfc5217SJeff Kirsher bp->rx_mode = rx_mode; 3610adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); 3611adfc5217SJeff Kirsher } 3612adfc5217SJeff Kirsher 3613adfc5217SJeff Kirsher REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); 3614adfc5217SJeff Kirsher REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode); 3615adfc5217SJeff Kirsher REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); 3616adfc5217SJeff Kirsher 3617adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 3618adfc5217SJeff Kirsher } 3619adfc5217SJeff Kirsher 36207880b72eSfrançois romieu static int 3621adfc5217SJeff Kirsher check_fw_section(const struct firmware *fw, 3622adfc5217SJeff Kirsher const struct bnx2_fw_file_section *section, 3623adfc5217SJeff Kirsher u32 alignment, bool non_empty) 3624adfc5217SJeff Kirsher { 3625adfc5217SJeff Kirsher u32 offset = be32_to_cpu(section->offset); 3626adfc5217SJeff Kirsher u32 len = be32_to_cpu(section->len); 3627adfc5217SJeff Kirsher 3628adfc5217SJeff Kirsher if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3) 3629adfc5217SJeff Kirsher return -EINVAL; 3630adfc5217SJeff Kirsher if ((non_empty && len == 0) || len > fw->size - offset || 3631adfc5217SJeff Kirsher len & (alignment - 1)) 3632adfc5217SJeff Kirsher return -EINVAL; 3633adfc5217SJeff Kirsher return 0; 3634adfc5217SJeff Kirsher } 3635adfc5217SJeff Kirsher 36367880b72eSfrançois romieu static int 3637adfc5217SJeff Kirsher check_mips_fw_entry(const struct firmware *fw, 3638adfc5217SJeff Kirsher const struct bnx2_mips_fw_file_entry *entry) 3639adfc5217SJeff Kirsher { 3640adfc5217SJeff Kirsher if (check_fw_section(fw, &entry->text, 4, true) || 3641adfc5217SJeff Kirsher check_fw_section(fw, &entry->data, 4, false) || 3642adfc5217SJeff Kirsher check_fw_section(fw, &entry->rodata, 4, false)) 3643adfc5217SJeff Kirsher return -EINVAL; 3644adfc5217SJeff Kirsher return 0; 3645adfc5217SJeff Kirsher } 3646adfc5217SJeff Kirsher 36477880b72eSfrançois romieu static void bnx2_release_firmware(struct bnx2 *bp) 36487880b72eSfrançois romieu { 36497880b72eSfrançois romieu if (bp->rv2p_firmware) { 36507880b72eSfrançois romieu release_firmware(bp->mips_firmware); 36517880b72eSfrançois romieu release_firmware(bp->rv2p_firmware); 36527880b72eSfrançois romieu bp->rv2p_firmware = NULL; 36537880b72eSfrançois romieu } 36547880b72eSfrançois romieu } 36557880b72eSfrançois romieu 36567880b72eSfrançois romieu static int bnx2_request_uncached_firmware(struct bnx2 *bp) 3657adfc5217SJeff Kirsher { 3658adfc5217SJeff Kirsher const char *mips_fw_file, *rv2p_fw_file; 3659adfc5217SJeff Kirsher const struct bnx2_mips_fw_file *mips_fw; 3660adfc5217SJeff Kirsher const struct bnx2_rv2p_fw_file *rv2p_fw; 3661adfc5217SJeff Kirsher int rc; 3662adfc5217SJeff Kirsher 3663adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 3664adfc5217SJeff Kirsher mips_fw_file = FW_MIPS_FILE_09; 3665adfc5217SJeff Kirsher if ((CHIP_ID(bp) == CHIP_ID_5709_A0) || 3666adfc5217SJeff Kirsher (CHIP_ID(bp) == CHIP_ID_5709_A1)) 3667adfc5217SJeff Kirsher rv2p_fw_file = FW_RV2P_FILE_09_Ax; 3668adfc5217SJeff Kirsher else 3669adfc5217SJeff Kirsher rv2p_fw_file = FW_RV2P_FILE_09; 3670adfc5217SJeff Kirsher } else { 3671adfc5217SJeff Kirsher mips_fw_file = FW_MIPS_FILE_06; 3672adfc5217SJeff Kirsher rv2p_fw_file = FW_RV2P_FILE_06; 3673adfc5217SJeff Kirsher } 3674adfc5217SJeff Kirsher 3675adfc5217SJeff Kirsher rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev); 3676adfc5217SJeff Kirsher if (rc) { 3677adfc5217SJeff Kirsher pr_err("Can't load firmware file \"%s\"\n", mips_fw_file); 36787880b72eSfrançois romieu goto out; 3679adfc5217SJeff Kirsher } 3680adfc5217SJeff Kirsher 3681adfc5217SJeff Kirsher rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev); 3682adfc5217SJeff Kirsher if (rc) { 3683adfc5217SJeff Kirsher pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file); 36847880b72eSfrançois romieu goto err_release_mips_firmware; 3685adfc5217SJeff Kirsher } 3686adfc5217SJeff Kirsher mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; 3687adfc5217SJeff Kirsher rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; 3688adfc5217SJeff Kirsher if (bp->mips_firmware->size < sizeof(*mips_fw) || 3689adfc5217SJeff Kirsher check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) || 3690adfc5217SJeff Kirsher check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) || 3691adfc5217SJeff Kirsher check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) || 3692adfc5217SJeff Kirsher check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) || 3693adfc5217SJeff Kirsher check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) { 3694adfc5217SJeff Kirsher pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file); 36957880b72eSfrançois romieu rc = -EINVAL; 36967880b72eSfrançois romieu goto err_release_firmware; 3697adfc5217SJeff Kirsher } 3698adfc5217SJeff Kirsher if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) || 3699adfc5217SJeff Kirsher check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) || 3700adfc5217SJeff Kirsher check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) { 3701adfc5217SJeff Kirsher pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file); 37027880b72eSfrançois romieu rc = -EINVAL; 37037880b72eSfrançois romieu goto err_release_firmware; 37047880b72eSfrançois romieu } 37057880b72eSfrançois romieu out: 37067880b72eSfrançois romieu return rc; 37077880b72eSfrançois romieu 37087880b72eSfrançois romieu err_release_firmware: 37097880b72eSfrançois romieu release_firmware(bp->rv2p_firmware); 37107880b72eSfrançois romieu bp->rv2p_firmware = NULL; 37117880b72eSfrançois romieu err_release_mips_firmware: 37127880b72eSfrançois romieu release_firmware(bp->mips_firmware); 37137880b72eSfrançois romieu goto out; 3714adfc5217SJeff Kirsher } 3715adfc5217SJeff Kirsher 37167880b72eSfrançois romieu static int bnx2_request_firmware(struct bnx2 *bp) 37177880b72eSfrançois romieu { 37187880b72eSfrançois romieu return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp); 3719adfc5217SJeff Kirsher } 3720adfc5217SJeff Kirsher 3721adfc5217SJeff Kirsher static u32 3722adfc5217SJeff Kirsher rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code) 3723adfc5217SJeff Kirsher { 3724adfc5217SJeff Kirsher switch (idx) { 3725adfc5217SJeff Kirsher case RV2P_P1_FIXUP_PAGE_SIZE_IDX: 3726adfc5217SJeff Kirsher rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK; 3727adfc5217SJeff Kirsher rv2p_code |= RV2P_BD_PAGE_SIZE; 3728adfc5217SJeff Kirsher break; 3729adfc5217SJeff Kirsher } 3730adfc5217SJeff Kirsher return rv2p_code; 3731adfc5217SJeff Kirsher } 3732adfc5217SJeff Kirsher 3733adfc5217SJeff Kirsher static int 3734adfc5217SJeff Kirsher load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc, 3735adfc5217SJeff Kirsher const struct bnx2_rv2p_fw_file_entry *fw_entry) 3736adfc5217SJeff Kirsher { 3737adfc5217SJeff Kirsher u32 rv2p_code_len, file_offset; 3738adfc5217SJeff Kirsher __be32 *rv2p_code; 3739adfc5217SJeff Kirsher int i; 3740adfc5217SJeff Kirsher u32 val, cmd, addr; 3741adfc5217SJeff Kirsher 3742adfc5217SJeff Kirsher rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len); 3743adfc5217SJeff Kirsher file_offset = be32_to_cpu(fw_entry->rv2p.offset); 3744adfc5217SJeff Kirsher 3745adfc5217SJeff Kirsher rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); 3746adfc5217SJeff Kirsher 3747adfc5217SJeff Kirsher if (rv2p_proc == RV2P_PROC1) { 3748adfc5217SJeff Kirsher cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR; 3749adfc5217SJeff Kirsher addr = BNX2_RV2P_PROC1_ADDR_CMD; 3750adfc5217SJeff Kirsher } else { 3751adfc5217SJeff Kirsher cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR; 3752adfc5217SJeff Kirsher addr = BNX2_RV2P_PROC2_ADDR_CMD; 3753adfc5217SJeff Kirsher } 3754adfc5217SJeff Kirsher 3755adfc5217SJeff Kirsher for (i = 0; i < rv2p_code_len; i += 8) { 3756adfc5217SJeff Kirsher REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code)); 3757adfc5217SJeff Kirsher rv2p_code++; 3758adfc5217SJeff Kirsher REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code)); 3759adfc5217SJeff Kirsher rv2p_code++; 3760adfc5217SJeff Kirsher 3761adfc5217SJeff Kirsher val = (i / 8) | cmd; 3762adfc5217SJeff Kirsher REG_WR(bp, addr, val); 3763adfc5217SJeff Kirsher } 3764adfc5217SJeff Kirsher 3765adfc5217SJeff Kirsher rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); 3766adfc5217SJeff Kirsher for (i = 0; i < 8; i++) { 3767adfc5217SJeff Kirsher u32 loc, code; 3768adfc5217SJeff Kirsher 3769adfc5217SJeff Kirsher loc = be32_to_cpu(fw_entry->fixup[i]); 3770adfc5217SJeff Kirsher if (loc && ((loc * 4) < rv2p_code_len)) { 3771adfc5217SJeff Kirsher code = be32_to_cpu(*(rv2p_code + loc - 1)); 3772adfc5217SJeff Kirsher REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code); 3773adfc5217SJeff Kirsher code = be32_to_cpu(*(rv2p_code + loc)); 3774adfc5217SJeff Kirsher code = rv2p_fw_fixup(rv2p_proc, i, loc, code); 3775adfc5217SJeff Kirsher REG_WR(bp, BNX2_RV2P_INSTR_LOW, code); 3776adfc5217SJeff Kirsher 3777adfc5217SJeff Kirsher val = (loc / 2) | cmd; 3778adfc5217SJeff Kirsher REG_WR(bp, addr, val); 3779adfc5217SJeff Kirsher } 3780adfc5217SJeff Kirsher } 3781adfc5217SJeff Kirsher 3782adfc5217SJeff Kirsher /* Reset the processor, un-stall is done later. */ 3783adfc5217SJeff Kirsher if (rv2p_proc == RV2P_PROC1) { 3784adfc5217SJeff Kirsher REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET); 3785adfc5217SJeff Kirsher } 3786adfc5217SJeff Kirsher else { 3787adfc5217SJeff Kirsher REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); 3788adfc5217SJeff Kirsher } 3789adfc5217SJeff Kirsher 3790adfc5217SJeff Kirsher return 0; 3791adfc5217SJeff Kirsher } 3792adfc5217SJeff Kirsher 3793adfc5217SJeff Kirsher static int 3794adfc5217SJeff Kirsher load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, 3795adfc5217SJeff Kirsher const struct bnx2_mips_fw_file_entry *fw_entry) 3796adfc5217SJeff Kirsher { 3797adfc5217SJeff Kirsher u32 addr, len, file_offset; 3798adfc5217SJeff Kirsher __be32 *data; 3799adfc5217SJeff Kirsher u32 offset; 3800adfc5217SJeff Kirsher u32 val; 3801adfc5217SJeff Kirsher 3802adfc5217SJeff Kirsher /* Halt the CPU. */ 3803adfc5217SJeff Kirsher val = bnx2_reg_rd_ind(bp, cpu_reg->mode); 3804adfc5217SJeff Kirsher val |= cpu_reg->mode_value_halt; 3805adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, cpu_reg->mode, val); 3806adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); 3807adfc5217SJeff Kirsher 3808adfc5217SJeff Kirsher /* Load the Text area. */ 3809adfc5217SJeff Kirsher addr = be32_to_cpu(fw_entry->text.addr); 3810adfc5217SJeff Kirsher len = be32_to_cpu(fw_entry->text.len); 3811adfc5217SJeff Kirsher file_offset = be32_to_cpu(fw_entry->text.offset); 3812adfc5217SJeff Kirsher data = (__be32 *)(bp->mips_firmware->data + file_offset); 3813adfc5217SJeff Kirsher 3814adfc5217SJeff Kirsher offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); 3815adfc5217SJeff Kirsher if (len) { 3816adfc5217SJeff Kirsher int j; 3817adfc5217SJeff Kirsher 3818adfc5217SJeff Kirsher for (j = 0; j < (len / 4); j++, offset += 4) 3819adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); 3820adfc5217SJeff Kirsher } 3821adfc5217SJeff Kirsher 3822adfc5217SJeff Kirsher /* Load the Data area. */ 3823adfc5217SJeff Kirsher addr = be32_to_cpu(fw_entry->data.addr); 3824adfc5217SJeff Kirsher len = be32_to_cpu(fw_entry->data.len); 3825adfc5217SJeff Kirsher file_offset = be32_to_cpu(fw_entry->data.offset); 3826adfc5217SJeff Kirsher data = (__be32 *)(bp->mips_firmware->data + file_offset); 3827adfc5217SJeff Kirsher 3828adfc5217SJeff Kirsher offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); 3829adfc5217SJeff Kirsher if (len) { 3830adfc5217SJeff Kirsher int j; 3831adfc5217SJeff Kirsher 3832adfc5217SJeff Kirsher for (j = 0; j < (len / 4); j++, offset += 4) 3833adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); 3834adfc5217SJeff Kirsher } 3835adfc5217SJeff Kirsher 3836adfc5217SJeff Kirsher /* Load the Read-Only area. */ 3837adfc5217SJeff Kirsher addr = be32_to_cpu(fw_entry->rodata.addr); 3838adfc5217SJeff Kirsher len = be32_to_cpu(fw_entry->rodata.len); 3839adfc5217SJeff Kirsher file_offset = be32_to_cpu(fw_entry->rodata.offset); 3840adfc5217SJeff Kirsher data = (__be32 *)(bp->mips_firmware->data + file_offset); 3841adfc5217SJeff Kirsher 3842adfc5217SJeff Kirsher offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); 3843adfc5217SJeff Kirsher if (len) { 3844adfc5217SJeff Kirsher int j; 3845adfc5217SJeff Kirsher 3846adfc5217SJeff Kirsher for (j = 0; j < (len / 4); j++, offset += 4) 3847adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); 3848adfc5217SJeff Kirsher } 3849adfc5217SJeff Kirsher 3850adfc5217SJeff Kirsher /* Clear the pre-fetch instruction. */ 3851adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); 3852adfc5217SJeff Kirsher 3853adfc5217SJeff Kirsher val = be32_to_cpu(fw_entry->start_addr); 3854adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, cpu_reg->pc, val); 3855adfc5217SJeff Kirsher 3856adfc5217SJeff Kirsher /* Start the CPU. */ 3857adfc5217SJeff Kirsher val = bnx2_reg_rd_ind(bp, cpu_reg->mode); 3858adfc5217SJeff Kirsher val &= ~cpu_reg->mode_value_halt; 3859adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); 3860adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, cpu_reg->mode, val); 3861adfc5217SJeff Kirsher 3862adfc5217SJeff Kirsher return 0; 3863adfc5217SJeff Kirsher } 3864adfc5217SJeff Kirsher 3865adfc5217SJeff Kirsher static int 3866adfc5217SJeff Kirsher bnx2_init_cpus(struct bnx2 *bp) 3867adfc5217SJeff Kirsher { 3868adfc5217SJeff Kirsher const struct bnx2_mips_fw_file *mips_fw = 3869adfc5217SJeff Kirsher (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; 3870adfc5217SJeff Kirsher const struct bnx2_rv2p_fw_file *rv2p_fw = 3871adfc5217SJeff Kirsher (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; 3872adfc5217SJeff Kirsher int rc; 3873adfc5217SJeff Kirsher 3874adfc5217SJeff Kirsher /* Initialize the RV2P processor. */ 3875adfc5217SJeff Kirsher load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1); 3876adfc5217SJeff Kirsher load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2); 3877adfc5217SJeff Kirsher 3878adfc5217SJeff Kirsher /* Initialize the RX Processor. */ 3879adfc5217SJeff Kirsher rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp); 3880adfc5217SJeff Kirsher if (rc) 3881adfc5217SJeff Kirsher goto init_cpu_err; 3882adfc5217SJeff Kirsher 3883adfc5217SJeff Kirsher /* Initialize the TX Processor. */ 3884adfc5217SJeff Kirsher rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp); 3885adfc5217SJeff Kirsher if (rc) 3886adfc5217SJeff Kirsher goto init_cpu_err; 3887adfc5217SJeff Kirsher 3888adfc5217SJeff Kirsher /* Initialize the TX Patch-up Processor. */ 3889adfc5217SJeff Kirsher rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat); 3890adfc5217SJeff Kirsher if (rc) 3891adfc5217SJeff Kirsher goto init_cpu_err; 3892adfc5217SJeff Kirsher 3893adfc5217SJeff Kirsher /* Initialize the Completion Processor. */ 3894adfc5217SJeff Kirsher rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com); 3895adfc5217SJeff Kirsher if (rc) 3896adfc5217SJeff Kirsher goto init_cpu_err; 3897adfc5217SJeff Kirsher 3898adfc5217SJeff Kirsher /* Initialize the Command Processor. */ 3899adfc5217SJeff Kirsher rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp); 3900adfc5217SJeff Kirsher 3901adfc5217SJeff Kirsher init_cpu_err: 3902adfc5217SJeff Kirsher return rc; 3903adfc5217SJeff Kirsher } 3904adfc5217SJeff Kirsher 3905adfc5217SJeff Kirsher static int 3906adfc5217SJeff Kirsher bnx2_set_power_state(struct bnx2 *bp, pci_power_t state) 3907adfc5217SJeff Kirsher { 3908adfc5217SJeff Kirsher u16 pmcsr; 3909adfc5217SJeff Kirsher 3910adfc5217SJeff Kirsher pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr); 3911adfc5217SJeff Kirsher 3912adfc5217SJeff Kirsher switch (state) { 3913adfc5217SJeff Kirsher case PCI_D0: { 3914adfc5217SJeff Kirsher u32 val; 3915adfc5217SJeff Kirsher 3916adfc5217SJeff Kirsher pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, 3917adfc5217SJeff Kirsher (pmcsr & ~PCI_PM_CTRL_STATE_MASK) | 3918adfc5217SJeff Kirsher PCI_PM_CTRL_PME_STATUS); 3919adfc5217SJeff Kirsher 3920adfc5217SJeff Kirsher if (pmcsr & PCI_PM_CTRL_STATE_MASK) 3921adfc5217SJeff Kirsher /* delay required during transition out of D3hot */ 3922adfc5217SJeff Kirsher msleep(20); 3923adfc5217SJeff Kirsher 3924adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_EMAC_MODE); 3925adfc5217SJeff Kirsher val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; 3926adfc5217SJeff Kirsher val &= ~BNX2_EMAC_MODE_MPKT; 3927adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MODE, val); 3928adfc5217SJeff Kirsher 3929adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_RPM_CONFIG); 3930adfc5217SJeff Kirsher val &= ~BNX2_RPM_CONFIG_ACPI_ENA; 3931adfc5217SJeff Kirsher REG_WR(bp, BNX2_RPM_CONFIG, val); 3932adfc5217SJeff Kirsher break; 3933adfc5217SJeff Kirsher } 3934adfc5217SJeff Kirsher case PCI_D3hot: { 3935adfc5217SJeff Kirsher int i; 3936adfc5217SJeff Kirsher u32 val, wol_msg; 3937adfc5217SJeff Kirsher 3938adfc5217SJeff Kirsher if (bp->wol) { 3939adfc5217SJeff Kirsher u32 advertising; 3940adfc5217SJeff Kirsher u8 autoneg; 3941adfc5217SJeff Kirsher 3942adfc5217SJeff Kirsher autoneg = bp->autoneg; 3943adfc5217SJeff Kirsher advertising = bp->advertising; 3944adfc5217SJeff Kirsher 3945adfc5217SJeff Kirsher if (bp->phy_port == PORT_TP) { 3946adfc5217SJeff Kirsher bp->autoneg = AUTONEG_SPEED; 3947adfc5217SJeff Kirsher bp->advertising = ADVERTISED_10baseT_Half | 3948adfc5217SJeff Kirsher ADVERTISED_10baseT_Full | 3949adfc5217SJeff Kirsher ADVERTISED_100baseT_Half | 3950adfc5217SJeff Kirsher ADVERTISED_100baseT_Full | 3951adfc5217SJeff Kirsher ADVERTISED_Autoneg; 3952adfc5217SJeff Kirsher } 3953adfc5217SJeff Kirsher 3954adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 3955adfc5217SJeff Kirsher bnx2_setup_phy(bp, bp->phy_port); 3956adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 3957adfc5217SJeff Kirsher 3958adfc5217SJeff Kirsher bp->autoneg = autoneg; 3959adfc5217SJeff Kirsher bp->advertising = advertising; 3960adfc5217SJeff Kirsher 3961adfc5217SJeff Kirsher bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); 3962adfc5217SJeff Kirsher 3963adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_EMAC_MODE); 3964adfc5217SJeff Kirsher 3965adfc5217SJeff Kirsher /* Enable port mode. */ 3966adfc5217SJeff Kirsher val &= ~BNX2_EMAC_MODE_PORT; 3967adfc5217SJeff Kirsher val |= BNX2_EMAC_MODE_MPKT_RCVD | 3968adfc5217SJeff Kirsher BNX2_EMAC_MODE_ACPI_RCVD | 3969adfc5217SJeff Kirsher BNX2_EMAC_MODE_MPKT; 3970adfc5217SJeff Kirsher if (bp->phy_port == PORT_TP) 3971adfc5217SJeff Kirsher val |= BNX2_EMAC_MODE_PORT_MII; 3972adfc5217SJeff Kirsher else { 3973adfc5217SJeff Kirsher val |= BNX2_EMAC_MODE_PORT_GMII; 3974adfc5217SJeff Kirsher if (bp->line_speed == SPEED_2500) 3975adfc5217SJeff Kirsher val |= BNX2_EMAC_MODE_25G_MODE; 3976adfc5217SJeff Kirsher } 3977adfc5217SJeff Kirsher 3978adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MODE, val); 3979adfc5217SJeff Kirsher 3980adfc5217SJeff Kirsher /* receive all multicast */ 3981adfc5217SJeff Kirsher for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 3982adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), 3983adfc5217SJeff Kirsher 0xffffffff); 3984adfc5217SJeff Kirsher } 3985adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_RX_MODE, 3986adfc5217SJeff Kirsher BNX2_EMAC_RX_MODE_SORT_MODE); 3987adfc5217SJeff Kirsher 3988adfc5217SJeff Kirsher val = 1 | BNX2_RPM_SORT_USER0_BC_EN | 3989adfc5217SJeff Kirsher BNX2_RPM_SORT_USER0_MC_EN; 3990adfc5217SJeff Kirsher REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); 3991adfc5217SJeff Kirsher REG_WR(bp, BNX2_RPM_SORT_USER0, val); 3992adfc5217SJeff Kirsher REG_WR(bp, BNX2_RPM_SORT_USER0, val | 3993adfc5217SJeff Kirsher BNX2_RPM_SORT_USER0_ENA); 3994adfc5217SJeff Kirsher 3995adfc5217SJeff Kirsher /* Need to enable EMAC and RPM for WOL. */ 3996adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 3997adfc5217SJeff Kirsher BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE | 3998adfc5217SJeff Kirsher BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE | 3999adfc5217SJeff Kirsher BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE); 4000adfc5217SJeff Kirsher 4001adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_RPM_CONFIG); 4002adfc5217SJeff Kirsher val &= ~BNX2_RPM_CONFIG_ACPI_ENA; 4003adfc5217SJeff Kirsher REG_WR(bp, BNX2_RPM_CONFIG, val); 4004adfc5217SJeff Kirsher 4005adfc5217SJeff Kirsher wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL; 4006adfc5217SJeff Kirsher } 4007adfc5217SJeff Kirsher else { 4008adfc5217SJeff Kirsher wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; 4009adfc5217SJeff Kirsher } 4010adfc5217SJeff Kirsher 4011adfc5217SJeff Kirsher if (!(bp->flags & BNX2_FLAG_NO_WOL)) 4012adfc5217SJeff Kirsher bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 4013adfc5217SJeff Kirsher 1, 0); 4014adfc5217SJeff Kirsher 4015adfc5217SJeff Kirsher pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 4016adfc5217SJeff Kirsher if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || 4017adfc5217SJeff Kirsher (CHIP_ID(bp) == CHIP_ID_5706_A1)) { 4018adfc5217SJeff Kirsher 4019adfc5217SJeff Kirsher if (bp->wol) 4020adfc5217SJeff Kirsher pmcsr |= 3; 4021adfc5217SJeff Kirsher } 4022adfc5217SJeff Kirsher else { 4023adfc5217SJeff Kirsher pmcsr |= 3; 4024adfc5217SJeff Kirsher } 4025adfc5217SJeff Kirsher if (bp->wol) { 4026adfc5217SJeff Kirsher pmcsr |= PCI_PM_CTRL_PME_ENABLE; 4027adfc5217SJeff Kirsher } 4028adfc5217SJeff Kirsher pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, 4029adfc5217SJeff Kirsher pmcsr); 4030adfc5217SJeff Kirsher 4031adfc5217SJeff Kirsher /* No more memory access after this point until 4032adfc5217SJeff Kirsher * device is brought back to D0. 4033adfc5217SJeff Kirsher */ 4034adfc5217SJeff Kirsher udelay(50); 4035adfc5217SJeff Kirsher break; 4036adfc5217SJeff Kirsher } 4037adfc5217SJeff Kirsher default: 4038adfc5217SJeff Kirsher return -EINVAL; 4039adfc5217SJeff Kirsher } 4040adfc5217SJeff Kirsher return 0; 4041adfc5217SJeff Kirsher } 4042adfc5217SJeff Kirsher 4043adfc5217SJeff Kirsher static int 4044adfc5217SJeff Kirsher bnx2_acquire_nvram_lock(struct bnx2 *bp) 4045adfc5217SJeff Kirsher { 4046adfc5217SJeff Kirsher u32 val; 4047adfc5217SJeff Kirsher int j; 4048adfc5217SJeff Kirsher 4049adfc5217SJeff Kirsher /* Request access to the flash interface. */ 4050adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2); 4051adfc5217SJeff Kirsher for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4052adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_NVM_SW_ARB); 4053adfc5217SJeff Kirsher if (val & BNX2_NVM_SW_ARB_ARB_ARB2) 4054adfc5217SJeff Kirsher break; 4055adfc5217SJeff Kirsher 4056adfc5217SJeff Kirsher udelay(5); 4057adfc5217SJeff Kirsher } 4058adfc5217SJeff Kirsher 4059adfc5217SJeff Kirsher if (j >= NVRAM_TIMEOUT_COUNT) 4060adfc5217SJeff Kirsher return -EBUSY; 4061adfc5217SJeff Kirsher 4062adfc5217SJeff Kirsher return 0; 4063adfc5217SJeff Kirsher } 4064adfc5217SJeff Kirsher 4065adfc5217SJeff Kirsher static int 4066adfc5217SJeff Kirsher bnx2_release_nvram_lock(struct bnx2 *bp) 4067adfc5217SJeff Kirsher { 4068adfc5217SJeff Kirsher int j; 4069adfc5217SJeff Kirsher u32 val; 4070adfc5217SJeff Kirsher 4071adfc5217SJeff Kirsher /* Relinquish nvram interface. */ 4072adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2); 4073adfc5217SJeff Kirsher 4074adfc5217SJeff Kirsher for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4075adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_NVM_SW_ARB); 4076adfc5217SJeff Kirsher if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2)) 4077adfc5217SJeff Kirsher break; 4078adfc5217SJeff Kirsher 4079adfc5217SJeff Kirsher udelay(5); 4080adfc5217SJeff Kirsher } 4081adfc5217SJeff Kirsher 4082adfc5217SJeff Kirsher if (j >= NVRAM_TIMEOUT_COUNT) 4083adfc5217SJeff Kirsher return -EBUSY; 4084adfc5217SJeff Kirsher 4085adfc5217SJeff Kirsher return 0; 4086adfc5217SJeff Kirsher } 4087adfc5217SJeff Kirsher 4088adfc5217SJeff Kirsher 4089adfc5217SJeff Kirsher static int 4090adfc5217SJeff Kirsher bnx2_enable_nvram_write(struct bnx2 *bp) 4091adfc5217SJeff Kirsher { 4092adfc5217SJeff Kirsher u32 val; 4093adfc5217SJeff Kirsher 4094adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_MISC_CFG); 4095adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI); 4096adfc5217SJeff Kirsher 4097adfc5217SJeff Kirsher if (bp->flash_info->flags & BNX2_NV_WREN) { 4098adfc5217SJeff Kirsher int j; 4099adfc5217SJeff Kirsher 4100adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); 4101adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_COMMAND, 4102adfc5217SJeff Kirsher BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT); 4103adfc5217SJeff Kirsher 4104adfc5217SJeff Kirsher for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4105adfc5217SJeff Kirsher udelay(5); 4106adfc5217SJeff Kirsher 4107adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_NVM_COMMAND); 4108adfc5217SJeff Kirsher if (val & BNX2_NVM_COMMAND_DONE) 4109adfc5217SJeff Kirsher break; 4110adfc5217SJeff Kirsher } 4111adfc5217SJeff Kirsher 4112adfc5217SJeff Kirsher if (j >= NVRAM_TIMEOUT_COUNT) 4113adfc5217SJeff Kirsher return -EBUSY; 4114adfc5217SJeff Kirsher } 4115adfc5217SJeff Kirsher return 0; 4116adfc5217SJeff Kirsher } 4117adfc5217SJeff Kirsher 4118adfc5217SJeff Kirsher static void 4119adfc5217SJeff Kirsher bnx2_disable_nvram_write(struct bnx2 *bp) 4120adfc5217SJeff Kirsher { 4121adfc5217SJeff Kirsher u32 val; 4122adfc5217SJeff Kirsher 4123adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_MISC_CFG); 4124adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN); 4125adfc5217SJeff Kirsher } 4126adfc5217SJeff Kirsher 4127adfc5217SJeff Kirsher 4128adfc5217SJeff Kirsher static void 4129adfc5217SJeff Kirsher bnx2_enable_nvram_access(struct bnx2 *bp) 4130adfc5217SJeff Kirsher { 4131adfc5217SJeff Kirsher u32 val; 4132adfc5217SJeff Kirsher 4133adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); 4134adfc5217SJeff Kirsher /* Enable both bits, even on read. */ 4135adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, 4136adfc5217SJeff Kirsher val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); 4137adfc5217SJeff Kirsher } 4138adfc5217SJeff Kirsher 4139adfc5217SJeff Kirsher static void 4140adfc5217SJeff Kirsher bnx2_disable_nvram_access(struct bnx2 *bp) 4141adfc5217SJeff Kirsher { 4142adfc5217SJeff Kirsher u32 val; 4143adfc5217SJeff Kirsher 4144adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); 4145adfc5217SJeff Kirsher /* Disable both bits, even after read. */ 4146adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, 4147adfc5217SJeff Kirsher val & ~(BNX2_NVM_ACCESS_ENABLE_EN | 4148adfc5217SJeff Kirsher BNX2_NVM_ACCESS_ENABLE_WR_EN)); 4149adfc5217SJeff Kirsher } 4150adfc5217SJeff Kirsher 4151adfc5217SJeff Kirsher static int 4152adfc5217SJeff Kirsher bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset) 4153adfc5217SJeff Kirsher { 4154adfc5217SJeff Kirsher u32 cmd; 4155adfc5217SJeff Kirsher int j; 4156adfc5217SJeff Kirsher 4157adfc5217SJeff Kirsher if (bp->flash_info->flags & BNX2_NV_BUFFERED) 4158adfc5217SJeff Kirsher /* Buffered flash, no erase needed */ 4159adfc5217SJeff Kirsher return 0; 4160adfc5217SJeff Kirsher 4161adfc5217SJeff Kirsher /* Build an erase command */ 4162adfc5217SJeff Kirsher cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR | 4163adfc5217SJeff Kirsher BNX2_NVM_COMMAND_DOIT; 4164adfc5217SJeff Kirsher 4165adfc5217SJeff Kirsher /* Need to clear DONE bit separately. */ 4166adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); 4167adfc5217SJeff Kirsher 4168adfc5217SJeff Kirsher /* Address of the NVRAM to read from. */ 4169adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); 4170adfc5217SJeff Kirsher 4171adfc5217SJeff Kirsher /* Issue an erase command. */ 4172adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_COMMAND, cmd); 4173adfc5217SJeff Kirsher 4174adfc5217SJeff Kirsher /* Wait for completion. */ 4175adfc5217SJeff Kirsher for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4176adfc5217SJeff Kirsher u32 val; 4177adfc5217SJeff Kirsher 4178adfc5217SJeff Kirsher udelay(5); 4179adfc5217SJeff Kirsher 4180adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_NVM_COMMAND); 4181adfc5217SJeff Kirsher if (val & BNX2_NVM_COMMAND_DONE) 4182adfc5217SJeff Kirsher break; 4183adfc5217SJeff Kirsher } 4184adfc5217SJeff Kirsher 4185adfc5217SJeff Kirsher if (j >= NVRAM_TIMEOUT_COUNT) 4186adfc5217SJeff Kirsher return -EBUSY; 4187adfc5217SJeff Kirsher 4188adfc5217SJeff Kirsher return 0; 4189adfc5217SJeff Kirsher } 4190adfc5217SJeff Kirsher 4191adfc5217SJeff Kirsher static int 4192adfc5217SJeff Kirsher bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) 4193adfc5217SJeff Kirsher { 4194adfc5217SJeff Kirsher u32 cmd; 4195adfc5217SJeff Kirsher int j; 4196adfc5217SJeff Kirsher 4197adfc5217SJeff Kirsher /* Build the command word. */ 4198adfc5217SJeff Kirsher cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags; 4199adfc5217SJeff Kirsher 4200adfc5217SJeff Kirsher /* Calculate an offset of a buffered flash, not needed for 5709. */ 4201adfc5217SJeff Kirsher if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { 4202adfc5217SJeff Kirsher offset = ((offset / bp->flash_info->page_size) << 4203adfc5217SJeff Kirsher bp->flash_info->page_bits) + 4204adfc5217SJeff Kirsher (offset % bp->flash_info->page_size); 4205adfc5217SJeff Kirsher } 4206adfc5217SJeff Kirsher 4207adfc5217SJeff Kirsher /* Need to clear DONE bit separately. */ 4208adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); 4209adfc5217SJeff Kirsher 4210adfc5217SJeff Kirsher /* Address of the NVRAM to read from. */ 4211adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); 4212adfc5217SJeff Kirsher 4213adfc5217SJeff Kirsher /* Issue a read command. */ 4214adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_COMMAND, cmd); 4215adfc5217SJeff Kirsher 4216adfc5217SJeff Kirsher /* Wait for completion. */ 4217adfc5217SJeff Kirsher for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4218adfc5217SJeff Kirsher u32 val; 4219adfc5217SJeff Kirsher 4220adfc5217SJeff Kirsher udelay(5); 4221adfc5217SJeff Kirsher 4222adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_NVM_COMMAND); 4223adfc5217SJeff Kirsher if (val & BNX2_NVM_COMMAND_DONE) { 4224adfc5217SJeff Kirsher __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ)); 4225adfc5217SJeff Kirsher memcpy(ret_val, &v, 4); 4226adfc5217SJeff Kirsher break; 4227adfc5217SJeff Kirsher } 4228adfc5217SJeff Kirsher } 4229adfc5217SJeff Kirsher if (j >= NVRAM_TIMEOUT_COUNT) 4230adfc5217SJeff Kirsher return -EBUSY; 4231adfc5217SJeff Kirsher 4232adfc5217SJeff Kirsher return 0; 4233adfc5217SJeff Kirsher } 4234adfc5217SJeff Kirsher 4235adfc5217SJeff Kirsher 4236adfc5217SJeff Kirsher static int 4237adfc5217SJeff Kirsher bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) 4238adfc5217SJeff Kirsher { 4239adfc5217SJeff Kirsher u32 cmd; 4240adfc5217SJeff Kirsher __be32 val32; 4241adfc5217SJeff Kirsher int j; 4242adfc5217SJeff Kirsher 4243adfc5217SJeff Kirsher /* Build the command word. */ 4244adfc5217SJeff Kirsher cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags; 4245adfc5217SJeff Kirsher 4246adfc5217SJeff Kirsher /* Calculate an offset of a buffered flash, not needed for 5709. */ 4247adfc5217SJeff Kirsher if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { 4248adfc5217SJeff Kirsher offset = ((offset / bp->flash_info->page_size) << 4249adfc5217SJeff Kirsher bp->flash_info->page_bits) + 4250adfc5217SJeff Kirsher (offset % bp->flash_info->page_size); 4251adfc5217SJeff Kirsher } 4252adfc5217SJeff Kirsher 4253adfc5217SJeff Kirsher /* Need to clear DONE bit separately. */ 4254adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); 4255adfc5217SJeff Kirsher 4256adfc5217SJeff Kirsher memcpy(&val32, val, 4); 4257adfc5217SJeff Kirsher 4258adfc5217SJeff Kirsher /* Write the data. */ 4259adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32)); 4260adfc5217SJeff Kirsher 4261adfc5217SJeff Kirsher /* Address of the NVRAM to write to. */ 4262adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); 4263adfc5217SJeff Kirsher 4264adfc5217SJeff Kirsher /* Issue the write command. */ 4265adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_COMMAND, cmd); 4266adfc5217SJeff Kirsher 4267adfc5217SJeff Kirsher /* Wait for completion. */ 4268adfc5217SJeff Kirsher for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4269adfc5217SJeff Kirsher udelay(5); 4270adfc5217SJeff Kirsher 4271adfc5217SJeff Kirsher if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE) 4272adfc5217SJeff Kirsher break; 4273adfc5217SJeff Kirsher } 4274adfc5217SJeff Kirsher if (j >= NVRAM_TIMEOUT_COUNT) 4275adfc5217SJeff Kirsher return -EBUSY; 4276adfc5217SJeff Kirsher 4277adfc5217SJeff Kirsher return 0; 4278adfc5217SJeff Kirsher } 4279adfc5217SJeff Kirsher 4280adfc5217SJeff Kirsher static int 4281adfc5217SJeff Kirsher bnx2_init_nvram(struct bnx2 *bp) 4282adfc5217SJeff Kirsher { 4283adfc5217SJeff Kirsher u32 val; 4284adfc5217SJeff Kirsher int j, entry_count, rc = 0; 4285adfc5217SJeff Kirsher const struct flash_spec *flash; 4286adfc5217SJeff Kirsher 4287adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 4288adfc5217SJeff Kirsher bp->flash_info = &flash_5709; 4289adfc5217SJeff Kirsher goto get_flash_size; 4290adfc5217SJeff Kirsher } 4291adfc5217SJeff Kirsher 4292adfc5217SJeff Kirsher /* Determine the selected interface. */ 4293adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_NVM_CFG1); 4294adfc5217SJeff Kirsher 4295adfc5217SJeff Kirsher entry_count = ARRAY_SIZE(flash_table); 4296adfc5217SJeff Kirsher 4297adfc5217SJeff Kirsher if (val & 0x40000000) { 4298adfc5217SJeff Kirsher 4299adfc5217SJeff Kirsher /* Flash interface has been reconfigured */ 4300adfc5217SJeff Kirsher for (j = 0, flash = &flash_table[0]; j < entry_count; 4301adfc5217SJeff Kirsher j++, flash++) { 4302adfc5217SJeff Kirsher if ((val & FLASH_BACKUP_STRAP_MASK) == 4303adfc5217SJeff Kirsher (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 4304adfc5217SJeff Kirsher bp->flash_info = flash; 4305adfc5217SJeff Kirsher break; 4306adfc5217SJeff Kirsher } 4307adfc5217SJeff Kirsher } 4308adfc5217SJeff Kirsher } 4309adfc5217SJeff Kirsher else { 4310adfc5217SJeff Kirsher u32 mask; 4311adfc5217SJeff Kirsher /* Not yet been reconfigured */ 4312adfc5217SJeff Kirsher 4313adfc5217SJeff Kirsher if (val & (1 << 23)) 4314adfc5217SJeff Kirsher mask = FLASH_BACKUP_STRAP_MASK; 4315adfc5217SJeff Kirsher else 4316adfc5217SJeff Kirsher mask = FLASH_STRAP_MASK; 4317adfc5217SJeff Kirsher 4318adfc5217SJeff Kirsher for (j = 0, flash = &flash_table[0]; j < entry_count; 4319adfc5217SJeff Kirsher j++, flash++) { 4320adfc5217SJeff Kirsher 4321adfc5217SJeff Kirsher if ((val & mask) == (flash->strapping & mask)) { 4322adfc5217SJeff Kirsher bp->flash_info = flash; 4323adfc5217SJeff Kirsher 4324adfc5217SJeff Kirsher /* Request access to the flash interface. */ 4325adfc5217SJeff Kirsher if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) 4326adfc5217SJeff Kirsher return rc; 4327adfc5217SJeff Kirsher 4328adfc5217SJeff Kirsher /* Enable access to flash interface */ 4329adfc5217SJeff Kirsher bnx2_enable_nvram_access(bp); 4330adfc5217SJeff Kirsher 4331adfc5217SJeff Kirsher /* Reconfigure the flash interface */ 4332adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_CFG1, flash->config1); 4333adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_CFG2, flash->config2); 4334adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_CFG3, flash->config3); 4335adfc5217SJeff Kirsher REG_WR(bp, BNX2_NVM_WRITE1, flash->write1); 4336adfc5217SJeff Kirsher 4337adfc5217SJeff Kirsher /* Disable access to flash interface */ 4338adfc5217SJeff Kirsher bnx2_disable_nvram_access(bp); 4339adfc5217SJeff Kirsher bnx2_release_nvram_lock(bp); 4340adfc5217SJeff Kirsher 4341adfc5217SJeff Kirsher break; 4342adfc5217SJeff Kirsher } 4343adfc5217SJeff Kirsher } 4344adfc5217SJeff Kirsher } /* if (val & 0x40000000) */ 4345adfc5217SJeff Kirsher 4346adfc5217SJeff Kirsher if (j == entry_count) { 4347adfc5217SJeff Kirsher bp->flash_info = NULL; 4348adfc5217SJeff Kirsher pr_alert("Unknown flash/EEPROM type\n"); 4349adfc5217SJeff Kirsher return -ENODEV; 4350adfc5217SJeff Kirsher } 4351adfc5217SJeff Kirsher 4352adfc5217SJeff Kirsher get_flash_size: 4353adfc5217SJeff Kirsher val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2); 4354adfc5217SJeff Kirsher val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK; 4355adfc5217SJeff Kirsher if (val) 4356adfc5217SJeff Kirsher bp->flash_size = val; 4357adfc5217SJeff Kirsher else 4358adfc5217SJeff Kirsher bp->flash_size = bp->flash_info->total_size; 4359adfc5217SJeff Kirsher 4360adfc5217SJeff Kirsher return rc; 4361adfc5217SJeff Kirsher } 4362adfc5217SJeff Kirsher 4363adfc5217SJeff Kirsher static int 4364adfc5217SJeff Kirsher bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf, 4365adfc5217SJeff Kirsher int buf_size) 4366adfc5217SJeff Kirsher { 4367adfc5217SJeff Kirsher int rc = 0; 4368adfc5217SJeff Kirsher u32 cmd_flags, offset32, len32, extra; 4369adfc5217SJeff Kirsher 4370adfc5217SJeff Kirsher if (buf_size == 0) 4371adfc5217SJeff Kirsher return 0; 4372adfc5217SJeff Kirsher 4373adfc5217SJeff Kirsher /* Request access to the flash interface. */ 4374adfc5217SJeff Kirsher if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) 4375adfc5217SJeff Kirsher return rc; 4376adfc5217SJeff Kirsher 4377adfc5217SJeff Kirsher /* Enable access to flash interface */ 4378adfc5217SJeff Kirsher bnx2_enable_nvram_access(bp); 4379adfc5217SJeff Kirsher 4380adfc5217SJeff Kirsher len32 = buf_size; 4381adfc5217SJeff Kirsher offset32 = offset; 4382adfc5217SJeff Kirsher extra = 0; 4383adfc5217SJeff Kirsher 4384adfc5217SJeff Kirsher cmd_flags = 0; 4385adfc5217SJeff Kirsher 4386adfc5217SJeff Kirsher if (offset32 & 3) { 4387adfc5217SJeff Kirsher u8 buf[4]; 4388adfc5217SJeff Kirsher u32 pre_len; 4389adfc5217SJeff Kirsher 4390adfc5217SJeff Kirsher offset32 &= ~3; 4391adfc5217SJeff Kirsher pre_len = 4 - (offset & 3); 4392adfc5217SJeff Kirsher 4393adfc5217SJeff Kirsher if (pre_len >= len32) { 4394adfc5217SJeff Kirsher pre_len = len32; 4395adfc5217SJeff Kirsher cmd_flags = BNX2_NVM_COMMAND_FIRST | 4396adfc5217SJeff Kirsher BNX2_NVM_COMMAND_LAST; 4397adfc5217SJeff Kirsher } 4398adfc5217SJeff Kirsher else { 4399adfc5217SJeff Kirsher cmd_flags = BNX2_NVM_COMMAND_FIRST; 4400adfc5217SJeff Kirsher } 4401adfc5217SJeff Kirsher 4402adfc5217SJeff Kirsher rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); 4403adfc5217SJeff Kirsher 4404adfc5217SJeff Kirsher if (rc) 4405adfc5217SJeff Kirsher return rc; 4406adfc5217SJeff Kirsher 4407adfc5217SJeff Kirsher memcpy(ret_buf, buf + (offset & 3), pre_len); 4408adfc5217SJeff Kirsher 4409adfc5217SJeff Kirsher offset32 += 4; 4410adfc5217SJeff Kirsher ret_buf += pre_len; 4411adfc5217SJeff Kirsher len32 -= pre_len; 4412adfc5217SJeff Kirsher } 4413adfc5217SJeff Kirsher if (len32 & 3) { 4414adfc5217SJeff Kirsher extra = 4 - (len32 & 3); 4415adfc5217SJeff Kirsher len32 = (len32 + 4) & ~3; 4416adfc5217SJeff Kirsher } 4417adfc5217SJeff Kirsher 4418adfc5217SJeff Kirsher if (len32 == 4) { 4419adfc5217SJeff Kirsher u8 buf[4]; 4420adfc5217SJeff Kirsher 4421adfc5217SJeff Kirsher if (cmd_flags) 4422adfc5217SJeff Kirsher cmd_flags = BNX2_NVM_COMMAND_LAST; 4423adfc5217SJeff Kirsher else 4424adfc5217SJeff Kirsher cmd_flags = BNX2_NVM_COMMAND_FIRST | 4425adfc5217SJeff Kirsher BNX2_NVM_COMMAND_LAST; 4426adfc5217SJeff Kirsher 4427adfc5217SJeff Kirsher rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); 4428adfc5217SJeff Kirsher 4429adfc5217SJeff Kirsher memcpy(ret_buf, buf, 4 - extra); 4430adfc5217SJeff Kirsher } 4431adfc5217SJeff Kirsher else if (len32 > 0) { 4432adfc5217SJeff Kirsher u8 buf[4]; 4433adfc5217SJeff Kirsher 4434adfc5217SJeff Kirsher /* Read the first word. */ 4435adfc5217SJeff Kirsher if (cmd_flags) 4436adfc5217SJeff Kirsher cmd_flags = 0; 4437adfc5217SJeff Kirsher else 4438adfc5217SJeff Kirsher cmd_flags = BNX2_NVM_COMMAND_FIRST; 4439adfc5217SJeff Kirsher 4440adfc5217SJeff Kirsher rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags); 4441adfc5217SJeff Kirsher 4442adfc5217SJeff Kirsher /* Advance to the next dword. */ 4443adfc5217SJeff Kirsher offset32 += 4; 4444adfc5217SJeff Kirsher ret_buf += 4; 4445adfc5217SJeff Kirsher len32 -= 4; 4446adfc5217SJeff Kirsher 4447adfc5217SJeff Kirsher while (len32 > 4 && rc == 0) { 4448adfc5217SJeff Kirsher rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0); 4449adfc5217SJeff Kirsher 4450adfc5217SJeff Kirsher /* Advance to the next dword. */ 4451adfc5217SJeff Kirsher offset32 += 4; 4452adfc5217SJeff Kirsher ret_buf += 4; 4453adfc5217SJeff Kirsher len32 -= 4; 4454adfc5217SJeff Kirsher } 4455adfc5217SJeff Kirsher 4456adfc5217SJeff Kirsher if (rc) 4457adfc5217SJeff Kirsher return rc; 4458adfc5217SJeff Kirsher 4459adfc5217SJeff Kirsher cmd_flags = BNX2_NVM_COMMAND_LAST; 4460adfc5217SJeff Kirsher rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); 4461adfc5217SJeff Kirsher 4462adfc5217SJeff Kirsher memcpy(ret_buf, buf, 4 - extra); 4463adfc5217SJeff Kirsher } 4464adfc5217SJeff Kirsher 4465adfc5217SJeff Kirsher /* Disable access to flash interface */ 4466adfc5217SJeff Kirsher bnx2_disable_nvram_access(bp); 4467adfc5217SJeff Kirsher 4468adfc5217SJeff Kirsher bnx2_release_nvram_lock(bp); 4469adfc5217SJeff Kirsher 4470adfc5217SJeff Kirsher return rc; 4471adfc5217SJeff Kirsher } 4472adfc5217SJeff Kirsher 4473adfc5217SJeff Kirsher static int 4474adfc5217SJeff Kirsher bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, 4475adfc5217SJeff Kirsher int buf_size) 4476adfc5217SJeff Kirsher { 4477adfc5217SJeff Kirsher u32 written, offset32, len32; 4478adfc5217SJeff Kirsher u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL; 4479adfc5217SJeff Kirsher int rc = 0; 4480adfc5217SJeff Kirsher int align_start, align_end; 4481adfc5217SJeff Kirsher 4482adfc5217SJeff Kirsher buf = data_buf; 4483adfc5217SJeff Kirsher offset32 = offset; 4484adfc5217SJeff Kirsher len32 = buf_size; 4485adfc5217SJeff Kirsher align_start = align_end = 0; 4486adfc5217SJeff Kirsher 4487adfc5217SJeff Kirsher if ((align_start = (offset32 & 3))) { 4488adfc5217SJeff Kirsher offset32 &= ~3; 4489adfc5217SJeff Kirsher len32 += align_start; 4490adfc5217SJeff Kirsher if (len32 < 4) 4491adfc5217SJeff Kirsher len32 = 4; 4492adfc5217SJeff Kirsher if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) 4493adfc5217SJeff Kirsher return rc; 4494adfc5217SJeff Kirsher } 4495adfc5217SJeff Kirsher 4496adfc5217SJeff Kirsher if (len32 & 3) { 4497adfc5217SJeff Kirsher align_end = 4 - (len32 & 3); 4498adfc5217SJeff Kirsher len32 += align_end; 4499adfc5217SJeff Kirsher if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4))) 4500adfc5217SJeff Kirsher return rc; 4501adfc5217SJeff Kirsher } 4502adfc5217SJeff Kirsher 4503adfc5217SJeff Kirsher if (align_start || align_end) { 4504adfc5217SJeff Kirsher align_buf = kmalloc(len32, GFP_KERNEL); 4505adfc5217SJeff Kirsher if (align_buf == NULL) 4506adfc5217SJeff Kirsher return -ENOMEM; 4507adfc5217SJeff Kirsher if (align_start) { 4508adfc5217SJeff Kirsher memcpy(align_buf, start, 4); 4509adfc5217SJeff Kirsher } 4510adfc5217SJeff Kirsher if (align_end) { 4511adfc5217SJeff Kirsher memcpy(align_buf + len32 - 4, end, 4); 4512adfc5217SJeff Kirsher } 4513adfc5217SJeff Kirsher memcpy(align_buf + align_start, data_buf, buf_size); 4514adfc5217SJeff Kirsher buf = align_buf; 4515adfc5217SJeff Kirsher } 4516adfc5217SJeff Kirsher 4517adfc5217SJeff Kirsher if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { 4518adfc5217SJeff Kirsher flash_buffer = kmalloc(264, GFP_KERNEL); 4519adfc5217SJeff Kirsher if (flash_buffer == NULL) { 4520adfc5217SJeff Kirsher rc = -ENOMEM; 4521adfc5217SJeff Kirsher goto nvram_write_end; 4522adfc5217SJeff Kirsher } 4523adfc5217SJeff Kirsher } 4524adfc5217SJeff Kirsher 4525adfc5217SJeff Kirsher written = 0; 4526adfc5217SJeff Kirsher while ((written < len32) && (rc == 0)) { 4527adfc5217SJeff Kirsher u32 page_start, page_end, data_start, data_end; 4528adfc5217SJeff Kirsher u32 addr, cmd_flags; 4529adfc5217SJeff Kirsher int i; 4530adfc5217SJeff Kirsher 4531adfc5217SJeff Kirsher /* Find the page_start addr */ 4532adfc5217SJeff Kirsher page_start = offset32 + written; 4533adfc5217SJeff Kirsher page_start -= (page_start % bp->flash_info->page_size); 4534adfc5217SJeff Kirsher /* Find the page_end addr */ 4535adfc5217SJeff Kirsher page_end = page_start + bp->flash_info->page_size; 4536adfc5217SJeff Kirsher /* Find the data_start addr */ 4537adfc5217SJeff Kirsher data_start = (written == 0) ? offset32 : page_start; 4538adfc5217SJeff Kirsher /* Find the data_end addr */ 4539adfc5217SJeff Kirsher data_end = (page_end > offset32 + len32) ? 4540adfc5217SJeff Kirsher (offset32 + len32) : page_end; 4541adfc5217SJeff Kirsher 4542adfc5217SJeff Kirsher /* Request access to the flash interface. */ 4543adfc5217SJeff Kirsher if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) 4544adfc5217SJeff Kirsher goto nvram_write_end; 4545adfc5217SJeff Kirsher 4546adfc5217SJeff Kirsher /* Enable access to flash interface */ 4547adfc5217SJeff Kirsher bnx2_enable_nvram_access(bp); 4548adfc5217SJeff Kirsher 4549adfc5217SJeff Kirsher cmd_flags = BNX2_NVM_COMMAND_FIRST; 4550adfc5217SJeff Kirsher if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { 4551adfc5217SJeff Kirsher int j; 4552adfc5217SJeff Kirsher 4553adfc5217SJeff Kirsher /* Read the whole page into the buffer 4554adfc5217SJeff Kirsher * (non-buffer flash only) */ 4555adfc5217SJeff Kirsher for (j = 0; j < bp->flash_info->page_size; j += 4) { 4556adfc5217SJeff Kirsher if (j == (bp->flash_info->page_size - 4)) { 4557adfc5217SJeff Kirsher cmd_flags |= BNX2_NVM_COMMAND_LAST; 4558adfc5217SJeff Kirsher } 4559adfc5217SJeff Kirsher rc = bnx2_nvram_read_dword(bp, 4560adfc5217SJeff Kirsher page_start + j, 4561adfc5217SJeff Kirsher &flash_buffer[j], 4562adfc5217SJeff Kirsher cmd_flags); 4563adfc5217SJeff Kirsher 4564adfc5217SJeff Kirsher if (rc) 4565adfc5217SJeff Kirsher goto nvram_write_end; 4566adfc5217SJeff Kirsher 4567adfc5217SJeff Kirsher cmd_flags = 0; 4568adfc5217SJeff Kirsher } 4569adfc5217SJeff Kirsher } 4570adfc5217SJeff Kirsher 4571adfc5217SJeff Kirsher /* Enable writes to flash interface (unlock write-protect) */ 4572adfc5217SJeff Kirsher if ((rc = bnx2_enable_nvram_write(bp)) != 0) 4573adfc5217SJeff Kirsher goto nvram_write_end; 4574adfc5217SJeff Kirsher 4575adfc5217SJeff Kirsher /* Loop to write back the buffer data from page_start to 4576adfc5217SJeff Kirsher * data_start */ 4577adfc5217SJeff Kirsher i = 0; 4578adfc5217SJeff Kirsher if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { 4579adfc5217SJeff Kirsher /* Erase the page */ 4580adfc5217SJeff Kirsher if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) 4581adfc5217SJeff Kirsher goto nvram_write_end; 4582adfc5217SJeff Kirsher 4583adfc5217SJeff Kirsher /* Re-enable the write again for the actual write */ 4584adfc5217SJeff Kirsher bnx2_enable_nvram_write(bp); 4585adfc5217SJeff Kirsher 4586adfc5217SJeff Kirsher for (addr = page_start; addr < data_start; 4587adfc5217SJeff Kirsher addr += 4, i += 4) { 4588adfc5217SJeff Kirsher 4589adfc5217SJeff Kirsher rc = bnx2_nvram_write_dword(bp, addr, 4590adfc5217SJeff Kirsher &flash_buffer[i], cmd_flags); 4591adfc5217SJeff Kirsher 4592adfc5217SJeff Kirsher if (rc != 0) 4593adfc5217SJeff Kirsher goto nvram_write_end; 4594adfc5217SJeff Kirsher 4595adfc5217SJeff Kirsher cmd_flags = 0; 4596adfc5217SJeff Kirsher } 4597adfc5217SJeff Kirsher } 4598adfc5217SJeff Kirsher 4599adfc5217SJeff Kirsher /* Loop to write the new data from data_start to data_end */ 4600adfc5217SJeff Kirsher for (addr = data_start; addr < data_end; addr += 4, i += 4) { 4601adfc5217SJeff Kirsher if ((addr == page_end - 4) || 4602adfc5217SJeff Kirsher ((bp->flash_info->flags & BNX2_NV_BUFFERED) && 4603adfc5217SJeff Kirsher (addr == data_end - 4))) { 4604adfc5217SJeff Kirsher 4605adfc5217SJeff Kirsher cmd_flags |= BNX2_NVM_COMMAND_LAST; 4606adfc5217SJeff Kirsher } 4607adfc5217SJeff Kirsher rc = bnx2_nvram_write_dword(bp, addr, buf, 4608adfc5217SJeff Kirsher cmd_flags); 4609adfc5217SJeff Kirsher 4610adfc5217SJeff Kirsher if (rc != 0) 4611adfc5217SJeff Kirsher goto nvram_write_end; 4612adfc5217SJeff Kirsher 4613adfc5217SJeff Kirsher cmd_flags = 0; 4614adfc5217SJeff Kirsher buf += 4; 4615adfc5217SJeff Kirsher } 4616adfc5217SJeff Kirsher 4617adfc5217SJeff Kirsher /* Loop to write back the buffer data from data_end 4618adfc5217SJeff Kirsher * to page_end */ 4619adfc5217SJeff Kirsher if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { 4620adfc5217SJeff Kirsher for (addr = data_end; addr < page_end; 4621adfc5217SJeff Kirsher addr += 4, i += 4) { 4622adfc5217SJeff Kirsher 4623adfc5217SJeff Kirsher if (addr == page_end-4) { 4624adfc5217SJeff Kirsher cmd_flags = BNX2_NVM_COMMAND_LAST; 4625adfc5217SJeff Kirsher } 4626adfc5217SJeff Kirsher rc = bnx2_nvram_write_dword(bp, addr, 4627adfc5217SJeff Kirsher &flash_buffer[i], cmd_flags); 4628adfc5217SJeff Kirsher 4629adfc5217SJeff Kirsher if (rc != 0) 4630adfc5217SJeff Kirsher goto nvram_write_end; 4631adfc5217SJeff Kirsher 4632adfc5217SJeff Kirsher cmd_flags = 0; 4633adfc5217SJeff Kirsher } 4634adfc5217SJeff Kirsher } 4635adfc5217SJeff Kirsher 4636adfc5217SJeff Kirsher /* Disable writes to flash interface (lock write-protect) */ 4637adfc5217SJeff Kirsher bnx2_disable_nvram_write(bp); 4638adfc5217SJeff Kirsher 4639adfc5217SJeff Kirsher /* Disable access to flash interface */ 4640adfc5217SJeff Kirsher bnx2_disable_nvram_access(bp); 4641adfc5217SJeff Kirsher bnx2_release_nvram_lock(bp); 4642adfc5217SJeff Kirsher 4643adfc5217SJeff Kirsher /* Increment written */ 4644adfc5217SJeff Kirsher written += data_end - data_start; 4645adfc5217SJeff Kirsher } 4646adfc5217SJeff Kirsher 4647adfc5217SJeff Kirsher nvram_write_end: 4648adfc5217SJeff Kirsher kfree(flash_buffer); 4649adfc5217SJeff Kirsher kfree(align_buf); 4650adfc5217SJeff Kirsher return rc; 4651adfc5217SJeff Kirsher } 4652adfc5217SJeff Kirsher 4653adfc5217SJeff Kirsher static void 4654adfc5217SJeff Kirsher bnx2_init_fw_cap(struct bnx2 *bp) 4655adfc5217SJeff Kirsher { 4656adfc5217SJeff Kirsher u32 val, sig = 0; 4657adfc5217SJeff Kirsher 4658adfc5217SJeff Kirsher bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP; 4659adfc5217SJeff Kirsher bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN; 4660adfc5217SJeff Kirsher 4661adfc5217SJeff Kirsher if (!(bp->flags & BNX2_FLAG_ASF_ENABLE)) 4662adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; 4663adfc5217SJeff Kirsher 4664adfc5217SJeff Kirsher val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB); 4665adfc5217SJeff Kirsher if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE) 4666adfc5217SJeff Kirsher return; 4667adfc5217SJeff Kirsher 4668adfc5217SJeff Kirsher if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) { 4669adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; 4670adfc5217SJeff Kirsher sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN; 4671adfc5217SJeff Kirsher } 4672adfc5217SJeff Kirsher 4673adfc5217SJeff Kirsher if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 4674adfc5217SJeff Kirsher (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) { 4675adfc5217SJeff Kirsher u32 link; 4676adfc5217SJeff Kirsher 4677adfc5217SJeff Kirsher bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; 4678adfc5217SJeff Kirsher 4679adfc5217SJeff Kirsher link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); 4680adfc5217SJeff Kirsher if (link & BNX2_LINK_STATUS_SERDES_LINK) 4681adfc5217SJeff Kirsher bp->phy_port = PORT_FIBRE; 4682adfc5217SJeff Kirsher else 4683adfc5217SJeff Kirsher bp->phy_port = PORT_TP; 4684adfc5217SJeff Kirsher 4685adfc5217SJeff Kirsher sig |= BNX2_DRV_ACK_CAP_SIGNATURE | 4686adfc5217SJeff Kirsher BNX2_FW_CAP_REMOTE_PHY_CAPABLE; 4687adfc5217SJeff Kirsher } 4688adfc5217SJeff Kirsher 4689adfc5217SJeff Kirsher if (netif_running(bp->dev) && sig) 4690adfc5217SJeff Kirsher bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig); 4691adfc5217SJeff Kirsher } 4692adfc5217SJeff Kirsher 4693adfc5217SJeff Kirsher static void 4694adfc5217SJeff Kirsher bnx2_setup_msix_tbl(struct bnx2 *bp) 4695adfc5217SJeff Kirsher { 4696adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN); 4697adfc5217SJeff Kirsher 4698adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR); 4699adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR); 4700adfc5217SJeff Kirsher } 4701adfc5217SJeff Kirsher 4702adfc5217SJeff Kirsher static int 4703adfc5217SJeff Kirsher bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) 4704adfc5217SJeff Kirsher { 4705adfc5217SJeff Kirsher u32 val; 4706adfc5217SJeff Kirsher int i, rc = 0; 4707adfc5217SJeff Kirsher u8 old_port; 4708adfc5217SJeff Kirsher 4709adfc5217SJeff Kirsher /* Wait for the current PCI transaction to complete before 4710adfc5217SJeff Kirsher * issuing a reset. */ 4711adfc5217SJeff Kirsher if ((CHIP_NUM(bp) == CHIP_NUM_5706) || 4712adfc5217SJeff Kirsher (CHIP_NUM(bp) == CHIP_NUM_5708)) { 4713adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, 4714adfc5217SJeff Kirsher BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4715adfc5217SJeff Kirsher BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4716adfc5217SJeff Kirsher BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4717adfc5217SJeff Kirsher BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4718adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); 4719adfc5217SJeff Kirsher udelay(5); 4720adfc5217SJeff Kirsher } else { /* 5709 */ 4721adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL); 4722adfc5217SJeff Kirsher val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; 4723adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); 4724adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL); 4725adfc5217SJeff Kirsher 4726adfc5217SJeff Kirsher for (i = 0; i < 100; i++) { 4727adfc5217SJeff Kirsher msleep(1); 4728adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_PCICFG_DEVICE_CONTROL); 4729adfc5217SJeff Kirsher if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND)) 4730adfc5217SJeff Kirsher break; 4731adfc5217SJeff Kirsher } 4732adfc5217SJeff Kirsher } 4733adfc5217SJeff Kirsher 4734adfc5217SJeff Kirsher /* Wait for the firmware to tell us it is ok to issue a reset. */ 4735adfc5217SJeff Kirsher bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1); 4736adfc5217SJeff Kirsher 4737adfc5217SJeff Kirsher /* Deposit a driver reset signature so the firmware knows that 4738adfc5217SJeff Kirsher * this is a soft reset. */ 4739adfc5217SJeff Kirsher bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE, 4740adfc5217SJeff Kirsher BNX2_DRV_RESET_SIGNATURE_MAGIC); 4741adfc5217SJeff Kirsher 4742adfc5217SJeff Kirsher /* Do a dummy read to force the chip to complete all current transaction 4743adfc5217SJeff Kirsher * before we issue a reset. */ 4744adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_MISC_ID); 4745adfc5217SJeff Kirsher 4746adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 4747adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); 4748adfc5217SJeff Kirsher REG_RD(bp, BNX2_MISC_COMMAND); 4749adfc5217SJeff Kirsher udelay(5); 4750adfc5217SJeff Kirsher 4751adfc5217SJeff Kirsher val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4752adfc5217SJeff Kirsher BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4753adfc5217SJeff Kirsher 4754adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); 4755adfc5217SJeff Kirsher 4756adfc5217SJeff Kirsher } else { 4757adfc5217SJeff Kirsher val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4758adfc5217SJeff Kirsher BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4759adfc5217SJeff Kirsher BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4760adfc5217SJeff Kirsher 4761adfc5217SJeff Kirsher /* Chip reset. */ 4762adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); 4763adfc5217SJeff Kirsher 4764adfc5217SJeff Kirsher /* Reading back any register after chip reset will hang the 4765adfc5217SJeff Kirsher * bus on 5706 A0 and A1. The msleep below provides plenty 4766adfc5217SJeff Kirsher * of margin for write posting. 4767adfc5217SJeff Kirsher */ 4768adfc5217SJeff Kirsher if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || 4769adfc5217SJeff Kirsher (CHIP_ID(bp) == CHIP_ID_5706_A1)) 4770adfc5217SJeff Kirsher msleep(20); 4771adfc5217SJeff Kirsher 4772adfc5217SJeff Kirsher /* Reset takes approximate 30 usec */ 4773adfc5217SJeff Kirsher for (i = 0; i < 10; i++) { 4774adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); 4775adfc5217SJeff Kirsher if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4776adfc5217SJeff Kirsher BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) 4777adfc5217SJeff Kirsher break; 4778adfc5217SJeff Kirsher udelay(10); 4779adfc5217SJeff Kirsher } 4780adfc5217SJeff Kirsher 4781adfc5217SJeff Kirsher if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4782adfc5217SJeff Kirsher BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4783adfc5217SJeff Kirsher pr_err("Chip reset did not complete\n"); 4784adfc5217SJeff Kirsher return -EBUSY; 4785adfc5217SJeff Kirsher } 4786adfc5217SJeff Kirsher } 4787adfc5217SJeff Kirsher 4788adfc5217SJeff Kirsher /* Make sure byte swapping is properly configured. */ 4789adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0); 4790adfc5217SJeff Kirsher if (val != 0x01020304) { 4791adfc5217SJeff Kirsher pr_err("Chip not in correct endian mode\n"); 4792adfc5217SJeff Kirsher return -ENODEV; 4793adfc5217SJeff Kirsher } 4794adfc5217SJeff Kirsher 4795adfc5217SJeff Kirsher /* Wait for the firmware to finish its initialization. */ 4796adfc5217SJeff Kirsher rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0); 4797adfc5217SJeff Kirsher if (rc) 4798adfc5217SJeff Kirsher return rc; 4799adfc5217SJeff Kirsher 4800adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 4801adfc5217SJeff Kirsher old_port = bp->phy_port; 4802adfc5217SJeff Kirsher bnx2_init_fw_cap(bp); 4803adfc5217SJeff Kirsher if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) && 4804adfc5217SJeff Kirsher old_port != bp->phy_port) 4805adfc5217SJeff Kirsher bnx2_set_default_remote_link(bp); 4806adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 4807adfc5217SJeff Kirsher 4808adfc5217SJeff Kirsher if (CHIP_ID(bp) == CHIP_ID_5706_A0) { 4809adfc5217SJeff Kirsher /* Adjust the voltage regular to two steps lower. The default 4810adfc5217SJeff Kirsher * of this register is 0x0000000e. */ 4811adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); 4812adfc5217SJeff Kirsher 4813adfc5217SJeff Kirsher /* Remove bad rbuf memory from the free pool. */ 4814adfc5217SJeff Kirsher rc = bnx2_alloc_bad_rbuf(bp); 4815adfc5217SJeff Kirsher } 4816adfc5217SJeff Kirsher 4817adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_USING_MSIX) { 4818adfc5217SJeff Kirsher bnx2_setup_msix_tbl(bp); 4819adfc5217SJeff Kirsher /* Prevent MSIX table reads and write from timing out */ 4820adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_ECO_HW_CTL, 4821adfc5217SJeff Kirsher BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN); 4822adfc5217SJeff Kirsher } 4823adfc5217SJeff Kirsher 4824adfc5217SJeff Kirsher return rc; 4825adfc5217SJeff Kirsher } 4826adfc5217SJeff Kirsher 4827adfc5217SJeff Kirsher static int 4828adfc5217SJeff Kirsher bnx2_init_chip(struct bnx2 *bp) 4829adfc5217SJeff Kirsher { 4830adfc5217SJeff Kirsher u32 val, mtu; 4831adfc5217SJeff Kirsher int rc, i; 4832adfc5217SJeff Kirsher 4833adfc5217SJeff Kirsher /* Make sure the interrupt is not active. */ 4834adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 4835adfc5217SJeff Kirsher 4836adfc5217SJeff Kirsher val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | 4837adfc5217SJeff Kirsher BNX2_DMA_CONFIG_DATA_WORD_SWAP | 4838adfc5217SJeff Kirsher #ifdef __BIG_ENDIAN 4839adfc5217SJeff Kirsher BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | 4840adfc5217SJeff Kirsher #endif 4841adfc5217SJeff Kirsher BNX2_DMA_CONFIG_CNTL_WORD_SWAP | 4842adfc5217SJeff Kirsher DMA_READ_CHANS << 12 | 4843adfc5217SJeff Kirsher DMA_WRITE_CHANS << 16; 4844adfc5217SJeff Kirsher 4845adfc5217SJeff Kirsher val |= (0x2 << 20) | (1 << 11); 4846adfc5217SJeff Kirsher 4847adfc5217SJeff Kirsher if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133)) 4848adfc5217SJeff Kirsher val |= (1 << 23); 4849adfc5217SJeff Kirsher 4850adfc5217SJeff Kirsher if ((CHIP_NUM(bp) == CHIP_NUM_5706) && 4851adfc5217SJeff Kirsher (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX)) 4852adfc5217SJeff Kirsher val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; 4853adfc5217SJeff Kirsher 4854adfc5217SJeff Kirsher REG_WR(bp, BNX2_DMA_CONFIG, val); 4855adfc5217SJeff Kirsher 4856adfc5217SJeff Kirsher if (CHIP_ID(bp) == CHIP_ID_5706_A0) { 4857adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_TDMA_CONFIG); 4858adfc5217SJeff Kirsher val |= BNX2_TDMA_CONFIG_ONE_DMA; 4859adfc5217SJeff Kirsher REG_WR(bp, BNX2_TDMA_CONFIG, val); 4860adfc5217SJeff Kirsher } 4861adfc5217SJeff Kirsher 4862adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_PCIX) { 4863adfc5217SJeff Kirsher u16 val16; 4864adfc5217SJeff Kirsher 4865adfc5217SJeff Kirsher pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, 4866adfc5217SJeff Kirsher &val16); 4867adfc5217SJeff Kirsher pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, 4868adfc5217SJeff Kirsher val16 & ~PCI_X_CMD_ERO); 4869adfc5217SJeff Kirsher } 4870adfc5217SJeff Kirsher 4871adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 4872adfc5217SJeff Kirsher BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 4873adfc5217SJeff Kirsher BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 4874adfc5217SJeff Kirsher BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 4875adfc5217SJeff Kirsher 4876adfc5217SJeff Kirsher /* Initialize context mapping and zero out the quick contexts. The 4877adfc5217SJeff Kirsher * context block must have already been enabled. */ 4878adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 4879adfc5217SJeff Kirsher rc = bnx2_init_5709_context(bp); 4880adfc5217SJeff Kirsher if (rc) 4881adfc5217SJeff Kirsher return rc; 4882adfc5217SJeff Kirsher } else 4883adfc5217SJeff Kirsher bnx2_init_context(bp); 4884adfc5217SJeff Kirsher 4885adfc5217SJeff Kirsher if ((rc = bnx2_init_cpus(bp)) != 0) 4886adfc5217SJeff Kirsher return rc; 4887adfc5217SJeff Kirsher 4888adfc5217SJeff Kirsher bnx2_init_nvram(bp); 4889adfc5217SJeff Kirsher 4890adfc5217SJeff Kirsher bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); 4891adfc5217SJeff Kirsher 4892adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_MQ_CONFIG); 4893adfc5217SJeff Kirsher val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; 4894adfc5217SJeff Kirsher val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 4895adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 4896adfc5217SJeff Kirsher val |= BNX2_MQ_CONFIG_BIN_MQ_MODE; 4897adfc5217SJeff Kirsher if (CHIP_REV(bp) == CHIP_REV_Ax) 4898adfc5217SJeff Kirsher val |= BNX2_MQ_CONFIG_HALT_DIS; 4899adfc5217SJeff Kirsher } 4900adfc5217SJeff Kirsher 4901adfc5217SJeff Kirsher REG_WR(bp, BNX2_MQ_CONFIG, val); 4902adfc5217SJeff Kirsher 4903adfc5217SJeff Kirsher val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 4904adfc5217SJeff Kirsher REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); 4905adfc5217SJeff Kirsher REG_WR(bp, BNX2_MQ_KNL_WIND_END, val); 4906adfc5217SJeff Kirsher 4907adfc5217SJeff Kirsher val = (BCM_PAGE_BITS - 8) << 24; 4908adfc5217SJeff Kirsher REG_WR(bp, BNX2_RV2P_CONFIG, val); 4909adfc5217SJeff Kirsher 4910adfc5217SJeff Kirsher /* Configure page size. */ 4911adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_TBDR_CONFIG); 4912adfc5217SJeff Kirsher val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; 4913adfc5217SJeff Kirsher val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 4914adfc5217SJeff Kirsher REG_WR(bp, BNX2_TBDR_CONFIG, val); 4915adfc5217SJeff Kirsher 4916adfc5217SJeff Kirsher val = bp->mac_addr[0] + 4917adfc5217SJeff Kirsher (bp->mac_addr[1] << 8) + 4918adfc5217SJeff Kirsher (bp->mac_addr[2] << 16) + 4919adfc5217SJeff Kirsher bp->mac_addr[3] + 4920adfc5217SJeff Kirsher (bp->mac_addr[4] << 8) + 4921adfc5217SJeff Kirsher (bp->mac_addr[5] << 16); 4922adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); 4923adfc5217SJeff Kirsher 4924adfc5217SJeff Kirsher /* Program the MTU. Also include 4 bytes for CRC32. */ 4925adfc5217SJeff Kirsher mtu = bp->dev->mtu; 4926adfc5217SJeff Kirsher val = mtu + ETH_HLEN + ETH_FCS_LEN; 4927adfc5217SJeff Kirsher if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) 4928adfc5217SJeff Kirsher val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; 4929adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); 4930adfc5217SJeff Kirsher 4931adfc5217SJeff Kirsher if (mtu < 1500) 4932adfc5217SJeff Kirsher mtu = 1500; 4933adfc5217SJeff Kirsher 4934adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu)); 4935adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu)); 4936adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu)); 4937adfc5217SJeff Kirsher 4938adfc5217SJeff Kirsher memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size); 4939adfc5217SJeff Kirsher for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) 4940adfc5217SJeff Kirsher bp->bnx2_napi[i].last_status_idx = 0; 4941adfc5217SJeff Kirsher 4942adfc5217SJeff Kirsher bp->idle_chk_status_idx = 0xffff; 4943adfc5217SJeff Kirsher 4944adfc5217SJeff Kirsher bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE; 4945adfc5217SJeff Kirsher 4946adfc5217SJeff Kirsher /* Set up how to generate a link change interrupt. */ 4947adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); 4948adfc5217SJeff Kirsher 4949adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_STATUS_ADDR_L, 4950adfc5217SJeff Kirsher (u64) bp->status_blk_mapping & 0xffffffff); 4951adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); 4952adfc5217SJeff Kirsher 4953adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L, 4954adfc5217SJeff Kirsher (u64) bp->stats_blk_mapping & 0xffffffff); 4955adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H, 4956adfc5217SJeff Kirsher (u64) bp->stats_blk_mapping >> 32); 4957adfc5217SJeff Kirsher 4958adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, 4959adfc5217SJeff Kirsher (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); 4960adfc5217SJeff Kirsher 4961adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, 4962adfc5217SJeff Kirsher (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); 4963adfc5217SJeff Kirsher 4964adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_COMP_PROD_TRIP, 4965adfc5217SJeff Kirsher (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); 4966adfc5217SJeff Kirsher 4967adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); 4968adfc5217SJeff Kirsher 4969adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); 4970adfc5217SJeff Kirsher 4971adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_COM_TICKS, 4972adfc5217SJeff Kirsher (bp->com_ticks_int << 16) | bp->com_ticks); 4973adfc5217SJeff Kirsher 4974adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_CMD_TICKS, 4975adfc5217SJeff Kirsher (bp->cmd_ticks_int << 16) | bp->cmd_ticks); 4976adfc5217SJeff Kirsher 4977adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_BROKEN_STATS) 4978adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_STATS_TICKS, 0); 4979adfc5217SJeff Kirsher else 4980adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); 4981adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 4982adfc5217SJeff Kirsher 4983adfc5217SJeff Kirsher if (CHIP_ID(bp) == CHIP_ID_5706_A1) 4984adfc5217SJeff Kirsher val = BNX2_HC_CONFIG_COLLECT_STATS; 4985adfc5217SJeff Kirsher else { 4986adfc5217SJeff Kirsher val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE | 4987adfc5217SJeff Kirsher BNX2_HC_CONFIG_COLLECT_STATS; 4988adfc5217SJeff Kirsher } 4989adfc5217SJeff Kirsher 4990adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_USING_MSIX) { 4991adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, 4992adfc5217SJeff Kirsher BNX2_HC_MSIX_BIT_VECTOR_VAL); 4993adfc5217SJeff Kirsher 4994adfc5217SJeff Kirsher val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; 4995adfc5217SJeff Kirsher } 4996adfc5217SJeff Kirsher 4997adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) 4998adfc5217SJeff Kirsher val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM; 4999adfc5217SJeff Kirsher 5000adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_CONFIG, val); 5001adfc5217SJeff Kirsher 5002adfc5217SJeff Kirsher if (bp->rx_ticks < 25) 5003adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1); 5004adfc5217SJeff Kirsher else 5005adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0); 5006adfc5217SJeff Kirsher 5007adfc5217SJeff Kirsher for (i = 1; i < bp->irq_nvecs; i++) { 5008adfc5217SJeff Kirsher u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) + 5009adfc5217SJeff Kirsher BNX2_HC_SB_CONFIG_1; 5010adfc5217SJeff Kirsher 5011adfc5217SJeff Kirsher REG_WR(bp, base, 5012adfc5217SJeff Kirsher BNX2_HC_SB_CONFIG_1_TX_TMR_MODE | 5013adfc5217SJeff Kirsher BNX2_HC_SB_CONFIG_1_RX_TMR_MODE | 5014adfc5217SJeff Kirsher BNX2_HC_SB_CONFIG_1_ONE_SHOT); 5015adfc5217SJeff Kirsher 5016adfc5217SJeff Kirsher REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF, 5017adfc5217SJeff Kirsher (bp->tx_quick_cons_trip_int << 16) | 5018adfc5217SJeff Kirsher bp->tx_quick_cons_trip); 5019adfc5217SJeff Kirsher 5020adfc5217SJeff Kirsher REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF, 5021adfc5217SJeff Kirsher (bp->tx_ticks_int << 16) | bp->tx_ticks); 5022adfc5217SJeff Kirsher 5023adfc5217SJeff Kirsher REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF, 5024adfc5217SJeff Kirsher (bp->rx_quick_cons_trip_int << 16) | 5025adfc5217SJeff Kirsher bp->rx_quick_cons_trip); 5026adfc5217SJeff Kirsher 5027adfc5217SJeff Kirsher REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF, 5028adfc5217SJeff Kirsher (bp->rx_ticks_int << 16) | bp->rx_ticks); 5029adfc5217SJeff Kirsher } 5030adfc5217SJeff Kirsher 5031adfc5217SJeff Kirsher /* Clear internal stats counters. */ 5032adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); 5033adfc5217SJeff Kirsher 5034adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS); 5035adfc5217SJeff Kirsher 5036adfc5217SJeff Kirsher /* Initialize the receive filter. */ 5037adfc5217SJeff Kirsher bnx2_set_rx_mode(bp->dev); 5038adfc5217SJeff Kirsher 5039adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 5040adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL); 5041adfc5217SJeff Kirsher val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; 5042adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); 5043adfc5217SJeff Kirsher } 5044adfc5217SJeff Kirsher rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, 5045adfc5217SJeff Kirsher 1, 0); 5046adfc5217SJeff Kirsher 5047adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT); 5048adfc5217SJeff Kirsher REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS); 5049adfc5217SJeff Kirsher 5050adfc5217SJeff Kirsher udelay(20); 5051adfc5217SJeff Kirsher 5052adfc5217SJeff Kirsher bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND); 5053adfc5217SJeff Kirsher 5054adfc5217SJeff Kirsher return rc; 5055adfc5217SJeff Kirsher } 5056adfc5217SJeff Kirsher 5057adfc5217SJeff Kirsher static void 5058adfc5217SJeff Kirsher bnx2_clear_ring_states(struct bnx2 *bp) 5059adfc5217SJeff Kirsher { 5060adfc5217SJeff Kirsher struct bnx2_napi *bnapi; 5061adfc5217SJeff Kirsher struct bnx2_tx_ring_info *txr; 5062adfc5217SJeff Kirsher struct bnx2_rx_ring_info *rxr; 5063adfc5217SJeff Kirsher int i; 5064adfc5217SJeff Kirsher 5065adfc5217SJeff Kirsher for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { 5066adfc5217SJeff Kirsher bnapi = &bp->bnx2_napi[i]; 5067adfc5217SJeff Kirsher txr = &bnapi->tx_ring; 5068adfc5217SJeff Kirsher rxr = &bnapi->rx_ring; 5069adfc5217SJeff Kirsher 5070adfc5217SJeff Kirsher txr->tx_cons = 0; 5071adfc5217SJeff Kirsher txr->hw_tx_cons = 0; 5072adfc5217SJeff Kirsher rxr->rx_prod_bseq = 0; 5073adfc5217SJeff Kirsher rxr->rx_prod = 0; 5074adfc5217SJeff Kirsher rxr->rx_cons = 0; 5075adfc5217SJeff Kirsher rxr->rx_pg_prod = 0; 5076adfc5217SJeff Kirsher rxr->rx_pg_cons = 0; 5077adfc5217SJeff Kirsher } 5078adfc5217SJeff Kirsher } 5079adfc5217SJeff Kirsher 5080adfc5217SJeff Kirsher static void 5081adfc5217SJeff Kirsher bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr) 5082adfc5217SJeff Kirsher { 5083adfc5217SJeff Kirsher u32 val, offset0, offset1, offset2, offset3; 5084adfc5217SJeff Kirsher u32 cid_addr = GET_CID_ADDR(cid); 5085adfc5217SJeff Kirsher 5086adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 5087adfc5217SJeff Kirsher offset0 = BNX2_L2CTX_TYPE_XI; 5088adfc5217SJeff Kirsher offset1 = BNX2_L2CTX_CMD_TYPE_XI; 5089adfc5217SJeff Kirsher offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI; 5090adfc5217SJeff Kirsher offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI; 5091adfc5217SJeff Kirsher } else { 5092adfc5217SJeff Kirsher offset0 = BNX2_L2CTX_TYPE; 5093adfc5217SJeff Kirsher offset1 = BNX2_L2CTX_CMD_TYPE; 5094adfc5217SJeff Kirsher offset2 = BNX2_L2CTX_TBDR_BHADDR_HI; 5095adfc5217SJeff Kirsher offset3 = BNX2_L2CTX_TBDR_BHADDR_LO; 5096adfc5217SJeff Kirsher } 5097adfc5217SJeff Kirsher val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; 5098adfc5217SJeff Kirsher bnx2_ctx_wr(bp, cid_addr, offset0, val); 5099adfc5217SJeff Kirsher 5100adfc5217SJeff Kirsher val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 5101adfc5217SJeff Kirsher bnx2_ctx_wr(bp, cid_addr, offset1, val); 5102adfc5217SJeff Kirsher 5103adfc5217SJeff Kirsher val = (u64) txr->tx_desc_mapping >> 32; 5104adfc5217SJeff Kirsher bnx2_ctx_wr(bp, cid_addr, offset2, val); 5105adfc5217SJeff Kirsher 5106adfc5217SJeff Kirsher val = (u64) txr->tx_desc_mapping & 0xffffffff; 5107adfc5217SJeff Kirsher bnx2_ctx_wr(bp, cid_addr, offset3, val); 5108adfc5217SJeff Kirsher } 5109adfc5217SJeff Kirsher 5110adfc5217SJeff Kirsher static void 5111adfc5217SJeff Kirsher bnx2_init_tx_ring(struct bnx2 *bp, int ring_num) 5112adfc5217SJeff Kirsher { 5113adfc5217SJeff Kirsher struct tx_bd *txbd; 5114adfc5217SJeff Kirsher u32 cid = TX_CID; 5115adfc5217SJeff Kirsher struct bnx2_napi *bnapi; 5116adfc5217SJeff Kirsher struct bnx2_tx_ring_info *txr; 5117adfc5217SJeff Kirsher 5118adfc5217SJeff Kirsher bnapi = &bp->bnx2_napi[ring_num]; 5119adfc5217SJeff Kirsher txr = &bnapi->tx_ring; 5120adfc5217SJeff Kirsher 5121adfc5217SJeff Kirsher if (ring_num == 0) 5122adfc5217SJeff Kirsher cid = TX_CID; 5123adfc5217SJeff Kirsher else 5124adfc5217SJeff Kirsher cid = TX_TSS_CID + ring_num - 1; 5125adfc5217SJeff Kirsher 5126adfc5217SJeff Kirsher bp->tx_wake_thresh = bp->tx_ring_size / 2; 5127adfc5217SJeff Kirsher 5128adfc5217SJeff Kirsher txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT]; 5129adfc5217SJeff Kirsher 5130adfc5217SJeff Kirsher txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32; 5131adfc5217SJeff Kirsher txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff; 5132adfc5217SJeff Kirsher 5133adfc5217SJeff Kirsher txr->tx_prod = 0; 5134adfc5217SJeff Kirsher txr->tx_prod_bseq = 0; 5135adfc5217SJeff Kirsher 5136adfc5217SJeff Kirsher txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; 5137adfc5217SJeff Kirsher txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; 5138adfc5217SJeff Kirsher 5139adfc5217SJeff Kirsher bnx2_init_tx_context(bp, cid, txr); 5140adfc5217SJeff Kirsher } 5141adfc5217SJeff Kirsher 5142adfc5217SJeff Kirsher static void 5143adfc5217SJeff Kirsher bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size, 5144adfc5217SJeff Kirsher int num_rings) 5145adfc5217SJeff Kirsher { 5146adfc5217SJeff Kirsher int i; 5147adfc5217SJeff Kirsher struct rx_bd *rxbd; 5148adfc5217SJeff Kirsher 5149adfc5217SJeff Kirsher for (i = 0; i < num_rings; i++) { 5150adfc5217SJeff Kirsher int j; 5151adfc5217SJeff Kirsher 5152adfc5217SJeff Kirsher rxbd = &rx_ring[i][0]; 5153adfc5217SJeff Kirsher for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) { 5154adfc5217SJeff Kirsher rxbd->rx_bd_len = buf_size; 5155adfc5217SJeff Kirsher rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; 5156adfc5217SJeff Kirsher } 5157adfc5217SJeff Kirsher if (i == (num_rings - 1)) 5158adfc5217SJeff Kirsher j = 0; 5159adfc5217SJeff Kirsher else 5160adfc5217SJeff Kirsher j = i + 1; 5161adfc5217SJeff Kirsher rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32; 5162adfc5217SJeff Kirsher rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff; 5163adfc5217SJeff Kirsher } 5164adfc5217SJeff Kirsher } 5165adfc5217SJeff Kirsher 5166adfc5217SJeff Kirsher static void 5167adfc5217SJeff Kirsher bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) 5168adfc5217SJeff Kirsher { 5169adfc5217SJeff Kirsher int i; 5170adfc5217SJeff Kirsher u16 prod, ring_prod; 5171adfc5217SJeff Kirsher u32 cid, rx_cid_addr, val; 5172adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num]; 5173adfc5217SJeff Kirsher struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 5174adfc5217SJeff Kirsher 5175adfc5217SJeff Kirsher if (ring_num == 0) 5176adfc5217SJeff Kirsher cid = RX_CID; 5177adfc5217SJeff Kirsher else 5178adfc5217SJeff Kirsher cid = RX_RSS_CID + ring_num - 1; 5179adfc5217SJeff Kirsher 5180adfc5217SJeff Kirsher rx_cid_addr = GET_CID_ADDR(cid); 5181adfc5217SJeff Kirsher 5182adfc5217SJeff Kirsher bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping, 5183adfc5217SJeff Kirsher bp->rx_buf_use_size, bp->rx_max_ring); 5184adfc5217SJeff Kirsher 5185adfc5217SJeff Kirsher bnx2_init_rx_context(bp, cid); 5186adfc5217SJeff Kirsher 5187adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 5188adfc5217SJeff Kirsher val = REG_RD(bp, BNX2_MQ_MAP_L2_5); 5189adfc5217SJeff Kirsher REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM); 5190adfc5217SJeff Kirsher } 5191adfc5217SJeff Kirsher 5192adfc5217SJeff Kirsher bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); 5193adfc5217SJeff Kirsher if (bp->rx_pg_ring_size) { 5194adfc5217SJeff Kirsher bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring, 5195adfc5217SJeff Kirsher rxr->rx_pg_desc_mapping, 5196adfc5217SJeff Kirsher PAGE_SIZE, bp->rx_max_pg_ring); 5197adfc5217SJeff Kirsher val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; 5198adfc5217SJeff Kirsher bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); 5199adfc5217SJeff Kirsher bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, 5200adfc5217SJeff Kirsher BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num); 5201adfc5217SJeff Kirsher 5202adfc5217SJeff Kirsher val = (u64) rxr->rx_pg_desc_mapping[0] >> 32; 5203adfc5217SJeff Kirsher bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); 5204adfc5217SJeff Kirsher 5205adfc5217SJeff Kirsher val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; 5206adfc5217SJeff Kirsher bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); 5207adfc5217SJeff Kirsher 5208adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) 5209adfc5217SJeff Kirsher REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); 5210adfc5217SJeff Kirsher } 5211adfc5217SJeff Kirsher 5212adfc5217SJeff Kirsher val = (u64) rxr->rx_desc_mapping[0] >> 32; 5213adfc5217SJeff Kirsher bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); 5214adfc5217SJeff Kirsher 5215adfc5217SJeff Kirsher val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff; 5216adfc5217SJeff Kirsher bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); 5217adfc5217SJeff Kirsher 5218adfc5217SJeff Kirsher ring_prod = prod = rxr->rx_pg_prod; 5219adfc5217SJeff Kirsher for (i = 0; i < bp->rx_pg_ring_size; i++) { 5220adfc5217SJeff Kirsher if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) { 5221adfc5217SJeff Kirsher netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n", 5222adfc5217SJeff Kirsher ring_num, i, bp->rx_pg_ring_size); 5223adfc5217SJeff Kirsher break; 5224adfc5217SJeff Kirsher } 5225adfc5217SJeff Kirsher prod = NEXT_RX_BD(prod); 5226adfc5217SJeff Kirsher ring_prod = RX_PG_RING_IDX(prod); 5227adfc5217SJeff Kirsher } 5228adfc5217SJeff Kirsher rxr->rx_pg_prod = prod; 5229adfc5217SJeff Kirsher 5230adfc5217SJeff Kirsher ring_prod = prod = rxr->rx_prod; 5231adfc5217SJeff Kirsher for (i = 0; i < bp->rx_ring_size; i++) { 5232dd2bc8e9SEric Dumazet if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) { 5233adfc5217SJeff Kirsher netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n", 5234adfc5217SJeff Kirsher ring_num, i, bp->rx_ring_size); 5235adfc5217SJeff Kirsher break; 5236adfc5217SJeff Kirsher } 5237adfc5217SJeff Kirsher prod = NEXT_RX_BD(prod); 5238adfc5217SJeff Kirsher ring_prod = RX_RING_IDX(prod); 5239adfc5217SJeff Kirsher } 5240adfc5217SJeff Kirsher rxr->rx_prod = prod; 5241adfc5217SJeff Kirsher 5242adfc5217SJeff Kirsher rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX; 5243adfc5217SJeff Kirsher rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ; 5244adfc5217SJeff Kirsher rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX; 5245adfc5217SJeff Kirsher 5246adfc5217SJeff Kirsher REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); 5247adfc5217SJeff Kirsher REG_WR16(bp, rxr->rx_bidx_addr, prod); 5248adfc5217SJeff Kirsher 5249adfc5217SJeff Kirsher REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); 5250adfc5217SJeff Kirsher } 5251adfc5217SJeff Kirsher 5252adfc5217SJeff Kirsher static void 5253adfc5217SJeff Kirsher bnx2_init_all_rings(struct bnx2 *bp) 5254adfc5217SJeff Kirsher { 5255adfc5217SJeff Kirsher int i; 5256adfc5217SJeff Kirsher u32 val; 5257adfc5217SJeff Kirsher 5258adfc5217SJeff Kirsher bnx2_clear_ring_states(bp); 5259adfc5217SJeff Kirsher 5260adfc5217SJeff Kirsher REG_WR(bp, BNX2_TSCH_TSS_CFG, 0); 5261adfc5217SJeff Kirsher for (i = 0; i < bp->num_tx_rings; i++) 5262adfc5217SJeff Kirsher bnx2_init_tx_ring(bp, i); 5263adfc5217SJeff Kirsher 5264adfc5217SJeff Kirsher if (bp->num_tx_rings > 1) 5265adfc5217SJeff Kirsher REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) | 5266adfc5217SJeff Kirsher (TX_TSS_CID << 7)); 5267adfc5217SJeff Kirsher 5268adfc5217SJeff Kirsher REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0); 5269adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0); 5270adfc5217SJeff Kirsher 5271adfc5217SJeff Kirsher for (i = 0; i < bp->num_rx_rings; i++) 5272adfc5217SJeff Kirsher bnx2_init_rx_ring(bp, i); 5273adfc5217SJeff Kirsher 5274adfc5217SJeff Kirsher if (bp->num_rx_rings > 1) { 5275adfc5217SJeff Kirsher u32 tbl_32 = 0; 5276adfc5217SJeff Kirsher 5277adfc5217SJeff Kirsher for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) { 5278adfc5217SJeff Kirsher int shift = (i % 8) << 2; 5279adfc5217SJeff Kirsher 5280adfc5217SJeff Kirsher tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift; 5281adfc5217SJeff Kirsher if ((i % 8) == 7) { 5282adfc5217SJeff Kirsher REG_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32); 5283adfc5217SJeff Kirsher REG_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) | 5284adfc5217SJeff Kirsher BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK | 5285adfc5217SJeff Kirsher BNX2_RLUP_RSS_COMMAND_WRITE | 5286adfc5217SJeff Kirsher BNX2_RLUP_RSS_COMMAND_HASH_MASK); 5287adfc5217SJeff Kirsher tbl_32 = 0; 5288adfc5217SJeff Kirsher } 5289adfc5217SJeff Kirsher } 5290adfc5217SJeff Kirsher 5291adfc5217SJeff Kirsher val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI | 5292adfc5217SJeff Kirsher BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI; 5293adfc5217SJeff Kirsher 5294adfc5217SJeff Kirsher REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val); 5295adfc5217SJeff Kirsher 5296adfc5217SJeff Kirsher } 5297adfc5217SJeff Kirsher } 5298adfc5217SJeff Kirsher 5299adfc5217SJeff Kirsher static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size) 5300adfc5217SJeff Kirsher { 5301adfc5217SJeff Kirsher u32 max, num_rings = 1; 5302adfc5217SJeff Kirsher 5303adfc5217SJeff Kirsher while (ring_size > MAX_RX_DESC_CNT) { 5304adfc5217SJeff Kirsher ring_size -= MAX_RX_DESC_CNT; 5305adfc5217SJeff Kirsher num_rings++; 5306adfc5217SJeff Kirsher } 5307adfc5217SJeff Kirsher /* round to next power of 2 */ 5308adfc5217SJeff Kirsher max = max_size; 5309adfc5217SJeff Kirsher while ((max & num_rings) == 0) 5310adfc5217SJeff Kirsher max >>= 1; 5311adfc5217SJeff Kirsher 5312adfc5217SJeff Kirsher if (num_rings != max) 5313adfc5217SJeff Kirsher max <<= 1; 5314adfc5217SJeff Kirsher 5315adfc5217SJeff Kirsher return max; 5316adfc5217SJeff Kirsher } 5317adfc5217SJeff Kirsher 5318adfc5217SJeff Kirsher static void 5319adfc5217SJeff Kirsher bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) 5320adfc5217SJeff Kirsher { 5321adfc5217SJeff Kirsher u32 rx_size, rx_space, jumbo_size; 5322adfc5217SJeff Kirsher 5323adfc5217SJeff Kirsher /* 8 for CRC and VLAN */ 5324adfc5217SJeff Kirsher rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8; 5325adfc5217SJeff Kirsher 5326adfc5217SJeff Kirsher rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD + 5327dd2bc8e9SEric Dumazet SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 5328adfc5217SJeff Kirsher 5329adfc5217SJeff Kirsher bp->rx_copy_thresh = BNX2_RX_COPY_THRESH; 5330adfc5217SJeff Kirsher bp->rx_pg_ring_size = 0; 5331adfc5217SJeff Kirsher bp->rx_max_pg_ring = 0; 5332adfc5217SJeff Kirsher bp->rx_max_pg_ring_idx = 0; 5333adfc5217SJeff Kirsher if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) { 5334adfc5217SJeff Kirsher int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 5335adfc5217SJeff Kirsher 5336adfc5217SJeff Kirsher jumbo_size = size * pages; 5337adfc5217SJeff Kirsher if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT) 5338adfc5217SJeff Kirsher jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT; 5339adfc5217SJeff Kirsher 5340adfc5217SJeff Kirsher bp->rx_pg_ring_size = jumbo_size; 5341adfc5217SJeff Kirsher bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size, 5342adfc5217SJeff Kirsher MAX_RX_PG_RINGS); 5343adfc5217SJeff Kirsher bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1; 5344adfc5217SJeff Kirsher rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET; 5345adfc5217SJeff Kirsher bp->rx_copy_thresh = 0; 5346adfc5217SJeff Kirsher } 5347adfc5217SJeff Kirsher 5348adfc5217SJeff Kirsher bp->rx_buf_use_size = rx_size; 5349dd2bc8e9SEric Dumazet /* hw alignment + build_skb() overhead*/ 5350dd2bc8e9SEric Dumazet bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) + 5351dd2bc8e9SEric Dumazet NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 5352adfc5217SJeff Kirsher bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET; 5353adfc5217SJeff Kirsher bp->rx_ring_size = size; 5354adfc5217SJeff Kirsher bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS); 5355adfc5217SJeff Kirsher bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1; 5356adfc5217SJeff Kirsher } 5357adfc5217SJeff Kirsher 5358adfc5217SJeff Kirsher static void 5359adfc5217SJeff Kirsher bnx2_free_tx_skbs(struct bnx2 *bp) 5360adfc5217SJeff Kirsher { 5361adfc5217SJeff Kirsher int i; 5362adfc5217SJeff Kirsher 5363adfc5217SJeff Kirsher for (i = 0; i < bp->num_tx_rings; i++) { 5364adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 5365adfc5217SJeff Kirsher struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 5366adfc5217SJeff Kirsher int j; 5367adfc5217SJeff Kirsher 5368adfc5217SJeff Kirsher if (txr->tx_buf_ring == NULL) 5369adfc5217SJeff Kirsher continue; 5370adfc5217SJeff Kirsher 5371adfc5217SJeff Kirsher for (j = 0; j < TX_DESC_CNT; ) { 5372adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 5373adfc5217SJeff Kirsher struct sk_buff *skb = tx_buf->skb; 5374adfc5217SJeff Kirsher int k, last; 5375adfc5217SJeff Kirsher 5376adfc5217SJeff Kirsher if (skb == NULL) { 5377adfc5217SJeff Kirsher j++; 5378adfc5217SJeff Kirsher continue; 5379adfc5217SJeff Kirsher } 5380adfc5217SJeff Kirsher 5381adfc5217SJeff Kirsher dma_unmap_single(&bp->pdev->dev, 5382adfc5217SJeff Kirsher dma_unmap_addr(tx_buf, mapping), 5383adfc5217SJeff Kirsher skb_headlen(skb), 5384adfc5217SJeff Kirsher PCI_DMA_TODEVICE); 5385adfc5217SJeff Kirsher 5386adfc5217SJeff Kirsher tx_buf->skb = NULL; 5387adfc5217SJeff Kirsher 5388adfc5217SJeff Kirsher last = tx_buf->nr_frags; 5389adfc5217SJeff Kirsher j++; 5390adfc5217SJeff Kirsher for (k = 0; k < last; k++, j++) { 5391adfc5217SJeff Kirsher tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)]; 5392adfc5217SJeff Kirsher dma_unmap_page(&bp->pdev->dev, 5393adfc5217SJeff Kirsher dma_unmap_addr(tx_buf, mapping), 53949e903e08SEric Dumazet skb_frag_size(&skb_shinfo(skb)->frags[k]), 5395adfc5217SJeff Kirsher PCI_DMA_TODEVICE); 5396adfc5217SJeff Kirsher } 5397adfc5217SJeff Kirsher dev_kfree_skb(skb); 5398adfc5217SJeff Kirsher } 5399e9831909SEric Dumazet netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 5400adfc5217SJeff Kirsher } 5401adfc5217SJeff Kirsher } 5402adfc5217SJeff Kirsher 5403adfc5217SJeff Kirsher static void 5404adfc5217SJeff Kirsher bnx2_free_rx_skbs(struct bnx2 *bp) 5405adfc5217SJeff Kirsher { 5406adfc5217SJeff Kirsher int i; 5407adfc5217SJeff Kirsher 5408adfc5217SJeff Kirsher for (i = 0; i < bp->num_rx_rings; i++) { 5409adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 5410adfc5217SJeff Kirsher struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 5411adfc5217SJeff Kirsher int j; 5412adfc5217SJeff Kirsher 5413adfc5217SJeff Kirsher if (rxr->rx_buf_ring == NULL) 5414adfc5217SJeff Kirsher return; 5415adfc5217SJeff Kirsher 5416adfc5217SJeff Kirsher for (j = 0; j < bp->rx_max_ring_idx; j++) { 5417adfc5217SJeff Kirsher struct sw_bd *rx_buf = &rxr->rx_buf_ring[j]; 5418dd2bc8e9SEric Dumazet u8 *data = rx_buf->data; 5419adfc5217SJeff Kirsher 5420dd2bc8e9SEric Dumazet if (data == NULL) 5421adfc5217SJeff Kirsher continue; 5422adfc5217SJeff Kirsher 5423adfc5217SJeff Kirsher dma_unmap_single(&bp->pdev->dev, 5424adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 5425adfc5217SJeff Kirsher bp->rx_buf_use_size, 5426adfc5217SJeff Kirsher PCI_DMA_FROMDEVICE); 5427adfc5217SJeff Kirsher 5428dd2bc8e9SEric Dumazet rx_buf->data = NULL; 5429adfc5217SJeff Kirsher 5430dd2bc8e9SEric Dumazet kfree(data); 5431adfc5217SJeff Kirsher } 5432adfc5217SJeff Kirsher for (j = 0; j < bp->rx_max_pg_ring_idx; j++) 5433adfc5217SJeff Kirsher bnx2_free_rx_page(bp, rxr, j); 5434adfc5217SJeff Kirsher } 5435adfc5217SJeff Kirsher } 5436adfc5217SJeff Kirsher 5437adfc5217SJeff Kirsher static void 5438adfc5217SJeff Kirsher bnx2_free_skbs(struct bnx2 *bp) 5439adfc5217SJeff Kirsher { 5440adfc5217SJeff Kirsher bnx2_free_tx_skbs(bp); 5441adfc5217SJeff Kirsher bnx2_free_rx_skbs(bp); 5442adfc5217SJeff Kirsher } 5443adfc5217SJeff Kirsher 5444adfc5217SJeff Kirsher static int 5445adfc5217SJeff Kirsher bnx2_reset_nic(struct bnx2 *bp, u32 reset_code) 5446adfc5217SJeff Kirsher { 5447adfc5217SJeff Kirsher int rc; 5448adfc5217SJeff Kirsher 5449adfc5217SJeff Kirsher rc = bnx2_reset_chip(bp, reset_code); 5450adfc5217SJeff Kirsher bnx2_free_skbs(bp); 5451adfc5217SJeff Kirsher if (rc) 5452adfc5217SJeff Kirsher return rc; 5453adfc5217SJeff Kirsher 5454adfc5217SJeff Kirsher if ((rc = bnx2_init_chip(bp)) != 0) 5455adfc5217SJeff Kirsher return rc; 5456adfc5217SJeff Kirsher 5457adfc5217SJeff Kirsher bnx2_init_all_rings(bp); 5458adfc5217SJeff Kirsher return 0; 5459adfc5217SJeff Kirsher } 5460adfc5217SJeff Kirsher 5461adfc5217SJeff Kirsher static int 5462adfc5217SJeff Kirsher bnx2_init_nic(struct bnx2 *bp, int reset_phy) 5463adfc5217SJeff Kirsher { 5464adfc5217SJeff Kirsher int rc; 5465adfc5217SJeff Kirsher 5466adfc5217SJeff Kirsher if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) 5467adfc5217SJeff Kirsher return rc; 5468adfc5217SJeff Kirsher 5469adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 5470adfc5217SJeff Kirsher bnx2_init_phy(bp, reset_phy); 5471adfc5217SJeff Kirsher bnx2_set_link(bp); 5472adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 5473adfc5217SJeff Kirsher bnx2_remote_phy_event(bp); 5474adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 5475adfc5217SJeff Kirsher return 0; 5476adfc5217SJeff Kirsher } 5477adfc5217SJeff Kirsher 5478adfc5217SJeff Kirsher static int 5479adfc5217SJeff Kirsher bnx2_shutdown_chip(struct bnx2 *bp) 5480adfc5217SJeff Kirsher { 5481adfc5217SJeff Kirsher u32 reset_code; 5482adfc5217SJeff Kirsher 5483adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_NO_WOL) 5484adfc5217SJeff Kirsher reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; 5485adfc5217SJeff Kirsher else if (bp->wol) 5486adfc5217SJeff Kirsher reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; 5487adfc5217SJeff Kirsher else 5488adfc5217SJeff Kirsher reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; 5489adfc5217SJeff Kirsher 5490adfc5217SJeff Kirsher return bnx2_reset_chip(bp, reset_code); 5491adfc5217SJeff Kirsher } 5492adfc5217SJeff Kirsher 5493adfc5217SJeff Kirsher static int 5494adfc5217SJeff Kirsher bnx2_test_registers(struct bnx2 *bp) 5495adfc5217SJeff Kirsher { 5496adfc5217SJeff Kirsher int ret; 5497adfc5217SJeff Kirsher int i, is_5709; 5498adfc5217SJeff Kirsher static const struct { 5499adfc5217SJeff Kirsher u16 offset; 5500adfc5217SJeff Kirsher u16 flags; 5501adfc5217SJeff Kirsher #define BNX2_FL_NOT_5709 1 5502adfc5217SJeff Kirsher u32 rw_mask; 5503adfc5217SJeff Kirsher u32 ro_mask; 5504adfc5217SJeff Kirsher } reg_tbl[] = { 5505adfc5217SJeff Kirsher { 0x006c, 0, 0x00000000, 0x0000003f }, 5506adfc5217SJeff Kirsher { 0x0090, 0, 0xffffffff, 0x00000000 }, 5507adfc5217SJeff Kirsher { 0x0094, 0, 0x00000000, 0x00000000 }, 5508adfc5217SJeff Kirsher 5509adfc5217SJeff Kirsher { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 }, 5510adfc5217SJeff Kirsher { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5511adfc5217SJeff Kirsher { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5512adfc5217SJeff Kirsher { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff }, 5513adfc5217SJeff Kirsher { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 }, 5514adfc5217SJeff Kirsher { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, 5515adfc5217SJeff Kirsher { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff }, 5516adfc5217SJeff Kirsher { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5517adfc5217SJeff Kirsher { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5518adfc5217SJeff Kirsher 5519adfc5217SJeff Kirsher { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5520adfc5217SJeff Kirsher { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5521adfc5217SJeff Kirsher { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, 5522adfc5217SJeff Kirsher { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, 5523adfc5217SJeff Kirsher { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, 5524adfc5217SJeff Kirsher { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, 5525adfc5217SJeff Kirsher 5526adfc5217SJeff Kirsher { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, 5527adfc5217SJeff Kirsher { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 }, 5528adfc5217SJeff Kirsher { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 }, 5529adfc5217SJeff Kirsher 5530adfc5217SJeff Kirsher { 0x1000, 0, 0x00000000, 0x00000001 }, 5531adfc5217SJeff Kirsher { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 }, 5532adfc5217SJeff Kirsher 5533adfc5217SJeff Kirsher { 0x1408, 0, 0x01c00800, 0x00000000 }, 5534adfc5217SJeff Kirsher { 0x149c, 0, 0x8000ffff, 0x00000000 }, 5535adfc5217SJeff Kirsher { 0x14a8, 0, 0x00000000, 0x000001ff }, 5536adfc5217SJeff Kirsher { 0x14ac, 0, 0x0fffffff, 0x10000000 }, 5537adfc5217SJeff Kirsher { 0x14b0, 0, 0x00000002, 0x00000001 }, 5538adfc5217SJeff Kirsher { 0x14b8, 0, 0x00000000, 0x00000000 }, 5539adfc5217SJeff Kirsher { 0x14c0, 0, 0x00000000, 0x00000009 }, 5540adfc5217SJeff Kirsher { 0x14c4, 0, 0x00003fff, 0x00000000 }, 5541adfc5217SJeff Kirsher { 0x14cc, 0, 0x00000000, 0x00000001 }, 5542adfc5217SJeff Kirsher { 0x14d0, 0, 0xffffffff, 0x00000000 }, 5543adfc5217SJeff Kirsher 5544adfc5217SJeff Kirsher { 0x1800, 0, 0x00000000, 0x00000001 }, 5545adfc5217SJeff Kirsher { 0x1804, 0, 0x00000000, 0x00000003 }, 5546adfc5217SJeff Kirsher 5547adfc5217SJeff Kirsher { 0x2800, 0, 0x00000000, 0x00000001 }, 5548adfc5217SJeff Kirsher { 0x2804, 0, 0x00000000, 0x00003f01 }, 5549adfc5217SJeff Kirsher { 0x2808, 0, 0x0f3f3f03, 0x00000000 }, 5550adfc5217SJeff Kirsher { 0x2810, 0, 0xffff0000, 0x00000000 }, 5551adfc5217SJeff Kirsher { 0x2814, 0, 0xffff0000, 0x00000000 }, 5552adfc5217SJeff Kirsher { 0x2818, 0, 0xffff0000, 0x00000000 }, 5553adfc5217SJeff Kirsher { 0x281c, 0, 0xffff0000, 0x00000000 }, 5554adfc5217SJeff Kirsher { 0x2834, 0, 0xffffffff, 0x00000000 }, 5555adfc5217SJeff Kirsher { 0x2840, 0, 0x00000000, 0xffffffff }, 5556adfc5217SJeff Kirsher { 0x2844, 0, 0x00000000, 0xffffffff }, 5557adfc5217SJeff Kirsher { 0x2848, 0, 0xffffffff, 0x00000000 }, 5558adfc5217SJeff Kirsher { 0x284c, 0, 0xf800f800, 0x07ff07ff }, 5559adfc5217SJeff Kirsher 5560adfc5217SJeff Kirsher { 0x2c00, 0, 0x00000000, 0x00000011 }, 5561adfc5217SJeff Kirsher { 0x2c04, 0, 0x00000000, 0x00030007 }, 5562adfc5217SJeff Kirsher 5563adfc5217SJeff Kirsher { 0x3c00, 0, 0x00000000, 0x00000001 }, 5564adfc5217SJeff Kirsher { 0x3c04, 0, 0x00000000, 0x00070000 }, 5565adfc5217SJeff Kirsher { 0x3c08, 0, 0x00007f71, 0x07f00000 }, 5566adfc5217SJeff Kirsher { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 }, 5567adfc5217SJeff Kirsher { 0x3c10, 0, 0xffffffff, 0x00000000 }, 5568adfc5217SJeff Kirsher { 0x3c14, 0, 0x00000000, 0xffffffff }, 5569adfc5217SJeff Kirsher { 0x3c18, 0, 0x00000000, 0xffffffff }, 5570adfc5217SJeff Kirsher { 0x3c1c, 0, 0xfffff000, 0x00000000 }, 5571adfc5217SJeff Kirsher { 0x3c20, 0, 0xffffff00, 0x00000000 }, 5572adfc5217SJeff Kirsher 5573adfc5217SJeff Kirsher { 0x5004, 0, 0x00000000, 0x0000007f }, 5574adfc5217SJeff Kirsher { 0x5008, 0, 0x0f0007ff, 0x00000000 }, 5575adfc5217SJeff Kirsher 5576adfc5217SJeff Kirsher { 0x5c00, 0, 0x00000000, 0x00000001 }, 5577adfc5217SJeff Kirsher { 0x5c04, 0, 0x00000000, 0x0003000f }, 5578adfc5217SJeff Kirsher { 0x5c08, 0, 0x00000003, 0x00000000 }, 5579adfc5217SJeff Kirsher { 0x5c0c, 0, 0x0000fff8, 0x00000000 }, 5580adfc5217SJeff Kirsher { 0x5c10, 0, 0x00000000, 0xffffffff }, 5581adfc5217SJeff Kirsher { 0x5c80, 0, 0x00000000, 0x0f7113f1 }, 5582adfc5217SJeff Kirsher { 0x5c84, 0, 0x00000000, 0x0000f333 }, 5583adfc5217SJeff Kirsher { 0x5c88, 0, 0x00000000, 0x00077373 }, 5584adfc5217SJeff Kirsher { 0x5c8c, 0, 0x00000000, 0x0007f737 }, 5585adfc5217SJeff Kirsher 5586adfc5217SJeff Kirsher { 0x6808, 0, 0x0000ff7f, 0x00000000 }, 5587adfc5217SJeff Kirsher { 0x680c, 0, 0xffffffff, 0x00000000 }, 5588adfc5217SJeff Kirsher { 0x6810, 0, 0xffffffff, 0x00000000 }, 5589adfc5217SJeff Kirsher { 0x6814, 0, 0xffffffff, 0x00000000 }, 5590adfc5217SJeff Kirsher { 0x6818, 0, 0xffffffff, 0x00000000 }, 5591adfc5217SJeff Kirsher { 0x681c, 0, 0xffffffff, 0x00000000 }, 5592adfc5217SJeff Kirsher { 0x6820, 0, 0x00ff00ff, 0x00000000 }, 5593adfc5217SJeff Kirsher { 0x6824, 0, 0x00ff00ff, 0x00000000 }, 5594adfc5217SJeff Kirsher { 0x6828, 0, 0x00ff00ff, 0x00000000 }, 5595adfc5217SJeff Kirsher { 0x682c, 0, 0x03ff03ff, 0x00000000 }, 5596adfc5217SJeff Kirsher { 0x6830, 0, 0x03ff03ff, 0x00000000 }, 5597adfc5217SJeff Kirsher { 0x6834, 0, 0x03ff03ff, 0x00000000 }, 5598adfc5217SJeff Kirsher { 0x6838, 0, 0x03ff03ff, 0x00000000 }, 5599adfc5217SJeff Kirsher { 0x683c, 0, 0x0000ffff, 0x00000000 }, 5600adfc5217SJeff Kirsher { 0x6840, 0, 0x00000ff0, 0x00000000 }, 5601adfc5217SJeff Kirsher { 0x6844, 0, 0x00ffff00, 0x00000000 }, 5602adfc5217SJeff Kirsher { 0x684c, 0, 0xffffffff, 0x00000000 }, 5603adfc5217SJeff Kirsher { 0x6850, 0, 0x7f7f7f7f, 0x00000000 }, 5604adfc5217SJeff Kirsher { 0x6854, 0, 0x7f7f7f7f, 0x00000000 }, 5605adfc5217SJeff Kirsher { 0x6858, 0, 0x7f7f7f7f, 0x00000000 }, 5606adfc5217SJeff Kirsher { 0x685c, 0, 0x7f7f7f7f, 0x00000000 }, 5607adfc5217SJeff Kirsher { 0x6908, 0, 0x00000000, 0x0001ff0f }, 5608adfc5217SJeff Kirsher { 0x690c, 0, 0x00000000, 0x0ffe00f0 }, 5609adfc5217SJeff Kirsher 5610adfc5217SJeff Kirsher { 0xffff, 0, 0x00000000, 0x00000000 }, 5611adfc5217SJeff Kirsher }; 5612adfc5217SJeff Kirsher 5613adfc5217SJeff Kirsher ret = 0; 5614adfc5217SJeff Kirsher is_5709 = 0; 5615adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) 5616adfc5217SJeff Kirsher is_5709 = 1; 5617adfc5217SJeff Kirsher 5618adfc5217SJeff Kirsher for (i = 0; reg_tbl[i].offset != 0xffff; i++) { 5619adfc5217SJeff Kirsher u32 offset, rw_mask, ro_mask, save_val, val; 5620adfc5217SJeff Kirsher u16 flags = reg_tbl[i].flags; 5621adfc5217SJeff Kirsher 5622adfc5217SJeff Kirsher if (is_5709 && (flags & BNX2_FL_NOT_5709)) 5623adfc5217SJeff Kirsher continue; 5624adfc5217SJeff Kirsher 5625adfc5217SJeff Kirsher offset = (u32) reg_tbl[i].offset; 5626adfc5217SJeff Kirsher rw_mask = reg_tbl[i].rw_mask; 5627adfc5217SJeff Kirsher ro_mask = reg_tbl[i].ro_mask; 5628adfc5217SJeff Kirsher 5629adfc5217SJeff Kirsher save_val = readl(bp->regview + offset); 5630adfc5217SJeff Kirsher 5631adfc5217SJeff Kirsher writel(0, bp->regview + offset); 5632adfc5217SJeff Kirsher 5633adfc5217SJeff Kirsher val = readl(bp->regview + offset); 5634adfc5217SJeff Kirsher if ((val & rw_mask) != 0) { 5635adfc5217SJeff Kirsher goto reg_test_err; 5636adfc5217SJeff Kirsher } 5637adfc5217SJeff Kirsher 5638adfc5217SJeff Kirsher if ((val & ro_mask) != (save_val & ro_mask)) { 5639adfc5217SJeff Kirsher goto reg_test_err; 5640adfc5217SJeff Kirsher } 5641adfc5217SJeff Kirsher 5642adfc5217SJeff Kirsher writel(0xffffffff, bp->regview + offset); 5643adfc5217SJeff Kirsher 5644adfc5217SJeff Kirsher val = readl(bp->regview + offset); 5645adfc5217SJeff Kirsher if ((val & rw_mask) != rw_mask) { 5646adfc5217SJeff Kirsher goto reg_test_err; 5647adfc5217SJeff Kirsher } 5648adfc5217SJeff Kirsher 5649adfc5217SJeff Kirsher if ((val & ro_mask) != (save_val & ro_mask)) { 5650adfc5217SJeff Kirsher goto reg_test_err; 5651adfc5217SJeff Kirsher } 5652adfc5217SJeff Kirsher 5653adfc5217SJeff Kirsher writel(save_val, bp->regview + offset); 5654adfc5217SJeff Kirsher continue; 5655adfc5217SJeff Kirsher 5656adfc5217SJeff Kirsher reg_test_err: 5657adfc5217SJeff Kirsher writel(save_val, bp->regview + offset); 5658adfc5217SJeff Kirsher ret = -ENODEV; 5659adfc5217SJeff Kirsher break; 5660adfc5217SJeff Kirsher } 5661adfc5217SJeff Kirsher return ret; 5662adfc5217SJeff Kirsher } 5663adfc5217SJeff Kirsher 5664adfc5217SJeff Kirsher static int 5665adfc5217SJeff Kirsher bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size) 5666adfc5217SJeff Kirsher { 5667adfc5217SJeff Kirsher static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, 5668adfc5217SJeff Kirsher 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; 5669adfc5217SJeff Kirsher int i; 5670adfc5217SJeff Kirsher 5671adfc5217SJeff Kirsher for (i = 0; i < sizeof(test_pattern) / 4; i++) { 5672adfc5217SJeff Kirsher u32 offset; 5673adfc5217SJeff Kirsher 5674adfc5217SJeff Kirsher for (offset = 0; offset < size; offset += 4) { 5675adfc5217SJeff Kirsher 5676adfc5217SJeff Kirsher bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]); 5677adfc5217SJeff Kirsher 5678adfc5217SJeff Kirsher if (bnx2_reg_rd_ind(bp, start + offset) != 5679adfc5217SJeff Kirsher test_pattern[i]) { 5680adfc5217SJeff Kirsher return -ENODEV; 5681adfc5217SJeff Kirsher } 5682adfc5217SJeff Kirsher } 5683adfc5217SJeff Kirsher } 5684adfc5217SJeff Kirsher return 0; 5685adfc5217SJeff Kirsher } 5686adfc5217SJeff Kirsher 5687adfc5217SJeff Kirsher static int 5688adfc5217SJeff Kirsher bnx2_test_memory(struct bnx2 *bp) 5689adfc5217SJeff Kirsher { 5690adfc5217SJeff Kirsher int ret = 0; 5691adfc5217SJeff Kirsher int i; 5692adfc5217SJeff Kirsher static struct mem_entry { 5693adfc5217SJeff Kirsher u32 offset; 5694adfc5217SJeff Kirsher u32 len; 5695adfc5217SJeff Kirsher } mem_tbl_5706[] = { 5696adfc5217SJeff Kirsher { 0x60000, 0x4000 }, 5697adfc5217SJeff Kirsher { 0xa0000, 0x3000 }, 5698adfc5217SJeff Kirsher { 0xe0000, 0x4000 }, 5699adfc5217SJeff Kirsher { 0x120000, 0x4000 }, 5700adfc5217SJeff Kirsher { 0x1a0000, 0x4000 }, 5701adfc5217SJeff Kirsher { 0x160000, 0x4000 }, 5702adfc5217SJeff Kirsher { 0xffffffff, 0 }, 5703adfc5217SJeff Kirsher }, 5704adfc5217SJeff Kirsher mem_tbl_5709[] = { 5705adfc5217SJeff Kirsher { 0x60000, 0x4000 }, 5706adfc5217SJeff Kirsher { 0xa0000, 0x3000 }, 5707adfc5217SJeff Kirsher { 0xe0000, 0x4000 }, 5708adfc5217SJeff Kirsher { 0x120000, 0x4000 }, 5709adfc5217SJeff Kirsher { 0x1a0000, 0x4000 }, 5710adfc5217SJeff Kirsher { 0xffffffff, 0 }, 5711adfc5217SJeff Kirsher }; 5712adfc5217SJeff Kirsher struct mem_entry *mem_tbl; 5713adfc5217SJeff Kirsher 5714adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) 5715adfc5217SJeff Kirsher mem_tbl = mem_tbl_5709; 5716adfc5217SJeff Kirsher else 5717adfc5217SJeff Kirsher mem_tbl = mem_tbl_5706; 5718adfc5217SJeff Kirsher 5719adfc5217SJeff Kirsher for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { 5720adfc5217SJeff Kirsher if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset, 5721adfc5217SJeff Kirsher mem_tbl[i].len)) != 0) { 5722adfc5217SJeff Kirsher return ret; 5723adfc5217SJeff Kirsher } 5724adfc5217SJeff Kirsher } 5725adfc5217SJeff Kirsher 5726adfc5217SJeff Kirsher return ret; 5727adfc5217SJeff Kirsher } 5728adfc5217SJeff Kirsher 5729adfc5217SJeff Kirsher #define BNX2_MAC_LOOPBACK 0 5730adfc5217SJeff Kirsher #define BNX2_PHY_LOOPBACK 1 5731adfc5217SJeff Kirsher 5732adfc5217SJeff Kirsher static int 5733adfc5217SJeff Kirsher bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) 5734adfc5217SJeff Kirsher { 5735adfc5217SJeff Kirsher unsigned int pkt_size, num_pkts, i; 5736dd2bc8e9SEric Dumazet struct sk_buff *skb; 5737dd2bc8e9SEric Dumazet u8 *data; 5738adfc5217SJeff Kirsher unsigned char *packet; 5739adfc5217SJeff Kirsher u16 rx_start_idx, rx_idx; 5740adfc5217SJeff Kirsher dma_addr_t map; 5741adfc5217SJeff Kirsher struct tx_bd *txbd; 5742adfc5217SJeff Kirsher struct sw_bd *rx_buf; 5743adfc5217SJeff Kirsher struct l2_fhdr *rx_hdr; 5744adfc5217SJeff Kirsher int ret = -ENODEV; 5745adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; 5746adfc5217SJeff Kirsher struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 5747adfc5217SJeff Kirsher struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 5748adfc5217SJeff Kirsher 5749adfc5217SJeff Kirsher tx_napi = bnapi; 5750adfc5217SJeff Kirsher 5751adfc5217SJeff Kirsher txr = &tx_napi->tx_ring; 5752adfc5217SJeff Kirsher rxr = &bnapi->rx_ring; 5753adfc5217SJeff Kirsher if (loopback_mode == BNX2_MAC_LOOPBACK) { 5754adfc5217SJeff Kirsher bp->loopback = MAC_LOOPBACK; 5755adfc5217SJeff Kirsher bnx2_set_mac_loopback(bp); 5756adfc5217SJeff Kirsher } 5757adfc5217SJeff Kirsher else if (loopback_mode == BNX2_PHY_LOOPBACK) { 5758adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 5759adfc5217SJeff Kirsher return 0; 5760adfc5217SJeff Kirsher 5761adfc5217SJeff Kirsher bp->loopback = PHY_LOOPBACK; 5762adfc5217SJeff Kirsher bnx2_set_phy_loopback(bp); 5763adfc5217SJeff Kirsher } 5764adfc5217SJeff Kirsher else 5765adfc5217SJeff Kirsher return -EINVAL; 5766adfc5217SJeff Kirsher 5767adfc5217SJeff Kirsher pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4); 5768adfc5217SJeff Kirsher skb = netdev_alloc_skb(bp->dev, pkt_size); 5769adfc5217SJeff Kirsher if (!skb) 5770adfc5217SJeff Kirsher return -ENOMEM; 5771adfc5217SJeff Kirsher packet = skb_put(skb, pkt_size); 5772adfc5217SJeff Kirsher memcpy(packet, bp->dev->dev_addr, 6); 5773adfc5217SJeff Kirsher memset(packet + 6, 0x0, 8); 5774adfc5217SJeff Kirsher for (i = 14; i < pkt_size; i++) 5775adfc5217SJeff Kirsher packet[i] = (unsigned char) (i & 0xff); 5776adfc5217SJeff Kirsher 5777adfc5217SJeff Kirsher map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 5778adfc5217SJeff Kirsher PCI_DMA_TODEVICE); 5779adfc5217SJeff Kirsher if (dma_mapping_error(&bp->pdev->dev, map)) { 5780adfc5217SJeff Kirsher dev_kfree_skb(skb); 5781adfc5217SJeff Kirsher return -EIO; 5782adfc5217SJeff Kirsher } 5783adfc5217SJeff Kirsher 5784adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_COMMAND, 5785adfc5217SJeff Kirsher bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); 5786adfc5217SJeff Kirsher 5787adfc5217SJeff Kirsher REG_RD(bp, BNX2_HC_COMMAND); 5788adfc5217SJeff Kirsher 5789adfc5217SJeff Kirsher udelay(5); 5790adfc5217SJeff Kirsher rx_start_idx = bnx2_get_hw_rx_cons(bnapi); 5791adfc5217SJeff Kirsher 5792adfc5217SJeff Kirsher num_pkts = 0; 5793adfc5217SJeff Kirsher 5794adfc5217SJeff Kirsher txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)]; 5795adfc5217SJeff Kirsher 5796adfc5217SJeff Kirsher txbd->tx_bd_haddr_hi = (u64) map >> 32; 5797adfc5217SJeff Kirsher txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; 5798adfc5217SJeff Kirsher txbd->tx_bd_mss_nbytes = pkt_size; 5799adfc5217SJeff Kirsher txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; 5800adfc5217SJeff Kirsher 5801adfc5217SJeff Kirsher num_pkts++; 5802adfc5217SJeff Kirsher txr->tx_prod = NEXT_TX_BD(txr->tx_prod); 5803adfc5217SJeff Kirsher txr->tx_prod_bseq += pkt_size; 5804adfc5217SJeff Kirsher 5805adfc5217SJeff Kirsher REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod); 5806adfc5217SJeff Kirsher REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); 5807adfc5217SJeff Kirsher 5808adfc5217SJeff Kirsher udelay(100); 5809adfc5217SJeff Kirsher 5810adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_COMMAND, 5811adfc5217SJeff Kirsher bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); 5812adfc5217SJeff Kirsher 5813adfc5217SJeff Kirsher REG_RD(bp, BNX2_HC_COMMAND); 5814adfc5217SJeff Kirsher 5815adfc5217SJeff Kirsher udelay(5); 5816adfc5217SJeff Kirsher 5817adfc5217SJeff Kirsher dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE); 5818adfc5217SJeff Kirsher dev_kfree_skb(skb); 5819adfc5217SJeff Kirsher 5820adfc5217SJeff Kirsher if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod) 5821adfc5217SJeff Kirsher goto loopback_test_done; 5822adfc5217SJeff Kirsher 5823adfc5217SJeff Kirsher rx_idx = bnx2_get_hw_rx_cons(bnapi); 5824adfc5217SJeff Kirsher if (rx_idx != rx_start_idx + num_pkts) { 5825adfc5217SJeff Kirsher goto loopback_test_done; 5826adfc5217SJeff Kirsher } 5827adfc5217SJeff Kirsher 5828adfc5217SJeff Kirsher rx_buf = &rxr->rx_buf_ring[rx_start_idx]; 5829dd2bc8e9SEric Dumazet data = rx_buf->data; 5830adfc5217SJeff Kirsher 5831dd2bc8e9SEric Dumazet rx_hdr = get_l2_fhdr(data); 5832dd2bc8e9SEric Dumazet data = (u8 *)rx_hdr + BNX2_RX_OFFSET; 5833adfc5217SJeff Kirsher 5834adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, 5835adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 5836dd2bc8e9SEric Dumazet bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); 5837adfc5217SJeff Kirsher 5838adfc5217SJeff Kirsher if (rx_hdr->l2_fhdr_status & 5839adfc5217SJeff Kirsher (L2_FHDR_ERRORS_BAD_CRC | 5840adfc5217SJeff Kirsher L2_FHDR_ERRORS_PHY_DECODE | 5841adfc5217SJeff Kirsher L2_FHDR_ERRORS_ALIGNMENT | 5842adfc5217SJeff Kirsher L2_FHDR_ERRORS_TOO_SHORT | 5843adfc5217SJeff Kirsher L2_FHDR_ERRORS_GIANT_FRAME)) { 5844adfc5217SJeff Kirsher 5845adfc5217SJeff Kirsher goto loopback_test_done; 5846adfc5217SJeff Kirsher } 5847adfc5217SJeff Kirsher 5848adfc5217SJeff Kirsher if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) { 5849adfc5217SJeff Kirsher goto loopback_test_done; 5850adfc5217SJeff Kirsher } 5851adfc5217SJeff Kirsher 5852adfc5217SJeff Kirsher for (i = 14; i < pkt_size; i++) { 5853dd2bc8e9SEric Dumazet if (*(data + i) != (unsigned char) (i & 0xff)) { 5854adfc5217SJeff Kirsher goto loopback_test_done; 5855adfc5217SJeff Kirsher } 5856adfc5217SJeff Kirsher } 5857adfc5217SJeff Kirsher 5858adfc5217SJeff Kirsher ret = 0; 5859adfc5217SJeff Kirsher 5860adfc5217SJeff Kirsher loopback_test_done: 5861adfc5217SJeff Kirsher bp->loopback = 0; 5862adfc5217SJeff Kirsher return ret; 5863adfc5217SJeff Kirsher } 5864adfc5217SJeff Kirsher 5865adfc5217SJeff Kirsher #define BNX2_MAC_LOOPBACK_FAILED 1 5866adfc5217SJeff Kirsher #define BNX2_PHY_LOOPBACK_FAILED 2 5867adfc5217SJeff Kirsher #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \ 5868adfc5217SJeff Kirsher BNX2_PHY_LOOPBACK_FAILED) 5869adfc5217SJeff Kirsher 5870adfc5217SJeff Kirsher static int 5871adfc5217SJeff Kirsher bnx2_test_loopback(struct bnx2 *bp) 5872adfc5217SJeff Kirsher { 5873adfc5217SJeff Kirsher int rc = 0; 5874adfc5217SJeff Kirsher 5875adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 5876adfc5217SJeff Kirsher return BNX2_LOOPBACK_FAILED; 5877adfc5217SJeff Kirsher 5878adfc5217SJeff Kirsher bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); 5879adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 5880adfc5217SJeff Kirsher bnx2_init_phy(bp, 1); 5881adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 5882adfc5217SJeff Kirsher if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK)) 5883adfc5217SJeff Kirsher rc |= BNX2_MAC_LOOPBACK_FAILED; 5884adfc5217SJeff Kirsher if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK)) 5885adfc5217SJeff Kirsher rc |= BNX2_PHY_LOOPBACK_FAILED; 5886adfc5217SJeff Kirsher return rc; 5887adfc5217SJeff Kirsher } 5888adfc5217SJeff Kirsher 5889adfc5217SJeff Kirsher #define NVRAM_SIZE 0x200 5890adfc5217SJeff Kirsher #define CRC32_RESIDUAL 0xdebb20e3 5891adfc5217SJeff Kirsher 5892adfc5217SJeff Kirsher static int 5893adfc5217SJeff Kirsher bnx2_test_nvram(struct bnx2 *bp) 5894adfc5217SJeff Kirsher { 5895adfc5217SJeff Kirsher __be32 buf[NVRAM_SIZE / 4]; 5896adfc5217SJeff Kirsher u8 *data = (u8 *) buf; 5897adfc5217SJeff Kirsher int rc = 0; 5898adfc5217SJeff Kirsher u32 magic, csum; 5899adfc5217SJeff Kirsher 5900adfc5217SJeff Kirsher if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0) 5901adfc5217SJeff Kirsher goto test_nvram_done; 5902adfc5217SJeff Kirsher 5903adfc5217SJeff Kirsher magic = be32_to_cpu(buf[0]); 5904adfc5217SJeff Kirsher if (magic != 0x669955aa) { 5905adfc5217SJeff Kirsher rc = -ENODEV; 5906adfc5217SJeff Kirsher goto test_nvram_done; 5907adfc5217SJeff Kirsher } 5908adfc5217SJeff Kirsher 5909adfc5217SJeff Kirsher if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0) 5910adfc5217SJeff Kirsher goto test_nvram_done; 5911adfc5217SJeff Kirsher 5912adfc5217SJeff Kirsher csum = ether_crc_le(0x100, data); 5913adfc5217SJeff Kirsher if (csum != CRC32_RESIDUAL) { 5914adfc5217SJeff Kirsher rc = -ENODEV; 5915adfc5217SJeff Kirsher goto test_nvram_done; 5916adfc5217SJeff Kirsher } 5917adfc5217SJeff Kirsher 5918adfc5217SJeff Kirsher csum = ether_crc_le(0x100, data + 0x100); 5919adfc5217SJeff Kirsher if (csum != CRC32_RESIDUAL) { 5920adfc5217SJeff Kirsher rc = -ENODEV; 5921adfc5217SJeff Kirsher } 5922adfc5217SJeff Kirsher 5923adfc5217SJeff Kirsher test_nvram_done: 5924adfc5217SJeff Kirsher return rc; 5925adfc5217SJeff Kirsher } 5926adfc5217SJeff Kirsher 5927adfc5217SJeff Kirsher static int 5928adfc5217SJeff Kirsher bnx2_test_link(struct bnx2 *bp) 5929adfc5217SJeff Kirsher { 5930adfc5217SJeff Kirsher u32 bmsr; 5931adfc5217SJeff Kirsher 5932adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 5933adfc5217SJeff Kirsher return -ENODEV; 5934adfc5217SJeff Kirsher 5935adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 5936adfc5217SJeff Kirsher if (bp->link_up) 5937adfc5217SJeff Kirsher return 0; 5938adfc5217SJeff Kirsher return -ENODEV; 5939adfc5217SJeff Kirsher } 5940adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 5941adfc5217SJeff Kirsher bnx2_enable_bmsr1(bp); 5942adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 5943adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 5944adfc5217SJeff Kirsher bnx2_disable_bmsr1(bp); 5945adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 5946adfc5217SJeff Kirsher 5947adfc5217SJeff Kirsher if (bmsr & BMSR_LSTATUS) { 5948adfc5217SJeff Kirsher return 0; 5949adfc5217SJeff Kirsher } 5950adfc5217SJeff Kirsher return -ENODEV; 5951adfc5217SJeff Kirsher } 5952adfc5217SJeff Kirsher 5953adfc5217SJeff Kirsher static int 5954adfc5217SJeff Kirsher bnx2_test_intr(struct bnx2 *bp) 5955adfc5217SJeff Kirsher { 5956adfc5217SJeff Kirsher int i; 5957adfc5217SJeff Kirsher u16 status_idx; 5958adfc5217SJeff Kirsher 5959adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 5960adfc5217SJeff Kirsher return -ENODEV; 5961adfc5217SJeff Kirsher 5962adfc5217SJeff Kirsher status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; 5963adfc5217SJeff Kirsher 5964adfc5217SJeff Kirsher /* This register is not touched during run-time. */ 5965adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); 5966adfc5217SJeff Kirsher REG_RD(bp, BNX2_HC_COMMAND); 5967adfc5217SJeff Kirsher 5968adfc5217SJeff Kirsher for (i = 0; i < 10; i++) { 5969adfc5217SJeff Kirsher if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != 5970adfc5217SJeff Kirsher status_idx) { 5971adfc5217SJeff Kirsher 5972adfc5217SJeff Kirsher break; 5973adfc5217SJeff Kirsher } 5974adfc5217SJeff Kirsher 5975adfc5217SJeff Kirsher msleep_interruptible(10); 5976adfc5217SJeff Kirsher } 5977adfc5217SJeff Kirsher if (i < 10) 5978adfc5217SJeff Kirsher return 0; 5979adfc5217SJeff Kirsher 5980adfc5217SJeff Kirsher return -ENODEV; 5981adfc5217SJeff Kirsher } 5982adfc5217SJeff Kirsher 5983adfc5217SJeff Kirsher /* Determining link for parallel detection. */ 5984adfc5217SJeff Kirsher static int 5985adfc5217SJeff Kirsher bnx2_5706_serdes_has_link(struct bnx2 *bp) 5986adfc5217SJeff Kirsher { 5987adfc5217SJeff Kirsher u32 mode_ctl, an_dbg, exp; 5988adfc5217SJeff Kirsher 5989adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL) 5990adfc5217SJeff Kirsher return 0; 5991adfc5217SJeff Kirsher 5992adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL); 5993adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl); 5994adfc5217SJeff Kirsher 5995adfc5217SJeff Kirsher if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET)) 5996adfc5217SJeff Kirsher return 0; 5997adfc5217SJeff Kirsher 5998adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); 5999adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 6000adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 6001adfc5217SJeff Kirsher 6002adfc5217SJeff Kirsher if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID)) 6003adfc5217SJeff Kirsher return 0; 6004adfc5217SJeff Kirsher 6005adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1); 6006adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp); 6007adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp); 6008adfc5217SJeff Kirsher 6009adfc5217SJeff Kirsher if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */ 6010adfc5217SJeff Kirsher return 0; 6011adfc5217SJeff Kirsher 6012adfc5217SJeff Kirsher return 1; 6013adfc5217SJeff Kirsher } 6014adfc5217SJeff Kirsher 6015adfc5217SJeff Kirsher static void 6016adfc5217SJeff Kirsher bnx2_5706_serdes_timer(struct bnx2 *bp) 6017adfc5217SJeff Kirsher { 6018adfc5217SJeff Kirsher int check_link = 1; 6019adfc5217SJeff Kirsher 6020adfc5217SJeff Kirsher spin_lock(&bp->phy_lock); 6021adfc5217SJeff Kirsher if (bp->serdes_an_pending) { 6022adfc5217SJeff Kirsher bp->serdes_an_pending--; 6023adfc5217SJeff Kirsher check_link = 0; 6024adfc5217SJeff Kirsher } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { 6025adfc5217SJeff Kirsher u32 bmcr; 6026adfc5217SJeff Kirsher 6027adfc5217SJeff Kirsher bp->current_interval = BNX2_TIMER_INTERVAL; 6028adfc5217SJeff Kirsher 6029adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 6030adfc5217SJeff Kirsher 6031adfc5217SJeff Kirsher if (bmcr & BMCR_ANENABLE) { 6032adfc5217SJeff Kirsher if (bnx2_5706_serdes_has_link(bp)) { 6033adfc5217SJeff Kirsher bmcr &= ~BMCR_ANENABLE; 6034adfc5217SJeff Kirsher bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; 6035adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 6036adfc5217SJeff Kirsher bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT; 6037adfc5217SJeff Kirsher } 6038adfc5217SJeff Kirsher } 6039adfc5217SJeff Kirsher } 6040adfc5217SJeff Kirsher else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && 6041adfc5217SJeff Kirsher (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) { 6042adfc5217SJeff Kirsher u32 phy2; 6043adfc5217SJeff Kirsher 6044adfc5217SJeff Kirsher bnx2_write_phy(bp, 0x17, 0x0f01); 6045adfc5217SJeff Kirsher bnx2_read_phy(bp, 0x15, &phy2); 6046adfc5217SJeff Kirsher if (phy2 & 0x20) { 6047adfc5217SJeff Kirsher u32 bmcr; 6048adfc5217SJeff Kirsher 6049adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 6050adfc5217SJeff Kirsher bmcr |= BMCR_ANENABLE; 6051adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 6052adfc5217SJeff Kirsher 6053adfc5217SJeff Kirsher bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; 6054adfc5217SJeff Kirsher } 6055adfc5217SJeff Kirsher } else 6056adfc5217SJeff Kirsher bp->current_interval = BNX2_TIMER_INTERVAL; 6057adfc5217SJeff Kirsher 6058adfc5217SJeff Kirsher if (check_link) { 6059adfc5217SJeff Kirsher u32 val; 6060adfc5217SJeff Kirsher 6061adfc5217SJeff Kirsher bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); 6062adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); 6063adfc5217SJeff Kirsher bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); 6064adfc5217SJeff Kirsher 6065adfc5217SJeff Kirsher if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) { 6066adfc5217SJeff Kirsher if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) { 6067adfc5217SJeff Kirsher bnx2_5706s_force_link_dn(bp, 1); 6068adfc5217SJeff Kirsher bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN; 6069adfc5217SJeff Kirsher } else 6070adfc5217SJeff Kirsher bnx2_set_link(bp); 6071adfc5217SJeff Kirsher } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC)) 6072adfc5217SJeff Kirsher bnx2_set_link(bp); 6073adfc5217SJeff Kirsher } 6074adfc5217SJeff Kirsher spin_unlock(&bp->phy_lock); 6075adfc5217SJeff Kirsher } 6076adfc5217SJeff Kirsher 6077adfc5217SJeff Kirsher static void 6078adfc5217SJeff Kirsher bnx2_5708_serdes_timer(struct bnx2 *bp) 6079adfc5217SJeff Kirsher { 6080adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 6081adfc5217SJeff Kirsher return; 6082adfc5217SJeff Kirsher 6083adfc5217SJeff Kirsher if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) { 6084adfc5217SJeff Kirsher bp->serdes_an_pending = 0; 6085adfc5217SJeff Kirsher return; 6086adfc5217SJeff Kirsher } 6087adfc5217SJeff Kirsher 6088adfc5217SJeff Kirsher spin_lock(&bp->phy_lock); 6089adfc5217SJeff Kirsher if (bp->serdes_an_pending) 6090adfc5217SJeff Kirsher bp->serdes_an_pending--; 6091adfc5217SJeff Kirsher else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { 6092adfc5217SJeff Kirsher u32 bmcr; 6093adfc5217SJeff Kirsher 6094adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 6095adfc5217SJeff Kirsher if (bmcr & BMCR_ANENABLE) { 6096adfc5217SJeff Kirsher bnx2_enable_forced_2g5(bp); 6097adfc5217SJeff Kirsher bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT; 6098adfc5217SJeff Kirsher } else { 6099adfc5217SJeff Kirsher bnx2_disable_forced_2g5(bp); 6100adfc5217SJeff Kirsher bp->serdes_an_pending = 2; 6101adfc5217SJeff Kirsher bp->current_interval = BNX2_TIMER_INTERVAL; 6102adfc5217SJeff Kirsher } 6103adfc5217SJeff Kirsher 6104adfc5217SJeff Kirsher } else 6105adfc5217SJeff Kirsher bp->current_interval = BNX2_TIMER_INTERVAL; 6106adfc5217SJeff Kirsher 6107adfc5217SJeff Kirsher spin_unlock(&bp->phy_lock); 6108adfc5217SJeff Kirsher } 6109adfc5217SJeff Kirsher 6110adfc5217SJeff Kirsher static void 6111adfc5217SJeff Kirsher bnx2_timer(unsigned long data) 6112adfc5217SJeff Kirsher { 6113adfc5217SJeff Kirsher struct bnx2 *bp = (struct bnx2 *) data; 6114adfc5217SJeff Kirsher 6115adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 6116adfc5217SJeff Kirsher return; 6117adfc5217SJeff Kirsher 6118adfc5217SJeff Kirsher if (atomic_read(&bp->intr_sem) != 0) 6119adfc5217SJeff Kirsher goto bnx2_restart_timer; 6120adfc5217SJeff Kirsher 6121adfc5217SJeff Kirsher if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) == 6122adfc5217SJeff Kirsher BNX2_FLAG_USING_MSI) 6123adfc5217SJeff Kirsher bnx2_chk_missed_msi(bp); 6124adfc5217SJeff Kirsher 6125adfc5217SJeff Kirsher bnx2_send_heart_beat(bp); 6126adfc5217SJeff Kirsher 6127adfc5217SJeff Kirsher bp->stats_blk->stat_FwRxDrop = 6128adfc5217SJeff Kirsher bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT); 6129adfc5217SJeff Kirsher 6130adfc5217SJeff Kirsher /* workaround occasional corrupted counters */ 6131adfc5217SJeff Kirsher if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks) 6132adfc5217SJeff Kirsher REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | 6133adfc5217SJeff Kirsher BNX2_HC_COMMAND_STATS_NOW); 6134adfc5217SJeff Kirsher 6135adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 6136adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5706) 6137adfc5217SJeff Kirsher bnx2_5706_serdes_timer(bp); 6138adfc5217SJeff Kirsher else 6139adfc5217SJeff Kirsher bnx2_5708_serdes_timer(bp); 6140adfc5217SJeff Kirsher } 6141adfc5217SJeff Kirsher 6142adfc5217SJeff Kirsher bnx2_restart_timer: 6143adfc5217SJeff Kirsher mod_timer(&bp->timer, jiffies + bp->current_interval); 6144adfc5217SJeff Kirsher } 6145adfc5217SJeff Kirsher 6146adfc5217SJeff Kirsher static int 6147adfc5217SJeff Kirsher bnx2_request_irq(struct bnx2 *bp) 6148adfc5217SJeff Kirsher { 6149adfc5217SJeff Kirsher unsigned long flags; 6150adfc5217SJeff Kirsher struct bnx2_irq *irq; 6151adfc5217SJeff Kirsher int rc = 0, i; 6152adfc5217SJeff Kirsher 6153adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX) 6154adfc5217SJeff Kirsher flags = 0; 6155adfc5217SJeff Kirsher else 6156adfc5217SJeff Kirsher flags = IRQF_SHARED; 6157adfc5217SJeff Kirsher 6158adfc5217SJeff Kirsher for (i = 0; i < bp->irq_nvecs; i++) { 6159adfc5217SJeff Kirsher irq = &bp->irq_tbl[i]; 6160adfc5217SJeff Kirsher rc = request_irq(irq->vector, irq->handler, flags, irq->name, 6161adfc5217SJeff Kirsher &bp->bnx2_napi[i]); 6162adfc5217SJeff Kirsher if (rc) 6163adfc5217SJeff Kirsher break; 6164adfc5217SJeff Kirsher irq->requested = 1; 6165adfc5217SJeff Kirsher } 6166adfc5217SJeff Kirsher return rc; 6167adfc5217SJeff Kirsher } 6168adfc5217SJeff Kirsher 6169adfc5217SJeff Kirsher static void 6170adfc5217SJeff Kirsher __bnx2_free_irq(struct bnx2 *bp) 6171adfc5217SJeff Kirsher { 6172adfc5217SJeff Kirsher struct bnx2_irq *irq; 6173adfc5217SJeff Kirsher int i; 6174adfc5217SJeff Kirsher 6175adfc5217SJeff Kirsher for (i = 0; i < bp->irq_nvecs; i++) { 6176adfc5217SJeff Kirsher irq = &bp->irq_tbl[i]; 6177adfc5217SJeff Kirsher if (irq->requested) 6178adfc5217SJeff Kirsher free_irq(irq->vector, &bp->bnx2_napi[i]); 6179adfc5217SJeff Kirsher irq->requested = 0; 6180adfc5217SJeff Kirsher } 6181adfc5217SJeff Kirsher } 6182adfc5217SJeff Kirsher 6183adfc5217SJeff Kirsher static void 6184adfc5217SJeff Kirsher bnx2_free_irq(struct bnx2 *bp) 6185adfc5217SJeff Kirsher { 6186adfc5217SJeff Kirsher 6187adfc5217SJeff Kirsher __bnx2_free_irq(bp); 6188adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_USING_MSI) 6189adfc5217SJeff Kirsher pci_disable_msi(bp->pdev); 6190adfc5217SJeff Kirsher else if (bp->flags & BNX2_FLAG_USING_MSIX) 6191adfc5217SJeff Kirsher pci_disable_msix(bp->pdev); 6192adfc5217SJeff Kirsher 6193adfc5217SJeff Kirsher bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI); 6194adfc5217SJeff Kirsher } 6195adfc5217SJeff Kirsher 6196adfc5217SJeff Kirsher static void 6197adfc5217SJeff Kirsher bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) 6198adfc5217SJeff Kirsher { 6199adfc5217SJeff Kirsher int i, total_vecs, rc; 6200adfc5217SJeff Kirsher struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC]; 6201adfc5217SJeff Kirsher struct net_device *dev = bp->dev; 6202adfc5217SJeff Kirsher const int len = sizeof(bp->irq_tbl[0].name); 6203adfc5217SJeff Kirsher 6204adfc5217SJeff Kirsher bnx2_setup_msix_tbl(bp); 6205adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); 6206adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE); 6207adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE); 6208adfc5217SJeff Kirsher 6209adfc5217SJeff Kirsher /* Need to flush the previous three writes to ensure MSI-X 6210adfc5217SJeff Kirsher * is setup properly */ 6211adfc5217SJeff Kirsher REG_RD(bp, BNX2_PCI_MSIX_CONTROL); 6212adfc5217SJeff Kirsher 6213adfc5217SJeff Kirsher for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { 6214adfc5217SJeff Kirsher msix_ent[i].entry = i; 6215adfc5217SJeff Kirsher msix_ent[i].vector = 0; 6216adfc5217SJeff Kirsher } 6217adfc5217SJeff Kirsher 6218adfc5217SJeff Kirsher total_vecs = msix_vecs; 6219adfc5217SJeff Kirsher #ifdef BCM_CNIC 6220adfc5217SJeff Kirsher total_vecs++; 6221adfc5217SJeff Kirsher #endif 6222adfc5217SJeff Kirsher rc = -ENOSPC; 6223adfc5217SJeff Kirsher while (total_vecs >= BNX2_MIN_MSIX_VEC) { 6224adfc5217SJeff Kirsher rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs); 6225adfc5217SJeff Kirsher if (rc <= 0) 6226adfc5217SJeff Kirsher break; 6227adfc5217SJeff Kirsher if (rc > 0) 6228adfc5217SJeff Kirsher total_vecs = rc; 6229adfc5217SJeff Kirsher } 6230adfc5217SJeff Kirsher 6231adfc5217SJeff Kirsher if (rc != 0) 6232adfc5217SJeff Kirsher return; 6233adfc5217SJeff Kirsher 6234adfc5217SJeff Kirsher msix_vecs = total_vecs; 6235adfc5217SJeff Kirsher #ifdef BCM_CNIC 6236adfc5217SJeff Kirsher msix_vecs--; 6237adfc5217SJeff Kirsher #endif 6238adfc5217SJeff Kirsher bp->irq_nvecs = msix_vecs; 6239adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; 6240adfc5217SJeff Kirsher for (i = 0; i < total_vecs; i++) { 6241adfc5217SJeff Kirsher bp->irq_tbl[i].vector = msix_ent[i].vector; 6242adfc5217SJeff Kirsher snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); 6243adfc5217SJeff Kirsher bp->irq_tbl[i].handler = bnx2_msi_1shot; 6244adfc5217SJeff Kirsher } 6245adfc5217SJeff Kirsher } 6246adfc5217SJeff Kirsher 6247adfc5217SJeff Kirsher static int 6248adfc5217SJeff Kirsher bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) 6249adfc5217SJeff Kirsher { 6250adfc5217SJeff Kirsher int cpus = num_online_cpus(); 6251adfc5217SJeff Kirsher int msix_vecs = min(cpus + 1, RX_MAX_RINGS); 6252adfc5217SJeff Kirsher 6253adfc5217SJeff Kirsher bp->irq_tbl[0].handler = bnx2_interrupt; 6254adfc5217SJeff Kirsher strcpy(bp->irq_tbl[0].name, bp->dev->name); 6255adfc5217SJeff Kirsher bp->irq_nvecs = 1; 6256adfc5217SJeff Kirsher bp->irq_tbl[0].vector = bp->pdev->irq; 6257adfc5217SJeff Kirsher 6258adfc5217SJeff Kirsher if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi) 6259adfc5217SJeff Kirsher bnx2_enable_msix(bp, msix_vecs); 6260adfc5217SJeff Kirsher 6261adfc5217SJeff Kirsher if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi && 6262adfc5217SJeff Kirsher !(bp->flags & BNX2_FLAG_USING_MSIX)) { 6263adfc5217SJeff Kirsher if (pci_enable_msi(bp->pdev) == 0) { 6264adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_USING_MSI; 6265adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 6266adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_ONE_SHOT_MSI; 6267adfc5217SJeff Kirsher bp->irq_tbl[0].handler = bnx2_msi_1shot; 6268adfc5217SJeff Kirsher } else 6269adfc5217SJeff Kirsher bp->irq_tbl[0].handler = bnx2_msi; 6270adfc5217SJeff Kirsher 6271adfc5217SJeff Kirsher bp->irq_tbl[0].vector = bp->pdev->irq; 6272adfc5217SJeff Kirsher } 6273adfc5217SJeff Kirsher } 6274adfc5217SJeff Kirsher 6275adfc5217SJeff Kirsher bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs); 6276adfc5217SJeff Kirsher netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings); 6277adfc5217SJeff Kirsher 6278adfc5217SJeff Kirsher bp->num_rx_rings = bp->irq_nvecs; 6279adfc5217SJeff Kirsher return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings); 6280adfc5217SJeff Kirsher } 6281adfc5217SJeff Kirsher 6282adfc5217SJeff Kirsher /* Called with rtnl_lock */ 6283adfc5217SJeff Kirsher static int 6284adfc5217SJeff Kirsher bnx2_open(struct net_device *dev) 6285adfc5217SJeff Kirsher { 6286adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 6287adfc5217SJeff Kirsher int rc; 6288adfc5217SJeff Kirsher 62897880b72eSfrançois romieu rc = bnx2_request_firmware(bp); 62907880b72eSfrançois romieu if (rc < 0) 62917880b72eSfrançois romieu goto out; 62927880b72eSfrançois romieu 6293adfc5217SJeff Kirsher netif_carrier_off(dev); 6294adfc5217SJeff Kirsher 6295adfc5217SJeff Kirsher bnx2_set_power_state(bp, PCI_D0); 6296adfc5217SJeff Kirsher bnx2_disable_int(bp); 6297adfc5217SJeff Kirsher 6298adfc5217SJeff Kirsher rc = bnx2_setup_int_mode(bp, disable_msi); 6299adfc5217SJeff Kirsher if (rc) 6300adfc5217SJeff Kirsher goto open_err; 6301adfc5217SJeff Kirsher bnx2_init_napi(bp); 6302adfc5217SJeff Kirsher bnx2_napi_enable(bp); 6303adfc5217SJeff Kirsher rc = bnx2_alloc_mem(bp); 6304adfc5217SJeff Kirsher if (rc) 6305adfc5217SJeff Kirsher goto open_err; 6306adfc5217SJeff Kirsher 6307adfc5217SJeff Kirsher rc = bnx2_request_irq(bp); 6308adfc5217SJeff Kirsher if (rc) 6309adfc5217SJeff Kirsher goto open_err; 6310adfc5217SJeff Kirsher 6311adfc5217SJeff Kirsher rc = bnx2_init_nic(bp, 1); 6312adfc5217SJeff Kirsher if (rc) 6313adfc5217SJeff Kirsher goto open_err; 6314adfc5217SJeff Kirsher 6315adfc5217SJeff Kirsher mod_timer(&bp->timer, jiffies + bp->current_interval); 6316adfc5217SJeff Kirsher 6317adfc5217SJeff Kirsher atomic_set(&bp->intr_sem, 0); 6318adfc5217SJeff Kirsher 6319adfc5217SJeff Kirsher memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block)); 6320adfc5217SJeff Kirsher 6321adfc5217SJeff Kirsher bnx2_enable_int(bp); 6322adfc5217SJeff Kirsher 6323adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_USING_MSI) { 6324adfc5217SJeff Kirsher /* Test MSI to make sure it is working 6325adfc5217SJeff Kirsher * If MSI test fails, go back to INTx mode 6326adfc5217SJeff Kirsher */ 6327adfc5217SJeff Kirsher if (bnx2_test_intr(bp) != 0) { 6328adfc5217SJeff Kirsher netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n"); 6329adfc5217SJeff Kirsher 6330adfc5217SJeff Kirsher bnx2_disable_int(bp); 6331adfc5217SJeff Kirsher bnx2_free_irq(bp); 6332adfc5217SJeff Kirsher 6333adfc5217SJeff Kirsher bnx2_setup_int_mode(bp, 1); 6334adfc5217SJeff Kirsher 6335adfc5217SJeff Kirsher rc = bnx2_init_nic(bp, 0); 6336adfc5217SJeff Kirsher 6337adfc5217SJeff Kirsher if (!rc) 6338adfc5217SJeff Kirsher rc = bnx2_request_irq(bp); 6339adfc5217SJeff Kirsher 6340adfc5217SJeff Kirsher if (rc) { 6341adfc5217SJeff Kirsher del_timer_sync(&bp->timer); 6342adfc5217SJeff Kirsher goto open_err; 6343adfc5217SJeff Kirsher } 6344adfc5217SJeff Kirsher bnx2_enable_int(bp); 6345adfc5217SJeff Kirsher } 6346adfc5217SJeff Kirsher } 6347adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_USING_MSI) 6348adfc5217SJeff Kirsher netdev_info(dev, "using MSI\n"); 6349adfc5217SJeff Kirsher else if (bp->flags & BNX2_FLAG_USING_MSIX) 6350adfc5217SJeff Kirsher netdev_info(dev, "using MSIX\n"); 6351adfc5217SJeff Kirsher 6352adfc5217SJeff Kirsher netif_tx_start_all_queues(dev); 63537880b72eSfrançois romieu out: 63547880b72eSfrançois romieu return rc; 6355adfc5217SJeff Kirsher 6356adfc5217SJeff Kirsher open_err: 6357adfc5217SJeff Kirsher bnx2_napi_disable(bp); 6358adfc5217SJeff Kirsher bnx2_free_skbs(bp); 6359adfc5217SJeff Kirsher bnx2_free_irq(bp); 6360adfc5217SJeff Kirsher bnx2_free_mem(bp); 6361adfc5217SJeff Kirsher bnx2_del_napi(bp); 63627880b72eSfrançois romieu bnx2_release_firmware(bp); 63637880b72eSfrançois romieu goto out; 6364adfc5217SJeff Kirsher } 6365adfc5217SJeff Kirsher 6366adfc5217SJeff Kirsher static void 6367adfc5217SJeff Kirsher bnx2_reset_task(struct work_struct *work) 6368adfc5217SJeff Kirsher { 6369adfc5217SJeff Kirsher struct bnx2 *bp = container_of(work, struct bnx2, reset_task); 6370adfc5217SJeff Kirsher int rc; 6371adfc5217SJeff Kirsher 6372adfc5217SJeff Kirsher rtnl_lock(); 6373adfc5217SJeff Kirsher if (!netif_running(bp->dev)) { 6374adfc5217SJeff Kirsher rtnl_unlock(); 6375adfc5217SJeff Kirsher return; 6376adfc5217SJeff Kirsher } 6377adfc5217SJeff Kirsher 6378adfc5217SJeff Kirsher bnx2_netif_stop(bp, true); 6379adfc5217SJeff Kirsher 6380adfc5217SJeff Kirsher rc = bnx2_init_nic(bp, 1); 6381adfc5217SJeff Kirsher if (rc) { 6382adfc5217SJeff Kirsher netdev_err(bp->dev, "failed to reset NIC, closing\n"); 6383adfc5217SJeff Kirsher bnx2_napi_enable(bp); 6384adfc5217SJeff Kirsher dev_close(bp->dev); 6385adfc5217SJeff Kirsher rtnl_unlock(); 6386adfc5217SJeff Kirsher return; 6387adfc5217SJeff Kirsher } 6388adfc5217SJeff Kirsher 6389adfc5217SJeff Kirsher atomic_set(&bp->intr_sem, 1); 6390adfc5217SJeff Kirsher bnx2_netif_start(bp, true); 6391adfc5217SJeff Kirsher rtnl_unlock(); 6392adfc5217SJeff Kirsher } 6393adfc5217SJeff Kirsher 6394adfc5217SJeff Kirsher static void 6395adfc5217SJeff Kirsher bnx2_dump_state(struct bnx2 *bp) 6396adfc5217SJeff Kirsher { 6397adfc5217SJeff Kirsher struct net_device *dev = bp->dev; 6398adfc5217SJeff Kirsher u32 val1, val2; 6399adfc5217SJeff Kirsher 6400adfc5217SJeff Kirsher pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1); 6401adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n", 6402adfc5217SJeff Kirsher atomic_read(&bp->intr_sem), val1); 6403adfc5217SJeff Kirsher pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1); 6404adfc5217SJeff Kirsher pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2); 6405adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2); 6406adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n", 6407adfc5217SJeff Kirsher REG_RD(bp, BNX2_EMAC_TX_STATUS), 6408adfc5217SJeff Kirsher REG_RD(bp, BNX2_EMAC_RX_STATUS)); 6409adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n", 6410adfc5217SJeff Kirsher REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL)); 6411adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n", 6412adfc5217SJeff Kirsher REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS)); 6413adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_USING_MSIX) 6414adfc5217SJeff Kirsher netdev_err(dev, "DEBUG: PBA[%08x]\n", 6415adfc5217SJeff Kirsher REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE)); 6416adfc5217SJeff Kirsher } 6417adfc5217SJeff Kirsher 6418adfc5217SJeff Kirsher static void 6419adfc5217SJeff Kirsher bnx2_tx_timeout(struct net_device *dev) 6420adfc5217SJeff Kirsher { 6421adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 6422adfc5217SJeff Kirsher 6423adfc5217SJeff Kirsher bnx2_dump_state(bp); 6424adfc5217SJeff Kirsher bnx2_dump_mcp_state(bp); 6425adfc5217SJeff Kirsher 6426adfc5217SJeff Kirsher /* This allows the netif to be shutdown gracefully before resetting */ 6427adfc5217SJeff Kirsher schedule_work(&bp->reset_task); 6428adfc5217SJeff Kirsher } 6429adfc5217SJeff Kirsher 6430adfc5217SJeff Kirsher /* Called with netif_tx_lock. 6431adfc5217SJeff Kirsher * bnx2_tx_int() runs without netif_tx_lock unless it needs to call 6432adfc5217SJeff Kirsher * netif_wake_queue(). 6433adfc5217SJeff Kirsher */ 6434adfc5217SJeff Kirsher static netdev_tx_t 6435adfc5217SJeff Kirsher bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) 6436adfc5217SJeff Kirsher { 6437adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 6438adfc5217SJeff Kirsher dma_addr_t mapping; 6439adfc5217SJeff Kirsher struct tx_bd *txbd; 6440adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 6441adfc5217SJeff Kirsher u32 len, vlan_tag_flags, last_frag, mss; 6442adfc5217SJeff Kirsher u16 prod, ring_prod; 6443adfc5217SJeff Kirsher int i; 6444adfc5217SJeff Kirsher struct bnx2_napi *bnapi; 6445adfc5217SJeff Kirsher struct bnx2_tx_ring_info *txr; 6446adfc5217SJeff Kirsher struct netdev_queue *txq; 6447adfc5217SJeff Kirsher 6448adfc5217SJeff Kirsher /* Determine which tx ring we will be placed on */ 6449adfc5217SJeff Kirsher i = skb_get_queue_mapping(skb); 6450adfc5217SJeff Kirsher bnapi = &bp->bnx2_napi[i]; 6451adfc5217SJeff Kirsher txr = &bnapi->tx_ring; 6452adfc5217SJeff Kirsher txq = netdev_get_tx_queue(dev, i); 6453adfc5217SJeff Kirsher 6454adfc5217SJeff Kirsher if (unlikely(bnx2_tx_avail(bp, txr) < 6455adfc5217SJeff Kirsher (skb_shinfo(skb)->nr_frags + 1))) { 6456adfc5217SJeff Kirsher netif_tx_stop_queue(txq); 6457adfc5217SJeff Kirsher netdev_err(dev, "BUG! Tx ring full when queue awake!\n"); 6458adfc5217SJeff Kirsher 6459adfc5217SJeff Kirsher return NETDEV_TX_BUSY; 6460adfc5217SJeff Kirsher } 6461adfc5217SJeff Kirsher len = skb_headlen(skb); 6462adfc5217SJeff Kirsher prod = txr->tx_prod; 6463adfc5217SJeff Kirsher ring_prod = TX_RING_IDX(prod); 6464adfc5217SJeff Kirsher 6465adfc5217SJeff Kirsher vlan_tag_flags = 0; 6466adfc5217SJeff Kirsher if (skb->ip_summed == CHECKSUM_PARTIAL) { 6467adfc5217SJeff Kirsher vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 6468adfc5217SJeff Kirsher } 6469adfc5217SJeff Kirsher 6470adfc5217SJeff Kirsher if (vlan_tx_tag_present(skb)) { 6471adfc5217SJeff Kirsher vlan_tag_flags |= 6472adfc5217SJeff Kirsher (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); 6473adfc5217SJeff Kirsher } 6474adfc5217SJeff Kirsher 6475adfc5217SJeff Kirsher if ((mss = skb_shinfo(skb)->gso_size)) { 6476adfc5217SJeff Kirsher u32 tcp_opt_len; 6477adfc5217SJeff Kirsher struct iphdr *iph; 6478adfc5217SJeff Kirsher 6479adfc5217SJeff Kirsher vlan_tag_flags |= TX_BD_FLAGS_SW_LSO; 6480adfc5217SJeff Kirsher 6481adfc5217SJeff Kirsher tcp_opt_len = tcp_optlen(skb); 6482adfc5217SJeff Kirsher 6483adfc5217SJeff Kirsher if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { 6484adfc5217SJeff Kirsher u32 tcp_off = skb_transport_offset(skb) - 6485adfc5217SJeff Kirsher sizeof(struct ipv6hdr) - ETH_HLEN; 6486adfc5217SJeff Kirsher 6487adfc5217SJeff Kirsher vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) | 6488adfc5217SJeff Kirsher TX_BD_FLAGS_SW_FLAGS; 6489adfc5217SJeff Kirsher if (likely(tcp_off == 0)) 6490adfc5217SJeff Kirsher vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK; 6491adfc5217SJeff Kirsher else { 6492adfc5217SJeff Kirsher tcp_off >>= 3; 6493adfc5217SJeff Kirsher vlan_tag_flags |= ((tcp_off & 0x3) << 6494adfc5217SJeff Kirsher TX_BD_FLAGS_TCP6_OFF0_SHL) | 6495adfc5217SJeff Kirsher ((tcp_off & 0x10) << 6496adfc5217SJeff Kirsher TX_BD_FLAGS_TCP6_OFF4_SHL); 6497adfc5217SJeff Kirsher mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL; 6498adfc5217SJeff Kirsher } 6499adfc5217SJeff Kirsher } else { 6500adfc5217SJeff Kirsher iph = ip_hdr(skb); 6501adfc5217SJeff Kirsher if (tcp_opt_len || (iph->ihl > 5)) { 6502adfc5217SJeff Kirsher vlan_tag_flags |= ((iph->ihl - 5) + 6503adfc5217SJeff Kirsher (tcp_opt_len >> 2)) << 8; 6504adfc5217SJeff Kirsher } 6505adfc5217SJeff Kirsher } 6506adfc5217SJeff Kirsher } else 6507adfc5217SJeff Kirsher mss = 0; 6508adfc5217SJeff Kirsher 6509adfc5217SJeff Kirsher mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE); 6510adfc5217SJeff Kirsher if (dma_mapping_error(&bp->pdev->dev, mapping)) { 6511adfc5217SJeff Kirsher dev_kfree_skb(skb); 6512adfc5217SJeff Kirsher return NETDEV_TX_OK; 6513adfc5217SJeff Kirsher } 6514adfc5217SJeff Kirsher 6515adfc5217SJeff Kirsher tx_buf = &txr->tx_buf_ring[ring_prod]; 6516adfc5217SJeff Kirsher tx_buf->skb = skb; 6517adfc5217SJeff Kirsher dma_unmap_addr_set(tx_buf, mapping, mapping); 6518adfc5217SJeff Kirsher 6519adfc5217SJeff Kirsher txbd = &txr->tx_desc_ring[ring_prod]; 6520adfc5217SJeff Kirsher 6521adfc5217SJeff Kirsher txbd->tx_bd_haddr_hi = (u64) mapping >> 32; 6522adfc5217SJeff Kirsher txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; 6523adfc5217SJeff Kirsher txbd->tx_bd_mss_nbytes = len | (mss << 16); 6524adfc5217SJeff Kirsher txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START; 6525adfc5217SJeff Kirsher 6526adfc5217SJeff Kirsher last_frag = skb_shinfo(skb)->nr_frags; 6527adfc5217SJeff Kirsher tx_buf->nr_frags = last_frag; 6528adfc5217SJeff Kirsher tx_buf->is_gso = skb_is_gso(skb); 6529adfc5217SJeff Kirsher 6530adfc5217SJeff Kirsher for (i = 0; i < last_frag; i++) { 65319e903e08SEric Dumazet const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 6532adfc5217SJeff Kirsher 6533adfc5217SJeff Kirsher prod = NEXT_TX_BD(prod); 6534adfc5217SJeff Kirsher ring_prod = TX_RING_IDX(prod); 6535adfc5217SJeff Kirsher txbd = &txr->tx_desc_ring[ring_prod]; 6536adfc5217SJeff Kirsher 65379e903e08SEric Dumazet len = skb_frag_size(frag); 6538b7b6a688SIan Campbell mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len, 65395d6bcdfeSIan Campbell DMA_TO_DEVICE); 6540adfc5217SJeff Kirsher if (dma_mapping_error(&bp->pdev->dev, mapping)) 6541adfc5217SJeff Kirsher goto dma_error; 6542adfc5217SJeff Kirsher dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping, 6543adfc5217SJeff Kirsher mapping); 6544adfc5217SJeff Kirsher 6545adfc5217SJeff Kirsher txbd->tx_bd_haddr_hi = (u64) mapping >> 32; 6546adfc5217SJeff Kirsher txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; 6547adfc5217SJeff Kirsher txbd->tx_bd_mss_nbytes = len | (mss << 16); 6548adfc5217SJeff Kirsher txbd->tx_bd_vlan_tag_flags = vlan_tag_flags; 6549adfc5217SJeff Kirsher 6550adfc5217SJeff Kirsher } 6551adfc5217SJeff Kirsher txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; 6552adfc5217SJeff Kirsher 6553e9831909SEric Dumazet netdev_tx_sent_queue(txq, skb->len); 6554e9831909SEric Dumazet 6555adfc5217SJeff Kirsher prod = NEXT_TX_BD(prod); 6556adfc5217SJeff Kirsher txr->tx_prod_bseq += skb->len; 6557adfc5217SJeff Kirsher 6558adfc5217SJeff Kirsher REG_WR16(bp, txr->tx_bidx_addr, prod); 6559adfc5217SJeff Kirsher REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); 6560adfc5217SJeff Kirsher 6561adfc5217SJeff Kirsher mmiowb(); 6562adfc5217SJeff Kirsher 6563adfc5217SJeff Kirsher txr->tx_prod = prod; 6564adfc5217SJeff Kirsher 6565adfc5217SJeff Kirsher if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) { 6566adfc5217SJeff Kirsher netif_tx_stop_queue(txq); 6567adfc5217SJeff Kirsher 6568adfc5217SJeff Kirsher /* netif_tx_stop_queue() must be done before checking 6569adfc5217SJeff Kirsher * tx index in bnx2_tx_avail() below, because in 6570adfc5217SJeff Kirsher * bnx2_tx_int(), we update tx index before checking for 6571adfc5217SJeff Kirsher * netif_tx_queue_stopped(). 6572adfc5217SJeff Kirsher */ 6573adfc5217SJeff Kirsher smp_mb(); 6574adfc5217SJeff Kirsher if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh) 6575adfc5217SJeff Kirsher netif_tx_wake_queue(txq); 6576adfc5217SJeff Kirsher } 6577adfc5217SJeff Kirsher 6578adfc5217SJeff Kirsher return NETDEV_TX_OK; 6579adfc5217SJeff Kirsher dma_error: 6580adfc5217SJeff Kirsher /* save value of frag that failed */ 6581adfc5217SJeff Kirsher last_frag = i; 6582adfc5217SJeff Kirsher 6583adfc5217SJeff Kirsher /* start back at beginning and unmap skb */ 6584adfc5217SJeff Kirsher prod = txr->tx_prod; 6585adfc5217SJeff Kirsher ring_prod = TX_RING_IDX(prod); 6586adfc5217SJeff Kirsher tx_buf = &txr->tx_buf_ring[ring_prod]; 6587adfc5217SJeff Kirsher tx_buf->skb = NULL; 6588adfc5217SJeff Kirsher dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), 6589adfc5217SJeff Kirsher skb_headlen(skb), PCI_DMA_TODEVICE); 6590adfc5217SJeff Kirsher 6591adfc5217SJeff Kirsher /* unmap remaining mapped pages */ 6592adfc5217SJeff Kirsher for (i = 0; i < last_frag; i++) { 6593adfc5217SJeff Kirsher prod = NEXT_TX_BD(prod); 6594adfc5217SJeff Kirsher ring_prod = TX_RING_IDX(prod); 6595adfc5217SJeff Kirsher tx_buf = &txr->tx_buf_ring[ring_prod]; 6596adfc5217SJeff Kirsher dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), 65979e903e08SEric Dumazet skb_frag_size(&skb_shinfo(skb)->frags[i]), 6598adfc5217SJeff Kirsher PCI_DMA_TODEVICE); 6599adfc5217SJeff Kirsher } 6600adfc5217SJeff Kirsher 6601adfc5217SJeff Kirsher dev_kfree_skb(skb); 6602adfc5217SJeff Kirsher return NETDEV_TX_OK; 6603adfc5217SJeff Kirsher } 6604adfc5217SJeff Kirsher 6605adfc5217SJeff Kirsher /* Called with rtnl_lock */ 6606adfc5217SJeff Kirsher static int 6607adfc5217SJeff Kirsher bnx2_close(struct net_device *dev) 6608adfc5217SJeff Kirsher { 6609adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 6610adfc5217SJeff Kirsher 6611adfc5217SJeff Kirsher bnx2_disable_int_sync(bp); 6612adfc5217SJeff Kirsher bnx2_napi_disable(bp); 6613adfc5217SJeff Kirsher del_timer_sync(&bp->timer); 6614adfc5217SJeff Kirsher bnx2_shutdown_chip(bp); 6615adfc5217SJeff Kirsher bnx2_free_irq(bp); 6616adfc5217SJeff Kirsher bnx2_free_skbs(bp); 6617adfc5217SJeff Kirsher bnx2_free_mem(bp); 6618adfc5217SJeff Kirsher bnx2_del_napi(bp); 6619adfc5217SJeff Kirsher bp->link_up = 0; 6620adfc5217SJeff Kirsher netif_carrier_off(bp->dev); 6621adfc5217SJeff Kirsher bnx2_set_power_state(bp, PCI_D3hot); 6622adfc5217SJeff Kirsher return 0; 6623adfc5217SJeff Kirsher } 6624adfc5217SJeff Kirsher 6625adfc5217SJeff Kirsher static void 6626adfc5217SJeff Kirsher bnx2_save_stats(struct bnx2 *bp) 6627adfc5217SJeff Kirsher { 6628adfc5217SJeff Kirsher u32 *hw_stats = (u32 *) bp->stats_blk; 6629adfc5217SJeff Kirsher u32 *temp_stats = (u32 *) bp->temp_stats_blk; 6630adfc5217SJeff Kirsher int i; 6631adfc5217SJeff Kirsher 6632adfc5217SJeff Kirsher /* The 1st 10 counters are 64-bit counters */ 6633adfc5217SJeff Kirsher for (i = 0; i < 20; i += 2) { 6634adfc5217SJeff Kirsher u32 hi; 6635adfc5217SJeff Kirsher u64 lo; 6636adfc5217SJeff Kirsher 6637adfc5217SJeff Kirsher hi = temp_stats[i] + hw_stats[i]; 6638adfc5217SJeff Kirsher lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1]; 6639adfc5217SJeff Kirsher if (lo > 0xffffffff) 6640adfc5217SJeff Kirsher hi++; 6641adfc5217SJeff Kirsher temp_stats[i] = hi; 6642adfc5217SJeff Kirsher temp_stats[i + 1] = lo & 0xffffffff; 6643adfc5217SJeff Kirsher } 6644adfc5217SJeff Kirsher 6645adfc5217SJeff Kirsher for ( ; i < sizeof(struct statistics_block) / 4; i++) 6646adfc5217SJeff Kirsher temp_stats[i] += hw_stats[i]; 6647adfc5217SJeff Kirsher } 6648adfc5217SJeff Kirsher 6649adfc5217SJeff Kirsher #define GET_64BIT_NET_STATS64(ctr) \ 6650adfc5217SJeff Kirsher (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo)) 6651adfc5217SJeff Kirsher 6652adfc5217SJeff Kirsher #define GET_64BIT_NET_STATS(ctr) \ 6653adfc5217SJeff Kirsher GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \ 6654adfc5217SJeff Kirsher GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr) 6655adfc5217SJeff Kirsher 6656adfc5217SJeff Kirsher #define GET_32BIT_NET_STATS(ctr) \ 6657adfc5217SJeff Kirsher (unsigned long) (bp->stats_blk->ctr + \ 6658adfc5217SJeff Kirsher bp->temp_stats_blk->ctr) 6659adfc5217SJeff Kirsher 6660adfc5217SJeff Kirsher static struct rtnl_link_stats64 * 6661adfc5217SJeff Kirsher bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats) 6662adfc5217SJeff Kirsher { 6663adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 6664adfc5217SJeff Kirsher 6665adfc5217SJeff Kirsher if (bp->stats_blk == NULL) 6666adfc5217SJeff Kirsher return net_stats; 6667adfc5217SJeff Kirsher 6668adfc5217SJeff Kirsher net_stats->rx_packets = 6669adfc5217SJeff Kirsher GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) + 6670adfc5217SJeff Kirsher GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) + 6671adfc5217SJeff Kirsher GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts); 6672adfc5217SJeff Kirsher 6673adfc5217SJeff Kirsher net_stats->tx_packets = 6674adfc5217SJeff Kirsher GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) + 6675adfc5217SJeff Kirsher GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) + 6676adfc5217SJeff Kirsher GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts); 6677adfc5217SJeff Kirsher 6678adfc5217SJeff Kirsher net_stats->rx_bytes = 6679adfc5217SJeff Kirsher GET_64BIT_NET_STATS(stat_IfHCInOctets); 6680adfc5217SJeff Kirsher 6681adfc5217SJeff Kirsher net_stats->tx_bytes = 6682adfc5217SJeff Kirsher GET_64BIT_NET_STATS(stat_IfHCOutOctets); 6683adfc5217SJeff Kirsher 6684adfc5217SJeff Kirsher net_stats->multicast = 6685adfc5217SJeff Kirsher GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts); 6686adfc5217SJeff Kirsher 6687adfc5217SJeff Kirsher net_stats->collisions = 6688adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_EtherStatsCollisions); 6689adfc5217SJeff Kirsher 6690adfc5217SJeff Kirsher net_stats->rx_length_errors = 6691adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) + 6692adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts); 6693adfc5217SJeff Kirsher 6694adfc5217SJeff Kirsher net_stats->rx_over_errors = 6695adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_IfInFTQDiscards) + 6696adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_IfInMBUFDiscards); 6697adfc5217SJeff Kirsher 6698adfc5217SJeff Kirsher net_stats->rx_frame_errors = 6699adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors); 6700adfc5217SJeff Kirsher 6701adfc5217SJeff Kirsher net_stats->rx_crc_errors = 6702adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors); 6703adfc5217SJeff Kirsher 6704adfc5217SJeff Kirsher net_stats->rx_errors = net_stats->rx_length_errors + 6705adfc5217SJeff Kirsher net_stats->rx_over_errors + net_stats->rx_frame_errors + 6706adfc5217SJeff Kirsher net_stats->rx_crc_errors; 6707adfc5217SJeff Kirsher 6708adfc5217SJeff Kirsher net_stats->tx_aborted_errors = 6709adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) + 6710adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions); 6711adfc5217SJeff Kirsher 6712adfc5217SJeff Kirsher if ((CHIP_NUM(bp) == CHIP_NUM_5706) || 6713adfc5217SJeff Kirsher (CHIP_ID(bp) == CHIP_ID_5708_A0)) 6714adfc5217SJeff Kirsher net_stats->tx_carrier_errors = 0; 6715adfc5217SJeff Kirsher else { 6716adfc5217SJeff Kirsher net_stats->tx_carrier_errors = 6717adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors); 6718adfc5217SJeff Kirsher } 6719adfc5217SJeff Kirsher 6720adfc5217SJeff Kirsher net_stats->tx_errors = 6721adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) + 6722adfc5217SJeff Kirsher net_stats->tx_aborted_errors + 6723adfc5217SJeff Kirsher net_stats->tx_carrier_errors; 6724adfc5217SJeff Kirsher 6725adfc5217SJeff Kirsher net_stats->rx_missed_errors = 6726adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_IfInFTQDiscards) + 6727adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) + 6728adfc5217SJeff Kirsher GET_32BIT_NET_STATS(stat_FwRxDrop); 6729adfc5217SJeff Kirsher 6730adfc5217SJeff Kirsher return net_stats; 6731adfc5217SJeff Kirsher } 6732adfc5217SJeff Kirsher 6733adfc5217SJeff Kirsher /* All ethtool functions called with rtnl_lock */ 6734adfc5217SJeff Kirsher 6735adfc5217SJeff Kirsher static int 6736adfc5217SJeff Kirsher bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 6737adfc5217SJeff Kirsher { 6738adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 6739adfc5217SJeff Kirsher int support_serdes = 0, support_copper = 0; 6740adfc5217SJeff Kirsher 6741adfc5217SJeff Kirsher cmd->supported = SUPPORTED_Autoneg; 6742adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 6743adfc5217SJeff Kirsher support_serdes = 1; 6744adfc5217SJeff Kirsher support_copper = 1; 6745adfc5217SJeff Kirsher } else if (bp->phy_port == PORT_FIBRE) 6746adfc5217SJeff Kirsher support_serdes = 1; 6747adfc5217SJeff Kirsher else 6748adfc5217SJeff Kirsher support_copper = 1; 6749adfc5217SJeff Kirsher 6750adfc5217SJeff Kirsher if (support_serdes) { 6751adfc5217SJeff Kirsher cmd->supported |= SUPPORTED_1000baseT_Full | 6752adfc5217SJeff Kirsher SUPPORTED_FIBRE; 6753adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) 6754adfc5217SJeff Kirsher cmd->supported |= SUPPORTED_2500baseX_Full; 6755adfc5217SJeff Kirsher 6756adfc5217SJeff Kirsher } 6757adfc5217SJeff Kirsher if (support_copper) { 6758adfc5217SJeff Kirsher cmd->supported |= SUPPORTED_10baseT_Half | 6759adfc5217SJeff Kirsher SUPPORTED_10baseT_Full | 6760adfc5217SJeff Kirsher SUPPORTED_100baseT_Half | 6761adfc5217SJeff Kirsher SUPPORTED_100baseT_Full | 6762adfc5217SJeff Kirsher SUPPORTED_1000baseT_Full | 6763adfc5217SJeff Kirsher SUPPORTED_TP; 6764adfc5217SJeff Kirsher 6765adfc5217SJeff Kirsher } 6766adfc5217SJeff Kirsher 6767adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 6768adfc5217SJeff Kirsher cmd->port = bp->phy_port; 6769adfc5217SJeff Kirsher cmd->advertising = bp->advertising; 6770adfc5217SJeff Kirsher 6771adfc5217SJeff Kirsher if (bp->autoneg & AUTONEG_SPEED) { 6772adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_ENABLE; 6773adfc5217SJeff Kirsher } else { 6774adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_DISABLE; 6775adfc5217SJeff Kirsher } 6776adfc5217SJeff Kirsher 6777adfc5217SJeff Kirsher if (netif_carrier_ok(dev)) { 6778adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bp->line_speed); 6779adfc5217SJeff Kirsher cmd->duplex = bp->duplex; 6780adfc5217SJeff Kirsher } 6781adfc5217SJeff Kirsher else { 6782adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, -1); 6783adfc5217SJeff Kirsher cmd->duplex = -1; 6784adfc5217SJeff Kirsher } 6785adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 6786adfc5217SJeff Kirsher 6787adfc5217SJeff Kirsher cmd->transceiver = XCVR_INTERNAL; 6788adfc5217SJeff Kirsher cmd->phy_address = bp->phy_addr; 6789adfc5217SJeff Kirsher 6790adfc5217SJeff Kirsher return 0; 6791adfc5217SJeff Kirsher } 6792adfc5217SJeff Kirsher 6793adfc5217SJeff Kirsher static int 6794adfc5217SJeff Kirsher bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 6795adfc5217SJeff Kirsher { 6796adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 6797adfc5217SJeff Kirsher u8 autoneg = bp->autoneg; 6798adfc5217SJeff Kirsher u8 req_duplex = bp->req_duplex; 6799adfc5217SJeff Kirsher u16 req_line_speed = bp->req_line_speed; 6800adfc5217SJeff Kirsher u32 advertising = bp->advertising; 6801adfc5217SJeff Kirsher int err = -EINVAL; 6802adfc5217SJeff Kirsher 6803adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 6804adfc5217SJeff Kirsher 6805adfc5217SJeff Kirsher if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE) 6806adfc5217SJeff Kirsher goto err_out_unlock; 6807adfc5217SJeff Kirsher 6808adfc5217SJeff Kirsher if (cmd->port != bp->phy_port && 6809adfc5217SJeff Kirsher !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)) 6810adfc5217SJeff Kirsher goto err_out_unlock; 6811adfc5217SJeff Kirsher 6812adfc5217SJeff Kirsher /* If device is down, we can store the settings only if the user 6813adfc5217SJeff Kirsher * is setting the currently active port. 6814adfc5217SJeff Kirsher */ 6815adfc5217SJeff Kirsher if (!netif_running(dev) && cmd->port != bp->phy_port) 6816adfc5217SJeff Kirsher goto err_out_unlock; 6817adfc5217SJeff Kirsher 6818adfc5217SJeff Kirsher if (cmd->autoneg == AUTONEG_ENABLE) { 6819adfc5217SJeff Kirsher autoneg |= AUTONEG_SPEED; 6820adfc5217SJeff Kirsher 6821adfc5217SJeff Kirsher advertising = cmd->advertising; 6822adfc5217SJeff Kirsher if (cmd->port == PORT_TP) { 6823adfc5217SJeff Kirsher advertising &= ETHTOOL_ALL_COPPER_SPEED; 6824adfc5217SJeff Kirsher if (!advertising) 6825adfc5217SJeff Kirsher advertising = ETHTOOL_ALL_COPPER_SPEED; 6826adfc5217SJeff Kirsher } else { 6827adfc5217SJeff Kirsher advertising &= ETHTOOL_ALL_FIBRE_SPEED; 6828adfc5217SJeff Kirsher if (!advertising) 6829adfc5217SJeff Kirsher advertising = ETHTOOL_ALL_FIBRE_SPEED; 6830adfc5217SJeff Kirsher } 6831adfc5217SJeff Kirsher advertising |= ADVERTISED_Autoneg; 6832adfc5217SJeff Kirsher } 6833adfc5217SJeff Kirsher else { 6834adfc5217SJeff Kirsher u32 speed = ethtool_cmd_speed(cmd); 6835adfc5217SJeff Kirsher if (cmd->port == PORT_FIBRE) { 6836adfc5217SJeff Kirsher if ((speed != SPEED_1000 && 6837adfc5217SJeff Kirsher speed != SPEED_2500) || 6838adfc5217SJeff Kirsher (cmd->duplex != DUPLEX_FULL)) 6839adfc5217SJeff Kirsher goto err_out_unlock; 6840adfc5217SJeff Kirsher 6841adfc5217SJeff Kirsher if (speed == SPEED_2500 && 6842adfc5217SJeff Kirsher !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 6843adfc5217SJeff Kirsher goto err_out_unlock; 6844adfc5217SJeff Kirsher } else if (speed == SPEED_1000 || speed == SPEED_2500) 6845adfc5217SJeff Kirsher goto err_out_unlock; 6846adfc5217SJeff Kirsher 6847adfc5217SJeff Kirsher autoneg &= ~AUTONEG_SPEED; 6848adfc5217SJeff Kirsher req_line_speed = speed; 6849adfc5217SJeff Kirsher req_duplex = cmd->duplex; 6850adfc5217SJeff Kirsher advertising = 0; 6851adfc5217SJeff Kirsher } 6852adfc5217SJeff Kirsher 6853adfc5217SJeff Kirsher bp->autoneg = autoneg; 6854adfc5217SJeff Kirsher bp->advertising = advertising; 6855adfc5217SJeff Kirsher bp->req_line_speed = req_line_speed; 6856adfc5217SJeff Kirsher bp->req_duplex = req_duplex; 6857adfc5217SJeff Kirsher 6858adfc5217SJeff Kirsher err = 0; 6859adfc5217SJeff Kirsher /* If device is down, the new settings will be picked up when it is 6860adfc5217SJeff Kirsher * brought up. 6861adfc5217SJeff Kirsher */ 6862adfc5217SJeff Kirsher if (netif_running(dev)) 6863adfc5217SJeff Kirsher err = bnx2_setup_phy(bp, cmd->port); 6864adfc5217SJeff Kirsher 6865adfc5217SJeff Kirsher err_out_unlock: 6866adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 6867adfc5217SJeff Kirsher 6868adfc5217SJeff Kirsher return err; 6869adfc5217SJeff Kirsher } 6870adfc5217SJeff Kirsher 6871adfc5217SJeff Kirsher static void 6872adfc5217SJeff Kirsher bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 6873adfc5217SJeff Kirsher { 6874adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 6875adfc5217SJeff Kirsher 687668aad78cSRick Jones strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 687768aad78cSRick Jones strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 687868aad78cSRick Jones strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 687968aad78cSRick Jones strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version)); 6880adfc5217SJeff Kirsher } 6881adfc5217SJeff Kirsher 6882adfc5217SJeff Kirsher #define BNX2_REGDUMP_LEN (32 * 1024) 6883adfc5217SJeff Kirsher 6884adfc5217SJeff Kirsher static int 6885adfc5217SJeff Kirsher bnx2_get_regs_len(struct net_device *dev) 6886adfc5217SJeff Kirsher { 6887adfc5217SJeff Kirsher return BNX2_REGDUMP_LEN; 6888adfc5217SJeff Kirsher } 6889adfc5217SJeff Kirsher 6890adfc5217SJeff Kirsher static void 6891adfc5217SJeff Kirsher bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p) 6892adfc5217SJeff Kirsher { 6893adfc5217SJeff Kirsher u32 *p = _p, i, offset; 6894adfc5217SJeff Kirsher u8 *orig_p = _p; 6895adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 6896adfc5217SJeff Kirsher static const u32 reg_boundaries[] = { 6897adfc5217SJeff Kirsher 0x0000, 0x0098, 0x0400, 0x045c, 6898adfc5217SJeff Kirsher 0x0800, 0x0880, 0x0c00, 0x0c10, 6899adfc5217SJeff Kirsher 0x0c30, 0x0d08, 0x1000, 0x101c, 6900adfc5217SJeff Kirsher 0x1040, 0x1048, 0x1080, 0x10a4, 6901adfc5217SJeff Kirsher 0x1400, 0x1490, 0x1498, 0x14f0, 6902adfc5217SJeff Kirsher 0x1500, 0x155c, 0x1580, 0x15dc, 6903adfc5217SJeff Kirsher 0x1600, 0x1658, 0x1680, 0x16d8, 6904adfc5217SJeff Kirsher 0x1800, 0x1820, 0x1840, 0x1854, 6905adfc5217SJeff Kirsher 0x1880, 0x1894, 0x1900, 0x1984, 6906adfc5217SJeff Kirsher 0x1c00, 0x1c0c, 0x1c40, 0x1c54, 6907adfc5217SJeff Kirsher 0x1c80, 0x1c94, 0x1d00, 0x1d84, 6908adfc5217SJeff Kirsher 0x2000, 0x2030, 0x23c0, 0x2400, 6909adfc5217SJeff Kirsher 0x2800, 0x2820, 0x2830, 0x2850, 6910adfc5217SJeff Kirsher 0x2b40, 0x2c10, 0x2fc0, 0x3058, 6911adfc5217SJeff Kirsher 0x3c00, 0x3c94, 0x4000, 0x4010, 6912adfc5217SJeff Kirsher 0x4080, 0x4090, 0x43c0, 0x4458, 6913adfc5217SJeff Kirsher 0x4c00, 0x4c18, 0x4c40, 0x4c54, 6914adfc5217SJeff Kirsher 0x4fc0, 0x5010, 0x53c0, 0x5444, 6915adfc5217SJeff Kirsher 0x5c00, 0x5c18, 0x5c80, 0x5c90, 6916adfc5217SJeff Kirsher 0x5fc0, 0x6000, 0x6400, 0x6428, 6917adfc5217SJeff Kirsher 0x6800, 0x6848, 0x684c, 0x6860, 6918adfc5217SJeff Kirsher 0x6888, 0x6910, 0x8000 6919adfc5217SJeff Kirsher }; 6920adfc5217SJeff Kirsher 6921adfc5217SJeff Kirsher regs->version = 0; 6922adfc5217SJeff Kirsher 6923adfc5217SJeff Kirsher memset(p, 0, BNX2_REGDUMP_LEN); 6924adfc5217SJeff Kirsher 6925adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 6926adfc5217SJeff Kirsher return; 6927adfc5217SJeff Kirsher 6928adfc5217SJeff Kirsher i = 0; 6929adfc5217SJeff Kirsher offset = reg_boundaries[0]; 6930adfc5217SJeff Kirsher p += offset; 6931adfc5217SJeff Kirsher while (offset < BNX2_REGDUMP_LEN) { 6932adfc5217SJeff Kirsher *p++ = REG_RD(bp, offset); 6933adfc5217SJeff Kirsher offset += 4; 6934adfc5217SJeff Kirsher if (offset == reg_boundaries[i + 1]) { 6935adfc5217SJeff Kirsher offset = reg_boundaries[i + 2]; 6936adfc5217SJeff Kirsher p = (u32 *) (orig_p + offset); 6937adfc5217SJeff Kirsher i += 2; 6938adfc5217SJeff Kirsher } 6939adfc5217SJeff Kirsher } 6940adfc5217SJeff Kirsher } 6941adfc5217SJeff Kirsher 6942adfc5217SJeff Kirsher static void 6943adfc5217SJeff Kirsher bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 6944adfc5217SJeff Kirsher { 6945adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 6946adfc5217SJeff Kirsher 6947adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_NO_WOL) { 6948adfc5217SJeff Kirsher wol->supported = 0; 6949adfc5217SJeff Kirsher wol->wolopts = 0; 6950adfc5217SJeff Kirsher } 6951adfc5217SJeff Kirsher else { 6952adfc5217SJeff Kirsher wol->supported = WAKE_MAGIC; 6953adfc5217SJeff Kirsher if (bp->wol) 6954adfc5217SJeff Kirsher wol->wolopts = WAKE_MAGIC; 6955adfc5217SJeff Kirsher else 6956adfc5217SJeff Kirsher wol->wolopts = 0; 6957adfc5217SJeff Kirsher } 6958adfc5217SJeff Kirsher memset(&wol->sopass, 0, sizeof(wol->sopass)); 6959adfc5217SJeff Kirsher } 6960adfc5217SJeff Kirsher 6961adfc5217SJeff Kirsher static int 6962adfc5217SJeff Kirsher bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 6963adfc5217SJeff Kirsher { 6964adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 6965adfc5217SJeff Kirsher 6966adfc5217SJeff Kirsher if (wol->wolopts & ~WAKE_MAGIC) 6967adfc5217SJeff Kirsher return -EINVAL; 6968adfc5217SJeff Kirsher 6969adfc5217SJeff Kirsher if (wol->wolopts & WAKE_MAGIC) { 6970adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_NO_WOL) 6971adfc5217SJeff Kirsher return -EINVAL; 6972adfc5217SJeff Kirsher 6973adfc5217SJeff Kirsher bp->wol = 1; 6974adfc5217SJeff Kirsher } 6975adfc5217SJeff Kirsher else { 6976adfc5217SJeff Kirsher bp->wol = 0; 6977adfc5217SJeff Kirsher } 6978adfc5217SJeff Kirsher return 0; 6979adfc5217SJeff Kirsher } 6980adfc5217SJeff Kirsher 6981adfc5217SJeff Kirsher static int 6982adfc5217SJeff Kirsher bnx2_nway_reset(struct net_device *dev) 6983adfc5217SJeff Kirsher { 6984adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 6985adfc5217SJeff Kirsher u32 bmcr; 6986adfc5217SJeff Kirsher 6987adfc5217SJeff Kirsher if (!netif_running(dev)) 6988adfc5217SJeff Kirsher return -EAGAIN; 6989adfc5217SJeff Kirsher 6990adfc5217SJeff Kirsher if (!(bp->autoneg & AUTONEG_SPEED)) { 6991adfc5217SJeff Kirsher return -EINVAL; 6992adfc5217SJeff Kirsher } 6993adfc5217SJeff Kirsher 6994adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 6995adfc5217SJeff Kirsher 6996adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 6997adfc5217SJeff Kirsher int rc; 6998adfc5217SJeff Kirsher 6999adfc5217SJeff Kirsher rc = bnx2_setup_remote_phy(bp, bp->phy_port); 7000adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 7001adfc5217SJeff Kirsher return rc; 7002adfc5217SJeff Kirsher } 7003adfc5217SJeff Kirsher 7004adfc5217SJeff Kirsher /* Force a link down visible on the other side */ 7005adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 7006adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); 7007adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 7008adfc5217SJeff Kirsher 7009adfc5217SJeff Kirsher msleep(20); 7010adfc5217SJeff Kirsher 7011adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 7012adfc5217SJeff Kirsher 7013adfc5217SJeff Kirsher bp->current_interval = BNX2_SERDES_AN_TIMEOUT; 7014adfc5217SJeff Kirsher bp->serdes_an_pending = 1; 7015adfc5217SJeff Kirsher mod_timer(&bp->timer, jiffies + bp->current_interval); 7016adfc5217SJeff Kirsher } 7017adfc5217SJeff Kirsher 7018adfc5217SJeff Kirsher bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 7019adfc5217SJeff Kirsher bmcr &= ~BMCR_LOOPBACK; 7020adfc5217SJeff Kirsher bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); 7021adfc5217SJeff Kirsher 7022adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 7023adfc5217SJeff Kirsher 7024adfc5217SJeff Kirsher return 0; 7025adfc5217SJeff Kirsher } 7026adfc5217SJeff Kirsher 7027adfc5217SJeff Kirsher static u32 7028adfc5217SJeff Kirsher bnx2_get_link(struct net_device *dev) 7029adfc5217SJeff Kirsher { 7030adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7031adfc5217SJeff Kirsher 7032adfc5217SJeff Kirsher return bp->link_up; 7033adfc5217SJeff Kirsher } 7034adfc5217SJeff Kirsher 7035adfc5217SJeff Kirsher static int 7036adfc5217SJeff Kirsher bnx2_get_eeprom_len(struct net_device *dev) 7037adfc5217SJeff Kirsher { 7038adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7039adfc5217SJeff Kirsher 7040adfc5217SJeff Kirsher if (bp->flash_info == NULL) 7041adfc5217SJeff Kirsher return 0; 7042adfc5217SJeff Kirsher 7043adfc5217SJeff Kirsher return (int) bp->flash_size; 7044adfc5217SJeff Kirsher } 7045adfc5217SJeff Kirsher 7046adfc5217SJeff Kirsher static int 7047adfc5217SJeff Kirsher bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 7048adfc5217SJeff Kirsher u8 *eebuf) 7049adfc5217SJeff Kirsher { 7050adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7051adfc5217SJeff Kirsher int rc; 7052adfc5217SJeff Kirsher 7053adfc5217SJeff Kirsher if (!netif_running(dev)) 7054adfc5217SJeff Kirsher return -EAGAIN; 7055adfc5217SJeff Kirsher 7056adfc5217SJeff Kirsher /* parameters already validated in ethtool_get_eeprom */ 7057adfc5217SJeff Kirsher 7058adfc5217SJeff Kirsher rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 7059adfc5217SJeff Kirsher 7060adfc5217SJeff Kirsher return rc; 7061adfc5217SJeff Kirsher } 7062adfc5217SJeff Kirsher 7063adfc5217SJeff Kirsher static int 7064adfc5217SJeff Kirsher bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 7065adfc5217SJeff Kirsher u8 *eebuf) 7066adfc5217SJeff Kirsher { 7067adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7068adfc5217SJeff Kirsher int rc; 7069adfc5217SJeff Kirsher 7070adfc5217SJeff Kirsher if (!netif_running(dev)) 7071adfc5217SJeff Kirsher return -EAGAIN; 7072adfc5217SJeff Kirsher 7073adfc5217SJeff Kirsher /* parameters already validated in ethtool_set_eeprom */ 7074adfc5217SJeff Kirsher 7075adfc5217SJeff Kirsher rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 7076adfc5217SJeff Kirsher 7077adfc5217SJeff Kirsher return rc; 7078adfc5217SJeff Kirsher } 7079adfc5217SJeff Kirsher 7080adfc5217SJeff Kirsher static int 7081adfc5217SJeff Kirsher bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) 7082adfc5217SJeff Kirsher { 7083adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7084adfc5217SJeff Kirsher 7085adfc5217SJeff Kirsher memset(coal, 0, sizeof(struct ethtool_coalesce)); 7086adfc5217SJeff Kirsher 7087adfc5217SJeff Kirsher coal->rx_coalesce_usecs = bp->rx_ticks; 7088adfc5217SJeff Kirsher coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip; 7089adfc5217SJeff Kirsher coal->rx_coalesce_usecs_irq = bp->rx_ticks_int; 7090adfc5217SJeff Kirsher coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int; 7091adfc5217SJeff Kirsher 7092adfc5217SJeff Kirsher coal->tx_coalesce_usecs = bp->tx_ticks; 7093adfc5217SJeff Kirsher coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip; 7094adfc5217SJeff Kirsher coal->tx_coalesce_usecs_irq = bp->tx_ticks_int; 7095adfc5217SJeff Kirsher coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int; 7096adfc5217SJeff Kirsher 7097adfc5217SJeff Kirsher coal->stats_block_coalesce_usecs = bp->stats_ticks; 7098adfc5217SJeff Kirsher 7099adfc5217SJeff Kirsher return 0; 7100adfc5217SJeff Kirsher } 7101adfc5217SJeff Kirsher 7102adfc5217SJeff Kirsher static int 7103adfc5217SJeff Kirsher bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) 7104adfc5217SJeff Kirsher { 7105adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7106adfc5217SJeff Kirsher 7107adfc5217SJeff Kirsher bp->rx_ticks = (u16) coal->rx_coalesce_usecs; 7108adfc5217SJeff Kirsher if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; 7109adfc5217SJeff Kirsher 7110adfc5217SJeff Kirsher bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; 7111adfc5217SJeff Kirsher if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; 7112adfc5217SJeff Kirsher 7113adfc5217SJeff Kirsher bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; 7114adfc5217SJeff Kirsher if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; 7115adfc5217SJeff Kirsher 7116adfc5217SJeff Kirsher bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq; 7117adfc5217SJeff Kirsher if (bp->rx_quick_cons_trip_int > 0xff) 7118adfc5217SJeff Kirsher bp->rx_quick_cons_trip_int = 0xff; 7119adfc5217SJeff Kirsher 7120adfc5217SJeff Kirsher bp->tx_ticks = (u16) coal->tx_coalesce_usecs; 7121adfc5217SJeff Kirsher if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; 7122adfc5217SJeff Kirsher 7123adfc5217SJeff Kirsher bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames; 7124adfc5217SJeff Kirsher if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; 7125adfc5217SJeff Kirsher 7126adfc5217SJeff Kirsher bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq; 7127adfc5217SJeff Kirsher if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; 7128adfc5217SJeff Kirsher 7129adfc5217SJeff Kirsher bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq; 7130adfc5217SJeff Kirsher if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = 7131adfc5217SJeff Kirsher 0xff; 7132adfc5217SJeff Kirsher 7133adfc5217SJeff Kirsher bp->stats_ticks = coal->stats_block_coalesce_usecs; 7134adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_BROKEN_STATS) { 7135adfc5217SJeff Kirsher if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC) 7136adfc5217SJeff Kirsher bp->stats_ticks = USEC_PER_SEC; 7137adfc5217SJeff Kirsher } 7138adfc5217SJeff Kirsher if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS) 7139adfc5217SJeff Kirsher bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS; 7140adfc5217SJeff Kirsher bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS; 7141adfc5217SJeff Kirsher 7142adfc5217SJeff Kirsher if (netif_running(bp->dev)) { 7143adfc5217SJeff Kirsher bnx2_netif_stop(bp, true); 7144adfc5217SJeff Kirsher bnx2_init_nic(bp, 0); 7145adfc5217SJeff Kirsher bnx2_netif_start(bp, true); 7146adfc5217SJeff Kirsher } 7147adfc5217SJeff Kirsher 7148adfc5217SJeff Kirsher return 0; 7149adfc5217SJeff Kirsher } 7150adfc5217SJeff Kirsher 7151adfc5217SJeff Kirsher static void 7152adfc5217SJeff Kirsher bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) 7153adfc5217SJeff Kirsher { 7154adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7155adfc5217SJeff Kirsher 7156adfc5217SJeff Kirsher ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT; 7157adfc5217SJeff Kirsher ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT; 7158adfc5217SJeff Kirsher 7159adfc5217SJeff Kirsher ering->rx_pending = bp->rx_ring_size; 7160adfc5217SJeff Kirsher ering->rx_jumbo_pending = bp->rx_pg_ring_size; 7161adfc5217SJeff Kirsher 7162adfc5217SJeff Kirsher ering->tx_max_pending = MAX_TX_DESC_CNT; 7163adfc5217SJeff Kirsher ering->tx_pending = bp->tx_ring_size; 7164adfc5217SJeff Kirsher } 7165adfc5217SJeff Kirsher 7166adfc5217SJeff Kirsher static int 7167adfc5217SJeff Kirsher bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx) 7168adfc5217SJeff Kirsher { 7169adfc5217SJeff Kirsher if (netif_running(bp->dev)) { 7170adfc5217SJeff Kirsher /* Reset will erase chipset stats; save them */ 7171adfc5217SJeff Kirsher bnx2_save_stats(bp); 7172adfc5217SJeff Kirsher 7173adfc5217SJeff Kirsher bnx2_netif_stop(bp, true); 7174adfc5217SJeff Kirsher bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); 7175adfc5217SJeff Kirsher __bnx2_free_irq(bp); 7176adfc5217SJeff Kirsher bnx2_free_skbs(bp); 7177adfc5217SJeff Kirsher bnx2_free_mem(bp); 7178adfc5217SJeff Kirsher } 7179adfc5217SJeff Kirsher 7180adfc5217SJeff Kirsher bnx2_set_rx_ring_size(bp, rx); 7181adfc5217SJeff Kirsher bp->tx_ring_size = tx; 7182adfc5217SJeff Kirsher 7183adfc5217SJeff Kirsher if (netif_running(bp->dev)) { 7184adfc5217SJeff Kirsher int rc; 7185adfc5217SJeff Kirsher 7186adfc5217SJeff Kirsher rc = bnx2_alloc_mem(bp); 7187adfc5217SJeff Kirsher if (!rc) 7188adfc5217SJeff Kirsher rc = bnx2_request_irq(bp); 7189adfc5217SJeff Kirsher 7190adfc5217SJeff Kirsher if (!rc) 7191adfc5217SJeff Kirsher rc = bnx2_init_nic(bp, 0); 7192adfc5217SJeff Kirsher 7193adfc5217SJeff Kirsher if (rc) { 7194adfc5217SJeff Kirsher bnx2_napi_enable(bp); 7195adfc5217SJeff Kirsher dev_close(bp->dev); 7196adfc5217SJeff Kirsher return rc; 7197adfc5217SJeff Kirsher } 7198adfc5217SJeff Kirsher #ifdef BCM_CNIC 7199adfc5217SJeff Kirsher mutex_lock(&bp->cnic_lock); 7200adfc5217SJeff Kirsher /* Let cnic know about the new status block. */ 7201adfc5217SJeff Kirsher if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD) 7202adfc5217SJeff Kirsher bnx2_setup_cnic_irq_info(bp); 7203adfc5217SJeff Kirsher mutex_unlock(&bp->cnic_lock); 7204adfc5217SJeff Kirsher #endif 7205adfc5217SJeff Kirsher bnx2_netif_start(bp, true); 7206adfc5217SJeff Kirsher } 7207adfc5217SJeff Kirsher return 0; 7208adfc5217SJeff Kirsher } 7209adfc5217SJeff Kirsher 7210adfc5217SJeff Kirsher static int 7211adfc5217SJeff Kirsher bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) 7212adfc5217SJeff Kirsher { 7213adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7214adfc5217SJeff Kirsher int rc; 7215adfc5217SJeff Kirsher 7216adfc5217SJeff Kirsher if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) || 7217adfc5217SJeff Kirsher (ering->tx_pending > MAX_TX_DESC_CNT) || 7218adfc5217SJeff Kirsher (ering->tx_pending <= MAX_SKB_FRAGS)) { 7219adfc5217SJeff Kirsher 7220adfc5217SJeff Kirsher return -EINVAL; 7221adfc5217SJeff Kirsher } 7222adfc5217SJeff Kirsher rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending); 7223adfc5217SJeff Kirsher return rc; 7224adfc5217SJeff Kirsher } 7225adfc5217SJeff Kirsher 7226adfc5217SJeff Kirsher static void 7227adfc5217SJeff Kirsher bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 7228adfc5217SJeff Kirsher { 7229adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7230adfc5217SJeff Kirsher 7231adfc5217SJeff Kirsher epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); 7232adfc5217SJeff Kirsher epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); 7233adfc5217SJeff Kirsher epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); 7234adfc5217SJeff Kirsher } 7235adfc5217SJeff Kirsher 7236adfc5217SJeff Kirsher static int 7237adfc5217SJeff Kirsher bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 7238adfc5217SJeff Kirsher { 7239adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7240adfc5217SJeff Kirsher 7241adfc5217SJeff Kirsher bp->req_flow_ctrl = 0; 7242adfc5217SJeff Kirsher if (epause->rx_pause) 7243adfc5217SJeff Kirsher bp->req_flow_ctrl |= FLOW_CTRL_RX; 7244adfc5217SJeff Kirsher if (epause->tx_pause) 7245adfc5217SJeff Kirsher bp->req_flow_ctrl |= FLOW_CTRL_TX; 7246adfc5217SJeff Kirsher 7247adfc5217SJeff Kirsher if (epause->autoneg) { 7248adfc5217SJeff Kirsher bp->autoneg |= AUTONEG_FLOW_CTRL; 7249adfc5217SJeff Kirsher } 7250adfc5217SJeff Kirsher else { 7251adfc5217SJeff Kirsher bp->autoneg &= ~AUTONEG_FLOW_CTRL; 7252adfc5217SJeff Kirsher } 7253adfc5217SJeff Kirsher 7254adfc5217SJeff Kirsher if (netif_running(dev)) { 7255adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 7256adfc5217SJeff Kirsher bnx2_setup_phy(bp, bp->phy_port); 7257adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 7258adfc5217SJeff Kirsher } 7259adfc5217SJeff Kirsher 7260adfc5217SJeff Kirsher return 0; 7261adfc5217SJeff Kirsher } 7262adfc5217SJeff Kirsher 7263adfc5217SJeff Kirsher static struct { 7264adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 7265adfc5217SJeff Kirsher } bnx2_stats_str_arr[] = { 7266adfc5217SJeff Kirsher { "rx_bytes" }, 7267adfc5217SJeff Kirsher { "rx_error_bytes" }, 7268adfc5217SJeff Kirsher { "tx_bytes" }, 7269adfc5217SJeff Kirsher { "tx_error_bytes" }, 7270adfc5217SJeff Kirsher { "rx_ucast_packets" }, 7271adfc5217SJeff Kirsher { "rx_mcast_packets" }, 7272adfc5217SJeff Kirsher { "rx_bcast_packets" }, 7273adfc5217SJeff Kirsher { "tx_ucast_packets" }, 7274adfc5217SJeff Kirsher { "tx_mcast_packets" }, 7275adfc5217SJeff Kirsher { "tx_bcast_packets" }, 7276adfc5217SJeff Kirsher { "tx_mac_errors" }, 7277adfc5217SJeff Kirsher { "tx_carrier_errors" }, 7278adfc5217SJeff Kirsher { "rx_crc_errors" }, 7279adfc5217SJeff Kirsher { "rx_align_errors" }, 7280adfc5217SJeff Kirsher { "tx_single_collisions" }, 7281adfc5217SJeff Kirsher { "tx_multi_collisions" }, 7282adfc5217SJeff Kirsher { "tx_deferred" }, 7283adfc5217SJeff Kirsher { "tx_excess_collisions" }, 7284adfc5217SJeff Kirsher { "tx_late_collisions" }, 7285adfc5217SJeff Kirsher { "tx_total_collisions" }, 7286adfc5217SJeff Kirsher { "rx_fragments" }, 7287adfc5217SJeff Kirsher { "rx_jabbers" }, 7288adfc5217SJeff Kirsher { "rx_undersize_packets" }, 7289adfc5217SJeff Kirsher { "rx_oversize_packets" }, 7290adfc5217SJeff Kirsher { "rx_64_byte_packets" }, 7291adfc5217SJeff Kirsher { "rx_65_to_127_byte_packets" }, 7292adfc5217SJeff Kirsher { "rx_128_to_255_byte_packets" }, 7293adfc5217SJeff Kirsher { "rx_256_to_511_byte_packets" }, 7294adfc5217SJeff Kirsher { "rx_512_to_1023_byte_packets" }, 7295adfc5217SJeff Kirsher { "rx_1024_to_1522_byte_packets" }, 7296adfc5217SJeff Kirsher { "rx_1523_to_9022_byte_packets" }, 7297adfc5217SJeff Kirsher { "tx_64_byte_packets" }, 7298adfc5217SJeff Kirsher { "tx_65_to_127_byte_packets" }, 7299adfc5217SJeff Kirsher { "tx_128_to_255_byte_packets" }, 7300adfc5217SJeff Kirsher { "tx_256_to_511_byte_packets" }, 7301adfc5217SJeff Kirsher { "tx_512_to_1023_byte_packets" }, 7302adfc5217SJeff Kirsher { "tx_1024_to_1522_byte_packets" }, 7303adfc5217SJeff Kirsher { "tx_1523_to_9022_byte_packets" }, 7304adfc5217SJeff Kirsher { "rx_xon_frames" }, 7305adfc5217SJeff Kirsher { "rx_xoff_frames" }, 7306adfc5217SJeff Kirsher { "tx_xon_frames" }, 7307adfc5217SJeff Kirsher { "tx_xoff_frames" }, 7308adfc5217SJeff Kirsher { "rx_mac_ctrl_frames" }, 7309adfc5217SJeff Kirsher { "rx_filtered_packets" }, 7310adfc5217SJeff Kirsher { "rx_ftq_discards" }, 7311adfc5217SJeff Kirsher { "rx_discards" }, 7312adfc5217SJeff Kirsher { "rx_fw_discards" }, 7313adfc5217SJeff Kirsher }; 7314adfc5217SJeff Kirsher 7315adfc5217SJeff Kirsher #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\ 7316adfc5217SJeff Kirsher sizeof(bnx2_stats_str_arr[0])) 7317adfc5217SJeff Kirsher 7318adfc5217SJeff Kirsher #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4) 7319adfc5217SJeff Kirsher 7320adfc5217SJeff Kirsher static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = { 7321adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfHCInOctets_hi), 7322adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfHCInBadOctets_hi), 7323adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfHCOutOctets_hi), 7324adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfHCOutBadOctets_hi), 7325adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfHCInUcastPkts_hi), 7326adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfHCInMulticastPkts_hi), 7327adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi), 7328adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfHCOutUcastPkts_hi), 7329adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi), 7330adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi), 7331adfc5217SJeff Kirsher STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors), 7332adfc5217SJeff Kirsher STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), 7333adfc5217SJeff Kirsher STATS_OFFSET32(stat_Dot3StatsFCSErrors), 7334adfc5217SJeff Kirsher STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), 7335adfc5217SJeff Kirsher STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), 7336adfc5217SJeff Kirsher STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), 7337adfc5217SJeff Kirsher STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), 7338adfc5217SJeff Kirsher STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), 7339adfc5217SJeff Kirsher STATS_OFFSET32(stat_Dot3StatsLateCollisions), 7340adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsCollisions), 7341adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsFragments), 7342adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsJabbers), 7343adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsUndersizePkts), 7344adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsOverrsizePkts), 7345adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), 7346adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), 7347adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), 7348adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), 7349adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), 7350adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), 7351adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), 7352adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), 7353adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), 7354adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), 7355adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), 7356adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), 7357adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), 7358adfc5217SJeff Kirsher STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), 7359adfc5217SJeff Kirsher STATS_OFFSET32(stat_XonPauseFramesReceived), 7360adfc5217SJeff Kirsher STATS_OFFSET32(stat_XoffPauseFramesReceived), 7361adfc5217SJeff Kirsher STATS_OFFSET32(stat_OutXonSent), 7362adfc5217SJeff Kirsher STATS_OFFSET32(stat_OutXoffSent), 7363adfc5217SJeff Kirsher STATS_OFFSET32(stat_MacControlFramesReceived), 7364adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), 7365adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfInFTQDiscards), 7366adfc5217SJeff Kirsher STATS_OFFSET32(stat_IfInMBUFDiscards), 7367adfc5217SJeff Kirsher STATS_OFFSET32(stat_FwRxDrop), 7368adfc5217SJeff Kirsher }; 7369adfc5217SJeff Kirsher 7370adfc5217SJeff Kirsher /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are 7371adfc5217SJeff Kirsher * skipped because of errata. 7372adfc5217SJeff Kirsher */ 7373adfc5217SJeff Kirsher static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = { 7374adfc5217SJeff Kirsher 8,0,8,8,8,8,8,8,8,8, 7375adfc5217SJeff Kirsher 4,0,4,4,4,4,4,4,4,4, 7376adfc5217SJeff Kirsher 4,4,4,4,4,4,4,4,4,4, 7377adfc5217SJeff Kirsher 4,4,4,4,4,4,4,4,4,4, 7378adfc5217SJeff Kirsher 4,4,4,4,4,4,4, 7379adfc5217SJeff Kirsher }; 7380adfc5217SJeff Kirsher 7381adfc5217SJeff Kirsher static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = { 7382adfc5217SJeff Kirsher 8,0,8,8,8,8,8,8,8,8, 7383adfc5217SJeff Kirsher 4,4,4,4,4,4,4,4,4,4, 7384adfc5217SJeff Kirsher 4,4,4,4,4,4,4,4,4,4, 7385adfc5217SJeff Kirsher 4,4,4,4,4,4,4,4,4,4, 7386adfc5217SJeff Kirsher 4,4,4,4,4,4,4, 7387adfc5217SJeff Kirsher }; 7388adfc5217SJeff Kirsher 7389adfc5217SJeff Kirsher #define BNX2_NUM_TESTS 6 7390adfc5217SJeff Kirsher 7391adfc5217SJeff Kirsher static struct { 7392adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 7393adfc5217SJeff Kirsher } bnx2_tests_str_arr[BNX2_NUM_TESTS] = { 7394adfc5217SJeff Kirsher { "register_test (offline)" }, 7395adfc5217SJeff Kirsher { "memory_test (offline)" }, 7396adfc5217SJeff Kirsher { "loopback_test (offline)" }, 7397adfc5217SJeff Kirsher { "nvram_test (online)" }, 7398adfc5217SJeff Kirsher { "interrupt_test (online)" }, 7399adfc5217SJeff Kirsher { "link_test (online)" }, 7400adfc5217SJeff Kirsher }; 7401adfc5217SJeff Kirsher 7402adfc5217SJeff Kirsher static int 7403adfc5217SJeff Kirsher bnx2_get_sset_count(struct net_device *dev, int sset) 7404adfc5217SJeff Kirsher { 7405adfc5217SJeff Kirsher switch (sset) { 7406adfc5217SJeff Kirsher case ETH_SS_TEST: 7407adfc5217SJeff Kirsher return BNX2_NUM_TESTS; 7408adfc5217SJeff Kirsher case ETH_SS_STATS: 7409adfc5217SJeff Kirsher return BNX2_NUM_STATS; 7410adfc5217SJeff Kirsher default: 7411adfc5217SJeff Kirsher return -EOPNOTSUPP; 7412adfc5217SJeff Kirsher } 7413adfc5217SJeff Kirsher } 7414adfc5217SJeff Kirsher 7415adfc5217SJeff Kirsher static void 7416adfc5217SJeff Kirsher bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) 7417adfc5217SJeff Kirsher { 7418adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7419adfc5217SJeff Kirsher 7420adfc5217SJeff Kirsher bnx2_set_power_state(bp, PCI_D0); 7421adfc5217SJeff Kirsher 7422adfc5217SJeff Kirsher memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); 7423adfc5217SJeff Kirsher if (etest->flags & ETH_TEST_FL_OFFLINE) { 7424adfc5217SJeff Kirsher int i; 7425adfc5217SJeff Kirsher 7426adfc5217SJeff Kirsher bnx2_netif_stop(bp, true); 7427adfc5217SJeff Kirsher bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG); 7428adfc5217SJeff Kirsher bnx2_free_skbs(bp); 7429adfc5217SJeff Kirsher 7430adfc5217SJeff Kirsher if (bnx2_test_registers(bp) != 0) { 7431adfc5217SJeff Kirsher buf[0] = 1; 7432adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 7433adfc5217SJeff Kirsher } 7434adfc5217SJeff Kirsher if (bnx2_test_memory(bp) != 0) { 7435adfc5217SJeff Kirsher buf[1] = 1; 7436adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 7437adfc5217SJeff Kirsher } 7438adfc5217SJeff Kirsher if ((buf[2] = bnx2_test_loopback(bp)) != 0) 7439adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 7440adfc5217SJeff Kirsher 7441adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 7442adfc5217SJeff Kirsher bnx2_shutdown_chip(bp); 7443adfc5217SJeff Kirsher else { 7444adfc5217SJeff Kirsher bnx2_init_nic(bp, 1); 7445adfc5217SJeff Kirsher bnx2_netif_start(bp, true); 7446adfc5217SJeff Kirsher } 7447adfc5217SJeff Kirsher 7448adfc5217SJeff Kirsher /* wait for link up */ 7449adfc5217SJeff Kirsher for (i = 0; i < 7; i++) { 7450adfc5217SJeff Kirsher if (bp->link_up) 7451adfc5217SJeff Kirsher break; 7452adfc5217SJeff Kirsher msleep_interruptible(1000); 7453adfc5217SJeff Kirsher } 7454adfc5217SJeff Kirsher } 7455adfc5217SJeff Kirsher 7456adfc5217SJeff Kirsher if (bnx2_test_nvram(bp) != 0) { 7457adfc5217SJeff Kirsher buf[3] = 1; 7458adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 7459adfc5217SJeff Kirsher } 7460adfc5217SJeff Kirsher if (bnx2_test_intr(bp) != 0) { 7461adfc5217SJeff Kirsher buf[4] = 1; 7462adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 7463adfc5217SJeff Kirsher } 7464adfc5217SJeff Kirsher 7465adfc5217SJeff Kirsher if (bnx2_test_link(bp) != 0) { 7466adfc5217SJeff Kirsher buf[5] = 1; 7467adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 7468adfc5217SJeff Kirsher 7469adfc5217SJeff Kirsher } 7470adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 7471adfc5217SJeff Kirsher bnx2_set_power_state(bp, PCI_D3hot); 7472adfc5217SJeff Kirsher } 7473adfc5217SJeff Kirsher 7474adfc5217SJeff Kirsher static void 7475adfc5217SJeff Kirsher bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 7476adfc5217SJeff Kirsher { 7477adfc5217SJeff Kirsher switch (stringset) { 7478adfc5217SJeff Kirsher case ETH_SS_STATS: 7479adfc5217SJeff Kirsher memcpy(buf, bnx2_stats_str_arr, 7480adfc5217SJeff Kirsher sizeof(bnx2_stats_str_arr)); 7481adfc5217SJeff Kirsher break; 7482adfc5217SJeff Kirsher case ETH_SS_TEST: 7483adfc5217SJeff Kirsher memcpy(buf, bnx2_tests_str_arr, 7484adfc5217SJeff Kirsher sizeof(bnx2_tests_str_arr)); 7485adfc5217SJeff Kirsher break; 7486adfc5217SJeff Kirsher } 7487adfc5217SJeff Kirsher } 7488adfc5217SJeff Kirsher 7489adfc5217SJeff Kirsher static void 7490adfc5217SJeff Kirsher bnx2_get_ethtool_stats(struct net_device *dev, 7491adfc5217SJeff Kirsher struct ethtool_stats *stats, u64 *buf) 7492adfc5217SJeff Kirsher { 7493adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7494adfc5217SJeff Kirsher int i; 7495adfc5217SJeff Kirsher u32 *hw_stats = (u32 *) bp->stats_blk; 7496adfc5217SJeff Kirsher u32 *temp_stats = (u32 *) bp->temp_stats_blk; 7497adfc5217SJeff Kirsher u8 *stats_len_arr = NULL; 7498adfc5217SJeff Kirsher 7499adfc5217SJeff Kirsher if (hw_stats == NULL) { 7500adfc5217SJeff Kirsher memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS); 7501adfc5217SJeff Kirsher return; 7502adfc5217SJeff Kirsher } 7503adfc5217SJeff Kirsher 7504adfc5217SJeff Kirsher if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || 7505adfc5217SJeff Kirsher (CHIP_ID(bp) == CHIP_ID_5706_A1) || 7506adfc5217SJeff Kirsher (CHIP_ID(bp) == CHIP_ID_5706_A2) || 7507adfc5217SJeff Kirsher (CHIP_ID(bp) == CHIP_ID_5708_A0)) 7508adfc5217SJeff Kirsher stats_len_arr = bnx2_5706_stats_len_arr; 7509adfc5217SJeff Kirsher else 7510adfc5217SJeff Kirsher stats_len_arr = bnx2_5708_stats_len_arr; 7511adfc5217SJeff Kirsher 7512adfc5217SJeff Kirsher for (i = 0; i < BNX2_NUM_STATS; i++) { 7513adfc5217SJeff Kirsher unsigned long offset; 7514adfc5217SJeff Kirsher 7515adfc5217SJeff Kirsher if (stats_len_arr[i] == 0) { 7516adfc5217SJeff Kirsher /* skip this counter */ 7517adfc5217SJeff Kirsher buf[i] = 0; 7518adfc5217SJeff Kirsher continue; 7519adfc5217SJeff Kirsher } 7520adfc5217SJeff Kirsher 7521adfc5217SJeff Kirsher offset = bnx2_stats_offset_arr[i]; 7522adfc5217SJeff Kirsher if (stats_len_arr[i] == 4) { 7523adfc5217SJeff Kirsher /* 4-byte counter */ 7524adfc5217SJeff Kirsher buf[i] = (u64) *(hw_stats + offset) + 7525adfc5217SJeff Kirsher *(temp_stats + offset); 7526adfc5217SJeff Kirsher continue; 7527adfc5217SJeff Kirsher } 7528adfc5217SJeff Kirsher /* 8-byte counter */ 7529adfc5217SJeff Kirsher buf[i] = (((u64) *(hw_stats + offset)) << 32) + 7530adfc5217SJeff Kirsher *(hw_stats + offset + 1) + 7531adfc5217SJeff Kirsher (((u64) *(temp_stats + offset)) << 32) + 7532adfc5217SJeff Kirsher *(temp_stats + offset + 1); 7533adfc5217SJeff Kirsher } 7534adfc5217SJeff Kirsher } 7535adfc5217SJeff Kirsher 7536adfc5217SJeff Kirsher static int 7537adfc5217SJeff Kirsher bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state) 7538adfc5217SJeff Kirsher { 7539adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7540adfc5217SJeff Kirsher 7541adfc5217SJeff Kirsher switch (state) { 7542adfc5217SJeff Kirsher case ETHTOOL_ID_ACTIVE: 7543adfc5217SJeff Kirsher bnx2_set_power_state(bp, PCI_D0); 7544adfc5217SJeff Kirsher 7545adfc5217SJeff Kirsher bp->leds_save = REG_RD(bp, BNX2_MISC_CFG); 7546adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC); 7547adfc5217SJeff Kirsher return 1; /* cycle on/off once per second */ 7548adfc5217SJeff Kirsher 7549adfc5217SJeff Kirsher case ETHTOOL_ID_ON: 7550adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE | 7551adfc5217SJeff Kirsher BNX2_EMAC_LED_1000MB_OVERRIDE | 7552adfc5217SJeff Kirsher BNX2_EMAC_LED_100MB_OVERRIDE | 7553adfc5217SJeff Kirsher BNX2_EMAC_LED_10MB_OVERRIDE | 7554adfc5217SJeff Kirsher BNX2_EMAC_LED_TRAFFIC_OVERRIDE | 7555adfc5217SJeff Kirsher BNX2_EMAC_LED_TRAFFIC); 7556adfc5217SJeff Kirsher break; 7557adfc5217SJeff Kirsher 7558adfc5217SJeff Kirsher case ETHTOOL_ID_OFF: 7559adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE); 7560adfc5217SJeff Kirsher break; 7561adfc5217SJeff Kirsher 7562adfc5217SJeff Kirsher case ETHTOOL_ID_INACTIVE: 7563adfc5217SJeff Kirsher REG_WR(bp, BNX2_EMAC_LED, 0); 7564adfc5217SJeff Kirsher REG_WR(bp, BNX2_MISC_CFG, bp->leds_save); 7565adfc5217SJeff Kirsher 7566adfc5217SJeff Kirsher if (!netif_running(dev)) 7567adfc5217SJeff Kirsher bnx2_set_power_state(bp, PCI_D3hot); 7568adfc5217SJeff Kirsher break; 7569adfc5217SJeff Kirsher } 7570adfc5217SJeff Kirsher 7571adfc5217SJeff Kirsher return 0; 7572adfc5217SJeff Kirsher } 7573adfc5217SJeff Kirsher 7574c8f44affSMichał Mirosław static netdev_features_t 7575c8f44affSMichał Mirosław bnx2_fix_features(struct net_device *dev, netdev_features_t features) 7576adfc5217SJeff Kirsher { 7577adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7578adfc5217SJeff Kirsher 7579adfc5217SJeff Kirsher if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) 7580adfc5217SJeff Kirsher features |= NETIF_F_HW_VLAN_RX; 7581adfc5217SJeff Kirsher 7582adfc5217SJeff Kirsher return features; 7583adfc5217SJeff Kirsher } 7584adfc5217SJeff Kirsher 7585adfc5217SJeff Kirsher static int 7586c8f44affSMichał Mirosław bnx2_set_features(struct net_device *dev, netdev_features_t features) 7587adfc5217SJeff Kirsher { 7588adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7589adfc5217SJeff Kirsher 7590adfc5217SJeff Kirsher /* TSO with VLAN tag won't work with current firmware */ 7591adfc5217SJeff Kirsher if (features & NETIF_F_HW_VLAN_TX) 7592adfc5217SJeff Kirsher dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO); 7593adfc5217SJeff Kirsher else 7594adfc5217SJeff Kirsher dev->vlan_features &= ~NETIF_F_ALL_TSO; 7595adfc5217SJeff Kirsher 7596adfc5217SJeff Kirsher if ((!!(features & NETIF_F_HW_VLAN_RX) != 7597adfc5217SJeff Kirsher !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) && 7598adfc5217SJeff Kirsher netif_running(dev)) { 7599adfc5217SJeff Kirsher bnx2_netif_stop(bp, false); 7600adfc5217SJeff Kirsher dev->features = features; 7601adfc5217SJeff Kirsher bnx2_set_rx_mode(dev); 7602adfc5217SJeff Kirsher bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1); 7603adfc5217SJeff Kirsher bnx2_netif_start(bp, false); 7604adfc5217SJeff Kirsher return 1; 7605adfc5217SJeff Kirsher } 7606adfc5217SJeff Kirsher 7607adfc5217SJeff Kirsher return 0; 7608adfc5217SJeff Kirsher } 7609adfc5217SJeff Kirsher 7610adfc5217SJeff Kirsher static const struct ethtool_ops bnx2_ethtool_ops = { 7611adfc5217SJeff Kirsher .get_settings = bnx2_get_settings, 7612adfc5217SJeff Kirsher .set_settings = bnx2_set_settings, 7613adfc5217SJeff Kirsher .get_drvinfo = bnx2_get_drvinfo, 7614adfc5217SJeff Kirsher .get_regs_len = bnx2_get_regs_len, 7615adfc5217SJeff Kirsher .get_regs = bnx2_get_regs, 7616adfc5217SJeff Kirsher .get_wol = bnx2_get_wol, 7617adfc5217SJeff Kirsher .set_wol = bnx2_set_wol, 7618adfc5217SJeff Kirsher .nway_reset = bnx2_nway_reset, 7619adfc5217SJeff Kirsher .get_link = bnx2_get_link, 7620adfc5217SJeff Kirsher .get_eeprom_len = bnx2_get_eeprom_len, 7621adfc5217SJeff Kirsher .get_eeprom = bnx2_get_eeprom, 7622adfc5217SJeff Kirsher .set_eeprom = bnx2_set_eeprom, 7623adfc5217SJeff Kirsher .get_coalesce = bnx2_get_coalesce, 7624adfc5217SJeff Kirsher .set_coalesce = bnx2_set_coalesce, 7625adfc5217SJeff Kirsher .get_ringparam = bnx2_get_ringparam, 7626adfc5217SJeff Kirsher .set_ringparam = bnx2_set_ringparam, 7627adfc5217SJeff Kirsher .get_pauseparam = bnx2_get_pauseparam, 7628adfc5217SJeff Kirsher .set_pauseparam = bnx2_set_pauseparam, 7629adfc5217SJeff Kirsher .self_test = bnx2_self_test, 7630adfc5217SJeff Kirsher .get_strings = bnx2_get_strings, 7631adfc5217SJeff Kirsher .set_phys_id = bnx2_set_phys_id, 7632adfc5217SJeff Kirsher .get_ethtool_stats = bnx2_get_ethtool_stats, 7633adfc5217SJeff Kirsher .get_sset_count = bnx2_get_sset_count, 7634adfc5217SJeff Kirsher }; 7635adfc5217SJeff Kirsher 7636adfc5217SJeff Kirsher /* Called with rtnl_lock */ 7637adfc5217SJeff Kirsher static int 7638adfc5217SJeff Kirsher bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 7639adfc5217SJeff Kirsher { 7640adfc5217SJeff Kirsher struct mii_ioctl_data *data = if_mii(ifr); 7641adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7642adfc5217SJeff Kirsher int err; 7643adfc5217SJeff Kirsher 7644adfc5217SJeff Kirsher switch(cmd) { 7645adfc5217SJeff Kirsher case SIOCGMIIPHY: 7646adfc5217SJeff Kirsher data->phy_id = bp->phy_addr; 7647adfc5217SJeff Kirsher 7648adfc5217SJeff Kirsher /* fallthru */ 7649adfc5217SJeff Kirsher case SIOCGMIIREG: { 7650adfc5217SJeff Kirsher u32 mii_regval; 7651adfc5217SJeff Kirsher 7652adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 7653adfc5217SJeff Kirsher return -EOPNOTSUPP; 7654adfc5217SJeff Kirsher 7655adfc5217SJeff Kirsher if (!netif_running(dev)) 7656adfc5217SJeff Kirsher return -EAGAIN; 7657adfc5217SJeff Kirsher 7658adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 7659adfc5217SJeff Kirsher err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); 7660adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 7661adfc5217SJeff Kirsher 7662adfc5217SJeff Kirsher data->val_out = mii_regval; 7663adfc5217SJeff Kirsher 7664adfc5217SJeff Kirsher return err; 7665adfc5217SJeff Kirsher } 7666adfc5217SJeff Kirsher 7667adfc5217SJeff Kirsher case SIOCSMIIREG: 7668adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 7669adfc5217SJeff Kirsher return -EOPNOTSUPP; 7670adfc5217SJeff Kirsher 7671adfc5217SJeff Kirsher if (!netif_running(dev)) 7672adfc5217SJeff Kirsher return -EAGAIN; 7673adfc5217SJeff Kirsher 7674adfc5217SJeff Kirsher spin_lock_bh(&bp->phy_lock); 7675adfc5217SJeff Kirsher err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); 7676adfc5217SJeff Kirsher spin_unlock_bh(&bp->phy_lock); 7677adfc5217SJeff Kirsher 7678adfc5217SJeff Kirsher return err; 7679adfc5217SJeff Kirsher 7680adfc5217SJeff Kirsher default: 7681adfc5217SJeff Kirsher /* do nothing */ 7682adfc5217SJeff Kirsher break; 7683adfc5217SJeff Kirsher } 7684adfc5217SJeff Kirsher return -EOPNOTSUPP; 7685adfc5217SJeff Kirsher } 7686adfc5217SJeff Kirsher 7687adfc5217SJeff Kirsher /* Called with rtnl_lock */ 7688adfc5217SJeff Kirsher static int 7689adfc5217SJeff Kirsher bnx2_change_mac_addr(struct net_device *dev, void *p) 7690adfc5217SJeff Kirsher { 7691adfc5217SJeff Kirsher struct sockaddr *addr = p; 7692adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7693adfc5217SJeff Kirsher 7694adfc5217SJeff Kirsher if (!is_valid_ether_addr(addr->sa_data)) 7695adfc5217SJeff Kirsher return -EINVAL; 7696adfc5217SJeff Kirsher 7697adfc5217SJeff Kirsher memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 7698adfc5217SJeff Kirsher if (netif_running(dev)) 7699adfc5217SJeff Kirsher bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); 7700adfc5217SJeff Kirsher 7701adfc5217SJeff Kirsher return 0; 7702adfc5217SJeff Kirsher } 7703adfc5217SJeff Kirsher 7704adfc5217SJeff Kirsher /* Called with rtnl_lock */ 7705adfc5217SJeff Kirsher static int 7706adfc5217SJeff Kirsher bnx2_change_mtu(struct net_device *dev, int new_mtu) 7707adfc5217SJeff Kirsher { 7708adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7709adfc5217SJeff Kirsher 7710adfc5217SJeff Kirsher if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) || 7711adfc5217SJeff Kirsher ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE)) 7712adfc5217SJeff Kirsher return -EINVAL; 7713adfc5217SJeff Kirsher 7714adfc5217SJeff Kirsher dev->mtu = new_mtu; 7715adfc5217SJeff Kirsher return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size); 7716adfc5217SJeff Kirsher } 7717adfc5217SJeff Kirsher 7718adfc5217SJeff Kirsher #ifdef CONFIG_NET_POLL_CONTROLLER 7719adfc5217SJeff Kirsher static void 7720adfc5217SJeff Kirsher poll_bnx2(struct net_device *dev) 7721adfc5217SJeff Kirsher { 7722adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 7723adfc5217SJeff Kirsher int i; 7724adfc5217SJeff Kirsher 7725adfc5217SJeff Kirsher for (i = 0; i < bp->irq_nvecs; i++) { 7726adfc5217SJeff Kirsher struct bnx2_irq *irq = &bp->irq_tbl[i]; 7727adfc5217SJeff Kirsher 7728adfc5217SJeff Kirsher disable_irq(irq->vector); 7729adfc5217SJeff Kirsher irq->handler(irq->vector, &bp->bnx2_napi[i]); 7730adfc5217SJeff Kirsher enable_irq(irq->vector); 7731adfc5217SJeff Kirsher } 7732adfc5217SJeff Kirsher } 7733adfc5217SJeff Kirsher #endif 7734adfc5217SJeff Kirsher 7735adfc5217SJeff Kirsher static void __devinit 7736adfc5217SJeff Kirsher bnx2_get_5709_media(struct bnx2 *bp) 7737adfc5217SJeff Kirsher { 7738adfc5217SJeff Kirsher u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); 7739adfc5217SJeff Kirsher u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID; 7740adfc5217SJeff Kirsher u32 strap; 7741adfc5217SJeff Kirsher 7742adfc5217SJeff Kirsher if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) 7743adfc5217SJeff Kirsher return; 7744adfc5217SJeff Kirsher else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 7745adfc5217SJeff Kirsher bp->phy_flags |= BNX2_PHY_FLAG_SERDES; 7746adfc5217SJeff Kirsher return; 7747adfc5217SJeff Kirsher } 7748adfc5217SJeff Kirsher 7749adfc5217SJeff Kirsher if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 7750adfc5217SJeff Kirsher strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 7751adfc5217SJeff Kirsher else 7752adfc5217SJeff Kirsher strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 7753adfc5217SJeff Kirsher 7754adfc5217SJeff Kirsher if (PCI_FUNC(bp->pdev->devfn) == 0) { 7755adfc5217SJeff Kirsher switch (strap) { 7756adfc5217SJeff Kirsher case 0x4: 7757adfc5217SJeff Kirsher case 0x5: 7758adfc5217SJeff Kirsher case 0x6: 7759adfc5217SJeff Kirsher bp->phy_flags |= BNX2_PHY_FLAG_SERDES; 7760adfc5217SJeff Kirsher return; 7761adfc5217SJeff Kirsher } 7762adfc5217SJeff Kirsher } else { 7763adfc5217SJeff Kirsher switch (strap) { 7764adfc5217SJeff Kirsher case 0x1: 7765adfc5217SJeff Kirsher case 0x2: 7766adfc5217SJeff Kirsher case 0x4: 7767adfc5217SJeff Kirsher bp->phy_flags |= BNX2_PHY_FLAG_SERDES; 7768adfc5217SJeff Kirsher return; 7769adfc5217SJeff Kirsher } 7770adfc5217SJeff Kirsher } 7771adfc5217SJeff Kirsher } 7772adfc5217SJeff Kirsher 7773adfc5217SJeff Kirsher static void __devinit 7774adfc5217SJeff Kirsher bnx2_get_pci_speed(struct bnx2 *bp) 7775adfc5217SJeff Kirsher { 7776adfc5217SJeff Kirsher u32 reg; 7777adfc5217SJeff Kirsher 7778adfc5217SJeff Kirsher reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); 7779adfc5217SJeff Kirsher if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { 7780adfc5217SJeff Kirsher u32 clkreg; 7781adfc5217SJeff Kirsher 7782adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_PCIX; 7783adfc5217SJeff Kirsher 7784adfc5217SJeff Kirsher clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); 7785adfc5217SJeff Kirsher 7786adfc5217SJeff Kirsher clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 7787adfc5217SJeff Kirsher switch (clkreg) { 7788adfc5217SJeff Kirsher case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 7789adfc5217SJeff Kirsher bp->bus_speed_mhz = 133; 7790adfc5217SJeff Kirsher break; 7791adfc5217SJeff Kirsher 7792adfc5217SJeff Kirsher case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 7793adfc5217SJeff Kirsher bp->bus_speed_mhz = 100; 7794adfc5217SJeff Kirsher break; 7795adfc5217SJeff Kirsher 7796adfc5217SJeff Kirsher case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 7797adfc5217SJeff Kirsher case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 7798adfc5217SJeff Kirsher bp->bus_speed_mhz = 66; 7799adfc5217SJeff Kirsher break; 7800adfc5217SJeff Kirsher 7801adfc5217SJeff Kirsher case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 7802adfc5217SJeff Kirsher case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 7803adfc5217SJeff Kirsher bp->bus_speed_mhz = 50; 7804adfc5217SJeff Kirsher break; 7805adfc5217SJeff Kirsher 7806adfc5217SJeff Kirsher case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 7807adfc5217SJeff Kirsher case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 7808adfc5217SJeff Kirsher case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 7809adfc5217SJeff Kirsher bp->bus_speed_mhz = 33; 7810adfc5217SJeff Kirsher break; 7811adfc5217SJeff Kirsher } 7812adfc5217SJeff Kirsher } 7813adfc5217SJeff Kirsher else { 7814adfc5217SJeff Kirsher if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) 7815adfc5217SJeff Kirsher bp->bus_speed_mhz = 66; 7816adfc5217SJeff Kirsher else 7817adfc5217SJeff Kirsher bp->bus_speed_mhz = 33; 7818adfc5217SJeff Kirsher } 7819adfc5217SJeff Kirsher 7820adfc5217SJeff Kirsher if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) 7821adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_PCI_32BIT; 7822adfc5217SJeff Kirsher 7823adfc5217SJeff Kirsher } 7824adfc5217SJeff Kirsher 7825adfc5217SJeff Kirsher static void __devinit 7826adfc5217SJeff Kirsher bnx2_read_vpd_fw_ver(struct bnx2 *bp) 7827adfc5217SJeff Kirsher { 7828adfc5217SJeff Kirsher int rc, i, j; 7829adfc5217SJeff Kirsher u8 *data; 7830adfc5217SJeff Kirsher unsigned int block_end, rosize, len; 7831adfc5217SJeff Kirsher 7832adfc5217SJeff Kirsher #define BNX2_VPD_NVRAM_OFFSET 0x300 7833adfc5217SJeff Kirsher #define BNX2_VPD_LEN 128 7834adfc5217SJeff Kirsher #define BNX2_MAX_VER_SLEN 30 7835adfc5217SJeff Kirsher 7836adfc5217SJeff Kirsher data = kmalloc(256, GFP_KERNEL); 7837adfc5217SJeff Kirsher if (!data) 7838adfc5217SJeff Kirsher return; 7839adfc5217SJeff Kirsher 7840adfc5217SJeff Kirsher rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN, 7841adfc5217SJeff Kirsher BNX2_VPD_LEN); 7842adfc5217SJeff Kirsher if (rc) 7843adfc5217SJeff Kirsher goto vpd_done; 7844adfc5217SJeff Kirsher 7845adfc5217SJeff Kirsher for (i = 0; i < BNX2_VPD_LEN; i += 4) { 7846adfc5217SJeff Kirsher data[i] = data[i + BNX2_VPD_LEN + 3]; 7847adfc5217SJeff Kirsher data[i + 1] = data[i + BNX2_VPD_LEN + 2]; 7848adfc5217SJeff Kirsher data[i + 2] = data[i + BNX2_VPD_LEN + 1]; 7849adfc5217SJeff Kirsher data[i + 3] = data[i + BNX2_VPD_LEN]; 7850adfc5217SJeff Kirsher } 7851adfc5217SJeff Kirsher 7852adfc5217SJeff Kirsher i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA); 7853adfc5217SJeff Kirsher if (i < 0) 7854adfc5217SJeff Kirsher goto vpd_done; 7855adfc5217SJeff Kirsher 7856adfc5217SJeff Kirsher rosize = pci_vpd_lrdt_size(&data[i]); 7857adfc5217SJeff Kirsher i += PCI_VPD_LRDT_TAG_SIZE; 7858adfc5217SJeff Kirsher block_end = i + rosize; 7859adfc5217SJeff Kirsher 7860adfc5217SJeff Kirsher if (block_end > BNX2_VPD_LEN) 7861adfc5217SJeff Kirsher goto vpd_done; 7862adfc5217SJeff Kirsher 7863adfc5217SJeff Kirsher j = pci_vpd_find_info_keyword(data, i, rosize, 7864adfc5217SJeff Kirsher PCI_VPD_RO_KEYWORD_MFR_ID); 7865adfc5217SJeff Kirsher if (j < 0) 7866adfc5217SJeff Kirsher goto vpd_done; 7867adfc5217SJeff Kirsher 7868adfc5217SJeff Kirsher len = pci_vpd_info_field_size(&data[j]); 7869adfc5217SJeff Kirsher 7870adfc5217SJeff Kirsher j += PCI_VPD_INFO_FLD_HDR_SIZE; 7871adfc5217SJeff Kirsher if (j + len > block_end || len != 4 || 7872adfc5217SJeff Kirsher memcmp(&data[j], "1028", 4)) 7873adfc5217SJeff Kirsher goto vpd_done; 7874adfc5217SJeff Kirsher 7875adfc5217SJeff Kirsher j = pci_vpd_find_info_keyword(data, i, rosize, 7876adfc5217SJeff Kirsher PCI_VPD_RO_KEYWORD_VENDOR0); 7877adfc5217SJeff Kirsher if (j < 0) 7878adfc5217SJeff Kirsher goto vpd_done; 7879adfc5217SJeff Kirsher 7880adfc5217SJeff Kirsher len = pci_vpd_info_field_size(&data[j]); 7881adfc5217SJeff Kirsher 7882adfc5217SJeff Kirsher j += PCI_VPD_INFO_FLD_HDR_SIZE; 7883adfc5217SJeff Kirsher if (j + len > block_end || len > BNX2_MAX_VER_SLEN) 7884adfc5217SJeff Kirsher goto vpd_done; 7885adfc5217SJeff Kirsher 7886adfc5217SJeff Kirsher memcpy(bp->fw_version, &data[j], len); 7887adfc5217SJeff Kirsher bp->fw_version[len] = ' '; 7888adfc5217SJeff Kirsher 7889adfc5217SJeff Kirsher vpd_done: 7890adfc5217SJeff Kirsher kfree(data); 7891adfc5217SJeff Kirsher } 7892adfc5217SJeff Kirsher 7893adfc5217SJeff Kirsher static int __devinit 7894adfc5217SJeff Kirsher bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) 7895adfc5217SJeff Kirsher { 7896adfc5217SJeff Kirsher struct bnx2 *bp; 7897adfc5217SJeff Kirsher unsigned long mem_len; 7898adfc5217SJeff Kirsher int rc, i, j; 7899adfc5217SJeff Kirsher u32 reg; 7900adfc5217SJeff Kirsher u64 dma_mask, persist_dma_mask; 7901adfc5217SJeff Kirsher int err; 7902adfc5217SJeff Kirsher 7903adfc5217SJeff Kirsher SET_NETDEV_DEV(dev, &pdev->dev); 7904adfc5217SJeff Kirsher bp = netdev_priv(dev); 7905adfc5217SJeff Kirsher 7906adfc5217SJeff Kirsher bp->flags = 0; 7907adfc5217SJeff Kirsher bp->phy_flags = 0; 7908adfc5217SJeff Kirsher 7909adfc5217SJeff Kirsher bp->temp_stats_blk = 7910adfc5217SJeff Kirsher kzalloc(sizeof(struct statistics_block), GFP_KERNEL); 7911adfc5217SJeff Kirsher 7912adfc5217SJeff Kirsher if (bp->temp_stats_blk == NULL) { 7913adfc5217SJeff Kirsher rc = -ENOMEM; 7914adfc5217SJeff Kirsher goto err_out; 7915adfc5217SJeff Kirsher } 7916adfc5217SJeff Kirsher 7917adfc5217SJeff Kirsher /* enable device (incl. PCI PM wakeup), and bus-mastering */ 7918adfc5217SJeff Kirsher rc = pci_enable_device(pdev); 7919adfc5217SJeff Kirsher if (rc) { 7920adfc5217SJeff Kirsher dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 7921adfc5217SJeff Kirsher goto err_out; 7922adfc5217SJeff Kirsher } 7923adfc5217SJeff Kirsher 7924adfc5217SJeff Kirsher if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 7925adfc5217SJeff Kirsher dev_err(&pdev->dev, 7926adfc5217SJeff Kirsher "Cannot find PCI device base address, aborting\n"); 7927adfc5217SJeff Kirsher rc = -ENODEV; 7928adfc5217SJeff Kirsher goto err_out_disable; 7929adfc5217SJeff Kirsher } 7930adfc5217SJeff Kirsher 7931adfc5217SJeff Kirsher rc = pci_request_regions(pdev, DRV_MODULE_NAME); 7932adfc5217SJeff Kirsher if (rc) { 7933adfc5217SJeff Kirsher dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 7934adfc5217SJeff Kirsher goto err_out_disable; 7935adfc5217SJeff Kirsher } 7936adfc5217SJeff Kirsher 7937adfc5217SJeff Kirsher pci_set_master(pdev); 7938adfc5217SJeff Kirsher 7939adfc5217SJeff Kirsher bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 7940adfc5217SJeff Kirsher if (bp->pm_cap == 0) { 7941adfc5217SJeff Kirsher dev_err(&pdev->dev, 7942adfc5217SJeff Kirsher "Cannot find power management capability, aborting\n"); 7943adfc5217SJeff Kirsher rc = -EIO; 7944adfc5217SJeff Kirsher goto err_out_release; 7945adfc5217SJeff Kirsher } 7946adfc5217SJeff Kirsher 7947adfc5217SJeff Kirsher bp->dev = dev; 7948adfc5217SJeff Kirsher bp->pdev = pdev; 7949adfc5217SJeff Kirsher 7950adfc5217SJeff Kirsher spin_lock_init(&bp->phy_lock); 7951adfc5217SJeff Kirsher spin_lock_init(&bp->indirect_lock); 7952adfc5217SJeff Kirsher #ifdef BCM_CNIC 7953adfc5217SJeff Kirsher mutex_init(&bp->cnic_lock); 7954adfc5217SJeff Kirsher #endif 7955adfc5217SJeff Kirsher INIT_WORK(&bp->reset_task, bnx2_reset_task); 7956adfc5217SJeff Kirsher 7957adfc5217SJeff Kirsher dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0); 7958adfc5217SJeff Kirsher mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1); 7959adfc5217SJeff Kirsher dev->mem_end = dev->mem_start + mem_len; 7960adfc5217SJeff Kirsher dev->irq = pdev->irq; 7961adfc5217SJeff Kirsher 7962adfc5217SJeff Kirsher bp->regview = ioremap_nocache(dev->base_addr, mem_len); 7963adfc5217SJeff Kirsher 7964adfc5217SJeff Kirsher if (!bp->regview) { 7965adfc5217SJeff Kirsher dev_err(&pdev->dev, "Cannot map register space, aborting\n"); 7966adfc5217SJeff Kirsher rc = -ENOMEM; 7967adfc5217SJeff Kirsher goto err_out_release; 7968adfc5217SJeff Kirsher } 7969adfc5217SJeff Kirsher 7970adfc5217SJeff Kirsher bnx2_set_power_state(bp, PCI_D0); 7971adfc5217SJeff Kirsher 7972adfc5217SJeff Kirsher /* Configure byte swap and enable write to the reg_window registers. 7973adfc5217SJeff Kirsher * Rely on CPU to do target byte swapping on big endian systems 7974adfc5217SJeff Kirsher * The chip's target access swapping will not swap all accesses 7975adfc5217SJeff Kirsher */ 7976adfc5217SJeff Kirsher REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, 7977adfc5217SJeff Kirsher BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 7978adfc5217SJeff Kirsher BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 7979adfc5217SJeff Kirsher 7980adfc5217SJeff Kirsher bp->chip_id = REG_RD(bp, BNX2_MISC_ID); 7981adfc5217SJeff Kirsher 7982adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) { 7983adfc5217SJeff Kirsher if (!pci_is_pcie(pdev)) { 7984adfc5217SJeff Kirsher dev_err(&pdev->dev, "Not PCIE, aborting\n"); 7985adfc5217SJeff Kirsher rc = -EIO; 7986adfc5217SJeff Kirsher goto err_out_unmap; 7987adfc5217SJeff Kirsher } 7988adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_PCIE; 7989adfc5217SJeff Kirsher if (CHIP_REV(bp) == CHIP_REV_Ax) 7990adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_JUMBO_BROKEN; 7991adfc5217SJeff Kirsher 7992adfc5217SJeff Kirsher /* AER (Advanced Error Reporting) hooks */ 7993adfc5217SJeff Kirsher err = pci_enable_pcie_error_reporting(pdev); 7994adfc5217SJeff Kirsher if (!err) 7995adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_AER_ENABLED; 7996adfc5217SJeff Kirsher 7997adfc5217SJeff Kirsher } else { 7998adfc5217SJeff Kirsher bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); 7999adfc5217SJeff Kirsher if (bp->pcix_cap == 0) { 8000adfc5217SJeff Kirsher dev_err(&pdev->dev, 8001adfc5217SJeff Kirsher "Cannot find PCIX capability, aborting\n"); 8002adfc5217SJeff Kirsher rc = -EIO; 8003adfc5217SJeff Kirsher goto err_out_unmap; 8004adfc5217SJeff Kirsher } 8005adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_BROKEN_STATS; 8006adfc5217SJeff Kirsher } 8007adfc5217SJeff Kirsher 8008adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) { 8009adfc5217SJeff Kirsher if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) 8010adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_MSIX_CAP; 8011adfc5217SJeff Kirsher } 8012adfc5217SJeff Kirsher 8013adfc5217SJeff Kirsher if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) { 8014adfc5217SJeff Kirsher if (pci_find_capability(pdev, PCI_CAP_ID_MSI)) 8015adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_MSI_CAP; 8016adfc5217SJeff Kirsher } 8017adfc5217SJeff Kirsher 8018adfc5217SJeff Kirsher /* 5708 cannot support DMA addresses > 40-bit. */ 8019adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5708) 8020adfc5217SJeff Kirsher persist_dma_mask = dma_mask = DMA_BIT_MASK(40); 8021adfc5217SJeff Kirsher else 8022adfc5217SJeff Kirsher persist_dma_mask = dma_mask = DMA_BIT_MASK(64); 8023adfc5217SJeff Kirsher 8024adfc5217SJeff Kirsher /* Configure DMA attributes. */ 8025adfc5217SJeff Kirsher if (pci_set_dma_mask(pdev, dma_mask) == 0) { 8026adfc5217SJeff Kirsher dev->features |= NETIF_F_HIGHDMA; 8027adfc5217SJeff Kirsher rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask); 8028adfc5217SJeff Kirsher if (rc) { 8029adfc5217SJeff Kirsher dev_err(&pdev->dev, 8030adfc5217SJeff Kirsher "pci_set_consistent_dma_mask failed, aborting\n"); 8031adfc5217SJeff Kirsher goto err_out_unmap; 8032adfc5217SJeff Kirsher } 8033adfc5217SJeff Kirsher } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) { 8034adfc5217SJeff Kirsher dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 8035adfc5217SJeff Kirsher goto err_out_unmap; 8036adfc5217SJeff Kirsher } 8037adfc5217SJeff Kirsher 8038adfc5217SJeff Kirsher if (!(bp->flags & BNX2_FLAG_PCIE)) 8039adfc5217SJeff Kirsher bnx2_get_pci_speed(bp); 8040adfc5217SJeff Kirsher 8041adfc5217SJeff Kirsher /* 5706A0 may falsely detect SERR and PERR. */ 8042adfc5217SJeff Kirsher if (CHIP_ID(bp) == CHIP_ID_5706_A0) { 8043adfc5217SJeff Kirsher reg = REG_RD(bp, PCI_COMMAND); 8044adfc5217SJeff Kirsher reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 8045adfc5217SJeff Kirsher REG_WR(bp, PCI_COMMAND, reg); 8046adfc5217SJeff Kirsher } 8047adfc5217SJeff Kirsher else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) && 8048adfc5217SJeff Kirsher !(bp->flags & BNX2_FLAG_PCIX)) { 8049adfc5217SJeff Kirsher 8050adfc5217SJeff Kirsher dev_err(&pdev->dev, 8051adfc5217SJeff Kirsher "5706 A1 can only be used in a PCIX bus, aborting\n"); 8052adfc5217SJeff Kirsher goto err_out_unmap; 8053adfc5217SJeff Kirsher } 8054adfc5217SJeff Kirsher 8055adfc5217SJeff Kirsher bnx2_init_nvram(bp); 8056adfc5217SJeff Kirsher 8057adfc5217SJeff Kirsher reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE); 8058adfc5217SJeff Kirsher 8059adfc5217SJeff Kirsher if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == 8060adfc5217SJeff Kirsher BNX2_SHM_HDR_SIGNATURE_SIG) { 8061adfc5217SJeff Kirsher u32 off = PCI_FUNC(pdev->devfn) << 2; 8062adfc5217SJeff Kirsher 8063adfc5217SJeff Kirsher bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off); 8064adfc5217SJeff Kirsher } else 8065adfc5217SJeff Kirsher bp->shmem_base = HOST_VIEW_SHMEM_BASE; 8066adfc5217SJeff Kirsher 8067adfc5217SJeff Kirsher /* Get the permanent MAC address. First we need to make sure the 8068adfc5217SJeff Kirsher * firmware is actually running. 8069adfc5217SJeff Kirsher */ 8070adfc5217SJeff Kirsher reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE); 8071adfc5217SJeff Kirsher 8072adfc5217SJeff Kirsher if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != 8073adfc5217SJeff Kirsher BNX2_DEV_INFO_SIGNATURE_MAGIC) { 8074adfc5217SJeff Kirsher dev_err(&pdev->dev, "Firmware not running, aborting\n"); 8075adfc5217SJeff Kirsher rc = -ENODEV; 8076adfc5217SJeff Kirsher goto err_out_unmap; 8077adfc5217SJeff Kirsher } 8078adfc5217SJeff Kirsher 8079adfc5217SJeff Kirsher bnx2_read_vpd_fw_ver(bp); 8080adfc5217SJeff Kirsher 8081adfc5217SJeff Kirsher j = strlen(bp->fw_version); 8082adfc5217SJeff Kirsher reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV); 8083adfc5217SJeff Kirsher for (i = 0; i < 3 && j < 24; i++) { 8084adfc5217SJeff Kirsher u8 num, k, skip0; 8085adfc5217SJeff Kirsher 8086adfc5217SJeff Kirsher if (i == 0) { 8087adfc5217SJeff Kirsher bp->fw_version[j++] = 'b'; 8088adfc5217SJeff Kirsher bp->fw_version[j++] = 'c'; 8089adfc5217SJeff Kirsher bp->fw_version[j++] = ' '; 8090adfc5217SJeff Kirsher } 8091adfc5217SJeff Kirsher num = (u8) (reg >> (24 - (i * 8))); 8092adfc5217SJeff Kirsher for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 8093adfc5217SJeff Kirsher if (num >= k || !skip0 || k == 1) { 8094adfc5217SJeff Kirsher bp->fw_version[j++] = (num / k) + '0'; 8095adfc5217SJeff Kirsher skip0 = 0; 8096adfc5217SJeff Kirsher } 8097adfc5217SJeff Kirsher } 8098adfc5217SJeff Kirsher if (i != 2) 8099adfc5217SJeff Kirsher bp->fw_version[j++] = '.'; 8100adfc5217SJeff Kirsher } 8101adfc5217SJeff Kirsher reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE); 8102adfc5217SJeff Kirsher if (reg & BNX2_PORT_FEATURE_WOL_ENABLED) 8103adfc5217SJeff Kirsher bp->wol = 1; 8104adfc5217SJeff Kirsher 8105adfc5217SJeff Kirsher if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) { 8106adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_ASF_ENABLE; 8107adfc5217SJeff Kirsher 8108adfc5217SJeff Kirsher for (i = 0; i < 30; i++) { 8109adfc5217SJeff Kirsher reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); 8110adfc5217SJeff Kirsher if (reg & BNX2_CONDITION_MFW_RUN_MASK) 8111adfc5217SJeff Kirsher break; 8112adfc5217SJeff Kirsher msleep(10); 8113adfc5217SJeff Kirsher } 8114adfc5217SJeff Kirsher } 8115adfc5217SJeff Kirsher reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); 8116adfc5217SJeff Kirsher reg &= BNX2_CONDITION_MFW_RUN_MASK; 8117adfc5217SJeff Kirsher if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN && 8118adfc5217SJeff Kirsher reg != BNX2_CONDITION_MFW_RUN_NONE) { 8119adfc5217SJeff Kirsher u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR); 8120adfc5217SJeff Kirsher 8121adfc5217SJeff Kirsher if (j < 32) 8122adfc5217SJeff Kirsher bp->fw_version[j++] = ' '; 8123adfc5217SJeff Kirsher for (i = 0; i < 3 && j < 28; i++) { 8124adfc5217SJeff Kirsher reg = bnx2_reg_rd_ind(bp, addr + i * 4); 8125adfc5217SJeff Kirsher reg = be32_to_cpu(reg); 8126adfc5217SJeff Kirsher memcpy(&bp->fw_version[j], ®, 4); 8127adfc5217SJeff Kirsher j += 4; 8128adfc5217SJeff Kirsher } 8129adfc5217SJeff Kirsher } 8130adfc5217SJeff Kirsher 8131adfc5217SJeff Kirsher reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER); 8132adfc5217SJeff Kirsher bp->mac_addr[0] = (u8) (reg >> 8); 8133adfc5217SJeff Kirsher bp->mac_addr[1] = (u8) reg; 8134adfc5217SJeff Kirsher 8135adfc5217SJeff Kirsher reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER); 8136adfc5217SJeff Kirsher bp->mac_addr[2] = (u8) (reg >> 24); 8137adfc5217SJeff Kirsher bp->mac_addr[3] = (u8) (reg >> 16); 8138adfc5217SJeff Kirsher bp->mac_addr[4] = (u8) (reg >> 8); 8139adfc5217SJeff Kirsher bp->mac_addr[5] = (u8) reg; 8140adfc5217SJeff Kirsher 8141adfc5217SJeff Kirsher bp->tx_ring_size = MAX_TX_DESC_CNT; 8142adfc5217SJeff Kirsher bnx2_set_rx_ring_size(bp, 255); 8143adfc5217SJeff Kirsher 8144adfc5217SJeff Kirsher bp->tx_quick_cons_trip_int = 2; 8145adfc5217SJeff Kirsher bp->tx_quick_cons_trip = 20; 8146adfc5217SJeff Kirsher bp->tx_ticks_int = 18; 8147adfc5217SJeff Kirsher bp->tx_ticks = 80; 8148adfc5217SJeff Kirsher 8149adfc5217SJeff Kirsher bp->rx_quick_cons_trip_int = 2; 8150adfc5217SJeff Kirsher bp->rx_quick_cons_trip = 12; 8151adfc5217SJeff Kirsher bp->rx_ticks_int = 18; 8152adfc5217SJeff Kirsher bp->rx_ticks = 18; 8153adfc5217SJeff Kirsher 8154adfc5217SJeff Kirsher bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS; 8155adfc5217SJeff Kirsher 8156adfc5217SJeff Kirsher bp->current_interval = BNX2_TIMER_INTERVAL; 8157adfc5217SJeff Kirsher 8158adfc5217SJeff Kirsher bp->phy_addr = 1; 8159adfc5217SJeff Kirsher 8160adfc5217SJeff Kirsher /* Disable WOL support if we are running on a SERDES chip. */ 8161adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) 8162adfc5217SJeff Kirsher bnx2_get_5709_media(bp); 8163adfc5217SJeff Kirsher else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) 8164adfc5217SJeff Kirsher bp->phy_flags |= BNX2_PHY_FLAG_SERDES; 8165adfc5217SJeff Kirsher 8166adfc5217SJeff Kirsher bp->phy_port = PORT_TP; 8167adfc5217SJeff Kirsher if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 8168adfc5217SJeff Kirsher bp->phy_port = PORT_FIBRE; 8169adfc5217SJeff Kirsher reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); 8170adfc5217SJeff Kirsher if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) { 8171adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_NO_WOL; 8172adfc5217SJeff Kirsher bp->wol = 0; 8173adfc5217SJeff Kirsher } 8174adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5706) { 8175adfc5217SJeff Kirsher /* Don't do parallel detect on this board because of 8176adfc5217SJeff Kirsher * some board problems. The link will not go down 8177adfc5217SJeff Kirsher * if we do parallel detect. 8178adfc5217SJeff Kirsher */ 8179adfc5217SJeff Kirsher if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP && 8180adfc5217SJeff Kirsher pdev->subsystem_device == 0x310c) 8181adfc5217SJeff Kirsher bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL; 8182adfc5217SJeff Kirsher } else { 8183adfc5217SJeff Kirsher bp->phy_addr = 2; 8184adfc5217SJeff Kirsher if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) 8185adfc5217SJeff Kirsher bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; 8186adfc5217SJeff Kirsher } 8187adfc5217SJeff Kirsher } else if (CHIP_NUM(bp) == CHIP_NUM_5706 || 8188adfc5217SJeff Kirsher CHIP_NUM(bp) == CHIP_NUM_5708) 8189adfc5217SJeff Kirsher bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX; 8190adfc5217SJeff Kirsher else if (CHIP_NUM(bp) == CHIP_NUM_5709 && 8191adfc5217SJeff Kirsher (CHIP_REV(bp) == CHIP_REV_Ax || 8192adfc5217SJeff Kirsher CHIP_REV(bp) == CHIP_REV_Bx)) 8193adfc5217SJeff Kirsher bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC; 8194adfc5217SJeff Kirsher 8195adfc5217SJeff Kirsher bnx2_init_fw_cap(bp); 8196adfc5217SJeff Kirsher 8197adfc5217SJeff Kirsher if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || 8198adfc5217SJeff Kirsher (CHIP_ID(bp) == CHIP_ID_5708_B0) || 8199adfc5217SJeff Kirsher (CHIP_ID(bp) == CHIP_ID_5708_B1) || 8200adfc5217SJeff Kirsher !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) { 8201adfc5217SJeff Kirsher bp->flags |= BNX2_FLAG_NO_WOL; 8202adfc5217SJeff Kirsher bp->wol = 0; 8203adfc5217SJeff Kirsher } 8204adfc5217SJeff Kirsher 8205adfc5217SJeff Kirsher if (CHIP_ID(bp) == CHIP_ID_5706_A0) { 8206adfc5217SJeff Kirsher bp->tx_quick_cons_trip_int = 8207adfc5217SJeff Kirsher bp->tx_quick_cons_trip; 8208adfc5217SJeff Kirsher bp->tx_ticks_int = bp->tx_ticks; 8209adfc5217SJeff Kirsher bp->rx_quick_cons_trip_int = 8210adfc5217SJeff Kirsher bp->rx_quick_cons_trip; 8211adfc5217SJeff Kirsher bp->rx_ticks_int = bp->rx_ticks; 8212adfc5217SJeff Kirsher bp->comp_prod_trip_int = bp->comp_prod_trip; 8213adfc5217SJeff Kirsher bp->com_ticks_int = bp->com_ticks; 8214adfc5217SJeff Kirsher bp->cmd_ticks_int = bp->cmd_ticks; 8215adfc5217SJeff Kirsher } 8216adfc5217SJeff Kirsher 8217adfc5217SJeff Kirsher /* Disable MSI on 5706 if AMD 8132 bridge is found. 8218adfc5217SJeff Kirsher * 8219adfc5217SJeff Kirsher * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes 8220adfc5217SJeff Kirsher * with byte enables disabled on the unused 32-bit word. This is legal 8221adfc5217SJeff Kirsher * but causes problems on the AMD 8132 which will eventually stop 8222adfc5217SJeff Kirsher * responding after a while. 8223adfc5217SJeff Kirsher * 8224adfc5217SJeff Kirsher * AMD believes this incompatibility is unique to the 5706, and 8225adfc5217SJeff Kirsher * prefers to locally disable MSI rather than globally disabling it. 8226adfc5217SJeff Kirsher */ 8227adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) { 8228adfc5217SJeff Kirsher struct pci_dev *amd_8132 = NULL; 8229adfc5217SJeff Kirsher 8230adfc5217SJeff Kirsher while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD, 8231adfc5217SJeff Kirsher PCI_DEVICE_ID_AMD_8132_BRIDGE, 8232adfc5217SJeff Kirsher amd_8132))) { 8233adfc5217SJeff Kirsher 8234adfc5217SJeff Kirsher if (amd_8132->revision >= 0x10 && 8235adfc5217SJeff Kirsher amd_8132->revision <= 0x13) { 8236adfc5217SJeff Kirsher disable_msi = 1; 8237adfc5217SJeff Kirsher pci_dev_put(amd_8132); 8238adfc5217SJeff Kirsher break; 8239adfc5217SJeff Kirsher } 8240adfc5217SJeff Kirsher } 8241adfc5217SJeff Kirsher } 8242adfc5217SJeff Kirsher 8243adfc5217SJeff Kirsher bnx2_set_default_link(bp); 8244adfc5217SJeff Kirsher bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; 8245adfc5217SJeff Kirsher 8246adfc5217SJeff Kirsher init_timer(&bp->timer); 8247adfc5217SJeff Kirsher bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL); 8248adfc5217SJeff Kirsher bp->timer.data = (unsigned long) bp; 8249adfc5217SJeff Kirsher bp->timer.function = bnx2_timer; 8250adfc5217SJeff Kirsher 8251adfc5217SJeff Kirsher #ifdef BCM_CNIC 8252adfc5217SJeff Kirsher if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN) 8253adfc5217SJeff Kirsher bp->cnic_eth_dev.max_iscsi_conn = 8254adfc5217SJeff Kirsher (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) & 8255adfc5217SJeff Kirsher BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT; 8256adfc5217SJeff Kirsher #endif 8257adfc5217SJeff Kirsher pci_save_state(pdev); 8258adfc5217SJeff Kirsher 8259adfc5217SJeff Kirsher return 0; 8260adfc5217SJeff Kirsher 8261adfc5217SJeff Kirsher err_out_unmap: 8262adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_AER_ENABLED) { 8263adfc5217SJeff Kirsher pci_disable_pcie_error_reporting(pdev); 8264adfc5217SJeff Kirsher bp->flags &= ~BNX2_FLAG_AER_ENABLED; 8265adfc5217SJeff Kirsher } 8266adfc5217SJeff Kirsher 8267adfc5217SJeff Kirsher if (bp->regview) { 8268adfc5217SJeff Kirsher iounmap(bp->regview); 8269adfc5217SJeff Kirsher bp->regview = NULL; 8270adfc5217SJeff Kirsher } 8271adfc5217SJeff Kirsher 8272adfc5217SJeff Kirsher err_out_release: 8273adfc5217SJeff Kirsher pci_release_regions(pdev); 8274adfc5217SJeff Kirsher 8275adfc5217SJeff Kirsher err_out_disable: 8276adfc5217SJeff Kirsher pci_disable_device(pdev); 8277adfc5217SJeff Kirsher pci_set_drvdata(pdev, NULL); 8278adfc5217SJeff Kirsher 8279adfc5217SJeff Kirsher err_out: 8280adfc5217SJeff Kirsher return rc; 8281adfc5217SJeff Kirsher } 8282adfc5217SJeff Kirsher 8283adfc5217SJeff Kirsher static char * __devinit 8284adfc5217SJeff Kirsher bnx2_bus_string(struct bnx2 *bp, char *str) 8285adfc5217SJeff Kirsher { 8286adfc5217SJeff Kirsher char *s = str; 8287adfc5217SJeff Kirsher 8288adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_PCIE) { 8289adfc5217SJeff Kirsher s += sprintf(s, "PCI Express"); 8290adfc5217SJeff Kirsher } else { 8291adfc5217SJeff Kirsher s += sprintf(s, "PCI"); 8292adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_PCIX) 8293adfc5217SJeff Kirsher s += sprintf(s, "-X"); 8294adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_PCI_32BIT) 8295adfc5217SJeff Kirsher s += sprintf(s, " 32-bit"); 8296adfc5217SJeff Kirsher else 8297adfc5217SJeff Kirsher s += sprintf(s, " 64-bit"); 8298adfc5217SJeff Kirsher s += sprintf(s, " %dMHz", bp->bus_speed_mhz); 8299adfc5217SJeff Kirsher } 8300adfc5217SJeff Kirsher return str; 8301adfc5217SJeff Kirsher } 8302adfc5217SJeff Kirsher 8303adfc5217SJeff Kirsher static void 8304adfc5217SJeff Kirsher bnx2_del_napi(struct bnx2 *bp) 8305adfc5217SJeff Kirsher { 8306adfc5217SJeff Kirsher int i; 8307adfc5217SJeff Kirsher 8308adfc5217SJeff Kirsher for (i = 0; i < bp->irq_nvecs; i++) 8309adfc5217SJeff Kirsher netif_napi_del(&bp->bnx2_napi[i].napi); 8310adfc5217SJeff Kirsher } 8311adfc5217SJeff Kirsher 8312adfc5217SJeff Kirsher static void 8313adfc5217SJeff Kirsher bnx2_init_napi(struct bnx2 *bp) 8314adfc5217SJeff Kirsher { 8315adfc5217SJeff Kirsher int i; 8316adfc5217SJeff Kirsher 8317adfc5217SJeff Kirsher for (i = 0; i < bp->irq_nvecs; i++) { 8318adfc5217SJeff Kirsher struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 8319adfc5217SJeff Kirsher int (*poll)(struct napi_struct *, int); 8320adfc5217SJeff Kirsher 8321adfc5217SJeff Kirsher if (i == 0) 8322adfc5217SJeff Kirsher poll = bnx2_poll; 8323adfc5217SJeff Kirsher else 8324adfc5217SJeff Kirsher poll = bnx2_poll_msix; 8325adfc5217SJeff Kirsher 8326adfc5217SJeff Kirsher netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64); 8327adfc5217SJeff Kirsher bnapi->bp = bp; 8328adfc5217SJeff Kirsher } 8329adfc5217SJeff Kirsher } 8330adfc5217SJeff Kirsher 8331adfc5217SJeff Kirsher static const struct net_device_ops bnx2_netdev_ops = { 8332adfc5217SJeff Kirsher .ndo_open = bnx2_open, 8333adfc5217SJeff Kirsher .ndo_start_xmit = bnx2_start_xmit, 8334adfc5217SJeff Kirsher .ndo_stop = bnx2_close, 8335adfc5217SJeff Kirsher .ndo_get_stats64 = bnx2_get_stats64, 8336adfc5217SJeff Kirsher .ndo_set_rx_mode = bnx2_set_rx_mode, 8337adfc5217SJeff Kirsher .ndo_do_ioctl = bnx2_ioctl, 8338adfc5217SJeff Kirsher .ndo_validate_addr = eth_validate_addr, 8339adfc5217SJeff Kirsher .ndo_set_mac_address = bnx2_change_mac_addr, 8340adfc5217SJeff Kirsher .ndo_change_mtu = bnx2_change_mtu, 8341adfc5217SJeff Kirsher .ndo_fix_features = bnx2_fix_features, 8342adfc5217SJeff Kirsher .ndo_set_features = bnx2_set_features, 8343adfc5217SJeff Kirsher .ndo_tx_timeout = bnx2_tx_timeout, 8344adfc5217SJeff Kirsher #ifdef CONFIG_NET_POLL_CONTROLLER 8345adfc5217SJeff Kirsher .ndo_poll_controller = poll_bnx2, 8346adfc5217SJeff Kirsher #endif 8347adfc5217SJeff Kirsher }; 8348adfc5217SJeff Kirsher 8349adfc5217SJeff Kirsher static int __devinit 8350adfc5217SJeff Kirsher bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 8351adfc5217SJeff Kirsher { 8352adfc5217SJeff Kirsher static int version_printed = 0; 8353adfc5217SJeff Kirsher struct net_device *dev = NULL; 8354adfc5217SJeff Kirsher struct bnx2 *bp; 8355adfc5217SJeff Kirsher int rc; 8356adfc5217SJeff Kirsher char str[40]; 8357adfc5217SJeff Kirsher 8358adfc5217SJeff Kirsher if (version_printed++ == 0) 8359adfc5217SJeff Kirsher pr_info("%s", version); 8360adfc5217SJeff Kirsher 8361adfc5217SJeff Kirsher /* dev zeroed in init_etherdev */ 8362adfc5217SJeff Kirsher dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS); 8363adfc5217SJeff Kirsher 8364adfc5217SJeff Kirsher if (!dev) 8365adfc5217SJeff Kirsher return -ENOMEM; 8366adfc5217SJeff Kirsher 8367adfc5217SJeff Kirsher rc = bnx2_init_board(pdev, dev); 8368adfc5217SJeff Kirsher if (rc < 0) { 8369adfc5217SJeff Kirsher free_netdev(dev); 8370adfc5217SJeff Kirsher return rc; 8371adfc5217SJeff Kirsher } 8372adfc5217SJeff Kirsher 8373adfc5217SJeff Kirsher dev->netdev_ops = &bnx2_netdev_ops; 8374adfc5217SJeff Kirsher dev->watchdog_timeo = TX_TIMEOUT; 8375adfc5217SJeff Kirsher dev->ethtool_ops = &bnx2_ethtool_ops; 8376adfc5217SJeff Kirsher 8377adfc5217SJeff Kirsher bp = netdev_priv(dev); 8378adfc5217SJeff Kirsher 8379adfc5217SJeff Kirsher pci_set_drvdata(pdev, dev); 8380adfc5217SJeff Kirsher 8381adfc5217SJeff Kirsher memcpy(dev->dev_addr, bp->mac_addr, 6); 8382adfc5217SJeff Kirsher memcpy(dev->perm_addr, bp->mac_addr, 6); 8383adfc5217SJeff Kirsher 8384adfc5217SJeff Kirsher dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 8385adfc5217SJeff Kirsher NETIF_F_TSO | NETIF_F_TSO_ECN | 8386adfc5217SJeff Kirsher NETIF_F_RXHASH | NETIF_F_RXCSUM; 8387adfc5217SJeff Kirsher 8388adfc5217SJeff Kirsher if (CHIP_NUM(bp) == CHIP_NUM_5709) 8389adfc5217SJeff Kirsher dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 8390adfc5217SJeff Kirsher 8391adfc5217SJeff Kirsher dev->vlan_features = dev->hw_features; 8392adfc5217SJeff Kirsher dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 8393adfc5217SJeff Kirsher dev->features |= dev->hw_features; 839401789349SJiri Pirko dev->priv_flags |= IFF_UNICAST_FLT; 8395adfc5217SJeff Kirsher 8396adfc5217SJeff Kirsher if ((rc = register_netdev(dev))) { 8397adfc5217SJeff Kirsher dev_err(&pdev->dev, "Cannot register net device\n"); 8398adfc5217SJeff Kirsher goto error; 8399adfc5217SJeff Kirsher } 8400adfc5217SJeff Kirsher 8401adfc5217SJeff Kirsher netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n", 8402adfc5217SJeff Kirsher board_info[ent->driver_data].name, 8403adfc5217SJeff Kirsher ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', 8404adfc5217SJeff Kirsher ((CHIP_ID(bp) & 0x0ff0) >> 4), 8405adfc5217SJeff Kirsher bnx2_bus_string(bp, str), 8406adfc5217SJeff Kirsher dev->base_addr, 8407adfc5217SJeff Kirsher bp->pdev->irq, dev->dev_addr); 8408adfc5217SJeff Kirsher 8409adfc5217SJeff Kirsher return 0; 8410adfc5217SJeff Kirsher 8411adfc5217SJeff Kirsher error: 8412adfc5217SJeff Kirsher if (bp->regview) 8413adfc5217SJeff Kirsher iounmap(bp->regview); 8414adfc5217SJeff Kirsher pci_release_regions(pdev); 8415adfc5217SJeff Kirsher pci_disable_device(pdev); 8416adfc5217SJeff Kirsher pci_set_drvdata(pdev, NULL); 8417adfc5217SJeff Kirsher free_netdev(dev); 8418adfc5217SJeff Kirsher return rc; 8419adfc5217SJeff Kirsher } 8420adfc5217SJeff Kirsher 8421adfc5217SJeff Kirsher static void __devexit 8422adfc5217SJeff Kirsher bnx2_remove_one(struct pci_dev *pdev) 8423adfc5217SJeff Kirsher { 8424adfc5217SJeff Kirsher struct net_device *dev = pci_get_drvdata(pdev); 8425adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 8426adfc5217SJeff Kirsher 8427adfc5217SJeff Kirsher unregister_netdev(dev); 8428adfc5217SJeff Kirsher 8429adfc5217SJeff Kirsher del_timer_sync(&bp->timer); 8430adfc5217SJeff Kirsher cancel_work_sync(&bp->reset_task); 8431adfc5217SJeff Kirsher 8432adfc5217SJeff Kirsher if (bp->regview) 8433adfc5217SJeff Kirsher iounmap(bp->regview); 8434adfc5217SJeff Kirsher 8435adfc5217SJeff Kirsher kfree(bp->temp_stats_blk); 8436adfc5217SJeff Kirsher 8437adfc5217SJeff Kirsher if (bp->flags & BNX2_FLAG_AER_ENABLED) { 8438adfc5217SJeff Kirsher pci_disable_pcie_error_reporting(pdev); 8439adfc5217SJeff Kirsher bp->flags &= ~BNX2_FLAG_AER_ENABLED; 8440adfc5217SJeff Kirsher } 8441adfc5217SJeff Kirsher 84427880b72eSfrançois romieu bnx2_release_firmware(bp); 84437880b72eSfrançois romieu 8444adfc5217SJeff Kirsher free_netdev(dev); 8445adfc5217SJeff Kirsher 8446adfc5217SJeff Kirsher pci_release_regions(pdev); 8447adfc5217SJeff Kirsher pci_disable_device(pdev); 8448adfc5217SJeff Kirsher pci_set_drvdata(pdev, NULL); 8449adfc5217SJeff Kirsher } 8450adfc5217SJeff Kirsher 8451adfc5217SJeff Kirsher static int 8452adfc5217SJeff Kirsher bnx2_suspend(struct pci_dev *pdev, pm_message_t state) 8453adfc5217SJeff Kirsher { 8454adfc5217SJeff Kirsher struct net_device *dev = pci_get_drvdata(pdev); 8455adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 8456adfc5217SJeff Kirsher 8457adfc5217SJeff Kirsher /* PCI register 4 needs to be saved whether netif_running() or not. 8458adfc5217SJeff Kirsher * MSI address and data need to be saved if using MSI and 8459adfc5217SJeff Kirsher * netif_running(). 8460adfc5217SJeff Kirsher */ 8461adfc5217SJeff Kirsher pci_save_state(pdev); 8462adfc5217SJeff Kirsher if (!netif_running(dev)) 8463adfc5217SJeff Kirsher return 0; 8464adfc5217SJeff Kirsher 8465adfc5217SJeff Kirsher cancel_work_sync(&bp->reset_task); 8466adfc5217SJeff Kirsher bnx2_netif_stop(bp, true); 8467adfc5217SJeff Kirsher netif_device_detach(dev); 8468adfc5217SJeff Kirsher del_timer_sync(&bp->timer); 8469adfc5217SJeff Kirsher bnx2_shutdown_chip(bp); 8470adfc5217SJeff Kirsher bnx2_free_skbs(bp); 8471adfc5217SJeff Kirsher bnx2_set_power_state(bp, pci_choose_state(pdev, state)); 8472adfc5217SJeff Kirsher return 0; 8473adfc5217SJeff Kirsher } 8474adfc5217SJeff Kirsher 8475adfc5217SJeff Kirsher static int 8476adfc5217SJeff Kirsher bnx2_resume(struct pci_dev *pdev) 8477adfc5217SJeff Kirsher { 8478adfc5217SJeff Kirsher struct net_device *dev = pci_get_drvdata(pdev); 8479adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 8480adfc5217SJeff Kirsher 8481adfc5217SJeff Kirsher pci_restore_state(pdev); 8482adfc5217SJeff Kirsher if (!netif_running(dev)) 8483adfc5217SJeff Kirsher return 0; 8484adfc5217SJeff Kirsher 8485adfc5217SJeff Kirsher bnx2_set_power_state(bp, PCI_D0); 8486adfc5217SJeff Kirsher netif_device_attach(dev); 8487adfc5217SJeff Kirsher bnx2_init_nic(bp, 1); 8488adfc5217SJeff Kirsher bnx2_netif_start(bp, true); 8489adfc5217SJeff Kirsher return 0; 8490adfc5217SJeff Kirsher } 8491adfc5217SJeff Kirsher 8492adfc5217SJeff Kirsher /** 8493adfc5217SJeff Kirsher * bnx2_io_error_detected - called when PCI error is detected 8494adfc5217SJeff Kirsher * @pdev: Pointer to PCI device 8495adfc5217SJeff Kirsher * @state: The current pci connection state 8496adfc5217SJeff Kirsher * 8497adfc5217SJeff Kirsher * This function is called after a PCI bus error affecting 8498adfc5217SJeff Kirsher * this device has been detected. 8499adfc5217SJeff Kirsher */ 8500adfc5217SJeff Kirsher static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev, 8501adfc5217SJeff Kirsher pci_channel_state_t state) 8502adfc5217SJeff Kirsher { 8503adfc5217SJeff Kirsher struct net_device *dev = pci_get_drvdata(pdev); 8504adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 8505adfc5217SJeff Kirsher 8506adfc5217SJeff Kirsher rtnl_lock(); 8507adfc5217SJeff Kirsher netif_device_detach(dev); 8508adfc5217SJeff Kirsher 8509adfc5217SJeff Kirsher if (state == pci_channel_io_perm_failure) { 8510adfc5217SJeff Kirsher rtnl_unlock(); 8511adfc5217SJeff Kirsher return PCI_ERS_RESULT_DISCONNECT; 8512adfc5217SJeff Kirsher } 8513adfc5217SJeff Kirsher 8514adfc5217SJeff Kirsher if (netif_running(dev)) { 8515adfc5217SJeff Kirsher bnx2_netif_stop(bp, true); 8516adfc5217SJeff Kirsher del_timer_sync(&bp->timer); 8517adfc5217SJeff Kirsher bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); 8518adfc5217SJeff Kirsher } 8519adfc5217SJeff Kirsher 8520adfc5217SJeff Kirsher pci_disable_device(pdev); 8521adfc5217SJeff Kirsher rtnl_unlock(); 8522adfc5217SJeff Kirsher 8523adfc5217SJeff Kirsher /* Request a slot slot reset. */ 8524adfc5217SJeff Kirsher return PCI_ERS_RESULT_NEED_RESET; 8525adfc5217SJeff Kirsher } 8526adfc5217SJeff Kirsher 8527adfc5217SJeff Kirsher /** 8528adfc5217SJeff Kirsher * bnx2_io_slot_reset - called after the pci bus has been reset. 8529adfc5217SJeff Kirsher * @pdev: Pointer to PCI device 8530adfc5217SJeff Kirsher * 8531adfc5217SJeff Kirsher * Restart the card from scratch, as if from a cold-boot. 8532adfc5217SJeff Kirsher */ 8533adfc5217SJeff Kirsher static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev) 8534adfc5217SJeff Kirsher { 8535adfc5217SJeff Kirsher struct net_device *dev = pci_get_drvdata(pdev); 8536adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 8537adfc5217SJeff Kirsher pci_ers_result_t result; 8538adfc5217SJeff Kirsher int err; 8539adfc5217SJeff Kirsher 8540adfc5217SJeff Kirsher rtnl_lock(); 8541adfc5217SJeff Kirsher if (pci_enable_device(pdev)) { 8542adfc5217SJeff Kirsher dev_err(&pdev->dev, 8543adfc5217SJeff Kirsher "Cannot re-enable PCI device after reset\n"); 8544adfc5217SJeff Kirsher result = PCI_ERS_RESULT_DISCONNECT; 8545adfc5217SJeff Kirsher } else { 8546adfc5217SJeff Kirsher pci_set_master(pdev); 8547adfc5217SJeff Kirsher pci_restore_state(pdev); 8548adfc5217SJeff Kirsher pci_save_state(pdev); 8549adfc5217SJeff Kirsher 8550adfc5217SJeff Kirsher if (netif_running(dev)) { 8551adfc5217SJeff Kirsher bnx2_set_power_state(bp, PCI_D0); 8552adfc5217SJeff Kirsher bnx2_init_nic(bp, 1); 8553adfc5217SJeff Kirsher } 8554adfc5217SJeff Kirsher result = PCI_ERS_RESULT_RECOVERED; 8555adfc5217SJeff Kirsher } 8556adfc5217SJeff Kirsher rtnl_unlock(); 8557adfc5217SJeff Kirsher 8558adfc5217SJeff Kirsher if (!(bp->flags & BNX2_FLAG_AER_ENABLED)) 8559adfc5217SJeff Kirsher return result; 8560adfc5217SJeff Kirsher 8561adfc5217SJeff Kirsher err = pci_cleanup_aer_uncorrect_error_status(pdev); 8562adfc5217SJeff Kirsher if (err) { 8563adfc5217SJeff Kirsher dev_err(&pdev->dev, 8564adfc5217SJeff Kirsher "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 8565adfc5217SJeff Kirsher err); /* non-fatal, continue */ 8566adfc5217SJeff Kirsher } 8567adfc5217SJeff Kirsher 8568adfc5217SJeff Kirsher return result; 8569adfc5217SJeff Kirsher } 8570adfc5217SJeff Kirsher 8571adfc5217SJeff Kirsher /** 8572adfc5217SJeff Kirsher * bnx2_io_resume - called when traffic can start flowing again. 8573adfc5217SJeff Kirsher * @pdev: Pointer to PCI device 8574adfc5217SJeff Kirsher * 8575adfc5217SJeff Kirsher * This callback is called when the error recovery driver tells us that 8576adfc5217SJeff Kirsher * its OK to resume normal operation. 8577adfc5217SJeff Kirsher */ 8578adfc5217SJeff Kirsher static void bnx2_io_resume(struct pci_dev *pdev) 8579adfc5217SJeff Kirsher { 8580adfc5217SJeff Kirsher struct net_device *dev = pci_get_drvdata(pdev); 8581adfc5217SJeff Kirsher struct bnx2 *bp = netdev_priv(dev); 8582adfc5217SJeff Kirsher 8583adfc5217SJeff Kirsher rtnl_lock(); 8584adfc5217SJeff Kirsher if (netif_running(dev)) 8585adfc5217SJeff Kirsher bnx2_netif_start(bp, true); 8586adfc5217SJeff Kirsher 8587adfc5217SJeff Kirsher netif_device_attach(dev); 8588adfc5217SJeff Kirsher rtnl_unlock(); 8589adfc5217SJeff Kirsher } 8590adfc5217SJeff Kirsher 8591adfc5217SJeff Kirsher static struct pci_error_handlers bnx2_err_handler = { 8592adfc5217SJeff Kirsher .error_detected = bnx2_io_error_detected, 8593adfc5217SJeff Kirsher .slot_reset = bnx2_io_slot_reset, 8594adfc5217SJeff Kirsher .resume = bnx2_io_resume, 8595adfc5217SJeff Kirsher }; 8596adfc5217SJeff Kirsher 8597adfc5217SJeff Kirsher static struct pci_driver bnx2_pci_driver = { 8598adfc5217SJeff Kirsher .name = DRV_MODULE_NAME, 8599adfc5217SJeff Kirsher .id_table = bnx2_pci_tbl, 8600adfc5217SJeff Kirsher .probe = bnx2_init_one, 8601adfc5217SJeff Kirsher .remove = __devexit_p(bnx2_remove_one), 8602adfc5217SJeff Kirsher .suspend = bnx2_suspend, 8603adfc5217SJeff Kirsher .resume = bnx2_resume, 8604adfc5217SJeff Kirsher .err_handler = &bnx2_err_handler, 8605adfc5217SJeff Kirsher }; 8606adfc5217SJeff Kirsher 8607adfc5217SJeff Kirsher static int __init bnx2_init(void) 8608adfc5217SJeff Kirsher { 8609adfc5217SJeff Kirsher return pci_register_driver(&bnx2_pci_driver); 8610adfc5217SJeff Kirsher } 8611adfc5217SJeff Kirsher 8612adfc5217SJeff Kirsher static void __exit bnx2_cleanup(void) 8613adfc5217SJeff Kirsher { 8614adfc5217SJeff Kirsher pci_unregister_driver(&bnx2_pci_driver); 8615adfc5217SJeff Kirsher } 8616adfc5217SJeff Kirsher 8617adfc5217SJeff Kirsher module_init(bnx2_init); 8618adfc5217SJeff Kirsher module_exit(bnx2_cleanup); 8619adfc5217SJeff Kirsher 8620adfc5217SJeff Kirsher 8621adfc5217SJeff Kirsher 8622