1 #ifndef _BGMAC_H 2 #define _BGMAC_H 3 4 #include <linux/netdevice.h> 5 6 #define BGMAC_DEV_CTL 0x000 7 #define BGMAC_DC_TSM 0x00000002 8 #define BGMAC_DC_CFCO 0x00000004 9 #define BGMAC_DC_RLSS 0x00000008 10 #define BGMAC_DC_MROR 0x00000010 11 #define BGMAC_DC_FCM_MASK 0x00000060 12 #define BGMAC_DC_FCM_SHIFT 5 13 #define BGMAC_DC_NAE 0x00000080 14 #define BGMAC_DC_TF 0x00000100 15 #define BGMAC_DC_RDS_MASK 0x00030000 16 #define BGMAC_DC_RDS_SHIFT 16 17 #define BGMAC_DC_TDS_MASK 0x000c0000 18 #define BGMAC_DC_TDS_SHIFT 18 19 #define BGMAC_DEV_STATUS 0x004 /* Configuration of the interface */ 20 #define BGMAC_DS_RBF 0x00000001 21 #define BGMAC_DS_RDF 0x00000002 22 #define BGMAC_DS_RIF 0x00000004 23 #define BGMAC_DS_TBF 0x00000008 24 #define BGMAC_DS_TDF 0x00000010 25 #define BGMAC_DS_TIF 0x00000020 26 #define BGMAC_DS_PO 0x00000040 27 #define BGMAC_DS_MM_MASK 0x00000300 /* Mode of the interface */ 28 #define BGMAC_DS_MM_SHIFT 8 29 #define BGMAC_BIST_STATUS 0x00c 30 #define BGMAC_INT_STATUS 0x020 /* Interrupt status */ 31 #define BGMAC_IS_MRO 0x00000001 32 #define BGMAC_IS_MTO 0x00000002 33 #define BGMAC_IS_TFD 0x00000004 34 #define BGMAC_IS_LS 0x00000008 35 #define BGMAC_IS_MDIO 0x00000010 36 #define BGMAC_IS_MR 0x00000020 37 #define BGMAC_IS_MT 0x00000040 38 #define BGMAC_IS_TO 0x00000080 39 #define BGMAC_IS_DESC_ERR 0x00000400 /* Descriptor error */ 40 #define BGMAC_IS_DATA_ERR 0x00000800 /* Data error */ 41 #define BGMAC_IS_DESC_PROT_ERR 0x00001000 /* Descriptor protocol error */ 42 #define BGMAC_IS_RX_DESC_UNDERF 0x00002000 /* Receive descriptor underflow */ 43 #define BGMAC_IS_RX_F_OVERF 0x00004000 /* Receive FIFO overflow */ 44 #define BGMAC_IS_TX_F_UNDERF 0x00008000 /* Transmit FIFO underflow */ 45 #define BGMAC_IS_RX 0x00010000 /* Interrupt for RX queue 0 */ 46 #define BGMAC_IS_TX0 0x01000000 /* Interrupt for TX queue 0 */ 47 #define BGMAC_IS_TX1 0x02000000 /* Interrupt for TX queue 1 */ 48 #define BGMAC_IS_TX2 0x04000000 /* Interrupt for TX queue 2 */ 49 #define BGMAC_IS_TX3 0x08000000 /* Interrupt for TX queue 3 */ 50 #define BGMAC_IS_TX_MASK 0x0f000000 51 #define BGMAC_IS_INTMASK 0x0f01fcff 52 #define BGMAC_IS_ERRMASK 0x0000fc00 53 #define BGMAC_INT_MASK 0x024 /* Interrupt mask */ 54 #define BGMAC_GP_TIMER 0x028 55 #define BGMAC_INT_RECV_LAZY 0x100 56 #define BGMAC_IRL_TO_MASK 0x00ffffff 57 #define BGMAC_IRL_FC_MASK 0xff000000 58 #define BGMAC_IRL_FC_SHIFT 24 /* Shift the number of interrupts triggered per received frame */ 59 #define BGMAC_FLOW_CTL_THRESH 0x104 /* Flow control thresholds */ 60 #define BGMAC_WRRTHRESH 0x108 61 #define BGMAC_GMAC_IDLE_CNT_THRESH 0x10c 62 #define BGMAC_PHY_ACCESS 0x180 /* PHY access address */ 63 #define BGMAC_PA_DATA_MASK 0x0000ffff 64 #define BGMAC_PA_ADDR_MASK 0x001f0000 65 #define BGMAC_PA_ADDR_SHIFT 16 66 #define BGMAC_PA_REG_MASK 0x1f000000 67 #define BGMAC_PA_REG_SHIFT 24 68 #define BGMAC_PA_WRITE 0x20000000 69 #define BGMAC_PA_START 0x40000000 70 #define BGMAC_PHY_CNTL 0x188 /* PHY control address */ 71 #define BGMAC_PC_EPA_MASK 0x0000001f 72 #define BGMAC_PC_MCT_MASK 0x007f0000 73 #define BGMAC_PC_MCT_SHIFT 16 74 #define BGMAC_PC_MTE 0x00800000 75 #define BGMAC_TXQ_CTL 0x18c 76 #define BGMAC_TXQ_CTL_DBT_MASK 0x00000fff 77 #define BGMAC_TXQ_CTL_DBT_SHIFT 0 78 #define BGMAC_RXQ_CTL 0x190 79 #define BGMAC_RXQ_CTL_DBT_MASK 0x00000fff 80 #define BGMAC_RXQ_CTL_DBT_SHIFT 0 81 #define BGMAC_RXQ_CTL_PTE 0x00001000 82 #define BGMAC_RXQ_CTL_MDP_MASK 0x3f000000 83 #define BGMAC_RXQ_CTL_MDP_SHIFT 24 84 #define BGMAC_GPIO_SELECT 0x194 85 #define BGMAC_GPIO_OUTPUT_EN 0x198 86 87 /* For 0x1e0 see BCMA_CLKCTLST. Below are BGMAC specific bits */ 88 #define BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ 0x00000100 89 #define BGMAC_BCMA_CLKCTLST_MISC_PLL_ST 0x01000000 90 91 #define BGMAC_HW_WAR 0x1e4 92 #define BGMAC_PWR_CTL 0x1e8 93 #define BGMAC_DMA_BASE0 0x200 /* Tx and Rx controller */ 94 #define BGMAC_DMA_BASE1 0x240 /* Tx controller only */ 95 #define BGMAC_DMA_BASE2 0x280 /* Tx controller only */ 96 #define BGMAC_DMA_BASE3 0x2C0 /* Tx controller only */ 97 #define BGMAC_TX_GOOD_OCTETS 0x300 98 #define BGMAC_TX_GOOD_OCTETS_HIGH 0x304 99 #define BGMAC_TX_GOOD_PKTS 0x308 100 #define BGMAC_TX_OCTETS 0x30c 101 #define BGMAC_TX_OCTETS_HIGH 0x310 102 #define BGMAC_TX_PKTS 0x314 103 #define BGMAC_TX_BROADCAST_PKTS 0x318 104 #define BGMAC_TX_MULTICAST_PKTS 0x31c 105 #define BGMAC_TX_LEN_64 0x320 106 #define BGMAC_TX_LEN_65_TO_127 0x324 107 #define BGMAC_TX_LEN_128_TO_255 0x328 108 #define BGMAC_TX_LEN_256_TO_511 0x32c 109 #define BGMAC_TX_LEN_512_TO_1023 0x330 110 #define BGMAC_TX_LEN_1024_TO_1522 0x334 111 #define BGMAC_TX_LEN_1523_TO_2047 0x338 112 #define BGMAC_TX_LEN_2048_TO_4095 0x33c 113 #define BGMAC_TX_LEN_4096_TO_8191 0x340 114 #define BGMAC_TX_LEN_8192_TO_MAX 0x344 115 #define BGMAC_TX_JABBER_PKTS 0x348 /* Error */ 116 #define BGMAC_TX_OVERSIZE_PKTS 0x34c /* Error */ 117 #define BGMAC_TX_FRAGMENT_PKTS 0x350 118 #define BGMAC_TX_UNDERRUNS 0x354 /* Error */ 119 #define BGMAC_TX_TOTAL_COLS 0x358 120 #define BGMAC_TX_SINGLE_COLS 0x35c 121 #define BGMAC_TX_MULTIPLE_COLS 0x360 122 #define BGMAC_TX_EXCESSIVE_COLS 0x364 /* Error */ 123 #define BGMAC_TX_LATE_COLS 0x368 /* Error */ 124 #define BGMAC_TX_DEFERED 0x36c 125 #define BGMAC_TX_CARRIER_LOST 0x370 126 #define BGMAC_TX_PAUSE_PKTS 0x374 127 #define BGMAC_TX_UNI_PKTS 0x378 128 #define BGMAC_TX_Q0_PKTS 0x37c 129 #define BGMAC_TX_Q0_OCTETS 0x380 130 #define BGMAC_TX_Q0_OCTETS_HIGH 0x384 131 #define BGMAC_TX_Q1_PKTS 0x388 132 #define BGMAC_TX_Q1_OCTETS 0x38c 133 #define BGMAC_TX_Q1_OCTETS_HIGH 0x390 134 #define BGMAC_TX_Q2_PKTS 0x394 135 #define BGMAC_TX_Q2_OCTETS 0x398 136 #define BGMAC_TX_Q2_OCTETS_HIGH 0x39c 137 #define BGMAC_TX_Q3_PKTS 0x3a0 138 #define BGMAC_TX_Q3_OCTETS 0x3a4 139 #define BGMAC_TX_Q3_OCTETS_HIGH 0x3a8 140 #define BGMAC_RX_GOOD_OCTETS 0x3b0 141 #define BGMAC_RX_GOOD_OCTETS_HIGH 0x3b4 142 #define BGMAC_RX_GOOD_PKTS 0x3b8 143 #define BGMAC_RX_OCTETS 0x3bc 144 #define BGMAC_RX_OCTETS_HIGH 0x3c0 145 #define BGMAC_RX_PKTS 0x3c4 146 #define BGMAC_RX_BROADCAST_PKTS 0x3c8 147 #define BGMAC_RX_MULTICAST_PKTS 0x3cc 148 #define BGMAC_RX_LEN_64 0x3d0 149 #define BGMAC_RX_LEN_65_TO_127 0x3d4 150 #define BGMAC_RX_LEN_128_TO_255 0x3d8 151 #define BGMAC_RX_LEN_256_TO_511 0x3dc 152 #define BGMAC_RX_LEN_512_TO_1023 0x3e0 153 #define BGMAC_RX_LEN_1024_TO_1522 0x3e4 154 #define BGMAC_RX_LEN_1523_TO_2047 0x3e8 155 #define BGMAC_RX_LEN_2048_TO_4095 0x3ec 156 #define BGMAC_RX_LEN_4096_TO_8191 0x3f0 157 #define BGMAC_RX_LEN_8192_TO_MAX 0x3f4 158 #define BGMAC_RX_JABBER_PKTS 0x3f8 /* Error */ 159 #define BGMAC_RX_OVERSIZE_PKTS 0x3fc /* Error */ 160 #define BGMAC_RX_FRAGMENT_PKTS 0x400 161 #define BGMAC_RX_MISSED_PKTS 0x404 /* Error */ 162 #define BGMAC_RX_CRC_ALIGN_ERRS 0x408 /* Error */ 163 #define BGMAC_RX_UNDERSIZE 0x40c /* Error */ 164 #define BGMAC_RX_CRC_ERRS 0x410 /* Error */ 165 #define BGMAC_RX_ALIGN_ERRS 0x414 /* Error */ 166 #define BGMAC_RX_SYMBOL_ERRS 0x418 /* Error */ 167 #define BGMAC_RX_PAUSE_PKTS 0x41c 168 #define BGMAC_RX_NONPAUSE_PKTS 0x420 169 #define BGMAC_RX_SACHANGES 0x424 170 #define BGMAC_RX_UNI_PKTS 0x428 171 #define BGMAC_UNIMAC_VERSION 0x800 172 #define BGMAC_HDBKP_CTL 0x804 173 #define BGMAC_CMDCFG 0x808 /* Configuration */ 174 #define BGMAC_CMDCFG_TE 0x00000001 /* Set to activate TX */ 175 #define BGMAC_CMDCFG_RE 0x00000002 /* Set to activate RX */ 176 #define BGMAC_CMDCFG_ES_MASK 0x0000000c /* Ethernet speed see gmac_speed */ 177 #define BGMAC_CMDCFG_ES_10 0x00000000 178 #define BGMAC_CMDCFG_ES_100 0x00000004 179 #define BGMAC_CMDCFG_ES_1000 0x00000008 180 #define BGMAC_CMDCFG_ES_2500 0x0000000C 181 #define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */ 182 #define BGMAC_CMDCFG_PAD_EN 0x00000020 183 #define BGMAC_CMDCFG_CF 0x00000040 184 #define BGMAC_CMDCFG_PF 0x00000080 185 #define BGMAC_CMDCFG_RPI 0x00000100 /* Unset to enable 802.3x tx flow control */ 186 #define BGMAC_CMDCFG_TAI 0x00000200 187 #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */ 188 #define BGMAC_CMDCFG_HD_SHIFT 10 189 #define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for core rev 0-3 */ 190 #define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, for core rev >= 4 */ 191 #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */ 192 #define BGMAC_CMDCFG_AE 0x00400000 193 #define BGMAC_CMDCFG_CFE 0x00800000 194 #define BGMAC_CMDCFG_NLC 0x01000000 195 #define BGMAC_CMDCFG_RL 0x02000000 196 #define BGMAC_CMDCFG_RED 0x04000000 197 #define BGMAC_CMDCFG_PE 0x08000000 198 #define BGMAC_CMDCFG_TPI 0x10000000 199 #define BGMAC_CMDCFG_AT 0x20000000 200 #define BGMAC_MACADDR_HIGH 0x80c /* High 4 octets of own mac address */ 201 #define BGMAC_MACADDR_LOW 0x810 /* Low 2 octets of own mac address */ 202 #define BGMAC_RXMAX_LENGTH 0x814 /* Max receive frame length with vlan tag */ 203 #define BGMAC_PAUSEQUANTA 0x818 204 #define BGMAC_MAC_MODE 0x844 205 #define BGMAC_OUTERTAG 0x848 206 #define BGMAC_INNERTAG 0x84c 207 #define BGMAC_TXIPG 0x85c 208 #define BGMAC_PAUSE_CTL 0xb30 209 #define BGMAC_TX_FLUSH 0xb34 210 #define BGMAC_RX_STATUS 0xb38 211 #define BGMAC_TX_STATUS 0xb3c 212 213 /* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */ 214 #define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */ 215 #define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */ 216 /* The IOCTL values appear to be different in NS, NSP, and NS2, and do not match 217 * the values directly above 218 */ 219 #define BGMAC_CLK_EN BIT(0) 220 #define BGMAC_RESERVED_0 BIT(1) 221 #define BGMAC_SOURCE_SYNC_MODE_EN BIT(2) 222 #define BGMAC_DEST_SYNC_MODE_EN BIT(3) 223 #define BGMAC_TX_CLK_OUT_INVERT_EN BIT(4) 224 #define BGMAC_DIRECT_GMII_MODE BIT(5) 225 #define BGMAC_CLK_250_SEL BIT(6) 226 #define BGMAC_AWCACHE (0xf << 7) 227 #define BGMAC_RESERVED_1 (0x1f << 11) 228 #define BGMAC_ARCACHE (0xf << 16) 229 #define BGMAC_AWUSER (0x3f << 20) 230 #define BGMAC_ARUSER (0x3f << 26) 231 #define BGMAC_RESERVED BIT(31) 232 233 /* BCMA GMAC core specific IO status (BCMA_IOST) flags */ 234 #define BGMAC_BCMA_IOST_ATTACHED 0x00000800 235 236 #define BGMAC_NUM_MIB_TX_REGS \ 237 (((BGMAC_TX_Q3_OCTETS_HIGH - BGMAC_TX_GOOD_OCTETS) / 4) + 1) 238 #define BGMAC_NUM_MIB_RX_REGS \ 239 (((BGMAC_RX_UNI_PKTS - BGMAC_RX_GOOD_OCTETS) / 4) + 1) 240 241 #define BGMAC_DMA_TX_CTL 0x00 242 #define BGMAC_DMA_TX_ENABLE 0x00000001 243 #define BGMAC_DMA_TX_SUSPEND 0x00000002 244 #define BGMAC_DMA_TX_LOOPBACK 0x00000004 245 #define BGMAC_DMA_TX_FLUSH 0x00000010 246 #define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */ 247 #define BGMAC_DMA_TX_MR_SHIFT 6 248 #define BGMAC_DMA_TX_MR_1 0 249 #define BGMAC_DMA_TX_MR_2 1 250 #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800 251 #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000 252 #define BGMAC_DMA_TX_ADDREXT_SHIFT 16 253 #define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */ 254 #define BGMAC_DMA_TX_BL_SHIFT 18 255 #define BGMAC_DMA_TX_BL_16 0 256 #define BGMAC_DMA_TX_BL_32 1 257 #define BGMAC_DMA_TX_BL_64 2 258 #define BGMAC_DMA_TX_BL_128 3 259 #define BGMAC_DMA_TX_BL_256 4 260 #define BGMAC_DMA_TX_BL_512 5 261 #define BGMAC_DMA_TX_BL_1024 6 262 #define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */ 263 #define BGMAC_DMA_TX_PC_SHIFT 21 264 #define BGMAC_DMA_TX_PC_0 0 265 #define BGMAC_DMA_TX_PC_4 1 266 #define BGMAC_DMA_TX_PC_8 2 267 #define BGMAC_DMA_TX_PC_16 3 268 #define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */ 269 #define BGMAC_DMA_TX_PT_SHIFT 24 270 #define BGMAC_DMA_TX_PT_1 0 271 #define BGMAC_DMA_TX_PT_2 1 272 #define BGMAC_DMA_TX_PT_4 2 273 #define BGMAC_DMA_TX_PT_8 3 274 #define BGMAC_DMA_TX_INDEX 0x04 275 #define BGMAC_DMA_TX_RINGLO 0x08 276 #define BGMAC_DMA_TX_RINGHI 0x0C 277 #define BGMAC_DMA_TX_STATUS 0x10 278 #define BGMAC_DMA_TX_STATDPTR 0x00001FFF 279 #define BGMAC_DMA_TX_STAT 0xF0000000 280 #define BGMAC_DMA_TX_STAT_DISABLED 0x00000000 281 #define BGMAC_DMA_TX_STAT_ACTIVE 0x10000000 282 #define BGMAC_DMA_TX_STAT_IDLEWAIT 0x20000000 283 #define BGMAC_DMA_TX_STAT_STOPPED 0x30000000 284 #define BGMAC_DMA_TX_STAT_SUSP 0x40000000 285 #define BGMAC_DMA_TX_ERROR 0x14 286 #define BGMAC_DMA_TX_ERRDPTR 0x0001FFFF 287 #define BGMAC_DMA_TX_ERR 0xF0000000 288 #define BGMAC_DMA_TX_ERR_NOERR 0x00000000 289 #define BGMAC_DMA_TX_ERR_PROT 0x10000000 290 #define BGMAC_DMA_TX_ERR_UNDERRUN 0x20000000 291 #define BGMAC_DMA_TX_ERR_TRANSFER 0x30000000 292 #define BGMAC_DMA_TX_ERR_DESCREAD 0x40000000 293 #define BGMAC_DMA_TX_ERR_CORE 0x50000000 294 #define BGMAC_DMA_RX_CTL 0x20 295 #define BGMAC_DMA_RX_ENABLE 0x00000001 296 #define BGMAC_DMA_RX_FRAME_OFFSET_MASK 0x000000FE 297 #define BGMAC_DMA_RX_FRAME_OFFSET_SHIFT 1 298 #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100 299 #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400 300 #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800 301 #define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */ 302 #define BGMAC_DMA_RX_MR_SHIFT 6 303 #define BGMAC_DMA_TX_MR_1 0 304 #define BGMAC_DMA_TX_MR_2 1 305 #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000 306 #define BGMAC_DMA_RX_ADDREXT_SHIFT 16 307 #define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */ 308 #define BGMAC_DMA_RX_BL_SHIFT 18 309 #define BGMAC_DMA_RX_BL_16 0 310 #define BGMAC_DMA_RX_BL_32 1 311 #define BGMAC_DMA_RX_BL_64 2 312 #define BGMAC_DMA_RX_BL_128 3 313 #define BGMAC_DMA_RX_BL_256 4 314 #define BGMAC_DMA_RX_BL_512 5 315 #define BGMAC_DMA_RX_BL_1024 6 316 #define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */ 317 #define BGMAC_DMA_RX_PC_SHIFT 21 318 #define BGMAC_DMA_RX_PC_0 0 319 #define BGMAC_DMA_RX_PC_4 1 320 #define BGMAC_DMA_RX_PC_8 2 321 #define BGMAC_DMA_RX_PC_16 3 322 #define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */ 323 #define BGMAC_DMA_RX_PT_SHIFT 24 324 #define BGMAC_DMA_RX_PT_1 0 325 #define BGMAC_DMA_RX_PT_2 1 326 #define BGMAC_DMA_RX_PT_4 2 327 #define BGMAC_DMA_RX_PT_8 3 328 #define BGMAC_DMA_RX_INDEX 0x24 329 #define BGMAC_DMA_RX_RINGLO 0x28 330 #define BGMAC_DMA_RX_RINGHI 0x2C 331 #define BGMAC_DMA_RX_STATUS 0x30 332 #define BGMAC_DMA_RX_STATDPTR 0x00001FFF 333 #define BGMAC_DMA_RX_STAT 0xF0000000 334 #define BGMAC_DMA_RX_STAT_DISABLED 0x00000000 335 #define BGMAC_DMA_RX_STAT_ACTIVE 0x10000000 336 #define BGMAC_DMA_RX_STAT_IDLEWAIT 0x20000000 337 #define BGMAC_DMA_RX_STAT_STOPPED 0x30000000 338 #define BGMAC_DMA_RX_STAT_SUSP 0x40000000 339 #define BGMAC_DMA_RX_ERROR 0x34 340 #define BGMAC_DMA_RX_ERRDPTR 0x0001FFFF 341 #define BGMAC_DMA_RX_ERR 0xF0000000 342 #define BGMAC_DMA_RX_ERR_NOERR 0x00000000 343 #define BGMAC_DMA_RX_ERR_PROT 0x10000000 344 #define BGMAC_DMA_RX_ERR_UNDERRUN 0x20000000 345 #define BGMAC_DMA_RX_ERR_TRANSFER 0x30000000 346 #define BGMAC_DMA_RX_ERR_DESCREAD 0x40000000 347 #define BGMAC_DMA_RX_ERR_CORE 0x50000000 348 349 #define BGMAC_DESC_CTL0_EOT 0x10000000 /* End of ring */ 350 #define BGMAC_DESC_CTL0_IOC 0x20000000 /* IRQ on complete */ 351 #define BGMAC_DESC_CTL0_EOF 0x40000000 /* End of frame */ 352 #define BGMAC_DESC_CTL0_SOF 0x80000000 /* Start of frame */ 353 #define BGMAC_DESC_CTL1_LEN 0x00001FFF 354 355 #define BGMAC_PHY_NOREGS BRCM_PSEUDO_PHY_ADDR 356 #define BGMAC_PHY_MASK 0x1F 357 358 #define BGMAC_MAX_TX_RINGS 4 359 #define BGMAC_MAX_RX_RINGS 1 360 361 #define BGMAC_TX_RING_SLOTS 128 362 #define BGMAC_RX_RING_SLOTS 512 363 364 #define BGMAC_RX_HEADER_LEN 28 /* Last 24 bytes are unused. Well... */ 365 #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ 366 #define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \ 367 BGMAC_RX_FRAME_OFFSET) 368 #define BGMAC_RX_MAX_FRAME_SIZE 1536 /* Copied from b44/tg3 */ 369 #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE) 370 #define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \ 371 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 372 373 #define BGMAC_BFL_ENETROBO 0x0010 /* has ephy roboswitch spi */ 374 #define BGMAC_BFL_ENETADM 0x0080 /* has ADMtek switch */ 375 #define BGMAC_BFL_ENETVLAN 0x0100 /* can do vlan */ 376 377 #define BGMAC_CHIPCTL_1_IF_TYPE_MASK 0x00000030 378 #define BGMAC_CHIPCTL_1_IF_TYPE_RMII 0x00000000 379 #define BGMAC_CHIPCTL_1_IF_TYPE_MII 0x00000010 380 #define BGMAC_CHIPCTL_1_IF_TYPE_RGMII 0x00000020 381 #define BGMAC_CHIPCTL_1_SW_TYPE_MASK 0x000000C0 382 #define BGMAC_CHIPCTL_1_SW_TYPE_EPHY 0x00000000 383 #define BGMAC_CHIPCTL_1_SW_TYPE_EPHYMII 0x00000040 384 #define BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII 0x00000080 385 #define BGMAC_CHIPCTL_1_SW_TYPE_RGMII 0x000000C0 386 #define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS 0x00010000 387 388 #define BGMAC_CHIPCTL_4_IF_TYPE_MASK 0x00003000 389 #define BGMAC_CHIPCTL_4_IF_TYPE_RMII 0x00000000 390 #define BGMAC_CHIPCTL_4_IF_TYPE_MII 0x00001000 391 #define BGMAC_CHIPCTL_4_IF_TYPE_RGMII 0x00002000 392 #define BGMAC_CHIPCTL_4_SW_TYPE_MASK 0x0000C000 393 #define BGMAC_CHIPCTL_4_SW_TYPE_EPHY 0x00000000 394 #define BGMAC_CHIPCTL_4_SW_TYPE_EPHYMII 0x00004000 395 #define BGMAC_CHIPCTL_4_SW_TYPE_EPHYRMII 0x00008000 396 #define BGMAC_CHIPCTL_4_SW_TYPE_RGMII 0x0000C000 397 398 #define BGMAC_CHIPCTL_7_IF_TYPE_MASK 0x000000C0 399 #define BGMAC_CHIPCTL_7_IF_TYPE_RMII 0x00000000 400 #define BGMAC_CHIPCTL_7_IF_TYPE_MII 0x00000040 401 #define BGMAC_CHIPCTL_7_IF_TYPE_RGMII 0x00000080 402 403 #define BGMAC_WEIGHT 64 404 405 #define ETHER_MAX_LEN (ETH_FRAME_LEN + ETH_FCS_LEN) 406 407 /* Feature Flags */ 408 #define BGMAC_FEAT_TX_MASK_SETUP BIT(0) 409 #define BGMAC_FEAT_RX_MASK_SETUP BIT(1) 410 #define BGMAC_FEAT_IOST_ATTACHED BIT(2) 411 #define BGMAC_FEAT_NO_RESET BIT(3) 412 #define BGMAC_FEAT_MISC_PLL_REQ BIT(4) 413 #define BGMAC_FEAT_SW_TYPE_PHY BIT(5) 414 #define BGMAC_FEAT_SW_TYPE_EPHYRMII BIT(6) 415 #define BGMAC_FEAT_SW_TYPE_RGMII BIT(7) 416 #define BGMAC_FEAT_CMN_PHY_CTL BIT(8) 417 #define BGMAC_FEAT_FLW_CTRL1 BIT(9) 418 #define BGMAC_FEAT_FLW_CTRL2 BIT(10) 419 #define BGMAC_FEAT_SET_RXQ_CLK BIT(11) 420 #define BGMAC_FEAT_CLKCTLST BIT(12) 421 #define BGMAC_FEAT_NO_CLR_MIB BIT(13) 422 #define BGMAC_FEAT_FORCE_SPEED_2500 BIT(14) 423 #define BGMAC_FEAT_CMDCFG_SR_REV4 BIT(15) 424 #define BGMAC_FEAT_IRQ_ID_OOB_6 BIT(16) 425 #define BGMAC_FEAT_CC4_IF_SW_TYPE BIT(17) 426 #define BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII BIT(18) 427 #define BGMAC_FEAT_CC7_IF_TYPE_RGMII BIT(19) 428 429 struct bgmac_slot_info { 430 union { 431 struct sk_buff *skb; 432 void *buf; 433 }; 434 dma_addr_t dma_addr; 435 }; 436 437 struct bgmac_dma_desc { 438 __le32 ctl0; 439 __le32 ctl1; 440 __le32 addr_low; 441 __le32 addr_high; 442 } __packed; 443 444 enum bgmac_dma_ring_type { 445 BGMAC_DMA_RING_TX, 446 BGMAC_DMA_RING_RX, 447 }; 448 449 /** 450 * bgmac_dma_ring - contains info about DMA ring (either TX or RX one) 451 * @start: index of the first slot containing data 452 * @end: index of a slot that can *not* be read (yet) 453 * 454 * Be really aware of the specific @end meaning. It's an index of a slot *after* 455 * the one containing data that can be read. If @start equals @end the ring is 456 * empty. 457 */ 458 struct bgmac_dma_ring { 459 u32 start; 460 u32 end; 461 462 struct bgmac_dma_desc *cpu_base; 463 dma_addr_t dma_base; 464 u32 index_base; /* Used for unaligned rings only, otherwise 0 */ 465 u16 mmio_base; 466 bool unaligned; 467 468 struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS]; 469 }; 470 471 struct bgmac_rx_header { 472 __le16 len; 473 __le16 flags; 474 __le16 pad[12]; 475 }; 476 477 struct bgmac { 478 union { 479 struct { 480 void *base; 481 void *idm_base; 482 void *nicpm_base; 483 } plat; 484 struct { 485 struct bcma_device *core; 486 /* Reference to CMN core for BCM4706 */ 487 struct bcma_device *cmn; 488 } bcma; 489 }; 490 491 struct device *dev; 492 struct device *dma_dev; 493 u32 feature_flags; 494 495 struct net_device *net_dev; 496 struct napi_struct napi; 497 struct mii_bus *mii_bus; 498 499 /* DMA */ 500 struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS]; 501 struct bgmac_dma_ring rx_ring[BGMAC_MAX_RX_RINGS]; 502 503 /* Stats */ 504 bool stats_grabbed; 505 u32 mib_tx_regs[BGMAC_NUM_MIB_TX_REGS]; 506 u32 mib_rx_regs[BGMAC_NUM_MIB_RX_REGS]; 507 508 /* Int */ 509 int irq; 510 u32 int_mask; 511 512 /* Current MAC state */ 513 int mac_speed; 514 int mac_duplex; 515 516 u8 phyaddr; 517 bool has_robosw; 518 519 bool loopback; 520 521 u32 (*read)(struct bgmac *bgmac, u16 offset); 522 void (*write)(struct bgmac *bgmac, u16 offset, u32 value); 523 u32 (*idm_read)(struct bgmac *bgmac, u16 offset); 524 void (*idm_write)(struct bgmac *bgmac, u16 offset, u32 value); 525 bool (*clk_enabled)(struct bgmac *bgmac); 526 void (*clk_enable)(struct bgmac *bgmac, u32 flags); 527 void (*cco_ctl_maskset)(struct bgmac *bgmac, u32 offset, u32 mask, 528 u32 set); 529 u32 (*get_bus_clock)(struct bgmac *bgmac); 530 void (*cmn_maskset32)(struct bgmac *bgmac, u16 offset, u32 mask, 531 u32 set); 532 int (*phy_connect)(struct bgmac *bgmac); 533 }; 534 535 struct bgmac *bgmac_alloc(struct device *dev); 536 int bgmac_enet_probe(struct bgmac *bgmac); 537 void bgmac_enet_remove(struct bgmac *bgmac); 538 void bgmac_adjust_link(struct net_device *net_dev); 539 int bgmac_phy_connect_direct(struct bgmac *bgmac); 540 int bgmac_enet_suspend(struct bgmac *bgmac); 541 int bgmac_enet_resume(struct bgmac *bgmac); 542 543 struct mii_bus *bcma_mdio_mii_register(struct bgmac *bgmac); 544 void bcma_mdio_mii_unregister(struct mii_bus *mii_bus); 545 546 static inline u32 bgmac_read(struct bgmac *bgmac, u16 offset) 547 { 548 return bgmac->read(bgmac, offset); 549 } 550 551 static inline void bgmac_write(struct bgmac *bgmac, u16 offset, u32 value) 552 { 553 bgmac->write(bgmac, offset, value); 554 } 555 556 static inline u32 bgmac_idm_read(struct bgmac *bgmac, u16 offset) 557 { 558 return bgmac->idm_read(bgmac, offset); 559 } 560 561 static inline void bgmac_idm_write(struct bgmac *bgmac, u16 offset, u32 value) 562 { 563 bgmac->idm_write(bgmac, offset, value); 564 } 565 566 static inline bool bgmac_clk_enabled(struct bgmac *bgmac) 567 { 568 return bgmac->clk_enabled(bgmac); 569 } 570 571 static inline void bgmac_clk_enable(struct bgmac *bgmac, u32 flags) 572 { 573 bgmac->clk_enable(bgmac, flags); 574 } 575 576 static inline void bgmac_cco_ctl_maskset(struct bgmac *bgmac, u32 offset, 577 u32 mask, u32 set) 578 { 579 bgmac->cco_ctl_maskset(bgmac, offset, mask, set); 580 } 581 582 static inline u32 bgmac_get_bus_clock(struct bgmac *bgmac) 583 { 584 return bgmac->get_bus_clock(bgmac); 585 } 586 587 static inline void bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset, 588 u32 mask, u32 set) 589 { 590 bgmac->cmn_maskset32(bgmac, offset, mask, set); 591 } 592 593 static inline void bgmac_maskset(struct bgmac *bgmac, u16 offset, u32 mask, 594 u32 set) 595 { 596 bgmac_write(bgmac, offset, (bgmac_read(bgmac, offset) & mask) | set); 597 } 598 599 static inline void bgmac_mask(struct bgmac *bgmac, u16 offset, u32 mask) 600 { 601 bgmac_maskset(bgmac, offset, mask, 0); 602 } 603 604 static inline void bgmac_set(struct bgmac *bgmac, u16 offset, u32 set) 605 { 606 bgmac_maskset(bgmac, offset, ~0, set); 607 } 608 609 static inline int bgmac_phy_connect(struct bgmac *bgmac) 610 { 611 return bgmac->phy_connect(bgmac); 612 } 613 #endif /* _BGMAC_H */ 614