1 #ifndef _BGMAC_H 2 #define _BGMAC_H 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #define bgmac_err(bgmac, fmt, ...) \ 7 dev_err(&(bgmac)->core->dev, fmt, ##__VA_ARGS__) 8 #define bgmac_warn(bgmac, fmt, ...) \ 9 dev_warn(&(bgmac)->core->dev, fmt, ##__VA_ARGS__) 10 #define bgmac_info(bgmac, fmt, ...) \ 11 dev_info(&(bgmac)->core->dev, fmt, ##__VA_ARGS__) 12 #define bgmac_dbg(bgmac, fmt, ...) \ 13 dev_dbg(&(bgmac)->core->dev, fmt, ##__VA_ARGS__) 14 15 #include <linux/bcma/bcma.h> 16 #include <linux/netdevice.h> 17 18 #define BGMAC_DEV_CTL 0x000 19 #define BGMAC_DC_TSM 0x00000002 20 #define BGMAC_DC_CFCO 0x00000004 21 #define BGMAC_DC_RLSS 0x00000008 22 #define BGMAC_DC_MROR 0x00000010 23 #define BGMAC_DC_FCM_MASK 0x00000060 24 #define BGMAC_DC_FCM_SHIFT 5 25 #define BGMAC_DC_NAE 0x00000080 26 #define BGMAC_DC_TF 0x00000100 27 #define BGMAC_DC_RDS_MASK 0x00030000 28 #define BGMAC_DC_RDS_SHIFT 16 29 #define BGMAC_DC_TDS_MASK 0x000c0000 30 #define BGMAC_DC_TDS_SHIFT 18 31 #define BGMAC_DEV_STATUS 0x004 /* Configuration of the interface */ 32 #define BGMAC_DS_RBF 0x00000001 33 #define BGMAC_DS_RDF 0x00000002 34 #define BGMAC_DS_RIF 0x00000004 35 #define BGMAC_DS_TBF 0x00000008 36 #define BGMAC_DS_TDF 0x00000010 37 #define BGMAC_DS_TIF 0x00000020 38 #define BGMAC_DS_PO 0x00000040 39 #define BGMAC_DS_MM_MASK 0x00000300 /* Mode of the interface */ 40 #define BGMAC_DS_MM_SHIFT 8 41 #define BGMAC_BIST_STATUS 0x00c 42 #define BGMAC_INT_STATUS 0x020 /* Interrupt status */ 43 #define BGMAC_IS_MRO 0x00000001 44 #define BGMAC_IS_MTO 0x00000002 45 #define BGMAC_IS_TFD 0x00000004 46 #define BGMAC_IS_LS 0x00000008 47 #define BGMAC_IS_MDIO 0x00000010 48 #define BGMAC_IS_MR 0x00000020 49 #define BGMAC_IS_MT 0x00000040 50 #define BGMAC_IS_TO 0x00000080 51 #define BGMAC_IS_DESC_ERR 0x00000400 /* Descriptor error */ 52 #define BGMAC_IS_DATA_ERR 0x00000800 /* Data error */ 53 #define BGMAC_IS_DESC_PROT_ERR 0x00001000 /* Descriptor protocol error */ 54 #define BGMAC_IS_RX_DESC_UNDERF 0x00002000 /* Receive descriptor underflow */ 55 #define BGMAC_IS_RX_F_OVERF 0x00004000 /* Receive FIFO overflow */ 56 #define BGMAC_IS_TX_F_UNDERF 0x00008000 /* Transmit FIFO underflow */ 57 #define BGMAC_IS_RX 0x00010000 /* Interrupt for RX queue 0 */ 58 #define BGMAC_IS_TX0 0x01000000 /* Interrupt for TX queue 0 */ 59 #define BGMAC_IS_TX1 0x02000000 /* Interrupt for TX queue 1 */ 60 #define BGMAC_IS_TX2 0x04000000 /* Interrupt for TX queue 2 */ 61 #define BGMAC_IS_TX3 0x08000000 /* Interrupt for TX queue 3 */ 62 #define BGMAC_IS_TX_MASK 0x0f000000 63 #define BGMAC_IS_INTMASK 0x0f01fcff 64 #define BGMAC_IS_ERRMASK 0x0000fc00 65 #define BGMAC_INT_MASK 0x024 /* Interrupt mask */ 66 #define BGMAC_GP_TIMER 0x028 67 #define BGMAC_INT_RECV_LAZY 0x100 68 #define BGMAC_IRL_TO_MASK 0x00ffffff 69 #define BGMAC_IRL_FC_MASK 0xff000000 70 #define BGMAC_IRL_FC_SHIFT 24 /* Shift the number of interrupts triggered per received frame */ 71 #define BGMAC_FLOW_CTL_THRESH 0x104 /* Flow control thresholds */ 72 #define BGMAC_WRRTHRESH 0x108 73 #define BGMAC_GMAC_IDLE_CNT_THRESH 0x10c 74 #define BGMAC_PHY_ACCESS 0x180 /* PHY access address */ 75 #define BGMAC_PA_DATA_MASK 0x0000ffff 76 #define BGMAC_PA_ADDR_MASK 0x001f0000 77 #define BGMAC_PA_ADDR_SHIFT 16 78 #define BGMAC_PA_REG_MASK 0x1f000000 79 #define BGMAC_PA_REG_SHIFT 24 80 #define BGMAC_PA_WRITE 0x20000000 81 #define BGMAC_PA_START 0x40000000 82 #define BGMAC_PHY_CNTL 0x188 /* PHY control address */ 83 #define BGMAC_PC_EPA_MASK 0x0000001f 84 #define BGMAC_PC_MCT_MASK 0x007f0000 85 #define BGMAC_PC_MCT_SHIFT 16 86 #define BGMAC_PC_MTE 0x00800000 87 #define BGMAC_TXQ_CTL 0x18c 88 #define BGMAC_TXQ_CTL_DBT_MASK 0x00000fff 89 #define BGMAC_TXQ_CTL_DBT_SHIFT 0 90 #define BGMAC_RXQ_CTL 0x190 91 #define BGMAC_RXQ_CTL_DBT_MASK 0x00000fff 92 #define BGMAC_RXQ_CTL_DBT_SHIFT 0 93 #define BGMAC_RXQ_CTL_PTE 0x00001000 94 #define BGMAC_RXQ_CTL_MDP_MASK 0x3f000000 95 #define BGMAC_RXQ_CTL_MDP_SHIFT 24 96 #define BGMAC_GPIO_SELECT 0x194 97 #define BGMAC_GPIO_OUTPUT_EN 0x198 98 99 /* For 0x1e0 see BCMA_CLKCTLST. Below are BGMAC specific bits */ 100 #define BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ 0x00000100 101 #define BGMAC_BCMA_CLKCTLST_MISC_PLL_ST 0x01000000 102 103 #define BGMAC_HW_WAR 0x1e4 104 #define BGMAC_PWR_CTL 0x1e8 105 #define BGMAC_DMA_BASE0 0x200 /* Tx and Rx controller */ 106 #define BGMAC_DMA_BASE1 0x240 /* Tx controller only */ 107 #define BGMAC_DMA_BASE2 0x280 /* Tx controller only */ 108 #define BGMAC_DMA_BASE3 0x2C0 /* Tx controller only */ 109 #define BGMAC_TX_GOOD_OCTETS 0x300 110 #define BGMAC_TX_GOOD_OCTETS_HIGH 0x304 111 #define BGMAC_TX_GOOD_PKTS 0x308 112 #define BGMAC_TX_OCTETS 0x30c 113 #define BGMAC_TX_OCTETS_HIGH 0x310 114 #define BGMAC_TX_PKTS 0x314 115 #define BGMAC_TX_BROADCAST_PKTS 0x318 116 #define BGMAC_TX_MULTICAST_PKTS 0x31c 117 #define BGMAC_TX_LEN_64 0x320 118 #define BGMAC_TX_LEN_65_TO_127 0x324 119 #define BGMAC_TX_LEN_128_TO_255 0x328 120 #define BGMAC_TX_LEN_256_TO_511 0x32c 121 #define BGMAC_TX_LEN_512_TO_1023 0x330 122 #define BGMAC_TX_LEN_1024_TO_1522 0x334 123 #define BGMAC_TX_LEN_1523_TO_2047 0x338 124 #define BGMAC_TX_LEN_2048_TO_4095 0x33c 125 #define BGMAC_TX_LEN_4095_TO_8191 0x340 126 #define BGMAC_TX_LEN_8192_TO_MAX 0x344 127 #define BGMAC_TX_JABBER_PKTS 0x348 /* Error */ 128 #define BGMAC_TX_OVERSIZE_PKTS 0x34c /* Error */ 129 #define BGMAC_TX_FRAGMENT_PKTS 0x350 130 #define BGMAC_TX_UNDERRUNS 0x354 /* Error */ 131 #define BGMAC_TX_TOTAL_COLS 0x358 132 #define BGMAC_TX_SINGLE_COLS 0x35c 133 #define BGMAC_TX_MULTIPLE_COLS 0x360 134 #define BGMAC_TX_EXCESSIVE_COLS 0x364 /* Error */ 135 #define BGMAC_TX_LATE_COLS 0x368 /* Error */ 136 #define BGMAC_TX_DEFERED 0x36c 137 #define BGMAC_TX_CARRIER_LOST 0x370 138 #define BGMAC_TX_PAUSE_PKTS 0x374 139 #define BGMAC_TX_UNI_PKTS 0x378 140 #define BGMAC_TX_Q0_PKTS 0x37c 141 #define BGMAC_TX_Q0_OCTETS 0x380 142 #define BGMAC_TX_Q0_OCTETS_HIGH 0x384 143 #define BGMAC_TX_Q1_PKTS 0x388 144 #define BGMAC_TX_Q1_OCTETS 0x38c 145 #define BGMAC_TX_Q1_OCTETS_HIGH 0x390 146 #define BGMAC_TX_Q2_PKTS 0x394 147 #define BGMAC_TX_Q2_OCTETS 0x398 148 #define BGMAC_TX_Q2_OCTETS_HIGH 0x39c 149 #define BGMAC_TX_Q3_PKTS 0x3a0 150 #define BGMAC_TX_Q3_OCTETS 0x3a4 151 #define BGMAC_TX_Q3_OCTETS_HIGH 0x3a8 152 #define BGMAC_RX_GOOD_OCTETS 0x3b0 153 #define BGMAC_RX_GOOD_OCTETS_HIGH 0x3b4 154 #define BGMAC_RX_GOOD_PKTS 0x3b8 155 #define BGMAC_RX_OCTETS 0x3bc 156 #define BGMAC_RX_OCTETS_HIGH 0x3c0 157 #define BGMAC_RX_PKTS 0x3c4 158 #define BGMAC_RX_BROADCAST_PKTS 0x3c8 159 #define BGMAC_RX_MULTICAST_PKTS 0x3cc 160 #define BGMAC_RX_LEN_64 0x3d0 161 #define BGMAC_RX_LEN_65_TO_127 0x3d4 162 #define BGMAC_RX_LEN_128_TO_255 0x3d8 163 #define BGMAC_RX_LEN_256_TO_511 0x3dc 164 #define BGMAC_RX_LEN_512_TO_1023 0x3e0 165 #define BGMAC_RX_LEN_1024_TO_1522 0x3e4 166 #define BGMAC_RX_LEN_1523_TO_2047 0x3e8 167 #define BGMAC_RX_LEN_2048_TO_4095 0x3ec 168 #define BGMAC_RX_LEN_4095_TO_8191 0x3f0 169 #define BGMAC_RX_LEN_8192_TO_MAX 0x3f4 170 #define BGMAC_RX_JABBER_PKTS 0x3f8 /* Error */ 171 #define BGMAC_RX_OVERSIZE_PKTS 0x3fc /* Error */ 172 #define BGMAC_RX_FRAGMENT_PKTS 0x400 173 #define BGMAC_RX_MISSED_PKTS 0x404 /* Error */ 174 #define BGMAC_RX_CRC_ALIGN_ERRS 0x408 /* Error */ 175 #define BGMAC_RX_UNDERSIZE 0x40c /* Error */ 176 #define BGMAC_RX_CRC_ERRS 0x410 /* Error */ 177 #define BGMAC_RX_ALIGN_ERRS 0x414 /* Error */ 178 #define BGMAC_RX_SYMBOL_ERRS 0x418 /* Error */ 179 #define BGMAC_RX_PAUSE_PKTS 0x41c 180 #define BGMAC_RX_NONPAUSE_PKTS 0x420 181 #define BGMAC_RX_SACHANGES 0x424 182 #define BGMAC_RX_UNI_PKTS 0x428 183 #define BGMAC_UNIMAC_VERSION 0x800 184 #define BGMAC_HDBKP_CTL 0x804 185 #define BGMAC_CMDCFG 0x808 /* Configuration */ 186 #define BGMAC_CMDCFG_TE 0x00000001 /* Set to activate TX */ 187 #define BGMAC_CMDCFG_RE 0x00000002 /* Set to activate RX */ 188 #define BGMAC_CMDCFG_ES_MASK 0x0000000c /* Ethernet speed see gmac_speed */ 189 #define BGMAC_CMDCFG_ES_10 0x00000000 190 #define BGMAC_CMDCFG_ES_100 0x00000004 191 #define BGMAC_CMDCFG_ES_1000 0x00000008 192 #define BGMAC_CMDCFG_ES_2500 0x0000000C 193 #define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */ 194 #define BGMAC_CMDCFG_PAD_EN 0x00000020 195 #define BGMAC_CMDCFG_CF 0x00000040 196 #define BGMAC_CMDCFG_PF 0x00000080 197 #define BGMAC_CMDCFG_RPI 0x00000100 /* Unset to enable 802.3x tx flow control */ 198 #define BGMAC_CMDCFG_TAI 0x00000200 199 #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */ 200 #define BGMAC_CMDCFG_HD_SHIFT 10 201 #define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */ 202 #define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */ 203 #define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0) 204 #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */ 205 #define BGMAC_CMDCFG_AE 0x00400000 206 #define BGMAC_CMDCFG_CFE 0x00800000 207 #define BGMAC_CMDCFG_NLC 0x01000000 208 #define BGMAC_CMDCFG_RL 0x02000000 209 #define BGMAC_CMDCFG_RED 0x04000000 210 #define BGMAC_CMDCFG_PE 0x08000000 211 #define BGMAC_CMDCFG_TPI 0x10000000 212 #define BGMAC_CMDCFG_AT 0x20000000 213 #define BGMAC_MACADDR_HIGH 0x80c /* High 4 octets of own mac address */ 214 #define BGMAC_MACADDR_LOW 0x810 /* Low 2 octets of own mac address */ 215 #define BGMAC_RXMAX_LENGTH 0x814 /* Max receive frame length with vlan tag */ 216 #define BGMAC_PAUSEQUANTA 0x818 217 #define BGMAC_MAC_MODE 0x844 218 #define BGMAC_OUTERTAG 0x848 219 #define BGMAC_INNERTAG 0x84c 220 #define BGMAC_TXIPG 0x85c 221 #define BGMAC_PAUSE_CTL 0xb30 222 #define BGMAC_TX_FLUSH 0xb34 223 #define BGMAC_RX_STATUS 0xb38 224 #define BGMAC_TX_STATUS 0xb3c 225 226 /* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */ 227 #define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */ 228 #define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */ 229 230 /* BCMA GMAC core specific IO status (BCMA_IOST) flags */ 231 #define BGMAC_BCMA_IOST_ATTACHED 0x00000800 232 233 #define BGMAC_NUM_MIB_TX_REGS \ 234 (((BGMAC_TX_Q3_OCTETS_HIGH - BGMAC_TX_GOOD_OCTETS) / 4) + 1) 235 #define BGMAC_NUM_MIB_RX_REGS \ 236 (((BGMAC_RX_UNI_PKTS - BGMAC_RX_GOOD_OCTETS) / 4) + 1) 237 238 #define BGMAC_DMA_TX_CTL 0x00 239 #define BGMAC_DMA_TX_ENABLE 0x00000001 240 #define BGMAC_DMA_TX_SUSPEND 0x00000002 241 #define BGMAC_DMA_TX_LOOPBACK 0x00000004 242 #define BGMAC_DMA_TX_FLUSH 0x00000010 243 #define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */ 244 #define BGMAC_DMA_TX_MR_SHIFT 6 245 #define BGMAC_DMA_TX_MR_1 0 246 #define BGMAC_DMA_TX_MR_2 1 247 #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800 248 #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000 249 #define BGMAC_DMA_TX_ADDREXT_SHIFT 16 250 #define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */ 251 #define BGMAC_DMA_TX_BL_SHIFT 18 252 #define BGMAC_DMA_TX_BL_16 0 253 #define BGMAC_DMA_TX_BL_32 1 254 #define BGMAC_DMA_TX_BL_64 2 255 #define BGMAC_DMA_TX_BL_128 3 256 #define BGMAC_DMA_TX_BL_256 4 257 #define BGMAC_DMA_TX_BL_512 5 258 #define BGMAC_DMA_TX_BL_1024 6 259 #define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */ 260 #define BGMAC_DMA_TX_PC_SHIFT 21 261 #define BGMAC_DMA_TX_PC_0 0 262 #define BGMAC_DMA_TX_PC_4 1 263 #define BGMAC_DMA_TX_PC_8 2 264 #define BGMAC_DMA_TX_PC_16 3 265 #define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */ 266 #define BGMAC_DMA_TX_PT_SHIFT 24 267 #define BGMAC_DMA_TX_PT_1 0 268 #define BGMAC_DMA_TX_PT_2 1 269 #define BGMAC_DMA_TX_PT_4 2 270 #define BGMAC_DMA_TX_PT_8 3 271 #define BGMAC_DMA_TX_INDEX 0x04 272 #define BGMAC_DMA_TX_RINGLO 0x08 273 #define BGMAC_DMA_TX_RINGHI 0x0C 274 #define BGMAC_DMA_TX_STATUS 0x10 275 #define BGMAC_DMA_TX_STATDPTR 0x00001FFF 276 #define BGMAC_DMA_TX_STAT 0xF0000000 277 #define BGMAC_DMA_TX_STAT_DISABLED 0x00000000 278 #define BGMAC_DMA_TX_STAT_ACTIVE 0x10000000 279 #define BGMAC_DMA_TX_STAT_IDLEWAIT 0x20000000 280 #define BGMAC_DMA_TX_STAT_STOPPED 0x30000000 281 #define BGMAC_DMA_TX_STAT_SUSP 0x40000000 282 #define BGMAC_DMA_TX_ERROR 0x14 283 #define BGMAC_DMA_TX_ERRDPTR 0x0001FFFF 284 #define BGMAC_DMA_TX_ERR 0xF0000000 285 #define BGMAC_DMA_TX_ERR_NOERR 0x00000000 286 #define BGMAC_DMA_TX_ERR_PROT 0x10000000 287 #define BGMAC_DMA_TX_ERR_UNDERRUN 0x20000000 288 #define BGMAC_DMA_TX_ERR_TRANSFER 0x30000000 289 #define BGMAC_DMA_TX_ERR_DESCREAD 0x40000000 290 #define BGMAC_DMA_TX_ERR_CORE 0x50000000 291 #define BGMAC_DMA_RX_CTL 0x20 292 #define BGMAC_DMA_RX_ENABLE 0x00000001 293 #define BGMAC_DMA_RX_FRAME_OFFSET_MASK 0x000000FE 294 #define BGMAC_DMA_RX_FRAME_OFFSET_SHIFT 1 295 #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100 296 #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400 297 #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800 298 #define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */ 299 #define BGMAC_DMA_RX_MR_SHIFT 6 300 #define BGMAC_DMA_TX_MR_1 0 301 #define BGMAC_DMA_TX_MR_2 1 302 #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000 303 #define BGMAC_DMA_RX_ADDREXT_SHIFT 16 304 #define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */ 305 #define BGMAC_DMA_RX_BL_SHIFT 18 306 #define BGMAC_DMA_RX_BL_16 0 307 #define BGMAC_DMA_RX_BL_32 1 308 #define BGMAC_DMA_RX_BL_64 2 309 #define BGMAC_DMA_RX_BL_128 3 310 #define BGMAC_DMA_RX_BL_256 4 311 #define BGMAC_DMA_RX_BL_512 5 312 #define BGMAC_DMA_RX_BL_1024 6 313 #define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */ 314 #define BGMAC_DMA_RX_PC_SHIFT 21 315 #define BGMAC_DMA_RX_PC_0 0 316 #define BGMAC_DMA_RX_PC_4 1 317 #define BGMAC_DMA_RX_PC_8 2 318 #define BGMAC_DMA_RX_PC_16 3 319 #define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */ 320 #define BGMAC_DMA_RX_PT_SHIFT 24 321 #define BGMAC_DMA_RX_PT_1 0 322 #define BGMAC_DMA_RX_PT_2 1 323 #define BGMAC_DMA_RX_PT_4 2 324 #define BGMAC_DMA_RX_PT_8 3 325 #define BGMAC_DMA_RX_INDEX 0x24 326 #define BGMAC_DMA_RX_RINGLO 0x28 327 #define BGMAC_DMA_RX_RINGHI 0x2C 328 #define BGMAC_DMA_RX_STATUS 0x30 329 #define BGMAC_DMA_RX_STATDPTR 0x00001FFF 330 #define BGMAC_DMA_RX_STAT 0xF0000000 331 #define BGMAC_DMA_RX_STAT_DISABLED 0x00000000 332 #define BGMAC_DMA_RX_STAT_ACTIVE 0x10000000 333 #define BGMAC_DMA_RX_STAT_IDLEWAIT 0x20000000 334 #define BGMAC_DMA_RX_STAT_STOPPED 0x30000000 335 #define BGMAC_DMA_RX_STAT_SUSP 0x40000000 336 #define BGMAC_DMA_RX_ERROR 0x34 337 #define BGMAC_DMA_RX_ERRDPTR 0x0001FFFF 338 #define BGMAC_DMA_RX_ERR 0xF0000000 339 #define BGMAC_DMA_RX_ERR_NOERR 0x00000000 340 #define BGMAC_DMA_RX_ERR_PROT 0x10000000 341 #define BGMAC_DMA_RX_ERR_UNDERRUN 0x20000000 342 #define BGMAC_DMA_RX_ERR_TRANSFER 0x30000000 343 #define BGMAC_DMA_RX_ERR_DESCREAD 0x40000000 344 #define BGMAC_DMA_RX_ERR_CORE 0x50000000 345 346 #define BGMAC_DESC_CTL0_EOT 0x10000000 /* End of ring */ 347 #define BGMAC_DESC_CTL0_IOC 0x20000000 /* IRQ on complete */ 348 #define BGMAC_DESC_CTL0_EOF 0x40000000 /* End of frame */ 349 #define BGMAC_DESC_CTL0_SOF 0x80000000 /* Start of frame */ 350 #define BGMAC_DESC_CTL1_LEN 0x00001FFF 351 352 #define BGMAC_PHY_NOREGS 0x1E 353 #define BGMAC_PHY_MASK 0x1F 354 355 #define BGMAC_MAX_TX_RINGS 4 356 #define BGMAC_MAX_RX_RINGS 1 357 358 #define BGMAC_TX_RING_SLOTS 128 359 #define BGMAC_RX_RING_SLOTS 512 360 361 #define BGMAC_RX_HEADER_LEN 28 /* Last 24 bytes are unused. Well... */ 362 #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ 363 #define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \ 364 BGMAC_RX_FRAME_OFFSET) 365 #define BGMAC_RX_MAX_FRAME_SIZE 1536 /* Copied from b44/tg3 */ 366 #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE) 367 #define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \ 368 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 369 370 #define BGMAC_BFL_ENETROBO 0x0010 /* has ephy roboswitch spi */ 371 #define BGMAC_BFL_ENETADM 0x0080 /* has ADMtek switch */ 372 #define BGMAC_BFL_ENETVLAN 0x0100 /* can do vlan */ 373 374 #define BGMAC_CHIPCTL_1_IF_TYPE_MASK 0x00000030 375 #define BGMAC_CHIPCTL_1_IF_TYPE_RMII 0x00000000 376 #define BGMAC_CHIPCTL_1_IF_TYPE_MII 0x00000010 377 #define BGMAC_CHIPCTL_1_IF_TYPE_RGMII 0x00000020 378 #define BGMAC_CHIPCTL_1_SW_TYPE_MASK 0x000000C0 379 #define BGMAC_CHIPCTL_1_SW_TYPE_EPHY 0x00000000 380 #define BGMAC_CHIPCTL_1_SW_TYPE_EPHYMII 0x00000040 381 #define BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII 0x00000080 382 #define BGMAC_CHIPCTL_1_SW_TYPE_RGMII 0x000000C0 383 #define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS 0x00010000 384 385 #define BGMAC_WEIGHT 64 386 387 #define ETHER_MAX_LEN 1518 388 389 struct bgmac_slot_info { 390 union { 391 struct sk_buff *skb; 392 void *buf; 393 }; 394 dma_addr_t dma_addr; 395 }; 396 397 struct bgmac_dma_desc { 398 __le32 ctl0; 399 __le32 ctl1; 400 __le32 addr_low; 401 __le32 addr_high; 402 } __packed; 403 404 enum bgmac_dma_ring_type { 405 BGMAC_DMA_RING_TX, 406 BGMAC_DMA_RING_RX, 407 }; 408 409 /** 410 * bgmac_dma_ring - contains info about DMA ring (either TX or RX one) 411 * @start: index of the first slot containing data 412 * @end: index of a slot that can *not* be read (yet) 413 * 414 * Be really aware of the specific @end meaning. It's an index of a slot *after* 415 * the one containing data that can be read. If @start equals @end the ring is 416 * empty. 417 */ 418 struct bgmac_dma_ring { 419 u32 start; 420 u32 end; 421 422 struct bgmac_dma_desc *cpu_base; 423 dma_addr_t dma_base; 424 u32 index_base; /* Used for unaligned rings only, otherwise 0 */ 425 u16 mmio_base; 426 bool unaligned; 427 428 struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS]; 429 }; 430 431 struct bgmac_rx_header { 432 __le16 len; 433 __le16 flags; 434 __le16 pad[12]; 435 }; 436 437 struct bgmac { 438 struct bcma_device *core; 439 struct bcma_device *cmn; /* Reference to CMN core for BCM4706 */ 440 struct net_device *net_dev; 441 struct napi_struct napi; 442 struct mii_bus *mii_bus; 443 struct phy_device *phy_dev; 444 445 /* DMA */ 446 struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS]; 447 struct bgmac_dma_ring rx_ring[BGMAC_MAX_RX_RINGS]; 448 449 /* Stats */ 450 bool stats_grabbed; 451 u32 mib_tx_regs[BGMAC_NUM_MIB_TX_REGS]; 452 u32 mib_rx_regs[BGMAC_NUM_MIB_RX_REGS]; 453 454 /* Int */ 455 u32 int_mask; 456 457 /* Current MAC state */ 458 int mac_speed; 459 int mac_duplex; 460 461 u8 phyaddr; 462 bool has_robosw; 463 464 bool loopback; 465 }; 466 467 static inline u32 bgmac_read(struct bgmac *bgmac, u16 offset) 468 { 469 return bcma_read32(bgmac->core, offset); 470 } 471 472 static inline void bgmac_write(struct bgmac *bgmac, u16 offset, u32 value) 473 { 474 bcma_write32(bgmac->core, offset, value); 475 } 476 477 static inline void bgmac_maskset(struct bgmac *bgmac, u16 offset, u32 mask, 478 u32 set) 479 { 480 bgmac_write(bgmac, offset, (bgmac_read(bgmac, offset) & mask) | set); 481 } 482 483 static inline void bgmac_mask(struct bgmac *bgmac, u16 offset, u32 mask) 484 { 485 bgmac_maskset(bgmac, offset, mask, 0); 486 } 487 488 static inline void bgmac_set(struct bgmac *bgmac, u16 offset, u32 set) 489 { 490 bgmac_maskset(bgmac, offset, ~0, set); 491 } 492 493 #endif /* _BGMAC_H */ 494