1 #ifndef _BGMAC_H
2 #define _BGMAC_H
3 
4 #define pr_fmt(fmt)		KBUILD_MODNAME ": " fmt
5 
6 #define bgmac_err(bgmac, fmt, ...) \
7 	dev_err(&(bgmac)->core->dev, fmt, ##__VA_ARGS__)
8 #define bgmac_warn(bgmac, fmt, ...) \
9 	dev_warn(&(bgmac)->core->dev, fmt,  ##__VA_ARGS__)
10 #define bgmac_info(bgmac, fmt, ...) \
11 	dev_info(&(bgmac)->core->dev, fmt,  ##__VA_ARGS__)
12 #define bgmac_dbg(bgmac, fmt, ...) \
13 	dev_dbg(&(bgmac)->core->dev, fmt, ##__VA_ARGS__)
14 
15 #include <linux/bcma/bcma.h>
16 #include <linux/brcmphy.h>
17 #include <linux/netdevice.h>
18 
19 #define BGMAC_DEV_CTL				0x000
20 #define  BGMAC_DC_TSM				0x00000002
21 #define  BGMAC_DC_CFCO				0x00000004
22 #define  BGMAC_DC_RLSS				0x00000008
23 #define  BGMAC_DC_MROR				0x00000010
24 #define  BGMAC_DC_FCM_MASK			0x00000060
25 #define  BGMAC_DC_FCM_SHIFT			5
26 #define  BGMAC_DC_NAE				0x00000080
27 #define  BGMAC_DC_TF				0x00000100
28 #define  BGMAC_DC_RDS_MASK			0x00030000
29 #define  BGMAC_DC_RDS_SHIFT			16
30 #define  BGMAC_DC_TDS_MASK			0x000c0000
31 #define  BGMAC_DC_TDS_SHIFT			18
32 #define BGMAC_DEV_STATUS			0x004		/* Configuration of the interface */
33 #define  BGMAC_DS_RBF				0x00000001
34 #define  BGMAC_DS_RDF				0x00000002
35 #define  BGMAC_DS_RIF				0x00000004
36 #define  BGMAC_DS_TBF				0x00000008
37 #define  BGMAC_DS_TDF				0x00000010
38 #define  BGMAC_DS_TIF				0x00000020
39 #define  BGMAC_DS_PO				0x00000040
40 #define  BGMAC_DS_MM_MASK			0x00000300	/* Mode of the interface */
41 #define  BGMAC_DS_MM_SHIFT			8
42 #define BGMAC_BIST_STATUS			0x00c
43 #define BGMAC_INT_STATUS			0x020		/* Interrupt status */
44 #define  BGMAC_IS_MRO				0x00000001
45 #define  BGMAC_IS_MTO				0x00000002
46 #define  BGMAC_IS_TFD				0x00000004
47 #define  BGMAC_IS_LS				0x00000008
48 #define  BGMAC_IS_MDIO				0x00000010
49 #define  BGMAC_IS_MR				0x00000020
50 #define  BGMAC_IS_MT				0x00000040
51 #define  BGMAC_IS_TO				0x00000080
52 #define  BGMAC_IS_DESC_ERR			0x00000400	/* Descriptor error */
53 #define  BGMAC_IS_DATA_ERR			0x00000800	/* Data error */
54 #define  BGMAC_IS_DESC_PROT_ERR			0x00001000	/* Descriptor protocol error */
55 #define  BGMAC_IS_RX_DESC_UNDERF		0x00002000	/* Receive descriptor underflow */
56 #define  BGMAC_IS_RX_F_OVERF			0x00004000	/* Receive FIFO overflow */
57 #define  BGMAC_IS_TX_F_UNDERF			0x00008000	/* Transmit FIFO underflow */
58 #define  BGMAC_IS_RX				0x00010000	/* Interrupt for RX queue 0 */
59 #define  BGMAC_IS_TX0				0x01000000	/* Interrupt for TX queue 0 */
60 #define  BGMAC_IS_TX1				0x02000000	/* Interrupt for TX queue 1 */
61 #define  BGMAC_IS_TX2				0x04000000	/* Interrupt for TX queue 2 */
62 #define  BGMAC_IS_TX3				0x08000000	/* Interrupt for TX queue 3 */
63 #define  BGMAC_IS_TX_MASK			0x0f000000
64 #define  BGMAC_IS_INTMASK			0x0f01fcff
65 #define  BGMAC_IS_ERRMASK			0x0000fc00
66 #define BGMAC_INT_MASK				0x024		/* Interrupt mask */
67 #define BGMAC_GP_TIMER				0x028
68 #define BGMAC_INT_RECV_LAZY			0x100
69 #define  BGMAC_IRL_TO_MASK			0x00ffffff
70 #define  BGMAC_IRL_FC_MASK			0xff000000
71 #define  BGMAC_IRL_FC_SHIFT			24		/* Shift the number of interrupts triggered per received frame */
72 #define BGMAC_FLOW_CTL_THRESH			0x104		/* Flow control thresholds */
73 #define BGMAC_WRRTHRESH				0x108
74 #define BGMAC_GMAC_IDLE_CNT_THRESH		0x10c
75 #define BGMAC_PHY_ACCESS			0x180		/* PHY access address */
76 #define  BGMAC_PA_DATA_MASK			0x0000ffff
77 #define  BGMAC_PA_ADDR_MASK			0x001f0000
78 #define  BGMAC_PA_ADDR_SHIFT			16
79 #define  BGMAC_PA_REG_MASK			0x1f000000
80 #define  BGMAC_PA_REG_SHIFT			24
81 #define  BGMAC_PA_WRITE				0x20000000
82 #define  BGMAC_PA_START				0x40000000
83 #define BGMAC_PHY_CNTL				0x188		/* PHY control address */
84 #define  BGMAC_PC_EPA_MASK			0x0000001f
85 #define  BGMAC_PC_MCT_MASK			0x007f0000
86 #define  BGMAC_PC_MCT_SHIFT			16
87 #define  BGMAC_PC_MTE				0x00800000
88 #define BGMAC_TXQ_CTL				0x18c
89 #define  BGMAC_TXQ_CTL_DBT_MASK			0x00000fff
90 #define  BGMAC_TXQ_CTL_DBT_SHIFT		0
91 #define BGMAC_RXQ_CTL				0x190
92 #define  BGMAC_RXQ_CTL_DBT_MASK			0x00000fff
93 #define  BGMAC_RXQ_CTL_DBT_SHIFT		0
94 #define  BGMAC_RXQ_CTL_PTE			0x00001000
95 #define  BGMAC_RXQ_CTL_MDP_MASK			0x3f000000
96 #define  BGMAC_RXQ_CTL_MDP_SHIFT		24
97 #define BGMAC_GPIO_SELECT			0x194
98 #define BGMAC_GPIO_OUTPUT_EN			0x198
99 
100 /* For 0x1e0 see BCMA_CLKCTLST. Below are BGMAC specific bits */
101 #define  BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ	0x00000100
102 #define  BGMAC_BCMA_CLKCTLST_MISC_PLL_ST	0x01000000
103 
104 #define BGMAC_HW_WAR				0x1e4
105 #define BGMAC_PWR_CTL				0x1e8
106 #define BGMAC_DMA_BASE0				0x200		/* Tx and Rx controller */
107 #define BGMAC_DMA_BASE1				0x240		/* Tx controller only */
108 #define BGMAC_DMA_BASE2				0x280		/* Tx controller only */
109 #define BGMAC_DMA_BASE3				0x2C0		/* Tx controller only */
110 #define BGMAC_TX_GOOD_OCTETS			0x300
111 #define BGMAC_TX_GOOD_OCTETS_HIGH		0x304
112 #define BGMAC_TX_GOOD_PKTS			0x308
113 #define BGMAC_TX_OCTETS				0x30c
114 #define BGMAC_TX_OCTETS_HIGH			0x310
115 #define BGMAC_TX_PKTS				0x314
116 #define BGMAC_TX_BROADCAST_PKTS			0x318
117 #define BGMAC_TX_MULTICAST_PKTS			0x31c
118 #define BGMAC_TX_LEN_64				0x320
119 #define BGMAC_TX_LEN_65_TO_127			0x324
120 #define BGMAC_TX_LEN_128_TO_255			0x328
121 #define BGMAC_TX_LEN_256_TO_511			0x32c
122 #define BGMAC_TX_LEN_512_TO_1023		0x330
123 #define BGMAC_TX_LEN_1024_TO_1522		0x334
124 #define BGMAC_TX_LEN_1523_TO_2047		0x338
125 #define BGMAC_TX_LEN_2048_TO_4095		0x33c
126 #define BGMAC_TX_LEN_4095_TO_8191		0x340
127 #define BGMAC_TX_LEN_8192_TO_MAX		0x344
128 #define BGMAC_TX_JABBER_PKTS			0x348		/* Error */
129 #define BGMAC_TX_OVERSIZE_PKTS			0x34c		/* Error */
130 #define BGMAC_TX_FRAGMENT_PKTS			0x350
131 #define BGMAC_TX_UNDERRUNS			0x354		/* Error */
132 #define BGMAC_TX_TOTAL_COLS			0x358
133 #define BGMAC_TX_SINGLE_COLS			0x35c
134 #define BGMAC_TX_MULTIPLE_COLS			0x360
135 #define BGMAC_TX_EXCESSIVE_COLS			0x364		/* Error */
136 #define BGMAC_TX_LATE_COLS			0x368		/* Error */
137 #define BGMAC_TX_DEFERED			0x36c
138 #define BGMAC_TX_CARRIER_LOST			0x370
139 #define BGMAC_TX_PAUSE_PKTS			0x374
140 #define BGMAC_TX_UNI_PKTS			0x378
141 #define BGMAC_TX_Q0_PKTS			0x37c
142 #define BGMAC_TX_Q0_OCTETS			0x380
143 #define BGMAC_TX_Q0_OCTETS_HIGH			0x384
144 #define BGMAC_TX_Q1_PKTS			0x388
145 #define BGMAC_TX_Q1_OCTETS			0x38c
146 #define BGMAC_TX_Q1_OCTETS_HIGH			0x390
147 #define BGMAC_TX_Q2_PKTS			0x394
148 #define BGMAC_TX_Q2_OCTETS			0x398
149 #define BGMAC_TX_Q2_OCTETS_HIGH			0x39c
150 #define BGMAC_TX_Q3_PKTS			0x3a0
151 #define BGMAC_TX_Q3_OCTETS			0x3a4
152 #define BGMAC_TX_Q3_OCTETS_HIGH			0x3a8
153 #define BGMAC_RX_GOOD_OCTETS			0x3b0
154 #define BGMAC_RX_GOOD_OCTETS_HIGH		0x3b4
155 #define BGMAC_RX_GOOD_PKTS			0x3b8
156 #define BGMAC_RX_OCTETS				0x3bc
157 #define BGMAC_RX_OCTETS_HIGH			0x3c0
158 #define BGMAC_RX_PKTS				0x3c4
159 #define BGMAC_RX_BROADCAST_PKTS			0x3c8
160 #define BGMAC_RX_MULTICAST_PKTS			0x3cc
161 #define BGMAC_RX_LEN_64				0x3d0
162 #define BGMAC_RX_LEN_65_TO_127			0x3d4
163 #define BGMAC_RX_LEN_128_TO_255			0x3d8
164 #define BGMAC_RX_LEN_256_TO_511			0x3dc
165 #define BGMAC_RX_LEN_512_TO_1023		0x3e0
166 #define BGMAC_RX_LEN_1024_TO_1522		0x3e4
167 #define BGMAC_RX_LEN_1523_TO_2047		0x3e8
168 #define BGMAC_RX_LEN_2048_TO_4095		0x3ec
169 #define BGMAC_RX_LEN_4095_TO_8191		0x3f0
170 #define BGMAC_RX_LEN_8192_TO_MAX		0x3f4
171 #define BGMAC_RX_JABBER_PKTS			0x3f8		/* Error */
172 #define BGMAC_RX_OVERSIZE_PKTS			0x3fc		/* Error */
173 #define BGMAC_RX_FRAGMENT_PKTS			0x400
174 #define BGMAC_RX_MISSED_PKTS			0x404		/* Error */
175 #define BGMAC_RX_CRC_ALIGN_ERRS			0x408		/* Error */
176 #define BGMAC_RX_UNDERSIZE			0x40c		/* Error */
177 #define BGMAC_RX_CRC_ERRS			0x410		/* Error */
178 #define BGMAC_RX_ALIGN_ERRS			0x414		/* Error */
179 #define BGMAC_RX_SYMBOL_ERRS			0x418		/* Error */
180 #define BGMAC_RX_PAUSE_PKTS			0x41c
181 #define BGMAC_RX_NONPAUSE_PKTS			0x420
182 #define BGMAC_RX_SACHANGES			0x424
183 #define BGMAC_RX_UNI_PKTS			0x428
184 #define BGMAC_UNIMAC_VERSION			0x800
185 #define BGMAC_HDBKP_CTL				0x804
186 #define BGMAC_CMDCFG				0x808		/* Configuration */
187 #define  BGMAC_CMDCFG_TE			0x00000001	/* Set to activate TX */
188 #define  BGMAC_CMDCFG_RE			0x00000002	/* Set to activate RX */
189 #define  BGMAC_CMDCFG_ES_MASK			0x0000000c	/* Ethernet speed see gmac_speed */
190 #define   BGMAC_CMDCFG_ES_10			0x00000000
191 #define   BGMAC_CMDCFG_ES_100			0x00000004
192 #define   BGMAC_CMDCFG_ES_1000			0x00000008
193 #define   BGMAC_CMDCFG_ES_2500			0x0000000C
194 #define  BGMAC_CMDCFG_PROM			0x00000010	/* Set to activate promiscuous mode */
195 #define  BGMAC_CMDCFG_PAD_EN			0x00000020
196 #define  BGMAC_CMDCFG_CF			0x00000040
197 #define  BGMAC_CMDCFG_PF			0x00000080
198 #define  BGMAC_CMDCFG_RPI			0x00000100	/* Unset to enable 802.3x tx flow control */
199 #define  BGMAC_CMDCFG_TAI			0x00000200
200 #define  BGMAC_CMDCFG_HD			0x00000400	/* Set if in half duplex mode */
201 #define  BGMAC_CMDCFG_HD_SHIFT			10
202 #define  BGMAC_CMDCFG_SR_REV0			0x00000800	/* Set to reset mode, for core rev 0-3 */
203 #define  BGMAC_CMDCFG_SR_REV4			0x00002000	/* Set to reset mode, for core rev >= 4 */
204 #define  BGMAC_CMDCFG_SR(rev)  ((rev >= 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0)
205 #define  BGMAC_CMDCFG_ML			0x00008000	/* Set to activate mac loopback mode */
206 #define  BGMAC_CMDCFG_AE			0x00400000
207 #define  BGMAC_CMDCFG_CFE			0x00800000
208 #define  BGMAC_CMDCFG_NLC			0x01000000
209 #define  BGMAC_CMDCFG_RL			0x02000000
210 #define  BGMAC_CMDCFG_RED			0x04000000
211 #define  BGMAC_CMDCFG_PE			0x08000000
212 #define  BGMAC_CMDCFG_TPI			0x10000000
213 #define  BGMAC_CMDCFG_AT			0x20000000
214 #define BGMAC_MACADDR_HIGH			0x80c		/* High 4 octets of own mac address */
215 #define BGMAC_MACADDR_LOW			0x810		/* Low 2 octets of own mac address */
216 #define BGMAC_RXMAX_LENGTH			0x814		/* Max receive frame length with vlan tag */
217 #define BGMAC_PAUSEQUANTA			0x818
218 #define BGMAC_MAC_MODE				0x844
219 #define BGMAC_OUTERTAG				0x848
220 #define BGMAC_INNERTAG				0x84c
221 #define BGMAC_TXIPG				0x85c
222 #define BGMAC_PAUSE_CTL				0xb30
223 #define BGMAC_TX_FLUSH				0xb34
224 #define BGMAC_RX_STATUS				0xb38
225 #define BGMAC_TX_STATUS				0xb3c
226 
227 /* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */
228 #define BGMAC_BCMA_IOCTL_SW_CLKEN		0x00000004	/* PHY Clock Enable */
229 #define BGMAC_BCMA_IOCTL_SW_RESET		0x00000008	/* PHY Reset */
230 
231 /* BCMA GMAC core specific IO status (BCMA_IOST) flags */
232 #define BGMAC_BCMA_IOST_ATTACHED		0x00000800
233 
234 #define BGMAC_NUM_MIB_TX_REGS	\
235 		(((BGMAC_TX_Q3_OCTETS_HIGH - BGMAC_TX_GOOD_OCTETS) / 4) + 1)
236 #define BGMAC_NUM_MIB_RX_REGS	\
237 		(((BGMAC_RX_UNI_PKTS - BGMAC_RX_GOOD_OCTETS) / 4) + 1)
238 
239 #define BGMAC_DMA_TX_CTL			0x00
240 #define  BGMAC_DMA_TX_ENABLE			0x00000001
241 #define  BGMAC_DMA_TX_SUSPEND			0x00000002
242 #define  BGMAC_DMA_TX_LOOPBACK			0x00000004
243 #define  BGMAC_DMA_TX_FLUSH			0x00000010
244 #define  BGMAC_DMA_TX_MR_MASK			0x000000C0	/* Multiple outstanding reads */
245 #define  BGMAC_DMA_TX_MR_SHIFT			6
246 #define   BGMAC_DMA_TX_MR_1			0
247 #define   BGMAC_DMA_TX_MR_2			1
248 #define  BGMAC_DMA_TX_PARITY_DISABLE		0x00000800
249 #define  BGMAC_DMA_TX_ADDREXT_MASK		0x00030000
250 #define  BGMAC_DMA_TX_ADDREXT_SHIFT		16
251 #define  BGMAC_DMA_TX_BL_MASK			0x001C0000	/* BurstLen bits */
252 #define  BGMAC_DMA_TX_BL_SHIFT			18
253 #define   BGMAC_DMA_TX_BL_16			0
254 #define   BGMAC_DMA_TX_BL_32			1
255 #define   BGMAC_DMA_TX_BL_64			2
256 #define   BGMAC_DMA_TX_BL_128			3
257 #define   BGMAC_DMA_TX_BL_256			4
258 #define   BGMAC_DMA_TX_BL_512			5
259 #define   BGMAC_DMA_TX_BL_1024			6
260 #define  BGMAC_DMA_TX_PC_MASK			0x00E00000	/* Prefetch control */
261 #define  BGMAC_DMA_TX_PC_SHIFT			21
262 #define   BGMAC_DMA_TX_PC_0			0
263 #define   BGMAC_DMA_TX_PC_4			1
264 #define   BGMAC_DMA_TX_PC_8			2
265 #define   BGMAC_DMA_TX_PC_16			3
266 #define  BGMAC_DMA_TX_PT_MASK			0x03000000	/* Prefetch threshold */
267 #define  BGMAC_DMA_TX_PT_SHIFT			24
268 #define   BGMAC_DMA_TX_PT_1			0
269 #define   BGMAC_DMA_TX_PT_2			1
270 #define   BGMAC_DMA_TX_PT_4			2
271 #define   BGMAC_DMA_TX_PT_8			3
272 #define BGMAC_DMA_TX_INDEX			0x04
273 #define BGMAC_DMA_TX_RINGLO			0x08
274 #define BGMAC_DMA_TX_RINGHI			0x0C
275 #define BGMAC_DMA_TX_STATUS			0x10
276 #define  BGMAC_DMA_TX_STATDPTR			0x00001FFF
277 #define  BGMAC_DMA_TX_STAT			0xF0000000
278 #define   BGMAC_DMA_TX_STAT_DISABLED		0x00000000
279 #define   BGMAC_DMA_TX_STAT_ACTIVE		0x10000000
280 #define   BGMAC_DMA_TX_STAT_IDLEWAIT		0x20000000
281 #define   BGMAC_DMA_TX_STAT_STOPPED		0x30000000
282 #define   BGMAC_DMA_TX_STAT_SUSP		0x40000000
283 #define BGMAC_DMA_TX_ERROR			0x14
284 #define  BGMAC_DMA_TX_ERRDPTR			0x0001FFFF
285 #define  BGMAC_DMA_TX_ERR			0xF0000000
286 #define   BGMAC_DMA_TX_ERR_NOERR		0x00000000
287 #define   BGMAC_DMA_TX_ERR_PROT			0x10000000
288 #define   BGMAC_DMA_TX_ERR_UNDERRUN		0x20000000
289 #define   BGMAC_DMA_TX_ERR_TRANSFER		0x30000000
290 #define   BGMAC_DMA_TX_ERR_DESCREAD		0x40000000
291 #define   BGMAC_DMA_TX_ERR_CORE			0x50000000
292 #define BGMAC_DMA_RX_CTL			0x20
293 #define  BGMAC_DMA_RX_ENABLE			0x00000001
294 #define  BGMAC_DMA_RX_FRAME_OFFSET_MASK		0x000000FE
295 #define  BGMAC_DMA_RX_FRAME_OFFSET_SHIFT	1
296 #define  BGMAC_DMA_RX_DIRECT_FIFO		0x00000100
297 #define  BGMAC_DMA_RX_OVERFLOW_CONT		0x00000400
298 #define  BGMAC_DMA_RX_PARITY_DISABLE		0x00000800
299 #define  BGMAC_DMA_RX_MR_MASK			0x000000C0	/* Multiple outstanding reads */
300 #define  BGMAC_DMA_RX_MR_SHIFT			6
301 #define   BGMAC_DMA_TX_MR_1			0
302 #define   BGMAC_DMA_TX_MR_2			1
303 #define  BGMAC_DMA_RX_ADDREXT_MASK		0x00030000
304 #define  BGMAC_DMA_RX_ADDREXT_SHIFT		16
305 #define  BGMAC_DMA_RX_BL_MASK			0x001C0000	/* BurstLen bits */
306 #define  BGMAC_DMA_RX_BL_SHIFT			18
307 #define   BGMAC_DMA_RX_BL_16			0
308 #define   BGMAC_DMA_RX_BL_32			1
309 #define   BGMAC_DMA_RX_BL_64			2
310 #define   BGMAC_DMA_RX_BL_128			3
311 #define   BGMAC_DMA_RX_BL_256			4
312 #define   BGMAC_DMA_RX_BL_512			5
313 #define   BGMAC_DMA_RX_BL_1024			6
314 #define  BGMAC_DMA_RX_PC_MASK			0x00E00000	/* Prefetch control */
315 #define  BGMAC_DMA_RX_PC_SHIFT			21
316 #define   BGMAC_DMA_RX_PC_0			0
317 #define   BGMAC_DMA_RX_PC_4			1
318 #define   BGMAC_DMA_RX_PC_8			2
319 #define   BGMAC_DMA_RX_PC_16			3
320 #define  BGMAC_DMA_RX_PT_MASK			0x03000000	/* Prefetch threshold */
321 #define  BGMAC_DMA_RX_PT_SHIFT			24
322 #define   BGMAC_DMA_RX_PT_1			0
323 #define   BGMAC_DMA_RX_PT_2			1
324 #define   BGMAC_DMA_RX_PT_4			2
325 #define   BGMAC_DMA_RX_PT_8			3
326 #define BGMAC_DMA_RX_INDEX			0x24
327 #define BGMAC_DMA_RX_RINGLO			0x28
328 #define BGMAC_DMA_RX_RINGHI			0x2C
329 #define BGMAC_DMA_RX_STATUS			0x30
330 #define  BGMAC_DMA_RX_STATDPTR			0x00001FFF
331 #define  BGMAC_DMA_RX_STAT			0xF0000000
332 #define   BGMAC_DMA_RX_STAT_DISABLED		0x00000000
333 #define   BGMAC_DMA_RX_STAT_ACTIVE		0x10000000
334 #define   BGMAC_DMA_RX_STAT_IDLEWAIT		0x20000000
335 #define   BGMAC_DMA_RX_STAT_STOPPED		0x30000000
336 #define   BGMAC_DMA_RX_STAT_SUSP		0x40000000
337 #define BGMAC_DMA_RX_ERROR			0x34
338 #define  BGMAC_DMA_RX_ERRDPTR			0x0001FFFF
339 #define  BGMAC_DMA_RX_ERR			0xF0000000
340 #define   BGMAC_DMA_RX_ERR_NOERR		0x00000000
341 #define   BGMAC_DMA_RX_ERR_PROT			0x10000000
342 #define   BGMAC_DMA_RX_ERR_UNDERRUN		0x20000000
343 #define   BGMAC_DMA_RX_ERR_TRANSFER		0x30000000
344 #define   BGMAC_DMA_RX_ERR_DESCREAD		0x40000000
345 #define   BGMAC_DMA_RX_ERR_CORE			0x50000000
346 
347 #define BGMAC_DESC_CTL0_EOT			0x10000000	/* End of ring */
348 #define BGMAC_DESC_CTL0_IOC			0x20000000	/* IRQ on complete */
349 #define BGMAC_DESC_CTL0_EOF			0x40000000	/* End of frame */
350 #define BGMAC_DESC_CTL0_SOF			0x80000000	/* Start of frame */
351 #define BGMAC_DESC_CTL1_LEN			0x00001FFF
352 
353 #define BGMAC_PHY_NOREGS			BRCM_PSEUDO_PHY_ADDR
354 #define BGMAC_PHY_MASK				0x1F
355 
356 #define BGMAC_MAX_TX_RINGS			4
357 #define BGMAC_MAX_RX_RINGS			1
358 
359 #define BGMAC_TX_RING_SLOTS			128
360 #define BGMAC_RX_RING_SLOTS			512
361 
362 #define BGMAC_RX_HEADER_LEN			28		/* Last 24 bytes are unused. Well... */
363 #define BGMAC_RX_FRAME_OFFSET			30		/* There are 2 unused bytes between header and real data */
364 #define BGMAC_RX_BUF_OFFSET			(NET_SKB_PAD + NET_IP_ALIGN - \
365 						 BGMAC_RX_FRAME_OFFSET)
366 #define BGMAC_RX_MAX_FRAME_SIZE			1536		/* Copied from b44/tg3 */
367 #define BGMAC_RX_BUF_SIZE			(BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE)
368 #define BGMAC_RX_ALLOC_SIZE			(SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \
369 						 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
370 
371 #define BGMAC_BFL_ENETROBO			0x0010		/* has ephy roboswitch spi */
372 #define BGMAC_BFL_ENETADM			0x0080		/* has ADMtek switch */
373 #define BGMAC_BFL_ENETVLAN			0x0100		/* can do vlan */
374 
375 #define BGMAC_CHIPCTL_1_IF_TYPE_MASK		0x00000030
376 #define BGMAC_CHIPCTL_1_IF_TYPE_RMII		0x00000000
377 #define BGMAC_CHIPCTL_1_IF_TYPE_MII		0x00000010
378 #define BGMAC_CHIPCTL_1_IF_TYPE_RGMII		0x00000020
379 #define BGMAC_CHIPCTL_1_SW_TYPE_MASK		0x000000C0
380 #define BGMAC_CHIPCTL_1_SW_TYPE_EPHY		0x00000000
381 #define BGMAC_CHIPCTL_1_SW_TYPE_EPHYMII		0x00000040
382 #define BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII	0x00000080
383 #define BGMAC_CHIPCTL_1_SW_TYPE_RGMII		0x000000C0
384 #define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS		0x00010000
385 
386 #define BGMAC_WEIGHT	64
387 
388 #define ETHER_MAX_LEN   1518
389 
390 struct bgmac_slot_info {
391 	union {
392 		struct sk_buff *skb;
393 		void *buf;
394 	};
395 	dma_addr_t dma_addr;
396 };
397 
398 struct bgmac_dma_desc {
399 	__le32 ctl0;
400 	__le32 ctl1;
401 	__le32 addr_low;
402 	__le32 addr_high;
403 } __packed;
404 
405 enum bgmac_dma_ring_type {
406 	BGMAC_DMA_RING_TX,
407 	BGMAC_DMA_RING_RX,
408 };
409 
410 /**
411  * bgmac_dma_ring - contains info about DMA ring (either TX or RX one)
412  * @start: index of the first slot containing data
413  * @end: index of a slot that can *not* be read (yet)
414  *
415  * Be really aware of the specific @end meaning. It's an index of a slot *after*
416  * the one containing data that can be read. If @start equals @end the ring is
417  * empty.
418  */
419 struct bgmac_dma_ring {
420 	u32 start;
421 	u32 end;
422 
423 	struct bgmac_dma_desc *cpu_base;
424 	dma_addr_t dma_base;
425 	u32 index_base; /* Used for unaligned rings only, otherwise 0 */
426 	u16 mmio_base;
427 	bool unaligned;
428 
429 	struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS];
430 };
431 
432 struct bgmac_rx_header {
433 	__le16 len;
434 	__le16 flags;
435 	__le16 pad[12];
436 };
437 
438 struct bgmac {
439 	struct bcma_device *core;
440 	struct bcma_device *cmn; /* Reference to CMN core for BCM4706 */
441 	struct net_device *net_dev;
442 	struct napi_struct napi;
443 	struct mii_bus *mii_bus;
444 	struct phy_device *phy_dev;
445 
446 	/* DMA */
447 	struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS];
448 	struct bgmac_dma_ring rx_ring[BGMAC_MAX_RX_RINGS];
449 
450 	/* Stats */
451 	bool stats_grabbed;
452 	u32 mib_tx_regs[BGMAC_NUM_MIB_TX_REGS];
453 	u32 mib_rx_regs[BGMAC_NUM_MIB_RX_REGS];
454 
455 	/* Int */
456 	u32 int_mask;
457 
458 	/* Current MAC state */
459 	int mac_speed;
460 	int mac_duplex;
461 
462 	u8 phyaddr;
463 	bool has_robosw;
464 
465 	bool loopback;
466 };
467 
468 static inline u32 bgmac_read(struct bgmac *bgmac, u16 offset)
469 {
470 	return bcma_read32(bgmac->core, offset);
471 }
472 
473 static inline void bgmac_write(struct bgmac *bgmac, u16 offset, u32 value)
474 {
475 	bcma_write32(bgmac->core, offset, value);
476 }
477 
478 static inline void bgmac_maskset(struct bgmac *bgmac, u16 offset, u32 mask,
479 				   u32 set)
480 {
481 	bgmac_write(bgmac, offset, (bgmac_read(bgmac, offset) & mask) | set);
482 }
483 
484 static inline void bgmac_mask(struct bgmac *bgmac, u16 offset, u32 mask)
485 {
486 	bgmac_maskset(bgmac, offset, mask, 0);
487 }
488 
489 static inline void bgmac_set(struct bgmac *bgmac, u16 offset, u32 set)
490 {
491 	bgmac_maskset(bgmac, offset, ~0, set);
492 }
493 
494 #endif /* _BGMAC_H */
495