1 /* 2 * Driver for (BCM4706)? GBit MAC core on BCMA bus. 3 * 4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> 5 * 6 * Licensed under the GNU/GPL. See COPYING for details. 7 */ 8 9 10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 11 12 #include <linux/bcma/bcma.h> 13 #include <linux/etherdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/bcm47xx_nvram.h> 16 #include <linux/phy.h> 17 #include <linux/phy_fixed.h> 18 #include <net/dsa.h> 19 #include "bgmac.h" 20 21 static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask, 22 u32 value, int timeout) 23 { 24 u32 val; 25 int i; 26 27 for (i = 0; i < timeout / 10; i++) { 28 val = bgmac_read(bgmac, reg); 29 if ((val & mask) == value) 30 return true; 31 udelay(10); 32 } 33 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg); 34 return false; 35 } 36 37 /************************************************** 38 * DMA 39 **************************************************/ 40 41 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 42 { 43 u32 val; 44 int i; 45 46 if (!ring->mmio_base) 47 return; 48 49 /* Suspend DMA TX ring first. 50 * bgmac_wait_value doesn't support waiting for any of few values, so 51 * implement whole loop here. 52 */ 53 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 54 BGMAC_DMA_TX_SUSPEND); 55 for (i = 0; i < 10000 / 10; i++) { 56 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 57 val &= BGMAC_DMA_TX_STAT; 58 if (val == BGMAC_DMA_TX_STAT_DISABLED || 59 val == BGMAC_DMA_TX_STAT_IDLEWAIT || 60 val == BGMAC_DMA_TX_STAT_STOPPED) { 61 i = 0; 62 break; 63 } 64 udelay(10); 65 } 66 if (i) 67 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", 68 ring->mmio_base, val); 69 70 /* Remove SUSPEND bit */ 71 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); 72 if (!bgmac_wait_value(bgmac, 73 ring->mmio_base + BGMAC_DMA_TX_STATUS, 74 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, 75 10000)) { 76 dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", 77 ring->mmio_base); 78 udelay(300); 79 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 80 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) 81 dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n", 82 ring->mmio_base); 83 } 84 } 85 86 static void bgmac_dma_tx_enable(struct bgmac *bgmac, 87 struct bgmac_dma_ring *ring) 88 { 89 u32 ctl; 90 91 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); 92 if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) { 93 ctl &= ~BGMAC_DMA_TX_BL_MASK; 94 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; 95 96 ctl &= ~BGMAC_DMA_TX_MR_MASK; 97 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT; 98 99 ctl &= ~BGMAC_DMA_TX_PC_MASK; 100 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT; 101 102 ctl &= ~BGMAC_DMA_TX_PT_MASK; 103 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT; 104 } 105 ctl |= BGMAC_DMA_TX_ENABLE; 106 ctl |= BGMAC_DMA_TX_PARITY_DISABLE; 107 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); 108 } 109 110 static void 111 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 112 int i, int len, u32 ctl0) 113 { 114 struct bgmac_slot_info *slot; 115 struct bgmac_dma_desc *dma_desc; 116 u32 ctl1; 117 118 if (i == BGMAC_TX_RING_SLOTS - 1) 119 ctl0 |= BGMAC_DESC_CTL0_EOT; 120 121 ctl1 = len & BGMAC_DESC_CTL1_LEN; 122 123 slot = &ring->slots[i]; 124 dma_desc = &ring->cpu_base[i]; 125 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); 126 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); 127 dma_desc->ctl0 = cpu_to_le32(ctl0); 128 dma_desc->ctl1 = cpu_to_le32(ctl1); 129 } 130 131 #define ENET_BRCM_TAG_LEN 4 132 133 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, 134 struct bgmac_dma_ring *ring, 135 struct sk_buff *skb) 136 { 137 struct device *dma_dev = bgmac->dma_dev; 138 struct net_device *net_dev = bgmac->net_dev; 139 int index = ring->end % BGMAC_TX_RING_SLOTS; 140 struct bgmac_slot_info *slot = &ring->slots[index]; 141 int nr_frags; 142 u32 flags; 143 int i; 144 145 /* The Ethernet switch we are interfaced with needs packets to be at 146 * least 64 bytes (including FCS) otherwise they will be discarded when 147 * they enter the switch port logic. When Broadcom tags are enabled, we 148 * need to make sure that packets are at least 68 bytes 149 * (including FCS and tag) because the length verification is done after 150 * the Broadcom tag is stripped off the ingress packet. 151 */ 152 if (netdev_uses_dsa(net_dev)) { 153 if (skb_put_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) 154 goto err_stats; 155 } 156 157 if (skb->len > BGMAC_DESC_CTL1_LEN) { 158 netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len); 159 goto err_drop; 160 } 161 162 if (skb->ip_summed == CHECKSUM_PARTIAL) 163 skb_checksum_help(skb); 164 165 nr_frags = skb_shinfo(skb)->nr_frags; 166 167 /* ring->end - ring->start will return the number of valid slots, 168 * even when ring->end overflows 169 */ 170 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) { 171 netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n"); 172 netif_stop_queue(net_dev); 173 return NETDEV_TX_BUSY; 174 } 175 176 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb), 177 DMA_TO_DEVICE); 178 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 179 goto err_dma_head; 180 181 flags = BGMAC_DESC_CTL0_SOF; 182 if (!nr_frags) 183 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 184 185 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags); 186 flags = 0; 187 188 for (i = 0; i < nr_frags; i++) { 189 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 190 int len = skb_frag_size(frag); 191 192 index = (index + 1) % BGMAC_TX_RING_SLOTS; 193 slot = &ring->slots[index]; 194 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0, 195 len, DMA_TO_DEVICE); 196 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 197 goto err_dma; 198 199 if (i == nr_frags - 1) 200 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 201 202 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags); 203 } 204 205 slot->skb = skb; 206 ring->end += nr_frags + 1; 207 netdev_sent_queue(net_dev, skb->len); 208 209 wmb(); 210 211 /* Increase ring->end to point empty slot. We tell hardware the first 212 * slot it should *not* read. 213 */ 214 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, 215 ring->index_base + 216 (ring->end % BGMAC_TX_RING_SLOTS) * 217 sizeof(struct bgmac_dma_desc)); 218 219 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8) 220 netif_stop_queue(net_dev); 221 222 return NETDEV_TX_OK; 223 224 err_dma: 225 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb), 226 DMA_TO_DEVICE); 227 228 while (i-- > 0) { 229 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS; 230 struct bgmac_slot_info *slot = &ring->slots[index]; 231 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); 232 int len = ctl1 & BGMAC_DESC_CTL1_LEN; 233 234 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE); 235 } 236 237 err_dma_head: 238 netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n", 239 ring->mmio_base); 240 241 err_drop: 242 dev_kfree_skb(skb); 243 err_stats: 244 net_dev->stats.tx_dropped++; 245 net_dev->stats.tx_errors++; 246 return NETDEV_TX_OK; 247 } 248 249 /* Free transmitted packets */ 250 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 251 { 252 struct device *dma_dev = bgmac->dma_dev; 253 int empty_slot; 254 bool freed = false; 255 unsigned bytes_compl = 0, pkts_compl = 0; 256 257 /* The last slot that hardware didn't consume yet */ 258 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 259 empty_slot &= BGMAC_DMA_TX_STATDPTR; 260 empty_slot -= ring->index_base; 261 empty_slot &= BGMAC_DMA_TX_STATDPTR; 262 empty_slot /= sizeof(struct bgmac_dma_desc); 263 264 while (ring->start != ring->end) { 265 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS; 266 struct bgmac_slot_info *slot = &ring->slots[slot_idx]; 267 u32 ctl0, ctl1; 268 int len; 269 270 if (slot_idx == empty_slot) 271 break; 272 273 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0); 274 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); 275 len = ctl1 & BGMAC_DESC_CTL1_LEN; 276 if (ctl0 & BGMAC_DESC_CTL0_SOF) 277 /* Unmap no longer used buffer */ 278 dma_unmap_single(dma_dev, slot->dma_addr, len, 279 DMA_TO_DEVICE); 280 else 281 dma_unmap_page(dma_dev, slot->dma_addr, len, 282 DMA_TO_DEVICE); 283 284 if (slot->skb) { 285 bgmac->net_dev->stats.tx_bytes += slot->skb->len; 286 bgmac->net_dev->stats.tx_packets++; 287 bytes_compl += slot->skb->len; 288 pkts_compl++; 289 290 /* Free memory! :) */ 291 dev_kfree_skb(slot->skb); 292 slot->skb = NULL; 293 } 294 295 slot->dma_addr = 0; 296 ring->start++; 297 freed = true; 298 } 299 300 if (!pkts_compl) 301 return; 302 303 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); 304 305 if (netif_queue_stopped(bgmac->net_dev)) 306 netif_wake_queue(bgmac->net_dev); 307 } 308 309 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 310 { 311 if (!ring->mmio_base) 312 return; 313 314 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); 315 if (!bgmac_wait_value(bgmac, 316 ring->mmio_base + BGMAC_DMA_RX_STATUS, 317 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, 318 10000)) 319 dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n", 320 ring->mmio_base); 321 } 322 323 static void bgmac_dma_rx_enable(struct bgmac *bgmac, 324 struct bgmac_dma_ring *ring) 325 { 326 u32 ctl; 327 328 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); 329 330 /* preserve ONLY bits 16-17 from current hardware value */ 331 ctl &= BGMAC_DMA_RX_ADDREXT_MASK; 332 333 if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) { 334 ctl &= ~BGMAC_DMA_RX_BL_MASK; 335 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; 336 337 ctl &= ~BGMAC_DMA_RX_PC_MASK; 338 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT; 339 340 ctl &= ~BGMAC_DMA_RX_PT_MASK; 341 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; 342 } 343 ctl |= BGMAC_DMA_RX_ENABLE; 344 ctl |= BGMAC_DMA_RX_PARITY_DISABLE; 345 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; 346 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; 347 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); 348 } 349 350 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, 351 struct bgmac_slot_info *slot) 352 { 353 struct device *dma_dev = bgmac->dma_dev; 354 dma_addr_t dma_addr; 355 struct bgmac_rx_header *rx; 356 void *buf; 357 358 /* Alloc skb */ 359 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE); 360 if (!buf) 361 return -ENOMEM; 362 363 /* Poison - if everything goes fine, hardware will overwrite it */ 364 rx = buf + BGMAC_RX_BUF_OFFSET; 365 rx->len = cpu_to_le16(0xdead); 366 rx->flags = cpu_to_le16(0xbeef); 367 368 /* Map skb for the DMA */ 369 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET, 370 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 371 if (dma_mapping_error(dma_dev, dma_addr)) { 372 netdev_err(bgmac->net_dev, "DMA mapping error\n"); 373 put_page(virt_to_head_page(buf)); 374 return -ENOMEM; 375 } 376 377 /* Update the slot */ 378 slot->buf = buf; 379 slot->dma_addr = dma_addr; 380 381 return 0; 382 } 383 384 static void bgmac_dma_rx_update_index(struct bgmac *bgmac, 385 struct bgmac_dma_ring *ring) 386 { 387 dma_wmb(); 388 389 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, 390 ring->index_base + 391 ring->end * sizeof(struct bgmac_dma_desc)); 392 } 393 394 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, 395 struct bgmac_dma_ring *ring, int desc_idx) 396 { 397 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; 398 u32 ctl0 = 0, ctl1 = 0; 399 400 if (desc_idx == BGMAC_RX_RING_SLOTS - 1) 401 ctl0 |= BGMAC_DESC_CTL0_EOT; 402 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; 403 /* Is there any BGMAC device that requires extension? */ 404 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & 405 * B43_DMA64_DCTL1_ADDREXT_MASK; 406 */ 407 408 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr)); 409 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); 410 dma_desc->ctl0 = cpu_to_le32(ctl0); 411 dma_desc->ctl1 = cpu_to_le32(ctl1); 412 413 ring->end = desc_idx; 414 } 415 416 static void bgmac_dma_rx_poison_buf(struct device *dma_dev, 417 struct bgmac_slot_info *slot) 418 { 419 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 420 421 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, 422 DMA_FROM_DEVICE); 423 rx->len = cpu_to_le16(0xdead); 424 rx->flags = cpu_to_le16(0xbeef); 425 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, 426 DMA_FROM_DEVICE); 427 } 428 429 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 430 int weight) 431 { 432 u32 end_slot; 433 int handled = 0; 434 435 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); 436 end_slot &= BGMAC_DMA_RX_STATDPTR; 437 end_slot -= ring->index_base; 438 end_slot &= BGMAC_DMA_RX_STATDPTR; 439 end_slot /= sizeof(struct bgmac_dma_desc); 440 441 while (ring->start != end_slot) { 442 struct device *dma_dev = bgmac->dma_dev; 443 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 444 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 445 struct sk_buff *skb; 446 void *buf = slot->buf; 447 dma_addr_t dma_addr = slot->dma_addr; 448 u16 len, flags; 449 450 do { 451 /* Prepare new skb as replacement */ 452 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) { 453 bgmac_dma_rx_poison_buf(dma_dev, slot); 454 break; 455 } 456 457 /* Unmap buffer to make it accessible to the CPU */ 458 dma_unmap_single(dma_dev, dma_addr, 459 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 460 461 /* Get info from the header */ 462 len = le16_to_cpu(rx->len); 463 flags = le16_to_cpu(rx->flags); 464 465 /* Check for poison and drop or pass the packet */ 466 if (len == 0xdead && flags == 0xbeef) { 467 netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n", 468 ring->start); 469 put_page(virt_to_head_page(buf)); 470 bgmac->net_dev->stats.rx_errors++; 471 break; 472 } 473 474 if (len > BGMAC_RX_ALLOC_SIZE) { 475 netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n", 476 ring->start); 477 put_page(virt_to_head_page(buf)); 478 bgmac->net_dev->stats.rx_length_errors++; 479 bgmac->net_dev->stats.rx_errors++; 480 break; 481 } 482 483 /* Omit CRC. */ 484 len -= ETH_FCS_LEN; 485 486 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); 487 if (unlikely(!skb)) { 488 netdev_err(bgmac->net_dev, "build_skb failed\n"); 489 put_page(virt_to_head_page(buf)); 490 bgmac->net_dev->stats.rx_errors++; 491 break; 492 } 493 skb_put(skb, BGMAC_RX_FRAME_OFFSET + 494 BGMAC_RX_BUF_OFFSET + len); 495 skb_pull(skb, BGMAC_RX_FRAME_OFFSET + 496 BGMAC_RX_BUF_OFFSET); 497 498 skb_checksum_none_assert(skb); 499 skb->protocol = eth_type_trans(skb, bgmac->net_dev); 500 bgmac->net_dev->stats.rx_bytes += len; 501 bgmac->net_dev->stats.rx_packets++; 502 napi_gro_receive(&bgmac->napi, skb); 503 handled++; 504 } while (0); 505 506 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); 507 508 if (++ring->start >= BGMAC_RX_RING_SLOTS) 509 ring->start = 0; 510 511 if (handled >= weight) /* Should never be greater */ 512 break; 513 } 514 515 bgmac_dma_rx_update_index(bgmac, ring); 516 517 return handled; 518 } 519 520 /* Does ring support unaligned addressing? */ 521 static bool bgmac_dma_unaligned(struct bgmac *bgmac, 522 struct bgmac_dma_ring *ring, 523 enum bgmac_dma_ring_type ring_type) 524 { 525 switch (ring_type) { 526 case BGMAC_DMA_RING_TX: 527 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 528 0xff0); 529 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) 530 return true; 531 break; 532 case BGMAC_DMA_RING_RX: 533 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 534 0xff0); 535 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) 536 return true; 537 break; 538 } 539 return false; 540 } 541 542 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac, 543 struct bgmac_dma_ring *ring) 544 { 545 struct device *dma_dev = bgmac->dma_dev; 546 struct bgmac_dma_desc *dma_desc = ring->cpu_base; 547 struct bgmac_slot_info *slot; 548 int i; 549 550 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) { 551 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN; 552 553 slot = &ring->slots[i]; 554 dev_kfree_skb(slot->skb); 555 556 if (!slot->dma_addr) 557 continue; 558 559 if (slot->skb) 560 dma_unmap_single(dma_dev, slot->dma_addr, 561 len, DMA_TO_DEVICE); 562 else 563 dma_unmap_page(dma_dev, slot->dma_addr, 564 len, DMA_TO_DEVICE); 565 } 566 } 567 568 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac, 569 struct bgmac_dma_ring *ring) 570 { 571 struct device *dma_dev = bgmac->dma_dev; 572 struct bgmac_slot_info *slot; 573 int i; 574 575 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) { 576 slot = &ring->slots[i]; 577 if (!slot->dma_addr) 578 continue; 579 580 dma_unmap_single(dma_dev, slot->dma_addr, 581 BGMAC_RX_BUF_SIZE, 582 DMA_FROM_DEVICE); 583 put_page(virt_to_head_page(slot->buf)); 584 slot->dma_addr = 0; 585 } 586 } 587 588 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, 589 struct bgmac_dma_ring *ring, 590 int num_slots) 591 { 592 struct device *dma_dev = bgmac->dma_dev; 593 int size; 594 595 if (!ring->cpu_base) 596 return; 597 598 /* Free ring of descriptors */ 599 size = num_slots * sizeof(struct bgmac_dma_desc); 600 dma_free_coherent(dma_dev, size, ring->cpu_base, 601 ring->dma_base); 602 } 603 604 static void bgmac_dma_cleanup(struct bgmac *bgmac) 605 { 606 int i; 607 608 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 609 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); 610 611 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 612 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); 613 } 614 615 static void bgmac_dma_free(struct bgmac *bgmac) 616 { 617 int i; 618 619 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 620 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i], 621 BGMAC_TX_RING_SLOTS); 622 623 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 624 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i], 625 BGMAC_RX_RING_SLOTS); 626 } 627 628 static int bgmac_dma_alloc(struct bgmac *bgmac) 629 { 630 struct device *dma_dev = bgmac->dma_dev; 631 struct bgmac_dma_ring *ring; 632 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, 633 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, }; 634 int size; /* ring size: different for Tx and Rx */ 635 int err; 636 int i; 637 638 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); 639 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); 640 641 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) { 642 if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) { 643 dev_err(bgmac->dev, "Core does not report 64-bit DMA\n"); 644 return -ENOTSUPP; 645 } 646 } 647 648 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 649 ring = &bgmac->tx_ring[i]; 650 ring->mmio_base = ring_base[i]; 651 652 /* Alloc ring of descriptors */ 653 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc); 654 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 655 &ring->dma_base, 656 GFP_KERNEL); 657 if (!ring->cpu_base) { 658 dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n", 659 ring->mmio_base); 660 goto err_dma_free; 661 } 662 663 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 664 BGMAC_DMA_RING_TX); 665 if (ring->unaligned) 666 ring->index_base = lower_32_bits(ring->dma_base); 667 else 668 ring->index_base = 0; 669 670 /* No need to alloc TX slots yet */ 671 } 672 673 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 674 ring = &bgmac->rx_ring[i]; 675 ring->mmio_base = ring_base[i]; 676 677 /* Alloc ring of descriptors */ 678 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc); 679 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 680 &ring->dma_base, 681 GFP_KERNEL); 682 if (!ring->cpu_base) { 683 dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n", 684 ring->mmio_base); 685 err = -ENOMEM; 686 goto err_dma_free; 687 } 688 689 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 690 BGMAC_DMA_RING_RX); 691 if (ring->unaligned) 692 ring->index_base = lower_32_bits(ring->dma_base); 693 else 694 ring->index_base = 0; 695 } 696 697 return 0; 698 699 err_dma_free: 700 bgmac_dma_free(bgmac); 701 return -ENOMEM; 702 } 703 704 static int bgmac_dma_init(struct bgmac *bgmac) 705 { 706 struct bgmac_dma_ring *ring; 707 int i, err; 708 709 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 710 ring = &bgmac->tx_ring[i]; 711 712 if (!ring->unaligned) 713 bgmac_dma_tx_enable(bgmac, ring); 714 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 715 lower_32_bits(ring->dma_base)); 716 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, 717 upper_32_bits(ring->dma_base)); 718 if (ring->unaligned) 719 bgmac_dma_tx_enable(bgmac, ring); 720 721 ring->start = 0; 722 ring->end = 0; /* Points the slot that should *not* be read */ 723 } 724 725 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 726 int j; 727 728 ring = &bgmac->rx_ring[i]; 729 730 if (!ring->unaligned) 731 bgmac_dma_rx_enable(bgmac, ring); 732 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 733 lower_32_bits(ring->dma_base)); 734 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, 735 upper_32_bits(ring->dma_base)); 736 if (ring->unaligned) 737 bgmac_dma_rx_enable(bgmac, ring); 738 739 ring->start = 0; 740 ring->end = 0; 741 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) { 742 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); 743 if (err) 744 goto error; 745 746 bgmac_dma_rx_setup_desc(bgmac, ring, j); 747 } 748 749 bgmac_dma_rx_update_index(bgmac, ring); 750 } 751 752 return 0; 753 754 error: 755 bgmac_dma_cleanup(bgmac); 756 return err; 757 } 758 759 760 /************************************************** 761 * Chip ops 762 **************************************************/ 763 764 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is 765 * nothing to change? Try if after stabilizng driver. 766 */ 767 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, 768 bool force) 769 { 770 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 771 u32 new_val = (cmdcfg & mask) | set; 772 u32 cmdcfg_sr; 773 774 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) 775 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; 776 else 777 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; 778 779 bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr); 780 udelay(2); 781 782 if (new_val != cmdcfg || force) 783 bgmac_write(bgmac, BGMAC_CMDCFG, new_val); 784 785 bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr); 786 udelay(2); 787 } 788 789 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr) 790 { 791 u32 tmp; 792 793 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 794 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); 795 tmp = (addr[4] << 8) | addr[5]; 796 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); 797 } 798 799 static void bgmac_set_rx_mode(struct net_device *net_dev) 800 { 801 struct bgmac *bgmac = netdev_priv(net_dev); 802 803 if (net_dev->flags & IFF_PROMISC) 804 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true); 805 else 806 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true); 807 } 808 809 #if 0 /* We don't use that regs yet */ 810 static void bgmac_chip_stats_update(struct bgmac *bgmac) 811 { 812 int i; 813 814 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) { 815 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 816 bgmac->mib_tx_regs[i] = 817 bgmac_read(bgmac, 818 BGMAC_TX_GOOD_OCTETS + (i * 4)); 819 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 820 bgmac->mib_rx_regs[i] = 821 bgmac_read(bgmac, 822 BGMAC_RX_GOOD_OCTETS + (i * 4)); 823 } 824 825 /* TODO: what else? how to handle BCM4706? Specs are needed */ 826 } 827 #endif 828 829 static void bgmac_clear_mib(struct bgmac *bgmac) 830 { 831 int i; 832 833 if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB) 834 return; 835 836 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); 837 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 838 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); 839 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 840 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); 841 } 842 843 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ 844 static void bgmac_mac_speed(struct bgmac *bgmac) 845 { 846 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); 847 u32 set = 0; 848 849 switch (bgmac->mac_speed) { 850 case SPEED_10: 851 set |= BGMAC_CMDCFG_ES_10; 852 break; 853 case SPEED_100: 854 set |= BGMAC_CMDCFG_ES_100; 855 break; 856 case SPEED_1000: 857 set |= BGMAC_CMDCFG_ES_1000; 858 break; 859 case SPEED_2500: 860 set |= BGMAC_CMDCFG_ES_2500; 861 break; 862 default: 863 dev_err(bgmac->dev, "Unsupported speed: %d\n", 864 bgmac->mac_speed); 865 } 866 867 if (bgmac->mac_duplex == DUPLEX_HALF) 868 set |= BGMAC_CMDCFG_HD; 869 870 bgmac_cmdcfg_maskset(bgmac, mask, set, true); 871 } 872 873 static void bgmac_miiconfig(struct bgmac *bgmac) 874 { 875 if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) { 876 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) { 877 bgmac_idm_write(bgmac, BCMA_IOCTL, 878 bgmac_idm_read(bgmac, BCMA_IOCTL) | 879 0x40 | BGMAC_BCMA_IOCTL_SW_CLKEN); 880 } 881 bgmac->mac_speed = SPEED_2500; 882 bgmac->mac_duplex = DUPLEX_FULL; 883 bgmac_mac_speed(bgmac); 884 } else { 885 u8 imode; 886 887 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & 888 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; 889 if (imode == 0 || imode == 1) { 890 bgmac->mac_speed = SPEED_100; 891 bgmac->mac_duplex = DUPLEX_FULL; 892 bgmac_mac_speed(bgmac); 893 } 894 } 895 } 896 897 static void bgmac_chip_reset_idm_config(struct bgmac *bgmac) 898 { 899 u32 iost; 900 901 iost = bgmac_idm_read(bgmac, BCMA_IOST); 902 if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED) 903 iost &= ~BGMAC_BCMA_IOST_ATTACHED; 904 905 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */ 906 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) { 907 u32 flags = 0; 908 909 if (iost & BGMAC_BCMA_IOST_ATTACHED) { 910 flags = BGMAC_BCMA_IOCTL_SW_CLKEN; 911 if (!bgmac->has_robosw) 912 flags |= BGMAC_BCMA_IOCTL_SW_RESET; 913 } 914 bgmac_clk_enable(bgmac, flags); 915 } 916 917 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) 918 bgmac_idm_write(bgmac, BCMA_IOCTL, 919 bgmac_idm_read(bgmac, BCMA_IOCTL) & 920 ~BGMAC_BCMA_IOCTL_SW_RESET); 921 } 922 923 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ 924 static void bgmac_chip_reset(struct bgmac *bgmac) 925 { 926 u32 cmdcfg_sr; 927 int i; 928 929 if (bgmac_clk_enabled(bgmac)) { 930 if (!bgmac->stats_grabbed) { 931 /* bgmac_chip_stats_update(bgmac); */ 932 bgmac->stats_grabbed = true; 933 } 934 935 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 936 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); 937 938 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 939 udelay(1); 940 941 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 942 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); 943 944 /* TODO: Clear software multicast filter list */ 945 } 946 947 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) 948 bgmac_chip_reset_idm_config(bgmac); 949 950 /* Request Misc PLL for corerev > 2 */ 951 if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) { 952 bgmac_set(bgmac, BCMA_CLKCTLST, 953 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); 954 bgmac_wait_value(bgmac, BCMA_CLKCTLST, 955 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 956 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 957 1000); 958 } 959 960 if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) { 961 u8 et_swtype = 0; 962 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | 963 BGMAC_CHIPCTL_1_IF_TYPE_MII; 964 char buf[4]; 965 966 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 967 if (kstrtou8(buf, 0, &et_swtype)) 968 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n", 969 buf); 970 et_swtype &= 0x0f; 971 et_swtype <<= 4; 972 sw_type = et_swtype; 973 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) { 974 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RMII | 975 BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; 976 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) { 977 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | 978 BGMAC_CHIPCTL_1_SW_TYPE_RGMII; 979 } 980 bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | 981 BGMAC_CHIPCTL_1_SW_TYPE_MASK), 982 sw_type); 983 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE) { 984 u32 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_MII | 985 BGMAC_CHIPCTL_4_SW_TYPE_EPHY; 986 u8 et_swtype = 0; 987 char buf[4]; 988 989 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 990 if (kstrtou8(buf, 0, &et_swtype)) 991 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n", 992 buf); 993 sw_type = (et_swtype & 0x0f) << 12; 994 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII) { 995 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_RGMII | 996 BGMAC_CHIPCTL_4_SW_TYPE_RGMII; 997 } 998 bgmac_cco_ctl_maskset(bgmac, 4, ~(BGMAC_CHIPCTL_4_IF_TYPE_MASK | 999 BGMAC_CHIPCTL_4_SW_TYPE_MASK), 1000 sw_type); 1001 } else if (bgmac->feature_flags & BGMAC_FEAT_CC7_IF_TYPE_RGMII) { 1002 bgmac_cco_ctl_maskset(bgmac, 7, ~BGMAC_CHIPCTL_7_IF_TYPE_MASK, 1003 BGMAC_CHIPCTL_7_IF_TYPE_RGMII); 1004 } 1005 1006 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset 1007 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine 1008 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to 1009 * be keps until taking MAC out of the reset. 1010 */ 1011 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) 1012 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; 1013 else 1014 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; 1015 1016 bgmac_cmdcfg_maskset(bgmac, 1017 ~(BGMAC_CMDCFG_TE | 1018 BGMAC_CMDCFG_RE | 1019 BGMAC_CMDCFG_RPI | 1020 BGMAC_CMDCFG_TAI | 1021 BGMAC_CMDCFG_HD | 1022 BGMAC_CMDCFG_ML | 1023 BGMAC_CMDCFG_CFE | 1024 BGMAC_CMDCFG_RL | 1025 BGMAC_CMDCFG_RED | 1026 BGMAC_CMDCFG_PE | 1027 BGMAC_CMDCFG_TPI | 1028 BGMAC_CMDCFG_PAD_EN | 1029 BGMAC_CMDCFG_PF), 1030 BGMAC_CMDCFG_PROM | 1031 BGMAC_CMDCFG_NLC | 1032 BGMAC_CMDCFG_CFE | 1033 cmdcfg_sr, 1034 false); 1035 bgmac->mac_speed = SPEED_UNKNOWN; 1036 bgmac->mac_duplex = DUPLEX_UNKNOWN; 1037 1038 bgmac_clear_mib(bgmac); 1039 if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL) 1040 bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0, 1041 BCMA_GMAC_CMN_PC_MTE); 1042 else 1043 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); 1044 bgmac_miiconfig(bgmac); 1045 if (bgmac->mii_bus) 1046 bgmac->mii_bus->reset(bgmac->mii_bus); 1047 1048 netdev_reset_queue(bgmac->net_dev); 1049 } 1050 1051 static void bgmac_chip_intrs_on(struct bgmac *bgmac) 1052 { 1053 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); 1054 } 1055 1056 static void bgmac_chip_intrs_off(struct bgmac *bgmac) 1057 { 1058 bgmac_write(bgmac, BGMAC_INT_MASK, 0); 1059 bgmac_read(bgmac, BGMAC_INT_MASK); 1060 } 1061 1062 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ 1063 static void bgmac_enable(struct bgmac *bgmac) 1064 { 1065 u32 cmdcfg_sr; 1066 u32 cmdcfg; 1067 u32 mode; 1068 1069 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) 1070 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; 1071 else 1072 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; 1073 1074 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 1075 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), 1076 cmdcfg_sr, true); 1077 udelay(2); 1078 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; 1079 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); 1080 1081 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 1082 BGMAC_DS_MM_SHIFT; 1083 if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0) 1084 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 1085 if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) && mode == 2) 1086 bgmac_cco_ctl_maskset(bgmac, 1, ~0, 1087 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); 1088 1089 if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 | 1090 BGMAC_FEAT_FLW_CTRL2)) { 1091 u32 fl_ctl; 1092 1093 if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1) 1094 fl_ctl = 0x2300e1; 1095 else 1096 fl_ctl = 0x03cb04cb; 1097 1098 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); 1099 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); 1100 } 1101 1102 if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) { 1103 u32 rxq_ctl; 1104 u16 bp_clk; 1105 u8 mdp; 1106 1107 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); 1108 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; 1109 bp_clk = bgmac_get_bus_clock(bgmac) / 1000000; 1110 mdp = (bp_clk * 128 / 1000) - 3; 1111 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); 1112 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); 1113 } 1114 } 1115 1116 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ 1117 static void bgmac_chip_init(struct bgmac *bgmac) 1118 { 1119 /* Clear any erroneously pending interrupts */ 1120 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); 1121 1122 /* 1 interrupt per received frame */ 1123 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); 1124 1125 /* Enable 802.3x tx flow control (honor received PAUSE frames) */ 1126 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); 1127 1128 bgmac_set_rx_mode(bgmac->net_dev); 1129 1130 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr); 1131 1132 if (bgmac->loopback) 1133 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1134 else 1135 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false); 1136 1137 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); 1138 1139 bgmac_chip_intrs_on(bgmac); 1140 1141 bgmac_enable(bgmac); 1142 } 1143 1144 static irqreturn_t bgmac_interrupt(int irq, void *dev_id) 1145 { 1146 struct bgmac *bgmac = netdev_priv(dev_id); 1147 1148 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); 1149 int_status &= bgmac->int_mask; 1150 1151 if (!int_status) 1152 return IRQ_NONE; 1153 1154 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX); 1155 if (int_status) 1156 dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status); 1157 1158 /* Disable new interrupts until handling existing ones */ 1159 bgmac_chip_intrs_off(bgmac); 1160 1161 napi_schedule(&bgmac->napi); 1162 1163 return IRQ_HANDLED; 1164 } 1165 1166 static int bgmac_poll(struct napi_struct *napi, int weight) 1167 { 1168 struct bgmac *bgmac = container_of(napi, struct bgmac, napi); 1169 int handled = 0; 1170 1171 /* Ack */ 1172 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); 1173 1174 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]); 1175 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight); 1176 1177 /* Poll again if more events arrived in the meantime */ 1178 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX)) 1179 return weight; 1180 1181 if (handled < weight) { 1182 napi_complete_done(napi, handled); 1183 bgmac_chip_intrs_on(bgmac); 1184 } 1185 1186 return handled; 1187 } 1188 1189 /************************************************** 1190 * net_device_ops 1191 **************************************************/ 1192 1193 static int bgmac_open(struct net_device *net_dev) 1194 { 1195 struct bgmac *bgmac = netdev_priv(net_dev); 1196 int err = 0; 1197 1198 bgmac_chip_reset(bgmac); 1199 1200 err = bgmac_dma_init(bgmac); 1201 if (err) 1202 return err; 1203 1204 /* Specs say about reclaiming rings here, but we do that in DMA init */ 1205 bgmac_chip_init(bgmac); 1206 1207 err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED, 1208 KBUILD_MODNAME, net_dev); 1209 if (err < 0) { 1210 dev_err(bgmac->dev, "IRQ request error: %d!\n", err); 1211 bgmac_dma_cleanup(bgmac); 1212 return err; 1213 } 1214 napi_enable(&bgmac->napi); 1215 1216 phy_start(net_dev->phydev); 1217 1218 netif_start_queue(net_dev); 1219 1220 return 0; 1221 } 1222 1223 static int bgmac_stop(struct net_device *net_dev) 1224 { 1225 struct bgmac *bgmac = netdev_priv(net_dev); 1226 1227 netif_carrier_off(net_dev); 1228 1229 phy_stop(net_dev->phydev); 1230 1231 napi_disable(&bgmac->napi); 1232 bgmac_chip_intrs_off(bgmac); 1233 free_irq(bgmac->irq, net_dev); 1234 1235 bgmac_chip_reset(bgmac); 1236 bgmac_dma_cleanup(bgmac); 1237 1238 return 0; 1239 } 1240 1241 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, 1242 struct net_device *net_dev) 1243 { 1244 struct bgmac *bgmac = netdev_priv(net_dev); 1245 struct bgmac_dma_ring *ring; 1246 1247 /* No QOS support yet */ 1248 ring = &bgmac->tx_ring[0]; 1249 return bgmac_dma_tx_add(bgmac, ring, skb); 1250 } 1251 1252 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr) 1253 { 1254 struct bgmac *bgmac = netdev_priv(net_dev); 1255 struct sockaddr *sa = addr; 1256 int ret; 1257 1258 ret = eth_prepare_mac_addr_change(net_dev, addr); 1259 if (ret < 0) 1260 return ret; 1261 1262 ether_addr_copy(net_dev->dev_addr, sa->sa_data); 1263 bgmac_write_mac_address(bgmac, net_dev->dev_addr); 1264 1265 eth_commit_mac_addr_change(net_dev, addr); 1266 return 0; 1267 } 1268 1269 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1270 { 1271 if (!netif_running(net_dev)) 1272 return -EINVAL; 1273 1274 return phy_mii_ioctl(net_dev->phydev, ifr, cmd); 1275 } 1276 1277 static const struct net_device_ops bgmac_netdev_ops = { 1278 .ndo_open = bgmac_open, 1279 .ndo_stop = bgmac_stop, 1280 .ndo_start_xmit = bgmac_start_xmit, 1281 .ndo_set_rx_mode = bgmac_set_rx_mode, 1282 .ndo_set_mac_address = bgmac_set_mac_address, 1283 .ndo_validate_addr = eth_validate_addr, 1284 .ndo_do_ioctl = bgmac_ioctl, 1285 }; 1286 1287 /************************************************** 1288 * ethtool_ops 1289 **************************************************/ 1290 1291 struct bgmac_stat { 1292 u8 size; 1293 u32 offset; 1294 const char *name; 1295 }; 1296 1297 static struct bgmac_stat bgmac_get_strings_stats[] = { 1298 { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" }, 1299 { 4, BGMAC_TX_GOOD_PKTS, "tx_good" }, 1300 { 8, BGMAC_TX_OCTETS, "tx_octets" }, 1301 { 4, BGMAC_TX_PKTS, "tx_pkts" }, 1302 { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" }, 1303 { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" }, 1304 { 4, BGMAC_TX_LEN_64, "tx_64" }, 1305 { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" }, 1306 { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" }, 1307 { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" }, 1308 { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" }, 1309 { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" }, 1310 { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" }, 1311 { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" }, 1312 { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" }, 1313 { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" }, 1314 { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" }, 1315 { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" }, 1316 { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" }, 1317 { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" }, 1318 { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" }, 1319 { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" }, 1320 { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" }, 1321 { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" }, 1322 { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" }, 1323 { 4, BGMAC_TX_DEFERED, "tx_defered" }, 1324 { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" }, 1325 { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" }, 1326 { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" }, 1327 { 4, BGMAC_TX_Q0_PKTS, "tx_q0" }, 1328 { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" }, 1329 { 4, BGMAC_TX_Q1_PKTS, "tx_q1" }, 1330 { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" }, 1331 { 4, BGMAC_TX_Q2_PKTS, "tx_q2" }, 1332 { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" }, 1333 { 4, BGMAC_TX_Q3_PKTS, "tx_q3" }, 1334 { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" }, 1335 { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" }, 1336 { 4, BGMAC_RX_GOOD_PKTS, "rx_good" }, 1337 { 8, BGMAC_RX_OCTETS, "rx_octets" }, 1338 { 4, BGMAC_RX_PKTS, "rx_pkts" }, 1339 { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" }, 1340 { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" }, 1341 { 4, BGMAC_RX_LEN_64, "rx_64" }, 1342 { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" }, 1343 { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" }, 1344 { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" }, 1345 { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" }, 1346 { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" }, 1347 { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" }, 1348 { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" }, 1349 { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" }, 1350 { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" }, 1351 { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" }, 1352 { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" }, 1353 { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" }, 1354 { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" }, 1355 { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" }, 1356 { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" }, 1357 { 4, BGMAC_RX_CRC_ERRS, "rx_crc" }, 1358 { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" }, 1359 { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" }, 1360 { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" }, 1361 { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" }, 1362 { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" }, 1363 { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" }, 1364 }; 1365 1366 #define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats) 1367 1368 static int bgmac_get_sset_count(struct net_device *dev, int string_set) 1369 { 1370 switch (string_set) { 1371 case ETH_SS_STATS: 1372 return BGMAC_STATS_LEN; 1373 } 1374 1375 return -EOPNOTSUPP; 1376 } 1377 1378 static void bgmac_get_strings(struct net_device *dev, u32 stringset, 1379 u8 *data) 1380 { 1381 int i; 1382 1383 if (stringset != ETH_SS_STATS) 1384 return; 1385 1386 for (i = 0; i < BGMAC_STATS_LEN; i++) 1387 strlcpy(data + i * ETH_GSTRING_LEN, 1388 bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN); 1389 } 1390 1391 static void bgmac_get_ethtool_stats(struct net_device *dev, 1392 struct ethtool_stats *ss, uint64_t *data) 1393 { 1394 struct bgmac *bgmac = netdev_priv(dev); 1395 const struct bgmac_stat *s; 1396 unsigned int i; 1397 u64 val; 1398 1399 if (!netif_running(dev)) 1400 return; 1401 1402 for (i = 0; i < BGMAC_STATS_LEN; i++) { 1403 s = &bgmac_get_strings_stats[i]; 1404 val = 0; 1405 if (s->size == 8) 1406 val = (u64)bgmac_read(bgmac, s->offset + 4) << 32; 1407 val |= bgmac_read(bgmac, s->offset); 1408 data[i] = val; 1409 } 1410 } 1411 1412 static void bgmac_get_drvinfo(struct net_device *net_dev, 1413 struct ethtool_drvinfo *info) 1414 { 1415 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1416 strlcpy(info->bus_info, "AXI", sizeof(info->bus_info)); 1417 } 1418 1419 static const struct ethtool_ops bgmac_ethtool_ops = { 1420 .get_strings = bgmac_get_strings, 1421 .get_sset_count = bgmac_get_sset_count, 1422 .get_ethtool_stats = bgmac_get_ethtool_stats, 1423 .get_drvinfo = bgmac_get_drvinfo, 1424 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1425 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1426 }; 1427 1428 /************************************************** 1429 * MII 1430 **************************************************/ 1431 1432 void bgmac_adjust_link(struct net_device *net_dev) 1433 { 1434 struct bgmac *bgmac = netdev_priv(net_dev); 1435 struct phy_device *phy_dev = net_dev->phydev; 1436 bool update = false; 1437 1438 if (phy_dev->link) { 1439 if (phy_dev->speed != bgmac->mac_speed) { 1440 bgmac->mac_speed = phy_dev->speed; 1441 update = true; 1442 } 1443 1444 if (phy_dev->duplex != bgmac->mac_duplex) { 1445 bgmac->mac_duplex = phy_dev->duplex; 1446 update = true; 1447 } 1448 } 1449 1450 if (update) { 1451 bgmac_mac_speed(bgmac); 1452 phy_print_status(phy_dev); 1453 } 1454 } 1455 EXPORT_SYMBOL_GPL(bgmac_adjust_link); 1456 1457 int bgmac_phy_connect_direct(struct bgmac *bgmac) 1458 { 1459 struct fixed_phy_status fphy_status = { 1460 .link = 1, 1461 .speed = SPEED_1000, 1462 .duplex = DUPLEX_FULL, 1463 }; 1464 struct phy_device *phy_dev; 1465 int err; 1466 1467 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); 1468 if (!phy_dev || IS_ERR(phy_dev)) { 1469 dev_err(bgmac->dev, "Failed to register fixed PHY device\n"); 1470 return -ENODEV; 1471 } 1472 1473 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link, 1474 PHY_INTERFACE_MODE_MII); 1475 if (err) { 1476 dev_err(bgmac->dev, "Connecting PHY failed\n"); 1477 return err; 1478 } 1479 1480 return err; 1481 } 1482 EXPORT_SYMBOL_GPL(bgmac_phy_connect_direct); 1483 1484 struct bgmac *bgmac_alloc(struct device *dev) 1485 { 1486 struct net_device *net_dev; 1487 struct bgmac *bgmac; 1488 1489 /* Allocation and references */ 1490 net_dev = devm_alloc_etherdev(dev, sizeof(*bgmac)); 1491 if (!net_dev) 1492 return NULL; 1493 1494 net_dev->netdev_ops = &bgmac_netdev_ops; 1495 net_dev->ethtool_ops = &bgmac_ethtool_ops; 1496 1497 bgmac = netdev_priv(net_dev); 1498 bgmac->dev = dev; 1499 bgmac->net_dev = net_dev; 1500 1501 return bgmac; 1502 } 1503 EXPORT_SYMBOL_GPL(bgmac_alloc); 1504 1505 int bgmac_enet_probe(struct bgmac *bgmac) 1506 { 1507 struct net_device *net_dev = bgmac->net_dev; 1508 int err; 1509 1510 net_dev->irq = bgmac->irq; 1511 SET_NETDEV_DEV(net_dev, bgmac->dev); 1512 dev_set_drvdata(bgmac->dev, bgmac); 1513 1514 if (!is_valid_ether_addr(net_dev->dev_addr)) { 1515 dev_err(bgmac->dev, "Invalid MAC addr: %pM\n", 1516 net_dev->dev_addr); 1517 eth_hw_addr_random(net_dev); 1518 dev_warn(bgmac->dev, "Using random MAC: %pM\n", 1519 net_dev->dev_addr); 1520 } 1521 1522 /* This (reset &) enable is not preset in specs or reference driver but 1523 * Broadcom does it in arch PCI code when enabling fake PCI device. 1524 */ 1525 bgmac_clk_enable(bgmac, 0); 1526 1527 /* This seems to be fixing IRQ by assigning OOB #6 to the core */ 1528 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) { 1529 if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6) 1530 bgmac_idm_write(bgmac, BCMA_OOB_SEL_OUT_A30, 0x86); 1531 } 1532 1533 bgmac_chip_reset(bgmac); 1534 1535 err = bgmac_dma_alloc(bgmac); 1536 if (err) { 1537 dev_err(bgmac->dev, "Unable to alloc memory for DMA\n"); 1538 goto err_out; 1539 } 1540 1541 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; 1542 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0) 1543 bgmac->int_mask &= ~BGMAC_IS_TX_MASK; 1544 1545 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); 1546 1547 err = bgmac_phy_connect(bgmac); 1548 if (err) { 1549 dev_err(bgmac->dev, "Cannot connect to phy\n"); 1550 goto err_dma_free; 1551 } 1552 1553 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1554 net_dev->hw_features = net_dev->features; 1555 net_dev->vlan_features = net_dev->features; 1556 1557 err = register_netdev(bgmac->net_dev); 1558 if (err) { 1559 dev_err(bgmac->dev, "Cannot register net device\n"); 1560 goto err_phy_disconnect; 1561 } 1562 1563 netif_carrier_off(net_dev); 1564 1565 return 0; 1566 1567 err_phy_disconnect: 1568 phy_disconnect(net_dev->phydev); 1569 err_dma_free: 1570 bgmac_dma_free(bgmac); 1571 err_out: 1572 1573 return err; 1574 } 1575 EXPORT_SYMBOL_GPL(bgmac_enet_probe); 1576 1577 void bgmac_enet_remove(struct bgmac *bgmac) 1578 { 1579 unregister_netdev(bgmac->net_dev); 1580 phy_disconnect(bgmac->net_dev->phydev); 1581 netif_napi_del(&bgmac->napi); 1582 bgmac_dma_free(bgmac); 1583 free_netdev(bgmac->net_dev); 1584 } 1585 EXPORT_SYMBOL_GPL(bgmac_enet_remove); 1586 1587 int bgmac_enet_suspend(struct bgmac *bgmac) 1588 { 1589 if (!netif_running(bgmac->net_dev)) 1590 return 0; 1591 1592 phy_stop(bgmac->net_dev->phydev); 1593 1594 netif_stop_queue(bgmac->net_dev); 1595 1596 napi_disable(&bgmac->napi); 1597 1598 netif_tx_lock(bgmac->net_dev); 1599 netif_device_detach(bgmac->net_dev); 1600 netif_tx_unlock(bgmac->net_dev); 1601 1602 bgmac_chip_intrs_off(bgmac); 1603 bgmac_chip_reset(bgmac); 1604 bgmac_dma_cleanup(bgmac); 1605 1606 return 0; 1607 } 1608 EXPORT_SYMBOL_GPL(bgmac_enet_suspend); 1609 1610 int bgmac_enet_resume(struct bgmac *bgmac) 1611 { 1612 int rc; 1613 1614 if (!netif_running(bgmac->net_dev)) 1615 return 0; 1616 1617 rc = bgmac_dma_init(bgmac); 1618 if (rc) 1619 return rc; 1620 1621 bgmac_chip_init(bgmac); 1622 1623 napi_enable(&bgmac->napi); 1624 1625 netif_tx_lock(bgmac->net_dev); 1626 netif_device_attach(bgmac->net_dev); 1627 netif_tx_unlock(bgmac->net_dev); 1628 1629 netif_start_queue(bgmac->net_dev); 1630 1631 phy_start(bgmac->net_dev->phydev); 1632 1633 return 0; 1634 } 1635 EXPORT_SYMBOL_GPL(bgmac_enet_resume); 1636 1637 MODULE_AUTHOR("Rafał Miłecki"); 1638 MODULE_LICENSE("GPL"); 1639