1 /* 2 * Driver for (BCM4706)? GBit MAC core on BCMA bus. 3 * 4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> 5 * 6 * Licensed under the GNU/GPL. See COPYING for details. 7 */ 8 9 10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 11 12 #include <linux/bcma/bcma.h> 13 #include <linux/etherdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/bcm47xx_nvram.h> 16 #include <linux/phy.h> 17 #include <linux/phy_fixed.h> 18 #include <net/dsa.h> 19 #include "bgmac.h" 20 21 static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask, 22 u32 value, int timeout) 23 { 24 u32 val; 25 int i; 26 27 for (i = 0; i < timeout / 10; i++) { 28 val = bgmac_read(bgmac, reg); 29 if ((val & mask) == value) 30 return true; 31 udelay(10); 32 } 33 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg); 34 return false; 35 } 36 37 /************************************************** 38 * DMA 39 **************************************************/ 40 41 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 42 { 43 u32 val; 44 int i; 45 46 if (!ring->mmio_base) 47 return; 48 49 /* Suspend DMA TX ring first. 50 * bgmac_wait_value doesn't support waiting for any of few values, so 51 * implement whole loop here. 52 */ 53 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 54 BGMAC_DMA_TX_SUSPEND); 55 for (i = 0; i < 10000 / 10; i++) { 56 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 57 val &= BGMAC_DMA_TX_STAT; 58 if (val == BGMAC_DMA_TX_STAT_DISABLED || 59 val == BGMAC_DMA_TX_STAT_IDLEWAIT || 60 val == BGMAC_DMA_TX_STAT_STOPPED) { 61 i = 0; 62 break; 63 } 64 udelay(10); 65 } 66 if (i) 67 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", 68 ring->mmio_base, val); 69 70 /* Remove SUSPEND bit */ 71 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); 72 if (!bgmac_wait_value(bgmac, 73 ring->mmio_base + BGMAC_DMA_TX_STATUS, 74 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, 75 10000)) { 76 dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", 77 ring->mmio_base); 78 udelay(300); 79 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 80 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) 81 dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n", 82 ring->mmio_base); 83 } 84 } 85 86 static void bgmac_dma_tx_enable(struct bgmac *bgmac, 87 struct bgmac_dma_ring *ring) 88 { 89 u32 ctl; 90 91 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); 92 if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) { 93 ctl &= ~BGMAC_DMA_TX_BL_MASK; 94 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; 95 96 ctl &= ~BGMAC_DMA_TX_MR_MASK; 97 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT; 98 99 ctl &= ~BGMAC_DMA_TX_PC_MASK; 100 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT; 101 102 ctl &= ~BGMAC_DMA_TX_PT_MASK; 103 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT; 104 } 105 ctl |= BGMAC_DMA_TX_ENABLE; 106 ctl |= BGMAC_DMA_TX_PARITY_DISABLE; 107 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); 108 } 109 110 static void 111 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 112 int i, int len, u32 ctl0) 113 { 114 struct bgmac_slot_info *slot; 115 struct bgmac_dma_desc *dma_desc; 116 u32 ctl1; 117 118 if (i == BGMAC_TX_RING_SLOTS - 1) 119 ctl0 |= BGMAC_DESC_CTL0_EOT; 120 121 ctl1 = len & BGMAC_DESC_CTL1_LEN; 122 123 slot = &ring->slots[i]; 124 dma_desc = &ring->cpu_base[i]; 125 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); 126 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); 127 dma_desc->ctl0 = cpu_to_le32(ctl0); 128 dma_desc->ctl1 = cpu_to_le32(ctl1); 129 } 130 131 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, 132 struct bgmac_dma_ring *ring, 133 struct sk_buff *skb) 134 { 135 struct device *dma_dev = bgmac->dma_dev; 136 struct net_device *net_dev = bgmac->net_dev; 137 int index = ring->end % BGMAC_TX_RING_SLOTS; 138 struct bgmac_slot_info *slot = &ring->slots[index]; 139 int nr_frags; 140 u32 flags; 141 int i; 142 143 if (skb->len > BGMAC_DESC_CTL1_LEN) { 144 netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len); 145 goto err_drop; 146 } 147 148 if (skb->ip_summed == CHECKSUM_PARTIAL) 149 skb_checksum_help(skb); 150 151 nr_frags = skb_shinfo(skb)->nr_frags; 152 153 /* ring->end - ring->start will return the number of valid slots, 154 * even when ring->end overflows 155 */ 156 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) { 157 netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n"); 158 netif_stop_queue(net_dev); 159 return NETDEV_TX_BUSY; 160 } 161 162 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb), 163 DMA_TO_DEVICE); 164 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 165 goto err_dma_head; 166 167 flags = BGMAC_DESC_CTL0_SOF; 168 if (!nr_frags) 169 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 170 171 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags); 172 flags = 0; 173 174 for (i = 0; i < nr_frags; i++) { 175 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 176 int len = skb_frag_size(frag); 177 178 index = (index + 1) % BGMAC_TX_RING_SLOTS; 179 slot = &ring->slots[index]; 180 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0, 181 len, DMA_TO_DEVICE); 182 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 183 goto err_dma; 184 185 if (i == nr_frags - 1) 186 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 187 188 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags); 189 } 190 191 slot->skb = skb; 192 ring->end += nr_frags + 1; 193 netdev_sent_queue(net_dev, skb->len); 194 195 wmb(); 196 197 /* Increase ring->end to point empty slot. We tell hardware the first 198 * slot it should *not* read. 199 */ 200 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, 201 ring->index_base + 202 (ring->end % BGMAC_TX_RING_SLOTS) * 203 sizeof(struct bgmac_dma_desc)); 204 205 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8) 206 netif_stop_queue(net_dev); 207 208 return NETDEV_TX_OK; 209 210 err_dma: 211 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb), 212 DMA_TO_DEVICE); 213 214 while (i-- > 0) { 215 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS; 216 struct bgmac_slot_info *slot = &ring->slots[index]; 217 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); 218 int len = ctl1 & BGMAC_DESC_CTL1_LEN; 219 220 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE); 221 } 222 223 err_dma_head: 224 netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n", 225 ring->mmio_base); 226 227 err_drop: 228 dev_kfree_skb(skb); 229 net_dev->stats.tx_dropped++; 230 net_dev->stats.tx_errors++; 231 return NETDEV_TX_OK; 232 } 233 234 /* Free transmitted packets */ 235 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 236 { 237 struct device *dma_dev = bgmac->dma_dev; 238 int empty_slot; 239 bool freed = false; 240 unsigned bytes_compl = 0, pkts_compl = 0; 241 242 /* The last slot that hardware didn't consume yet */ 243 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 244 empty_slot &= BGMAC_DMA_TX_STATDPTR; 245 empty_slot -= ring->index_base; 246 empty_slot &= BGMAC_DMA_TX_STATDPTR; 247 empty_slot /= sizeof(struct bgmac_dma_desc); 248 249 while (ring->start != ring->end) { 250 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS; 251 struct bgmac_slot_info *slot = &ring->slots[slot_idx]; 252 u32 ctl0, ctl1; 253 int len; 254 255 if (slot_idx == empty_slot) 256 break; 257 258 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0); 259 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); 260 len = ctl1 & BGMAC_DESC_CTL1_LEN; 261 if (ctl0 & BGMAC_DESC_CTL0_SOF) 262 /* Unmap no longer used buffer */ 263 dma_unmap_single(dma_dev, slot->dma_addr, len, 264 DMA_TO_DEVICE); 265 else 266 dma_unmap_page(dma_dev, slot->dma_addr, len, 267 DMA_TO_DEVICE); 268 269 if (slot->skb) { 270 bgmac->net_dev->stats.tx_bytes += slot->skb->len; 271 bgmac->net_dev->stats.tx_packets++; 272 bytes_compl += slot->skb->len; 273 pkts_compl++; 274 275 /* Free memory! :) */ 276 dev_kfree_skb(slot->skb); 277 slot->skb = NULL; 278 } 279 280 slot->dma_addr = 0; 281 ring->start++; 282 freed = true; 283 } 284 285 if (!pkts_compl) 286 return; 287 288 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); 289 290 if (netif_queue_stopped(bgmac->net_dev)) 291 netif_wake_queue(bgmac->net_dev); 292 } 293 294 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 295 { 296 if (!ring->mmio_base) 297 return; 298 299 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); 300 if (!bgmac_wait_value(bgmac, 301 ring->mmio_base + BGMAC_DMA_RX_STATUS, 302 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, 303 10000)) 304 dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n", 305 ring->mmio_base); 306 } 307 308 static void bgmac_dma_rx_enable(struct bgmac *bgmac, 309 struct bgmac_dma_ring *ring) 310 { 311 u32 ctl; 312 313 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); 314 315 /* preserve ONLY bits 16-17 from current hardware value */ 316 ctl &= BGMAC_DMA_RX_ADDREXT_MASK; 317 318 if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) { 319 ctl &= ~BGMAC_DMA_RX_BL_MASK; 320 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; 321 322 ctl &= ~BGMAC_DMA_RX_PC_MASK; 323 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT; 324 325 ctl &= ~BGMAC_DMA_RX_PT_MASK; 326 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; 327 } 328 ctl |= BGMAC_DMA_RX_ENABLE; 329 ctl |= BGMAC_DMA_RX_PARITY_DISABLE; 330 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; 331 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; 332 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); 333 } 334 335 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, 336 struct bgmac_slot_info *slot) 337 { 338 struct device *dma_dev = bgmac->dma_dev; 339 dma_addr_t dma_addr; 340 struct bgmac_rx_header *rx; 341 void *buf; 342 343 /* Alloc skb */ 344 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE); 345 if (!buf) 346 return -ENOMEM; 347 348 /* Poison - if everything goes fine, hardware will overwrite it */ 349 rx = buf + BGMAC_RX_BUF_OFFSET; 350 rx->len = cpu_to_le16(0xdead); 351 rx->flags = cpu_to_le16(0xbeef); 352 353 /* Map skb for the DMA */ 354 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET, 355 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 356 if (dma_mapping_error(dma_dev, dma_addr)) { 357 netdev_err(bgmac->net_dev, "DMA mapping error\n"); 358 put_page(virt_to_head_page(buf)); 359 return -ENOMEM; 360 } 361 362 /* Update the slot */ 363 slot->buf = buf; 364 slot->dma_addr = dma_addr; 365 366 return 0; 367 } 368 369 static void bgmac_dma_rx_update_index(struct bgmac *bgmac, 370 struct bgmac_dma_ring *ring) 371 { 372 dma_wmb(); 373 374 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, 375 ring->index_base + 376 ring->end * sizeof(struct bgmac_dma_desc)); 377 } 378 379 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, 380 struct bgmac_dma_ring *ring, int desc_idx) 381 { 382 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; 383 u32 ctl0 = 0, ctl1 = 0; 384 385 if (desc_idx == BGMAC_RX_RING_SLOTS - 1) 386 ctl0 |= BGMAC_DESC_CTL0_EOT; 387 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; 388 /* Is there any BGMAC device that requires extension? */ 389 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & 390 * B43_DMA64_DCTL1_ADDREXT_MASK; 391 */ 392 393 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr)); 394 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); 395 dma_desc->ctl0 = cpu_to_le32(ctl0); 396 dma_desc->ctl1 = cpu_to_le32(ctl1); 397 398 ring->end = desc_idx; 399 } 400 401 static void bgmac_dma_rx_poison_buf(struct device *dma_dev, 402 struct bgmac_slot_info *slot) 403 { 404 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 405 406 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, 407 DMA_FROM_DEVICE); 408 rx->len = cpu_to_le16(0xdead); 409 rx->flags = cpu_to_le16(0xbeef); 410 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, 411 DMA_FROM_DEVICE); 412 } 413 414 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 415 int weight) 416 { 417 u32 end_slot; 418 int handled = 0; 419 420 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); 421 end_slot &= BGMAC_DMA_RX_STATDPTR; 422 end_slot -= ring->index_base; 423 end_slot &= BGMAC_DMA_RX_STATDPTR; 424 end_slot /= sizeof(struct bgmac_dma_desc); 425 426 while (ring->start != end_slot) { 427 struct device *dma_dev = bgmac->dma_dev; 428 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 429 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 430 struct sk_buff *skb; 431 void *buf = slot->buf; 432 dma_addr_t dma_addr = slot->dma_addr; 433 u16 len, flags; 434 435 do { 436 /* Prepare new skb as replacement */ 437 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) { 438 bgmac_dma_rx_poison_buf(dma_dev, slot); 439 break; 440 } 441 442 /* Unmap buffer to make it accessible to the CPU */ 443 dma_unmap_single(dma_dev, dma_addr, 444 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 445 446 /* Get info from the header */ 447 len = le16_to_cpu(rx->len); 448 flags = le16_to_cpu(rx->flags); 449 450 /* Check for poison and drop or pass the packet */ 451 if (len == 0xdead && flags == 0xbeef) { 452 netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n", 453 ring->start); 454 put_page(virt_to_head_page(buf)); 455 bgmac->net_dev->stats.rx_errors++; 456 break; 457 } 458 459 if (len > BGMAC_RX_ALLOC_SIZE) { 460 netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n", 461 ring->start); 462 put_page(virt_to_head_page(buf)); 463 bgmac->net_dev->stats.rx_length_errors++; 464 bgmac->net_dev->stats.rx_errors++; 465 break; 466 } 467 468 /* Omit CRC. */ 469 len -= ETH_FCS_LEN; 470 471 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); 472 if (unlikely(!skb)) { 473 netdev_err(bgmac->net_dev, "build_skb failed\n"); 474 put_page(virt_to_head_page(buf)); 475 bgmac->net_dev->stats.rx_errors++; 476 break; 477 } 478 skb_put(skb, BGMAC_RX_FRAME_OFFSET + 479 BGMAC_RX_BUF_OFFSET + len); 480 skb_pull(skb, BGMAC_RX_FRAME_OFFSET + 481 BGMAC_RX_BUF_OFFSET); 482 483 skb_checksum_none_assert(skb); 484 skb->protocol = eth_type_trans(skb, bgmac->net_dev); 485 bgmac->net_dev->stats.rx_bytes += len; 486 bgmac->net_dev->stats.rx_packets++; 487 napi_gro_receive(&bgmac->napi, skb); 488 handled++; 489 } while (0); 490 491 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); 492 493 if (++ring->start >= BGMAC_RX_RING_SLOTS) 494 ring->start = 0; 495 496 if (handled >= weight) /* Should never be greater */ 497 break; 498 } 499 500 bgmac_dma_rx_update_index(bgmac, ring); 501 502 return handled; 503 } 504 505 /* Does ring support unaligned addressing? */ 506 static bool bgmac_dma_unaligned(struct bgmac *bgmac, 507 struct bgmac_dma_ring *ring, 508 enum bgmac_dma_ring_type ring_type) 509 { 510 switch (ring_type) { 511 case BGMAC_DMA_RING_TX: 512 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 513 0xff0); 514 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) 515 return true; 516 break; 517 case BGMAC_DMA_RING_RX: 518 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 519 0xff0); 520 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) 521 return true; 522 break; 523 } 524 return false; 525 } 526 527 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac, 528 struct bgmac_dma_ring *ring) 529 { 530 struct device *dma_dev = bgmac->dma_dev; 531 struct bgmac_dma_desc *dma_desc = ring->cpu_base; 532 struct bgmac_slot_info *slot; 533 int i; 534 535 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) { 536 u32 ctl1 = le32_to_cpu(dma_desc[i].ctl1); 537 unsigned int len = ctl1 & BGMAC_DESC_CTL1_LEN; 538 539 slot = &ring->slots[i]; 540 dev_kfree_skb(slot->skb); 541 542 if (!slot->dma_addr) 543 continue; 544 545 if (slot->skb) 546 dma_unmap_single(dma_dev, slot->dma_addr, 547 len, DMA_TO_DEVICE); 548 else 549 dma_unmap_page(dma_dev, slot->dma_addr, 550 len, DMA_TO_DEVICE); 551 } 552 } 553 554 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac, 555 struct bgmac_dma_ring *ring) 556 { 557 struct device *dma_dev = bgmac->dma_dev; 558 struct bgmac_slot_info *slot; 559 int i; 560 561 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) { 562 slot = &ring->slots[i]; 563 if (!slot->dma_addr) 564 continue; 565 566 dma_unmap_single(dma_dev, slot->dma_addr, 567 BGMAC_RX_BUF_SIZE, 568 DMA_FROM_DEVICE); 569 put_page(virt_to_head_page(slot->buf)); 570 slot->dma_addr = 0; 571 } 572 } 573 574 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, 575 struct bgmac_dma_ring *ring, 576 int num_slots) 577 { 578 struct device *dma_dev = bgmac->dma_dev; 579 int size; 580 581 if (!ring->cpu_base) 582 return; 583 584 /* Free ring of descriptors */ 585 size = num_slots * sizeof(struct bgmac_dma_desc); 586 dma_free_coherent(dma_dev, size, ring->cpu_base, 587 ring->dma_base); 588 } 589 590 static void bgmac_dma_cleanup(struct bgmac *bgmac) 591 { 592 int i; 593 594 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 595 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); 596 597 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 598 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); 599 } 600 601 static void bgmac_dma_free(struct bgmac *bgmac) 602 { 603 int i; 604 605 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 606 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i], 607 BGMAC_TX_RING_SLOTS); 608 609 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 610 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i], 611 BGMAC_RX_RING_SLOTS); 612 } 613 614 static int bgmac_dma_alloc(struct bgmac *bgmac) 615 { 616 struct device *dma_dev = bgmac->dma_dev; 617 struct bgmac_dma_ring *ring; 618 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, 619 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, }; 620 int size; /* ring size: different for Tx and Rx */ 621 int err; 622 int i; 623 624 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); 625 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); 626 627 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) { 628 if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) { 629 dev_err(bgmac->dev, "Core does not report 64-bit DMA\n"); 630 return -ENOTSUPP; 631 } 632 } 633 634 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 635 ring = &bgmac->tx_ring[i]; 636 ring->mmio_base = ring_base[i]; 637 638 /* Alloc ring of descriptors */ 639 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc); 640 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 641 &ring->dma_base, 642 GFP_KERNEL); 643 if (!ring->cpu_base) { 644 dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n", 645 ring->mmio_base); 646 goto err_dma_free; 647 } 648 649 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 650 BGMAC_DMA_RING_TX); 651 if (ring->unaligned) 652 ring->index_base = lower_32_bits(ring->dma_base); 653 else 654 ring->index_base = 0; 655 656 /* No need to alloc TX slots yet */ 657 } 658 659 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 660 ring = &bgmac->rx_ring[i]; 661 ring->mmio_base = ring_base[i]; 662 663 /* Alloc ring of descriptors */ 664 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc); 665 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 666 &ring->dma_base, 667 GFP_KERNEL); 668 if (!ring->cpu_base) { 669 dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n", 670 ring->mmio_base); 671 err = -ENOMEM; 672 goto err_dma_free; 673 } 674 675 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 676 BGMAC_DMA_RING_RX); 677 if (ring->unaligned) 678 ring->index_base = lower_32_bits(ring->dma_base); 679 else 680 ring->index_base = 0; 681 } 682 683 return 0; 684 685 err_dma_free: 686 bgmac_dma_free(bgmac); 687 return -ENOMEM; 688 } 689 690 static int bgmac_dma_init(struct bgmac *bgmac) 691 { 692 struct bgmac_dma_ring *ring; 693 int i, err; 694 695 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 696 ring = &bgmac->tx_ring[i]; 697 698 if (!ring->unaligned) 699 bgmac_dma_tx_enable(bgmac, ring); 700 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 701 lower_32_bits(ring->dma_base)); 702 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, 703 upper_32_bits(ring->dma_base)); 704 if (ring->unaligned) 705 bgmac_dma_tx_enable(bgmac, ring); 706 707 ring->start = 0; 708 ring->end = 0; /* Points the slot that should *not* be read */ 709 } 710 711 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 712 int j; 713 714 ring = &bgmac->rx_ring[i]; 715 716 if (!ring->unaligned) 717 bgmac_dma_rx_enable(bgmac, ring); 718 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 719 lower_32_bits(ring->dma_base)); 720 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, 721 upper_32_bits(ring->dma_base)); 722 if (ring->unaligned) 723 bgmac_dma_rx_enable(bgmac, ring); 724 725 ring->start = 0; 726 ring->end = 0; 727 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) { 728 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); 729 if (err) 730 goto error; 731 732 bgmac_dma_rx_setup_desc(bgmac, ring, j); 733 } 734 735 bgmac_dma_rx_update_index(bgmac, ring); 736 } 737 738 return 0; 739 740 error: 741 bgmac_dma_cleanup(bgmac); 742 return err; 743 } 744 745 746 /************************************************** 747 * Chip ops 748 **************************************************/ 749 750 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is 751 * nothing to change? Try if after stabilizng driver. 752 */ 753 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, 754 bool force) 755 { 756 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 757 u32 new_val = (cmdcfg & mask) | set; 758 u32 cmdcfg_sr; 759 760 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) 761 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; 762 else 763 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; 764 765 bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr); 766 udelay(2); 767 768 if (new_val != cmdcfg || force) 769 bgmac_write(bgmac, BGMAC_CMDCFG, new_val); 770 771 bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr); 772 udelay(2); 773 } 774 775 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr) 776 { 777 u32 tmp; 778 779 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 780 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); 781 tmp = (addr[4] << 8) | addr[5]; 782 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); 783 } 784 785 static void bgmac_set_rx_mode(struct net_device *net_dev) 786 { 787 struct bgmac *bgmac = netdev_priv(net_dev); 788 789 if (net_dev->flags & IFF_PROMISC) 790 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true); 791 else 792 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true); 793 } 794 795 #if 0 /* We don't use that regs yet */ 796 static void bgmac_chip_stats_update(struct bgmac *bgmac) 797 { 798 int i; 799 800 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) { 801 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 802 bgmac->mib_tx_regs[i] = 803 bgmac_read(bgmac, 804 BGMAC_TX_GOOD_OCTETS + (i * 4)); 805 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 806 bgmac->mib_rx_regs[i] = 807 bgmac_read(bgmac, 808 BGMAC_RX_GOOD_OCTETS + (i * 4)); 809 } 810 811 /* TODO: what else? how to handle BCM4706? Specs are needed */ 812 } 813 #endif 814 815 static void bgmac_clear_mib(struct bgmac *bgmac) 816 { 817 int i; 818 819 if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB) 820 return; 821 822 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); 823 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 824 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); 825 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 826 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); 827 } 828 829 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ 830 static void bgmac_mac_speed(struct bgmac *bgmac) 831 { 832 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); 833 u32 set = 0; 834 835 switch (bgmac->mac_speed) { 836 case SPEED_10: 837 set |= BGMAC_CMDCFG_ES_10; 838 break; 839 case SPEED_100: 840 set |= BGMAC_CMDCFG_ES_100; 841 break; 842 case SPEED_1000: 843 set |= BGMAC_CMDCFG_ES_1000; 844 break; 845 case SPEED_2500: 846 set |= BGMAC_CMDCFG_ES_2500; 847 break; 848 default: 849 dev_err(bgmac->dev, "Unsupported speed: %d\n", 850 bgmac->mac_speed); 851 } 852 853 if (bgmac->mac_duplex == DUPLEX_HALF) 854 set |= BGMAC_CMDCFG_HD; 855 856 bgmac_cmdcfg_maskset(bgmac, mask, set, true); 857 } 858 859 static void bgmac_miiconfig(struct bgmac *bgmac) 860 { 861 if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) { 862 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) { 863 bgmac_idm_write(bgmac, BCMA_IOCTL, 864 bgmac_idm_read(bgmac, BCMA_IOCTL) | 865 0x40 | BGMAC_BCMA_IOCTL_SW_CLKEN); 866 } 867 bgmac->mac_speed = SPEED_2500; 868 bgmac->mac_duplex = DUPLEX_FULL; 869 bgmac_mac_speed(bgmac); 870 } else { 871 u8 imode; 872 873 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & 874 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; 875 if (imode == 0 || imode == 1) { 876 bgmac->mac_speed = SPEED_100; 877 bgmac->mac_duplex = DUPLEX_FULL; 878 bgmac_mac_speed(bgmac); 879 } 880 } 881 } 882 883 static void bgmac_chip_reset_idm_config(struct bgmac *bgmac) 884 { 885 u32 iost; 886 887 iost = bgmac_idm_read(bgmac, BCMA_IOST); 888 if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED) 889 iost &= ~BGMAC_BCMA_IOST_ATTACHED; 890 891 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */ 892 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) { 893 u32 flags = 0; 894 895 if (iost & BGMAC_BCMA_IOST_ATTACHED) { 896 flags = BGMAC_BCMA_IOCTL_SW_CLKEN; 897 if (!bgmac->has_robosw) 898 flags |= BGMAC_BCMA_IOCTL_SW_RESET; 899 } 900 bgmac_clk_enable(bgmac, flags); 901 } 902 903 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) 904 bgmac_idm_write(bgmac, BCMA_IOCTL, 905 bgmac_idm_read(bgmac, BCMA_IOCTL) & 906 ~BGMAC_BCMA_IOCTL_SW_RESET); 907 } 908 909 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ 910 static void bgmac_chip_reset(struct bgmac *bgmac) 911 { 912 u32 cmdcfg_sr; 913 int i; 914 915 if (bgmac_clk_enabled(bgmac)) { 916 if (!bgmac->stats_grabbed) { 917 /* bgmac_chip_stats_update(bgmac); */ 918 bgmac->stats_grabbed = true; 919 } 920 921 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 922 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); 923 924 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 925 udelay(1); 926 927 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 928 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); 929 930 /* TODO: Clear software multicast filter list */ 931 } 932 933 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) 934 bgmac_chip_reset_idm_config(bgmac); 935 936 /* Request Misc PLL for corerev > 2 */ 937 if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) { 938 bgmac_set(bgmac, BCMA_CLKCTLST, 939 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); 940 bgmac_wait_value(bgmac, BCMA_CLKCTLST, 941 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 942 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 943 1000); 944 } 945 946 if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) { 947 u8 et_swtype = 0; 948 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | 949 BGMAC_CHIPCTL_1_IF_TYPE_MII; 950 char buf[4]; 951 952 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 953 if (kstrtou8(buf, 0, &et_swtype)) 954 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n", 955 buf); 956 et_swtype &= 0x0f; 957 et_swtype <<= 4; 958 sw_type = et_swtype; 959 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) { 960 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RMII | 961 BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; 962 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) { 963 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | 964 BGMAC_CHIPCTL_1_SW_TYPE_RGMII; 965 } 966 bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | 967 BGMAC_CHIPCTL_1_SW_TYPE_MASK), 968 sw_type); 969 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE) { 970 u32 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_MII | 971 BGMAC_CHIPCTL_4_SW_TYPE_EPHY; 972 u8 et_swtype = 0; 973 char buf[4]; 974 975 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 976 if (kstrtou8(buf, 0, &et_swtype)) 977 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n", 978 buf); 979 sw_type = (et_swtype & 0x0f) << 12; 980 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII) { 981 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_RGMII | 982 BGMAC_CHIPCTL_4_SW_TYPE_RGMII; 983 } 984 bgmac_cco_ctl_maskset(bgmac, 4, ~(BGMAC_CHIPCTL_4_IF_TYPE_MASK | 985 BGMAC_CHIPCTL_4_SW_TYPE_MASK), 986 sw_type); 987 } else if (bgmac->feature_flags & BGMAC_FEAT_CC7_IF_TYPE_RGMII) { 988 bgmac_cco_ctl_maskset(bgmac, 7, ~BGMAC_CHIPCTL_7_IF_TYPE_MASK, 989 BGMAC_CHIPCTL_7_IF_TYPE_RGMII); 990 } 991 992 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset 993 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine 994 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to 995 * be keps until taking MAC out of the reset. 996 */ 997 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) 998 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; 999 else 1000 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; 1001 1002 bgmac_cmdcfg_maskset(bgmac, 1003 ~(BGMAC_CMDCFG_TE | 1004 BGMAC_CMDCFG_RE | 1005 BGMAC_CMDCFG_RPI | 1006 BGMAC_CMDCFG_TAI | 1007 BGMAC_CMDCFG_HD | 1008 BGMAC_CMDCFG_ML | 1009 BGMAC_CMDCFG_CFE | 1010 BGMAC_CMDCFG_RL | 1011 BGMAC_CMDCFG_RED | 1012 BGMAC_CMDCFG_PE | 1013 BGMAC_CMDCFG_TPI | 1014 BGMAC_CMDCFG_PAD_EN | 1015 BGMAC_CMDCFG_PF), 1016 BGMAC_CMDCFG_PROM | 1017 BGMAC_CMDCFG_NLC | 1018 BGMAC_CMDCFG_CFE | 1019 cmdcfg_sr, 1020 false); 1021 bgmac->mac_speed = SPEED_UNKNOWN; 1022 bgmac->mac_duplex = DUPLEX_UNKNOWN; 1023 1024 bgmac_clear_mib(bgmac); 1025 if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL) 1026 bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0, 1027 BCMA_GMAC_CMN_PC_MTE); 1028 else 1029 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); 1030 bgmac_miiconfig(bgmac); 1031 if (bgmac->mii_bus) 1032 bgmac->mii_bus->reset(bgmac->mii_bus); 1033 1034 netdev_reset_queue(bgmac->net_dev); 1035 } 1036 1037 static void bgmac_chip_intrs_on(struct bgmac *bgmac) 1038 { 1039 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); 1040 } 1041 1042 static void bgmac_chip_intrs_off(struct bgmac *bgmac) 1043 { 1044 bgmac_write(bgmac, BGMAC_INT_MASK, 0); 1045 bgmac_read(bgmac, BGMAC_INT_MASK); 1046 } 1047 1048 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ 1049 static void bgmac_enable(struct bgmac *bgmac) 1050 { 1051 u32 cmdcfg_sr; 1052 u32 cmdcfg; 1053 u32 mode; 1054 1055 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) 1056 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; 1057 else 1058 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; 1059 1060 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 1061 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), 1062 cmdcfg_sr, true); 1063 udelay(2); 1064 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; 1065 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); 1066 1067 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 1068 BGMAC_DS_MM_SHIFT; 1069 if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0) 1070 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 1071 if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) && mode == 2) 1072 bgmac_cco_ctl_maskset(bgmac, 1, ~0, 1073 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); 1074 1075 if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 | 1076 BGMAC_FEAT_FLW_CTRL2)) { 1077 u32 fl_ctl; 1078 1079 if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1) 1080 fl_ctl = 0x2300e1; 1081 else 1082 fl_ctl = 0x03cb04cb; 1083 1084 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); 1085 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); 1086 } 1087 1088 if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) { 1089 u32 rxq_ctl; 1090 u16 bp_clk; 1091 u8 mdp; 1092 1093 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); 1094 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; 1095 bp_clk = bgmac_get_bus_clock(bgmac) / 1000000; 1096 mdp = (bp_clk * 128 / 1000) - 3; 1097 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); 1098 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); 1099 } 1100 } 1101 1102 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ 1103 static void bgmac_chip_init(struct bgmac *bgmac) 1104 { 1105 /* Clear any erroneously pending interrupts */ 1106 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); 1107 1108 /* 1 interrupt per received frame */ 1109 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); 1110 1111 /* Enable 802.3x tx flow control (honor received PAUSE frames) */ 1112 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); 1113 1114 bgmac_set_rx_mode(bgmac->net_dev); 1115 1116 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr); 1117 1118 if (bgmac->loopback) 1119 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1120 else 1121 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false); 1122 1123 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); 1124 1125 bgmac_chip_intrs_on(bgmac); 1126 1127 bgmac_enable(bgmac); 1128 } 1129 1130 static irqreturn_t bgmac_interrupt(int irq, void *dev_id) 1131 { 1132 struct bgmac *bgmac = netdev_priv(dev_id); 1133 1134 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); 1135 int_status &= bgmac->int_mask; 1136 1137 if (!int_status) 1138 return IRQ_NONE; 1139 1140 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX); 1141 if (int_status) 1142 dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status); 1143 1144 /* Disable new interrupts until handling existing ones */ 1145 bgmac_chip_intrs_off(bgmac); 1146 1147 napi_schedule(&bgmac->napi); 1148 1149 return IRQ_HANDLED; 1150 } 1151 1152 static int bgmac_poll(struct napi_struct *napi, int weight) 1153 { 1154 struct bgmac *bgmac = container_of(napi, struct bgmac, napi); 1155 int handled = 0; 1156 1157 /* Ack */ 1158 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); 1159 1160 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]); 1161 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight); 1162 1163 /* Poll again if more events arrived in the meantime */ 1164 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX)) 1165 return weight; 1166 1167 if (handled < weight) { 1168 napi_complete_done(napi, handled); 1169 bgmac_chip_intrs_on(bgmac); 1170 } 1171 1172 return handled; 1173 } 1174 1175 /************************************************** 1176 * net_device_ops 1177 **************************************************/ 1178 1179 static int bgmac_open(struct net_device *net_dev) 1180 { 1181 struct bgmac *bgmac = netdev_priv(net_dev); 1182 int err = 0; 1183 1184 bgmac_chip_reset(bgmac); 1185 1186 err = bgmac_dma_init(bgmac); 1187 if (err) 1188 return err; 1189 1190 /* Specs say about reclaiming rings here, but we do that in DMA init */ 1191 bgmac_chip_init(bgmac); 1192 1193 err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED, 1194 net_dev->name, net_dev); 1195 if (err < 0) { 1196 dev_err(bgmac->dev, "IRQ request error: %d!\n", err); 1197 bgmac_dma_cleanup(bgmac); 1198 return err; 1199 } 1200 napi_enable(&bgmac->napi); 1201 1202 phy_start(net_dev->phydev); 1203 1204 netif_start_queue(net_dev); 1205 1206 return 0; 1207 } 1208 1209 static int bgmac_stop(struct net_device *net_dev) 1210 { 1211 struct bgmac *bgmac = netdev_priv(net_dev); 1212 1213 netif_carrier_off(net_dev); 1214 1215 phy_stop(net_dev->phydev); 1216 1217 napi_disable(&bgmac->napi); 1218 bgmac_chip_intrs_off(bgmac); 1219 free_irq(bgmac->irq, net_dev); 1220 1221 bgmac_chip_reset(bgmac); 1222 bgmac_dma_cleanup(bgmac); 1223 1224 return 0; 1225 } 1226 1227 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, 1228 struct net_device *net_dev) 1229 { 1230 struct bgmac *bgmac = netdev_priv(net_dev); 1231 struct bgmac_dma_ring *ring; 1232 1233 /* No QOS support yet */ 1234 ring = &bgmac->tx_ring[0]; 1235 return bgmac_dma_tx_add(bgmac, ring, skb); 1236 } 1237 1238 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr) 1239 { 1240 struct bgmac *bgmac = netdev_priv(net_dev); 1241 struct sockaddr *sa = addr; 1242 int ret; 1243 1244 ret = eth_prepare_mac_addr_change(net_dev, addr); 1245 if (ret < 0) 1246 return ret; 1247 1248 ether_addr_copy(net_dev->dev_addr, sa->sa_data); 1249 bgmac_write_mac_address(bgmac, net_dev->dev_addr); 1250 1251 eth_commit_mac_addr_change(net_dev, addr); 1252 return 0; 1253 } 1254 1255 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1256 { 1257 if (!netif_running(net_dev)) 1258 return -EINVAL; 1259 1260 return phy_mii_ioctl(net_dev->phydev, ifr, cmd); 1261 } 1262 1263 static const struct net_device_ops bgmac_netdev_ops = { 1264 .ndo_open = bgmac_open, 1265 .ndo_stop = bgmac_stop, 1266 .ndo_start_xmit = bgmac_start_xmit, 1267 .ndo_set_rx_mode = bgmac_set_rx_mode, 1268 .ndo_set_mac_address = bgmac_set_mac_address, 1269 .ndo_validate_addr = eth_validate_addr, 1270 .ndo_do_ioctl = bgmac_ioctl, 1271 }; 1272 1273 /************************************************** 1274 * ethtool_ops 1275 **************************************************/ 1276 1277 struct bgmac_stat { 1278 u8 size; 1279 u32 offset; 1280 const char *name; 1281 }; 1282 1283 static struct bgmac_stat bgmac_get_strings_stats[] = { 1284 { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" }, 1285 { 4, BGMAC_TX_GOOD_PKTS, "tx_good" }, 1286 { 8, BGMAC_TX_OCTETS, "tx_octets" }, 1287 { 4, BGMAC_TX_PKTS, "tx_pkts" }, 1288 { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" }, 1289 { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" }, 1290 { 4, BGMAC_TX_LEN_64, "tx_64" }, 1291 { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" }, 1292 { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" }, 1293 { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" }, 1294 { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" }, 1295 { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" }, 1296 { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" }, 1297 { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" }, 1298 { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" }, 1299 { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" }, 1300 { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" }, 1301 { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" }, 1302 { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" }, 1303 { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" }, 1304 { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" }, 1305 { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" }, 1306 { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" }, 1307 { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" }, 1308 { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" }, 1309 { 4, BGMAC_TX_DEFERED, "tx_defered" }, 1310 { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" }, 1311 { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" }, 1312 { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" }, 1313 { 4, BGMAC_TX_Q0_PKTS, "tx_q0" }, 1314 { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" }, 1315 { 4, BGMAC_TX_Q1_PKTS, "tx_q1" }, 1316 { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" }, 1317 { 4, BGMAC_TX_Q2_PKTS, "tx_q2" }, 1318 { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" }, 1319 { 4, BGMAC_TX_Q3_PKTS, "tx_q3" }, 1320 { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" }, 1321 { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" }, 1322 { 4, BGMAC_RX_GOOD_PKTS, "rx_good" }, 1323 { 8, BGMAC_RX_OCTETS, "rx_octets" }, 1324 { 4, BGMAC_RX_PKTS, "rx_pkts" }, 1325 { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" }, 1326 { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" }, 1327 { 4, BGMAC_RX_LEN_64, "rx_64" }, 1328 { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" }, 1329 { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" }, 1330 { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" }, 1331 { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" }, 1332 { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" }, 1333 { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" }, 1334 { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" }, 1335 { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" }, 1336 { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" }, 1337 { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" }, 1338 { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" }, 1339 { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" }, 1340 { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" }, 1341 { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" }, 1342 { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" }, 1343 { 4, BGMAC_RX_CRC_ERRS, "rx_crc" }, 1344 { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" }, 1345 { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" }, 1346 { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" }, 1347 { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" }, 1348 { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" }, 1349 { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" }, 1350 }; 1351 1352 #define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats) 1353 1354 static int bgmac_get_sset_count(struct net_device *dev, int string_set) 1355 { 1356 switch (string_set) { 1357 case ETH_SS_STATS: 1358 return BGMAC_STATS_LEN; 1359 } 1360 1361 return -EOPNOTSUPP; 1362 } 1363 1364 static void bgmac_get_strings(struct net_device *dev, u32 stringset, 1365 u8 *data) 1366 { 1367 int i; 1368 1369 if (stringset != ETH_SS_STATS) 1370 return; 1371 1372 for (i = 0; i < BGMAC_STATS_LEN; i++) 1373 strlcpy(data + i * ETH_GSTRING_LEN, 1374 bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN); 1375 } 1376 1377 static void bgmac_get_ethtool_stats(struct net_device *dev, 1378 struct ethtool_stats *ss, uint64_t *data) 1379 { 1380 struct bgmac *bgmac = netdev_priv(dev); 1381 const struct bgmac_stat *s; 1382 unsigned int i; 1383 u64 val; 1384 1385 if (!netif_running(dev)) 1386 return; 1387 1388 for (i = 0; i < BGMAC_STATS_LEN; i++) { 1389 s = &bgmac_get_strings_stats[i]; 1390 val = 0; 1391 if (s->size == 8) 1392 val = (u64)bgmac_read(bgmac, s->offset + 4) << 32; 1393 val |= bgmac_read(bgmac, s->offset); 1394 data[i] = val; 1395 } 1396 } 1397 1398 static void bgmac_get_drvinfo(struct net_device *net_dev, 1399 struct ethtool_drvinfo *info) 1400 { 1401 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1402 strlcpy(info->bus_info, "AXI", sizeof(info->bus_info)); 1403 } 1404 1405 static const struct ethtool_ops bgmac_ethtool_ops = { 1406 .get_strings = bgmac_get_strings, 1407 .get_sset_count = bgmac_get_sset_count, 1408 .get_ethtool_stats = bgmac_get_ethtool_stats, 1409 .get_drvinfo = bgmac_get_drvinfo, 1410 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1411 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1412 }; 1413 1414 /************************************************** 1415 * MII 1416 **************************************************/ 1417 1418 void bgmac_adjust_link(struct net_device *net_dev) 1419 { 1420 struct bgmac *bgmac = netdev_priv(net_dev); 1421 struct phy_device *phy_dev = net_dev->phydev; 1422 bool update = false; 1423 1424 if (phy_dev->link) { 1425 if (phy_dev->speed != bgmac->mac_speed) { 1426 bgmac->mac_speed = phy_dev->speed; 1427 update = true; 1428 } 1429 1430 if (phy_dev->duplex != bgmac->mac_duplex) { 1431 bgmac->mac_duplex = phy_dev->duplex; 1432 update = true; 1433 } 1434 } 1435 1436 if (update) { 1437 bgmac_mac_speed(bgmac); 1438 phy_print_status(phy_dev); 1439 } 1440 } 1441 EXPORT_SYMBOL_GPL(bgmac_adjust_link); 1442 1443 int bgmac_phy_connect_direct(struct bgmac *bgmac) 1444 { 1445 struct fixed_phy_status fphy_status = { 1446 .link = 1, 1447 .speed = SPEED_1000, 1448 .duplex = DUPLEX_FULL, 1449 }; 1450 struct phy_device *phy_dev; 1451 int err; 1452 1453 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); 1454 if (!phy_dev || IS_ERR(phy_dev)) { 1455 dev_err(bgmac->dev, "Failed to register fixed PHY device\n"); 1456 return -ENODEV; 1457 } 1458 1459 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link, 1460 PHY_INTERFACE_MODE_MII); 1461 if (err) { 1462 dev_err(bgmac->dev, "Connecting PHY failed\n"); 1463 return err; 1464 } 1465 1466 return err; 1467 } 1468 EXPORT_SYMBOL_GPL(bgmac_phy_connect_direct); 1469 1470 struct bgmac *bgmac_alloc(struct device *dev) 1471 { 1472 struct net_device *net_dev; 1473 struct bgmac *bgmac; 1474 1475 /* Allocation and references */ 1476 net_dev = devm_alloc_etherdev(dev, sizeof(*bgmac)); 1477 if (!net_dev) 1478 return NULL; 1479 1480 net_dev->netdev_ops = &bgmac_netdev_ops; 1481 net_dev->ethtool_ops = &bgmac_ethtool_ops; 1482 1483 bgmac = netdev_priv(net_dev); 1484 bgmac->dev = dev; 1485 bgmac->net_dev = net_dev; 1486 1487 return bgmac; 1488 } 1489 EXPORT_SYMBOL_GPL(bgmac_alloc); 1490 1491 int bgmac_enet_probe(struct bgmac *bgmac) 1492 { 1493 struct net_device *net_dev = bgmac->net_dev; 1494 int err; 1495 1496 bgmac_chip_intrs_off(bgmac); 1497 1498 net_dev->irq = bgmac->irq; 1499 SET_NETDEV_DEV(net_dev, bgmac->dev); 1500 dev_set_drvdata(bgmac->dev, bgmac); 1501 1502 if (!is_valid_ether_addr(net_dev->dev_addr)) { 1503 dev_err(bgmac->dev, "Invalid MAC addr: %pM\n", 1504 net_dev->dev_addr); 1505 eth_hw_addr_random(net_dev); 1506 dev_warn(bgmac->dev, "Using random MAC: %pM\n", 1507 net_dev->dev_addr); 1508 } 1509 1510 /* This (reset &) enable is not preset in specs or reference driver but 1511 * Broadcom does it in arch PCI code when enabling fake PCI device. 1512 */ 1513 bgmac_clk_enable(bgmac, 0); 1514 1515 /* This seems to be fixing IRQ by assigning OOB #6 to the core */ 1516 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) { 1517 if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6) 1518 bgmac_idm_write(bgmac, BCMA_OOB_SEL_OUT_A30, 0x86); 1519 } 1520 1521 bgmac_chip_reset(bgmac); 1522 1523 err = bgmac_dma_alloc(bgmac); 1524 if (err) { 1525 dev_err(bgmac->dev, "Unable to alloc memory for DMA\n"); 1526 goto err_out; 1527 } 1528 1529 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; 1530 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0) 1531 bgmac->int_mask &= ~BGMAC_IS_TX_MASK; 1532 1533 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); 1534 1535 err = bgmac_phy_connect(bgmac); 1536 if (err) { 1537 dev_err(bgmac->dev, "Cannot connect to phy\n"); 1538 goto err_dma_free; 1539 } 1540 1541 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1542 net_dev->hw_features = net_dev->features; 1543 net_dev->vlan_features = net_dev->features; 1544 1545 err = register_netdev(bgmac->net_dev); 1546 if (err) { 1547 dev_err(bgmac->dev, "Cannot register net device\n"); 1548 goto err_phy_disconnect; 1549 } 1550 1551 netif_carrier_off(net_dev); 1552 1553 return 0; 1554 1555 err_phy_disconnect: 1556 phy_disconnect(net_dev->phydev); 1557 err_dma_free: 1558 bgmac_dma_free(bgmac); 1559 err_out: 1560 1561 return err; 1562 } 1563 EXPORT_SYMBOL_GPL(bgmac_enet_probe); 1564 1565 void bgmac_enet_remove(struct bgmac *bgmac) 1566 { 1567 unregister_netdev(bgmac->net_dev); 1568 phy_disconnect(bgmac->net_dev->phydev); 1569 netif_napi_del(&bgmac->napi); 1570 bgmac_dma_free(bgmac); 1571 free_netdev(bgmac->net_dev); 1572 } 1573 EXPORT_SYMBOL_GPL(bgmac_enet_remove); 1574 1575 int bgmac_enet_suspend(struct bgmac *bgmac) 1576 { 1577 if (!netif_running(bgmac->net_dev)) 1578 return 0; 1579 1580 phy_stop(bgmac->net_dev->phydev); 1581 1582 netif_stop_queue(bgmac->net_dev); 1583 1584 napi_disable(&bgmac->napi); 1585 1586 netif_tx_lock(bgmac->net_dev); 1587 netif_device_detach(bgmac->net_dev); 1588 netif_tx_unlock(bgmac->net_dev); 1589 1590 bgmac_chip_intrs_off(bgmac); 1591 bgmac_chip_reset(bgmac); 1592 bgmac_dma_cleanup(bgmac); 1593 1594 return 0; 1595 } 1596 EXPORT_SYMBOL_GPL(bgmac_enet_suspend); 1597 1598 int bgmac_enet_resume(struct bgmac *bgmac) 1599 { 1600 int rc; 1601 1602 if (!netif_running(bgmac->net_dev)) 1603 return 0; 1604 1605 rc = bgmac_dma_init(bgmac); 1606 if (rc) 1607 return rc; 1608 1609 bgmac_chip_init(bgmac); 1610 1611 napi_enable(&bgmac->napi); 1612 1613 netif_tx_lock(bgmac->net_dev); 1614 netif_device_attach(bgmac->net_dev); 1615 netif_tx_unlock(bgmac->net_dev); 1616 1617 netif_start_queue(bgmac->net_dev); 1618 1619 phy_start(bgmac->net_dev->phydev); 1620 1621 return 0; 1622 } 1623 EXPORT_SYMBOL_GPL(bgmac_enet_resume); 1624 1625 MODULE_AUTHOR("Rafał Miłecki"); 1626 MODULE_LICENSE("GPL"); 1627