1 /* 2 * Driver for (BCM4706)? GBit MAC core on BCMA bus. 3 * 4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> 5 * 6 * Licensed under the GNU/GPL. See COPYING for details. 7 */ 8 9 #include "bgmac.h" 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/phy.h> 17 #include <linux/phy_fixed.h> 18 #include <linux/interrupt.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/bcm47xx_nvram.h> 21 22 static const struct bcma_device_id bgmac_bcma_tbl[] = { 23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 24 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 25 {}, 26 }; 27 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl); 28 29 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask, 30 u32 value, int timeout) 31 { 32 u32 val; 33 int i; 34 35 for (i = 0; i < timeout / 10; i++) { 36 val = bcma_read32(core, reg); 37 if ((val & mask) == value) 38 return true; 39 udelay(10); 40 } 41 pr_err("Timeout waiting for reg 0x%X\n", reg); 42 return false; 43 } 44 45 /************************************************** 46 * DMA 47 **************************************************/ 48 49 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 50 { 51 u32 val; 52 int i; 53 54 if (!ring->mmio_base) 55 return; 56 57 /* Suspend DMA TX ring first. 58 * bgmac_wait_value doesn't support waiting for any of few values, so 59 * implement whole loop here. 60 */ 61 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 62 BGMAC_DMA_TX_SUSPEND); 63 for (i = 0; i < 10000 / 10; i++) { 64 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 65 val &= BGMAC_DMA_TX_STAT; 66 if (val == BGMAC_DMA_TX_STAT_DISABLED || 67 val == BGMAC_DMA_TX_STAT_IDLEWAIT || 68 val == BGMAC_DMA_TX_STAT_STOPPED) { 69 i = 0; 70 break; 71 } 72 udelay(10); 73 } 74 if (i) 75 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", 76 ring->mmio_base, val); 77 78 /* Remove SUSPEND bit */ 79 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); 80 if (!bgmac_wait_value(bgmac->core, 81 ring->mmio_base + BGMAC_DMA_TX_STATUS, 82 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, 83 10000)) { 84 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", 85 ring->mmio_base); 86 udelay(300); 87 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 88 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) 89 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n", 90 ring->mmio_base); 91 } 92 } 93 94 static void bgmac_dma_tx_enable(struct bgmac *bgmac, 95 struct bgmac_dma_ring *ring) 96 { 97 u32 ctl; 98 99 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); 100 if (bgmac->core->id.rev >= 4) { 101 ctl &= ~BGMAC_DMA_TX_BL_MASK; 102 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; 103 104 ctl &= ~BGMAC_DMA_TX_MR_MASK; 105 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT; 106 107 ctl &= ~BGMAC_DMA_TX_PC_MASK; 108 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT; 109 110 ctl &= ~BGMAC_DMA_TX_PT_MASK; 111 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT; 112 } 113 ctl |= BGMAC_DMA_TX_ENABLE; 114 ctl |= BGMAC_DMA_TX_PARITY_DISABLE; 115 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); 116 } 117 118 static void 119 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 120 int i, int len, u32 ctl0) 121 { 122 struct bgmac_slot_info *slot; 123 struct bgmac_dma_desc *dma_desc; 124 u32 ctl1; 125 126 if (i == BGMAC_TX_RING_SLOTS - 1) 127 ctl0 |= BGMAC_DESC_CTL0_EOT; 128 129 ctl1 = len & BGMAC_DESC_CTL1_LEN; 130 131 slot = &ring->slots[i]; 132 dma_desc = &ring->cpu_base[i]; 133 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); 134 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); 135 dma_desc->ctl0 = cpu_to_le32(ctl0); 136 dma_desc->ctl1 = cpu_to_le32(ctl1); 137 } 138 139 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, 140 struct bgmac_dma_ring *ring, 141 struct sk_buff *skb) 142 { 143 struct device *dma_dev = bgmac->core->dma_dev; 144 struct net_device *net_dev = bgmac->net_dev; 145 int index = ring->end % BGMAC_TX_RING_SLOTS; 146 struct bgmac_slot_info *slot = &ring->slots[index]; 147 int nr_frags; 148 u32 flags; 149 int i; 150 151 if (skb->len > BGMAC_DESC_CTL1_LEN) { 152 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len); 153 goto err_drop; 154 } 155 156 if (skb->ip_summed == CHECKSUM_PARTIAL) 157 skb_checksum_help(skb); 158 159 nr_frags = skb_shinfo(skb)->nr_frags; 160 161 /* ring->end - ring->start will return the number of valid slots, 162 * even when ring->end overflows 163 */ 164 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) { 165 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n"); 166 netif_stop_queue(net_dev); 167 return NETDEV_TX_BUSY; 168 } 169 170 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb), 171 DMA_TO_DEVICE); 172 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 173 goto err_dma_head; 174 175 flags = BGMAC_DESC_CTL0_SOF; 176 if (!nr_frags) 177 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 178 179 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags); 180 flags = 0; 181 182 for (i = 0; i < nr_frags; i++) { 183 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 184 int len = skb_frag_size(frag); 185 186 index = (index + 1) % BGMAC_TX_RING_SLOTS; 187 slot = &ring->slots[index]; 188 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0, 189 len, DMA_TO_DEVICE); 190 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 191 goto err_dma; 192 193 if (i == nr_frags - 1) 194 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 195 196 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags); 197 } 198 199 slot->skb = skb; 200 ring->end += nr_frags + 1; 201 netdev_sent_queue(net_dev, skb->len); 202 203 wmb(); 204 205 /* Increase ring->end to point empty slot. We tell hardware the first 206 * slot it should *not* read. 207 */ 208 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, 209 ring->index_base + 210 (ring->end % BGMAC_TX_RING_SLOTS) * 211 sizeof(struct bgmac_dma_desc)); 212 213 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8) 214 netif_stop_queue(net_dev); 215 216 return NETDEV_TX_OK; 217 218 err_dma: 219 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb), 220 DMA_TO_DEVICE); 221 222 while (i > 0) { 223 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS; 224 struct bgmac_slot_info *slot = &ring->slots[index]; 225 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); 226 int len = ctl1 & BGMAC_DESC_CTL1_LEN; 227 228 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE); 229 } 230 231 err_dma_head: 232 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", 233 ring->mmio_base); 234 235 err_drop: 236 dev_kfree_skb(skb); 237 return NETDEV_TX_OK; 238 } 239 240 /* Free transmitted packets */ 241 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 242 { 243 struct device *dma_dev = bgmac->core->dma_dev; 244 int empty_slot; 245 bool freed = false; 246 unsigned bytes_compl = 0, pkts_compl = 0; 247 248 /* The last slot that hardware didn't consume yet */ 249 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 250 empty_slot &= BGMAC_DMA_TX_STATDPTR; 251 empty_slot -= ring->index_base; 252 empty_slot &= BGMAC_DMA_TX_STATDPTR; 253 empty_slot /= sizeof(struct bgmac_dma_desc); 254 255 while (ring->start != ring->end) { 256 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS; 257 struct bgmac_slot_info *slot = &ring->slots[slot_idx]; 258 u32 ctl1; 259 int len; 260 261 if (slot_idx == empty_slot) 262 break; 263 264 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); 265 len = ctl1 & BGMAC_DESC_CTL1_LEN; 266 if (ctl1 & BGMAC_DESC_CTL0_SOF) 267 /* Unmap no longer used buffer */ 268 dma_unmap_single(dma_dev, slot->dma_addr, len, 269 DMA_TO_DEVICE); 270 else 271 dma_unmap_page(dma_dev, slot->dma_addr, len, 272 DMA_TO_DEVICE); 273 274 if (slot->skb) { 275 bytes_compl += slot->skb->len; 276 pkts_compl++; 277 278 /* Free memory! :) */ 279 dev_kfree_skb(slot->skb); 280 slot->skb = NULL; 281 } 282 283 slot->dma_addr = 0; 284 ring->start++; 285 freed = true; 286 } 287 288 if (!pkts_compl) 289 return; 290 291 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); 292 293 if (netif_queue_stopped(bgmac->net_dev)) 294 netif_wake_queue(bgmac->net_dev); 295 } 296 297 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 298 { 299 if (!ring->mmio_base) 300 return; 301 302 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); 303 if (!bgmac_wait_value(bgmac->core, 304 ring->mmio_base + BGMAC_DMA_RX_STATUS, 305 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, 306 10000)) 307 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n", 308 ring->mmio_base); 309 } 310 311 static void bgmac_dma_rx_enable(struct bgmac *bgmac, 312 struct bgmac_dma_ring *ring) 313 { 314 u32 ctl; 315 316 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); 317 if (bgmac->core->id.rev >= 4) { 318 ctl &= ~BGMAC_DMA_RX_BL_MASK; 319 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; 320 321 ctl &= ~BGMAC_DMA_RX_PC_MASK; 322 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT; 323 324 ctl &= ~BGMAC_DMA_RX_PT_MASK; 325 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; 326 } 327 ctl &= BGMAC_DMA_RX_ADDREXT_MASK; 328 ctl |= BGMAC_DMA_RX_ENABLE; 329 ctl |= BGMAC_DMA_RX_PARITY_DISABLE; 330 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; 331 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; 332 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); 333 } 334 335 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, 336 struct bgmac_slot_info *slot) 337 { 338 struct device *dma_dev = bgmac->core->dma_dev; 339 dma_addr_t dma_addr; 340 struct bgmac_rx_header *rx; 341 void *buf; 342 343 /* Alloc skb */ 344 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE); 345 if (!buf) 346 return -ENOMEM; 347 348 /* Poison - if everything goes fine, hardware will overwrite it */ 349 rx = buf + BGMAC_RX_BUF_OFFSET; 350 rx->len = cpu_to_le16(0xdead); 351 rx->flags = cpu_to_le16(0xbeef); 352 353 /* Map skb for the DMA */ 354 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET, 355 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 356 if (dma_mapping_error(dma_dev, dma_addr)) { 357 bgmac_err(bgmac, "DMA mapping error\n"); 358 put_page(virt_to_head_page(buf)); 359 return -ENOMEM; 360 } 361 362 /* Update the slot */ 363 slot->buf = buf; 364 slot->dma_addr = dma_addr; 365 366 return 0; 367 } 368 369 static void bgmac_dma_rx_update_index(struct bgmac *bgmac, 370 struct bgmac_dma_ring *ring) 371 { 372 dma_wmb(); 373 374 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, 375 ring->index_base + 376 ring->end * sizeof(struct bgmac_dma_desc)); 377 } 378 379 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, 380 struct bgmac_dma_ring *ring, int desc_idx) 381 { 382 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; 383 u32 ctl0 = 0, ctl1 = 0; 384 385 if (desc_idx == BGMAC_RX_RING_SLOTS - 1) 386 ctl0 |= BGMAC_DESC_CTL0_EOT; 387 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; 388 /* Is there any BGMAC device that requires extension? */ 389 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & 390 * B43_DMA64_DCTL1_ADDREXT_MASK; 391 */ 392 393 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr)); 394 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); 395 dma_desc->ctl0 = cpu_to_le32(ctl0); 396 dma_desc->ctl1 = cpu_to_le32(ctl1); 397 398 ring->end = desc_idx; 399 } 400 401 static void bgmac_dma_rx_poison_buf(struct device *dma_dev, 402 struct bgmac_slot_info *slot) 403 { 404 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 405 406 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, 407 DMA_FROM_DEVICE); 408 rx->len = cpu_to_le16(0xdead); 409 rx->flags = cpu_to_le16(0xbeef); 410 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, 411 DMA_FROM_DEVICE); 412 } 413 414 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 415 int weight) 416 { 417 u32 end_slot; 418 int handled = 0; 419 420 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); 421 end_slot &= BGMAC_DMA_RX_STATDPTR; 422 end_slot -= ring->index_base; 423 end_slot &= BGMAC_DMA_RX_STATDPTR; 424 end_slot /= sizeof(struct bgmac_dma_desc); 425 426 while (ring->start != end_slot) { 427 struct device *dma_dev = bgmac->core->dma_dev; 428 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 429 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 430 struct sk_buff *skb; 431 void *buf = slot->buf; 432 dma_addr_t dma_addr = slot->dma_addr; 433 u16 len, flags; 434 435 do { 436 /* Prepare new skb as replacement */ 437 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) { 438 bgmac_dma_rx_poison_buf(dma_dev, slot); 439 break; 440 } 441 442 /* Unmap buffer to make it accessible to the CPU */ 443 dma_unmap_single(dma_dev, dma_addr, 444 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 445 446 /* Get info from the header */ 447 len = le16_to_cpu(rx->len); 448 flags = le16_to_cpu(rx->flags); 449 450 /* Check for poison and drop or pass the packet */ 451 if (len == 0xdead && flags == 0xbeef) { 452 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n", 453 ring->start); 454 put_page(virt_to_head_page(buf)); 455 break; 456 } 457 458 if (len > BGMAC_RX_ALLOC_SIZE) { 459 bgmac_err(bgmac, "Found oversized packet at slot %d, DMA issue!\n", 460 ring->start); 461 put_page(virt_to_head_page(buf)); 462 break; 463 } 464 465 /* Omit CRC. */ 466 len -= ETH_FCS_LEN; 467 468 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); 469 if (unlikely(!skb)) { 470 bgmac_err(bgmac, "build_skb failed\n"); 471 put_page(virt_to_head_page(buf)); 472 break; 473 } 474 skb_put(skb, BGMAC_RX_FRAME_OFFSET + 475 BGMAC_RX_BUF_OFFSET + len); 476 skb_pull(skb, BGMAC_RX_FRAME_OFFSET + 477 BGMAC_RX_BUF_OFFSET); 478 479 skb_checksum_none_assert(skb); 480 skb->protocol = eth_type_trans(skb, bgmac->net_dev); 481 napi_gro_receive(&bgmac->napi, skb); 482 handled++; 483 } while (0); 484 485 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); 486 487 if (++ring->start >= BGMAC_RX_RING_SLOTS) 488 ring->start = 0; 489 490 if (handled >= weight) /* Should never be greater */ 491 break; 492 } 493 494 bgmac_dma_rx_update_index(bgmac, ring); 495 496 return handled; 497 } 498 499 /* Does ring support unaligned addressing? */ 500 static bool bgmac_dma_unaligned(struct bgmac *bgmac, 501 struct bgmac_dma_ring *ring, 502 enum bgmac_dma_ring_type ring_type) 503 { 504 switch (ring_type) { 505 case BGMAC_DMA_RING_TX: 506 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 507 0xff0); 508 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) 509 return true; 510 break; 511 case BGMAC_DMA_RING_RX: 512 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 513 0xff0); 514 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) 515 return true; 516 break; 517 } 518 return false; 519 } 520 521 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac, 522 struct bgmac_dma_ring *ring) 523 { 524 struct device *dma_dev = bgmac->core->dma_dev; 525 struct bgmac_dma_desc *dma_desc = ring->cpu_base; 526 struct bgmac_slot_info *slot; 527 int i; 528 529 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) { 530 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN; 531 532 slot = &ring->slots[i]; 533 dev_kfree_skb(slot->skb); 534 535 if (!slot->dma_addr) 536 continue; 537 538 if (slot->skb) 539 dma_unmap_single(dma_dev, slot->dma_addr, 540 len, DMA_TO_DEVICE); 541 else 542 dma_unmap_page(dma_dev, slot->dma_addr, 543 len, DMA_TO_DEVICE); 544 } 545 } 546 547 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac, 548 struct bgmac_dma_ring *ring) 549 { 550 struct device *dma_dev = bgmac->core->dma_dev; 551 struct bgmac_slot_info *slot; 552 int i; 553 554 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) { 555 slot = &ring->slots[i]; 556 if (!slot->dma_addr) 557 continue; 558 559 dma_unmap_single(dma_dev, slot->dma_addr, 560 BGMAC_RX_BUF_SIZE, 561 DMA_FROM_DEVICE); 562 put_page(virt_to_head_page(slot->buf)); 563 slot->dma_addr = 0; 564 } 565 } 566 567 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, 568 struct bgmac_dma_ring *ring, 569 int num_slots) 570 { 571 struct device *dma_dev = bgmac->core->dma_dev; 572 int size; 573 574 if (!ring->cpu_base) 575 return; 576 577 /* Free ring of descriptors */ 578 size = num_slots * sizeof(struct bgmac_dma_desc); 579 dma_free_coherent(dma_dev, size, ring->cpu_base, 580 ring->dma_base); 581 } 582 583 static void bgmac_dma_cleanup(struct bgmac *bgmac) 584 { 585 int i; 586 587 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 588 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); 589 590 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 591 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); 592 } 593 594 static void bgmac_dma_free(struct bgmac *bgmac) 595 { 596 int i; 597 598 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 599 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i], 600 BGMAC_TX_RING_SLOTS); 601 602 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 603 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i], 604 BGMAC_RX_RING_SLOTS); 605 } 606 607 static int bgmac_dma_alloc(struct bgmac *bgmac) 608 { 609 struct device *dma_dev = bgmac->core->dma_dev; 610 struct bgmac_dma_ring *ring; 611 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, 612 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, }; 613 int size; /* ring size: different for Tx and Rx */ 614 int err; 615 int i; 616 617 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); 618 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); 619 620 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) { 621 bgmac_err(bgmac, "Core does not report 64-bit DMA\n"); 622 return -ENOTSUPP; 623 } 624 625 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 626 ring = &bgmac->tx_ring[i]; 627 ring->mmio_base = ring_base[i]; 628 629 /* Alloc ring of descriptors */ 630 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc); 631 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 632 &ring->dma_base, 633 GFP_KERNEL); 634 if (!ring->cpu_base) { 635 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n", 636 ring->mmio_base); 637 goto err_dma_free; 638 } 639 640 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 641 BGMAC_DMA_RING_TX); 642 if (ring->unaligned) 643 ring->index_base = lower_32_bits(ring->dma_base); 644 else 645 ring->index_base = 0; 646 647 /* No need to alloc TX slots yet */ 648 } 649 650 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 651 ring = &bgmac->rx_ring[i]; 652 ring->mmio_base = ring_base[i]; 653 654 /* Alloc ring of descriptors */ 655 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc); 656 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 657 &ring->dma_base, 658 GFP_KERNEL); 659 if (!ring->cpu_base) { 660 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n", 661 ring->mmio_base); 662 err = -ENOMEM; 663 goto err_dma_free; 664 } 665 666 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 667 BGMAC_DMA_RING_RX); 668 if (ring->unaligned) 669 ring->index_base = lower_32_bits(ring->dma_base); 670 else 671 ring->index_base = 0; 672 } 673 674 return 0; 675 676 err_dma_free: 677 bgmac_dma_free(bgmac); 678 return -ENOMEM; 679 } 680 681 static int bgmac_dma_init(struct bgmac *bgmac) 682 { 683 struct bgmac_dma_ring *ring; 684 int i, err; 685 686 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 687 ring = &bgmac->tx_ring[i]; 688 689 if (!ring->unaligned) 690 bgmac_dma_tx_enable(bgmac, ring); 691 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 692 lower_32_bits(ring->dma_base)); 693 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, 694 upper_32_bits(ring->dma_base)); 695 if (ring->unaligned) 696 bgmac_dma_tx_enable(bgmac, ring); 697 698 ring->start = 0; 699 ring->end = 0; /* Points the slot that should *not* be read */ 700 } 701 702 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 703 int j; 704 705 ring = &bgmac->rx_ring[i]; 706 707 if (!ring->unaligned) 708 bgmac_dma_rx_enable(bgmac, ring); 709 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 710 lower_32_bits(ring->dma_base)); 711 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, 712 upper_32_bits(ring->dma_base)); 713 if (ring->unaligned) 714 bgmac_dma_rx_enable(bgmac, ring); 715 716 ring->start = 0; 717 ring->end = 0; 718 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) { 719 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); 720 if (err) 721 goto error; 722 723 bgmac_dma_rx_setup_desc(bgmac, ring, j); 724 } 725 726 bgmac_dma_rx_update_index(bgmac, ring); 727 } 728 729 return 0; 730 731 error: 732 bgmac_dma_cleanup(bgmac); 733 return err; 734 } 735 736 /************************************************** 737 * PHY ops 738 **************************************************/ 739 740 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg) 741 { 742 struct bcma_device *core; 743 u16 phy_access_addr; 744 u16 phy_ctl_addr; 745 u32 tmp; 746 747 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK); 748 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK); 749 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT); 750 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK); 751 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT); 752 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE); 753 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START); 754 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK); 755 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK); 756 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT); 757 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE); 758 759 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 760 core = bgmac->core->bus->drv_gmac_cmn.core; 761 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 762 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 763 } else { 764 core = bgmac->core; 765 phy_access_addr = BGMAC_PHY_ACCESS; 766 phy_ctl_addr = BGMAC_PHY_CNTL; 767 } 768 769 tmp = bcma_read32(core, phy_ctl_addr); 770 tmp &= ~BGMAC_PC_EPA_MASK; 771 tmp |= phyaddr; 772 bcma_write32(core, phy_ctl_addr, tmp); 773 774 tmp = BGMAC_PA_START; 775 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 776 tmp |= reg << BGMAC_PA_REG_SHIFT; 777 bcma_write32(core, phy_access_addr, tmp); 778 779 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 780 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n", 781 phyaddr, reg); 782 return 0xffff; 783 } 784 785 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK; 786 } 787 788 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */ 789 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value) 790 { 791 struct bcma_device *core; 792 u16 phy_access_addr; 793 u16 phy_ctl_addr; 794 u32 tmp; 795 796 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 797 core = bgmac->core->bus->drv_gmac_cmn.core; 798 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 799 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 800 } else { 801 core = bgmac->core; 802 phy_access_addr = BGMAC_PHY_ACCESS; 803 phy_ctl_addr = BGMAC_PHY_CNTL; 804 } 805 806 tmp = bcma_read32(core, phy_ctl_addr); 807 tmp &= ~BGMAC_PC_EPA_MASK; 808 tmp |= phyaddr; 809 bcma_write32(core, phy_ctl_addr, tmp); 810 811 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO); 812 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO) 813 bgmac_warn(bgmac, "Error setting MDIO int\n"); 814 815 tmp = BGMAC_PA_START; 816 tmp |= BGMAC_PA_WRITE; 817 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 818 tmp |= reg << BGMAC_PA_REG_SHIFT; 819 tmp |= value; 820 bcma_write32(core, phy_access_addr, tmp); 821 822 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 823 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n", 824 phyaddr, reg); 825 return -ETIMEDOUT; 826 } 827 828 return 0; 829 } 830 831 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */ 832 static void bgmac_phy_init(struct bgmac *bgmac) 833 { 834 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 835 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 836 u8 i; 837 838 if (ci->id == BCMA_CHIP_ID_BCM5356) { 839 for (i = 0; i < 5; i++) { 840 bgmac_phy_write(bgmac, i, 0x1f, 0x008b); 841 bgmac_phy_write(bgmac, i, 0x15, 0x0100); 842 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 843 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa); 844 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 845 } 846 } 847 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) || 848 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) || 849 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) { 850 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0); 851 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0); 852 for (i = 0; i < 5; i++) { 853 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 854 bgmac_phy_write(bgmac, i, 0x16, 0x5284); 855 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 856 bgmac_phy_write(bgmac, i, 0x17, 0x0010); 857 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 858 bgmac_phy_write(bgmac, i, 0x16, 0x5296); 859 bgmac_phy_write(bgmac, i, 0x17, 0x1073); 860 bgmac_phy_write(bgmac, i, 0x17, 0x9073); 861 bgmac_phy_write(bgmac, i, 0x16, 0x52b6); 862 bgmac_phy_write(bgmac, i, 0x17, 0x9273); 863 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 864 } 865 } 866 } 867 868 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */ 869 static void bgmac_phy_reset(struct bgmac *bgmac) 870 { 871 if (bgmac->phyaddr == BGMAC_PHY_NOREGS) 872 return; 873 874 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET); 875 udelay(100); 876 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET) 877 bgmac_err(bgmac, "PHY reset failed\n"); 878 bgmac_phy_init(bgmac); 879 } 880 881 /************************************************** 882 * Chip ops 883 **************************************************/ 884 885 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is 886 * nothing to change? Try if after stabilizng driver. 887 */ 888 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, 889 bool force) 890 { 891 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 892 u32 new_val = (cmdcfg & mask) | set; 893 894 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 895 udelay(2); 896 897 if (new_val != cmdcfg || force) 898 bgmac_write(bgmac, BGMAC_CMDCFG, new_val); 899 900 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 901 udelay(2); 902 } 903 904 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr) 905 { 906 u32 tmp; 907 908 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 909 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); 910 tmp = (addr[4] << 8) | addr[5]; 911 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); 912 } 913 914 static void bgmac_set_rx_mode(struct net_device *net_dev) 915 { 916 struct bgmac *bgmac = netdev_priv(net_dev); 917 918 if (net_dev->flags & IFF_PROMISC) 919 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true); 920 else 921 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true); 922 } 923 924 #if 0 /* We don't use that regs yet */ 925 static void bgmac_chip_stats_update(struct bgmac *bgmac) 926 { 927 int i; 928 929 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) { 930 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 931 bgmac->mib_tx_regs[i] = 932 bgmac_read(bgmac, 933 BGMAC_TX_GOOD_OCTETS + (i * 4)); 934 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 935 bgmac->mib_rx_regs[i] = 936 bgmac_read(bgmac, 937 BGMAC_RX_GOOD_OCTETS + (i * 4)); 938 } 939 940 /* TODO: what else? how to handle BCM4706? Specs are needed */ 941 } 942 #endif 943 944 static void bgmac_clear_mib(struct bgmac *bgmac) 945 { 946 int i; 947 948 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) 949 return; 950 951 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); 952 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 953 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); 954 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 955 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); 956 } 957 958 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ 959 static void bgmac_mac_speed(struct bgmac *bgmac) 960 { 961 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); 962 u32 set = 0; 963 964 switch (bgmac->mac_speed) { 965 case SPEED_10: 966 set |= BGMAC_CMDCFG_ES_10; 967 break; 968 case SPEED_100: 969 set |= BGMAC_CMDCFG_ES_100; 970 break; 971 case SPEED_1000: 972 set |= BGMAC_CMDCFG_ES_1000; 973 break; 974 case SPEED_2500: 975 set |= BGMAC_CMDCFG_ES_2500; 976 break; 977 default: 978 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed); 979 } 980 981 if (bgmac->mac_duplex == DUPLEX_HALF) 982 set |= BGMAC_CMDCFG_HD; 983 984 bgmac_cmdcfg_maskset(bgmac, mask, set, true); 985 } 986 987 static void bgmac_miiconfig(struct bgmac *bgmac) 988 { 989 struct bcma_device *core = bgmac->core; 990 struct bcma_chipinfo *ci = &core->bus->chipinfo; 991 u8 imode; 992 993 if (ci->id == BCMA_CHIP_ID_BCM4707 || 994 ci->id == BCMA_CHIP_ID_BCM53018) { 995 bcma_awrite32(core, BCMA_IOCTL, 996 bcma_aread32(core, BCMA_IOCTL) | 0x40 | 997 BGMAC_BCMA_IOCTL_SW_CLKEN); 998 bgmac->mac_speed = SPEED_2500; 999 bgmac->mac_duplex = DUPLEX_FULL; 1000 bgmac_mac_speed(bgmac); 1001 } else { 1002 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & 1003 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; 1004 if (imode == 0 || imode == 1) { 1005 bgmac->mac_speed = SPEED_100; 1006 bgmac->mac_duplex = DUPLEX_FULL; 1007 bgmac_mac_speed(bgmac); 1008 } 1009 } 1010 } 1011 1012 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ 1013 static void bgmac_chip_reset(struct bgmac *bgmac) 1014 { 1015 struct bcma_device *core = bgmac->core; 1016 struct bcma_bus *bus = core->bus; 1017 struct bcma_chipinfo *ci = &bus->chipinfo; 1018 u32 flags; 1019 u32 iost; 1020 int i; 1021 1022 if (bcma_core_is_enabled(core)) { 1023 if (!bgmac->stats_grabbed) { 1024 /* bgmac_chip_stats_update(bgmac); */ 1025 bgmac->stats_grabbed = true; 1026 } 1027 1028 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 1029 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); 1030 1031 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1032 udelay(1); 1033 1034 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 1035 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); 1036 1037 /* TODO: Clear software multicast filter list */ 1038 } 1039 1040 iost = bcma_aread32(core, BCMA_IOST); 1041 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 1042 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 1043 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) 1044 iost &= ~BGMAC_BCMA_IOST_ATTACHED; 1045 1046 /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */ 1047 if (ci->id != BCMA_CHIP_ID_BCM4707) { 1048 flags = 0; 1049 if (iost & BGMAC_BCMA_IOST_ATTACHED) { 1050 flags = BGMAC_BCMA_IOCTL_SW_CLKEN; 1051 if (!bgmac->has_robosw) 1052 flags |= BGMAC_BCMA_IOCTL_SW_RESET; 1053 } 1054 bcma_core_enable(core, flags); 1055 } 1056 1057 /* Request Misc PLL for corerev > 2 */ 1058 if (core->id.rev > 2 && 1059 ci->id != BCMA_CHIP_ID_BCM4707 && 1060 ci->id != BCMA_CHIP_ID_BCM53018) { 1061 bgmac_set(bgmac, BCMA_CLKCTLST, 1062 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); 1063 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1064 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 1065 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 1066 1000); 1067 } 1068 1069 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1070 ci->id == BCMA_CHIP_ID_BCM4749 || 1071 ci->id == BCMA_CHIP_ID_BCM53572) { 1072 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 1073 u8 et_swtype = 0; 1074 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | 1075 BGMAC_CHIPCTL_1_IF_TYPE_MII; 1076 char buf[4]; 1077 1078 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 1079 if (kstrtou8(buf, 0, &et_swtype)) 1080 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n", 1081 buf); 1082 et_swtype &= 0x0f; 1083 et_swtype <<= 4; 1084 sw_type = et_swtype; 1085 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) { 1086 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; 1087 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 1088 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 1089 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) { 1090 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | 1091 BGMAC_CHIPCTL_1_SW_TYPE_RGMII; 1092 } 1093 bcma_chipco_chipctl_maskset(cc, 1, 1094 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | 1095 BGMAC_CHIPCTL_1_SW_TYPE_MASK), 1096 sw_type); 1097 } 1098 1099 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) 1100 bcma_awrite32(core, BCMA_IOCTL, 1101 bcma_aread32(core, BCMA_IOCTL) & 1102 ~BGMAC_BCMA_IOCTL_SW_RESET); 1103 1104 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset 1105 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine 1106 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to 1107 * be keps until taking MAC out of the reset. 1108 */ 1109 bgmac_cmdcfg_maskset(bgmac, 1110 ~(BGMAC_CMDCFG_TE | 1111 BGMAC_CMDCFG_RE | 1112 BGMAC_CMDCFG_RPI | 1113 BGMAC_CMDCFG_TAI | 1114 BGMAC_CMDCFG_HD | 1115 BGMAC_CMDCFG_ML | 1116 BGMAC_CMDCFG_CFE | 1117 BGMAC_CMDCFG_RL | 1118 BGMAC_CMDCFG_RED | 1119 BGMAC_CMDCFG_PE | 1120 BGMAC_CMDCFG_TPI | 1121 BGMAC_CMDCFG_PAD_EN | 1122 BGMAC_CMDCFG_PF), 1123 BGMAC_CMDCFG_PROM | 1124 BGMAC_CMDCFG_NLC | 1125 BGMAC_CMDCFG_CFE | 1126 BGMAC_CMDCFG_SR(core->id.rev), 1127 false); 1128 bgmac->mac_speed = SPEED_UNKNOWN; 1129 bgmac->mac_duplex = DUPLEX_UNKNOWN; 1130 1131 bgmac_clear_mib(bgmac); 1132 if (core->id.id == BCMA_CORE_4706_MAC_GBIT) 1133 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0, 1134 BCMA_GMAC_CMN_PC_MTE); 1135 else 1136 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); 1137 bgmac_miiconfig(bgmac); 1138 bgmac_phy_init(bgmac); 1139 1140 netdev_reset_queue(bgmac->net_dev); 1141 } 1142 1143 static void bgmac_chip_intrs_on(struct bgmac *bgmac) 1144 { 1145 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); 1146 } 1147 1148 static void bgmac_chip_intrs_off(struct bgmac *bgmac) 1149 { 1150 bgmac_write(bgmac, BGMAC_INT_MASK, 0); 1151 bgmac_read(bgmac, BGMAC_INT_MASK); 1152 } 1153 1154 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ 1155 static void bgmac_enable(struct bgmac *bgmac) 1156 { 1157 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 1158 u32 cmdcfg; 1159 u32 mode; 1160 u32 rxq_ctl; 1161 u32 fl_ctl; 1162 u16 bp_clk; 1163 u8 mdp; 1164 1165 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 1166 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), 1167 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true); 1168 udelay(2); 1169 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; 1170 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); 1171 1172 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 1173 BGMAC_DS_MM_SHIFT; 1174 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0) 1175 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 1176 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2) 1177 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0, 1178 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); 1179 1180 switch (ci->id) { 1181 case BCMA_CHIP_ID_BCM5357: 1182 case BCMA_CHIP_ID_BCM4749: 1183 case BCMA_CHIP_ID_BCM53572: 1184 case BCMA_CHIP_ID_BCM4716: 1185 case BCMA_CHIP_ID_BCM47162: 1186 fl_ctl = 0x03cb04cb; 1187 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1188 ci->id == BCMA_CHIP_ID_BCM4749 || 1189 ci->id == BCMA_CHIP_ID_BCM53572) 1190 fl_ctl = 0x2300e1; 1191 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); 1192 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); 1193 break; 1194 } 1195 1196 if (ci->id != BCMA_CHIP_ID_BCM4707 && 1197 ci->id != BCMA_CHIP_ID_BCM53018) { 1198 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); 1199 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; 1200 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1201 1000000; 1202 mdp = (bp_clk * 128 / 1000) - 3; 1203 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); 1204 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); 1205 } 1206 } 1207 1208 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ 1209 static void bgmac_chip_init(struct bgmac *bgmac) 1210 { 1211 /* 1 interrupt per received frame */ 1212 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); 1213 1214 /* Enable 802.3x tx flow control (honor received PAUSE frames) */ 1215 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); 1216 1217 bgmac_set_rx_mode(bgmac->net_dev); 1218 1219 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr); 1220 1221 if (bgmac->loopback) 1222 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1223 else 1224 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false); 1225 1226 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); 1227 1228 bgmac_chip_intrs_on(bgmac); 1229 1230 bgmac_enable(bgmac); 1231 } 1232 1233 static irqreturn_t bgmac_interrupt(int irq, void *dev_id) 1234 { 1235 struct bgmac *bgmac = netdev_priv(dev_id); 1236 1237 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); 1238 int_status &= bgmac->int_mask; 1239 1240 if (!int_status) 1241 return IRQ_NONE; 1242 1243 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX); 1244 if (int_status) 1245 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status); 1246 1247 /* Disable new interrupts until handling existing ones */ 1248 bgmac_chip_intrs_off(bgmac); 1249 1250 napi_schedule(&bgmac->napi); 1251 1252 return IRQ_HANDLED; 1253 } 1254 1255 static int bgmac_poll(struct napi_struct *napi, int weight) 1256 { 1257 struct bgmac *bgmac = container_of(napi, struct bgmac, napi); 1258 int handled = 0; 1259 1260 /* Ack */ 1261 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); 1262 1263 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]); 1264 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight); 1265 1266 /* Poll again if more events arrived in the meantime */ 1267 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX)) 1268 return weight; 1269 1270 if (handled < weight) { 1271 napi_complete(napi); 1272 bgmac_chip_intrs_on(bgmac); 1273 } 1274 1275 return handled; 1276 } 1277 1278 /************************************************** 1279 * net_device_ops 1280 **************************************************/ 1281 1282 static int bgmac_open(struct net_device *net_dev) 1283 { 1284 struct bgmac *bgmac = netdev_priv(net_dev); 1285 int err = 0; 1286 1287 bgmac_chip_reset(bgmac); 1288 1289 err = bgmac_dma_init(bgmac); 1290 if (err) 1291 return err; 1292 1293 /* Specs say about reclaiming rings here, but we do that in DMA init */ 1294 bgmac_chip_init(bgmac); 1295 1296 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED, 1297 KBUILD_MODNAME, net_dev); 1298 if (err < 0) { 1299 bgmac_err(bgmac, "IRQ request error: %d!\n", err); 1300 bgmac_dma_cleanup(bgmac); 1301 return err; 1302 } 1303 napi_enable(&bgmac->napi); 1304 1305 phy_start(bgmac->phy_dev); 1306 1307 netif_carrier_on(net_dev); 1308 return 0; 1309 } 1310 1311 static int bgmac_stop(struct net_device *net_dev) 1312 { 1313 struct bgmac *bgmac = netdev_priv(net_dev); 1314 1315 netif_carrier_off(net_dev); 1316 1317 phy_stop(bgmac->phy_dev); 1318 1319 napi_disable(&bgmac->napi); 1320 bgmac_chip_intrs_off(bgmac); 1321 free_irq(bgmac->core->irq, net_dev); 1322 1323 bgmac_chip_reset(bgmac); 1324 bgmac_dma_cleanup(bgmac); 1325 1326 return 0; 1327 } 1328 1329 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, 1330 struct net_device *net_dev) 1331 { 1332 struct bgmac *bgmac = netdev_priv(net_dev); 1333 struct bgmac_dma_ring *ring; 1334 1335 /* No QOS support yet */ 1336 ring = &bgmac->tx_ring[0]; 1337 return bgmac_dma_tx_add(bgmac, ring, skb); 1338 } 1339 1340 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr) 1341 { 1342 struct bgmac *bgmac = netdev_priv(net_dev); 1343 int ret; 1344 1345 ret = eth_prepare_mac_addr_change(net_dev, addr); 1346 if (ret < 0) 1347 return ret; 1348 bgmac_write_mac_address(bgmac, (u8 *)addr); 1349 eth_commit_mac_addr_change(net_dev, addr); 1350 return 0; 1351 } 1352 1353 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1354 { 1355 struct bgmac *bgmac = netdev_priv(net_dev); 1356 1357 if (!netif_running(net_dev)) 1358 return -EINVAL; 1359 1360 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd); 1361 } 1362 1363 static const struct net_device_ops bgmac_netdev_ops = { 1364 .ndo_open = bgmac_open, 1365 .ndo_stop = bgmac_stop, 1366 .ndo_start_xmit = bgmac_start_xmit, 1367 .ndo_set_rx_mode = bgmac_set_rx_mode, 1368 .ndo_set_mac_address = bgmac_set_mac_address, 1369 .ndo_validate_addr = eth_validate_addr, 1370 .ndo_do_ioctl = bgmac_ioctl, 1371 }; 1372 1373 /************************************************** 1374 * ethtool_ops 1375 **************************************************/ 1376 1377 static int bgmac_get_settings(struct net_device *net_dev, 1378 struct ethtool_cmd *cmd) 1379 { 1380 struct bgmac *bgmac = netdev_priv(net_dev); 1381 1382 return phy_ethtool_gset(bgmac->phy_dev, cmd); 1383 } 1384 1385 static int bgmac_set_settings(struct net_device *net_dev, 1386 struct ethtool_cmd *cmd) 1387 { 1388 struct bgmac *bgmac = netdev_priv(net_dev); 1389 1390 return phy_ethtool_sset(bgmac->phy_dev, cmd); 1391 } 1392 1393 static void bgmac_get_drvinfo(struct net_device *net_dev, 1394 struct ethtool_drvinfo *info) 1395 { 1396 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1397 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info)); 1398 } 1399 1400 static const struct ethtool_ops bgmac_ethtool_ops = { 1401 .get_settings = bgmac_get_settings, 1402 .set_settings = bgmac_set_settings, 1403 .get_drvinfo = bgmac_get_drvinfo, 1404 }; 1405 1406 /************************************************** 1407 * MII 1408 **************************************************/ 1409 1410 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum) 1411 { 1412 return bgmac_phy_read(bus->priv, mii_id, regnum); 1413 } 1414 1415 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum, 1416 u16 value) 1417 { 1418 return bgmac_phy_write(bus->priv, mii_id, regnum, value); 1419 } 1420 1421 static void bgmac_adjust_link(struct net_device *net_dev) 1422 { 1423 struct bgmac *bgmac = netdev_priv(net_dev); 1424 struct phy_device *phy_dev = bgmac->phy_dev; 1425 bool update = false; 1426 1427 if (phy_dev->link) { 1428 if (phy_dev->speed != bgmac->mac_speed) { 1429 bgmac->mac_speed = phy_dev->speed; 1430 update = true; 1431 } 1432 1433 if (phy_dev->duplex != bgmac->mac_duplex) { 1434 bgmac->mac_duplex = phy_dev->duplex; 1435 update = true; 1436 } 1437 } 1438 1439 if (update) { 1440 bgmac_mac_speed(bgmac); 1441 phy_print_status(phy_dev); 1442 } 1443 } 1444 1445 static int bgmac_fixed_phy_register(struct bgmac *bgmac) 1446 { 1447 struct fixed_phy_status fphy_status = { 1448 .link = 1, 1449 .speed = SPEED_1000, 1450 .duplex = DUPLEX_FULL, 1451 }; 1452 struct phy_device *phy_dev; 1453 int err; 1454 1455 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); 1456 if (!phy_dev || IS_ERR(phy_dev)) { 1457 bgmac_err(bgmac, "Failed to register fixed PHY device\n"); 1458 return -ENODEV; 1459 } 1460 1461 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link, 1462 PHY_INTERFACE_MODE_MII); 1463 if (err) { 1464 bgmac_err(bgmac, "Connecting PHY failed\n"); 1465 return err; 1466 } 1467 1468 bgmac->phy_dev = phy_dev; 1469 1470 return err; 1471 } 1472 1473 static int bgmac_mii_register(struct bgmac *bgmac) 1474 { 1475 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 1476 struct mii_bus *mii_bus; 1477 struct phy_device *phy_dev; 1478 char bus_id[MII_BUS_ID_SIZE + 3]; 1479 int err = 0; 1480 1481 if (ci->id == BCMA_CHIP_ID_BCM4707 || 1482 ci->id == BCMA_CHIP_ID_BCM53018) 1483 return bgmac_fixed_phy_register(bgmac); 1484 1485 mii_bus = mdiobus_alloc(); 1486 if (!mii_bus) 1487 return -ENOMEM; 1488 1489 mii_bus->name = "bgmac mii bus"; 1490 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num, 1491 bgmac->core->core_unit); 1492 mii_bus->priv = bgmac; 1493 mii_bus->read = bgmac_mii_read; 1494 mii_bus->write = bgmac_mii_write; 1495 mii_bus->parent = &bgmac->core->dev; 1496 mii_bus->phy_mask = ~(1 << bgmac->phyaddr); 1497 1498 err = mdiobus_register(mii_bus); 1499 if (err) { 1500 bgmac_err(bgmac, "Registration of mii bus failed\n"); 1501 goto err_free_bus; 1502 } 1503 1504 bgmac->mii_bus = mii_bus; 1505 1506 /* Connect to the PHY */ 1507 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id, 1508 bgmac->phyaddr); 1509 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link, 1510 PHY_INTERFACE_MODE_MII); 1511 if (IS_ERR(phy_dev)) { 1512 bgmac_err(bgmac, "PHY connecton failed\n"); 1513 err = PTR_ERR(phy_dev); 1514 goto err_unregister_bus; 1515 } 1516 bgmac->phy_dev = phy_dev; 1517 1518 return err; 1519 1520 err_unregister_bus: 1521 mdiobus_unregister(mii_bus); 1522 err_free_bus: 1523 mdiobus_free(mii_bus); 1524 return err; 1525 } 1526 1527 static void bgmac_mii_unregister(struct bgmac *bgmac) 1528 { 1529 struct mii_bus *mii_bus = bgmac->mii_bus; 1530 1531 mdiobus_unregister(mii_bus); 1532 mdiobus_free(mii_bus); 1533 } 1534 1535 /************************************************** 1536 * BCMA bus ops 1537 **************************************************/ 1538 1539 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */ 1540 static int bgmac_probe(struct bcma_device *core) 1541 { 1542 struct bcma_chipinfo *ci = &core->bus->chipinfo; 1543 struct net_device *net_dev; 1544 struct bgmac *bgmac; 1545 struct ssb_sprom *sprom = &core->bus->sprom; 1546 u8 *mac; 1547 int err; 1548 1549 switch (core->core_unit) { 1550 case 0: 1551 mac = sprom->et0mac; 1552 break; 1553 case 1: 1554 mac = sprom->et1mac; 1555 break; 1556 case 2: 1557 mac = sprom->et2mac; 1558 break; 1559 default: 1560 pr_err("Unsupported core_unit %d\n", core->core_unit); 1561 return -ENOTSUPP; 1562 } 1563 1564 if (!is_valid_ether_addr(mac)) { 1565 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac); 1566 eth_random_addr(mac); 1567 dev_warn(&core->dev, "Using random MAC: %pM\n", mac); 1568 } 1569 1570 /* Allocation and references */ 1571 net_dev = alloc_etherdev(sizeof(*bgmac)); 1572 if (!net_dev) 1573 return -ENOMEM; 1574 net_dev->netdev_ops = &bgmac_netdev_ops; 1575 net_dev->irq = core->irq; 1576 net_dev->ethtool_ops = &bgmac_ethtool_ops; 1577 bgmac = netdev_priv(net_dev); 1578 bgmac->net_dev = net_dev; 1579 bgmac->core = core; 1580 bcma_set_drvdata(core, bgmac); 1581 1582 /* Defaults */ 1583 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN); 1584 1585 /* On BCM4706 we need common core to access PHY */ 1586 if (core->id.id == BCMA_CORE_4706_MAC_GBIT && 1587 !core->bus->drv_gmac_cmn.core) { 1588 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n"); 1589 err = -ENODEV; 1590 goto err_netdev_free; 1591 } 1592 bgmac->cmn = core->bus->drv_gmac_cmn.core; 1593 1594 switch (core->core_unit) { 1595 case 0: 1596 bgmac->phyaddr = sprom->et0phyaddr; 1597 break; 1598 case 1: 1599 bgmac->phyaddr = sprom->et1phyaddr; 1600 break; 1601 case 2: 1602 bgmac->phyaddr = sprom->et2phyaddr; 1603 break; 1604 } 1605 bgmac->phyaddr &= BGMAC_PHY_MASK; 1606 if (bgmac->phyaddr == BGMAC_PHY_MASK) { 1607 bgmac_err(bgmac, "No PHY found\n"); 1608 err = -ENODEV; 1609 goto err_netdev_free; 1610 } 1611 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr, 1612 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : ""); 1613 1614 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) { 1615 bgmac_err(bgmac, "PCI setup not implemented\n"); 1616 err = -ENOTSUPP; 1617 goto err_netdev_free; 1618 } 1619 1620 bgmac_chip_reset(bgmac); 1621 1622 /* For Northstar, we have to take all GMAC core out of reset */ 1623 if (ci->id == BCMA_CHIP_ID_BCM4707 || 1624 ci->id == BCMA_CHIP_ID_BCM53018) { 1625 struct bcma_device *ns_core; 1626 int ns_gmac; 1627 1628 /* Northstar has 4 GMAC cores */ 1629 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) { 1630 /* As Northstar requirement, we have to reset all GMACs 1631 * before accessing one. bgmac_chip_reset() call 1632 * bcma_core_enable() for this core. Then the other 1633 * three GMACs didn't reset. We do it here. 1634 */ 1635 ns_core = bcma_find_core_unit(core->bus, 1636 BCMA_CORE_MAC_GBIT, 1637 ns_gmac); 1638 if (ns_core && !bcma_core_is_enabled(ns_core)) 1639 bcma_core_enable(ns_core, 0); 1640 } 1641 } 1642 1643 err = bgmac_dma_alloc(bgmac); 1644 if (err) { 1645 bgmac_err(bgmac, "Unable to alloc memory for DMA\n"); 1646 goto err_netdev_free; 1647 } 1648 1649 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; 1650 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0) 1651 bgmac->int_mask &= ~BGMAC_IS_TX_MASK; 1652 1653 /* TODO: reset the external phy. Specs are needed */ 1654 bgmac_phy_reset(bgmac); 1655 1656 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo & 1657 BGMAC_BFL_ENETROBO); 1658 if (bgmac->has_robosw) 1659 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n"); 1660 1661 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) 1662 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n"); 1663 1664 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); 1665 1666 err = bgmac_mii_register(bgmac); 1667 if (err) { 1668 bgmac_err(bgmac, "Cannot register MDIO\n"); 1669 goto err_dma_free; 1670 } 1671 1672 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1673 net_dev->hw_features = net_dev->features; 1674 net_dev->vlan_features = net_dev->features; 1675 1676 err = register_netdev(bgmac->net_dev); 1677 if (err) { 1678 bgmac_err(bgmac, "Cannot register net device\n"); 1679 goto err_mii_unregister; 1680 } 1681 1682 netif_carrier_off(net_dev); 1683 1684 return 0; 1685 1686 err_mii_unregister: 1687 bgmac_mii_unregister(bgmac); 1688 err_dma_free: 1689 bgmac_dma_free(bgmac); 1690 1691 err_netdev_free: 1692 bcma_set_drvdata(core, NULL); 1693 free_netdev(net_dev); 1694 1695 return err; 1696 } 1697 1698 static void bgmac_remove(struct bcma_device *core) 1699 { 1700 struct bgmac *bgmac = bcma_get_drvdata(core); 1701 1702 unregister_netdev(bgmac->net_dev); 1703 bgmac_mii_unregister(bgmac); 1704 netif_napi_del(&bgmac->napi); 1705 bgmac_dma_free(bgmac); 1706 bcma_set_drvdata(core, NULL); 1707 free_netdev(bgmac->net_dev); 1708 } 1709 1710 static struct bcma_driver bgmac_bcma_driver = { 1711 .name = KBUILD_MODNAME, 1712 .id_table = bgmac_bcma_tbl, 1713 .probe = bgmac_probe, 1714 .remove = bgmac_remove, 1715 }; 1716 1717 static int __init bgmac_init(void) 1718 { 1719 int err; 1720 1721 err = bcma_driver_register(&bgmac_bcma_driver); 1722 if (err) 1723 return err; 1724 pr_info("Broadcom 47xx GBit MAC driver loaded\n"); 1725 1726 return 0; 1727 } 1728 1729 static void __exit bgmac_exit(void) 1730 { 1731 bcma_driver_unregister(&bgmac_bcma_driver); 1732 } 1733 1734 module_init(bgmac_init) 1735 module_exit(bgmac_exit) 1736 1737 MODULE_AUTHOR("Rafał Miłecki"); 1738 MODULE_LICENSE("GPL"); 1739