1 /* 2 * Driver for (BCM4706)? GBit MAC core on BCMA bus. 3 * 4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> 5 * 6 * Licensed under the GNU/GPL. See COPYING for details. 7 */ 8 9 10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 11 12 #include <linux/bcma/bcma.h> 13 #include <linux/etherdevice.h> 14 #include <linux/bcm47xx_nvram.h> 15 #include "bgmac.h" 16 17 static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask, 18 u32 value, int timeout) 19 { 20 u32 val; 21 int i; 22 23 for (i = 0; i < timeout / 10; i++) { 24 val = bgmac_read(bgmac, reg); 25 if ((val & mask) == value) 26 return true; 27 udelay(10); 28 } 29 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg); 30 return false; 31 } 32 33 /************************************************** 34 * DMA 35 **************************************************/ 36 37 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 38 { 39 u32 val; 40 int i; 41 42 if (!ring->mmio_base) 43 return; 44 45 /* Suspend DMA TX ring first. 46 * bgmac_wait_value doesn't support waiting for any of few values, so 47 * implement whole loop here. 48 */ 49 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 50 BGMAC_DMA_TX_SUSPEND); 51 for (i = 0; i < 10000 / 10; i++) { 52 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 53 val &= BGMAC_DMA_TX_STAT; 54 if (val == BGMAC_DMA_TX_STAT_DISABLED || 55 val == BGMAC_DMA_TX_STAT_IDLEWAIT || 56 val == BGMAC_DMA_TX_STAT_STOPPED) { 57 i = 0; 58 break; 59 } 60 udelay(10); 61 } 62 if (i) 63 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", 64 ring->mmio_base, val); 65 66 /* Remove SUSPEND bit */ 67 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); 68 if (!bgmac_wait_value(bgmac, 69 ring->mmio_base + BGMAC_DMA_TX_STATUS, 70 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, 71 10000)) { 72 dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", 73 ring->mmio_base); 74 udelay(300); 75 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 76 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) 77 dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n", 78 ring->mmio_base); 79 } 80 } 81 82 static void bgmac_dma_tx_enable(struct bgmac *bgmac, 83 struct bgmac_dma_ring *ring) 84 { 85 u32 ctl; 86 87 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); 88 if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) { 89 ctl &= ~BGMAC_DMA_TX_BL_MASK; 90 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; 91 92 ctl &= ~BGMAC_DMA_TX_MR_MASK; 93 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT; 94 95 ctl &= ~BGMAC_DMA_TX_PC_MASK; 96 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT; 97 98 ctl &= ~BGMAC_DMA_TX_PT_MASK; 99 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT; 100 } 101 ctl |= BGMAC_DMA_TX_ENABLE; 102 ctl |= BGMAC_DMA_TX_PARITY_DISABLE; 103 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); 104 } 105 106 static void 107 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 108 int i, int len, u32 ctl0) 109 { 110 struct bgmac_slot_info *slot; 111 struct bgmac_dma_desc *dma_desc; 112 u32 ctl1; 113 114 if (i == BGMAC_TX_RING_SLOTS - 1) 115 ctl0 |= BGMAC_DESC_CTL0_EOT; 116 117 ctl1 = len & BGMAC_DESC_CTL1_LEN; 118 119 slot = &ring->slots[i]; 120 dma_desc = &ring->cpu_base[i]; 121 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); 122 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); 123 dma_desc->ctl0 = cpu_to_le32(ctl0); 124 dma_desc->ctl1 = cpu_to_le32(ctl1); 125 } 126 127 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, 128 struct bgmac_dma_ring *ring, 129 struct sk_buff *skb) 130 { 131 struct device *dma_dev = bgmac->dma_dev; 132 struct net_device *net_dev = bgmac->net_dev; 133 int index = ring->end % BGMAC_TX_RING_SLOTS; 134 struct bgmac_slot_info *slot = &ring->slots[index]; 135 int nr_frags; 136 u32 flags; 137 int i; 138 139 if (skb->len > BGMAC_DESC_CTL1_LEN) { 140 netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len); 141 goto err_drop; 142 } 143 144 if (skb->ip_summed == CHECKSUM_PARTIAL) 145 skb_checksum_help(skb); 146 147 nr_frags = skb_shinfo(skb)->nr_frags; 148 149 /* ring->end - ring->start will return the number of valid slots, 150 * even when ring->end overflows 151 */ 152 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) { 153 netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n"); 154 netif_stop_queue(net_dev); 155 return NETDEV_TX_BUSY; 156 } 157 158 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb), 159 DMA_TO_DEVICE); 160 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 161 goto err_dma_head; 162 163 flags = BGMAC_DESC_CTL0_SOF; 164 if (!nr_frags) 165 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 166 167 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags); 168 flags = 0; 169 170 for (i = 0; i < nr_frags; i++) { 171 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 172 int len = skb_frag_size(frag); 173 174 index = (index + 1) % BGMAC_TX_RING_SLOTS; 175 slot = &ring->slots[index]; 176 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0, 177 len, DMA_TO_DEVICE); 178 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 179 goto err_dma; 180 181 if (i == nr_frags - 1) 182 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 183 184 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags); 185 } 186 187 slot->skb = skb; 188 ring->end += nr_frags + 1; 189 netdev_sent_queue(net_dev, skb->len); 190 191 wmb(); 192 193 /* Increase ring->end to point empty slot. We tell hardware the first 194 * slot it should *not* read. 195 */ 196 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, 197 ring->index_base + 198 (ring->end % BGMAC_TX_RING_SLOTS) * 199 sizeof(struct bgmac_dma_desc)); 200 201 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8) 202 netif_stop_queue(net_dev); 203 204 return NETDEV_TX_OK; 205 206 err_dma: 207 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb), 208 DMA_TO_DEVICE); 209 210 while (i-- > 0) { 211 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS; 212 struct bgmac_slot_info *slot = &ring->slots[index]; 213 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); 214 int len = ctl1 & BGMAC_DESC_CTL1_LEN; 215 216 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE); 217 } 218 219 err_dma_head: 220 netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n", 221 ring->mmio_base); 222 223 err_drop: 224 dev_kfree_skb(skb); 225 net_dev->stats.tx_dropped++; 226 net_dev->stats.tx_errors++; 227 return NETDEV_TX_OK; 228 } 229 230 /* Free transmitted packets */ 231 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 232 { 233 struct device *dma_dev = bgmac->dma_dev; 234 int empty_slot; 235 bool freed = false; 236 unsigned bytes_compl = 0, pkts_compl = 0; 237 238 /* The last slot that hardware didn't consume yet */ 239 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 240 empty_slot &= BGMAC_DMA_TX_STATDPTR; 241 empty_slot -= ring->index_base; 242 empty_slot &= BGMAC_DMA_TX_STATDPTR; 243 empty_slot /= sizeof(struct bgmac_dma_desc); 244 245 while (ring->start != ring->end) { 246 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS; 247 struct bgmac_slot_info *slot = &ring->slots[slot_idx]; 248 u32 ctl0, ctl1; 249 int len; 250 251 if (slot_idx == empty_slot) 252 break; 253 254 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0); 255 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); 256 len = ctl1 & BGMAC_DESC_CTL1_LEN; 257 if (ctl0 & BGMAC_DESC_CTL0_SOF) 258 /* Unmap no longer used buffer */ 259 dma_unmap_single(dma_dev, slot->dma_addr, len, 260 DMA_TO_DEVICE); 261 else 262 dma_unmap_page(dma_dev, slot->dma_addr, len, 263 DMA_TO_DEVICE); 264 265 if (slot->skb) { 266 bgmac->net_dev->stats.tx_bytes += slot->skb->len; 267 bgmac->net_dev->stats.tx_packets++; 268 bytes_compl += slot->skb->len; 269 pkts_compl++; 270 271 /* Free memory! :) */ 272 dev_kfree_skb(slot->skb); 273 slot->skb = NULL; 274 } 275 276 slot->dma_addr = 0; 277 ring->start++; 278 freed = true; 279 } 280 281 if (!pkts_compl) 282 return; 283 284 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); 285 286 if (netif_queue_stopped(bgmac->net_dev)) 287 netif_wake_queue(bgmac->net_dev); 288 } 289 290 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 291 { 292 if (!ring->mmio_base) 293 return; 294 295 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); 296 if (!bgmac_wait_value(bgmac, 297 ring->mmio_base + BGMAC_DMA_RX_STATUS, 298 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, 299 10000)) 300 dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n", 301 ring->mmio_base); 302 } 303 304 static void bgmac_dma_rx_enable(struct bgmac *bgmac, 305 struct bgmac_dma_ring *ring) 306 { 307 u32 ctl; 308 309 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); 310 311 /* preserve ONLY bits 16-17 from current hardware value */ 312 ctl &= BGMAC_DMA_RX_ADDREXT_MASK; 313 314 if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) { 315 ctl &= ~BGMAC_DMA_RX_BL_MASK; 316 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; 317 318 ctl &= ~BGMAC_DMA_RX_PC_MASK; 319 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT; 320 321 ctl &= ~BGMAC_DMA_RX_PT_MASK; 322 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; 323 } 324 ctl |= BGMAC_DMA_RX_ENABLE; 325 ctl |= BGMAC_DMA_RX_PARITY_DISABLE; 326 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; 327 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; 328 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); 329 } 330 331 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, 332 struct bgmac_slot_info *slot) 333 { 334 struct device *dma_dev = bgmac->dma_dev; 335 dma_addr_t dma_addr; 336 struct bgmac_rx_header *rx; 337 void *buf; 338 339 /* Alloc skb */ 340 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE); 341 if (!buf) 342 return -ENOMEM; 343 344 /* Poison - if everything goes fine, hardware will overwrite it */ 345 rx = buf + BGMAC_RX_BUF_OFFSET; 346 rx->len = cpu_to_le16(0xdead); 347 rx->flags = cpu_to_le16(0xbeef); 348 349 /* Map skb for the DMA */ 350 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET, 351 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 352 if (dma_mapping_error(dma_dev, dma_addr)) { 353 netdev_err(bgmac->net_dev, "DMA mapping error\n"); 354 put_page(virt_to_head_page(buf)); 355 return -ENOMEM; 356 } 357 358 /* Update the slot */ 359 slot->buf = buf; 360 slot->dma_addr = dma_addr; 361 362 return 0; 363 } 364 365 static void bgmac_dma_rx_update_index(struct bgmac *bgmac, 366 struct bgmac_dma_ring *ring) 367 { 368 dma_wmb(); 369 370 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, 371 ring->index_base + 372 ring->end * sizeof(struct bgmac_dma_desc)); 373 } 374 375 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, 376 struct bgmac_dma_ring *ring, int desc_idx) 377 { 378 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; 379 u32 ctl0 = 0, ctl1 = 0; 380 381 if (desc_idx == BGMAC_RX_RING_SLOTS - 1) 382 ctl0 |= BGMAC_DESC_CTL0_EOT; 383 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; 384 /* Is there any BGMAC device that requires extension? */ 385 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & 386 * B43_DMA64_DCTL1_ADDREXT_MASK; 387 */ 388 389 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr)); 390 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); 391 dma_desc->ctl0 = cpu_to_le32(ctl0); 392 dma_desc->ctl1 = cpu_to_le32(ctl1); 393 394 ring->end = desc_idx; 395 } 396 397 static void bgmac_dma_rx_poison_buf(struct device *dma_dev, 398 struct bgmac_slot_info *slot) 399 { 400 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 401 402 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, 403 DMA_FROM_DEVICE); 404 rx->len = cpu_to_le16(0xdead); 405 rx->flags = cpu_to_le16(0xbeef); 406 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, 407 DMA_FROM_DEVICE); 408 } 409 410 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 411 int weight) 412 { 413 u32 end_slot; 414 int handled = 0; 415 416 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); 417 end_slot &= BGMAC_DMA_RX_STATDPTR; 418 end_slot -= ring->index_base; 419 end_slot &= BGMAC_DMA_RX_STATDPTR; 420 end_slot /= sizeof(struct bgmac_dma_desc); 421 422 while (ring->start != end_slot) { 423 struct device *dma_dev = bgmac->dma_dev; 424 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 425 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 426 struct sk_buff *skb; 427 void *buf = slot->buf; 428 dma_addr_t dma_addr = slot->dma_addr; 429 u16 len, flags; 430 431 do { 432 /* Prepare new skb as replacement */ 433 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) { 434 bgmac_dma_rx_poison_buf(dma_dev, slot); 435 break; 436 } 437 438 /* Unmap buffer to make it accessible to the CPU */ 439 dma_unmap_single(dma_dev, dma_addr, 440 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 441 442 /* Get info from the header */ 443 len = le16_to_cpu(rx->len); 444 flags = le16_to_cpu(rx->flags); 445 446 /* Check for poison and drop or pass the packet */ 447 if (len == 0xdead && flags == 0xbeef) { 448 netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n", 449 ring->start); 450 put_page(virt_to_head_page(buf)); 451 bgmac->net_dev->stats.rx_errors++; 452 break; 453 } 454 455 if (len > BGMAC_RX_ALLOC_SIZE) { 456 netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n", 457 ring->start); 458 put_page(virt_to_head_page(buf)); 459 bgmac->net_dev->stats.rx_length_errors++; 460 bgmac->net_dev->stats.rx_errors++; 461 break; 462 } 463 464 /* Omit CRC. */ 465 len -= ETH_FCS_LEN; 466 467 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); 468 if (unlikely(!skb)) { 469 netdev_err(bgmac->net_dev, "build_skb failed\n"); 470 put_page(virt_to_head_page(buf)); 471 bgmac->net_dev->stats.rx_errors++; 472 break; 473 } 474 skb_put(skb, BGMAC_RX_FRAME_OFFSET + 475 BGMAC_RX_BUF_OFFSET + len); 476 skb_pull(skb, BGMAC_RX_FRAME_OFFSET + 477 BGMAC_RX_BUF_OFFSET); 478 479 skb_checksum_none_assert(skb); 480 skb->protocol = eth_type_trans(skb, bgmac->net_dev); 481 bgmac->net_dev->stats.rx_bytes += len; 482 bgmac->net_dev->stats.rx_packets++; 483 napi_gro_receive(&bgmac->napi, skb); 484 handled++; 485 } while (0); 486 487 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); 488 489 if (++ring->start >= BGMAC_RX_RING_SLOTS) 490 ring->start = 0; 491 492 if (handled >= weight) /* Should never be greater */ 493 break; 494 } 495 496 bgmac_dma_rx_update_index(bgmac, ring); 497 498 return handled; 499 } 500 501 /* Does ring support unaligned addressing? */ 502 static bool bgmac_dma_unaligned(struct bgmac *bgmac, 503 struct bgmac_dma_ring *ring, 504 enum bgmac_dma_ring_type ring_type) 505 { 506 switch (ring_type) { 507 case BGMAC_DMA_RING_TX: 508 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 509 0xff0); 510 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) 511 return true; 512 break; 513 case BGMAC_DMA_RING_RX: 514 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 515 0xff0); 516 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) 517 return true; 518 break; 519 } 520 return false; 521 } 522 523 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac, 524 struct bgmac_dma_ring *ring) 525 { 526 struct device *dma_dev = bgmac->dma_dev; 527 struct bgmac_dma_desc *dma_desc = ring->cpu_base; 528 struct bgmac_slot_info *slot; 529 int i; 530 531 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) { 532 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN; 533 534 slot = &ring->slots[i]; 535 dev_kfree_skb(slot->skb); 536 537 if (!slot->dma_addr) 538 continue; 539 540 if (slot->skb) 541 dma_unmap_single(dma_dev, slot->dma_addr, 542 len, DMA_TO_DEVICE); 543 else 544 dma_unmap_page(dma_dev, slot->dma_addr, 545 len, DMA_TO_DEVICE); 546 } 547 } 548 549 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac, 550 struct bgmac_dma_ring *ring) 551 { 552 struct device *dma_dev = bgmac->dma_dev; 553 struct bgmac_slot_info *slot; 554 int i; 555 556 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) { 557 slot = &ring->slots[i]; 558 if (!slot->dma_addr) 559 continue; 560 561 dma_unmap_single(dma_dev, slot->dma_addr, 562 BGMAC_RX_BUF_SIZE, 563 DMA_FROM_DEVICE); 564 put_page(virt_to_head_page(slot->buf)); 565 slot->dma_addr = 0; 566 } 567 } 568 569 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, 570 struct bgmac_dma_ring *ring, 571 int num_slots) 572 { 573 struct device *dma_dev = bgmac->dma_dev; 574 int size; 575 576 if (!ring->cpu_base) 577 return; 578 579 /* Free ring of descriptors */ 580 size = num_slots * sizeof(struct bgmac_dma_desc); 581 dma_free_coherent(dma_dev, size, ring->cpu_base, 582 ring->dma_base); 583 } 584 585 static void bgmac_dma_cleanup(struct bgmac *bgmac) 586 { 587 int i; 588 589 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 590 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); 591 592 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 593 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); 594 } 595 596 static void bgmac_dma_free(struct bgmac *bgmac) 597 { 598 int i; 599 600 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 601 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i], 602 BGMAC_TX_RING_SLOTS); 603 604 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 605 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i], 606 BGMAC_RX_RING_SLOTS); 607 } 608 609 static int bgmac_dma_alloc(struct bgmac *bgmac) 610 { 611 struct device *dma_dev = bgmac->dma_dev; 612 struct bgmac_dma_ring *ring; 613 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, 614 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, }; 615 int size; /* ring size: different for Tx and Rx */ 616 int err; 617 int i; 618 619 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); 620 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); 621 622 if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) { 623 dev_err(bgmac->dev, "Core does not report 64-bit DMA\n"); 624 return -ENOTSUPP; 625 } 626 627 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 628 ring = &bgmac->tx_ring[i]; 629 ring->mmio_base = ring_base[i]; 630 631 /* Alloc ring of descriptors */ 632 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc); 633 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 634 &ring->dma_base, 635 GFP_KERNEL); 636 if (!ring->cpu_base) { 637 dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n", 638 ring->mmio_base); 639 goto err_dma_free; 640 } 641 642 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 643 BGMAC_DMA_RING_TX); 644 if (ring->unaligned) 645 ring->index_base = lower_32_bits(ring->dma_base); 646 else 647 ring->index_base = 0; 648 649 /* No need to alloc TX slots yet */ 650 } 651 652 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 653 ring = &bgmac->rx_ring[i]; 654 ring->mmio_base = ring_base[i]; 655 656 /* Alloc ring of descriptors */ 657 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc); 658 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 659 &ring->dma_base, 660 GFP_KERNEL); 661 if (!ring->cpu_base) { 662 dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n", 663 ring->mmio_base); 664 err = -ENOMEM; 665 goto err_dma_free; 666 } 667 668 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 669 BGMAC_DMA_RING_RX); 670 if (ring->unaligned) 671 ring->index_base = lower_32_bits(ring->dma_base); 672 else 673 ring->index_base = 0; 674 } 675 676 return 0; 677 678 err_dma_free: 679 bgmac_dma_free(bgmac); 680 return -ENOMEM; 681 } 682 683 static int bgmac_dma_init(struct bgmac *bgmac) 684 { 685 struct bgmac_dma_ring *ring; 686 int i, err; 687 688 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 689 ring = &bgmac->tx_ring[i]; 690 691 if (!ring->unaligned) 692 bgmac_dma_tx_enable(bgmac, ring); 693 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 694 lower_32_bits(ring->dma_base)); 695 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, 696 upper_32_bits(ring->dma_base)); 697 if (ring->unaligned) 698 bgmac_dma_tx_enable(bgmac, ring); 699 700 ring->start = 0; 701 ring->end = 0; /* Points the slot that should *not* be read */ 702 } 703 704 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 705 int j; 706 707 ring = &bgmac->rx_ring[i]; 708 709 if (!ring->unaligned) 710 bgmac_dma_rx_enable(bgmac, ring); 711 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 712 lower_32_bits(ring->dma_base)); 713 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, 714 upper_32_bits(ring->dma_base)); 715 if (ring->unaligned) 716 bgmac_dma_rx_enable(bgmac, ring); 717 718 ring->start = 0; 719 ring->end = 0; 720 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) { 721 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); 722 if (err) 723 goto error; 724 725 bgmac_dma_rx_setup_desc(bgmac, ring, j); 726 } 727 728 bgmac_dma_rx_update_index(bgmac, ring); 729 } 730 731 return 0; 732 733 error: 734 bgmac_dma_cleanup(bgmac); 735 return err; 736 } 737 738 739 /************************************************** 740 * Chip ops 741 **************************************************/ 742 743 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is 744 * nothing to change? Try if after stabilizng driver. 745 */ 746 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, 747 bool force) 748 { 749 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 750 u32 new_val = (cmdcfg & mask) | set; 751 u32 cmdcfg_sr; 752 753 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) 754 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; 755 else 756 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; 757 758 bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr); 759 udelay(2); 760 761 if (new_val != cmdcfg || force) 762 bgmac_write(bgmac, BGMAC_CMDCFG, new_val); 763 764 bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr); 765 udelay(2); 766 } 767 768 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr) 769 { 770 u32 tmp; 771 772 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 773 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); 774 tmp = (addr[4] << 8) | addr[5]; 775 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); 776 } 777 778 static void bgmac_set_rx_mode(struct net_device *net_dev) 779 { 780 struct bgmac *bgmac = netdev_priv(net_dev); 781 782 if (net_dev->flags & IFF_PROMISC) 783 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true); 784 else 785 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true); 786 } 787 788 #if 0 /* We don't use that regs yet */ 789 static void bgmac_chip_stats_update(struct bgmac *bgmac) 790 { 791 int i; 792 793 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) { 794 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 795 bgmac->mib_tx_regs[i] = 796 bgmac_read(bgmac, 797 BGMAC_TX_GOOD_OCTETS + (i * 4)); 798 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 799 bgmac->mib_rx_regs[i] = 800 bgmac_read(bgmac, 801 BGMAC_RX_GOOD_OCTETS + (i * 4)); 802 } 803 804 /* TODO: what else? how to handle BCM4706? Specs are needed */ 805 } 806 #endif 807 808 static void bgmac_clear_mib(struct bgmac *bgmac) 809 { 810 int i; 811 812 if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB) 813 return; 814 815 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); 816 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 817 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); 818 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 819 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); 820 } 821 822 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ 823 static void bgmac_mac_speed(struct bgmac *bgmac) 824 { 825 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); 826 u32 set = 0; 827 828 switch (bgmac->mac_speed) { 829 case SPEED_10: 830 set |= BGMAC_CMDCFG_ES_10; 831 break; 832 case SPEED_100: 833 set |= BGMAC_CMDCFG_ES_100; 834 break; 835 case SPEED_1000: 836 set |= BGMAC_CMDCFG_ES_1000; 837 break; 838 case SPEED_2500: 839 set |= BGMAC_CMDCFG_ES_2500; 840 break; 841 default: 842 dev_err(bgmac->dev, "Unsupported speed: %d\n", 843 bgmac->mac_speed); 844 } 845 846 if (bgmac->mac_duplex == DUPLEX_HALF) 847 set |= BGMAC_CMDCFG_HD; 848 849 bgmac_cmdcfg_maskset(bgmac, mask, set, true); 850 } 851 852 static void bgmac_miiconfig(struct bgmac *bgmac) 853 { 854 if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) { 855 bgmac_idm_write(bgmac, BCMA_IOCTL, 856 bgmac_idm_read(bgmac, BCMA_IOCTL) | 0x40 | 857 BGMAC_BCMA_IOCTL_SW_CLKEN); 858 bgmac->mac_speed = SPEED_2500; 859 bgmac->mac_duplex = DUPLEX_FULL; 860 bgmac_mac_speed(bgmac); 861 } else { 862 u8 imode; 863 864 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & 865 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; 866 if (imode == 0 || imode == 1) { 867 bgmac->mac_speed = SPEED_100; 868 bgmac->mac_duplex = DUPLEX_FULL; 869 bgmac_mac_speed(bgmac); 870 } 871 } 872 } 873 874 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ 875 static void bgmac_chip_reset(struct bgmac *bgmac) 876 { 877 u32 cmdcfg_sr; 878 u32 iost; 879 int i; 880 881 if (bgmac_clk_enabled(bgmac)) { 882 if (!bgmac->stats_grabbed) { 883 /* bgmac_chip_stats_update(bgmac); */ 884 bgmac->stats_grabbed = true; 885 } 886 887 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 888 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); 889 890 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 891 udelay(1); 892 893 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 894 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); 895 896 /* TODO: Clear software multicast filter list */ 897 } 898 899 iost = bgmac_idm_read(bgmac, BCMA_IOST); 900 if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED) 901 iost &= ~BGMAC_BCMA_IOST_ATTACHED; 902 903 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */ 904 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) { 905 u32 flags = 0; 906 if (iost & BGMAC_BCMA_IOST_ATTACHED) { 907 flags = BGMAC_BCMA_IOCTL_SW_CLKEN; 908 if (!bgmac->has_robosw) 909 flags |= BGMAC_BCMA_IOCTL_SW_RESET; 910 } 911 bgmac_clk_enable(bgmac, flags); 912 } 913 914 /* Request Misc PLL for corerev > 2 */ 915 if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) { 916 bgmac_set(bgmac, BCMA_CLKCTLST, 917 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); 918 bgmac_wait_value(bgmac, BCMA_CLKCTLST, 919 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 920 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 921 1000); 922 } 923 924 if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) { 925 u8 et_swtype = 0; 926 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | 927 BGMAC_CHIPCTL_1_IF_TYPE_MII; 928 char buf[4]; 929 930 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 931 if (kstrtou8(buf, 0, &et_swtype)) 932 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n", 933 buf); 934 et_swtype &= 0x0f; 935 et_swtype <<= 4; 936 sw_type = et_swtype; 937 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) { 938 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RMII | 939 BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; 940 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) { 941 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | 942 BGMAC_CHIPCTL_1_SW_TYPE_RGMII; 943 } 944 bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | 945 BGMAC_CHIPCTL_1_SW_TYPE_MASK), 946 sw_type); 947 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE) { 948 u32 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_MII | 949 BGMAC_CHIPCTL_4_SW_TYPE_EPHY; 950 u8 et_swtype = 0; 951 char buf[4]; 952 953 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 954 if (kstrtou8(buf, 0, &et_swtype)) 955 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n", 956 buf); 957 sw_type = (et_swtype & 0x0f) << 12; 958 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII) { 959 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_RGMII | 960 BGMAC_CHIPCTL_4_SW_TYPE_RGMII; 961 } 962 bgmac_cco_ctl_maskset(bgmac, 4, ~(BGMAC_CHIPCTL_4_IF_TYPE_MASK | 963 BGMAC_CHIPCTL_4_SW_TYPE_MASK), 964 sw_type); 965 } else if (bgmac->feature_flags & BGMAC_FEAT_CC7_IF_TYPE_RGMII) { 966 bgmac_cco_ctl_maskset(bgmac, 7, ~BGMAC_CHIPCTL_7_IF_TYPE_MASK, 967 BGMAC_CHIPCTL_7_IF_TYPE_RGMII); 968 } 969 970 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) 971 bgmac_idm_write(bgmac, BCMA_IOCTL, 972 bgmac_idm_read(bgmac, BCMA_IOCTL) & 973 ~BGMAC_BCMA_IOCTL_SW_RESET); 974 975 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset 976 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine 977 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to 978 * be keps until taking MAC out of the reset. 979 */ 980 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) 981 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; 982 else 983 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; 984 985 bgmac_cmdcfg_maskset(bgmac, 986 ~(BGMAC_CMDCFG_TE | 987 BGMAC_CMDCFG_RE | 988 BGMAC_CMDCFG_RPI | 989 BGMAC_CMDCFG_TAI | 990 BGMAC_CMDCFG_HD | 991 BGMAC_CMDCFG_ML | 992 BGMAC_CMDCFG_CFE | 993 BGMAC_CMDCFG_RL | 994 BGMAC_CMDCFG_RED | 995 BGMAC_CMDCFG_PE | 996 BGMAC_CMDCFG_TPI | 997 BGMAC_CMDCFG_PAD_EN | 998 BGMAC_CMDCFG_PF), 999 BGMAC_CMDCFG_PROM | 1000 BGMAC_CMDCFG_NLC | 1001 BGMAC_CMDCFG_CFE | 1002 cmdcfg_sr, 1003 false); 1004 bgmac->mac_speed = SPEED_UNKNOWN; 1005 bgmac->mac_duplex = DUPLEX_UNKNOWN; 1006 1007 bgmac_clear_mib(bgmac); 1008 if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL) 1009 bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0, 1010 BCMA_GMAC_CMN_PC_MTE); 1011 else 1012 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); 1013 bgmac_miiconfig(bgmac); 1014 if (bgmac->mii_bus) 1015 bgmac->mii_bus->reset(bgmac->mii_bus); 1016 1017 netdev_reset_queue(bgmac->net_dev); 1018 } 1019 1020 static void bgmac_chip_intrs_on(struct bgmac *bgmac) 1021 { 1022 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); 1023 } 1024 1025 static void bgmac_chip_intrs_off(struct bgmac *bgmac) 1026 { 1027 bgmac_write(bgmac, BGMAC_INT_MASK, 0); 1028 bgmac_read(bgmac, BGMAC_INT_MASK); 1029 } 1030 1031 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ 1032 static void bgmac_enable(struct bgmac *bgmac) 1033 { 1034 u32 cmdcfg_sr; 1035 u32 cmdcfg; 1036 u32 mode; 1037 1038 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) 1039 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; 1040 else 1041 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; 1042 1043 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 1044 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), 1045 cmdcfg_sr, true); 1046 udelay(2); 1047 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; 1048 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); 1049 1050 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 1051 BGMAC_DS_MM_SHIFT; 1052 if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0) 1053 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 1054 if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) && mode == 2) 1055 bgmac_cco_ctl_maskset(bgmac, 1, ~0, 1056 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); 1057 1058 if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 | 1059 BGMAC_FEAT_FLW_CTRL2)) { 1060 u32 fl_ctl; 1061 1062 if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1) 1063 fl_ctl = 0x2300e1; 1064 else 1065 fl_ctl = 0x03cb04cb; 1066 1067 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); 1068 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); 1069 } 1070 1071 if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) { 1072 u32 rxq_ctl; 1073 u16 bp_clk; 1074 u8 mdp; 1075 1076 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); 1077 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; 1078 bp_clk = bgmac_get_bus_clock(bgmac) / 1000000; 1079 mdp = (bp_clk * 128 / 1000) - 3; 1080 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); 1081 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); 1082 } 1083 } 1084 1085 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ 1086 static void bgmac_chip_init(struct bgmac *bgmac) 1087 { 1088 /* Clear any erroneously pending interrupts */ 1089 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); 1090 1091 /* 1 interrupt per received frame */ 1092 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); 1093 1094 /* Enable 802.3x tx flow control (honor received PAUSE frames) */ 1095 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); 1096 1097 bgmac_set_rx_mode(bgmac->net_dev); 1098 1099 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr); 1100 1101 if (bgmac->loopback) 1102 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1103 else 1104 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false); 1105 1106 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); 1107 1108 bgmac_chip_intrs_on(bgmac); 1109 1110 bgmac_enable(bgmac); 1111 } 1112 1113 static irqreturn_t bgmac_interrupt(int irq, void *dev_id) 1114 { 1115 struct bgmac *bgmac = netdev_priv(dev_id); 1116 1117 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); 1118 int_status &= bgmac->int_mask; 1119 1120 if (!int_status) 1121 return IRQ_NONE; 1122 1123 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX); 1124 if (int_status) 1125 dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status); 1126 1127 /* Disable new interrupts until handling existing ones */ 1128 bgmac_chip_intrs_off(bgmac); 1129 1130 napi_schedule(&bgmac->napi); 1131 1132 return IRQ_HANDLED; 1133 } 1134 1135 static int bgmac_poll(struct napi_struct *napi, int weight) 1136 { 1137 struct bgmac *bgmac = container_of(napi, struct bgmac, napi); 1138 int handled = 0; 1139 1140 /* Ack */ 1141 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); 1142 1143 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]); 1144 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight); 1145 1146 /* Poll again if more events arrived in the meantime */ 1147 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX)) 1148 return weight; 1149 1150 if (handled < weight) { 1151 napi_complete(napi); 1152 bgmac_chip_intrs_on(bgmac); 1153 } 1154 1155 return handled; 1156 } 1157 1158 /************************************************** 1159 * net_device_ops 1160 **************************************************/ 1161 1162 static int bgmac_open(struct net_device *net_dev) 1163 { 1164 struct bgmac *bgmac = netdev_priv(net_dev); 1165 int err = 0; 1166 1167 bgmac_chip_reset(bgmac); 1168 1169 err = bgmac_dma_init(bgmac); 1170 if (err) 1171 return err; 1172 1173 /* Specs say about reclaiming rings here, but we do that in DMA init */ 1174 bgmac_chip_init(bgmac); 1175 1176 err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED, 1177 KBUILD_MODNAME, net_dev); 1178 if (err < 0) { 1179 dev_err(bgmac->dev, "IRQ request error: %d!\n", err); 1180 bgmac_dma_cleanup(bgmac); 1181 return err; 1182 } 1183 napi_enable(&bgmac->napi); 1184 1185 phy_start(net_dev->phydev); 1186 1187 netif_start_queue(net_dev); 1188 1189 return 0; 1190 } 1191 1192 static int bgmac_stop(struct net_device *net_dev) 1193 { 1194 struct bgmac *bgmac = netdev_priv(net_dev); 1195 1196 netif_carrier_off(net_dev); 1197 1198 phy_stop(net_dev->phydev); 1199 1200 napi_disable(&bgmac->napi); 1201 bgmac_chip_intrs_off(bgmac); 1202 free_irq(bgmac->irq, net_dev); 1203 1204 bgmac_chip_reset(bgmac); 1205 bgmac_dma_cleanup(bgmac); 1206 1207 return 0; 1208 } 1209 1210 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, 1211 struct net_device *net_dev) 1212 { 1213 struct bgmac *bgmac = netdev_priv(net_dev); 1214 struct bgmac_dma_ring *ring; 1215 1216 /* No QOS support yet */ 1217 ring = &bgmac->tx_ring[0]; 1218 return bgmac_dma_tx_add(bgmac, ring, skb); 1219 } 1220 1221 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr) 1222 { 1223 struct bgmac *bgmac = netdev_priv(net_dev); 1224 int ret; 1225 1226 ret = eth_prepare_mac_addr_change(net_dev, addr); 1227 if (ret < 0) 1228 return ret; 1229 bgmac_write_mac_address(bgmac, (u8 *)addr); 1230 eth_commit_mac_addr_change(net_dev, addr); 1231 return 0; 1232 } 1233 1234 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1235 { 1236 if (!netif_running(net_dev)) 1237 return -EINVAL; 1238 1239 return phy_mii_ioctl(net_dev->phydev, ifr, cmd); 1240 } 1241 1242 static const struct net_device_ops bgmac_netdev_ops = { 1243 .ndo_open = bgmac_open, 1244 .ndo_stop = bgmac_stop, 1245 .ndo_start_xmit = bgmac_start_xmit, 1246 .ndo_set_rx_mode = bgmac_set_rx_mode, 1247 .ndo_set_mac_address = bgmac_set_mac_address, 1248 .ndo_validate_addr = eth_validate_addr, 1249 .ndo_do_ioctl = bgmac_ioctl, 1250 }; 1251 1252 /************************************************** 1253 * ethtool_ops 1254 **************************************************/ 1255 1256 struct bgmac_stat { 1257 u8 size; 1258 u32 offset; 1259 const char *name; 1260 }; 1261 1262 static struct bgmac_stat bgmac_get_strings_stats[] = { 1263 { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" }, 1264 { 4, BGMAC_TX_GOOD_PKTS, "tx_good" }, 1265 { 8, BGMAC_TX_OCTETS, "tx_octets" }, 1266 { 4, BGMAC_TX_PKTS, "tx_pkts" }, 1267 { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" }, 1268 { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" }, 1269 { 4, BGMAC_TX_LEN_64, "tx_64" }, 1270 { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" }, 1271 { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" }, 1272 { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" }, 1273 { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" }, 1274 { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" }, 1275 { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" }, 1276 { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" }, 1277 { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" }, 1278 { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" }, 1279 { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" }, 1280 { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" }, 1281 { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" }, 1282 { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" }, 1283 { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" }, 1284 { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" }, 1285 { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" }, 1286 { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" }, 1287 { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" }, 1288 { 4, BGMAC_TX_DEFERED, "tx_defered" }, 1289 { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" }, 1290 { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" }, 1291 { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" }, 1292 { 4, BGMAC_TX_Q0_PKTS, "tx_q0" }, 1293 { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" }, 1294 { 4, BGMAC_TX_Q1_PKTS, "tx_q1" }, 1295 { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" }, 1296 { 4, BGMAC_TX_Q2_PKTS, "tx_q2" }, 1297 { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" }, 1298 { 4, BGMAC_TX_Q3_PKTS, "tx_q3" }, 1299 { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" }, 1300 { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" }, 1301 { 4, BGMAC_RX_GOOD_PKTS, "rx_good" }, 1302 { 8, BGMAC_RX_OCTETS, "rx_octets" }, 1303 { 4, BGMAC_RX_PKTS, "rx_pkts" }, 1304 { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" }, 1305 { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" }, 1306 { 4, BGMAC_RX_LEN_64, "rx_64" }, 1307 { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" }, 1308 { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" }, 1309 { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" }, 1310 { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" }, 1311 { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" }, 1312 { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" }, 1313 { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" }, 1314 { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" }, 1315 { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" }, 1316 { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" }, 1317 { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" }, 1318 { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" }, 1319 { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" }, 1320 { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" }, 1321 { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" }, 1322 { 4, BGMAC_RX_CRC_ERRS, "rx_crc" }, 1323 { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" }, 1324 { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" }, 1325 { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" }, 1326 { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" }, 1327 { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" }, 1328 { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" }, 1329 }; 1330 1331 #define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats) 1332 1333 static int bgmac_get_sset_count(struct net_device *dev, int string_set) 1334 { 1335 switch (string_set) { 1336 case ETH_SS_STATS: 1337 return BGMAC_STATS_LEN; 1338 } 1339 1340 return -EOPNOTSUPP; 1341 } 1342 1343 static void bgmac_get_strings(struct net_device *dev, u32 stringset, 1344 u8 *data) 1345 { 1346 int i; 1347 1348 if (stringset != ETH_SS_STATS) 1349 return; 1350 1351 for (i = 0; i < BGMAC_STATS_LEN; i++) 1352 strlcpy(data + i * ETH_GSTRING_LEN, 1353 bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN); 1354 } 1355 1356 static void bgmac_get_ethtool_stats(struct net_device *dev, 1357 struct ethtool_stats *ss, uint64_t *data) 1358 { 1359 struct bgmac *bgmac = netdev_priv(dev); 1360 const struct bgmac_stat *s; 1361 unsigned int i; 1362 u64 val; 1363 1364 if (!netif_running(dev)) 1365 return; 1366 1367 for (i = 0; i < BGMAC_STATS_LEN; i++) { 1368 s = &bgmac_get_strings_stats[i]; 1369 val = 0; 1370 if (s->size == 8) 1371 val = (u64)bgmac_read(bgmac, s->offset + 4) << 32; 1372 val |= bgmac_read(bgmac, s->offset); 1373 data[i] = val; 1374 } 1375 } 1376 1377 static void bgmac_get_drvinfo(struct net_device *net_dev, 1378 struct ethtool_drvinfo *info) 1379 { 1380 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1381 strlcpy(info->bus_info, "AXI", sizeof(info->bus_info)); 1382 } 1383 1384 static const struct ethtool_ops bgmac_ethtool_ops = { 1385 .get_strings = bgmac_get_strings, 1386 .get_sset_count = bgmac_get_sset_count, 1387 .get_ethtool_stats = bgmac_get_ethtool_stats, 1388 .get_drvinfo = bgmac_get_drvinfo, 1389 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1390 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1391 }; 1392 1393 /************************************************** 1394 * MII 1395 **************************************************/ 1396 1397 void bgmac_adjust_link(struct net_device *net_dev) 1398 { 1399 struct bgmac *bgmac = netdev_priv(net_dev); 1400 struct phy_device *phy_dev = net_dev->phydev; 1401 bool update = false; 1402 1403 if (phy_dev->link) { 1404 if (phy_dev->speed != bgmac->mac_speed) { 1405 bgmac->mac_speed = phy_dev->speed; 1406 update = true; 1407 } 1408 1409 if (phy_dev->duplex != bgmac->mac_duplex) { 1410 bgmac->mac_duplex = phy_dev->duplex; 1411 update = true; 1412 } 1413 } 1414 1415 if (update) { 1416 bgmac_mac_speed(bgmac); 1417 phy_print_status(phy_dev); 1418 } 1419 } 1420 EXPORT_SYMBOL_GPL(bgmac_adjust_link); 1421 1422 int bgmac_phy_connect_direct(struct bgmac *bgmac) 1423 { 1424 struct fixed_phy_status fphy_status = { 1425 .link = 1, 1426 .speed = SPEED_1000, 1427 .duplex = DUPLEX_FULL, 1428 }; 1429 struct phy_device *phy_dev; 1430 int err; 1431 1432 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); 1433 if (!phy_dev || IS_ERR(phy_dev)) { 1434 dev_err(bgmac->dev, "Failed to register fixed PHY device\n"); 1435 return -ENODEV; 1436 } 1437 1438 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link, 1439 PHY_INTERFACE_MODE_MII); 1440 if (err) { 1441 dev_err(bgmac->dev, "Connecting PHY failed\n"); 1442 return err; 1443 } 1444 1445 return err; 1446 } 1447 EXPORT_SYMBOL_GPL(bgmac_phy_connect_direct); 1448 1449 int bgmac_enet_probe(struct bgmac *info) 1450 { 1451 struct net_device *net_dev; 1452 struct bgmac *bgmac; 1453 int err; 1454 1455 /* Allocation and references */ 1456 net_dev = alloc_etherdev(sizeof(*bgmac)); 1457 if (!net_dev) 1458 return -ENOMEM; 1459 1460 net_dev->netdev_ops = &bgmac_netdev_ops; 1461 net_dev->ethtool_ops = &bgmac_ethtool_ops; 1462 bgmac = netdev_priv(net_dev); 1463 memcpy(bgmac, info, sizeof(*bgmac)); 1464 bgmac->net_dev = net_dev; 1465 net_dev->irq = bgmac->irq; 1466 SET_NETDEV_DEV(net_dev, bgmac->dev); 1467 1468 if (!is_valid_ether_addr(bgmac->mac_addr)) { 1469 dev_err(bgmac->dev, "Invalid MAC addr: %pM\n", 1470 bgmac->mac_addr); 1471 eth_random_addr(bgmac->mac_addr); 1472 dev_warn(bgmac->dev, "Using random MAC: %pM\n", 1473 bgmac->mac_addr); 1474 } 1475 ether_addr_copy(net_dev->dev_addr, bgmac->mac_addr); 1476 1477 /* This (reset &) enable is not preset in specs or reference driver but 1478 * Broadcom does it in arch PCI code when enabling fake PCI device. 1479 */ 1480 bgmac_clk_enable(bgmac, 0); 1481 1482 /* This seems to be fixing IRQ by assigning OOB #6 to the core */ 1483 if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6) 1484 bgmac_idm_write(bgmac, BCMA_OOB_SEL_OUT_A30, 0x86); 1485 1486 bgmac_chip_reset(bgmac); 1487 1488 err = bgmac_dma_alloc(bgmac); 1489 if (err) { 1490 dev_err(bgmac->dev, "Unable to alloc memory for DMA\n"); 1491 goto err_netdev_free; 1492 } 1493 1494 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; 1495 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0) 1496 bgmac->int_mask &= ~BGMAC_IS_TX_MASK; 1497 1498 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); 1499 1500 err = bgmac_phy_connect(bgmac); 1501 if (err) { 1502 dev_err(bgmac->dev, "Cannot connect to phy\n"); 1503 goto err_dma_free; 1504 } 1505 1506 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1507 net_dev->hw_features = net_dev->features; 1508 net_dev->vlan_features = net_dev->features; 1509 1510 err = register_netdev(bgmac->net_dev); 1511 if (err) { 1512 dev_err(bgmac->dev, "Cannot register net device\n"); 1513 goto err_phy_disconnect; 1514 } 1515 1516 netif_carrier_off(net_dev); 1517 1518 return 0; 1519 1520 err_phy_disconnect: 1521 phy_disconnect(net_dev->phydev); 1522 err_dma_free: 1523 bgmac_dma_free(bgmac); 1524 err_netdev_free: 1525 free_netdev(net_dev); 1526 1527 return err; 1528 } 1529 EXPORT_SYMBOL_GPL(bgmac_enet_probe); 1530 1531 void bgmac_enet_remove(struct bgmac *bgmac) 1532 { 1533 unregister_netdev(bgmac->net_dev); 1534 phy_disconnect(bgmac->net_dev->phydev); 1535 netif_napi_del(&bgmac->napi); 1536 bgmac_dma_free(bgmac); 1537 free_netdev(bgmac->net_dev); 1538 } 1539 EXPORT_SYMBOL_GPL(bgmac_enet_remove); 1540 1541 MODULE_AUTHOR("Rafał Miłecki"); 1542 MODULE_LICENSE("GPL"); 1543