1 /* 2 * Broadcom BCM7xxx System Port Ethernet MAC driver 3 * 4 * Copyright (C) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef __BCM_SYSPORT_H 12 #define __BCM_SYSPORT_H 13 14 #include <linux/if_vlan.h> 15 16 /* Receive/transmit descriptor format */ 17 #define DESC_ADDR_HI_STATUS_LEN 0x00 18 #define DESC_ADDR_HI_SHIFT 0 19 #define DESC_ADDR_HI_MASK 0xff 20 #define DESC_STATUS_SHIFT 8 21 #define DESC_STATUS_MASK 0x3ff 22 #define DESC_LEN_SHIFT 18 23 #define DESC_LEN_MASK 0x7fff 24 #define DESC_ADDR_LO 0x04 25 26 /* HW supports 40-bit addressing hence the */ 27 #define DESC_SIZE (WORDS_PER_DESC * sizeof(u32)) 28 29 /* Default RX buffer allocation size */ 30 #define RX_BUF_LENGTH 2048 31 32 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(4) + FCS(4) = 1526. 33 * 1536 is multiple of 256 bytes 34 */ 35 #define ENET_BRCM_TAG_LEN 4 36 #define ENET_PAD 10 37 #define UMAC_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ 38 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) 39 40 /* Transmit status block */ 41 struct bcm_tsb { 42 u32 pcp_dei_vid; 43 #define PCP_DEI_MASK 0xf 44 #define VID_SHIFT 4 45 #define VID_MASK 0xfff 46 u32 l4_ptr_dest_map; 47 #define L4_CSUM_PTR_MASK 0x1ff 48 #define L4_PTR_SHIFT 9 49 #define L4_PTR_MASK 0x1ff 50 #define L4_UDP (1 << 18) 51 #define L4_LENGTH_VALID (1 << 19) 52 #define DEST_MAP_SHIFT 20 53 #define DEST_MAP_MASK 0x1ff 54 }; 55 56 /* Receive status block uses the same 57 * definitions as the DMA descriptor 58 */ 59 struct bcm_rsb { 60 u32 rx_status_len; 61 u32 brcm_egress_tag; 62 }; 63 64 /* Common Receive/Transmit status bits */ 65 #define DESC_L4_CSUM (1 << 7) 66 #define DESC_SOP (1 << 8) 67 #define DESC_EOP (1 << 9) 68 69 /* Receive Status bits */ 70 #define RX_STATUS_UCAST 0 71 #define RX_STATUS_BCAST 0x04 72 #define RX_STATUS_MCAST 0x08 73 #define RX_STATUS_L2_MCAST 0x0c 74 #define RX_STATUS_ERR (1 << 4) 75 #define RX_STATUS_OVFLOW (1 << 5) 76 #define RX_STATUS_PARSE_FAIL (1 << 6) 77 78 /* Transmit Status bits */ 79 #define TX_STATUS_VLAN_NO_ACT 0x00 80 #define TX_STATUS_VLAN_PCP_TSB 0x01 81 #define TX_STATUS_VLAN_QUEUE 0x02 82 #define TX_STATUS_VLAN_VID_TSB 0x03 83 #define TX_STATUS_OWR_CRC (1 << 2) 84 #define TX_STATUS_APP_CRC (1 << 3) 85 #define TX_STATUS_BRCM_TAG_NO_ACT 0 86 #define TX_STATUS_BRCM_TAG_ZERO 0x10 87 #define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20 88 #define TX_STATUS_BRCM_TAG_ONE_TSB 0x30 89 #define TX_STATUS_SKIP_BYTES (1 << 6) 90 91 /* Specific register definitions */ 92 #define SYS_PORT_TOPCTRL_OFFSET 0 93 #define REV_CNTL 0x00 94 #define REV_MASK 0xffff 95 96 #define RX_FLUSH_CNTL 0x04 97 #define RX_FLUSH (1 << 0) 98 99 #define TX_FLUSH_CNTL 0x08 100 #define TX_FLUSH (1 << 0) 101 102 #define MISC_CNTL 0x0c 103 #define SYS_CLK_SEL (1 << 0) 104 #define TDMA_EOP_SEL (1 << 1) 105 106 /* Level-2 Interrupt controller offsets and defines */ 107 #define SYS_PORT_INTRL2_0_OFFSET 0x200 108 #define SYS_PORT_INTRL2_1_OFFSET 0x240 109 #define INTRL2_CPU_STATUS 0x00 110 #define INTRL2_CPU_SET 0x04 111 #define INTRL2_CPU_CLEAR 0x08 112 #define INTRL2_CPU_MASK_STATUS 0x0c 113 #define INTRL2_CPU_MASK_SET 0x10 114 #define INTRL2_CPU_MASK_CLEAR 0x14 115 116 /* Level-2 instance 0 interrupt bits */ 117 #define INTRL2_0_GISB_ERR (1 << 0) 118 #define INTRL2_0_RBUF_OVFLOW (1 << 1) 119 #define INTRL2_0_TBUF_UNDFLOW (1 << 2) 120 #define INTRL2_0_MPD (1 << 3) 121 #define INTRL2_0_BRCM_MATCH_TAG (1 << 4) 122 #define INTRL2_0_RDMA_MBDONE (1 << 5) 123 #define INTRL2_0_OVER_MAX_THRESH (1 << 6) 124 #define INTRL2_0_BELOW_HYST_THRESH (1 << 7) 125 #define INTRL2_0_FREE_LIST_EMPTY (1 << 8) 126 #define INTRL2_0_TX_RING_FULL (1 << 9) 127 #define INTRL2_0_DESC_ALLOC_ERR (1 << 10) 128 #define INTRL2_0_UNEXP_PKTSIZE_ACK (1 << 11) 129 130 /* RXCHK offset and defines */ 131 #define SYS_PORT_RXCHK_OFFSET 0x300 132 133 #define RXCHK_CONTROL 0x00 134 #define RXCHK_EN (1 << 0) 135 #define RXCHK_SKIP_FCS (1 << 1) 136 #define RXCHK_BAD_CSUM_DIS (1 << 2) 137 #define RXCHK_BRCM_TAG_EN (1 << 3) 138 #define RXCHK_BRCM_TAG_MATCH_SHIFT 4 139 #define RXCHK_BRCM_TAG_MATCH_MASK 0xff 140 #define RXCHK_PARSE_TNL (1 << 12) 141 #define RXCHK_VIOL_EN (1 << 13) 142 #define RXCHK_VIOL_DIS (1 << 14) 143 #define RXCHK_INCOM_PKT (1 << 15) 144 #define RXCHK_V6_DUPEXT_EN (1 << 16) 145 #define RXCHK_V6_DUPEXT_DIS (1 << 17) 146 #define RXCHK_ETHERTYPE_DIS (1 << 18) 147 #define RXCHK_L2_HDR_DIS (1 << 19) 148 #define RXCHK_L3_HDR_DIS (1 << 20) 149 #define RXCHK_MAC_RX_ERR_DIS (1 << 21) 150 #define RXCHK_PARSE_AUTH (1 << 22) 151 152 #define RXCHK_BRCM_TAG0 0x04 153 #define RXCHK_BRCM_TAG(i) ((i) * RXCHK_BRCM_TAG0) 154 #define RXCHK_BRCM_TAG0_MASK 0x24 155 #define RXCHK_BRCM_TAG_MASK(i) ((i) * RXCHK_BRCM_TAG0_MASK) 156 #define RXCHK_BRCM_TAG_MATCH_STATUS 0x44 157 #define RXCHK_ETHERTYPE 0x48 158 #define RXCHK_BAD_CSUM_CNTR 0x4C 159 #define RXCHK_OTHER_DISC_CNTR 0x50 160 161 /* TXCHCK offsets and defines */ 162 #define SYS_PORT_TXCHK_OFFSET 0x380 163 #define TXCHK_PKT_RDY_THRESH 0x00 164 165 /* Receive buffer offset and defines */ 166 #define SYS_PORT_RBUF_OFFSET 0x400 167 168 #define RBUF_CONTROL 0x00 169 #define RBUF_RSB_EN (1 << 0) 170 #define RBUF_4B_ALGN (1 << 1) 171 #define RBUF_BRCM_TAG_STRIP (1 << 2) 172 #define RBUF_BAD_PKT_DISC (1 << 3) 173 #define RBUF_RESUME_THRESH_SHIFT 4 174 #define RBUF_RESUME_THRESH_MASK 0xff 175 #define RBUF_OK_TO_SEND_SHIFT 12 176 #define RBUF_OK_TO_SEND_MASK 0xff 177 #define RBUF_CRC_REPLACE (1 << 20) 178 #define RBUF_OK_TO_SEND_MODE (1 << 21) 179 #define RBUF_RSB_SWAP (1 << 22) 180 #define RBUF_ACPI_EN (1 << 23) 181 182 #define RBUF_PKT_RDY_THRESH 0x04 183 184 #define RBUF_STATUS 0x08 185 #define RBUF_WOL_MODE (1 << 0) 186 #define RBUF_MPD (1 << 1) 187 #define RBUF_ACPI (1 << 2) 188 189 #define RBUF_OVFL_DISC_CNTR 0x0c 190 #define RBUF_ERR_PKT_CNTR 0x10 191 192 /* Transmit buffer offset and defines */ 193 #define SYS_PORT_TBUF_OFFSET 0x600 194 195 #define TBUF_CONTROL 0x00 196 #define TBUF_BP_EN (1 << 0) 197 #define TBUF_MAX_PKT_THRESH_SHIFT 1 198 #define TBUF_MAX_PKT_THRESH_MASK 0x1f 199 #define TBUF_FULL_THRESH_SHIFT 8 200 #define TBUF_FULL_THRESH_MASK 0x1f 201 202 /* UniMAC offset and defines */ 203 #define SYS_PORT_UMAC_OFFSET 0x800 204 205 #define UMAC_CMD 0x008 206 #define CMD_TX_EN (1 << 0) 207 #define CMD_RX_EN (1 << 1) 208 #define CMD_SPEED_SHIFT 2 209 #define CMD_SPEED_10 0 210 #define CMD_SPEED_100 1 211 #define CMD_SPEED_1000 2 212 #define CMD_SPEED_2500 3 213 #define CMD_SPEED_MASK 3 214 #define CMD_PROMISC (1 << 4) 215 #define CMD_PAD_EN (1 << 5) 216 #define CMD_CRC_FWD (1 << 6) 217 #define CMD_PAUSE_FWD (1 << 7) 218 #define CMD_RX_PAUSE_IGNORE (1 << 8) 219 #define CMD_TX_ADDR_INS (1 << 9) 220 #define CMD_HD_EN (1 << 10) 221 #define CMD_SW_RESET (1 << 13) 222 #define CMD_LCL_LOOP_EN (1 << 15) 223 #define CMD_AUTO_CONFIG (1 << 22) 224 #define CMD_CNTL_FRM_EN (1 << 23) 225 #define CMD_NO_LEN_CHK (1 << 24) 226 #define CMD_RMT_LOOP_EN (1 << 25) 227 #define CMD_PRBL_EN (1 << 27) 228 #define CMD_TX_PAUSE_IGNORE (1 << 28) 229 #define CMD_TX_RX_EN (1 << 29) 230 #define CMD_RUNT_FILTER_DIS (1 << 30) 231 232 #define UMAC_MAC0 0x00c 233 #define UMAC_MAC1 0x010 234 #define UMAC_MAX_FRAME_LEN 0x014 235 236 #define UMAC_TX_FLUSH 0x334 237 238 #define UMAC_MIB_START 0x400 239 240 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 241 * between the end of TX stats and the beginning of the RX RUNT 242 */ 243 #define UMAC_MIB_STAT_OFFSET 0xc 244 245 #define UMAC_MIB_CTRL 0x580 246 #define MIB_RX_CNT_RST (1 << 0) 247 #define MIB_RUNT_CNT_RST (1 << 1) 248 #define MIB_TX_CNT_RST (1 << 2) 249 #define UMAC_MDF_CTRL 0x650 250 #define UMAC_MDF_ADDR 0x654 251 252 /* Receive DMA offset and defines */ 253 #define SYS_PORT_RDMA_OFFSET 0x2000 254 255 #define RDMA_CONTROL 0x1000 256 #define RDMA_EN (1 << 0) 257 #define RDMA_RING_CFG (1 << 1) 258 #define RDMA_DISC_EN (1 << 2) 259 #define RDMA_BUF_DATA_OFFSET_SHIFT 4 260 #define RDMA_BUF_DATA_OFFSET_MASK 0x3ff 261 262 #define RDMA_STATUS 0x1004 263 #define RDMA_DISABLED (1 << 0) 264 #define RDMA_DESC_RAM_INIT_BUSY (1 << 1) 265 #define RDMA_BP_STATUS (1 << 2) 266 267 #define RDMA_SCB_BURST_SIZE 0x1008 268 269 #define RDMA_RING_BUF_SIZE 0x100c 270 #define RDMA_RING_SIZE_SHIFT 16 271 272 #define RDMA_WRITE_PTR_HI 0x1010 273 #define RDMA_WRITE_PTR_LO 0x1014 274 #define RDMA_PROD_INDEX 0x1018 275 #define RDMA_PROD_INDEX_MASK 0xffff 276 277 #define RDMA_CONS_INDEX 0x101c 278 #define RDMA_CONS_INDEX_MASK 0xffff 279 280 #define RDMA_START_ADDR_HI 0x1020 281 #define RDMA_START_ADDR_LO 0x1024 282 #define RDMA_END_ADDR_HI 0x1028 283 #define RDMA_END_ADDR_LO 0x102c 284 285 #define RDMA_MBDONE_INTR 0x1030 286 #define RDMA_INTR_THRESH_MASK 0xff 287 #define RDMA_TIMEOUT_SHIFT 16 288 #define RDMA_TIMEOUT_MASK 0xffff 289 290 #define RDMA_XON_XOFF_THRESH 0x1034 291 #define RDMA_XON_XOFF_THRESH_MASK 0xffff 292 #define RDMA_XOFF_THRESH_SHIFT 16 293 294 #define RDMA_READ_PTR_HI 0x1038 295 #define RDMA_READ_PTR_LO 0x103c 296 297 #define RDMA_OVERRIDE 0x1040 298 #define RDMA_LE_MODE (1 << 0) 299 #define RDMA_REG_MODE (1 << 1) 300 301 #define RDMA_TEST 0x1044 302 #define RDMA_TP_OUT_SEL (1 << 0) 303 #define RDMA_MEM_SEL (1 << 1) 304 305 #define RDMA_DEBUG 0x1048 306 307 /* Transmit DMA offset and defines */ 308 #define TDMA_NUM_RINGS 32 /* rings = queues */ 309 #define TDMA_PORT_SIZE DESC_SIZE /* two 32-bits words */ 310 311 #define SYS_PORT_TDMA_OFFSET 0x4000 312 #define TDMA_WRITE_PORT_OFFSET 0x0000 313 #define TDMA_WRITE_PORT_HI(i) (TDMA_WRITE_PORT_OFFSET + \ 314 (i) * TDMA_PORT_SIZE) 315 #define TDMA_WRITE_PORT_LO(i) (TDMA_WRITE_PORT_OFFSET + \ 316 sizeof(u32) + (i) * TDMA_PORT_SIZE) 317 318 #define TDMA_READ_PORT_OFFSET (TDMA_WRITE_PORT_OFFSET + \ 319 (TDMA_NUM_RINGS * TDMA_PORT_SIZE)) 320 #define TDMA_READ_PORT_HI(i) (TDMA_READ_PORT_OFFSET + \ 321 (i) * TDMA_PORT_SIZE) 322 #define TDMA_READ_PORT_LO(i) (TDMA_READ_PORT_OFFSET + \ 323 sizeof(u32) + (i) * TDMA_PORT_SIZE) 324 325 #define TDMA_READ_PORT_CMD_OFFSET (TDMA_READ_PORT_OFFSET + \ 326 (TDMA_NUM_RINGS * TDMA_PORT_SIZE)) 327 #define TDMA_READ_PORT_CMD(i) (TDMA_READ_PORT_CMD_OFFSET + \ 328 (i) * sizeof(u32)) 329 330 #define TDMA_DESC_RING_00_BASE (TDMA_READ_PORT_CMD_OFFSET + \ 331 (TDMA_NUM_RINGS * sizeof(u32))) 332 333 /* Register offsets and defines relatives to a specific ring number */ 334 #define RING_HEAD_TAIL_PTR 0x00 335 #define RING_HEAD_MASK 0x7ff 336 #define RING_TAIL_SHIFT 11 337 #define RING_TAIL_MASK 0x7ff 338 #define RING_FLUSH (1 << 24) 339 #define RING_EN (1 << 25) 340 341 #define RING_COUNT 0x04 342 #define RING_COUNT_MASK 0x7ff 343 #define RING_BUFF_DONE_SHIFT 11 344 #define RING_BUFF_DONE_MASK 0x7ff 345 346 #define RING_MAX_HYST 0x08 347 #define RING_MAX_THRESH_MASK 0x7ff 348 #define RING_HYST_THRESH_SHIFT 11 349 #define RING_HYST_THRESH_MASK 0x7ff 350 351 #define RING_INTR_CONTROL 0x0c 352 #define RING_INTR_THRESH_MASK 0x7ff 353 #define RING_EMPTY_INTR_EN (1 << 15) 354 #define RING_TIMEOUT_SHIFT 16 355 #define RING_TIMEOUT_MASK 0xffff 356 357 #define RING_PROD_CONS_INDEX 0x10 358 #define RING_PROD_INDEX_MASK 0xffff 359 #define RING_CONS_INDEX_SHIFT 16 360 #define RING_CONS_INDEX_MASK 0xffff 361 362 #define RING_MAPPING 0x14 363 #define RING_QID_MASK 0x3 364 #define RING_PORT_ID_SHIFT 3 365 #define RING_PORT_ID_MASK 0x7 366 #define RING_IGNORE_STATUS (1 << 6) 367 #define RING_FAILOVER_EN (1 << 7) 368 #define RING_CREDIT_SHIFT 8 369 #define RING_CREDIT_MASK 0xffff 370 371 #define RING_PCP_DEI_VID 0x18 372 #define RING_VID_MASK 0x7ff 373 #define RING_DEI (1 << 12) 374 #define RING_PCP_SHIFT 13 375 #define RING_PCP_MASK 0x7 376 #define RING_PKT_SIZE_ADJ_SHIFT 16 377 #define RING_PKT_SIZE_ADJ_MASK 0xf 378 379 #define TDMA_DESC_RING_SIZE 28 380 381 /* Defininition for a given TX ring base address */ 382 #define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \ 383 ((i) * TDMA_DESC_RING_SIZE)) 384 385 /* Ring indexed register addreses */ 386 #define TDMA_DESC_RING_HEAD_TAIL_PTR(i) (TDMA_DESC_RING_BASE(i) + \ 387 RING_HEAD_TAIL_PTR) 388 #define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \ 389 RING_COUNT) 390 #define TDMA_DESC_RING_MAX_HYST(i) (TDMA_DESC_RING_BASE(i) + \ 391 RING_MAX_HYST) 392 #define TDMA_DESC_RING_INTR_CONTROL(i) (TDMA_DESC_RING_BASE(i) + \ 393 RING_INTR_CONTROL) 394 #define TDMA_DESC_RING_PROD_CONS_INDEX(i) \ 395 (TDMA_DESC_RING_BASE(i) + \ 396 RING_PROD_CONS_INDEX) 397 #define TDMA_DESC_RING_MAPPING(i) (TDMA_DESC_RING_BASE(i) + \ 398 RING_MAPPING) 399 #define TDMA_DESC_RING_PCP_DEI_VID(i) (TDMA_DESC_RING_BASE(i) + \ 400 RING_PCP_DEI_VID) 401 402 #define TDMA_CONTROL 0x600 403 #define TDMA_EN (1 << 0) 404 #define TSB_EN (1 << 1) 405 #define TSB_SWAP (1 << 2) 406 #define ACB_ALGO (1 << 3) 407 #define BUF_DATA_OFFSET_SHIFT 4 408 #define BUF_DATA_OFFSET_MASK 0x3ff 409 #define VLAN_EN (1 << 14) 410 #define SW_BRCM_TAG (1 << 15) 411 #define WNC_KPT_SIZE_UPDATE (1 << 16) 412 #define SYNC_PKT_SIZE (1 << 17) 413 #define ACH_TXDONE_DELAY_SHIFT 18 414 #define ACH_TXDONE_DELAY_MASK 0xff 415 416 #define TDMA_STATUS 0x604 417 #define TDMA_DISABLED (1 << 0) 418 #define TDMA_LL_RAM_INIT_BUSY (1 << 1) 419 420 #define TDMA_SCB_BURST_SIZE 0x608 421 #define TDMA_OVER_MAX_THRESH_STATUS 0x60c 422 #define TDMA_OVER_HYST_THRESH_STATUS 0x610 423 #define TDMA_TPID 0x614 424 425 #define TDMA_FREE_LIST_HEAD_TAIL_PTR 0x618 426 #define TDMA_FREE_HEAD_MASK 0x7ff 427 #define TDMA_FREE_TAIL_SHIFT 11 428 #define TDMA_FREE_TAIL_MASK 0x7ff 429 430 #define TDMA_FREE_LIST_COUNT 0x61c 431 #define TDMA_FREE_LIST_COUNT_MASK 0x7ff 432 433 #define TDMA_TIER2_ARB_CTRL 0x620 434 #define TDMA_ARB_MODE_RR 0 435 #define TDMA_ARB_MODE_WEIGHT_RR 0x1 436 #define TDMA_ARB_MODE_STRICT 0x2 437 #define TDMA_ARB_MODE_DEFICIT_RR 0x3 438 #define TDMA_CREDIT_SHIFT 4 439 #define TDMA_CREDIT_MASK 0xffff 440 441 #define TDMA_TIER1_ARB_0_CTRL 0x624 442 #define TDMA_ARB_EN (1 << 0) 443 444 #define TDMA_TIER1_ARB_0_QUEUE_EN 0x628 445 #define TDMA_TIER1_ARB_1_CTRL 0x62c 446 #define TDMA_TIER1_ARB_1_QUEUE_EN 0x630 447 #define TDMA_TIER1_ARB_2_CTRL 0x634 448 #define TDMA_TIER1_ARB_2_QUEUE_EN 0x638 449 #define TDMA_TIER1_ARB_3_CTRL 0x63c 450 #define TDMA_TIER1_ARB_3_QUEUE_EN 0x640 451 452 #define TDMA_SCB_ENDIAN_OVERRIDE 0x644 453 #define TDMA_LE_MODE (1 << 0) 454 #define TDMA_REG_MODE (1 << 1) 455 456 #define TDMA_TEST 0x648 457 #define TDMA_TP_OUT_SEL (1 << 0) 458 #define TDMA_MEM_TM (1 << 1) 459 460 #define TDMA_DEBUG 0x64c 461 462 /* Transmit/Receive descriptor */ 463 struct dma_desc { 464 u32 addr_status_len; 465 u32 addr_lo; 466 }; 467 468 /* Number of Receive hardware descriptor words */ 469 #define NUM_HW_RX_DESC_WORDS 1024 470 /* Real number of usable descriptors */ 471 #define NUM_RX_DESC (NUM_HW_RX_DESC_WORDS / WORDS_PER_DESC) 472 473 /* Internal linked-list RAM has up to 1536 entries */ 474 #define NUM_TX_DESC 1536 475 476 #define WORDS_PER_DESC (sizeof(struct dma_desc) / sizeof(u32)) 477 478 /* Rx/Tx common counter group.*/ 479 struct bcm_sysport_pkt_counters { 480 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ 481 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ 482 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ 483 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ 484 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ 485 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ 486 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ 487 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ 488 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ 489 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ 490 }; 491 492 /* RSV, Receive Status Vector */ 493 struct bcm_sysport_rx_counters { 494 struct bcm_sysport_pkt_counters pkt_cnt; 495 u32 pkt; /* RO (0x428) Received pkt count*/ 496 u32 bytes; /* RO Received byte count */ 497 u32 mca; /* RO # of Received multicast pkt */ 498 u32 bca; /* RO # of Receive broadcast pkt */ 499 u32 fcs; /* RO # of Received FCS error */ 500 u32 cf; /* RO # of Received control frame pkt*/ 501 u32 pf; /* RO # of Received pause frame pkt */ 502 u32 uo; /* RO # of unknown op code pkt */ 503 u32 aln; /* RO # of alignment error count */ 504 u32 flr; /* RO # of frame length out of range count */ 505 u32 cde; /* RO # of code error pkt */ 506 u32 fcr; /* RO # of carrier sense error pkt */ 507 u32 ovr; /* RO # of oversize pkt*/ 508 u32 jbr; /* RO # of jabber count */ 509 u32 mtue; /* RO # of MTU error pkt*/ 510 u32 pok; /* RO # of Received good pkt */ 511 u32 uc; /* RO # of unicast pkt */ 512 u32 ppp; /* RO # of PPP pkt */ 513 u32 rcrc; /* RO (0x470),# of CRC match pkt */ 514 }; 515 516 /* TSV, Transmit Status Vector */ 517 struct bcm_sysport_tx_counters { 518 struct bcm_sysport_pkt_counters pkt_cnt; 519 u32 pkts; /* RO (0x4a8) Transmited pkt */ 520 u32 mca; /* RO # of xmited multicast pkt */ 521 u32 bca; /* RO # of xmited broadcast pkt */ 522 u32 pf; /* RO # of xmited pause frame count */ 523 u32 cf; /* RO # of xmited control frame count */ 524 u32 fcs; /* RO # of xmited FCS error count */ 525 u32 ovr; /* RO # of xmited oversize pkt */ 526 u32 drf; /* RO # of xmited deferral pkt */ 527 u32 edf; /* RO # of xmited Excessive deferral pkt*/ 528 u32 scl; /* RO # of xmited single collision pkt */ 529 u32 mcl; /* RO # of xmited multiple collision pkt*/ 530 u32 lcl; /* RO # of xmited late collision pkt */ 531 u32 ecl; /* RO # of xmited excessive collision pkt*/ 532 u32 frg; /* RO # of xmited fragments pkt*/ 533 u32 ncl; /* RO # of xmited total collision count */ 534 u32 jbr; /* RO # of xmited jabber count*/ 535 u32 bytes; /* RO # of xmited byte count */ 536 u32 pok; /* RO # of xmited good pkt */ 537 u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */ 538 }; 539 540 struct bcm_sysport_mib { 541 struct bcm_sysport_rx_counters rx; 542 struct bcm_sysport_tx_counters tx; 543 u32 rx_runt_cnt; 544 u32 rx_runt_fcs; 545 u32 rx_runt_fcs_align; 546 u32 rx_runt_bytes; 547 u32 rxchk_bad_csum; 548 u32 rxchk_other_pkt_disc; 549 u32 rbuf_ovflow_cnt; 550 u32 rbuf_err_cnt; 551 }; 552 553 /* HW maintains a large list of counters */ 554 enum bcm_sysport_stat_type { 555 BCM_SYSPORT_STAT_NETDEV = -1, 556 BCM_SYSPORT_STAT_MIB_RX, 557 BCM_SYSPORT_STAT_MIB_TX, 558 BCM_SYSPORT_STAT_RUNT, 559 BCM_SYSPORT_STAT_RXCHK, 560 BCM_SYSPORT_STAT_RBUF, 561 }; 562 563 /* Macros to help define ethtool statistics */ 564 #define STAT_NETDEV(m) { \ 565 .stat_string = __stringify(m), \ 566 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 567 .stat_offset = offsetof(struct net_device_stats, m), \ 568 .type = BCM_SYSPORT_STAT_NETDEV, \ 569 } 570 571 #define STAT_MIB(str, m, _type) { \ 572 .stat_string = str, \ 573 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 574 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 575 .type = _type, \ 576 } 577 578 #define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX) 579 #define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX) 580 #define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT) 581 582 #define STAT_RXCHK(str, m, ofs) { \ 583 .stat_string = str, \ 584 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 585 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 586 .type = BCM_SYSPORT_STAT_RXCHK, \ 587 .reg_offset = ofs, \ 588 } 589 590 #define STAT_RBUF(str, m, ofs) { \ 591 .stat_string = str, \ 592 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 593 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 594 .type = BCM_SYSPORT_STAT_RBUF, \ 595 .reg_offset = ofs, \ 596 } 597 598 struct bcm_sysport_stats { 599 char stat_string[ETH_GSTRING_LEN]; 600 int stat_sizeof; 601 int stat_offset; 602 enum bcm_sysport_stat_type type; 603 /* reg offset from UMAC base for misc counters */ 604 u16 reg_offset; 605 }; 606 607 /* Software house keeping helper structure */ 608 struct bcm_sysport_cb { 609 struct sk_buff *skb; /* SKB for RX packets */ 610 void __iomem *bd_addr; /* Buffer descriptor PHYS addr */ 611 612 DEFINE_DMA_UNMAP_ADDR(dma_addr); 613 DEFINE_DMA_UNMAP_LEN(dma_len); 614 }; 615 616 /* Software view of the TX ring */ 617 struct bcm_sysport_tx_ring { 618 spinlock_t lock; /* Ring lock for tx reclaim/xmit */ 619 struct napi_struct napi; /* NAPI per tx queue */ 620 dma_addr_t desc_dma; /* DMA cookie */ 621 unsigned int index; /* Ring index */ 622 unsigned int size; /* Ring current size */ 623 unsigned int alloc_size; /* Ring one-time allocated size */ 624 unsigned int desc_count; /* Number of descriptors */ 625 unsigned int curr_desc; /* Current descriptor */ 626 unsigned int c_index; /* Last consumer index */ 627 unsigned int p_index; /* Current producer index */ 628 struct bcm_sysport_cb *cbs; /* Transmit control blocks */ 629 struct dma_desc *desc_cpu; /* CPU view of the descriptor */ 630 struct bcm_sysport_priv *priv; /* private context backpointer */ 631 }; 632 633 /* Driver private structure */ 634 struct bcm_sysport_priv { 635 void __iomem *base; 636 u32 irq0_stat; 637 u32 irq0_mask; 638 u32 irq1_stat; 639 u32 irq1_mask; 640 struct napi_struct napi ____cacheline_aligned; 641 struct net_device *netdev; 642 struct platform_device *pdev; 643 int irq0; 644 int irq1; 645 646 /* Transmit rings */ 647 struct bcm_sysport_tx_ring tx_rings[TDMA_NUM_RINGS]; 648 649 /* Receive queue */ 650 void __iomem *rx_bds; 651 void __iomem *rx_bd_assign_ptr; 652 unsigned int rx_bd_assign_index; 653 struct bcm_sysport_cb *rx_cbs; 654 unsigned int num_rx_bds; 655 unsigned int rx_read_ptr; 656 unsigned int rx_c_index; 657 658 /* PHY device */ 659 struct device_node *phy_dn; 660 struct phy_device *phydev; 661 phy_interface_t phy_interface; 662 int old_pause; 663 int old_link; 664 int old_duplex; 665 666 /* Misc fields */ 667 unsigned int rx_csum_en:1; 668 unsigned int tsb_en:1; 669 unsigned int crc_fwd:1; 670 u16 rev; 671 672 /* MIB related fields */ 673 struct bcm_sysport_mib mib; 674 675 /* Ethtool */ 676 u32 msg_enable; 677 }; 678 #endif /* __BCM_SYSPORT_H */ 679