1 /* 2 * Broadcom BCM7xxx System Port Ethernet MAC driver 3 * 4 * Copyright (C) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef __BCM_SYSPORT_H 12 #define __BCM_SYSPORT_H 13 14 #include <linux/bitmap.h> 15 #include <linux/ethtool.h> 16 #include <linux/if_vlan.h> 17 #include <linux/net_dim.h> 18 19 /* Receive/transmit descriptor format */ 20 #define DESC_ADDR_HI_STATUS_LEN 0x00 21 #define DESC_ADDR_HI_SHIFT 0 22 #define DESC_ADDR_HI_MASK 0xff 23 #define DESC_STATUS_SHIFT 8 24 #define DESC_STATUS_MASK 0x3ff 25 #define DESC_LEN_SHIFT 18 26 #define DESC_LEN_MASK 0x7fff 27 #define DESC_ADDR_LO 0x04 28 29 /* HW supports 40-bit addressing hence the */ 30 #define DESC_SIZE (WORDS_PER_DESC * sizeof(u32)) 31 32 /* Default RX buffer allocation size */ 33 #define RX_BUF_LENGTH 2048 34 35 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(4) + FCS(4) = 1526. 36 * 1536 is multiple of 256 bytes 37 */ 38 #define ENET_BRCM_TAG_LEN 4 39 #define ENET_PAD 10 40 #define UMAC_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ 41 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) 42 43 /* Transmit status block */ 44 struct bcm_tsb { 45 u32 pcp_dei_vid; 46 #define PCP_DEI_MASK 0xf 47 #define VID_SHIFT 4 48 #define VID_MASK 0xfff 49 u32 l4_ptr_dest_map; 50 #define L4_CSUM_PTR_MASK 0x1ff 51 #define L4_PTR_SHIFT 9 52 #define L4_PTR_MASK 0x1ff 53 #define L4_UDP (1 << 18) 54 #define L4_LENGTH_VALID (1 << 19) 55 #define DEST_MAP_SHIFT 20 56 #define DEST_MAP_MASK 0x1ff 57 }; 58 59 /* Receive status block uses the same 60 * definitions as the DMA descriptor 61 */ 62 struct bcm_rsb { 63 u32 rx_status_len; 64 u32 brcm_egress_tag; 65 }; 66 67 /* Common Receive/Transmit status bits */ 68 #define DESC_L4_CSUM (1 << 7) 69 #define DESC_SOP (1 << 8) 70 #define DESC_EOP (1 << 9) 71 72 /* Receive Status bits */ 73 #define RX_STATUS_UCAST 0 74 #define RX_STATUS_BCAST 0x04 75 #define RX_STATUS_MCAST 0x08 76 #define RX_STATUS_L2_MCAST 0x0c 77 #define RX_STATUS_ERR (1 << 4) 78 #define RX_STATUS_OVFLOW (1 << 5) 79 #define RX_STATUS_PARSE_FAIL (1 << 6) 80 81 /* Transmit Status bits */ 82 #define TX_STATUS_VLAN_NO_ACT 0x00 83 #define TX_STATUS_VLAN_PCP_TSB 0x01 84 #define TX_STATUS_VLAN_QUEUE 0x02 85 #define TX_STATUS_VLAN_VID_TSB 0x03 86 #define TX_STATUS_OWR_CRC (1 << 2) 87 #define TX_STATUS_APP_CRC (1 << 3) 88 #define TX_STATUS_BRCM_TAG_NO_ACT 0 89 #define TX_STATUS_BRCM_TAG_ZERO 0x10 90 #define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20 91 #define TX_STATUS_BRCM_TAG_ONE_TSB 0x30 92 #define TX_STATUS_SKIP_BYTES (1 << 6) 93 94 /* Specific register definitions */ 95 #define SYS_PORT_TOPCTRL_OFFSET 0 96 #define REV_CNTL 0x00 97 #define REV_MASK 0xffff 98 99 #define RX_FLUSH_CNTL 0x04 100 #define RX_FLUSH (1 << 0) 101 102 #define TX_FLUSH_CNTL 0x08 103 #define TX_FLUSH (1 << 0) 104 105 #define MISC_CNTL 0x0c 106 #define SYS_CLK_SEL (1 << 0) 107 #define TDMA_EOP_SEL (1 << 1) 108 109 /* Level-2 Interrupt controller offsets and defines */ 110 #define SYS_PORT_INTRL2_0_OFFSET 0x200 111 #define SYS_PORT_INTRL2_1_OFFSET 0x240 112 #define INTRL2_CPU_STATUS 0x00 113 #define INTRL2_CPU_SET 0x04 114 #define INTRL2_CPU_CLEAR 0x08 115 #define INTRL2_CPU_MASK_STATUS 0x0c 116 #define INTRL2_CPU_MASK_SET 0x10 117 #define INTRL2_CPU_MASK_CLEAR 0x14 118 119 /* Level-2 instance 0 interrupt bits */ 120 #define INTRL2_0_GISB_ERR (1 << 0) 121 #define INTRL2_0_RBUF_OVFLOW (1 << 1) 122 #define INTRL2_0_TBUF_UNDFLOW (1 << 2) 123 #define INTRL2_0_MPD (1 << 3) 124 #define INTRL2_0_BRCM_MATCH_TAG (1 << 4) 125 #define INTRL2_0_RDMA_MBDONE (1 << 5) 126 #define INTRL2_0_OVER_MAX_THRESH (1 << 6) 127 #define INTRL2_0_BELOW_HYST_THRESH (1 << 7) 128 #define INTRL2_0_FREE_LIST_EMPTY (1 << 8) 129 #define INTRL2_0_TX_RING_FULL (1 << 9) 130 #define INTRL2_0_DESC_ALLOC_ERR (1 << 10) 131 #define INTRL2_0_UNEXP_PKTSIZE_ACK (1 << 11) 132 133 /* SYSTEMPORT Lite groups the TX queues interrupts on instance 0 */ 134 #define INTRL2_0_TDMA_MBDONE_SHIFT 12 135 #define INTRL2_0_TDMA_MBDONE_MASK (0xffff << INTRL2_0_TDMA_MBDONE_SHIFT) 136 137 /* RXCHK offset and defines */ 138 #define SYS_PORT_RXCHK_OFFSET 0x300 139 140 #define RXCHK_CONTROL 0x00 141 #define RXCHK_EN (1 << 0) 142 #define RXCHK_SKIP_FCS (1 << 1) 143 #define RXCHK_BAD_CSUM_DIS (1 << 2) 144 #define RXCHK_BRCM_TAG_EN (1 << 3) 145 #define RXCHK_BRCM_TAG_MATCH_SHIFT 4 146 #define RXCHK_BRCM_TAG_MATCH_MASK 0xff 147 #define RXCHK_PARSE_TNL (1 << 12) 148 #define RXCHK_VIOL_EN (1 << 13) 149 #define RXCHK_VIOL_DIS (1 << 14) 150 #define RXCHK_INCOM_PKT (1 << 15) 151 #define RXCHK_V6_DUPEXT_EN (1 << 16) 152 #define RXCHK_V6_DUPEXT_DIS (1 << 17) 153 #define RXCHK_ETHERTYPE_DIS (1 << 18) 154 #define RXCHK_L2_HDR_DIS (1 << 19) 155 #define RXCHK_L3_HDR_DIS (1 << 20) 156 #define RXCHK_MAC_RX_ERR_DIS (1 << 21) 157 #define RXCHK_PARSE_AUTH (1 << 22) 158 159 #define RXCHK_BRCM_TAG0 0x04 160 #define RXCHK_BRCM_TAG(i) ((i) * 0x4 + RXCHK_BRCM_TAG0) 161 #define RXCHK_BRCM_TAG0_MASK 0x24 162 #define RXCHK_BRCM_TAG_MASK(i) ((i) * 0x4 + RXCHK_BRCM_TAG0_MASK) 163 #define RXCHK_BRCM_TAG_MATCH_STATUS 0x44 164 #define RXCHK_ETHERTYPE 0x48 165 #define RXCHK_BAD_CSUM_CNTR 0x4C 166 #define RXCHK_OTHER_DISC_CNTR 0x50 167 168 #define RXCHK_BRCM_TAG_MAX 8 169 #define RXCHK_BRCM_TAG_CID_SHIFT 16 170 #define RXCHK_BRCM_TAG_CID_MASK 0xff 171 172 /* TXCHCK offsets and defines */ 173 #define SYS_PORT_TXCHK_OFFSET 0x380 174 #define TXCHK_PKT_RDY_THRESH 0x00 175 176 /* Receive buffer offset and defines */ 177 #define SYS_PORT_RBUF_OFFSET 0x400 178 179 #define RBUF_CONTROL 0x00 180 #define RBUF_RSB_EN (1 << 0) 181 #define RBUF_4B_ALGN (1 << 1) 182 #define RBUF_BRCM_TAG_STRIP (1 << 2) 183 #define RBUF_BAD_PKT_DISC (1 << 3) 184 #define RBUF_RESUME_THRESH_SHIFT 4 185 #define RBUF_RESUME_THRESH_MASK 0xff 186 #define RBUF_OK_TO_SEND_SHIFT 12 187 #define RBUF_OK_TO_SEND_MASK 0xff 188 #define RBUF_CRC_REPLACE (1 << 20) 189 #define RBUF_OK_TO_SEND_MODE (1 << 21) 190 /* SYSTEMPORT Lite uses two bits here */ 191 #define RBUF_RSB_SWAP0 (1 << 22) 192 #define RBUF_RSB_SWAP1 (1 << 23) 193 #define RBUF_ACPI_EN (1 << 23) 194 #define RBUF_ACPI_EN_LITE (1 << 24) 195 196 #define RBUF_PKT_RDY_THRESH 0x04 197 198 #define RBUF_STATUS 0x08 199 #define RBUF_WOL_MODE (1 << 0) 200 #define RBUF_MPD (1 << 1) 201 #define RBUF_ACPI (1 << 2) 202 203 #define RBUF_OVFL_DISC_CNTR 0x0c 204 #define RBUF_ERR_PKT_CNTR 0x10 205 206 /* Transmit buffer offset and defines */ 207 #define SYS_PORT_TBUF_OFFSET 0x600 208 209 #define TBUF_CONTROL 0x00 210 #define TBUF_BP_EN (1 << 0) 211 #define TBUF_MAX_PKT_THRESH_SHIFT 1 212 #define TBUF_MAX_PKT_THRESH_MASK 0x1f 213 #define TBUF_FULL_THRESH_SHIFT 8 214 #define TBUF_FULL_THRESH_MASK 0x1f 215 216 /* UniMAC offset and defines */ 217 #define SYS_PORT_UMAC_OFFSET 0x800 218 219 #define UMAC_CMD 0x008 220 #define CMD_TX_EN (1 << 0) 221 #define CMD_RX_EN (1 << 1) 222 #define CMD_SPEED_SHIFT 2 223 #define CMD_SPEED_10 0 224 #define CMD_SPEED_100 1 225 #define CMD_SPEED_1000 2 226 #define CMD_SPEED_2500 3 227 #define CMD_SPEED_MASK 3 228 #define CMD_PROMISC (1 << 4) 229 #define CMD_PAD_EN (1 << 5) 230 #define CMD_CRC_FWD (1 << 6) 231 #define CMD_PAUSE_FWD (1 << 7) 232 #define CMD_RX_PAUSE_IGNORE (1 << 8) 233 #define CMD_TX_ADDR_INS (1 << 9) 234 #define CMD_HD_EN (1 << 10) 235 #define CMD_SW_RESET (1 << 13) 236 #define CMD_LCL_LOOP_EN (1 << 15) 237 #define CMD_AUTO_CONFIG (1 << 22) 238 #define CMD_CNTL_FRM_EN (1 << 23) 239 #define CMD_NO_LEN_CHK (1 << 24) 240 #define CMD_RMT_LOOP_EN (1 << 25) 241 #define CMD_PRBL_EN (1 << 27) 242 #define CMD_TX_PAUSE_IGNORE (1 << 28) 243 #define CMD_TX_RX_EN (1 << 29) 244 #define CMD_RUNT_FILTER_DIS (1 << 30) 245 246 #define UMAC_MAC0 0x00c 247 #define UMAC_MAC1 0x010 248 #define UMAC_MAX_FRAME_LEN 0x014 249 250 #define UMAC_TX_FLUSH 0x334 251 252 #define UMAC_MIB_START 0x400 253 254 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 255 * between the end of TX stats and the beginning of the RX RUNT 256 */ 257 #define UMAC_MIB_STAT_OFFSET 0xc 258 259 #define UMAC_MIB_CTRL 0x580 260 #define MIB_RX_CNT_RST (1 << 0) 261 #define MIB_RUNT_CNT_RST (1 << 1) 262 #define MIB_TX_CNT_RST (1 << 2) 263 264 /* These offsets are valid for SYSTEMPORT and SYSTEMPORT Lite */ 265 #define UMAC_MPD_CTRL 0x620 266 #define MPD_EN (1 << 0) 267 #define MSEQ_LEN_SHIFT 16 268 #define MSEQ_LEN_MASK 0xff 269 #define PSW_EN (1 << 27) 270 271 #define UMAC_PSW_MS 0x624 272 #define UMAC_PSW_LS 0x628 273 #define UMAC_MDF_CTRL 0x650 274 #define UMAC_MDF_ADDR 0x654 275 276 /* Only valid on SYSTEMPORT Lite */ 277 #define SYS_PORT_GIB_OFFSET 0x1000 278 279 #define GIB_CONTROL 0x00 280 #define GIB_TX_EN (1 << 0) 281 #define GIB_RX_EN (1 << 1) 282 #define GIB_TX_FLUSH (1 << 2) 283 #define GIB_RX_FLUSH (1 << 3) 284 #define GIB_GTX_CLK_SEL_SHIFT 4 285 #define GIB_GTX_CLK_EXT_CLK (0 << GIB_GTX_CLK_SEL_SHIFT) 286 #define GIB_GTX_CLK_125MHZ (1 << GIB_GTX_CLK_SEL_SHIFT) 287 #define GIB_GTX_CLK_250MHZ (2 << GIB_GTX_CLK_SEL_SHIFT) 288 #define GIB_FCS_STRIP_SHIFT 6 289 #define GIB_FCS_STRIP (1 << GIB_FCS_STRIP_SHIFT) 290 #define GIB_LCL_LOOP_EN (1 << 7) 291 #define GIB_LCL_LOOP_TXEN (1 << 8) 292 #define GIB_RMT_LOOP_EN (1 << 9) 293 #define GIB_RMT_LOOP_RXEN (1 << 10) 294 #define GIB_RX_PAUSE_EN (1 << 11) 295 #define GIB_PREAMBLE_LEN_SHIFT 12 296 #define GIB_PREAMBLE_LEN_MASK 0xf 297 #define GIB_IPG_LEN_SHIFT 16 298 #define GIB_IPG_LEN_MASK 0x3f 299 #define GIB_PAD_EXTENSION_SHIFT 22 300 #define GIB_PAD_EXTENSION_MASK 0x3f 301 302 #define GIB_MAC1 0x08 303 #define GIB_MAC0 0x0c 304 305 /* Receive DMA offset and defines */ 306 #define SYS_PORT_RDMA_OFFSET 0x2000 307 308 #define RDMA_CONTROL 0x1000 309 #define RDMA_EN (1 << 0) 310 #define RDMA_RING_CFG (1 << 1) 311 #define RDMA_DISC_EN (1 << 2) 312 #define RDMA_BUF_DATA_OFFSET_SHIFT 4 313 #define RDMA_BUF_DATA_OFFSET_MASK 0x3ff 314 315 #define RDMA_STATUS 0x1004 316 #define RDMA_DISABLED (1 << 0) 317 #define RDMA_DESC_RAM_INIT_BUSY (1 << 1) 318 #define RDMA_BP_STATUS (1 << 2) 319 320 #define RDMA_SCB_BURST_SIZE 0x1008 321 322 #define RDMA_RING_BUF_SIZE 0x100c 323 #define RDMA_RING_SIZE_SHIFT 16 324 325 #define RDMA_WRITE_PTR_HI 0x1010 326 #define RDMA_WRITE_PTR_LO 0x1014 327 #define RDMA_PROD_INDEX 0x1018 328 #define RDMA_PROD_INDEX_MASK 0xffff 329 330 #define RDMA_CONS_INDEX 0x101c 331 #define RDMA_CONS_INDEX_MASK 0xffff 332 333 #define RDMA_START_ADDR_HI 0x1020 334 #define RDMA_START_ADDR_LO 0x1024 335 #define RDMA_END_ADDR_HI 0x1028 336 #define RDMA_END_ADDR_LO 0x102c 337 338 #define RDMA_MBDONE_INTR 0x1030 339 #define RDMA_INTR_THRESH_MASK 0x1ff 340 #define RDMA_TIMEOUT_SHIFT 16 341 #define RDMA_TIMEOUT_MASK 0xffff 342 343 #define RDMA_XON_XOFF_THRESH 0x1034 344 #define RDMA_XON_XOFF_THRESH_MASK 0xffff 345 #define RDMA_XOFF_THRESH_SHIFT 16 346 347 #define RDMA_READ_PTR_HI 0x1038 348 #define RDMA_READ_PTR_LO 0x103c 349 350 #define RDMA_OVERRIDE 0x1040 351 #define RDMA_LE_MODE (1 << 0) 352 #define RDMA_REG_MODE (1 << 1) 353 354 #define RDMA_TEST 0x1044 355 #define RDMA_TP_OUT_SEL (1 << 0) 356 #define RDMA_MEM_SEL (1 << 1) 357 358 #define RDMA_DEBUG 0x1048 359 360 /* Transmit DMA offset and defines */ 361 #define TDMA_NUM_RINGS 32 /* rings = queues */ 362 #define TDMA_PORT_SIZE DESC_SIZE /* two 32-bits words */ 363 364 #define SYS_PORT_TDMA_OFFSET 0x4000 365 #define TDMA_WRITE_PORT_OFFSET 0x0000 366 #define TDMA_WRITE_PORT_HI(i) (TDMA_WRITE_PORT_OFFSET + \ 367 (i) * TDMA_PORT_SIZE) 368 #define TDMA_WRITE_PORT_LO(i) (TDMA_WRITE_PORT_OFFSET + \ 369 sizeof(u32) + (i) * TDMA_PORT_SIZE) 370 371 #define TDMA_READ_PORT_OFFSET (TDMA_WRITE_PORT_OFFSET + \ 372 (TDMA_NUM_RINGS * TDMA_PORT_SIZE)) 373 #define TDMA_READ_PORT_HI(i) (TDMA_READ_PORT_OFFSET + \ 374 (i) * TDMA_PORT_SIZE) 375 #define TDMA_READ_PORT_LO(i) (TDMA_READ_PORT_OFFSET + \ 376 sizeof(u32) + (i) * TDMA_PORT_SIZE) 377 378 #define TDMA_READ_PORT_CMD_OFFSET (TDMA_READ_PORT_OFFSET + \ 379 (TDMA_NUM_RINGS * TDMA_PORT_SIZE)) 380 #define TDMA_READ_PORT_CMD(i) (TDMA_READ_PORT_CMD_OFFSET + \ 381 (i) * sizeof(u32)) 382 383 #define TDMA_DESC_RING_00_BASE (TDMA_READ_PORT_CMD_OFFSET + \ 384 (TDMA_NUM_RINGS * sizeof(u32))) 385 386 /* Register offsets and defines relatives to a specific ring number */ 387 #define RING_HEAD_TAIL_PTR 0x00 388 #define RING_HEAD_MASK 0x7ff 389 #define RING_TAIL_SHIFT 11 390 #define RING_TAIL_MASK 0x7ff 391 #define RING_FLUSH (1 << 24) 392 #define RING_EN (1 << 25) 393 394 #define RING_COUNT 0x04 395 #define RING_COUNT_MASK 0x7ff 396 #define RING_BUFF_DONE_SHIFT 11 397 #define RING_BUFF_DONE_MASK 0x7ff 398 399 #define RING_MAX_HYST 0x08 400 #define RING_MAX_THRESH_MASK 0x7ff 401 #define RING_HYST_THRESH_SHIFT 11 402 #define RING_HYST_THRESH_MASK 0x7ff 403 404 #define RING_INTR_CONTROL 0x0c 405 #define RING_INTR_THRESH_MASK 0x7ff 406 #define RING_EMPTY_INTR_EN (1 << 15) 407 #define RING_TIMEOUT_SHIFT 16 408 #define RING_TIMEOUT_MASK 0xffff 409 410 #define RING_PROD_CONS_INDEX 0x10 411 #define RING_PROD_INDEX_MASK 0xffff 412 #define RING_CONS_INDEX_SHIFT 16 413 #define RING_CONS_INDEX_MASK 0xffff 414 415 #define RING_MAPPING 0x14 416 #define RING_QID_MASK 0x7 417 #define RING_PORT_ID_SHIFT 3 418 #define RING_PORT_ID_MASK 0x7 419 #define RING_IGNORE_STATUS (1 << 6) 420 #define RING_FAILOVER_EN (1 << 7) 421 #define RING_CREDIT_SHIFT 8 422 #define RING_CREDIT_MASK 0xffff 423 424 #define RING_PCP_DEI_VID 0x18 425 #define RING_VID_MASK 0x7ff 426 #define RING_DEI (1 << 12) 427 #define RING_PCP_SHIFT 13 428 #define RING_PCP_MASK 0x7 429 #define RING_PKT_SIZE_ADJ_SHIFT 16 430 #define RING_PKT_SIZE_ADJ_MASK 0xf 431 432 #define TDMA_DESC_RING_SIZE 28 433 434 /* Defininition for a given TX ring base address */ 435 #define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \ 436 ((i) * TDMA_DESC_RING_SIZE)) 437 438 /* Ring indexed register addreses */ 439 #define TDMA_DESC_RING_HEAD_TAIL_PTR(i) (TDMA_DESC_RING_BASE(i) + \ 440 RING_HEAD_TAIL_PTR) 441 #define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \ 442 RING_COUNT) 443 #define TDMA_DESC_RING_MAX_HYST(i) (TDMA_DESC_RING_BASE(i) + \ 444 RING_MAX_HYST) 445 #define TDMA_DESC_RING_INTR_CONTROL(i) (TDMA_DESC_RING_BASE(i) + \ 446 RING_INTR_CONTROL) 447 #define TDMA_DESC_RING_PROD_CONS_INDEX(i) \ 448 (TDMA_DESC_RING_BASE(i) + \ 449 RING_PROD_CONS_INDEX) 450 #define TDMA_DESC_RING_MAPPING(i) (TDMA_DESC_RING_BASE(i) + \ 451 RING_MAPPING) 452 #define TDMA_DESC_RING_PCP_DEI_VID(i) (TDMA_DESC_RING_BASE(i) + \ 453 RING_PCP_DEI_VID) 454 455 #define TDMA_CONTROL 0x600 456 #define TDMA_EN 0 457 #define TSB_EN 1 458 /* Uses 2 bits on SYSTEMPORT Lite and shifts everything by 1 bit, we 459 * keep the SYSTEMPORT layout here and adjust with tdma_control_bit() 460 */ 461 #define TSB_SWAP0 2 462 #define TSB_SWAP1 3 463 #define ACB_ALGO 3 464 #define BUF_DATA_OFFSET_SHIFT 4 465 #define BUF_DATA_OFFSET_MASK 0x3ff 466 #define VLAN_EN 14 467 #define SW_BRCM_TAG 15 468 #define WNC_KPT_SIZE_UPDATE 16 469 #define SYNC_PKT_SIZE 17 470 #define ACH_TXDONE_DELAY_SHIFT 18 471 #define ACH_TXDONE_DELAY_MASK 0xff 472 473 #define TDMA_STATUS 0x604 474 #define TDMA_DISABLED (1 << 0) 475 #define TDMA_LL_RAM_INIT_BUSY (1 << 1) 476 477 #define TDMA_SCB_BURST_SIZE 0x608 478 #define TDMA_OVER_MAX_THRESH_STATUS 0x60c 479 #define TDMA_OVER_HYST_THRESH_STATUS 0x610 480 #define TDMA_TPID 0x614 481 482 #define TDMA_FREE_LIST_HEAD_TAIL_PTR 0x618 483 #define TDMA_FREE_HEAD_MASK 0x7ff 484 #define TDMA_FREE_TAIL_SHIFT 11 485 #define TDMA_FREE_TAIL_MASK 0x7ff 486 487 #define TDMA_FREE_LIST_COUNT 0x61c 488 #define TDMA_FREE_LIST_COUNT_MASK 0x7ff 489 490 #define TDMA_TIER2_ARB_CTRL 0x620 491 #define TDMA_ARB_MODE_RR 0 492 #define TDMA_ARB_MODE_WEIGHT_RR 0x1 493 #define TDMA_ARB_MODE_STRICT 0x2 494 #define TDMA_ARB_MODE_DEFICIT_RR 0x3 495 #define TDMA_CREDIT_SHIFT 4 496 #define TDMA_CREDIT_MASK 0xffff 497 498 #define TDMA_TIER1_ARB_0_CTRL 0x624 499 #define TDMA_ARB_EN (1 << 0) 500 501 #define TDMA_TIER1_ARB_0_QUEUE_EN 0x628 502 #define TDMA_TIER1_ARB_1_CTRL 0x62c 503 #define TDMA_TIER1_ARB_1_QUEUE_EN 0x630 504 #define TDMA_TIER1_ARB_2_CTRL 0x634 505 #define TDMA_TIER1_ARB_2_QUEUE_EN 0x638 506 #define TDMA_TIER1_ARB_3_CTRL 0x63c 507 #define TDMA_TIER1_ARB_3_QUEUE_EN 0x640 508 509 #define TDMA_SCB_ENDIAN_OVERRIDE 0x644 510 #define TDMA_LE_MODE (1 << 0) 511 #define TDMA_REG_MODE (1 << 1) 512 513 #define TDMA_TEST 0x648 514 #define TDMA_TP_OUT_SEL (1 << 0) 515 #define TDMA_MEM_TM (1 << 1) 516 517 #define TDMA_DEBUG 0x64c 518 519 /* Number of Receive hardware descriptor words */ 520 #define SP_NUM_HW_RX_DESC_WORDS 1024 521 #define SP_LT_NUM_HW_RX_DESC_WORDS 256 522 523 /* Internal linked-list RAM size */ 524 #define SP_NUM_TX_DESC 1536 525 #define SP_LT_NUM_TX_DESC 256 526 527 #define WORDS_PER_DESC 2 528 529 /* Rx/Tx common counter group.*/ 530 struct bcm_sysport_pkt_counters { 531 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ 532 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ 533 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ 534 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ 535 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ 536 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ 537 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ 538 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ 539 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ 540 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ 541 }; 542 543 /* RSV, Receive Status Vector */ 544 struct bcm_sysport_rx_counters { 545 struct bcm_sysport_pkt_counters pkt_cnt; 546 u32 pkt; /* RO (0x428) Received pkt count*/ 547 u32 bytes; /* RO Received byte count */ 548 u32 mca; /* RO # of Received multicast pkt */ 549 u32 bca; /* RO # of Receive broadcast pkt */ 550 u32 fcs; /* RO # of Received FCS error */ 551 u32 cf; /* RO # of Received control frame pkt*/ 552 u32 pf; /* RO # of Received pause frame pkt */ 553 u32 uo; /* RO # of unknown op code pkt */ 554 u32 aln; /* RO # of alignment error count */ 555 u32 flr; /* RO # of frame length out of range count */ 556 u32 cde; /* RO # of code error pkt */ 557 u32 fcr; /* RO # of carrier sense error pkt */ 558 u32 ovr; /* RO # of oversize pkt*/ 559 u32 jbr; /* RO # of jabber count */ 560 u32 mtue; /* RO # of MTU error pkt*/ 561 u32 pok; /* RO # of Received good pkt */ 562 u32 uc; /* RO # of unicast pkt */ 563 u32 ppp; /* RO # of PPP pkt */ 564 u32 rcrc; /* RO (0x470),# of CRC match pkt */ 565 }; 566 567 /* TSV, Transmit Status Vector */ 568 struct bcm_sysport_tx_counters { 569 struct bcm_sysport_pkt_counters pkt_cnt; 570 u32 pkts; /* RO (0x4a8) Transmited pkt */ 571 u32 mca; /* RO # of xmited multicast pkt */ 572 u32 bca; /* RO # of xmited broadcast pkt */ 573 u32 pf; /* RO # of xmited pause frame count */ 574 u32 cf; /* RO # of xmited control frame count */ 575 u32 fcs; /* RO # of xmited FCS error count */ 576 u32 ovr; /* RO # of xmited oversize pkt */ 577 u32 drf; /* RO # of xmited deferral pkt */ 578 u32 edf; /* RO # of xmited Excessive deferral pkt*/ 579 u32 scl; /* RO # of xmited single collision pkt */ 580 u32 mcl; /* RO # of xmited multiple collision pkt*/ 581 u32 lcl; /* RO # of xmited late collision pkt */ 582 u32 ecl; /* RO # of xmited excessive collision pkt*/ 583 u32 frg; /* RO # of xmited fragments pkt*/ 584 u32 ncl; /* RO # of xmited total collision count */ 585 u32 jbr; /* RO # of xmited jabber count*/ 586 u32 bytes; /* RO # of xmited byte count */ 587 u32 pok; /* RO # of xmited good pkt */ 588 u32 uc; /* RO (0x4f0) # of xmited unicast pkt */ 589 }; 590 591 struct bcm_sysport_mib { 592 struct bcm_sysport_rx_counters rx; 593 struct bcm_sysport_tx_counters tx; 594 u32 rx_runt_cnt; 595 u32 rx_runt_fcs; 596 u32 rx_runt_fcs_align; 597 u32 rx_runt_bytes; 598 u32 rxchk_bad_csum; 599 u32 rxchk_other_pkt_disc; 600 u32 rbuf_ovflow_cnt; 601 u32 rbuf_err_cnt; 602 u32 alloc_rx_buff_failed; 603 u32 rx_dma_failed; 604 u32 tx_dma_failed; 605 u32 tx_realloc_tsb; 606 u32 tx_realloc_tsb_failed; 607 }; 608 609 /* HW maintains a large list of counters */ 610 enum bcm_sysport_stat_type { 611 BCM_SYSPORT_STAT_NETDEV = -1, 612 BCM_SYSPORT_STAT_NETDEV64, 613 BCM_SYSPORT_STAT_MIB_RX, 614 BCM_SYSPORT_STAT_MIB_TX, 615 BCM_SYSPORT_STAT_RUNT, 616 BCM_SYSPORT_STAT_RXCHK, 617 BCM_SYSPORT_STAT_RBUF, 618 BCM_SYSPORT_STAT_SOFT, 619 }; 620 621 /* Macros to help define ethtool statistics */ 622 #define STAT_NETDEV(m) { \ 623 .stat_string = __stringify(m), \ 624 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 625 .stat_offset = offsetof(struct net_device_stats, m), \ 626 .type = BCM_SYSPORT_STAT_NETDEV, \ 627 } 628 629 #define STAT_NETDEV64(m) { \ 630 .stat_string = __stringify(m), \ 631 .stat_sizeof = sizeof(((struct bcm_sysport_stats64 *)0)->m), \ 632 .stat_offset = offsetof(struct bcm_sysport_stats64, m), \ 633 .type = BCM_SYSPORT_STAT_NETDEV64, \ 634 } 635 636 #define STAT_MIB(str, m, _type) { \ 637 .stat_string = str, \ 638 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 639 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 640 .type = _type, \ 641 } 642 643 #define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX) 644 #define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX) 645 #define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT) 646 #define STAT_MIB_SOFT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_SOFT) 647 648 #define STAT_RXCHK(str, m, ofs) { \ 649 .stat_string = str, \ 650 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 651 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 652 .type = BCM_SYSPORT_STAT_RXCHK, \ 653 .reg_offset = ofs, \ 654 } 655 656 #define STAT_RBUF(str, m, ofs) { \ 657 .stat_string = str, \ 658 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 659 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 660 .type = BCM_SYSPORT_STAT_RBUF, \ 661 .reg_offset = ofs, \ 662 } 663 664 /* TX bytes and packets */ 665 #define NUM_SYSPORT_TXQ_STAT 2 666 667 struct bcm_sysport_stats { 668 char stat_string[ETH_GSTRING_LEN]; 669 int stat_sizeof; 670 int stat_offset; 671 enum bcm_sysport_stat_type type; 672 /* reg offset from UMAC base for misc counters */ 673 u16 reg_offset; 674 }; 675 676 struct bcm_sysport_stats64 { 677 /* 64bit stats on 32bit/64bit Machine */ 678 u64 rx_packets; 679 u64 rx_bytes; 680 u64 tx_packets; 681 u64 tx_bytes; 682 }; 683 684 /* Software house keeping helper structure */ 685 struct bcm_sysport_cb { 686 struct sk_buff *skb; /* SKB for RX packets */ 687 void __iomem *bd_addr; /* Buffer descriptor PHYS addr */ 688 689 DEFINE_DMA_UNMAP_ADDR(dma_addr); 690 DEFINE_DMA_UNMAP_LEN(dma_len); 691 }; 692 693 enum bcm_sysport_type { 694 SYSTEMPORT = 0, 695 SYSTEMPORT_LITE, 696 }; 697 698 struct bcm_sysport_hw_params { 699 bool is_lite; 700 unsigned int num_rx_desc_words; 701 }; 702 703 struct bcm_sysport_net_dim { 704 u16 use_dim; 705 u16 event_ctr; 706 unsigned long packets; 707 unsigned long bytes; 708 struct dim dim; 709 }; 710 711 /* Software view of the TX ring */ 712 struct bcm_sysport_tx_ring { 713 spinlock_t lock; /* Ring lock for tx reclaim/xmit */ 714 struct napi_struct napi; /* NAPI per tx queue */ 715 unsigned int index; /* Ring index */ 716 unsigned int size; /* Ring current size */ 717 unsigned int alloc_size; /* Ring one-time allocated size */ 718 unsigned int desc_count; /* Number of descriptors */ 719 unsigned int curr_desc; /* Current descriptor */ 720 unsigned int c_index; /* Last consumer index */ 721 unsigned int clean_index; /* Current clean index */ 722 struct bcm_sysport_cb *cbs; /* Transmit control blocks */ 723 struct bcm_sysport_priv *priv; /* private context backpointer */ 724 unsigned long packets; /* packets statistics */ 725 unsigned long bytes; /* bytes statistics */ 726 unsigned int switch_queue; /* switch port queue number */ 727 unsigned int switch_port; /* switch port queue number */ 728 bool inspect; /* inspect switch port and queue */ 729 }; 730 731 /* Driver private structure */ 732 struct bcm_sysport_priv { 733 void __iomem *base; 734 u32 irq0_stat; 735 u32 irq0_mask; 736 u32 irq1_stat; 737 u32 irq1_mask; 738 bool is_lite; 739 unsigned int num_rx_desc_words; 740 struct napi_struct napi ____cacheline_aligned; 741 struct net_device *netdev; 742 struct platform_device *pdev; 743 int irq0; 744 int irq1; 745 int wol_irq; 746 747 /* Transmit rings */ 748 struct bcm_sysport_tx_ring *tx_rings; 749 750 /* Receive queue */ 751 void __iomem *rx_bds; 752 struct bcm_sysport_cb *rx_cbs; 753 unsigned int num_rx_bds; 754 unsigned int rx_read_ptr; 755 unsigned int rx_c_index; 756 757 struct bcm_sysport_net_dim dim; 758 u32 rx_max_coalesced_frames; 759 u32 rx_coalesce_usecs; 760 761 /* PHY device */ 762 struct device_node *phy_dn; 763 phy_interface_t phy_interface; 764 int old_pause; 765 int old_link; 766 int old_duplex; 767 768 /* Misc fields */ 769 unsigned int rx_chk_en:1; 770 unsigned int tsb_en:1; 771 unsigned int crc_fwd:1; 772 u16 rev; 773 u32 wolopts; 774 u8 sopass[SOPASS_MAX]; 775 unsigned int wol_irq_disabled:1; 776 777 /* MIB related fields */ 778 struct bcm_sysport_mib mib; 779 780 /* Ethtool */ 781 u32 msg_enable; 782 DECLARE_BITMAP(filters, RXCHK_BRCM_TAG_MAX); 783 u32 filters_loc[RXCHK_BRCM_TAG_MAX]; 784 785 struct bcm_sysport_stats64 stats64; 786 787 /* For atomic update generic 64bit value on 32bit Machine */ 788 struct u64_stats_sync syncp; 789 790 /* map information between switch port queues and local queues */ 791 struct notifier_block dsa_notifier; 792 unsigned int per_port_num_tx_queues; 793 struct bcm_sysport_tx_ring *ring_map[DSA_MAX_PORTS * 8]; 794 795 }; 796 #endif /* __BCM_SYSPORT_H */ 797