1 /* 2 * Broadcom BCM7xxx System Port Ethernet MAC driver 3 * 4 * Copyright (C) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/netdevice.h> 18 #include <linux/etherdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/phy.h> 24 #include <linux/phy_fixed.h> 25 #include <net/ip.h> 26 #include <net/ipv6.h> 27 28 #include "bcmsysport.h" 29 30 /* I/O accessors register helpers */ 31 #define BCM_SYSPORT_IO_MACRO(name, offset) \ 32 static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \ 33 { \ 34 u32 reg = __raw_readl(priv->base + offset + off); \ 35 return reg; \ 36 } \ 37 static inline void name##_writel(struct bcm_sysport_priv *priv, \ 38 u32 val, u32 off) \ 39 { \ 40 __raw_writel(val, priv->base + offset + off); \ 41 } \ 42 43 BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET); 44 BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET); 45 BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET); 46 BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET); 47 BCM_SYSPORT_IO_MACRO(rdma, SYS_PORT_RDMA_OFFSET); 48 BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET); 49 BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET); 50 BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET); 51 BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET); 52 BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET); 53 54 /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied 55 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths. 56 */ 57 #define BCM_SYSPORT_INTR_L2(which) \ 58 static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \ 59 u32 mask) \ 60 { \ 61 priv->irq##which##_mask &= ~(mask); \ 62 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \ 63 } \ 64 static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \ 65 u32 mask) \ 66 { \ 67 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \ 68 priv->irq##which##_mask |= (mask); \ 69 } \ 70 71 BCM_SYSPORT_INTR_L2(0) 72 BCM_SYSPORT_INTR_L2(1) 73 74 /* Register accesses to GISB/RBUS registers are expensive (few hundred 75 * nanoseconds), so keep the check for 64-bits explicit here to save 76 * one register write per-packet on 32-bits platforms. 77 */ 78 static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv, 79 void __iomem *d, 80 dma_addr_t addr) 81 { 82 #ifdef CONFIG_PHYS_ADDR_T_64BIT 83 __raw_writel(upper_32_bits(addr) & DESC_ADDR_HI_MASK, 84 d + DESC_ADDR_HI_STATUS_LEN); 85 #endif 86 __raw_writel(lower_32_bits(addr), d + DESC_ADDR_LO); 87 } 88 89 static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv, 90 struct dma_desc *desc, 91 unsigned int port) 92 { 93 /* Ports are latched, so write upper address first */ 94 tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port)); 95 tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port)); 96 } 97 98 /* Ethtool operations */ 99 static int bcm_sysport_set_rx_csum(struct net_device *dev, 100 netdev_features_t wanted) 101 { 102 struct bcm_sysport_priv *priv = netdev_priv(dev); 103 u32 reg; 104 105 priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM); 106 reg = rxchk_readl(priv, RXCHK_CONTROL); 107 if (priv->rx_chk_en) 108 reg |= RXCHK_EN; 109 else 110 reg &= ~RXCHK_EN; 111 112 /* If UniMAC forwards CRC, we need to skip over it to get 113 * a valid CHK bit to be set in the per-packet status word 114 */ 115 if (priv->rx_chk_en && priv->crc_fwd) 116 reg |= RXCHK_SKIP_FCS; 117 else 118 reg &= ~RXCHK_SKIP_FCS; 119 120 /* If Broadcom tags are enabled (e.g: using a switch), make 121 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom 122 * tag after the Ethernet MAC Source Address. 123 */ 124 if (netdev_uses_dsa(dev)) 125 reg |= RXCHK_BRCM_TAG_EN; 126 else 127 reg &= ~RXCHK_BRCM_TAG_EN; 128 129 rxchk_writel(priv, reg, RXCHK_CONTROL); 130 131 return 0; 132 } 133 134 static int bcm_sysport_set_tx_csum(struct net_device *dev, 135 netdev_features_t wanted) 136 { 137 struct bcm_sysport_priv *priv = netdev_priv(dev); 138 u32 reg; 139 140 /* Hardware transmit checksum requires us to enable the Transmit status 141 * block prepended to the packet contents 142 */ 143 priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 144 reg = tdma_readl(priv, TDMA_CONTROL); 145 if (priv->tsb_en) 146 reg |= TSB_EN; 147 else 148 reg &= ~TSB_EN; 149 tdma_writel(priv, reg, TDMA_CONTROL); 150 151 return 0; 152 } 153 154 static int bcm_sysport_set_features(struct net_device *dev, 155 netdev_features_t features) 156 { 157 netdev_features_t changed = features ^ dev->features; 158 netdev_features_t wanted = dev->wanted_features; 159 int ret = 0; 160 161 if (changed & NETIF_F_RXCSUM) 162 ret = bcm_sysport_set_rx_csum(dev, wanted); 163 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) 164 ret = bcm_sysport_set_tx_csum(dev, wanted); 165 166 return ret; 167 } 168 169 /* Hardware counters must be kept in sync because the order/offset 170 * is important here (order in structure declaration = order in hardware) 171 */ 172 static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = { 173 /* general stats */ 174 STAT_NETDEV(rx_packets), 175 STAT_NETDEV(tx_packets), 176 STAT_NETDEV(rx_bytes), 177 STAT_NETDEV(tx_bytes), 178 STAT_NETDEV(rx_errors), 179 STAT_NETDEV(tx_errors), 180 STAT_NETDEV(rx_dropped), 181 STAT_NETDEV(tx_dropped), 182 STAT_NETDEV(multicast), 183 /* UniMAC RSV counters */ 184 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 185 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 186 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 187 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 188 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 189 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 190 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 191 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 192 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 193 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 194 STAT_MIB_RX("rx_pkts", mib.rx.pkt), 195 STAT_MIB_RX("rx_bytes", mib.rx.bytes), 196 STAT_MIB_RX("rx_multicast", mib.rx.mca), 197 STAT_MIB_RX("rx_broadcast", mib.rx.bca), 198 STAT_MIB_RX("rx_fcs", mib.rx.fcs), 199 STAT_MIB_RX("rx_control", mib.rx.cf), 200 STAT_MIB_RX("rx_pause", mib.rx.pf), 201 STAT_MIB_RX("rx_unknown", mib.rx.uo), 202 STAT_MIB_RX("rx_align", mib.rx.aln), 203 STAT_MIB_RX("rx_outrange", mib.rx.flr), 204 STAT_MIB_RX("rx_code", mib.rx.cde), 205 STAT_MIB_RX("rx_carrier", mib.rx.fcr), 206 STAT_MIB_RX("rx_oversize", mib.rx.ovr), 207 STAT_MIB_RX("rx_jabber", mib.rx.jbr), 208 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue), 209 STAT_MIB_RX("rx_good_pkts", mib.rx.pok), 210 STAT_MIB_RX("rx_unicast", mib.rx.uc), 211 STAT_MIB_RX("rx_ppp", mib.rx.ppp), 212 STAT_MIB_RX("rx_crc", mib.rx.rcrc), 213 /* UniMAC TSV counters */ 214 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 215 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 216 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 217 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 218 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 219 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 220 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 221 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 222 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 223 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 224 STAT_MIB_TX("tx_pkts", mib.tx.pkts), 225 STAT_MIB_TX("tx_multicast", mib.tx.mca), 226 STAT_MIB_TX("tx_broadcast", mib.tx.bca), 227 STAT_MIB_TX("tx_pause", mib.tx.pf), 228 STAT_MIB_TX("tx_control", mib.tx.cf), 229 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs), 230 STAT_MIB_TX("tx_oversize", mib.tx.ovr), 231 STAT_MIB_TX("tx_defer", mib.tx.drf), 232 STAT_MIB_TX("tx_excess_defer", mib.tx.edf), 233 STAT_MIB_TX("tx_single_col", mib.tx.scl), 234 STAT_MIB_TX("tx_multi_col", mib.tx.mcl), 235 STAT_MIB_TX("tx_late_col", mib.tx.lcl), 236 STAT_MIB_TX("tx_excess_col", mib.tx.ecl), 237 STAT_MIB_TX("tx_frags", mib.tx.frg), 238 STAT_MIB_TX("tx_total_col", mib.tx.ncl), 239 STAT_MIB_TX("tx_jabber", mib.tx.jbr), 240 STAT_MIB_TX("tx_bytes", mib.tx.bytes), 241 STAT_MIB_TX("tx_good_pkts", mib.tx.pok), 242 STAT_MIB_TX("tx_unicast", mib.tx.uc), 243 /* UniMAC RUNT counters */ 244 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 245 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 246 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 247 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 248 /* RXCHK misc statistics */ 249 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR), 250 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc, 251 RXCHK_OTHER_DISC_CNTR), 252 /* RBUF misc statistics */ 253 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR), 254 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR), 255 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 256 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed), 257 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed), 258 }; 259 260 #define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats) 261 262 static void bcm_sysport_get_drvinfo(struct net_device *dev, 263 struct ethtool_drvinfo *info) 264 { 265 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 266 strlcpy(info->version, "0.1", sizeof(info->version)); 267 strlcpy(info->bus_info, "platform", sizeof(info->bus_info)); 268 } 269 270 static u32 bcm_sysport_get_msglvl(struct net_device *dev) 271 { 272 struct bcm_sysport_priv *priv = netdev_priv(dev); 273 274 return priv->msg_enable; 275 } 276 277 static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable) 278 { 279 struct bcm_sysport_priv *priv = netdev_priv(dev); 280 281 priv->msg_enable = enable; 282 } 283 284 static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set) 285 { 286 switch (string_set) { 287 case ETH_SS_STATS: 288 return BCM_SYSPORT_STATS_LEN; 289 default: 290 return -EOPNOTSUPP; 291 } 292 } 293 294 static void bcm_sysport_get_strings(struct net_device *dev, 295 u32 stringset, u8 *data) 296 { 297 int i; 298 299 switch (stringset) { 300 case ETH_SS_STATS: 301 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 302 memcpy(data + i * ETH_GSTRING_LEN, 303 bcm_sysport_gstrings_stats[i].stat_string, 304 ETH_GSTRING_LEN); 305 } 306 break; 307 default: 308 break; 309 } 310 } 311 312 static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv) 313 { 314 int i, j = 0; 315 316 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 317 const struct bcm_sysport_stats *s; 318 u8 offset = 0; 319 u32 val = 0; 320 char *p; 321 322 s = &bcm_sysport_gstrings_stats[i]; 323 switch (s->type) { 324 case BCM_SYSPORT_STAT_NETDEV: 325 case BCM_SYSPORT_STAT_SOFT: 326 continue; 327 case BCM_SYSPORT_STAT_MIB_RX: 328 case BCM_SYSPORT_STAT_MIB_TX: 329 case BCM_SYSPORT_STAT_RUNT: 330 if (s->type != BCM_SYSPORT_STAT_MIB_RX) 331 offset = UMAC_MIB_STAT_OFFSET; 332 val = umac_readl(priv, UMAC_MIB_START + j + offset); 333 break; 334 case BCM_SYSPORT_STAT_RXCHK: 335 val = rxchk_readl(priv, s->reg_offset); 336 if (val == ~0) 337 rxchk_writel(priv, 0, s->reg_offset); 338 break; 339 case BCM_SYSPORT_STAT_RBUF: 340 val = rbuf_readl(priv, s->reg_offset); 341 if (val == ~0) 342 rbuf_writel(priv, 0, s->reg_offset); 343 break; 344 } 345 346 j += s->stat_sizeof; 347 p = (char *)priv + s->stat_offset; 348 *(u32 *)p = val; 349 } 350 351 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n"); 352 } 353 354 static void bcm_sysport_get_stats(struct net_device *dev, 355 struct ethtool_stats *stats, u64 *data) 356 { 357 struct bcm_sysport_priv *priv = netdev_priv(dev); 358 int i; 359 360 if (netif_running(dev)) 361 bcm_sysport_update_mib_counters(priv); 362 363 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 364 const struct bcm_sysport_stats *s; 365 char *p; 366 367 s = &bcm_sysport_gstrings_stats[i]; 368 if (s->type == BCM_SYSPORT_STAT_NETDEV) 369 p = (char *)&dev->stats; 370 else 371 p = (char *)priv; 372 p += s->stat_offset; 373 data[i] = *(unsigned long *)p; 374 } 375 } 376 377 static void bcm_sysport_get_wol(struct net_device *dev, 378 struct ethtool_wolinfo *wol) 379 { 380 struct bcm_sysport_priv *priv = netdev_priv(dev); 381 u32 reg; 382 383 wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE; 384 wol->wolopts = priv->wolopts; 385 386 if (!(priv->wolopts & WAKE_MAGICSECURE)) 387 return; 388 389 /* Return the programmed SecureOn password */ 390 reg = umac_readl(priv, UMAC_PSW_MS); 391 put_unaligned_be16(reg, &wol->sopass[0]); 392 reg = umac_readl(priv, UMAC_PSW_LS); 393 put_unaligned_be32(reg, &wol->sopass[2]); 394 } 395 396 static int bcm_sysport_set_wol(struct net_device *dev, 397 struct ethtool_wolinfo *wol) 398 { 399 struct bcm_sysport_priv *priv = netdev_priv(dev); 400 struct device *kdev = &priv->pdev->dev; 401 u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE; 402 403 if (!device_can_wakeup(kdev)) 404 return -ENOTSUPP; 405 406 if (wol->wolopts & ~supported) 407 return -EINVAL; 408 409 /* Program the SecureOn password */ 410 if (wol->wolopts & WAKE_MAGICSECURE) { 411 umac_writel(priv, get_unaligned_be16(&wol->sopass[0]), 412 UMAC_PSW_MS); 413 umac_writel(priv, get_unaligned_be32(&wol->sopass[2]), 414 UMAC_PSW_LS); 415 } 416 417 /* Flag the device and relevant IRQ as wakeup capable */ 418 if (wol->wolopts) { 419 device_set_wakeup_enable(kdev, 1); 420 if (priv->wol_irq_disabled) 421 enable_irq_wake(priv->wol_irq); 422 priv->wol_irq_disabled = 0; 423 } else { 424 device_set_wakeup_enable(kdev, 0); 425 /* Avoid unbalanced disable_irq_wake calls */ 426 if (!priv->wol_irq_disabled) 427 disable_irq_wake(priv->wol_irq); 428 priv->wol_irq_disabled = 1; 429 } 430 431 priv->wolopts = wol->wolopts; 432 433 return 0; 434 } 435 436 static int bcm_sysport_get_coalesce(struct net_device *dev, 437 struct ethtool_coalesce *ec) 438 { 439 struct bcm_sysport_priv *priv = netdev_priv(dev); 440 u32 reg; 441 442 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0)); 443 444 ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000; 445 ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK; 446 447 reg = rdma_readl(priv, RDMA_MBDONE_INTR); 448 449 ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000; 450 ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK; 451 452 return 0; 453 } 454 455 static int bcm_sysport_set_coalesce(struct net_device *dev, 456 struct ethtool_coalesce *ec) 457 { 458 struct bcm_sysport_priv *priv = netdev_priv(dev); 459 unsigned int i; 460 u32 reg; 461 462 /* Base system clock is 125Mhz, DMA timeout is this reference clock 463 * divided by 1024, which yield roughly 8.192 us, our maximum value has 464 * to fit in the RING_TIMEOUT_MASK (16 bits). 465 */ 466 if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK || 467 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 || 468 ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK || 469 ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1) 470 return -EINVAL; 471 472 if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) || 473 (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)) 474 return -EINVAL; 475 476 for (i = 0; i < dev->num_tx_queues; i++) { 477 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i)); 478 reg &= ~(RING_INTR_THRESH_MASK | 479 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT); 480 reg |= ec->tx_max_coalesced_frames; 481 reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) << 482 RING_TIMEOUT_SHIFT; 483 tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i)); 484 } 485 486 reg = rdma_readl(priv, RDMA_MBDONE_INTR); 487 reg &= ~(RDMA_INTR_THRESH_MASK | 488 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT); 489 reg |= ec->rx_max_coalesced_frames; 490 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192) << 491 RDMA_TIMEOUT_SHIFT; 492 rdma_writel(priv, reg, RDMA_MBDONE_INTR); 493 494 return 0; 495 } 496 497 static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb) 498 { 499 dev_kfree_skb_any(cb->skb); 500 cb->skb = NULL; 501 dma_unmap_addr_set(cb, dma_addr, 0); 502 } 503 504 static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv, 505 struct bcm_sysport_cb *cb) 506 { 507 struct device *kdev = &priv->pdev->dev; 508 struct net_device *ndev = priv->netdev; 509 struct sk_buff *skb, *rx_skb; 510 dma_addr_t mapping; 511 512 /* Allocate a new SKB for a new packet */ 513 skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH); 514 if (!skb) { 515 priv->mib.alloc_rx_buff_failed++; 516 netif_err(priv, rx_err, ndev, "SKB alloc failed\n"); 517 return NULL; 518 } 519 520 mapping = dma_map_single(kdev, skb->data, 521 RX_BUF_LENGTH, DMA_FROM_DEVICE); 522 if (dma_mapping_error(kdev, mapping)) { 523 priv->mib.rx_dma_failed++; 524 dev_kfree_skb_any(skb); 525 netif_err(priv, rx_err, ndev, "DMA mapping failure\n"); 526 return NULL; 527 } 528 529 /* Grab the current SKB on the ring */ 530 rx_skb = cb->skb; 531 if (likely(rx_skb)) 532 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 533 RX_BUF_LENGTH, DMA_FROM_DEVICE); 534 535 /* Put the new SKB on the ring */ 536 cb->skb = skb; 537 dma_unmap_addr_set(cb, dma_addr, mapping); 538 dma_desc_set_addr(priv, cb->bd_addr, mapping); 539 540 netif_dbg(priv, rx_status, ndev, "RX refill\n"); 541 542 /* Return the current SKB to the caller */ 543 return rx_skb; 544 } 545 546 static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv) 547 { 548 struct bcm_sysport_cb *cb; 549 struct sk_buff *skb; 550 unsigned int i; 551 552 for (i = 0; i < priv->num_rx_bds; i++) { 553 cb = &priv->rx_cbs[i]; 554 skb = bcm_sysport_rx_refill(priv, cb); 555 if (skb) 556 dev_kfree_skb(skb); 557 if (!cb->skb) 558 return -ENOMEM; 559 } 560 561 return 0; 562 } 563 564 /* Poll the hardware for up to budget packets to process */ 565 static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv, 566 unsigned int budget) 567 { 568 struct net_device *ndev = priv->netdev; 569 unsigned int processed = 0, to_process; 570 struct bcm_sysport_cb *cb; 571 struct sk_buff *skb; 572 unsigned int p_index; 573 u16 len, status; 574 struct bcm_rsb *rsb; 575 576 /* Determine how much we should process since last call */ 577 p_index = rdma_readl(priv, RDMA_PROD_INDEX); 578 p_index &= RDMA_PROD_INDEX_MASK; 579 580 if (p_index < priv->rx_c_index) 581 to_process = (RDMA_CONS_INDEX_MASK + 1) - 582 priv->rx_c_index + p_index; 583 else 584 to_process = p_index - priv->rx_c_index; 585 586 netif_dbg(priv, rx_status, ndev, 587 "p_index=%d rx_c_index=%d to_process=%d\n", 588 p_index, priv->rx_c_index, to_process); 589 590 while ((processed < to_process) && (processed < budget)) { 591 cb = &priv->rx_cbs[priv->rx_read_ptr]; 592 skb = bcm_sysport_rx_refill(priv, cb); 593 594 595 /* We do not have a backing SKB, so we do not a corresponding 596 * DMA mapping for this incoming packet since 597 * bcm_sysport_rx_refill always either has both skb and mapping 598 * or none. 599 */ 600 if (unlikely(!skb)) { 601 netif_err(priv, rx_err, ndev, "out of memory!\n"); 602 ndev->stats.rx_dropped++; 603 ndev->stats.rx_errors++; 604 goto next; 605 } 606 607 /* Extract the Receive Status Block prepended */ 608 rsb = (struct bcm_rsb *)skb->data; 609 len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK; 610 status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) & 611 DESC_STATUS_MASK; 612 613 netif_dbg(priv, rx_status, ndev, 614 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n", 615 p_index, priv->rx_c_index, priv->rx_read_ptr, 616 len, status); 617 618 if (unlikely(len > RX_BUF_LENGTH)) { 619 netif_err(priv, rx_status, ndev, "oversized packet\n"); 620 ndev->stats.rx_length_errors++; 621 ndev->stats.rx_errors++; 622 dev_kfree_skb_any(skb); 623 goto next; 624 } 625 626 if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) { 627 netif_err(priv, rx_status, ndev, "fragmented packet!\n"); 628 ndev->stats.rx_dropped++; 629 ndev->stats.rx_errors++; 630 dev_kfree_skb_any(skb); 631 goto next; 632 } 633 634 if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) { 635 netif_err(priv, rx_err, ndev, "error packet\n"); 636 if (status & RX_STATUS_OVFLOW) 637 ndev->stats.rx_over_errors++; 638 ndev->stats.rx_dropped++; 639 ndev->stats.rx_errors++; 640 dev_kfree_skb_any(skb); 641 goto next; 642 } 643 644 skb_put(skb, len); 645 646 /* Hardware validated our checksum */ 647 if (likely(status & DESC_L4_CSUM)) 648 skb->ip_summed = CHECKSUM_UNNECESSARY; 649 650 /* Hardware pre-pends packets with 2bytes before Ethernet 651 * header plus we have the Receive Status Block, strip off all 652 * of this from the SKB. 653 */ 654 skb_pull(skb, sizeof(*rsb) + 2); 655 len -= (sizeof(*rsb) + 2); 656 657 /* UniMAC may forward CRC */ 658 if (priv->crc_fwd) { 659 skb_trim(skb, len - ETH_FCS_LEN); 660 len -= ETH_FCS_LEN; 661 } 662 663 skb->protocol = eth_type_trans(skb, ndev); 664 ndev->stats.rx_packets++; 665 ndev->stats.rx_bytes += len; 666 667 napi_gro_receive(&priv->napi, skb); 668 next: 669 processed++; 670 priv->rx_read_ptr++; 671 672 if (priv->rx_read_ptr == priv->num_rx_bds) 673 priv->rx_read_ptr = 0; 674 } 675 676 return processed; 677 } 678 679 static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_priv *priv, 680 struct bcm_sysport_cb *cb, 681 unsigned int *bytes_compl, 682 unsigned int *pkts_compl) 683 { 684 struct device *kdev = &priv->pdev->dev; 685 struct net_device *ndev = priv->netdev; 686 687 if (cb->skb) { 688 ndev->stats.tx_bytes += cb->skb->len; 689 *bytes_compl += cb->skb->len; 690 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 691 dma_unmap_len(cb, dma_len), 692 DMA_TO_DEVICE); 693 ndev->stats.tx_packets++; 694 (*pkts_compl)++; 695 bcm_sysport_free_cb(cb); 696 /* SKB fragment */ 697 } else if (dma_unmap_addr(cb, dma_addr)) { 698 ndev->stats.tx_bytes += dma_unmap_len(cb, dma_len); 699 dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr), 700 dma_unmap_len(cb, dma_len), DMA_TO_DEVICE); 701 dma_unmap_addr_set(cb, dma_addr, 0); 702 } 703 } 704 705 /* Reclaim queued SKBs for transmission completion, lockless version */ 706 static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, 707 struct bcm_sysport_tx_ring *ring) 708 { 709 struct net_device *ndev = priv->netdev; 710 unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs; 711 unsigned int pkts_compl = 0, bytes_compl = 0; 712 struct bcm_sysport_cb *cb; 713 u32 hw_ind; 714 715 /* Compute how many descriptors have been processed since last call */ 716 hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index)); 717 c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK; 718 ring->p_index = (hw_ind & RING_PROD_INDEX_MASK); 719 720 last_c_index = ring->c_index; 721 num_tx_cbs = ring->size; 722 723 c_index &= (num_tx_cbs - 1); 724 725 if (c_index >= last_c_index) 726 last_tx_cn = c_index - last_c_index; 727 else 728 last_tx_cn = num_tx_cbs - last_c_index + c_index; 729 730 netif_dbg(priv, tx_done, ndev, 731 "ring=%d c_index=%d last_tx_cn=%d last_c_index=%d\n", 732 ring->index, c_index, last_tx_cn, last_c_index); 733 734 while (last_tx_cn-- > 0) { 735 cb = ring->cbs + last_c_index; 736 bcm_sysport_tx_reclaim_one(priv, cb, &bytes_compl, &pkts_compl); 737 738 ring->desc_count++; 739 last_c_index++; 740 last_c_index &= (num_tx_cbs - 1); 741 } 742 743 ring->c_index = c_index; 744 745 netif_dbg(priv, tx_done, ndev, 746 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n", 747 ring->index, ring->c_index, pkts_compl, bytes_compl); 748 749 return pkts_compl; 750 } 751 752 /* Locked version of the per-ring TX reclaim routine */ 753 static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, 754 struct bcm_sysport_tx_ring *ring) 755 { 756 struct netdev_queue *txq; 757 unsigned int released; 758 unsigned long flags; 759 760 txq = netdev_get_tx_queue(priv->netdev, ring->index); 761 762 spin_lock_irqsave(&ring->lock, flags); 763 released = __bcm_sysport_tx_reclaim(priv, ring); 764 if (released) 765 netif_tx_wake_queue(txq); 766 767 spin_unlock_irqrestore(&ring->lock, flags); 768 769 return released; 770 } 771 772 /* Locked version of the per-ring TX reclaim, but does not wake the queue */ 773 static void bcm_sysport_tx_clean(struct bcm_sysport_priv *priv, 774 struct bcm_sysport_tx_ring *ring) 775 { 776 unsigned long flags; 777 778 spin_lock_irqsave(&ring->lock, flags); 779 __bcm_sysport_tx_reclaim(priv, ring); 780 spin_unlock_irqrestore(&ring->lock, flags); 781 } 782 783 static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget) 784 { 785 struct bcm_sysport_tx_ring *ring = 786 container_of(napi, struct bcm_sysport_tx_ring, napi); 787 unsigned int work_done = 0; 788 789 work_done = bcm_sysport_tx_reclaim(ring->priv, ring); 790 791 if (work_done == 0) { 792 napi_complete(napi); 793 /* re-enable TX interrupt */ 794 intrl2_1_mask_clear(ring->priv, BIT(ring->index)); 795 796 return 0; 797 } 798 799 return budget; 800 } 801 802 static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv) 803 { 804 unsigned int q; 805 806 for (q = 0; q < priv->netdev->num_tx_queues; q++) 807 bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]); 808 } 809 810 static int bcm_sysport_poll(struct napi_struct *napi, int budget) 811 { 812 struct bcm_sysport_priv *priv = 813 container_of(napi, struct bcm_sysport_priv, napi); 814 unsigned int work_done = 0; 815 816 work_done = bcm_sysport_desc_rx(priv, budget); 817 818 priv->rx_c_index += work_done; 819 priv->rx_c_index &= RDMA_CONS_INDEX_MASK; 820 rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX); 821 822 if (work_done < budget) { 823 napi_complete_done(napi, work_done); 824 /* re-enable RX interrupts */ 825 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE); 826 } 827 828 return work_done; 829 } 830 831 static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv) 832 { 833 u32 reg; 834 835 /* Stop monitoring MPD interrupt */ 836 intrl2_0_mask_set(priv, INTRL2_0_MPD); 837 838 /* Clear the MagicPacket detection logic */ 839 reg = umac_readl(priv, UMAC_MPD_CTRL); 840 reg &= ~MPD_EN; 841 umac_writel(priv, reg, UMAC_MPD_CTRL); 842 843 netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n"); 844 } 845 846 /* RX and misc interrupt routine */ 847 static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id) 848 { 849 struct net_device *dev = dev_id; 850 struct bcm_sysport_priv *priv = netdev_priv(dev); 851 852 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 853 ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 854 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 855 856 if (unlikely(priv->irq0_stat == 0)) { 857 netdev_warn(priv->netdev, "spurious RX interrupt\n"); 858 return IRQ_NONE; 859 } 860 861 if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) { 862 if (likely(napi_schedule_prep(&priv->napi))) { 863 /* disable RX interrupts */ 864 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE); 865 __napi_schedule_irqoff(&priv->napi); 866 } 867 } 868 869 /* TX ring is full, perform a full reclaim since we do not know 870 * which one would trigger this interrupt 871 */ 872 if (priv->irq0_stat & INTRL2_0_TX_RING_FULL) 873 bcm_sysport_tx_reclaim_all(priv); 874 875 if (priv->irq0_stat & INTRL2_0_MPD) { 876 netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n"); 877 bcm_sysport_resume_from_wol(priv); 878 } 879 880 return IRQ_HANDLED; 881 } 882 883 /* TX interrupt service routine */ 884 static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id) 885 { 886 struct net_device *dev = dev_id; 887 struct bcm_sysport_priv *priv = netdev_priv(dev); 888 struct bcm_sysport_tx_ring *txr; 889 unsigned int ring; 890 891 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 892 ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 893 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 894 895 if (unlikely(priv->irq1_stat == 0)) { 896 netdev_warn(priv->netdev, "spurious TX interrupt\n"); 897 return IRQ_NONE; 898 } 899 900 for (ring = 0; ring < dev->num_tx_queues; ring++) { 901 if (!(priv->irq1_stat & BIT(ring))) 902 continue; 903 904 txr = &priv->tx_rings[ring]; 905 906 if (likely(napi_schedule_prep(&txr->napi))) { 907 intrl2_1_mask_set(priv, BIT(ring)); 908 __napi_schedule_irqoff(&txr->napi); 909 } 910 } 911 912 return IRQ_HANDLED; 913 } 914 915 static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id) 916 { 917 struct bcm_sysport_priv *priv = dev_id; 918 919 pm_wakeup_event(&priv->pdev->dev, 0); 920 921 return IRQ_HANDLED; 922 } 923 924 #ifdef CONFIG_NET_POLL_CONTROLLER 925 static void bcm_sysport_poll_controller(struct net_device *dev) 926 { 927 struct bcm_sysport_priv *priv = netdev_priv(dev); 928 929 disable_irq(priv->irq0); 930 bcm_sysport_rx_isr(priv->irq0, priv); 931 enable_irq(priv->irq0); 932 933 disable_irq(priv->irq1); 934 bcm_sysport_tx_isr(priv->irq1, priv); 935 enable_irq(priv->irq1); 936 } 937 #endif 938 939 static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb, 940 struct net_device *dev) 941 { 942 struct sk_buff *nskb; 943 struct bcm_tsb *tsb; 944 u32 csum_info; 945 u8 ip_proto; 946 u16 csum_start; 947 u16 ip_ver; 948 949 /* Re-allocate SKB if needed */ 950 if (unlikely(skb_headroom(skb) < sizeof(*tsb))) { 951 nskb = skb_realloc_headroom(skb, sizeof(*tsb)); 952 dev_kfree_skb(skb); 953 if (!nskb) { 954 dev->stats.tx_errors++; 955 dev->stats.tx_dropped++; 956 return NULL; 957 } 958 skb = nskb; 959 } 960 961 tsb = (struct bcm_tsb *)skb_push(skb, sizeof(*tsb)); 962 /* Zero-out TSB by default */ 963 memset(tsb, 0, sizeof(*tsb)); 964 965 if (skb->ip_summed == CHECKSUM_PARTIAL) { 966 ip_ver = htons(skb->protocol); 967 switch (ip_ver) { 968 case ETH_P_IP: 969 ip_proto = ip_hdr(skb)->protocol; 970 break; 971 case ETH_P_IPV6: 972 ip_proto = ipv6_hdr(skb)->nexthdr; 973 break; 974 default: 975 return skb; 976 } 977 978 /* Get the checksum offset and the L4 (transport) offset */ 979 csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb); 980 csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK; 981 csum_info |= (csum_start << L4_PTR_SHIFT); 982 983 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { 984 csum_info |= L4_LENGTH_VALID; 985 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) 986 csum_info |= L4_UDP; 987 } else { 988 csum_info = 0; 989 } 990 991 tsb->l4_ptr_dest_map = csum_info; 992 } 993 994 return skb; 995 } 996 997 static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb, 998 struct net_device *dev) 999 { 1000 struct bcm_sysport_priv *priv = netdev_priv(dev); 1001 struct device *kdev = &priv->pdev->dev; 1002 struct bcm_sysport_tx_ring *ring; 1003 struct bcm_sysport_cb *cb; 1004 struct netdev_queue *txq; 1005 struct dma_desc *desc; 1006 unsigned int skb_len; 1007 unsigned long flags; 1008 dma_addr_t mapping; 1009 u32 len_status; 1010 u16 queue; 1011 int ret; 1012 1013 queue = skb_get_queue_mapping(skb); 1014 txq = netdev_get_tx_queue(dev, queue); 1015 ring = &priv->tx_rings[queue]; 1016 1017 /* lock against tx reclaim in BH context and TX ring full interrupt */ 1018 spin_lock_irqsave(&ring->lock, flags); 1019 if (unlikely(ring->desc_count == 0)) { 1020 netif_tx_stop_queue(txq); 1021 netdev_err(dev, "queue %d awake and ring full!\n", queue); 1022 ret = NETDEV_TX_BUSY; 1023 goto out; 1024 } 1025 1026 /* The Ethernet switch we are interfaced with needs packets to be at 1027 * least 64 bytes (including FCS) otherwise they will be discarded when 1028 * they enter the switch port logic. When Broadcom tags are enabled, we 1029 * need to make sure that packets are at least 68 bytes 1030 * (including FCS and tag) because the length verification is done after 1031 * the Broadcom tag is stripped off the ingress packet. 1032 */ 1033 if (skb_put_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) { 1034 ret = NETDEV_TX_OK; 1035 goto out; 1036 } 1037 1038 /* Insert TSB and checksum infos */ 1039 if (priv->tsb_en) { 1040 skb = bcm_sysport_insert_tsb(skb, dev); 1041 if (!skb) { 1042 ret = NETDEV_TX_OK; 1043 goto out; 1044 } 1045 } 1046 1047 skb_len = skb->len; 1048 1049 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); 1050 if (dma_mapping_error(kdev, mapping)) { 1051 priv->mib.tx_dma_failed++; 1052 netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n", 1053 skb->data, skb_len); 1054 ret = NETDEV_TX_OK; 1055 goto out; 1056 } 1057 1058 /* Remember the SKB for future freeing */ 1059 cb = &ring->cbs[ring->curr_desc]; 1060 cb->skb = skb; 1061 dma_unmap_addr_set(cb, dma_addr, mapping); 1062 dma_unmap_len_set(cb, dma_len, skb_len); 1063 1064 /* Fetch a descriptor entry from our pool */ 1065 desc = ring->desc_cpu; 1066 1067 desc->addr_lo = lower_32_bits(mapping); 1068 len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK; 1069 len_status |= (skb_len << DESC_LEN_SHIFT); 1070 len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) << 1071 DESC_STATUS_SHIFT; 1072 if (skb->ip_summed == CHECKSUM_PARTIAL) 1073 len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT); 1074 1075 ring->curr_desc++; 1076 if (ring->curr_desc == ring->size) 1077 ring->curr_desc = 0; 1078 ring->desc_count--; 1079 1080 /* Ensure write completion of the descriptor status/length 1081 * in DRAM before the System Port WRITE_PORT register latches 1082 * the value 1083 */ 1084 wmb(); 1085 desc->addr_status_len = len_status; 1086 wmb(); 1087 1088 /* Write this descriptor address to the RING write port */ 1089 tdma_port_write_desc_addr(priv, desc, ring->index); 1090 1091 /* Check ring space and update SW control flow */ 1092 if (ring->desc_count == 0) 1093 netif_tx_stop_queue(txq); 1094 1095 netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n", 1096 ring->index, ring->desc_count, ring->curr_desc); 1097 1098 ret = NETDEV_TX_OK; 1099 out: 1100 spin_unlock_irqrestore(&ring->lock, flags); 1101 return ret; 1102 } 1103 1104 static void bcm_sysport_tx_timeout(struct net_device *dev) 1105 { 1106 netdev_warn(dev, "transmit timeout!\n"); 1107 1108 netif_trans_update(dev); 1109 dev->stats.tx_errors++; 1110 1111 netif_tx_wake_all_queues(dev); 1112 } 1113 1114 /* phylib adjust link callback */ 1115 static void bcm_sysport_adj_link(struct net_device *dev) 1116 { 1117 struct bcm_sysport_priv *priv = netdev_priv(dev); 1118 struct phy_device *phydev = dev->phydev; 1119 unsigned int changed = 0; 1120 u32 cmd_bits = 0, reg; 1121 1122 if (priv->old_link != phydev->link) { 1123 changed = 1; 1124 priv->old_link = phydev->link; 1125 } 1126 1127 if (priv->old_duplex != phydev->duplex) { 1128 changed = 1; 1129 priv->old_duplex = phydev->duplex; 1130 } 1131 1132 switch (phydev->speed) { 1133 case SPEED_2500: 1134 cmd_bits = CMD_SPEED_2500; 1135 break; 1136 case SPEED_1000: 1137 cmd_bits = CMD_SPEED_1000; 1138 break; 1139 case SPEED_100: 1140 cmd_bits = CMD_SPEED_100; 1141 break; 1142 case SPEED_10: 1143 cmd_bits = CMD_SPEED_10; 1144 break; 1145 default: 1146 break; 1147 } 1148 cmd_bits <<= CMD_SPEED_SHIFT; 1149 1150 if (phydev->duplex == DUPLEX_HALF) 1151 cmd_bits |= CMD_HD_EN; 1152 1153 if (priv->old_pause != phydev->pause) { 1154 changed = 1; 1155 priv->old_pause = phydev->pause; 1156 } 1157 1158 if (!phydev->pause) 1159 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 1160 1161 if (!changed) 1162 return; 1163 1164 if (phydev->link) { 1165 reg = umac_readl(priv, UMAC_CMD); 1166 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 1167 CMD_HD_EN | CMD_RX_PAUSE_IGNORE | 1168 CMD_TX_PAUSE_IGNORE); 1169 reg |= cmd_bits; 1170 umac_writel(priv, reg, UMAC_CMD); 1171 } 1172 1173 phy_print_status(phydev); 1174 } 1175 1176 static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv, 1177 unsigned int index) 1178 { 1179 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; 1180 struct device *kdev = &priv->pdev->dev; 1181 size_t size; 1182 void *p; 1183 u32 reg; 1184 1185 /* Simple descriptors partitioning for now */ 1186 size = 256; 1187 1188 /* We just need one DMA descriptor which is DMA-able, since writing to 1189 * the port will allocate a new descriptor in its internal linked-list 1190 */ 1191 p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma, 1192 GFP_KERNEL); 1193 if (!p) { 1194 netif_err(priv, hw, priv->netdev, "DMA alloc failed\n"); 1195 return -ENOMEM; 1196 } 1197 1198 ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL); 1199 if (!ring->cbs) { 1200 netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); 1201 return -ENOMEM; 1202 } 1203 1204 /* Initialize SW view of the ring */ 1205 spin_lock_init(&ring->lock); 1206 ring->priv = priv; 1207 netif_tx_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64); 1208 ring->index = index; 1209 ring->size = size; 1210 ring->alloc_size = ring->size; 1211 ring->desc_cpu = p; 1212 ring->desc_count = ring->size; 1213 ring->curr_desc = 0; 1214 1215 /* Initialize HW ring */ 1216 tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index)); 1217 tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index)); 1218 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index)); 1219 tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index)); 1220 tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index)); 1221 tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index)); 1222 1223 /* Program the number of descriptors as MAX_THRESHOLD and half of 1224 * its size for the hysteresis trigger 1225 */ 1226 tdma_writel(priv, ring->size | 1227 1 << RING_HYST_THRESH_SHIFT, 1228 TDMA_DESC_RING_MAX_HYST(index)); 1229 1230 /* Enable the ring queue in the arbiter */ 1231 reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN); 1232 reg |= (1 << index); 1233 tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN); 1234 1235 napi_enable(&ring->napi); 1236 1237 netif_dbg(priv, hw, priv->netdev, 1238 "TDMA cfg, size=%d, desc_cpu=%p\n", 1239 ring->size, ring->desc_cpu); 1240 1241 return 0; 1242 } 1243 1244 static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv, 1245 unsigned int index) 1246 { 1247 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; 1248 struct device *kdev = &priv->pdev->dev; 1249 u32 reg; 1250 1251 /* Caller should stop the TDMA engine */ 1252 reg = tdma_readl(priv, TDMA_STATUS); 1253 if (!(reg & TDMA_DISABLED)) 1254 netdev_warn(priv->netdev, "TDMA not stopped!\n"); 1255 1256 /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could 1257 * fail, so by checking this pointer we know whether the TX ring was 1258 * fully initialized or not. 1259 */ 1260 if (!ring->cbs) 1261 return; 1262 1263 napi_disable(&ring->napi); 1264 netif_napi_del(&ring->napi); 1265 1266 bcm_sysport_tx_clean(priv, ring); 1267 1268 kfree(ring->cbs); 1269 ring->cbs = NULL; 1270 1271 if (ring->desc_dma) { 1272 dma_free_coherent(kdev, sizeof(struct dma_desc), 1273 ring->desc_cpu, ring->desc_dma); 1274 ring->desc_dma = 0; 1275 } 1276 ring->size = 0; 1277 ring->alloc_size = 0; 1278 1279 netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n"); 1280 } 1281 1282 /* RDMA helper */ 1283 static inline int rdma_enable_set(struct bcm_sysport_priv *priv, 1284 unsigned int enable) 1285 { 1286 unsigned int timeout = 1000; 1287 u32 reg; 1288 1289 reg = rdma_readl(priv, RDMA_CONTROL); 1290 if (enable) 1291 reg |= RDMA_EN; 1292 else 1293 reg &= ~RDMA_EN; 1294 rdma_writel(priv, reg, RDMA_CONTROL); 1295 1296 /* Poll for RMDA disabling completion */ 1297 do { 1298 reg = rdma_readl(priv, RDMA_STATUS); 1299 if (!!(reg & RDMA_DISABLED) == !enable) 1300 return 0; 1301 usleep_range(1000, 2000); 1302 } while (timeout-- > 0); 1303 1304 netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n"); 1305 1306 return -ETIMEDOUT; 1307 } 1308 1309 /* TDMA helper */ 1310 static inline int tdma_enable_set(struct bcm_sysport_priv *priv, 1311 unsigned int enable) 1312 { 1313 unsigned int timeout = 1000; 1314 u32 reg; 1315 1316 reg = tdma_readl(priv, TDMA_CONTROL); 1317 if (enable) 1318 reg |= TDMA_EN; 1319 else 1320 reg &= ~TDMA_EN; 1321 tdma_writel(priv, reg, TDMA_CONTROL); 1322 1323 /* Poll for TMDA disabling completion */ 1324 do { 1325 reg = tdma_readl(priv, TDMA_STATUS); 1326 if (!!(reg & TDMA_DISABLED) == !enable) 1327 return 0; 1328 1329 usleep_range(1000, 2000); 1330 } while (timeout-- > 0); 1331 1332 netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n"); 1333 1334 return -ETIMEDOUT; 1335 } 1336 1337 static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv) 1338 { 1339 struct bcm_sysport_cb *cb; 1340 u32 reg; 1341 int ret; 1342 int i; 1343 1344 /* Initialize SW view of the RX ring */ 1345 priv->num_rx_bds = NUM_RX_DESC; 1346 priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET; 1347 priv->rx_c_index = 0; 1348 priv->rx_read_ptr = 0; 1349 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb), 1350 GFP_KERNEL); 1351 if (!priv->rx_cbs) { 1352 netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); 1353 return -ENOMEM; 1354 } 1355 1356 for (i = 0; i < priv->num_rx_bds; i++) { 1357 cb = priv->rx_cbs + i; 1358 cb->bd_addr = priv->rx_bds + i * DESC_SIZE; 1359 } 1360 1361 ret = bcm_sysport_alloc_rx_bufs(priv); 1362 if (ret) { 1363 netif_err(priv, hw, priv->netdev, "SKB allocation failed\n"); 1364 return ret; 1365 } 1366 1367 /* Initialize HW, ensure RDMA is disabled */ 1368 reg = rdma_readl(priv, RDMA_STATUS); 1369 if (!(reg & RDMA_DISABLED)) 1370 rdma_enable_set(priv, 0); 1371 1372 rdma_writel(priv, 0, RDMA_WRITE_PTR_LO); 1373 rdma_writel(priv, 0, RDMA_WRITE_PTR_HI); 1374 rdma_writel(priv, 0, RDMA_PROD_INDEX); 1375 rdma_writel(priv, 0, RDMA_CONS_INDEX); 1376 rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT | 1377 RX_BUF_LENGTH, RDMA_RING_BUF_SIZE); 1378 /* Operate the queue in ring mode */ 1379 rdma_writel(priv, 0, RDMA_START_ADDR_HI); 1380 rdma_writel(priv, 0, RDMA_START_ADDR_LO); 1381 rdma_writel(priv, 0, RDMA_END_ADDR_HI); 1382 rdma_writel(priv, NUM_HW_RX_DESC_WORDS - 1, RDMA_END_ADDR_LO); 1383 1384 rdma_writel(priv, 1, RDMA_MBDONE_INTR); 1385 1386 netif_dbg(priv, hw, priv->netdev, 1387 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n", 1388 priv->num_rx_bds, priv->rx_bds); 1389 1390 return 0; 1391 } 1392 1393 static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv) 1394 { 1395 struct bcm_sysport_cb *cb; 1396 unsigned int i; 1397 u32 reg; 1398 1399 /* Caller should ensure RDMA is disabled */ 1400 reg = rdma_readl(priv, RDMA_STATUS); 1401 if (!(reg & RDMA_DISABLED)) 1402 netdev_warn(priv->netdev, "RDMA not stopped!\n"); 1403 1404 for (i = 0; i < priv->num_rx_bds; i++) { 1405 cb = &priv->rx_cbs[i]; 1406 if (dma_unmap_addr(cb, dma_addr)) 1407 dma_unmap_single(&priv->pdev->dev, 1408 dma_unmap_addr(cb, dma_addr), 1409 RX_BUF_LENGTH, DMA_FROM_DEVICE); 1410 bcm_sysport_free_cb(cb); 1411 } 1412 1413 kfree(priv->rx_cbs); 1414 priv->rx_cbs = NULL; 1415 1416 netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n"); 1417 } 1418 1419 static void bcm_sysport_set_rx_mode(struct net_device *dev) 1420 { 1421 struct bcm_sysport_priv *priv = netdev_priv(dev); 1422 u32 reg; 1423 1424 reg = umac_readl(priv, UMAC_CMD); 1425 if (dev->flags & IFF_PROMISC) 1426 reg |= CMD_PROMISC; 1427 else 1428 reg &= ~CMD_PROMISC; 1429 umac_writel(priv, reg, UMAC_CMD); 1430 1431 /* No support for ALLMULTI */ 1432 if (dev->flags & IFF_ALLMULTI) 1433 return; 1434 } 1435 1436 static inline void umac_enable_set(struct bcm_sysport_priv *priv, 1437 u32 mask, unsigned int enable) 1438 { 1439 u32 reg; 1440 1441 reg = umac_readl(priv, UMAC_CMD); 1442 if (enable) 1443 reg |= mask; 1444 else 1445 reg &= ~mask; 1446 umac_writel(priv, reg, UMAC_CMD); 1447 1448 /* UniMAC stops on a packet boundary, wait for a full-sized packet 1449 * to be processed (1 msec). 1450 */ 1451 if (enable == 0) 1452 usleep_range(1000, 2000); 1453 } 1454 1455 static inline void umac_reset(struct bcm_sysport_priv *priv) 1456 { 1457 u32 reg; 1458 1459 reg = umac_readl(priv, UMAC_CMD); 1460 reg |= CMD_SW_RESET; 1461 umac_writel(priv, reg, UMAC_CMD); 1462 udelay(10); 1463 reg = umac_readl(priv, UMAC_CMD); 1464 reg &= ~CMD_SW_RESET; 1465 umac_writel(priv, reg, UMAC_CMD); 1466 } 1467 1468 static void umac_set_hw_addr(struct bcm_sysport_priv *priv, 1469 unsigned char *addr) 1470 { 1471 umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | 1472 (addr[2] << 8) | addr[3], UMAC_MAC0); 1473 umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); 1474 } 1475 1476 static void topctrl_flush(struct bcm_sysport_priv *priv) 1477 { 1478 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); 1479 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); 1480 mdelay(1); 1481 topctrl_writel(priv, 0, RX_FLUSH_CNTL); 1482 topctrl_writel(priv, 0, TX_FLUSH_CNTL); 1483 } 1484 1485 static int bcm_sysport_change_mac(struct net_device *dev, void *p) 1486 { 1487 struct bcm_sysport_priv *priv = netdev_priv(dev); 1488 struct sockaddr *addr = p; 1489 1490 if (!is_valid_ether_addr(addr->sa_data)) 1491 return -EINVAL; 1492 1493 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 1494 1495 /* interface is disabled, changes to MAC will be reflected on next 1496 * open call 1497 */ 1498 if (!netif_running(dev)) 1499 return 0; 1500 1501 umac_set_hw_addr(priv, dev->dev_addr); 1502 1503 return 0; 1504 } 1505 1506 static void bcm_sysport_netif_start(struct net_device *dev) 1507 { 1508 struct bcm_sysport_priv *priv = netdev_priv(dev); 1509 1510 /* Enable NAPI */ 1511 napi_enable(&priv->napi); 1512 1513 /* Enable RX interrupt and TX ring full interrupt */ 1514 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); 1515 1516 phy_start(dev->phydev); 1517 1518 /* Enable TX interrupts for the 32 TXQs */ 1519 intrl2_1_mask_clear(priv, 0xffffffff); 1520 1521 /* Last call before we start the real business */ 1522 netif_tx_start_all_queues(dev); 1523 } 1524 1525 static void rbuf_init(struct bcm_sysport_priv *priv) 1526 { 1527 u32 reg; 1528 1529 reg = rbuf_readl(priv, RBUF_CONTROL); 1530 reg |= RBUF_4B_ALGN | RBUF_RSB_EN; 1531 rbuf_writel(priv, reg, RBUF_CONTROL); 1532 } 1533 1534 static int bcm_sysport_open(struct net_device *dev) 1535 { 1536 struct bcm_sysport_priv *priv = netdev_priv(dev); 1537 struct phy_device *phydev; 1538 unsigned int i; 1539 int ret; 1540 1541 /* Reset UniMAC */ 1542 umac_reset(priv); 1543 1544 /* Flush TX and RX FIFOs at TOPCTRL level */ 1545 topctrl_flush(priv); 1546 1547 /* Disable the UniMAC RX/TX */ 1548 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0); 1549 1550 /* Enable RBUF 2bytes alignment and Receive Status Block */ 1551 rbuf_init(priv); 1552 1553 /* Set maximum frame length */ 1554 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 1555 1556 /* Set MAC address */ 1557 umac_set_hw_addr(priv, dev->dev_addr); 1558 1559 /* Read CRC forward */ 1560 priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD); 1561 1562 phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link, 1563 0, priv->phy_interface); 1564 if (!phydev) { 1565 netdev_err(dev, "could not attach to PHY\n"); 1566 return -ENODEV; 1567 } 1568 1569 /* Reset house keeping link status */ 1570 priv->old_duplex = -1; 1571 priv->old_link = -1; 1572 priv->old_pause = -1; 1573 1574 /* mask all interrupts and request them */ 1575 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET); 1576 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1577 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); 1578 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET); 1579 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1580 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); 1581 1582 ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev); 1583 if (ret) { 1584 netdev_err(dev, "failed to request RX interrupt\n"); 1585 goto out_phy_disconnect; 1586 } 1587 1588 ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, dev->name, dev); 1589 if (ret) { 1590 netdev_err(dev, "failed to request TX interrupt\n"); 1591 goto out_free_irq0; 1592 } 1593 1594 /* Initialize both hardware and software ring */ 1595 for (i = 0; i < dev->num_tx_queues; i++) { 1596 ret = bcm_sysport_init_tx_ring(priv, i); 1597 if (ret) { 1598 netdev_err(dev, "failed to initialize TX ring %d\n", 1599 i); 1600 goto out_free_tx_ring; 1601 } 1602 } 1603 1604 /* Initialize linked-list */ 1605 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); 1606 1607 /* Initialize RX ring */ 1608 ret = bcm_sysport_init_rx_ring(priv); 1609 if (ret) { 1610 netdev_err(dev, "failed to initialize RX ring\n"); 1611 goto out_free_rx_ring; 1612 } 1613 1614 /* Turn on RDMA */ 1615 ret = rdma_enable_set(priv, 1); 1616 if (ret) 1617 goto out_free_rx_ring; 1618 1619 /* Turn on TDMA */ 1620 ret = tdma_enable_set(priv, 1); 1621 if (ret) 1622 goto out_clear_rx_int; 1623 1624 /* Turn on UniMAC TX/RX */ 1625 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1); 1626 1627 bcm_sysport_netif_start(dev); 1628 1629 return 0; 1630 1631 out_clear_rx_int: 1632 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); 1633 out_free_rx_ring: 1634 bcm_sysport_fini_rx_ring(priv); 1635 out_free_tx_ring: 1636 for (i = 0; i < dev->num_tx_queues; i++) 1637 bcm_sysport_fini_tx_ring(priv, i); 1638 free_irq(priv->irq1, dev); 1639 out_free_irq0: 1640 free_irq(priv->irq0, dev); 1641 out_phy_disconnect: 1642 phy_disconnect(phydev); 1643 return ret; 1644 } 1645 1646 static void bcm_sysport_netif_stop(struct net_device *dev) 1647 { 1648 struct bcm_sysport_priv *priv = netdev_priv(dev); 1649 1650 /* stop all software from updating hardware */ 1651 netif_tx_stop_all_queues(dev); 1652 napi_disable(&priv->napi); 1653 phy_stop(dev->phydev); 1654 1655 /* mask all interrupts */ 1656 intrl2_0_mask_set(priv, 0xffffffff); 1657 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1658 intrl2_1_mask_set(priv, 0xffffffff); 1659 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1660 } 1661 1662 static int bcm_sysport_stop(struct net_device *dev) 1663 { 1664 struct bcm_sysport_priv *priv = netdev_priv(dev); 1665 unsigned int i; 1666 int ret; 1667 1668 bcm_sysport_netif_stop(dev); 1669 1670 /* Disable UniMAC RX */ 1671 umac_enable_set(priv, CMD_RX_EN, 0); 1672 1673 ret = tdma_enable_set(priv, 0); 1674 if (ret) { 1675 netdev_err(dev, "timeout disabling RDMA\n"); 1676 return ret; 1677 } 1678 1679 /* Wait for a maximum packet size to be drained */ 1680 usleep_range(2000, 3000); 1681 1682 ret = rdma_enable_set(priv, 0); 1683 if (ret) { 1684 netdev_err(dev, "timeout disabling TDMA\n"); 1685 return ret; 1686 } 1687 1688 /* Disable UniMAC TX */ 1689 umac_enable_set(priv, CMD_TX_EN, 0); 1690 1691 /* Free RX/TX rings SW structures */ 1692 for (i = 0; i < dev->num_tx_queues; i++) 1693 bcm_sysport_fini_tx_ring(priv, i); 1694 bcm_sysport_fini_rx_ring(priv); 1695 1696 free_irq(priv->irq0, dev); 1697 free_irq(priv->irq1, dev); 1698 1699 /* Disconnect from PHY */ 1700 phy_disconnect(dev->phydev); 1701 1702 return 0; 1703 } 1704 1705 static const struct ethtool_ops bcm_sysport_ethtool_ops = { 1706 .get_drvinfo = bcm_sysport_get_drvinfo, 1707 .get_msglevel = bcm_sysport_get_msglvl, 1708 .set_msglevel = bcm_sysport_set_msglvl, 1709 .get_link = ethtool_op_get_link, 1710 .get_strings = bcm_sysport_get_strings, 1711 .get_ethtool_stats = bcm_sysport_get_stats, 1712 .get_sset_count = bcm_sysport_get_sset_count, 1713 .get_wol = bcm_sysport_get_wol, 1714 .set_wol = bcm_sysport_set_wol, 1715 .get_coalesce = bcm_sysport_get_coalesce, 1716 .set_coalesce = bcm_sysport_set_coalesce, 1717 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1718 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1719 }; 1720 1721 static const struct net_device_ops bcm_sysport_netdev_ops = { 1722 .ndo_start_xmit = bcm_sysport_xmit, 1723 .ndo_tx_timeout = bcm_sysport_tx_timeout, 1724 .ndo_open = bcm_sysport_open, 1725 .ndo_stop = bcm_sysport_stop, 1726 .ndo_set_features = bcm_sysport_set_features, 1727 .ndo_set_rx_mode = bcm_sysport_set_rx_mode, 1728 .ndo_set_mac_address = bcm_sysport_change_mac, 1729 #ifdef CONFIG_NET_POLL_CONTROLLER 1730 .ndo_poll_controller = bcm_sysport_poll_controller, 1731 #endif 1732 }; 1733 1734 #define REV_FMT "v%2x.%02x" 1735 1736 static int bcm_sysport_probe(struct platform_device *pdev) 1737 { 1738 struct bcm_sysport_priv *priv; 1739 struct device_node *dn; 1740 struct net_device *dev; 1741 const void *macaddr; 1742 struct resource *r; 1743 u32 txq, rxq; 1744 int ret; 1745 1746 dn = pdev->dev.of_node; 1747 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1748 1749 /* Read the Transmit/Receive Queue properties */ 1750 if (of_property_read_u32(dn, "systemport,num-txq", &txq)) 1751 txq = TDMA_NUM_RINGS; 1752 if (of_property_read_u32(dn, "systemport,num-rxq", &rxq)) 1753 rxq = 1; 1754 1755 dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq); 1756 if (!dev) 1757 return -ENOMEM; 1758 1759 /* Initialize private members */ 1760 priv = netdev_priv(dev); 1761 1762 priv->irq0 = platform_get_irq(pdev, 0); 1763 priv->irq1 = platform_get_irq(pdev, 1); 1764 priv->wol_irq = platform_get_irq(pdev, 2); 1765 if (priv->irq0 <= 0 || priv->irq1 <= 0) { 1766 dev_err(&pdev->dev, "invalid interrupts\n"); 1767 ret = -EINVAL; 1768 goto err_free_netdev; 1769 } 1770 1771 priv->base = devm_ioremap_resource(&pdev->dev, r); 1772 if (IS_ERR(priv->base)) { 1773 ret = PTR_ERR(priv->base); 1774 goto err_free_netdev; 1775 } 1776 1777 priv->netdev = dev; 1778 priv->pdev = pdev; 1779 1780 priv->phy_interface = of_get_phy_mode(dn); 1781 /* Default to GMII interface mode */ 1782 if (priv->phy_interface < 0) 1783 priv->phy_interface = PHY_INTERFACE_MODE_GMII; 1784 1785 /* In the case of a fixed PHY, the DT node associated 1786 * to the PHY is the Ethernet MAC DT node. 1787 */ 1788 if (of_phy_is_fixed_link(dn)) { 1789 ret = of_phy_register_fixed_link(dn); 1790 if (ret) { 1791 dev_err(&pdev->dev, "failed to register fixed PHY\n"); 1792 goto err_free_netdev; 1793 } 1794 1795 priv->phy_dn = dn; 1796 } 1797 1798 /* Initialize netdevice members */ 1799 macaddr = of_get_mac_address(dn); 1800 if (!macaddr || !is_valid_ether_addr(macaddr)) { 1801 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 1802 eth_hw_addr_random(dev); 1803 } else { 1804 ether_addr_copy(dev->dev_addr, macaddr); 1805 } 1806 1807 SET_NETDEV_DEV(dev, &pdev->dev); 1808 dev_set_drvdata(&pdev->dev, dev); 1809 dev->ethtool_ops = &bcm_sysport_ethtool_ops; 1810 dev->netdev_ops = &bcm_sysport_netdev_ops; 1811 netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64); 1812 1813 /* HW supported features, none enabled by default */ 1814 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA | 1815 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1816 1817 /* Request the WOL interrupt and advertise suspend if available */ 1818 priv->wol_irq_disabled = 1; 1819 ret = devm_request_irq(&pdev->dev, priv->wol_irq, 1820 bcm_sysport_wol_isr, 0, dev->name, priv); 1821 if (!ret) 1822 device_set_wakeup_capable(&pdev->dev, 1); 1823 1824 /* Set the needed headroom once and for all */ 1825 BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8); 1826 dev->needed_headroom += sizeof(struct bcm_tsb); 1827 1828 /* libphy will adjust the link state accordingly */ 1829 netif_carrier_off(dev); 1830 1831 ret = register_netdev(dev); 1832 if (ret) { 1833 dev_err(&pdev->dev, "failed to register net_device\n"); 1834 goto err_deregister_fixed_link; 1835 } 1836 1837 priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK; 1838 dev_info(&pdev->dev, 1839 "Broadcom SYSTEMPORT" REV_FMT 1840 " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n", 1841 (priv->rev >> 8) & 0xff, priv->rev & 0xff, 1842 priv->base, priv->irq0, priv->irq1, txq, rxq); 1843 1844 return 0; 1845 1846 err_deregister_fixed_link: 1847 if (of_phy_is_fixed_link(dn)) 1848 of_phy_deregister_fixed_link(dn); 1849 err_free_netdev: 1850 free_netdev(dev); 1851 return ret; 1852 } 1853 1854 static int bcm_sysport_remove(struct platform_device *pdev) 1855 { 1856 struct net_device *dev = dev_get_drvdata(&pdev->dev); 1857 struct device_node *dn = pdev->dev.of_node; 1858 1859 /* Not much to do, ndo_close has been called 1860 * and we use managed allocations 1861 */ 1862 unregister_netdev(dev); 1863 if (of_phy_is_fixed_link(dn)) 1864 of_phy_deregister_fixed_link(dn); 1865 free_netdev(dev); 1866 dev_set_drvdata(&pdev->dev, NULL); 1867 1868 return 0; 1869 } 1870 1871 #ifdef CONFIG_PM_SLEEP 1872 static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv) 1873 { 1874 struct net_device *ndev = priv->netdev; 1875 unsigned int timeout = 1000; 1876 u32 reg; 1877 1878 /* Password has already been programmed */ 1879 reg = umac_readl(priv, UMAC_MPD_CTRL); 1880 reg |= MPD_EN; 1881 reg &= ~PSW_EN; 1882 if (priv->wolopts & WAKE_MAGICSECURE) 1883 reg |= PSW_EN; 1884 umac_writel(priv, reg, UMAC_MPD_CTRL); 1885 1886 /* Make sure RBUF entered WoL mode as result */ 1887 do { 1888 reg = rbuf_readl(priv, RBUF_STATUS); 1889 if (reg & RBUF_WOL_MODE) 1890 break; 1891 1892 udelay(10); 1893 } while (timeout-- > 0); 1894 1895 /* Do not leave the UniMAC RBUF matching only MPD packets */ 1896 if (!timeout) { 1897 reg = umac_readl(priv, UMAC_MPD_CTRL); 1898 reg &= ~MPD_EN; 1899 umac_writel(priv, reg, UMAC_MPD_CTRL); 1900 netif_err(priv, wol, ndev, "failed to enter WOL mode\n"); 1901 return -ETIMEDOUT; 1902 } 1903 1904 /* UniMAC receive needs to be turned on */ 1905 umac_enable_set(priv, CMD_RX_EN, 1); 1906 1907 /* Enable the interrupt wake-up source */ 1908 intrl2_0_mask_clear(priv, INTRL2_0_MPD); 1909 1910 netif_dbg(priv, wol, ndev, "entered WOL mode\n"); 1911 1912 return 0; 1913 } 1914 1915 static int bcm_sysport_suspend(struct device *d) 1916 { 1917 struct net_device *dev = dev_get_drvdata(d); 1918 struct bcm_sysport_priv *priv = netdev_priv(dev); 1919 unsigned int i; 1920 int ret = 0; 1921 u32 reg; 1922 1923 if (!netif_running(dev)) 1924 return 0; 1925 1926 bcm_sysport_netif_stop(dev); 1927 1928 phy_suspend(dev->phydev); 1929 1930 netif_device_detach(dev); 1931 1932 /* Disable UniMAC RX */ 1933 umac_enable_set(priv, CMD_RX_EN, 0); 1934 1935 ret = rdma_enable_set(priv, 0); 1936 if (ret) { 1937 netdev_err(dev, "RDMA timeout!\n"); 1938 return ret; 1939 } 1940 1941 /* Disable RXCHK if enabled */ 1942 if (priv->rx_chk_en) { 1943 reg = rxchk_readl(priv, RXCHK_CONTROL); 1944 reg &= ~RXCHK_EN; 1945 rxchk_writel(priv, reg, RXCHK_CONTROL); 1946 } 1947 1948 /* Flush RX pipe */ 1949 if (!priv->wolopts) 1950 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); 1951 1952 ret = tdma_enable_set(priv, 0); 1953 if (ret) { 1954 netdev_err(dev, "TDMA timeout!\n"); 1955 return ret; 1956 } 1957 1958 /* Wait for a packet boundary */ 1959 usleep_range(2000, 3000); 1960 1961 umac_enable_set(priv, CMD_TX_EN, 0); 1962 1963 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); 1964 1965 /* Free RX/TX rings SW structures */ 1966 for (i = 0; i < dev->num_tx_queues; i++) 1967 bcm_sysport_fini_tx_ring(priv, i); 1968 bcm_sysport_fini_rx_ring(priv); 1969 1970 /* Get prepared for Wake-on-LAN */ 1971 if (device_may_wakeup(d) && priv->wolopts) 1972 ret = bcm_sysport_suspend_to_wol(priv); 1973 1974 return ret; 1975 } 1976 1977 static int bcm_sysport_resume(struct device *d) 1978 { 1979 struct net_device *dev = dev_get_drvdata(d); 1980 struct bcm_sysport_priv *priv = netdev_priv(dev); 1981 unsigned int i; 1982 u32 reg; 1983 int ret; 1984 1985 if (!netif_running(dev)) 1986 return 0; 1987 1988 umac_reset(priv); 1989 1990 /* We may have been suspended and never received a WOL event that 1991 * would turn off MPD detection, take care of that now 1992 */ 1993 bcm_sysport_resume_from_wol(priv); 1994 1995 /* Initialize both hardware and software ring */ 1996 for (i = 0; i < dev->num_tx_queues; i++) { 1997 ret = bcm_sysport_init_tx_ring(priv, i); 1998 if (ret) { 1999 netdev_err(dev, "failed to initialize TX ring %d\n", 2000 i); 2001 goto out_free_tx_rings; 2002 } 2003 } 2004 2005 /* Initialize linked-list */ 2006 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); 2007 2008 /* Initialize RX ring */ 2009 ret = bcm_sysport_init_rx_ring(priv); 2010 if (ret) { 2011 netdev_err(dev, "failed to initialize RX ring\n"); 2012 goto out_free_rx_ring; 2013 } 2014 2015 netif_device_attach(dev); 2016 2017 /* RX pipe enable */ 2018 topctrl_writel(priv, 0, RX_FLUSH_CNTL); 2019 2020 ret = rdma_enable_set(priv, 1); 2021 if (ret) { 2022 netdev_err(dev, "failed to enable RDMA\n"); 2023 goto out_free_rx_ring; 2024 } 2025 2026 /* Enable rxhck */ 2027 if (priv->rx_chk_en) { 2028 reg = rxchk_readl(priv, RXCHK_CONTROL); 2029 reg |= RXCHK_EN; 2030 rxchk_writel(priv, reg, RXCHK_CONTROL); 2031 } 2032 2033 rbuf_init(priv); 2034 2035 /* Set maximum frame length */ 2036 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2037 2038 /* Set MAC address */ 2039 umac_set_hw_addr(priv, dev->dev_addr); 2040 2041 umac_enable_set(priv, CMD_RX_EN, 1); 2042 2043 /* TX pipe enable */ 2044 topctrl_writel(priv, 0, TX_FLUSH_CNTL); 2045 2046 umac_enable_set(priv, CMD_TX_EN, 1); 2047 2048 ret = tdma_enable_set(priv, 1); 2049 if (ret) { 2050 netdev_err(dev, "TDMA timeout!\n"); 2051 goto out_free_rx_ring; 2052 } 2053 2054 phy_resume(dev->phydev); 2055 2056 bcm_sysport_netif_start(dev); 2057 2058 return 0; 2059 2060 out_free_rx_ring: 2061 bcm_sysport_fini_rx_ring(priv); 2062 out_free_tx_rings: 2063 for (i = 0; i < dev->num_tx_queues; i++) 2064 bcm_sysport_fini_tx_ring(priv, i); 2065 return ret; 2066 } 2067 #endif 2068 2069 static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops, 2070 bcm_sysport_suspend, bcm_sysport_resume); 2071 2072 static const struct of_device_id bcm_sysport_of_match[] = { 2073 { .compatible = "brcm,systemport-v1.00" }, 2074 { .compatible = "brcm,systemport" }, 2075 { /* sentinel */ } 2076 }; 2077 MODULE_DEVICE_TABLE(of, bcm_sysport_of_match); 2078 2079 static struct platform_driver bcm_sysport_driver = { 2080 .probe = bcm_sysport_probe, 2081 .remove = bcm_sysport_remove, 2082 .driver = { 2083 .name = "brcm-systemport", 2084 .of_match_table = bcm_sysport_of_match, 2085 .pm = &bcm_sysport_pm_ops, 2086 }, 2087 }; 2088 module_platform_driver(bcm_sysport_driver); 2089 2090 MODULE_AUTHOR("Broadcom Corporation"); 2091 MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver"); 2092 MODULE_ALIAS("platform:brcm-systemport"); 2093 MODULE_LICENSE("GPL"); 2094