1 /* 2 * Broadcom BCM7xxx System Port Ethernet MAC driver 3 * 4 * Copyright (C) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/netdevice.h> 18 #include <linux/etherdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/phy.h> 24 #include <linux/phy_fixed.h> 25 #include <net/dsa.h> 26 #include <net/ip.h> 27 #include <net/ipv6.h> 28 29 #include "bcmsysport.h" 30 31 /* I/O accessors register helpers */ 32 #define BCM_SYSPORT_IO_MACRO(name, offset) \ 33 static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \ 34 { \ 35 u32 reg = __raw_readl(priv->base + offset + off); \ 36 return reg; \ 37 } \ 38 static inline void name##_writel(struct bcm_sysport_priv *priv, \ 39 u32 val, u32 off) \ 40 { \ 41 __raw_writel(val, priv->base + offset + off); \ 42 } \ 43 44 BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET); 45 BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET); 46 BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET); 47 BCM_SYSPORT_IO_MACRO(gib, SYS_PORT_GIB_OFFSET); 48 BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET); 49 BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET); 50 BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET); 51 BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET); 52 BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET); 53 BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET); 54 55 /* On SYSTEMPORT Lite, any register after RDMA_STATUS has the exact 56 * same layout, except it has been moved by 4 bytes up, *sigh* 57 */ 58 static inline u32 rdma_readl(struct bcm_sysport_priv *priv, u32 off) 59 { 60 if (priv->is_lite && off >= RDMA_STATUS) 61 off += 4; 62 return __raw_readl(priv->base + SYS_PORT_RDMA_OFFSET + off); 63 } 64 65 static inline void rdma_writel(struct bcm_sysport_priv *priv, u32 val, u32 off) 66 { 67 if (priv->is_lite && off >= RDMA_STATUS) 68 off += 4; 69 __raw_writel(val, priv->base + SYS_PORT_RDMA_OFFSET + off); 70 } 71 72 static inline u32 tdma_control_bit(struct bcm_sysport_priv *priv, u32 bit) 73 { 74 if (!priv->is_lite) { 75 return BIT(bit); 76 } else { 77 if (bit >= ACB_ALGO) 78 return BIT(bit + 1); 79 else 80 return BIT(bit); 81 } 82 } 83 84 /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied 85 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths. 86 */ 87 #define BCM_SYSPORT_INTR_L2(which) \ 88 static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \ 89 u32 mask) \ 90 { \ 91 priv->irq##which##_mask &= ~(mask); \ 92 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \ 93 } \ 94 static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \ 95 u32 mask) \ 96 { \ 97 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \ 98 priv->irq##which##_mask |= (mask); \ 99 } \ 100 101 BCM_SYSPORT_INTR_L2(0) 102 BCM_SYSPORT_INTR_L2(1) 103 104 /* Register accesses to GISB/RBUS registers are expensive (few hundred 105 * nanoseconds), so keep the check for 64-bits explicit here to save 106 * one register write per-packet on 32-bits platforms. 107 */ 108 static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv, 109 void __iomem *d, 110 dma_addr_t addr) 111 { 112 #ifdef CONFIG_PHYS_ADDR_T_64BIT 113 __raw_writel(upper_32_bits(addr) & DESC_ADDR_HI_MASK, 114 d + DESC_ADDR_HI_STATUS_LEN); 115 #endif 116 __raw_writel(lower_32_bits(addr), d + DESC_ADDR_LO); 117 } 118 119 static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv, 120 struct dma_desc *desc, 121 unsigned int port) 122 { 123 /* Ports are latched, so write upper address first */ 124 tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port)); 125 tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port)); 126 } 127 128 /* Ethtool operations */ 129 static int bcm_sysport_set_rx_csum(struct net_device *dev, 130 netdev_features_t wanted) 131 { 132 struct bcm_sysport_priv *priv = netdev_priv(dev); 133 u32 reg; 134 135 priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM); 136 reg = rxchk_readl(priv, RXCHK_CONTROL); 137 if (priv->rx_chk_en) 138 reg |= RXCHK_EN; 139 else 140 reg &= ~RXCHK_EN; 141 142 /* If UniMAC forwards CRC, we need to skip over it to get 143 * a valid CHK bit to be set in the per-packet status word 144 */ 145 if (priv->rx_chk_en && priv->crc_fwd) 146 reg |= RXCHK_SKIP_FCS; 147 else 148 reg &= ~RXCHK_SKIP_FCS; 149 150 /* If Broadcom tags are enabled (e.g: using a switch), make 151 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom 152 * tag after the Ethernet MAC Source Address. 153 */ 154 if (netdev_uses_dsa(dev)) 155 reg |= RXCHK_BRCM_TAG_EN; 156 else 157 reg &= ~RXCHK_BRCM_TAG_EN; 158 159 rxchk_writel(priv, reg, RXCHK_CONTROL); 160 161 return 0; 162 } 163 164 static int bcm_sysport_set_tx_csum(struct net_device *dev, 165 netdev_features_t wanted) 166 { 167 struct bcm_sysport_priv *priv = netdev_priv(dev); 168 u32 reg; 169 170 /* Hardware transmit checksum requires us to enable the Transmit status 171 * block prepended to the packet contents 172 */ 173 priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 174 reg = tdma_readl(priv, TDMA_CONTROL); 175 if (priv->tsb_en) 176 reg |= tdma_control_bit(priv, TSB_EN); 177 else 178 reg &= ~tdma_control_bit(priv, TSB_EN); 179 tdma_writel(priv, reg, TDMA_CONTROL); 180 181 return 0; 182 } 183 184 static int bcm_sysport_set_features(struct net_device *dev, 185 netdev_features_t features) 186 { 187 netdev_features_t changed = features ^ dev->features; 188 netdev_features_t wanted = dev->wanted_features; 189 int ret = 0; 190 191 if (changed & NETIF_F_RXCSUM) 192 ret = bcm_sysport_set_rx_csum(dev, wanted); 193 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) 194 ret = bcm_sysport_set_tx_csum(dev, wanted); 195 196 return ret; 197 } 198 199 /* Hardware counters must be kept in sync because the order/offset 200 * is important here (order in structure declaration = order in hardware) 201 */ 202 static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = { 203 /* general stats */ 204 STAT_NETDEV(rx_packets), 205 STAT_NETDEV(tx_packets), 206 STAT_NETDEV(rx_bytes), 207 STAT_NETDEV(tx_bytes), 208 STAT_NETDEV(rx_errors), 209 STAT_NETDEV(tx_errors), 210 STAT_NETDEV(rx_dropped), 211 STAT_NETDEV(tx_dropped), 212 STAT_NETDEV(multicast), 213 /* UniMAC RSV counters */ 214 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 215 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 216 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 217 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 218 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 219 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 220 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 221 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 222 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 223 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 224 STAT_MIB_RX("rx_pkts", mib.rx.pkt), 225 STAT_MIB_RX("rx_bytes", mib.rx.bytes), 226 STAT_MIB_RX("rx_multicast", mib.rx.mca), 227 STAT_MIB_RX("rx_broadcast", mib.rx.bca), 228 STAT_MIB_RX("rx_fcs", mib.rx.fcs), 229 STAT_MIB_RX("rx_control", mib.rx.cf), 230 STAT_MIB_RX("rx_pause", mib.rx.pf), 231 STAT_MIB_RX("rx_unknown", mib.rx.uo), 232 STAT_MIB_RX("rx_align", mib.rx.aln), 233 STAT_MIB_RX("rx_outrange", mib.rx.flr), 234 STAT_MIB_RX("rx_code", mib.rx.cde), 235 STAT_MIB_RX("rx_carrier", mib.rx.fcr), 236 STAT_MIB_RX("rx_oversize", mib.rx.ovr), 237 STAT_MIB_RX("rx_jabber", mib.rx.jbr), 238 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue), 239 STAT_MIB_RX("rx_good_pkts", mib.rx.pok), 240 STAT_MIB_RX("rx_unicast", mib.rx.uc), 241 STAT_MIB_RX("rx_ppp", mib.rx.ppp), 242 STAT_MIB_RX("rx_crc", mib.rx.rcrc), 243 /* UniMAC TSV counters */ 244 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 245 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 246 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 247 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 248 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 249 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 250 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 251 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 252 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 253 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 254 STAT_MIB_TX("tx_pkts", mib.tx.pkts), 255 STAT_MIB_TX("tx_multicast", mib.tx.mca), 256 STAT_MIB_TX("tx_broadcast", mib.tx.bca), 257 STAT_MIB_TX("tx_pause", mib.tx.pf), 258 STAT_MIB_TX("tx_control", mib.tx.cf), 259 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs), 260 STAT_MIB_TX("tx_oversize", mib.tx.ovr), 261 STAT_MIB_TX("tx_defer", mib.tx.drf), 262 STAT_MIB_TX("tx_excess_defer", mib.tx.edf), 263 STAT_MIB_TX("tx_single_col", mib.tx.scl), 264 STAT_MIB_TX("tx_multi_col", mib.tx.mcl), 265 STAT_MIB_TX("tx_late_col", mib.tx.lcl), 266 STAT_MIB_TX("tx_excess_col", mib.tx.ecl), 267 STAT_MIB_TX("tx_frags", mib.tx.frg), 268 STAT_MIB_TX("tx_total_col", mib.tx.ncl), 269 STAT_MIB_TX("tx_jabber", mib.tx.jbr), 270 STAT_MIB_TX("tx_bytes", mib.tx.bytes), 271 STAT_MIB_TX("tx_good_pkts", mib.tx.pok), 272 STAT_MIB_TX("tx_unicast", mib.tx.uc), 273 /* UniMAC RUNT counters */ 274 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 275 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 276 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 277 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 278 /* RXCHK misc statistics */ 279 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR), 280 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc, 281 RXCHK_OTHER_DISC_CNTR), 282 /* RBUF misc statistics */ 283 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR), 284 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR), 285 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 286 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed), 287 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed), 288 /* Per TX-queue statistics are dynamically appended */ 289 }; 290 291 #define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats) 292 293 static void bcm_sysport_get_drvinfo(struct net_device *dev, 294 struct ethtool_drvinfo *info) 295 { 296 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 297 strlcpy(info->version, "0.1", sizeof(info->version)); 298 strlcpy(info->bus_info, "platform", sizeof(info->bus_info)); 299 } 300 301 static u32 bcm_sysport_get_msglvl(struct net_device *dev) 302 { 303 struct bcm_sysport_priv *priv = netdev_priv(dev); 304 305 return priv->msg_enable; 306 } 307 308 static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable) 309 { 310 struct bcm_sysport_priv *priv = netdev_priv(dev); 311 312 priv->msg_enable = enable; 313 } 314 315 static inline bool bcm_sysport_lite_stat_valid(enum bcm_sysport_stat_type type) 316 { 317 switch (type) { 318 case BCM_SYSPORT_STAT_NETDEV: 319 case BCM_SYSPORT_STAT_RXCHK: 320 case BCM_SYSPORT_STAT_RBUF: 321 case BCM_SYSPORT_STAT_SOFT: 322 return true; 323 default: 324 return false; 325 } 326 } 327 328 static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set) 329 { 330 struct bcm_sysport_priv *priv = netdev_priv(dev); 331 const struct bcm_sysport_stats *s; 332 unsigned int i, j; 333 334 switch (string_set) { 335 case ETH_SS_STATS: 336 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 337 s = &bcm_sysport_gstrings_stats[i]; 338 if (priv->is_lite && 339 !bcm_sysport_lite_stat_valid(s->type)) 340 continue; 341 j++; 342 } 343 /* Include per-queue statistics */ 344 return j + dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT; 345 default: 346 return -EOPNOTSUPP; 347 } 348 } 349 350 static void bcm_sysport_get_strings(struct net_device *dev, 351 u32 stringset, u8 *data) 352 { 353 struct bcm_sysport_priv *priv = netdev_priv(dev); 354 const struct bcm_sysport_stats *s; 355 char buf[128]; 356 int i, j; 357 358 switch (stringset) { 359 case ETH_SS_STATS: 360 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 361 s = &bcm_sysport_gstrings_stats[i]; 362 if (priv->is_lite && 363 !bcm_sysport_lite_stat_valid(s->type)) 364 continue; 365 366 memcpy(data + j * ETH_GSTRING_LEN, s->stat_string, 367 ETH_GSTRING_LEN); 368 j++; 369 } 370 371 for (i = 0; i < dev->num_tx_queues; i++) { 372 snprintf(buf, sizeof(buf), "txq%d_packets", i); 373 memcpy(data + j * ETH_GSTRING_LEN, buf, 374 ETH_GSTRING_LEN); 375 j++; 376 377 snprintf(buf, sizeof(buf), "txq%d_bytes", i); 378 memcpy(data + j * ETH_GSTRING_LEN, buf, 379 ETH_GSTRING_LEN); 380 j++; 381 } 382 break; 383 default: 384 break; 385 } 386 } 387 388 static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv) 389 { 390 int i, j = 0; 391 392 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 393 const struct bcm_sysport_stats *s; 394 u8 offset = 0; 395 u32 val = 0; 396 char *p; 397 398 s = &bcm_sysport_gstrings_stats[i]; 399 switch (s->type) { 400 case BCM_SYSPORT_STAT_NETDEV: 401 case BCM_SYSPORT_STAT_SOFT: 402 continue; 403 case BCM_SYSPORT_STAT_MIB_RX: 404 case BCM_SYSPORT_STAT_MIB_TX: 405 case BCM_SYSPORT_STAT_RUNT: 406 if (priv->is_lite) 407 continue; 408 409 if (s->type != BCM_SYSPORT_STAT_MIB_RX) 410 offset = UMAC_MIB_STAT_OFFSET; 411 val = umac_readl(priv, UMAC_MIB_START + j + offset); 412 break; 413 case BCM_SYSPORT_STAT_RXCHK: 414 val = rxchk_readl(priv, s->reg_offset); 415 if (val == ~0) 416 rxchk_writel(priv, 0, s->reg_offset); 417 break; 418 case BCM_SYSPORT_STAT_RBUF: 419 val = rbuf_readl(priv, s->reg_offset); 420 if (val == ~0) 421 rbuf_writel(priv, 0, s->reg_offset); 422 break; 423 } 424 425 j += s->stat_sizeof; 426 p = (char *)priv + s->stat_offset; 427 *(u32 *)p = val; 428 } 429 430 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n"); 431 } 432 433 static void bcm_sysport_get_stats(struct net_device *dev, 434 struct ethtool_stats *stats, u64 *data) 435 { 436 struct bcm_sysport_priv *priv = netdev_priv(dev); 437 struct bcm_sysport_tx_ring *ring; 438 int i, j; 439 440 if (netif_running(dev)) 441 bcm_sysport_update_mib_counters(priv); 442 443 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 444 const struct bcm_sysport_stats *s; 445 char *p; 446 447 s = &bcm_sysport_gstrings_stats[i]; 448 if (s->type == BCM_SYSPORT_STAT_NETDEV) 449 p = (char *)&dev->stats; 450 else 451 p = (char *)priv; 452 453 if (priv->is_lite && !bcm_sysport_lite_stat_valid(s->type)) 454 continue; 455 456 p += s->stat_offset; 457 data[j] = *(unsigned long *)p; 458 j++; 459 } 460 461 /* For SYSTEMPORT Lite since we have holes in our statistics, j would 462 * be equal to BCM_SYSPORT_STATS_LEN at the end of the loop, but it 463 * needs to point to how many total statistics we have minus the 464 * number of per TX queue statistics 465 */ 466 j = bcm_sysport_get_sset_count(dev, ETH_SS_STATS) - 467 dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT; 468 469 for (i = 0; i < dev->num_tx_queues; i++) { 470 ring = &priv->tx_rings[i]; 471 data[j] = ring->packets; 472 j++; 473 data[j] = ring->bytes; 474 j++; 475 } 476 } 477 478 static void bcm_sysport_get_wol(struct net_device *dev, 479 struct ethtool_wolinfo *wol) 480 { 481 struct bcm_sysport_priv *priv = netdev_priv(dev); 482 u32 reg; 483 484 wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE; 485 wol->wolopts = priv->wolopts; 486 487 if (!(priv->wolopts & WAKE_MAGICSECURE)) 488 return; 489 490 /* Return the programmed SecureOn password */ 491 reg = umac_readl(priv, UMAC_PSW_MS); 492 put_unaligned_be16(reg, &wol->sopass[0]); 493 reg = umac_readl(priv, UMAC_PSW_LS); 494 put_unaligned_be32(reg, &wol->sopass[2]); 495 } 496 497 static int bcm_sysport_set_wol(struct net_device *dev, 498 struct ethtool_wolinfo *wol) 499 { 500 struct bcm_sysport_priv *priv = netdev_priv(dev); 501 struct device *kdev = &priv->pdev->dev; 502 u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE; 503 504 if (!device_can_wakeup(kdev)) 505 return -ENOTSUPP; 506 507 if (wol->wolopts & ~supported) 508 return -EINVAL; 509 510 /* Program the SecureOn password */ 511 if (wol->wolopts & WAKE_MAGICSECURE) { 512 umac_writel(priv, get_unaligned_be16(&wol->sopass[0]), 513 UMAC_PSW_MS); 514 umac_writel(priv, get_unaligned_be32(&wol->sopass[2]), 515 UMAC_PSW_LS); 516 } 517 518 /* Flag the device and relevant IRQ as wakeup capable */ 519 if (wol->wolopts) { 520 device_set_wakeup_enable(kdev, 1); 521 if (priv->wol_irq_disabled) 522 enable_irq_wake(priv->wol_irq); 523 priv->wol_irq_disabled = 0; 524 } else { 525 device_set_wakeup_enable(kdev, 0); 526 /* Avoid unbalanced disable_irq_wake calls */ 527 if (!priv->wol_irq_disabled) 528 disable_irq_wake(priv->wol_irq); 529 priv->wol_irq_disabled = 1; 530 } 531 532 priv->wolopts = wol->wolopts; 533 534 return 0; 535 } 536 537 static int bcm_sysport_get_coalesce(struct net_device *dev, 538 struct ethtool_coalesce *ec) 539 { 540 struct bcm_sysport_priv *priv = netdev_priv(dev); 541 u32 reg; 542 543 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0)); 544 545 ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000; 546 ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK; 547 548 reg = rdma_readl(priv, RDMA_MBDONE_INTR); 549 550 ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000; 551 ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK; 552 553 return 0; 554 } 555 556 static int bcm_sysport_set_coalesce(struct net_device *dev, 557 struct ethtool_coalesce *ec) 558 { 559 struct bcm_sysport_priv *priv = netdev_priv(dev); 560 unsigned int i; 561 u32 reg; 562 563 /* Base system clock is 125Mhz, DMA timeout is this reference clock 564 * divided by 1024, which yield roughly 8.192 us, our maximum value has 565 * to fit in the RING_TIMEOUT_MASK (16 bits). 566 */ 567 if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK || 568 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 || 569 ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK || 570 ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1) 571 return -EINVAL; 572 573 if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) || 574 (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)) 575 return -EINVAL; 576 577 for (i = 0; i < dev->num_tx_queues; i++) { 578 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i)); 579 reg &= ~(RING_INTR_THRESH_MASK | 580 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT); 581 reg |= ec->tx_max_coalesced_frames; 582 reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) << 583 RING_TIMEOUT_SHIFT; 584 tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i)); 585 } 586 587 reg = rdma_readl(priv, RDMA_MBDONE_INTR); 588 reg &= ~(RDMA_INTR_THRESH_MASK | 589 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT); 590 reg |= ec->rx_max_coalesced_frames; 591 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192) << 592 RDMA_TIMEOUT_SHIFT; 593 rdma_writel(priv, reg, RDMA_MBDONE_INTR); 594 595 return 0; 596 } 597 598 static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb) 599 { 600 dev_kfree_skb_any(cb->skb); 601 cb->skb = NULL; 602 dma_unmap_addr_set(cb, dma_addr, 0); 603 } 604 605 static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv, 606 struct bcm_sysport_cb *cb) 607 { 608 struct device *kdev = &priv->pdev->dev; 609 struct net_device *ndev = priv->netdev; 610 struct sk_buff *skb, *rx_skb; 611 dma_addr_t mapping; 612 613 /* Allocate a new SKB for a new packet */ 614 skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH); 615 if (!skb) { 616 priv->mib.alloc_rx_buff_failed++; 617 netif_err(priv, rx_err, ndev, "SKB alloc failed\n"); 618 return NULL; 619 } 620 621 mapping = dma_map_single(kdev, skb->data, 622 RX_BUF_LENGTH, DMA_FROM_DEVICE); 623 if (dma_mapping_error(kdev, mapping)) { 624 priv->mib.rx_dma_failed++; 625 dev_kfree_skb_any(skb); 626 netif_err(priv, rx_err, ndev, "DMA mapping failure\n"); 627 return NULL; 628 } 629 630 /* Grab the current SKB on the ring */ 631 rx_skb = cb->skb; 632 if (likely(rx_skb)) 633 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 634 RX_BUF_LENGTH, DMA_FROM_DEVICE); 635 636 /* Put the new SKB on the ring */ 637 cb->skb = skb; 638 dma_unmap_addr_set(cb, dma_addr, mapping); 639 dma_desc_set_addr(priv, cb->bd_addr, mapping); 640 641 netif_dbg(priv, rx_status, ndev, "RX refill\n"); 642 643 /* Return the current SKB to the caller */ 644 return rx_skb; 645 } 646 647 static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv) 648 { 649 struct bcm_sysport_cb *cb; 650 struct sk_buff *skb; 651 unsigned int i; 652 653 for (i = 0; i < priv->num_rx_bds; i++) { 654 cb = &priv->rx_cbs[i]; 655 skb = bcm_sysport_rx_refill(priv, cb); 656 if (skb) 657 dev_kfree_skb(skb); 658 if (!cb->skb) 659 return -ENOMEM; 660 } 661 662 return 0; 663 } 664 665 /* Poll the hardware for up to budget packets to process */ 666 static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv, 667 unsigned int budget) 668 { 669 struct net_device *ndev = priv->netdev; 670 unsigned int processed = 0, to_process; 671 struct bcm_sysport_cb *cb; 672 struct sk_buff *skb; 673 unsigned int p_index; 674 u16 len, status; 675 struct bcm_rsb *rsb; 676 677 /* Clear status before servicing to reduce spurious interrupts */ 678 intrl2_0_writel(priv, INTRL2_0_RDMA_MBDONE, INTRL2_CPU_CLEAR); 679 680 /* Determine how much we should process since last call, SYSTEMPORT Lite 681 * groups the producer and consumer indexes into the same 32-bit 682 * which we access using RDMA_CONS_INDEX 683 */ 684 if (!priv->is_lite) 685 p_index = rdma_readl(priv, RDMA_PROD_INDEX); 686 else 687 p_index = rdma_readl(priv, RDMA_CONS_INDEX); 688 p_index &= RDMA_PROD_INDEX_MASK; 689 690 to_process = (p_index - priv->rx_c_index) & RDMA_CONS_INDEX_MASK; 691 692 netif_dbg(priv, rx_status, ndev, 693 "p_index=%d rx_c_index=%d to_process=%d\n", 694 p_index, priv->rx_c_index, to_process); 695 696 while ((processed < to_process) && (processed < budget)) { 697 cb = &priv->rx_cbs[priv->rx_read_ptr]; 698 skb = bcm_sysport_rx_refill(priv, cb); 699 700 701 /* We do not have a backing SKB, so we do not a corresponding 702 * DMA mapping for this incoming packet since 703 * bcm_sysport_rx_refill always either has both skb and mapping 704 * or none. 705 */ 706 if (unlikely(!skb)) { 707 netif_err(priv, rx_err, ndev, "out of memory!\n"); 708 ndev->stats.rx_dropped++; 709 ndev->stats.rx_errors++; 710 goto next; 711 } 712 713 /* Extract the Receive Status Block prepended */ 714 rsb = (struct bcm_rsb *)skb->data; 715 len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK; 716 status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) & 717 DESC_STATUS_MASK; 718 719 netif_dbg(priv, rx_status, ndev, 720 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n", 721 p_index, priv->rx_c_index, priv->rx_read_ptr, 722 len, status); 723 724 if (unlikely(len > RX_BUF_LENGTH)) { 725 netif_err(priv, rx_status, ndev, "oversized packet\n"); 726 ndev->stats.rx_length_errors++; 727 ndev->stats.rx_errors++; 728 dev_kfree_skb_any(skb); 729 goto next; 730 } 731 732 if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) { 733 netif_err(priv, rx_status, ndev, "fragmented packet!\n"); 734 ndev->stats.rx_dropped++; 735 ndev->stats.rx_errors++; 736 dev_kfree_skb_any(skb); 737 goto next; 738 } 739 740 if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) { 741 netif_err(priv, rx_err, ndev, "error packet\n"); 742 if (status & RX_STATUS_OVFLOW) 743 ndev->stats.rx_over_errors++; 744 ndev->stats.rx_dropped++; 745 ndev->stats.rx_errors++; 746 dev_kfree_skb_any(skb); 747 goto next; 748 } 749 750 skb_put(skb, len); 751 752 /* Hardware validated our checksum */ 753 if (likely(status & DESC_L4_CSUM)) 754 skb->ip_summed = CHECKSUM_UNNECESSARY; 755 756 /* Hardware pre-pends packets with 2bytes before Ethernet 757 * header plus we have the Receive Status Block, strip off all 758 * of this from the SKB. 759 */ 760 skb_pull(skb, sizeof(*rsb) + 2); 761 len -= (sizeof(*rsb) + 2); 762 763 /* UniMAC may forward CRC */ 764 if (priv->crc_fwd) { 765 skb_trim(skb, len - ETH_FCS_LEN); 766 len -= ETH_FCS_LEN; 767 } 768 769 skb->protocol = eth_type_trans(skb, ndev); 770 ndev->stats.rx_packets++; 771 ndev->stats.rx_bytes += len; 772 773 napi_gro_receive(&priv->napi, skb); 774 next: 775 processed++; 776 priv->rx_read_ptr++; 777 778 if (priv->rx_read_ptr == priv->num_rx_bds) 779 priv->rx_read_ptr = 0; 780 } 781 782 return processed; 783 } 784 785 static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_tx_ring *ring, 786 struct bcm_sysport_cb *cb, 787 unsigned int *bytes_compl, 788 unsigned int *pkts_compl) 789 { 790 struct bcm_sysport_priv *priv = ring->priv; 791 struct device *kdev = &priv->pdev->dev; 792 793 if (cb->skb) { 794 ring->bytes += cb->skb->len; 795 *bytes_compl += cb->skb->len; 796 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 797 dma_unmap_len(cb, dma_len), 798 DMA_TO_DEVICE); 799 ring->packets++; 800 (*pkts_compl)++; 801 bcm_sysport_free_cb(cb); 802 /* SKB fragment */ 803 } else if (dma_unmap_addr(cb, dma_addr)) { 804 ring->bytes += dma_unmap_len(cb, dma_len); 805 dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr), 806 dma_unmap_len(cb, dma_len), DMA_TO_DEVICE); 807 dma_unmap_addr_set(cb, dma_addr, 0); 808 } 809 } 810 811 /* Reclaim queued SKBs for transmission completion, lockless version */ 812 static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, 813 struct bcm_sysport_tx_ring *ring) 814 { 815 struct net_device *ndev = priv->netdev; 816 unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs; 817 unsigned int pkts_compl = 0, bytes_compl = 0; 818 struct bcm_sysport_cb *cb; 819 u32 hw_ind; 820 821 /* Clear status before servicing to reduce spurious interrupts */ 822 if (!ring->priv->is_lite) 823 intrl2_1_writel(ring->priv, BIT(ring->index), INTRL2_CPU_CLEAR); 824 else 825 intrl2_0_writel(ring->priv, BIT(ring->index + 826 INTRL2_0_TDMA_MBDONE_SHIFT), INTRL2_CPU_CLEAR); 827 828 /* Compute how many descriptors have been processed since last call */ 829 hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index)); 830 c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK; 831 ring->p_index = (hw_ind & RING_PROD_INDEX_MASK); 832 833 last_c_index = ring->c_index; 834 num_tx_cbs = ring->size; 835 836 c_index &= (num_tx_cbs - 1); 837 838 if (c_index >= last_c_index) 839 last_tx_cn = c_index - last_c_index; 840 else 841 last_tx_cn = num_tx_cbs - last_c_index + c_index; 842 843 netif_dbg(priv, tx_done, ndev, 844 "ring=%d c_index=%d last_tx_cn=%d last_c_index=%d\n", 845 ring->index, c_index, last_tx_cn, last_c_index); 846 847 while (last_tx_cn-- > 0) { 848 cb = ring->cbs + last_c_index; 849 bcm_sysport_tx_reclaim_one(ring, cb, &bytes_compl, &pkts_compl); 850 851 ring->desc_count++; 852 last_c_index++; 853 last_c_index &= (num_tx_cbs - 1); 854 } 855 856 ring->c_index = c_index; 857 858 netif_dbg(priv, tx_done, ndev, 859 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n", 860 ring->index, ring->c_index, pkts_compl, bytes_compl); 861 862 return pkts_compl; 863 } 864 865 /* Locked version of the per-ring TX reclaim routine */ 866 static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, 867 struct bcm_sysport_tx_ring *ring) 868 { 869 struct netdev_queue *txq; 870 unsigned int released; 871 unsigned long flags; 872 873 txq = netdev_get_tx_queue(priv->netdev, ring->index); 874 875 spin_lock_irqsave(&ring->lock, flags); 876 released = __bcm_sysport_tx_reclaim(priv, ring); 877 if (released) 878 netif_tx_wake_queue(txq); 879 880 spin_unlock_irqrestore(&ring->lock, flags); 881 882 return released; 883 } 884 885 /* Locked version of the per-ring TX reclaim, but does not wake the queue */ 886 static void bcm_sysport_tx_clean(struct bcm_sysport_priv *priv, 887 struct bcm_sysport_tx_ring *ring) 888 { 889 unsigned long flags; 890 891 spin_lock_irqsave(&ring->lock, flags); 892 __bcm_sysport_tx_reclaim(priv, ring); 893 spin_unlock_irqrestore(&ring->lock, flags); 894 } 895 896 static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget) 897 { 898 struct bcm_sysport_tx_ring *ring = 899 container_of(napi, struct bcm_sysport_tx_ring, napi); 900 unsigned int work_done = 0; 901 902 work_done = bcm_sysport_tx_reclaim(ring->priv, ring); 903 904 if (work_done == 0) { 905 napi_complete(napi); 906 /* re-enable TX interrupt */ 907 if (!ring->priv->is_lite) 908 intrl2_1_mask_clear(ring->priv, BIT(ring->index)); 909 else 910 intrl2_0_mask_clear(ring->priv, BIT(ring->index + 911 INTRL2_0_TDMA_MBDONE_SHIFT)); 912 913 return 0; 914 } 915 916 return budget; 917 } 918 919 static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv) 920 { 921 unsigned int q; 922 923 for (q = 0; q < priv->netdev->num_tx_queues; q++) 924 bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]); 925 } 926 927 static int bcm_sysport_poll(struct napi_struct *napi, int budget) 928 { 929 struct bcm_sysport_priv *priv = 930 container_of(napi, struct bcm_sysport_priv, napi); 931 unsigned int work_done = 0; 932 933 work_done = bcm_sysport_desc_rx(priv, budget); 934 935 priv->rx_c_index += work_done; 936 priv->rx_c_index &= RDMA_CONS_INDEX_MASK; 937 938 /* SYSTEMPORT Lite groups the producer/consumer index, producer is 939 * maintained by HW, but writes to it will be ignore while RDMA 940 * is active 941 */ 942 if (!priv->is_lite) 943 rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX); 944 else 945 rdma_writel(priv, priv->rx_c_index << 16, RDMA_CONS_INDEX); 946 947 if (work_done < budget) { 948 napi_complete_done(napi, work_done); 949 /* re-enable RX interrupts */ 950 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE); 951 } 952 953 return work_done; 954 } 955 956 static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv) 957 { 958 u32 reg; 959 960 /* Stop monitoring MPD interrupt */ 961 intrl2_0_mask_set(priv, INTRL2_0_MPD); 962 963 /* Clear the MagicPacket detection logic */ 964 reg = umac_readl(priv, UMAC_MPD_CTRL); 965 reg &= ~MPD_EN; 966 umac_writel(priv, reg, UMAC_MPD_CTRL); 967 968 netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n"); 969 } 970 971 /* RX and misc interrupt routine */ 972 static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id) 973 { 974 struct net_device *dev = dev_id; 975 struct bcm_sysport_priv *priv = netdev_priv(dev); 976 struct bcm_sysport_tx_ring *txr; 977 unsigned int ring, ring_bit; 978 979 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 980 ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 981 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 982 983 if (unlikely(priv->irq0_stat == 0)) { 984 netdev_warn(priv->netdev, "spurious RX interrupt\n"); 985 return IRQ_NONE; 986 } 987 988 if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) { 989 if (likely(napi_schedule_prep(&priv->napi))) { 990 /* disable RX interrupts */ 991 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE); 992 __napi_schedule_irqoff(&priv->napi); 993 } 994 } 995 996 /* TX ring is full, perform a full reclaim since we do not know 997 * which one would trigger this interrupt 998 */ 999 if (priv->irq0_stat & INTRL2_0_TX_RING_FULL) 1000 bcm_sysport_tx_reclaim_all(priv); 1001 1002 if (priv->irq0_stat & INTRL2_0_MPD) { 1003 netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n"); 1004 bcm_sysport_resume_from_wol(priv); 1005 } 1006 1007 if (!priv->is_lite) 1008 goto out; 1009 1010 for (ring = 0; ring < dev->num_tx_queues; ring++) { 1011 ring_bit = BIT(ring + INTRL2_0_TDMA_MBDONE_SHIFT); 1012 if (!(priv->irq0_stat & ring_bit)) 1013 continue; 1014 1015 txr = &priv->tx_rings[ring]; 1016 1017 if (likely(napi_schedule_prep(&txr->napi))) { 1018 intrl2_0_mask_set(priv, ring_bit); 1019 __napi_schedule(&txr->napi); 1020 } 1021 } 1022 out: 1023 return IRQ_HANDLED; 1024 } 1025 1026 /* TX interrupt service routine */ 1027 static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id) 1028 { 1029 struct net_device *dev = dev_id; 1030 struct bcm_sysport_priv *priv = netdev_priv(dev); 1031 struct bcm_sysport_tx_ring *txr; 1032 unsigned int ring; 1033 1034 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 1035 ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 1036 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1037 1038 if (unlikely(priv->irq1_stat == 0)) { 1039 netdev_warn(priv->netdev, "spurious TX interrupt\n"); 1040 return IRQ_NONE; 1041 } 1042 1043 for (ring = 0; ring < dev->num_tx_queues; ring++) { 1044 if (!(priv->irq1_stat & BIT(ring))) 1045 continue; 1046 1047 txr = &priv->tx_rings[ring]; 1048 1049 if (likely(napi_schedule_prep(&txr->napi))) { 1050 intrl2_1_mask_set(priv, BIT(ring)); 1051 __napi_schedule_irqoff(&txr->napi); 1052 } 1053 } 1054 1055 return IRQ_HANDLED; 1056 } 1057 1058 static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id) 1059 { 1060 struct bcm_sysport_priv *priv = dev_id; 1061 1062 pm_wakeup_event(&priv->pdev->dev, 0); 1063 1064 return IRQ_HANDLED; 1065 } 1066 1067 #ifdef CONFIG_NET_POLL_CONTROLLER 1068 static void bcm_sysport_poll_controller(struct net_device *dev) 1069 { 1070 struct bcm_sysport_priv *priv = netdev_priv(dev); 1071 1072 disable_irq(priv->irq0); 1073 bcm_sysport_rx_isr(priv->irq0, priv); 1074 enable_irq(priv->irq0); 1075 1076 if (!priv->is_lite) { 1077 disable_irq(priv->irq1); 1078 bcm_sysport_tx_isr(priv->irq1, priv); 1079 enable_irq(priv->irq1); 1080 } 1081 } 1082 #endif 1083 1084 static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb, 1085 struct net_device *dev) 1086 { 1087 struct sk_buff *nskb; 1088 struct bcm_tsb *tsb; 1089 u32 csum_info; 1090 u8 ip_proto; 1091 u16 csum_start; 1092 u16 ip_ver; 1093 1094 /* Re-allocate SKB if needed */ 1095 if (unlikely(skb_headroom(skb) < sizeof(*tsb))) { 1096 nskb = skb_realloc_headroom(skb, sizeof(*tsb)); 1097 dev_kfree_skb(skb); 1098 if (!nskb) { 1099 dev->stats.tx_errors++; 1100 dev->stats.tx_dropped++; 1101 return NULL; 1102 } 1103 skb = nskb; 1104 } 1105 1106 tsb = skb_push(skb, sizeof(*tsb)); 1107 /* Zero-out TSB by default */ 1108 memset(tsb, 0, sizeof(*tsb)); 1109 1110 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1111 ip_ver = htons(skb->protocol); 1112 switch (ip_ver) { 1113 case ETH_P_IP: 1114 ip_proto = ip_hdr(skb)->protocol; 1115 break; 1116 case ETH_P_IPV6: 1117 ip_proto = ipv6_hdr(skb)->nexthdr; 1118 break; 1119 default: 1120 return skb; 1121 } 1122 1123 /* Get the checksum offset and the L4 (transport) offset */ 1124 csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb); 1125 csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK; 1126 csum_info |= (csum_start << L4_PTR_SHIFT); 1127 1128 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { 1129 csum_info |= L4_LENGTH_VALID; 1130 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) 1131 csum_info |= L4_UDP; 1132 } else { 1133 csum_info = 0; 1134 } 1135 1136 tsb->l4_ptr_dest_map = csum_info; 1137 } 1138 1139 return skb; 1140 } 1141 1142 static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb, 1143 struct net_device *dev) 1144 { 1145 struct bcm_sysport_priv *priv = netdev_priv(dev); 1146 struct device *kdev = &priv->pdev->dev; 1147 struct bcm_sysport_tx_ring *ring; 1148 struct bcm_sysport_cb *cb; 1149 struct netdev_queue *txq; 1150 struct dma_desc *desc; 1151 unsigned int skb_len; 1152 unsigned long flags; 1153 dma_addr_t mapping; 1154 u32 len_status; 1155 u16 queue; 1156 int ret; 1157 1158 queue = skb_get_queue_mapping(skb); 1159 txq = netdev_get_tx_queue(dev, queue); 1160 ring = &priv->tx_rings[queue]; 1161 1162 /* lock against tx reclaim in BH context and TX ring full interrupt */ 1163 spin_lock_irqsave(&ring->lock, flags); 1164 if (unlikely(ring->desc_count == 0)) { 1165 netif_tx_stop_queue(txq); 1166 netdev_err(dev, "queue %d awake and ring full!\n", queue); 1167 ret = NETDEV_TX_BUSY; 1168 goto out; 1169 } 1170 1171 /* The Ethernet switch we are interfaced with needs packets to be at 1172 * least 64 bytes (including FCS) otherwise they will be discarded when 1173 * they enter the switch port logic. When Broadcom tags are enabled, we 1174 * need to make sure that packets are at least 68 bytes 1175 * (including FCS and tag) because the length verification is done after 1176 * the Broadcom tag is stripped off the ingress packet. 1177 */ 1178 if (skb_put_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) { 1179 ret = NETDEV_TX_OK; 1180 goto out; 1181 } 1182 1183 /* Insert TSB and checksum infos */ 1184 if (priv->tsb_en) { 1185 skb = bcm_sysport_insert_tsb(skb, dev); 1186 if (!skb) { 1187 ret = NETDEV_TX_OK; 1188 goto out; 1189 } 1190 } 1191 1192 skb_len = skb->len; 1193 1194 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); 1195 if (dma_mapping_error(kdev, mapping)) { 1196 priv->mib.tx_dma_failed++; 1197 netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n", 1198 skb->data, skb_len); 1199 ret = NETDEV_TX_OK; 1200 goto out; 1201 } 1202 1203 /* Remember the SKB for future freeing */ 1204 cb = &ring->cbs[ring->curr_desc]; 1205 cb->skb = skb; 1206 dma_unmap_addr_set(cb, dma_addr, mapping); 1207 dma_unmap_len_set(cb, dma_len, skb_len); 1208 1209 /* Fetch a descriptor entry from our pool */ 1210 desc = ring->desc_cpu; 1211 1212 desc->addr_lo = lower_32_bits(mapping); 1213 len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK; 1214 len_status |= (skb_len << DESC_LEN_SHIFT); 1215 len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) << 1216 DESC_STATUS_SHIFT; 1217 if (skb->ip_summed == CHECKSUM_PARTIAL) 1218 len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT); 1219 1220 ring->curr_desc++; 1221 if (ring->curr_desc == ring->size) 1222 ring->curr_desc = 0; 1223 ring->desc_count--; 1224 1225 /* Ensure write completion of the descriptor status/length 1226 * in DRAM before the System Port WRITE_PORT register latches 1227 * the value 1228 */ 1229 wmb(); 1230 desc->addr_status_len = len_status; 1231 wmb(); 1232 1233 /* Write this descriptor address to the RING write port */ 1234 tdma_port_write_desc_addr(priv, desc, ring->index); 1235 1236 /* Check ring space and update SW control flow */ 1237 if (ring->desc_count == 0) 1238 netif_tx_stop_queue(txq); 1239 1240 netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n", 1241 ring->index, ring->desc_count, ring->curr_desc); 1242 1243 ret = NETDEV_TX_OK; 1244 out: 1245 spin_unlock_irqrestore(&ring->lock, flags); 1246 return ret; 1247 } 1248 1249 static void bcm_sysport_tx_timeout(struct net_device *dev) 1250 { 1251 netdev_warn(dev, "transmit timeout!\n"); 1252 1253 netif_trans_update(dev); 1254 dev->stats.tx_errors++; 1255 1256 netif_tx_wake_all_queues(dev); 1257 } 1258 1259 /* phylib adjust link callback */ 1260 static void bcm_sysport_adj_link(struct net_device *dev) 1261 { 1262 struct bcm_sysport_priv *priv = netdev_priv(dev); 1263 struct phy_device *phydev = dev->phydev; 1264 unsigned int changed = 0; 1265 u32 cmd_bits = 0, reg; 1266 1267 if (priv->old_link != phydev->link) { 1268 changed = 1; 1269 priv->old_link = phydev->link; 1270 } 1271 1272 if (priv->old_duplex != phydev->duplex) { 1273 changed = 1; 1274 priv->old_duplex = phydev->duplex; 1275 } 1276 1277 if (priv->is_lite) 1278 goto out; 1279 1280 switch (phydev->speed) { 1281 case SPEED_2500: 1282 cmd_bits = CMD_SPEED_2500; 1283 break; 1284 case SPEED_1000: 1285 cmd_bits = CMD_SPEED_1000; 1286 break; 1287 case SPEED_100: 1288 cmd_bits = CMD_SPEED_100; 1289 break; 1290 case SPEED_10: 1291 cmd_bits = CMD_SPEED_10; 1292 break; 1293 default: 1294 break; 1295 } 1296 cmd_bits <<= CMD_SPEED_SHIFT; 1297 1298 if (phydev->duplex == DUPLEX_HALF) 1299 cmd_bits |= CMD_HD_EN; 1300 1301 if (priv->old_pause != phydev->pause) { 1302 changed = 1; 1303 priv->old_pause = phydev->pause; 1304 } 1305 1306 if (!phydev->pause) 1307 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 1308 1309 if (!changed) 1310 return; 1311 1312 if (phydev->link) { 1313 reg = umac_readl(priv, UMAC_CMD); 1314 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 1315 CMD_HD_EN | CMD_RX_PAUSE_IGNORE | 1316 CMD_TX_PAUSE_IGNORE); 1317 reg |= cmd_bits; 1318 umac_writel(priv, reg, UMAC_CMD); 1319 } 1320 out: 1321 if (changed) 1322 phy_print_status(phydev); 1323 } 1324 1325 static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv, 1326 unsigned int index) 1327 { 1328 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; 1329 struct device *kdev = &priv->pdev->dev; 1330 size_t size; 1331 void *p; 1332 u32 reg; 1333 1334 /* Simple descriptors partitioning for now */ 1335 size = 256; 1336 1337 /* We just need one DMA descriptor which is DMA-able, since writing to 1338 * the port will allocate a new descriptor in its internal linked-list 1339 */ 1340 p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma, 1341 GFP_KERNEL); 1342 if (!p) { 1343 netif_err(priv, hw, priv->netdev, "DMA alloc failed\n"); 1344 return -ENOMEM; 1345 } 1346 1347 ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL); 1348 if (!ring->cbs) { 1349 netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); 1350 return -ENOMEM; 1351 } 1352 1353 /* Initialize SW view of the ring */ 1354 spin_lock_init(&ring->lock); 1355 ring->priv = priv; 1356 netif_tx_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64); 1357 ring->index = index; 1358 ring->size = size; 1359 ring->alloc_size = ring->size; 1360 ring->desc_cpu = p; 1361 ring->desc_count = ring->size; 1362 ring->curr_desc = 0; 1363 1364 /* Initialize HW ring */ 1365 tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index)); 1366 tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index)); 1367 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index)); 1368 tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index)); 1369 tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index)); 1370 tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index)); 1371 1372 /* Program the number of descriptors as MAX_THRESHOLD and half of 1373 * its size for the hysteresis trigger 1374 */ 1375 tdma_writel(priv, ring->size | 1376 1 << RING_HYST_THRESH_SHIFT, 1377 TDMA_DESC_RING_MAX_HYST(index)); 1378 1379 /* Enable the ring queue in the arbiter */ 1380 reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN); 1381 reg |= (1 << index); 1382 tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN); 1383 1384 napi_enable(&ring->napi); 1385 1386 netif_dbg(priv, hw, priv->netdev, 1387 "TDMA cfg, size=%d, desc_cpu=%p\n", 1388 ring->size, ring->desc_cpu); 1389 1390 return 0; 1391 } 1392 1393 static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv, 1394 unsigned int index) 1395 { 1396 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; 1397 struct device *kdev = &priv->pdev->dev; 1398 u32 reg; 1399 1400 /* Caller should stop the TDMA engine */ 1401 reg = tdma_readl(priv, TDMA_STATUS); 1402 if (!(reg & TDMA_DISABLED)) 1403 netdev_warn(priv->netdev, "TDMA not stopped!\n"); 1404 1405 /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could 1406 * fail, so by checking this pointer we know whether the TX ring was 1407 * fully initialized or not. 1408 */ 1409 if (!ring->cbs) 1410 return; 1411 1412 napi_disable(&ring->napi); 1413 netif_napi_del(&ring->napi); 1414 1415 bcm_sysport_tx_clean(priv, ring); 1416 1417 kfree(ring->cbs); 1418 ring->cbs = NULL; 1419 1420 if (ring->desc_dma) { 1421 dma_free_coherent(kdev, sizeof(struct dma_desc), 1422 ring->desc_cpu, ring->desc_dma); 1423 ring->desc_dma = 0; 1424 } 1425 ring->size = 0; 1426 ring->alloc_size = 0; 1427 1428 netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n"); 1429 } 1430 1431 /* RDMA helper */ 1432 static inline int rdma_enable_set(struct bcm_sysport_priv *priv, 1433 unsigned int enable) 1434 { 1435 unsigned int timeout = 1000; 1436 u32 reg; 1437 1438 reg = rdma_readl(priv, RDMA_CONTROL); 1439 if (enable) 1440 reg |= RDMA_EN; 1441 else 1442 reg &= ~RDMA_EN; 1443 rdma_writel(priv, reg, RDMA_CONTROL); 1444 1445 /* Poll for RMDA disabling completion */ 1446 do { 1447 reg = rdma_readl(priv, RDMA_STATUS); 1448 if (!!(reg & RDMA_DISABLED) == !enable) 1449 return 0; 1450 usleep_range(1000, 2000); 1451 } while (timeout-- > 0); 1452 1453 netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n"); 1454 1455 return -ETIMEDOUT; 1456 } 1457 1458 /* TDMA helper */ 1459 static inline int tdma_enable_set(struct bcm_sysport_priv *priv, 1460 unsigned int enable) 1461 { 1462 unsigned int timeout = 1000; 1463 u32 reg; 1464 1465 reg = tdma_readl(priv, TDMA_CONTROL); 1466 if (enable) 1467 reg |= tdma_control_bit(priv, TDMA_EN); 1468 else 1469 reg &= ~tdma_control_bit(priv, TDMA_EN); 1470 tdma_writel(priv, reg, TDMA_CONTROL); 1471 1472 /* Poll for TMDA disabling completion */ 1473 do { 1474 reg = tdma_readl(priv, TDMA_STATUS); 1475 if (!!(reg & TDMA_DISABLED) == !enable) 1476 return 0; 1477 1478 usleep_range(1000, 2000); 1479 } while (timeout-- > 0); 1480 1481 netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n"); 1482 1483 return -ETIMEDOUT; 1484 } 1485 1486 static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv) 1487 { 1488 struct bcm_sysport_cb *cb; 1489 u32 reg; 1490 int ret; 1491 int i; 1492 1493 /* Initialize SW view of the RX ring */ 1494 priv->num_rx_bds = priv->num_rx_desc_words / WORDS_PER_DESC; 1495 priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET; 1496 priv->rx_c_index = 0; 1497 priv->rx_read_ptr = 0; 1498 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb), 1499 GFP_KERNEL); 1500 if (!priv->rx_cbs) { 1501 netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); 1502 return -ENOMEM; 1503 } 1504 1505 for (i = 0; i < priv->num_rx_bds; i++) { 1506 cb = priv->rx_cbs + i; 1507 cb->bd_addr = priv->rx_bds + i * DESC_SIZE; 1508 } 1509 1510 ret = bcm_sysport_alloc_rx_bufs(priv); 1511 if (ret) { 1512 netif_err(priv, hw, priv->netdev, "SKB allocation failed\n"); 1513 return ret; 1514 } 1515 1516 /* Initialize HW, ensure RDMA is disabled */ 1517 reg = rdma_readl(priv, RDMA_STATUS); 1518 if (!(reg & RDMA_DISABLED)) 1519 rdma_enable_set(priv, 0); 1520 1521 rdma_writel(priv, 0, RDMA_WRITE_PTR_LO); 1522 rdma_writel(priv, 0, RDMA_WRITE_PTR_HI); 1523 rdma_writel(priv, 0, RDMA_PROD_INDEX); 1524 rdma_writel(priv, 0, RDMA_CONS_INDEX); 1525 rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT | 1526 RX_BUF_LENGTH, RDMA_RING_BUF_SIZE); 1527 /* Operate the queue in ring mode */ 1528 rdma_writel(priv, 0, RDMA_START_ADDR_HI); 1529 rdma_writel(priv, 0, RDMA_START_ADDR_LO); 1530 rdma_writel(priv, 0, RDMA_END_ADDR_HI); 1531 rdma_writel(priv, priv->num_rx_desc_words - 1, RDMA_END_ADDR_LO); 1532 1533 rdma_writel(priv, 1, RDMA_MBDONE_INTR); 1534 1535 netif_dbg(priv, hw, priv->netdev, 1536 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n", 1537 priv->num_rx_bds, priv->rx_bds); 1538 1539 return 0; 1540 } 1541 1542 static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv) 1543 { 1544 struct bcm_sysport_cb *cb; 1545 unsigned int i; 1546 u32 reg; 1547 1548 /* Caller should ensure RDMA is disabled */ 1549 reg = rdma_readl(priv, RDMA_STATUS); 1550 if (!(reg & RDMA_DISABLED)) 1551 netdev_warn(priv->netdev, "RDMA not stopped!\n"); 1552 1553 for (i = 0; i < priv->num_rx_bds; i++) { 1554 cb = &priv->rx_cbs[i]; 1555 if (dma_unmap_addr(cb, dma_addr)) 1556 dma_unmap_single(&priv->pdev->dev, 1557 dma_unmap_addr(cb, dma_addr), 1558 RX_BUF_LENGTH, DMA_FROM_DEVICE); 1559 bcm_sysport_free_cb(cb); 1560 } 1561 1562 kfree(priv->rx_cbs); 1563 priv->rx_cbs = NULL; 1564 1565 netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n"); 1566 } 1567 1568 static void bcm_sysport_set_rx_mode(struct net_device *dev) 1569 { 1570 struct bcm_sysport_priv *priv = netdev_priv(dev); 1571 u32 reg; 1572 1573 if (priv->is_lite) 1574 return; 1575 1576 reg = umac_readl(priv, UMAC_CMD); 1577 if (dev->flags & IFF_PROMISC) 1578 reg |= CMD_PROMISC; 1579 else 1580 reg &= ~CMD_PROMISC; 1581 umac_writel(priv, reg, UMAC_CMD); 1582 1583 /* No support for ALLMULTI */ 1584 if (dev->flags & IFF_ALLMULTI) 1585 return; 1586 } 1587 1588 static inline void umac_enable_set(struct bcm_sysport_priv *priv, 1589 u32 mask, unsigned int enable) 1590 { 1591 u32 reg; 1592 1593 if (!priv->is_lite) { 1594 reg = umac_readl(priv, UMAC_CMD); 1595 if (enable) 1596 reg |= mask; 1597 else 1598 reg &= ~mask; 1599 umac_writel(priv, reg, UMAC_CMD); 1600 } else { 1601 reg = gib_readl(priv, GIB_CONTROL); 1602 if (enable) 1603 reg |= mask; 1604 else 1605 reg &= ~mask; 1606 gib_writel(priv, reg, GIB_CONTROL); 1607 } 1608 1609 /* UniMAC stops on a packet boundary, wait for a full-sized packet 1610 * to be processed (1 msec). 1611 */ 1612 if (enable == 0) 1613 usleep_range(1000, 2000); 1614 } 1615 1616 static inline void umac_reset(struct bcm_sysport_priv *priv) 1617 { 1618 u32 reg; 1619 1620 if (priv->is_lite) 1621 return; 1622 1623 reg = umac_readl(priv, UMAC_CMD); 1624 reg |= CMD_SW_RESET; 1625 umac_writel(priv, reg, UMAC_CMD); 1626 udelay(10); 1627 reg = umac_readl(priv, UMAC_CMD); 1628 reg &= ~CMD_SW_RESET; 1629 umac_writel(priv, reg, UMAC_CMD); 1630 } 1631 1632 static void umac_set_hw_addr(struct bcm_sysport_priv *priv, 1633 unsigned char *addr) 1634 { 1635 u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | 1636 addr[3]; 1637 u32 mac1 = (addr[4] << 8) | addr[5]; 1638 1639 if (!priv->is_lite) { 1640 umac_writel(priv, mac0, UMAC_MAC0); 1641 umac_writel(priv, mac1, UMAC_MAC1); 1642 } else { 1643 gib_writel(priv, mac0, GIB_MAC0); 1644 gib_writel(priv, mac1, GIB_MAC1); 1645 } 1646 } 1647 1648 static void topctrl_flush(struct bcm_sysport_priv *priv) 1649 { 1650 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); 1651 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); 1652 mdelay(1); 1653 topctrl_writel(priv, 0, RX_FLUSH_CNTL); 1654 topctrl_writel(priv, 0, TX_FLUSH_CNTL); 1655 } 1656 1657 static int bcm_sysport_change_mac(struct net_device *dev, void *p) 1658 { 1659 struct bcm_sysport_priv *priv = netdev_priv(dev); 1660 struct sockaddr *addr = p; 1661 1662 if (!is_valid_ether_addr(addr->sa_data)) 1663 return -EINVAL; 1664 1665 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 1666 1667 /* interface is disabled, changes to MAC will be reflected on next 1668 * open call 1669 */ 1670 if (!netif_running(dev)) 1671 return 0; 1672 1673 umac_set_hw_addr(priv, dev->dev_addr); 1674 1675 return 0; 1676 } 1677 1678 static struct net_device_stats *bcm_sysport_get_nstats(struct net_device *dev) 1679 { 1680 struct bcm_sysport_priv *priv = netdev_priv(dev); 1681 unsigned long tx_bytes = 0, tx_packets = 0; 1682 struct bcm_sysport_tx_ring *ring; 1683 unsigned int q; 1684 1685 for (q = 0; q < dev->num_tx_queues; q++) { 1686 ring = &priv->tx_rings[q]; 1687 tx_bytes += ring->bytes; 1688 tx_packets += ring->packets; 1689 } 1690 1691 dev->stats.tx_bytes = tx_bytes; 1692 dev->stats.tx_packets = tx_packets; 1693 return &dev->stats; 1694 } 1695 1696 static void bcm_sysport_netif_start(struct net_device *dev) 1697 { 1698 struct bcm_sysport_priv *priv = netdev_priv(dev); 1699 1700 /* Enable NAPI */ 1701 napi_enable(&priv->napi); 1702 1703 /* Enable RX interrupt and TX ring full interrupt */ 1704 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); 1705 1706 phy_start(dev->phydev); 1707 1708 /* Enable TX interrupts for the TXQs */ 1709 if (!priv->is_lite) 1710 intrl2_1_mask_clear(priv, 0xffffffff); 1711 else 1712 intrl2_0_mask_clear(priv, INTRL2_0_TDMA_MBDONE_MASK); 1713 1714 /* Last call before we start the real business */ 1715 netif_tx_start_all_queues(dev); 1716 } 1717 1718 static void rbuf_init(struct bcm_sysport_priv *priv) 1719 { 1720 u32 reg; 1721 1722 reg = rbuf_readl(priv, RBUF_CONTROL); 1723 reg |= RBUF_4B_ALGN | RBUF_RSB_EN; 1724 /* Set a correct RSB format on SYSTEMPORT Lite */ 1725 if (priv->is_lite) { 1726 reg &= ~RBUF_RSB_SWAP1; 1727 reg |= RBUF_RSB_SWAP0; 1728 } 1729 rbuf_writel(priv, reg, RBUF_CONTROL); 1730 } 1731 1732 static inline void bcm_sysport_mask_all_intrs(struct bcm_sysport_priv *priv) 1733 { 1734 intrl2_0_mask_set(priv, 0xffffffff); 1735 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1736 if (!priv->is_lite) { 1737 intrl2_1_mask_set(priv, 0xffffffff); 1738 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1739 } 1740 } 1741 1742 static inline void gib_set_pad_extension(struct bcm_sysport_priv *priv) 1743 { 1744 u32 __maybe_unused reg; 1745 1746 /* Include Broadcom tag in pad extension */ 1747 if (netdev_uses_dsa(priv->netdev)) { 1748 reg = gib_readl(priv, GIB_CONTROL); 1749 reg &= ~(GIB_PAD_EXTENSION_MASK << GIB_PAD_EXTENSION_SHIFT); 1750 reg |= ENET_BRCM_TAG_LEN << GIB_PAD_EXTENSION_SHIFT; 1751 gib_writel(priv, reg, GIB_CONTROL); 1752 } 1753 } 1754 1755 static int bcm_sysport_open(struct net_device *dev) 1756 { 1757 struct bcm_sysport_priv *priv = netdev_priv(dev); 1758 struct phy_device *phydev; 1759 unsigned int i; 1760 int ret; 1761 1762 /* Reset UniMAC */ 1763 umac_reset(priv); 1764 1765 /* Flush TX and RX FIFOs at TOPCTRL level */ 1766 topctrl_flush(priv); 1767 1768 /* Disable the UniMAC RX/TX */ 1769 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0); 1770 1771 /* Enable RBUF 2bytes alignment and Receive Status Block */ 1772 rbuf_init(priv); 1773 1774 /* Set maximum frame length */ 1775 if (!priv->is_lite) 1776 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 1777 else 1778 gib_set_pad_extension(priv); 1779 1780 /* Set MAC address */ 1781 umac_set_hw_addr(priv, dev->dev_addr); 1782 1783 /* Read CRC forward */ 1784 if (!priv->is_lite) 1785 priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD); 1786 else 1787 priv->crc_fwd = !!(gib_readl(priv, GIB_CONTROL) & 1788 GIB_FCS_STRIP); 1789 1790 phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link, 1791 0, priv->phy_interface); 1792 if (!phydev) { 1793 netdev_err(dev, "could not attach to PHY\n"); 1794 return -ENODEV; 1795 } 1796 1797 /* Reset house keeping link status */ 1798 priv->old_duplex = -1; 1799 priv->old_link = -1; 1800 priv->old_pause = -1; 1801 1802 /* mask all interrupts and request them */ 1803 bcm_sysport_mask_all_intrs(priv); 1804 1805 ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev); 1806 if (ret) { 1807 netdev_err(dev, "failed to request RX interrupt\n"); 1808 goto out_phy_disconnect; 1809 } 1810 1811 if (!priv->is_lite) { 1812 ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, 1813 dev->name, dev); 1814 if (ret) { 1815 netdev_err(dev, "failed to request TX interrupt\n"); 1816 goto out_free_irq0; 1817 } 1818 } 1819 1820 /* Initialize both hardware and software ring */ 1821 for (i = 0; i < dev->num_tx_queues; i++) { 1822 ret = bcm_sysport_init_tx_ring(priv, i); 1823 if (ret) { 1824 netdev_err(dev, "failed to initialize TX ring %d\n", 1825 i); 1826 goto out_free_tx_ring; 1827 } 1828 } 1829 1830 /* Initialize linked-list */ 1831 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); 1832 1833 /* Initialize RX ring */ 1834 ret = bcm_sysport_init_rx_ring(priv); 1835 if (ret) { 1836 netdev_err(dev, "failed to initialize RX ring\n"); 1837 goto out_free_rx_ring; 1838 } 1839 1840 /* Turn on RDMA */ 1841 ret = rdma_enable_set(priv, 1); 1842 if (ret) 1843 goto out_free_rx_ring; 1844 1845 /* Turn on TDMA */ 1846 ret = tdma_enable_set(priv, 1); 1847 if (ret) 1848 goto out_clear_rx_int; 1849 1850 /* Turn on UniMAC TX/RX */ 1851 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1); 1852 1853 bcm_sysport_netif_start(dev); 1854 1855 return 0; 1856 1857 out_clear_rx_int: 1858 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); 1859 out_free_rx_ring: 1860 bcm_sysport_fini_rx_ring(priv); 1861 out_free_tx_ring: 1862 for (i = 0; i < dev->num_tx_queues; i++) 1863 bcm_sysport_fini_tx_ring(priv, i); 1864 if (!priv->is_lite) 1865 free_irq(priv->irq1, dev); 1866 out_free_irq0: 1867 free_irq(priv->irq0, dev); 1868 out_phy_disconnect: 1869 phy_disconnect(phydev); 1870 return ret; 1871 } 1872 1873 static void bcm_sysport_netif_stop(struct net_device *dev) 1874 { 1875 struct bcm_sysport_priv *priv = netdev_priv(dev); 1876 1877 /* stop all software from updating hardware */ 1878 netif_tx_stop_all_queues(dev); 1879 napi_disable(&priv->napi); 1880 phy_stop(dev->phydev); 1881 1882 /* mask all interrupts */ 1883 bcm_sysport_mask_all_intrs(priv); 1884 } 1885 1886 static int bcm_sysport_stop(struct net_device *dev) 1887 { 1888 struct bcm_sysport_priv *priv = netdev_priv(dev); 1889 unsigned int i; 1890 int ret; 1891 1892 bcm_sysport_netif_stop(dev); 1893 1894 /* Disable UniMAC RX */ 1895 umac_enable_set(priv, CMD_RX_EN, 0); 1896 1897 ret = tdma_enable_set(priv, 0); 1898 if (ret) { 1899 netdev_err(dev, "timeout disabling RDMA\n"); 1900 return ret; 1901 } 1902 1903 /* Wait for a maximum packet size to be drained */ 1904 usleep_range(2000, 3000); 1905 1906 ret = rdma_enable_set(priv, 0); 1907 if (ret) { 1908 netdev_err(dev, "timeout disabling TDMA\n"); 1909 return ret; 1910 } 1911 1912 /* Disable UniMAC TX */ 1913 umac_enable_set(priv, CMD_TX_EN, 0); 1914 1915 /* Free RX/TX rings SW structures */ 1916 for (i = 0; i < dev->num_tx_queues; i++) 1917 bcm_sysport_fini_tx_ring(priv, i); 1918 bcm_sysport_fini_rx_ring(priv); 1919 1920 free_irq(priv->irq0, dev); 1921 if (!priv->is_lite) 1922 free_irq(priv->irq1, dev); 1923 1924 /* Disconnect from PHY */ 1925 phy_disconnect(dev->phydev); 1926 1927 return 0; 1928 } 1929 1930 static const struct ethtool_ops bcm_sysport_ethtool_ops = { 1931 .get_drvinfo = bcm_sysport_get_drvinfo, 1932 .get_msglevel = bcm_sysport_get_msglvl, 1933 .set_msglevel = bcm_sysport_set_msglvl, 1934 .get_link = ethtool_op_get_link, 1935 .get_strings = bcm_sysport_get_strings, 1936 .get_ethtool_stats = bcm_sysport_get_stats, 1937 .get_sset_count = bcm_sysport_get_sset_count, 1938 .get_wol = bcm_sysport_get_wol, 1939 .set_wol = bcm_sysport_set_wol, 1940 .get_coalesce = bcm_sysport_get_coalesce, 1941 .set_coalesce = bcm_sysport_set_coalesce, 1942 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1943 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1944 }; 1945 1946 static const struct net_device_ops bcm_sysport_netdev_ops = { 1947 .ndo_start_xmit = bcm_sysport_xmit, 1948 .ndo_tx_timeout = bcm_sysport_tx_timeout, 1949 .ndo_open = bcm_sysport_open, 1950 .ndo_stop = bcm_sysport_stop, 1951 .ndo_set_features = bcm_sysport_set_features, 1952 .ndo_set_rx_mode = bcm_sysport_set_rx_mode, 1953 .ndo_set_mac_address = bcm_sysport_change_mac, 1954 #ifdef CONFIG_NET_POLL_CONTROLLER 1955 .ndo_poll_controller = bcm_sysport_poll_controller, 1956 #endif 1957 .ndo_get_stats = bcm_sysport_get_nstats, 1958 }; 1959 1960 #define REV_FMT "v%2x.%02x" 1961 1962 static const struct bcm_sysport_hw_params bcm_sysport_params[] = { 1963 [SYSTEMPORT] = { 1964 .is_lite = false, 1965 .num_rx_desc_words = SP_NUM_HW_RX_DESC_WORDS, 1966 }, 1967 [SYSTEMPORT_LITE] = { 1968 .is_lite = true, 1969 .num_rx_desc_words = SP_LT_NUM_HW_RX_DESC_WORDS, 1970 }, 1971 }; 1972 1973 static const struct of_device_id bcm_sysport_of_match[] = { 1974 { .compatible = "brcm,systemportlite-v1.00", 1975 .data = &bcm_sysport_params[SYSTEMPORT_LITE] }, 1976 { .compatible = "brcm,systemport-v1.00", 1977 .data = &bcm_sysport_params[SYSTEMPORT] }, 1978 { .compatible = "brcm,systemport", 1979 .data = &bcm_sysport_params[SYSTEMPORT] }, 1980 { /* sentinel */ } 1981 }; 1982 MODULE_DEVICE_TABLE(of, bcm_sysport_of_match); 1983 1984 static int bcm_sysport_probe(struct platform_device *pdev) 1985 { 1986 const struct bcm_sysport_hw_params *params; 1987 const struct of_device_id *of_id = NULL; 1988 struct bcm_sysport_priv *priv; 1989 struct device_node *dn; 1990 struct net_device *dev; 1991 const void *macaddr; 1992 struct resource *r; 1993 u32 txq, rxq; 1994 int ret; 1995 1996 dn = pdev->dev.of_node; 1997 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1998 of_id = of_match_node(bcm_sysport_of_match, dn); 1999 if (!of_id || !of_id->data) 2000 return -EINVAL; 2001 2002 /* Fairly quickly we need to know the type of adapter we have */ 2003 params = of_id->data; 2004 2005 /* Read the Transmit/Receive Queue properties */ 2006 if (of_property_read_u32(dn, "systemport,num-txq", &txq)) 2007 txq = TDMA_NUM_RINGS; 2008 if (of_property_read_u32(dn, "systemport,num-rxq", &rxq)) 2009 rxq = 1; 2010 2011 /* Sanity check the number of transmit queues */ 2012 if (!txq || txq > TDMA_NUM_RINGS) 2013 return -EINVAL; 2014 2015 dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq); 2016 if (!dev) 2017 return -ENOMEM; 2018 2019 /* Initialize private members */ 2020 priv = netdev_priv(dev); 2021 2022 /* Allocate number of TX rings */ 2023 priv->tx_rings = devm_kcalloc(&pdev->dev, txq, 2024 sizeof(struct bcm_sysport_tx_ring), 2025 GFP_KERNEL); 2026 if (!priv->tx_rings) 2027 return -ENOMEM; 2028 2029 priv->is_lite = params->is_lite; 2030 priv->num_rx_desc_words = params->num_rx_desc_words; 2031 2032 priv->irq0 = platform_get_irq(pdev, 0); 2033 if (!priv->is_lite) { 2034 priv->irq1 = platform_get_irq(pdev, 1); 2035 priv->wol_irq = platform_get_irq(pdev, 2); 2036 } else { 2037 priv->wol_irq = platform_get_irq(pdev, 1); 2038 } 2039 if (priv->irq0 <= 0 || (priv->irq1 <= 0 && !priv->is_lite)) { 2040 dev_err(&pdev->dev, "invalid interrupts\n"); 2041 ret = -EINVAL; 2042 goto err_free_netdev; 2043 } 2044 2045 priv->base = devm_ioremap_resource(&pdev->dev, r); 2046 if (IS_ERR(priv->base)) { 2047 ret = PTR_ERR(priv->base); 2048 goto err_free_netdev; 2049 } 2050 2051 priv->netdev = dev; 2052 priv->pdev = pdev; 2053 2054 priv->phy_interface = of_get_phy_mode(dn); 2055 /* Default to GMII interface mode */ 2056 if (priv->phy_interface < 0) 2057 priv->phy_interface = PHY_INTERFACE_MODE_GMII; 2058 2059 /* In the case of a fixed PHY, the DT node associated 2060 * to the PHY is the Ethernet MAC DT node. 2061 */ 2062 if (of_phy_is_fixed_link(dn)) { 2063 ret = of_phy_register_fixed_link(dn); 2064 if (ret) { 2065 dev_err(&pdev->dev, "failed to register fixed PHY\n"); 2066 goto err_free_netdev; 2067 } 2068 2069 priv->phy_dn = dn; 2070 } 2071 2072 /* Initialize netdevice members */ 2073 macaddr = of_get_mac_address(dn); 2074 if (!macaddr || !is_valid_ether_addr(macaddr)) { 2075 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 2076 eth_hw_addr_random(dev); 2077 } else { 2078 ether_addr_copy(dev->dev_addr, macaddr); 2079 } 2080 2081 SET_NETDEV_DEV(dev, &pdev->dev); 2082 dev_set_drvdata(&pdev->dev, dev); 2083 dev->ethtool_ops = &bcm_sysport_ethtool_ops; 2084 dev->netdev_ops = &bcm_sysport_netdev_ops; 2085 netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64); 2086 2087 /* HW supported features, none enabled by default */ 2088 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA | 2089 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2090 2091 /* Request the WOL interrupt and advertise suspend if available */ 2092 priv->wol_irq_disabled = 1; 2093 ret = devm_request_irq(&pdev->dev, priv->wol_irq, 2094 bcm_sysport_wol_isr, 0, dev->name, priv); 2095 if (!ret) 2096 device_set_wakeup_capable(&pdev->dev, 1); 2097 2098 /* Set the needed headroom once and for all */ 2099 BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8); 2100 dev->needed_headroom += sizeof(struct bcm_tsb); 2101 2102 /* libphy will adjust the link state accordingly */ 2103 netif_carrier_off(dev); 2104 2105 ret = register_netdev(dev); 2106 if (ret) { 2107 dev_err(&pdev->dev, "failed to register net_device\n"); 2108 goto err_deregister_fixed_link; 2109 } 2110 2111 priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK; 2112 dev_info(&pdev->dev, 2113 "Broadcom SYSTEMPORT%s" REV_FMT 2114 " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n", 2115 priv->is_lite ? " Lite" : "", 2116 (priv->rev >> 8) & 0xff, priv->rev & 0xff, 2117 priv->base, priv->irq0, priv->irq1, txq, rxq); 2118 2119 return 0; 2120 2121 err_deregister_fixed_link: 2122 if (of_phy_is_fixed_link(dn)) 2123 of_phy_deregister_fixed_link(dn); 2124 err_free_netdev: 2125 free_netdev(dev); 2126 return ret; 2127 } 2128 2129 static int bcm_sysport_remove(struct platform_device *pdev) 2130 { 2131 struct net_device *dev = dev_get_drvdata(&pdev->dev); 2132 struct device_node *dn = pdev->dev.of_node; 2133 2134 /* Not much to do, ndo_close has been called 2135 * and we use managed allocations 2136 */ 2137 unregister_netdev(dev); 2138 if (of_phy_is_fixed_link(dn)) 2139 of_phy_deregister_fixed_link(dn); 2140 free_netdev(dev); 2141 dev_set_drvdata(&pdev->dev, NULL); 2142 2143 return 0; 2144 } 2145 2146 #ifdef CONFIG_PM_SLEEP 2147 static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv) 2148 { 2149 struct net_device *ndev = priv->netdev; 2150 unsigned int timeout = 1000; 2151 u32 reg; 2152 2153 /* Password has already been programmed */ 2154 reg = umac_readl(priv, UMAC_MPD_CTRL); 2155 reg |= MPD_EN; 2156 reg &= ~PSW_EN; 2157 if (priv->wolopts & WAKE_MAGICSECURE) 2158 reg |= PSW_EN; 2159 umac_writel(priv, reg, UMAC_MPD_CTRL); 2160 2161 /* Make sure RBUF entered WoL mode as result */ 2162 do { 2163 reg = rbuf_readl(priv, RBUF_STATUS); 2164 if (reg & RBUF_WOL_MODE) 2165 break; 2166 2167 udelay(10); 2168 } while (timeout-- > 0); 2169 2170 /* Do not leave the UniMAC RBUF matching only MPD packets */ 2171 if (!timeout) { 2172 reg = umac_readl(priv, UMAC_MPD_CTRL); 2173 reg &= ~MPD_EN; 2174 umac_writel(priv, reg, UMAC_MPD_CTRL); 2175 netif_err(priv, wol, ndev, "failed to enter WOL mode\n"); 2176 return -ETIMEDOUT; 2177 } 2178 2179 /* UniMAC receive needs to be turned on */ 2180 umac_enable_set(priv, CMD_RX_EN, 1); 2181 2182 /* Enable the interrupt wake-up source */ 2183 intrl2_0_mask_clear(priv, INTRL2_0_MPD); 2184 2185 netif_dbg(priv, wol, ndev, "entered WOL mode\n"); 2186 2187 return 0; 2188 } 2189 2190 static int bcm_sysport_suspend(struct device *d) 2191 { 2192 struct net_device *dev = dev_get_drvdata(d); 2193 struct bcm_sysport_priv *priv = netdev_priv(dev); 2194 unsigned int i; 2195 int ret = 0; 2196 u32 reg; 2197 2198 if (!netif_running(dev)) 2199 return 0; 2200 2201 bcm_sysport_netif_stop(dev); 2202 2203 phy_suspend(dev->phydev); 2204 2205 netif_device_detach(dev); 2206 2207 /* Disable UniMAC RX */ 2208 umac_enable_set(priv, CMD_RX_EN, 0); 2209 2210 ret = rdma_enable_set(priv, 0); 2211 if (ret) { 2212 netdev_err(dev, "RDMA timeout!\n"); 2213 return ret; 2214 } 2215 2216 /* Disable RXCHK if enabled */ 2217 if (priv->rx_chk_en) { 2218 reg = rxchk_readl(priv, RXCHK_CONTROL); 2219 reg &= ~RXCHK_EN; 2220 rxchk_writel(priv, reg, RXCHK_CONTROL); 2221 } 2222 2223 /* Flush RX pipe */ 2224 if (!priv->wolopts) 2225 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); 2226 2227 ret = tdma_enable_set(priv, 0); 2228 if (ret) { 2229 netdev_err(dev, "TDMA timeout!\n"); 2230 return ret; 2231 } 2232 2233 /* Wait for a packet boundary */ 2234 usleep_range(2000, 3000); 2235 2236 umac_enable_set(priv, CMD_TX_EN, 0); 2237 2238 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); 2239 2240 /* Free RX/TX rings SW structures */ 2241 for (i = 0; i < dev->num_tx_queues; i++) 2242 bcm_sysport_fini_tx_ring(priv, i); 2243 bcm_sysport_fini_rx_ring(priv); 2244 2245 /* Get prepared for Wake-on-LAN */ 2246 if (device_may_wakeup(d) && priv->wolopts) 2247 ret = bcm_sysport_suspend_to_wol(priv); 2248 2249 return ret; 2250 } 2251 2252 static int bcm_sysport_resume(struct device *d) 2253 { 2254 struct net_device *dev = dev_get_drvdata(d); 2255 struct bcm_sysport_priv *priv = netdev_priv(dev); 2256 unsigned int i; 2257 u32 reg; 2258 int ret; 2259 2260 if (!netif_running(dev)) 2261 return 0; 2262 2263 umac_reset(priv); 2264 2265 /* We may have been suspended and never received a WOL event that 2266 * would turn off MPD detection, take care of that now 2267 */ 2268 bcm_sysport_resume_from_wol(priv); 2269 2270 /* Initialize both hardware and software ring */ 2271 for (i = 0; i < dev->num_tx_queues; i++) { 2272 ret = bcm_sysport_init_tx_ring(priv, i); 2273 if (ret) { 2274 netdev_err(dev, "failed to initialize TX ring %d\n", 2275 i); 2276 goto out_free_tx_rings; 2277 } 2278 } 2279 2280 /* Initialize linked-list */ 2281 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); 2282 2283 /* Initialize RX ring */ 2284 ret = bcm_sysport_init_rx_ring(priv); 2285 if (ret) { 2286 netdev_err(dev, "failed to initialize RX ring\n"); 2287 goto out_free_rx_ring; 2288 } 2289 2290 netif_device_attach(dev); 2291 2292 /* RX pipe enable */ 2293 topctrl_writel(priv, 0, RX_FLUSH_CNTL); 2294 2295 ret = rdma_enable_set(priv, 1); 2296 if (ret) { 2297 netdev_err(dev, "failed to enable RDMA\n"); 2298 goto out_free_rx_ring; 2299 } 2300 2301 /* Enable rxhck */ 2302 if (priv->rx_chk_en) { 2303 reg = rxchk_readl(priv, RXCHK_CONTROL); 2304 reg |= RXCHK_EN; 2305 rxchk_writel(priv, reg, RXCHK_CONTROL); 2306 } 2307 2308 rbuf_init(priv); 2309 2310 /* Set maximum frame length */ 2311 if (!priv->is_lite) 2312 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2313 else 2314 gib_set_pad_extension(priv); 2315 2316 /* Set MAC address */ 2317 umac_set_hw_addr(priv, dev->dev_addr); 2318 2319 umac_enable_set(priv, CMD_RX_EN, 1); 2320 2321 /* TX pipe enable */ 2322 topctrl_writel(priv, 0, TX_FLUSH_CNTL); 2323 2324 umac_enable_set(priv, CMD_TX_EN, 1); 2325 2326 ret = tdma_enable_set(priv, 1); 2327 if (ret) { 2328 netdev_err(dev, "TDMA timeout!\n"); 2329 goto out_free_rx_ring; 2330 } 2331 2332 phy_resume(dev->phydev); 2333 2334 bcm_sysport_netif_start(dev); 2335 2336 return 0; 2337 2338 out_free_rx_ring: 2339 bcm_sysport_fini_rx_ring(priv); 2340 out_free_tx_rings: 2341 for (i = 0; i < dev->num_tx_queues; i++) 2342 bcm_sysport_fini_tx_ring(priv, i); 2343 return ret; 2344 } 2345 #endif 2346 2347 static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops, 2348 bcm_sysport_suspend, bcm_sysport_resume); 2349 2350 static struct platform_driver bcm_sysport_driver = { 2351 .probe = bcm_sysport_probe, 2352 .remove = bcm_sysport_remove, 2353 .driver = { 2354 .name = "brcm-systemport", 2355 .of_match_table = bcm_sysport_of_match, 2356 .pm = &bcm_sysport_pm_ops, 2357 }, 2358 }; 2359 module_platform_driver(bcm_sysport_driver); 2360 2361 MODULE_AUTHOR("Broadcom Corporation"); 2362 MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver"); 2363 MODULE_ALIAS("platform:brcm-systemport"); 2364 MODULE_LICENSE("GPL"); 2365