1 /* 2 * Broadcom BCM7xxx System Port Ethernet MAC driver 3 * 4 * Copyright (C) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/netdevice.h> 18 #include <linux/etherdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/phy.h> 24 #include <linux/phy_fixed.h> 25 #include <net/ip.h> 26 #include <net/ipv6.h> 27 28 #include "bcmsysport.h" 29 30 /* I/O accessors register helpers */ 31 #define BCM_SYSPORT_IO_MACRO(name, offset) \ 32 static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \ 33 { \ 34 u32 reg = __raw_readl(priv->base + offset + off); \ 35 return reg; \ 36 } \ 37 static inline void name##_writel(struct bcm_sysport_priv *priv, \ 38 u32 val, u32 off) \ 39 { \ 40 __raw_writel(val, priv->base + offset + off); \ 41 } \ 42 43 BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET); 44 BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET); 45 BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET); 46 BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET); 47 BCM_SYSPORT_IO_MACRO(rdma, SYS_PORT_RDMA_OFFSET); 48 BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET); 49 BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET); 50 BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET); 51 BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET); 52 BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET); 53 54 /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied 55 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths. 56 */ 57 #define BCM_SYSPORT_INTR_L2(which) \ 58 static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \ 59 u32 mask) \ 60 { \ 61 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \ 62 priv->irq##which##_mask &= ~(mask); \ 63 } \ 64 static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \ 65 u32 mask) \ 66 { \ 67 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \ 68 priv->irq##which##_mask |= (mask); \ 69 } \ 70 71 BCM_SYSPORT_INTR_L2(0) 72 BCM_SYSPORT_INTR_L2(1) 73 74 /* Register accesses to GISB/RBUS registers are expensive (few hundred 75 * nanoseconds), so keep the check for 64-bits explicit here to save 76 * one register write per-packet on 32-bits platforms. 77 */ 78 static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv, 79 void __iomem *d, 80 dma_addr_t addr) 81 { 82 #ifdef CONFIG_PHYS_ADDR_T_64BIT 83 __raw_writel(upper_32_bits(addr) & DESC_ADDR_HI_MASK, 84 d + DESC_ADDR_HI_STATUS_LEN); 85 #endif 86 __raw_writel(lower_32_bits(addr), d + DESC_ADDR_LO); 87 } 88 89 static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv, 90 struct dma_desc *desc, 91 unsigned int port) 92 { 93 /* Ports are latched, so write upper address first */ 94 tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port)); 95 tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port)); 96 } 97 98 /* Ethtool operations */ 99 static int bcm_sysport_set_settings(struct net_device *dev, 100 struct ethtool_cmd *cmd) 101 { 102 struct bcm_sysport_priv *priv = netdev_priv(dev); 103 104 if (!netif_running(dev)) 105 return -EINVAL; 106 107 return phy_ethtool_sset(priv->phydev, cmd); 108 } 109 110 static int bcm_sysport_get_settings(struct net_device *dev, 111 struct ethtool_cmd *cmd) 112 { 113 struct bcm_sysport_priv *priv = netdev_priv(dev); 114 115 if (!netif_running(dev)) 116 return -EINVAL; 117 118 return phy_ethtool_gset(priv->phydev, cmd); 119 } 120 121 static int bcm_sysport_set_rx_csum(struct net_device *dev, 122 netdev_features_t wanted) 123 { 124 struct bcm_sysport_priv *priv = netdev_priv(dev); 125 u32 reg; 126 127 priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM); 128 reg = rxchk_readl(priv, RXCHK_CONTROL); 129 if (priv->rx_chk_en) 130 reg |= RXCHK_EN; 131 else 132 reg &= ~RXCHK_EN; 133 134 /* If UniMAC forwards CRC, we need to skip over it to get 135 * a valid CHK bit to be set in the per-packet status word 136 */ 137 if (priv->rx_chk_en && priv->crc_fwd) 138 reg |= RXCHK_SKIP_FCS; 139 else 140 reg &= ~RXCHK_SKIP_FCS; 141 142 /* If Broadcom tags are enabled (e.g: using a switch), make 143 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom 144 * tag after the Ethernet MAC Source Address. 145 */ 146 if (netdev_uses_dsa(dev)) 147 reg |= RXCHK_BRCM_TAG_EN; 148 else 149 reg &= ~RXCHK_BRCM_TAG_EN; 150 151 rxchk_writel(priv, reg, RXCHK_CONTROL); 152 153 return 0; 154 } 155 156 static int bcm_sysport_set_tx_csum(struct net_device *dev, 157 netdev_features_t wanted) 158 { 159 struct bcm_sysport_priv *priv = netdev_priv(dev); 160 u32 reg; 161 162 /* Hardware transmit checksum requires us to enable the Transmit status 163 * block prepended to the packet contents 164 */ 165 priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 166 reg = tdma_readl(priv, TDMA_CONTROL); 167 if (priv->tsb_en) 168 reg |= TSB_EN; 169 else 170 reg &= ~TSB_EN; 171 tdma_writel(priv, reg, TDMA_CONTROL); 172 173 return 0; 174 } 175 176 static int bcm_sysport_set_features(struct net_device *dev, 177 netdev_features_t features) 178 { 179 netdev_features_t changed = features ^ dev->features; 180 netdev_features_t wanted = dev->wanted_features; 181 int ret = 0; 182 183 if (changed & NETIF_F_RXCSUM) 184 ret = bcm_sysport_set_rx_csum(dev, wanted); 185 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) 186 ret = bcm_sysport_set_tx_csum(dev, wanted); 187 188 return ret; 189 } 190 191 /* Hardware counters must be kept in sync because the order/offset 192 * is important here (order in structure declaration = order in hardware) 193 */ 194 static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = { 195 /* general stats */ 196 STAT_NETDEV(rx_packets), 197 STAT_NETDEV(tx_packets), 198 STAT_NETDEV(rx_bytes), 199 STAT_NETDEV(tx_bytes), 200 STAT_NETDEV(rx_errors), 201 STAT_NETDEV(tx_errors), 202 STAT_NETDEV(rx_dropped), 203 STAT_NETDEV(tx_dropped), 204 STAT_NETDEV(multicast), 205 /* UniMAC RSV counters */ 206 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 207 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 208 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 209 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 210 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 211 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 212 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 213 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 214 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 215 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 216 STAT_MIB_RX("rx_pkts", mib.rx.pkt), 217 STAT_MIB_RX("rx_bytes", mib.rx.bytes), 218 STAT_MIB_RX("rx_multicast", mib.rx.mca), 219 STAT_MIB_RX("rx_broadcast", mib.rx.bca), 220 STAT_MIB_RX("rx_fcs", mib.rx.fcs), 221 STAT_MIB_RX("rx_control", mib.rx.cf), 222 STAT_MIB_RX("rx_pause", mib.rx.pf), 223 STAT_MIB_RX("rx_unknown", mib.rx.uo), 224 STAT_MIB_RX("rx_align", mib.rx.aln), 225 STAT_MIB_RX("rx_outrange", mib.rx.flr), 226 STAT_MIB_RX("rx_code", mib.rx.cde), 227 STAT_MIB_RX("rx_carrier", mib.rx.fcr), 228 STAT_MIB_RX("rx_oversize", mib.rx.ovr), 229 STAT_MIB_RX("rx_jabber", mib.rx.jbr), 230 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue), 231 STAT_MIB_RX("rx_good_pkts", mib.rx.pok), 232 STAT_MIB_RX("rx_unicast", mib.rx.uc), 233 STAT_MIB_RX("rx_ppp", mib.rx.ppp), 234 STAT_MIB_RX("rx_crc", mib.rx.rcrc), 235 /* UniMAC TSV counters */ 236 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 237 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 238 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 239 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 240 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 241 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 242 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 243 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 244 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 245 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 246 STAT_MIB_TX("tx_pkts", mib.tx.pkts), 247 STAT_MIB_TX("tx_multicast", mib.tx.mca), 248 STAT_MIB_TX("tx_broadcast", mib.tx.bca), 249 STAT_MIB_TX("tx_pause", mib.tx.pf), 250 STAT_MIB_TX("tx_control", mib.tx.cf), 251 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs), 252 STAT_MIB_TX("tx_oversize", mib.tx.ovr), 253 STAT_MIB_TX("tx_defer", mib.tx.drf), 254 STAT_MIB_TX("tx_excess_defer", mib.tx.edf), 255 STAT_MIB_TX("tx_single_col", mib.tx.scl), 256 STAT_MIB_TX("tx_multi_col", mib.tx.mcl), 257 STAT_MIB_TX("tx_late_col", mib.tx.lcl), 258 STAT_MIB_TX("tx_excess_col", mib.tx.ecl), 259 STAT_MIB_TX("tx_frags", mib.tx.frg), 260 STAT_MIB_TX("tx_total_col", mib.tx.ncl), 261 STAT_MIB_TX("tx_jabber", mib.tx.jbr), 262 STAT_MIB_TX("tx_bytes", mib.tx.bytes), 263 STAT_MIB_TX("tx_good_pkts", mib.tx.pok), 264 STAT_MIB_TX("tx_unicast", mib.tx.uc), 265 /* UniMAC RUNT counters */ 266 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 267 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 268 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 269 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 270 /* RXCHK misc statistics */ 271 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR), 272 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc, 273 RXCHK_OTHER_DISC_CNTR), 274 /* RBUF misc statistics */ 275 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR), 276 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR), 277 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 278 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed), 279 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed), 280 }; 281 282 #define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats) 283 284 static void bcm_sysport_get_drvinfo(struct net_device *dev, 285 struct ethtool_drvinfo *info) 286 { 287 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 288 strlcpy(info->version, "0.1", sizeof(info->version)); 289 strlcpy(info->bus_info, "platform", sizeof(info->bus_info)); 290 info->n_stats = BCM_SYSPORT_STATS_LEN; 291 } 292 293 static u32 bcm_sysport_get_msglvl(struct net_device *dev) 294 { 295 struct bcm_sysport_priv *priv = netdev_priv(dev); 296 297 return priv->msg_enable; 298 } 299 300 static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable) 301 { 302 struct bcm_sysport_priv *priv = netdev_priv(dev); 303 304 priv->msg_enable = enable; 305 } 306 307 static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set) 308 { 309 switch (string_set) { 310 case ETH_SS_STATS: 311 return BCM_SYSPORT_STATS_LEN; 312 default: 313 return -EOPNOTSUPP; 314 } 315 } 316 317 static void bcm_sysport_get_strings(struct net_device *dev, 318 u32 stringset, u8 *data) 319 { 320 int i; 321 322 switch (stringset) { 323 case ETH_SS_STATS: 324 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 325 memcpy(data + i * ETH_GSTRING_LEN, 326 bcm_sysport_gstrings_stats[i].stat_string, 327 ETH_GSTRING_LEN); 328 } 329 break; 330 default: 331 break; 332 } 333 } 334 335 static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv) 336 { 337 int i, j = 0; 338 339 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 340 const struct bcm_sysport_stats *s; 341 u8 offset = 0; 342 u32 val = 0; 343 char *p; 344 345 s = &bcm_sysport_gstrings_stats[i]; 346 switch (s->type) { 347 case BCM_SYSPORT_STAT_NETDEV: 348 case BCM_SYSPORT_STAT_SOFT: 349 continue; 350 case BCM_SYSPORT_STAT_MIB_RX: 351 case BCM_SYSPORT_STAT_MIB_TX: 352 case BCM_SYSPORT_STAT_RUNT: 353 if (s->type != BCM_SYSPORT_STAT_MIB_RX) 354 offset = UMAC_MIB_STAT_OFFSET; 355 val = umac_readl(priv, UMAC_MIB_START + j + offset); 356 break; 357 case BCM_SYSPORT_STAT_RXCHK: 358 val = rxchk_readl(priv, s->reg_offset); 359 if (val == ~0) 360 rxchk_writel(priv, 0, s->reg_offset); 361 break; 362 case BCM_SYSPORT_STAT_RBUF: 363 val = rbuf_readl(priv, s->reg_offset); 364 if (val == ~0) 365 rbuf_writel(priv, 0, s->reg_offset); 366 break; 367 } 368 369 j += s->stat_sizeof; 370 p = (char *)priv + s->stat_offset; 371 *(u32 *)p = val; 372 } 373 374 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n"); 375 } 376 377 static void bcm_sysport_get_stats(struct net_device *dev, 378 struct ethtool_stats *stats, u64 *data) 379 { 380 struct bcm_sysport_priv *priv = netdev_priv(dev); 381 int i; 382 383 if (netif_running(dev)) 384 bcm_sysport_update_mib_counters(priv); 385 386 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 387 const struct bcm_sysport_stats *s; 388 char *p; 389 390 s = &bcm_sysport_gstrings_stats[i]; 391 if (s->type == BCM_SYSPORT_STAT_NETDEV) 392 p = (char *)&dev->stats; 393 else 394 p = (char *)priv; 395 p += s->stat_offset; 396 data[i] = *(u32 *)p; 397 } 398 } 399 400 static void bcm_sysport_get_wol(struct net_device *dev, 401 struct ethtool_wolinfo *wol) 402 { 403 struct bcm_sysport_priv *priv = netdev_priv(dev); 404 u32 reg; 405 406 wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE; 407 wol->wolopts = priv->wolopts; 408 409 if (!(priv->wolopts & WAKE_MAGICSECURE)) 410 return; 411 412 /* Return the programmed SecureOn password */ 413 reg = umac_readl(priv, UMAC_PSW_MS); 414 put_unaligned_be16(reg, &wol->sopass[0]); 415 reg = umac_readl(priv, UMAC_PSW_LS); 416 put_unaligned_be32(reg, &wol->sopass[2]); 417 } 418 419 static int bcm_sysport_set_wol(struct net_device *dev, 420 struct ethtool_wolinfo *wol) 421 { 422 struct bcm_sysport_priv *priv = netdev_priv(dev); 423 struct device *kdev = &priv->pdev->dev; 424 u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE; 425 426 if (!device_can_wakeup(kdev)) 427 return -ENOTSUPP; 428 429 if (wol->wolopts & ~supported) 430 return -EINVAL; 431 432 /* Program the SecureOn password */ 433 if (wol->wolopts & WAKE_MAGICSECURE) { 434 umac_writel(priv, get_unaligned_be16(&wol->sopass[0]), 435 UMAC_PSW_MS); 436 umac_writel(priv, get_unaligned_be32(&wol->sopass[2]), 437 UMAC_PSW_LS); 438 } 439 440 /* Flag the device and relevant IRQ as wakeup capable */ 441 if (wol->wolopts) { 442 device_set_wakeup_enable(kdev, 1); 443 if (priv->wol_irq_disabled) 444 enable_irq_wake(priv->wol_irq); 445 priv->wol_irq_disabled = 0; 446 } else { 447 device_set_wakeup_enable(kdev, 0); 448 /* Avoid unbalanced disable_irq_wake calls */ 449 if (!priv->wol_irq_disabled) 450 disable_irq_wake(priv->wol_irq); 451 priv->wol_irq_disabled = 1; 452 } 453 454 priv->wolopts = wol->wolopts; 455 456 return 0; 457 } 458 459 static int bcm_sysport_get_coalesce(struct net_device *dev, 460 struct ethtool_coalesce *ec) 461 { 462 struct bcm_sysport_priv *priv = netdev_priv(dev); 463 u32 reg; 464 465 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0)); 466 467 ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000; 468 ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK; 469 470 reg = rdma_readl(priv, RDMA_MBDONE_INTR); 471 472 ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000; 473 ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK; 474 475 return 0; 476 } 477 478 static int bcm_sysport_set_coalesce(struct net_device *dev, 479 struct ethtool_coalesce *ec) 480 { 481 struct bcm_sysport_priv *priv = netdev_priv(dev); 482 unsigned int i; 483 u32 reg; 484 485 /* Base system clock is 125Mhz, DMA timeout is this reference clock 486 * divided by 1024, which yield roughly 8.192 us, our maximum value has 487 * to fit in the RING_TIMEOUT_MASK (16 bits). 488 */ 489 if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK || 490 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 || 491 ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK || 492 ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1) 493 return -EINVAL; 494 495 if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) || 496 (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)) 497 return -EINVAL; 498 499 for (i = 0; i < dev->num_tx_queues; i++) { 500 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i)); 501 reg &= ~(RING_INTR_THRESH_MASK | 502 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT); 503 reg |= ec->tx_max_coalesced_frames; 504 reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) << 505 RING_TIMEOUT_SHIFT; 506 tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i)); 507 } 508 509 reg = rdma_readl(priv, RDMA_MBDONE_INTR); 510 reg &= ~(RDMA_INTR_THRESH_MASK | 511 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT); 512 reg |= ec->rx_max_coalesced_frames; 513 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192) << 514 RDMA_TIMEOUT_SHIFT; 515 rdma_writel(priv, reg, RDMA_MBDONE_INTR); 516 517 return 0; 518 } 519 520 static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb) 521 { 522 dev_kfree_skb_any(cb->skb); 523 cb->skb = NULL; 524 dma_unmap_addr_set(cb, dma_addr, 0); 525 } 526 527 static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv, 528 struct bcm_sysport_cb *cb) 529 { 530 struct device *kdev = &priv->pdev->dev; 531 struct net_device *ndev = priv->netdev; 532 struct sk_buff *skb, *rx_skb; 533 dma_addr_t mapping; 534 535 /* Allocate a new SKB for a new packet */ 536 skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH); 537 if (!skb) { 538 priv->mib.alloc_rx_buff_failed++; 539 netif_err(priv, rx_err, ndev, "SKB alloc failed\n"); 540 return NULL; 541 } 542 543 mapping = dma_map_single(kdev, skb->data, 544 RX_BUF_LENGTH, DMA_FROM_DEVICE); 545 if (dma_mapping_error(kdev, mapping)) { 546 priv->mib.rx_dma_failed++; 547 dev_kfree_skb_any(skb); 548 netif_err(priv, rx_err, ndev, "DMA mapping failure\n"); 549 return NULL; 550 } 551 552 /* Grab the current SKB on the ring */ 553 rx_skb = cb->skb; 554 if (likely(rx_skb)) 555 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 556 RX_BUF_LENGTH, DMA_FROM_DEVICE); 557 558 /* Put the new SKB on the ring */ 559 cb->skb = skb; 560 dma_unmap_addr_set(cb, dma_addr, mapping); 561 dma_desc_set_addr(priv, cb->bd_addr, mapping); 562 563 netif_dbg(priv, rx_status, ndev, "RX refill\n"); 564 565 /* Return the current SKB to the caller */ 566 return rx_skb; 567 } 568 569 static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv) 570 { 571 struct bcm_sysport_cb *cb; 572 struct sk_buff *skb; 573 unsigned int i; 574 575 for (i = 0; i < priv->num_rx_bds; i++) { 576 cb = &priv->rx_cbs[i]; 577 skb = bcm_sysport_rx_refill(priv, cb); 578 if (skb) 579 dev_kfree_skb(skb); 580 if (!cb->skb) 581 return -ENOMEM; 582 } 583 584 return 0; 585 } 586 587 /* Poll the hardware for up to budget packets to process */ 588 static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv, 589 unsigned int budget) 590 { 591 struct net_device *ndev = priv->netdev; 592 unsigned int processed = 0, to_process; 593 struct bcm_sysport_cb *cb; 594 struct sk_buff *skb; 595 unsigned int p_index; 596 u16 len, status; 597 struct bcm_rsb *rsb; 598 599 /* Determine how much we should process since last call */ 600 p_index = rdma_readl(priv, RDMA_PROD_INDEX); 601 p_index &= RDMA_PROD_INDEX_MASK; 602 603 if (p_index < priv->rx_c_index) 604 to_process = (RDMA_CONS_INDEX_MASK + 1) - 605 priv->rx_c_index + p_index; 606 else 607 to_process = p_index - priv->rx_c_index; 608 609 netif_dbg(priv, rx_status, ndev, 610 "p_index=%d rx_c_index=%d to_process=%d\n", 611 p_index, priv->rx_c_index, to_process); 612 613 while ((processed < to_process) && (processed < budget)) { 614 cb = &priv->rx_cbs[priv->rx_read_ptr]; 615 skb = bcm_sysport_rx_refill(priv, cb); 616 617 618 /* We do not have a backing SKB, so we do not a corresponding 619 * DMA mapping for this incoming packet since 620 * bcm_sysport_rx_refill always either has both skb and mapping 621 * or none. 622 */ 623 if (unlikely(!skb)) { 624 netif_err(priv, rx_err, ndev, "out of memory!\n"); 625 ndev->stats.rx_dropped++; 626 ndev->stats.rx_errors++; 627 goto next; 628 } 629 630 /* Extract the Receive Status Block prepended */ 631 rsb = (struct bcm_rsb *)skb->data; 632 len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK; 633 status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) & 634 DESC_STATUS_MASK; 635 636 netif_dbg(priv, rx_status, ndev, 637 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n", 638 p_index, priv->rx_c_index, priv->rx_read_ptr, 639 len, status); 640 641 if (unlikely(len > RX_BUF_LENGTH)) { 642 netif_err(priv, rx_status, ndev, "oversized packet\n"); 643 ndev->stats.rx_length_errors++; 644 ndev->stats.rx_errors++; 645 dev_kfree_skb_any(skb); 646 goto next; 647 } 648 649 if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) { 650 netif_err(priv, rx_status, ndev, "fragmented packet!\n"); 651 ndev->stats.rx_dropped++; 652 ndev->stats.rx_errors++; 653 dev_kfree_skb_any(skb); 654 goto next; 655 } 656 657 if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) { 658 netif_err(priv, rx_err, ndev, "error packet\n"); 659 if (status & RX_STATUS_OVFLOW) 660 ndev->stats.rx_over_errors++; 661 ndev->stats.rx_dropped++; 662 ndev->stats.rx_errors++; 663 dev_kfree_skb_any(skb); 664 goto next; 665 } 666 667 skb_put(skb, len); 668 669 /* Hardware validated our checksum */ 670 if (likely(status & DESC_L4_CSUM)) 671 skb->ip_summed = CHECKSUM_UNNECESSARY; 672 673 /* Hardware pre-pends packets with 2bytes before Ethernet 674 * header plus we have the Receive Status Block, strip off all 675 * of this from the SKB. 676 */ 677 skb_pull(skb, sizeof(*rsb) + 2); 678 len -= (sizeof(*rsb) + 2); 679 680 /* UniMAC may forward CRC */ 681 if (priv->crc_fwd) { 682 skb_trim(skb, len - ETH_FCS_LEN); 683 len -= ETH_FCS_LEN; 684 } 685 686 skb->protocol = eth_type_trans(skb, ndev); 687 ndev->stats.rx_packets++; 688 ndev->stats.rx_bytes += len; 689 690 napi_gro_receive(&priv->napi, skb); 691 next: 692 processed++; 693 priv->rx_read_ptr++; 694 695 if (priv->rx_read_ptr == priv->num_rx_bds) 696 priv->rx_read_ptr = 0; 697 } 698 699 return processed; 700 } 701 702 static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_priv *priv, 703 struct bcm_sysport_cb *cb, 704 unsigned int *bytes_compl, 705 unsigned int *pkts_compl) 706 { 707 struct device *kdev = &priv->pdev->dev; 708 struct net_device *ndev = priv->netdev; 709 710 if (cb->skb) { 711 ndev->stats.tx_bytes += cb->skb->len; 712 *bytes_compl += cb->skb->len; 713 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 714 dma_unmap_len(cb, dma_len), 715 DMA_TO_DEVICE); 716 ndev->stats.tx_packets++; 717 (*pkts_compl)++; 718 bcm_sysport_free_cb(cb); 719 /* SKB fragment */ 720 } else if (dma_unmap_addr(cb, dma_addr)) { 721 ndev->stats.tx_bytes += dma_unmap_len(cb, dma_len); 722 dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr), 723 dma_unmap_len(cb, dma_len), DMA_TO_DEVICE); 724 dma_unmap_addr_set(cb, dma_addr, 0); 725 } 726 } 727 728 /* Reclaim queued SKBs for transmission completion, lockless version */ 729 static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, 730 struct bcm_sysport_tx_ring *ring) 731 { 732 struct net_device *ndev = priv->netdev; 733 unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs; 734 unsigned int pkts_compl = 0, bytes_compl = 0; 735 struct bcm_sysport_cb *cb; 736 struct netdev_queue *txq; 737 u32 hw_ind; 738 739 txq = netdev_get_tx_queue(ndev, ring->index); 740 741 /* Compute how many descriptors have been processed since last call */ 742 hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index)); 743 c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK; 744 ring->p_index = (hw_ind & RING_PROD_INDEX_MASK); 745 746 last_c_index = ring->c_index; 747 num_tx_cbs = ring->size; 748 749 c_index &= (num_tx_cbs - 1); 750 751 if (c_index >= last_c_index) 752 last_tx_cn = c_index - last_c_index; 753 else 754 last_tx_cn = num_tx_cbs - last_c_index + c_index; 755 756 netif_dbg(priv, tx_done, ndev, 757 "ring=%d c_index=%d last_tx_cn=%d last_c_index=%d\n", 758 ring->index, c_index, last_tx_cn, last_c_index); 759 760 while (last_tx_cn-- > 0) { 761 cb = ring->cbs + last_c_index; 762 bcm_sysport_tx_reclaim_one(priv, cb, &bytes_compl, &pkts_compl); 763 764 ring->desc_count++; 765 last_c_index++; 766 last_c_index &= (num_tx_cbs - 1); 767 } 768 769 ring->c_index = c_index; 770 771 if (netif_tx_queue_stopped(txq) && pkts_compl) 772 netif_tx_wake_queue(txq); 773 774 netif_dbg(priv, tx_done, ndev, 775 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n", 776 ring->index, ring->c_index, pkts_compl, bytes_compl); 777 778 return pkts_compl; 779 } 780 781 /* Locked version of the per-ring TX reclaim routine */ 782 static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, 783 struct bcm_sysport_tx_ring *ring) 784 { 785 unsigned int released; 786 unsigned long flags; 787 788 spin_lock_irqsave(&ring->lock, flags); 789 released = __bcm_sysport_tx_reclaim(priv, ring); 790 spin_unlock_irqrestore(&ring->lock, flags); 791 792 return released; 793 } 794 795 static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget) 796 { 797 struct bcm_sysport_tx_ring *ring = 798 container_of(napi, struct bcm_sysport_tx_ring, napi); 799 unsigned int work_done = 0; 800 801 work_done = bcm_sysport_tx_reclaim(ring->priv, ring); 802 803 if (work_done == 0) { 804 napi_complete(napi); 805 /* re-enable TX interrupt */ 806 intrl2_1_mask_clear(ring->priv, BIT(ring->index)); 807 808 return 0; 809 } 810 811 return budget; 812 } 813 814 static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv) 815 { 816 unsigned int q; 817 818 for (q = 0; q < priv->netdev->num_tx_queues; q++) 819 bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]); 820 } 821 822 static int bcm_sysport_poll(struct napi_struct *napi, int budget) 823 { 824 struct bcm_sysport_priv *priv = 825 container_of(napi, struct bcm_sysport_priv, napi); 826 unsigned int work_done = 0; 827 828 work_done = bcm_sysport_desc_rx(priv, budget); 829 830 priv->rx_c_index += work_done; 831 priv->rx_c_index &= RDMA_CONS_INDEX_MASK; 832 rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX); 833 834 if (work_done < budget) { 835 napi_complete(napi); 836 /* re-enable RX interrupts */ 837 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE); 838 } 839 840 return work_done; 841 } 842 843 static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv) 844 { 845 u32 reg; 846 847 /* Stop monitoring MPD interrupt */ 848 intrl2_0_mask_set(priv, INTRL2_0_MPD); 849 850 /* Clear the MagicPacket detection logic */ 851 reg = umac_readl(priv, UMAC_MPD_CTRL); 852 reg &= ~MPD_EN; 853 umac_writel(priv, reg, UMAC_MPD_CTRL); 854 855 netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n"); 856 } 857 858 /* RX and misc interrupt routine */ 859 static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id) 860 { 861 struct net_device *dev = dev_id; 862 struct bcm_sysport_priv *priv = netdev_priv(dev); 863 864 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 865 ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 866 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 867 868 if (unlikely(priv->irq0_stat == 0)) { 869 netdev_warn(priv->netdev, "spurious RX interrupt\n"); 870 return IRQ_NONE; 871 } 872 873 if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) { 874 if (likely(napi_schedule_prep(&priv->napi))) { 875 /* disable RX interrupts */ 876 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE); 877 __napi_schedule(&priv->napi); 878 } 879 } 880 881 /* TX ring is full, perform a full reclaim since we do not know 882 * which one would trigger this interrupt 883 */ 884 if (priv->irq0_stat & INTRL2_0_TX_RING_FULL) 885 bcm_sysport_tx_reclaim_all(priv); 886 887 if (priv->irq0_stat & INTRL2_0_MPD) { 888 netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n"); 889 bcm_sysport_resume_from_wol(priv); 890 } 891 892 return IRQ_HANDLED; 893 } 894 895 /* TX interrupt service routine */ 896 static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id) 897 { 898 struct net_device *dev = dev_id; 899 struct bcm_sysport_priv *priv = netdev_priv(dev); 900 struct bcm_sysport_tx_ring *txr; 901 unsigned int ring; 902 903 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 904 ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 905 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 906 907 if (unlikely(priv->irq1_stat == 0)) { 908 netdev_warn(priv->netdev, "spurious TX interrupt\n"); 909 return IRQ_NONE; 910 } 911 912 for (ring = 0; ring < dev->num_tx_queues; ring++) { 913 if (!(priv->irq1_stat & BIT(ring))) 914 continue; 915 916 txr = &priv->tx_rings[ring]; 917 918 if (likely(napi_schedule_prep(&txr->napi))) { 919 intrl2_1_mask_set(priv, BIT(ring)); 920 __napi_schedule(&txr->napi); 921 } 922 } 923 924 return IRQ_HANDLED; 925 } 926 927 static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id) 928 { 929 struct bcm_sysport_priv *priv = dev_id; 930 931 pm_wakeup_event(&priv->pdev->dev, 0); 932 933 return IRQ_HANDLED; 934 } 935 936 #ifdef CONFIG_NET_POLL_CONTROLLER 937 static void bcm_sysport_poll_controller(struct net_device *dev) 938 { 939 struct bcm_sysport_priv *priv = netdev_priv(dev); 940 941 disable_irq(priv->irq0); 942 bcm_sysport_rx_isr(priv->irq0, priv); 943 enable_irq(priv->irq0); 944 945 disable_irq(priv->irq1); 946 bcm_sysport_tx_isr(priv->irq1, priv); 947 enable_irq(priv->irq1); 948 } 949 #endif 950 951 static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb, 952 struct net_device *dev) 953 { 954 struct sk_buff *nskb; 955 struct bcm_tsb *tsb; 956 u32 csum_info; 957 u8 ip_proto; 958 u16 csum_start; 959 u16 ip_ver; 960 961 /* Re-allocate SKB if needed */ 962 if (unlikely(skb_headroom(skb) < sizeof(*tsb))) { 963 nskb = skb_realloc_headroom(skb, sizeof(*tsb)); 964 dev_kfree_skb(skb); 965 if (!nskb) { 966 dev->stats.tx_errors++; 967 dev->stats.tx_dropped++; 968 return NULL; 969 } 970 skb = nskb; 971 } 972 973 tsb = (struct bcm_tsb *)skb_push(skb, sizeof(*tsb)); 974 /* Zero-out TSB by default */ 975 memset(tsb, 0, sizeof(*tsb)); 976 977 if (skb->ip_summed == CHECKSUM_PARTIAL) { 978 ip_ver = htons(skb->protocol); 979 switch (ip_ver) { 980 case ETH_P_IP: 981 ip_proto = ip_hdr(skb)->protocol; 982 break; 983 case ETH_P_IPV6: 984 ip_proto = ipv6_hdr(skb)->nexthdr; 985 break; 986 default: 987 return skb; 988 } 989 990 /* Get the checksum offset and the L4 (transport) offset */ 991 csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb); 992 csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK; 993 csum_info |= (csum_start << L4_PTR_SHIFT); 994 995 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { 996 csum_info |= L4_LENGTH_VALID; 997 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) 998 csum_info |= L4_UDP; 999 } else { 1000 csum_info = 0; 1001 } 1002 1003 tsb->l4_ptr_dest_map = csum_info; 1004 } 1005 1006 return skb; 1007 } 1008 1009 static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb, 1010 struct net_device *dev) 1011 { 1012 struct bcm_sysport_priv *priv = netdev_priv(dev); 1013 struct device *kdev = &priv->pdev->dev; 1014 struct bcm_sysport_tx_ring *ring; 1015 struct bcm_sysport_cb *cb; 1016 struct netdev_queue *txq; 1017 struct dma_desc *desc; 1018 unsigned int skb_len; 1019 unsigned long flags; 1020 dma_addr_t mapping; 1021 u32 len_status; 1022 u16 queue; 1023 int ret; 1024 1025 queue = skb_get_queue_mapping(skb); 1026 txq = netdev_get_tx_queue(dev, queue); 1027 ring = &priv->tx_rings[queue]; 1028 1029 /* lock against tx reclaim in BH context and TX ring full interrupt */ 1030 spin_lock_irqsave(&ring->lock, flags); 1031 if (unlikely(ring->desc_count == 0)) { 1032 netif_tx_stop_queue(txq); 1033 netdev_err(dev, "queue %d awake and ring full!\n", queue); 1034 ret = NETDEV_TX_BUSY; 1035 goto out; 1036 } 1037 1038 /* Insert TSB and checksum infos */ 1039 if (priv->tsb_en) { 1040 skb = bcm_sysport_insert_tsb(skb, dev); 1041 if (!skb) { 1042 ret = NETDEV_TX_OK; 1043 goto out; 1044 } 1045 } 1046 1047 /* The Ethernet switch we are interfaced with needs packets to be at 1048 * least 64 bytes (including FCS) otherwise they will be discarded when 1049 * they enter the switch port logic. When Broadcom tags are enabled, we 1050 * need to make sure that packets are at least 68 bytes 1051 * (including FCS and tag) because the length verification is done after 1052 * the Broadcom tag is stripped off the ingress packet. 1053 */ 1054 if (skb_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) { 1055 ret = NETDEV_TX_OK; 1056 goto out; 1057 } 1058 1059 skb_len = skb->len < ETH_ZLEN + ENET_BRCM_TAG_LEN ? 1060 ETH_ZLEN + ENET_BRCM_TAG_LEN : skb->len; 1061 1062 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); 1063 if (dma_mapping_error(kdev, mapping)) { 1064 priv->mib.tx_dma_failed++; 1065 netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n", 1066 skb->data, skb_len); 1067 ret = NETDEV_TX_OK; 1068 goto out; 1069 } 1070 1071 /* Remember the SKB for future freeing */ 1072 cb = &ring->cbs[ring->curr_desc]; 1073 cb->skb = skb; 1074 dma_unmap_addr_set(cb, dma_addr, mapping); 1075 dma_unmap_len_set(cb, dma_len, skb_len); 1076 1077 /* Fetch a descriptor entry from our pool */ 1078 desc = ring->desc_cpu; 1079 1080 desc->addr_lo = lower_32_bits(mapping); 1081 len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK; 1082 len_status |= (skb_len << DESC_LEN_SHIFT); 1083 len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) << 1084 DESC_STATUS_SHIFT; 1085 if (skb->ip_summed == CHECKSUM_PARTIAL) 1086 len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT); 1087 1088 ring->curr_desc++; 1089 if (ring->curr_desc == ring->size) 1090 ring->curr_desc = 0; 1091 ring->desc_count--; 1092 1093 /* Ensure write completion of the descriptor status/length 1094 * in DRAM before the System Port WRITE_PORT register latches 1095 * the value 1096 */ 1097 wmb(); 1098 desc->addr_status_len = len_status; 1099 wmb(); 1100 1101 /* Write this descriptor address to the RING write port */ 1102 tdma_port_write_desc_addr(priv, desc, ring->index); 1103 1104 /* Check ring space and update SW control flow */ 1105 if (ring->desc_count == 0) 1106 netif_tx_stop_queue(txq); 1107 1108 netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n", 1109 ring->index, ring->desc_count, ring->curr_desc); 1110 1111 ret = NETDEV_TX_OK; 1112 out: 1113 spin_unlock_irqrestore(&ring->lock, flags); 1114 return ret; 1115 } 1116 1117 static void bcm_sysport_tx_timeout(struct net_device *dev) 1118 { 1119 netdev_warn(dev, "transmit timeout!\n"); 1120 1121 dev->trans_start = jiffies; 1122 dev->stats.tx_errors++; 1123 1124 netif_tx_wake_all_queues(dev); 1125 } 1126 1127 /* phylib adjust link callback */ 1128 static void bcm_sysport_adj_link(struct net_device *dev) 1129 { 1130 struct bcm_sysport_priv *priv = netdev_priv(dev); 1131 struct phy_device *phydev = priv->phydev; 1132 unsigned int changed = 0; 1133 u32 cmd_bits = 0, reg; 1134 1135 if (priv->old_link != phydev->link) { 1136 changed = 1; 1137 priv->old_link = phydev->link; 1138 } 1139 1140 if (priv->old_duplex != phydev->duplex) { 1141 changed = 1; 1142 priv->old_duplex = phydev->duplex; 1143 } 1144 1145 switch (phydev->speed) { 1146 case SPEED_2500: 1147 cmd_bits = CMD_SPEED_2500; 1148 break; 1149 case SPEED_1000: 1150 cmd_bits = CMD_SPEED_1000; 1151 break; 1152 case SPEED_100: 1153 cmd_bits = CMD_SPEED_100; 1154 break; 1155 case SPEED_10: 1156 cmd_bits = CMD_SPEED_10; 1157 break; 1158 default: 1159 break; 1160 } 1161 cmd_bits <<= CMD_SPEED_SHIFT; 1162 1163 if (phydev->duplex == DUPLEX_HALF) 1164 cmd_bits |= CMD_HD_EN; 1165 1166 if (priv->old_pause != phydev->pause) { 1167 changed = 1; 1168 priv->old_pause = phydev->pause; 1169 } 1170 1171 if (!phydev->pause) 1172 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 1173 1174 if (!changed) 1175 return; 1176 1177 if (phydev->link) { 1178 reg = umac_readl(priv, UMAC_CMD); 1179 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 1180 CMD_HD_EN | CMD_RX_PAUSE_IGNORE | 1181 CMD_TX_PAUSE_IGNORE); 1182 reg |= cmd_bits; 1183 umac_writel(priv, reg, UMAC_CMD); 1184 } 1185 1186 phy_print_status(priv->phydev); 1187 } 1188 1189 static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv, 1190 unsigned int index) 1191 { 1192 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; 1193 struct device *kdev = &priv->pdev->dev; 1194 size_t size; 1195 void *p; 1196 u32 reg; 1197 1198 /* Simple descriptors partitioning for now */ 1199 size = 256; 1200 1201 /* We just need one DMA descriptor which is DMA-able, since writing to 1202 * the port will allocate a new descriptor in its internal linked-list 1203 */ 1204 p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma, 1205 GFP_KERNEL); 1206 if (!p) { 1207 netif_err(priv, hw, priv->netdev, "DMA alloc failed\n"); 1208 return -ENOMEM; 1209 } 1210 1211 ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL); 1212 if (!ring->cbs) { 1213 netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); 1214 return -ENOMEM; 1215 } 1216 1217 /* Initialize SW view of the ring */ 1218 spin_lock_init(&ring->lock); 1219 ring->priv = priv; 1220 netif_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64); 1221 ring->index = index; 1222 ring->size = size; 1223 ring->alloc_size = ring->size; 1224 ring->desc_cpu = p; 1225 ring->desc_count = ring->size; 1226 ring->curr_desc = 0; 1227 1228 /* Initialize HW ring */ 1229 tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index)); 1230 tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index)); 1231 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index)); 1232 tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index)); 1233 tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index)); 1234 tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index)); 1235 1236 /* Program the number of descriptors as MAX_THRESHOLD and half of 1237 * its size for the hysteresis trigger 1238 */ 1239 tdma_writel(priv, ring->size | 1240 1 << RING_HYST_THRESH_SHIFT, 1241 TDMA_DESC_RING_MAX_HYST(index)); 1242 1243 /* Enable the ring queue in the arbiter */ 1244 reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN); 1245 reg |= (1 << index); 1246 tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN); 1247 1248 napi_enable(&ring->napi); 1249 1250 netif_dbg(priv, hw, priv->netdev, 1251 "TDMA cfg, size=%d, desc_cpu=%p\n", 1252 ring->size, ring->desc_cpu); 1253 1254 return 0; 1255 } 1256 1257 static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv, 1258 unsigned int index) 1259 { 1260 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; 1261 struct device *kdev = &priv->pdev->dev; 1262 u32 reg; 1263 1264 /* Caller should stop the TDMA engine */ 1265 reg = tdma_readl(priv, TDMA_STATUS); 1266 if (!(reg & TDMA_DISABLED)) 1267 netdev_warn(priv->netdev, "TDMA not stopped!\n"); 1268 1269 /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could 1270 * fail, so by checking this pointer we know whether the TX ring was 1271 * fully initialized or not. 1272 */ 1273 if (!ring->cbs) 1274 return; 1275 1276 napi_disable(&ring->napi); 1277 netif_napi_del(&ring->napi); 1278 1279 bcm_sysport_tx_reclaim(priv, ring); 1280 1281 kfree(ring->cbs); 1282 ring->cbs = NULL; 1283 1284 if (ring->desc_dma) { 1285 dma_free_coherent(kdev, sizeof(struct dma_desc), 1286 ring->desc_cpu, ring->desc_dma); 1287 ring->desc_dma = 0; 1288 } 1289 ring->size = 0; 1290 ring->alloc_size = 0; 1291 1292 netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n"); 1293 } 1294 1295 /* RDMA helper */ 1296 static inline int rdma_enable_set(struct bcm_sysport_priv *priv, 1297 unsigned int enable) 1298 { 1299 unsigned int timeout = 1000; 1300 u32 reg; 1301 1302 reg = rdma_readl(priv, RDMA_CONTROL); 1303 if (enable) 1304 reg |= RDMA_EN; 1305 else 1306 reg &= ~RDMA_EN; 1307 rdma_writel(priv, reg, RDMA_CONTROL); 1308 1309 /* Poll for RMDA disabling completion */ 1310 do { 1311 reg = rdma_readl(priv, RDMA_STATUS); 1312 if (!!(reg & RDMA_DISABLED) == !enable) 1313 return 0; 1314 usleep_range(1000, 2000); 1315 } while (timeout-- > 0); 1316 1317 netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n"); 1318 1319 return -ETIMEDOUT; 1320 } 1321 1322 /* TDMA helper */ 1323 static inline int tdma_enable_set(struct bcm_sysport_priv *priv, 1324 unsigned int enable) 1325 { 1326 unsigned int timeout = 1000; 1327 u32 reg; 1328 1329 reg = tdma_readl(priv, TDMA_CONTROL); 1330 if (enable) 1331 reg |= TDMA_EN; 1332 else 1333 reg &= ~TDMA_EN; 1334 tdma_writel(priv, reg, TDMA_CONTROL); 1335 1336 /* Poll for TMDA disabling completion */ 1337 do { 1338 reg = tdma_readl(priv, TDMA_STATUS); 1339 if (!!(reg & TDMA_DISABLED) == !enable) 1340 return 0; 1341 1342 usleep_range(1000, 2000); 1343 } while (timeout-- > 0); 1344 1345 netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n"); 1346 1347 return -ETIMEDOUT; 1348 } 1349 1350 static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv) 1351 { 1352 struct bcm_sysport_cb *cb; 1353 u32 reg; 1354 int ret; 1355 int i; 1356 1357 /* Initialize SW view of the RX ring */ 1358 priv->num_rx_bds = NUM_RX_DESC; 1359 priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET; 1360 priv->rx_c_index = 0; 1361 priv->rx_read_ptr = 0; 1362 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb), 1363 GFP_KERNEL); 1364 if (!priv->rx_cbs) { 1365 netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); 1366 return -ENOMEM; 1367 } 1368 1369 for (i = 0; i < priv->num_rx_bds; i++) { 1370 cb = priv->rx_cbs + i; 1371 cb->bd_addr = priv->rx_bds + i * DESC_SIZE; 1372 } 1373 1374 ret = bcm_sysport_alloc_rx_bufs(priv); 1375 if (ret) { 1376 netif_err(priv, hw, priv->netdev, "SKB allocation failed\n"); 1377 return ret; 1378 } 1379 1380 /* Initialize HW, ensure RDMA is disabled */ 1381 reg = rdma_readl(priv, RDMA_STATUS); 1382 if (!(reg & RDMA_DISABLED)) 1383 rdma_enable_set(priv, 0); 1384 1385 rdma_writel(priv, 0, RDMA_WRITE_PTR_LO); 1386 rdma_writel(priv, 0, RDMA_WRITE_PTR_HI); 1387 rdma_writel(priv, 0, RDMA_PROD_INDEX); 1388 rdma_writel(priv, 0, RDMA_CONS_INDEX); 1389 rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT | 1390 RX_BUF_LENGTH, RDMA_RING_BUF_SIZE); 1391 /* Operate the queue in ring mode */ 1392 rdma_writel(priv, 0, RDMA_START_ADDR_HI); 1393 rdma_writel(priv, 0, RDMA_START_ADDR_LO); 1394 rdma_writel(priv, 0, RDMA_END_ADDR_HI); 1395 rdma_writel(priv, NUM_HW_RX_DESC_WORDS - 1, RDMA_END_ADDR_LO); 1396 1397 rdma_writel(priv, 1, RDMA_MBDONE_INTR); 1398 1399 netif_dbg(priv, hw, priv->netdev, 1400 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n", 1401 priv->num_rx_bds, priv->rx_bds); 1402 1403 return 0; 1404 } 1405 1406 static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv) 1407 { 1408 struct bcm_sysport_cb *cb; 1409 unsigned int i; 1410 u32 reg; 1411 1412 /* Caller should ensure RDMA is disabled */ 1413 reg = rdma_readl(priv, RDMA_STATUS); 1414 if (!(reg & RDMA_DISABLED)) 1415 netdev_warn(priv->netdev, "RDMA not stopped!\n"); 1416 1417 for (i = 0; i < priv->num_rx_bds; i++) { 1418 cb = &priv->rx_cbs[i]; 1419 if (dma_unmap_addr(cb, dma_addr)) 1420 dma_unmap_single(&priv->pdev->dev, 1421 dma_unmap_addr(cb, dma_addr), 1422 RX_BUF_LENGTH, DMA_FROM_DEVICE); 1423 bcm_sysport_free_cb(cb); 1424 } 1425 1426 kfree(priv->rx_cbs); 1427 priv->rx_cbs = NULL; 1428 1429 netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n"); 1430 } 1431 1432 static void bcm_sysport_set_rx_mode(struct net_device *dev) 1433 { 1434 struct bcm_sysport_priv *priv = netdev_priv(dev); 1435 u32 reg; 1436 1437 reg = umac_readl(priv, UMAC_CMD); 1438 if (dev->flags & IFF_PROMISC) 1439 reg |= CMD_PROMISC; 1440 else 1441 reg &= ~CMD_PROMISC; 1442 umac_writel(priv, reg, UMAC_CMD); 1443 1444 /* No support for ALLMULTI */ 1445 if (dev->flags & IFF_ALLMULTI) 1446 return; 1447 } 1448 1449 static inline void umac_enable_set(struct bcm_sysport_priv *priv, 1450 u32 mask, unsigned int enable) 1451 { 1452 u32 reg; 1453 1454 reg = umac_readl(priv, UMAC_CMD); 1455 if (enable) 1456 reg |= mask; 1457 else 1458 reg &= ~mask; 1459 umac_writel(priv, reg, UMAC_CMD); 1460 1461 /* UniMAC stops on a packet boundary, wait for a full-sized packet 1462 * to be processed (1 msec). 1463 */ 1464 if (enable == 0) 1465 usleep_range(1000, 2000); 1466 } 1467 1468 static inline void umac_reset(struct bcm_sysport_priv *priv) 1469 { 1470 u32 reg; 1471 1472 reg = umac_readl(priv, UMAC_CMD); 1473 reg |= CMD_SW_RESET; 1474 umac_writel(priv, reg, UMAC_CMD); 1475 udelay(10); 1476 reg = umac_readl(priv, UMAC_CMD); 1477 reg &= ~CMD_SW_RESET; 1478 umac_writel(priv, reg, UMAC_CMD); 1479 } 1480 1481 static void umac_set_hw_addr(struct bcm_sysport_priv *priv, 1482 unsigned char *addr) 1483 { 1484 umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | 1485 (addr[2] << 8) | addr[3], UMAC_MAC0); 1486 umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); 1487 } 1488 1489 static void topctrl_flush(struct bcm_sysport_priv *priv) 1490 { 1491 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); 1492 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); 1493 mdelay(1); 1494 topctrl_writel(priv, 0, RX_FLUSH_CNTL); 1495 topctrl_writel(priv, 0, TX_FLUSH_CNTL); 1496 } 1497 1498 static int bcm_sysport_change_mac(struct net_device *dev, void *p) 1499 { 1500 struct bcm_sysport_priv *priv = netdev_priv(dev); 1501 struct sockaddr *addr = p; 1502 1503 if (!is_valid_ether_addr(addr->sa_data)) 1504 return -EINVAL; 1505 1506 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 1507 1508 /* interface is disabled, changes to MAC will be reflected on next 1509 * open call 1510 */ 1511 if (!netif_running(dev)) 1512 return 0; 1513 1514 umac_set_hw_addr(priv, dev->dev_addr); 1515 1516 return 0; 1517 } 1518 1519 static void bcm_sysport_netif_start(struct net_device *dev) 1520 { 1521 struct bcm_sysport_priv *priv = netdev_priv(dev); 1522 1523 /* Enable NAPI */ 1524 napi_enable(&priv->napi); 1525 1526 /* Enable RX interrupt and TX ring full interrupt */ 1527 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); 1528 1529 phy_start(priv->phydev); 1530 1531 /* Enable TX interrupts for the 32 TXQs */ 1532 intrl2_1_mask_clear(priv, 0xffffffff); 1533 1534 /* Last call before we start the real business */ 1535 netif_tx_start_all_queues(dev); 1536 } 1537 1538 static void rbuf_init(struct bcm_sysport_priv *priv) 1539 { 1540 u32 reg; 1541 1542 reg = rbuf_readl(priv, RBUF_CONTROL); 1543 reg |= RBUF_4B_ALGN | RBUF_RSB_EN; 1544 rbuf_writel(priv, reg, RBUF_CONTROL); 1545 } 1546 1547 static int bcm_sysport_open(struct net_device *dev) 1548 { 1549 struct bcm_sysport_priv *priv = netdev_priv(dev); 1550 unsigned int i; 1551 int ret; 1552 1553 /* Reset UniMAC */ 1554 umac_reset(priv); 1555 1556 /* Flush TX and RX FIFOs at TOPCTRL level */ 1557 topctrl_flush(priv); 1558 1559 /* Disable the UniMAC RX/TX */ 1560 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0); 1561 1562 /* Enable RBUF 2bytes alignment and Receive Status Block */ 1563 rbuf_init(priv); 1564 1565 /* Set maximum frame length */ 1566 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 1567 1568 /* Set MAC address */ 1569 umac_set_hw_addr(priv, dev->dev_addr); 1570 1571 /* Read CRC forward */ 1572 priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD); 1573 1574 priv->phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link, 1575 0, priv->phy_interface); 1576 if (!priv->phydev) { 1577 netdev_err(dev, "could not attach to PHY\n"); 1578 return -ENODEV; 1579 } 1580 1581 /* Reset house keeping link status */ 1582 priv->old_duplex = -1; 1583 priv->old_link = -1; 1584 priv->old_pause = -1; 1585 1586 /* mask all interrupts and request them */ 1587 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET); 1588 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1589 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); 1590 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET); 1591 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1592 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); 1593 1594 ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev); 1595 if (ret) { 1596 netdev_err(dev, "failed to request RX interrupt\n"); 1597 goto out_phy_disconnect; 1598 } 1599 1600 ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, dev->name, dev); 1601 if (ret) { 1602 netdev_err(dev, "failed to request TX interrupt\n"); 1603 goto out_free_irq0; 1604 } 1605 1606 /* Initialize both hardware and software ring */ 1607 for (i = 0; i < dev->num_tx_queues; i++) { 1608 ret = bcm_sysport_init_tx_ring(priv, i); 1609 if (ret) { 1610 netdev_err(dev, "failed to initialize TX ring %d\n", 1611 i); 1612 goto out_free_tx_ring; 1613 } 1614 } 1615 1616 /* Initialize linked-list */ 1617 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); 1618 1619 /* Initialize RX ring */ 1620 ret = bcm_sysport_init_rx_ring(priv); 1621 if (ret) { 1622 netdev_err(dev, "failed to initialize RX ring\n"); 1623 goto out_free_rx_ring; 1624 } 1625 1626 /* Turn on RDMA */ 1627 ret = rdma_enable_set(priv, 1); 1628 if (ret) 1629 goto out_free_rx_ring; 1630 1631 /* Turn on TDMA */ 1632 ret = tdma_enable_set(priv, 1); 1633 if (ret) 1634 goto out_clear_rx_int; 1635 1636 /* Turn on UniMAC TX/RX */ 1637 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1); 1638 1639 bcm_sysport_netif_start(dev); 1640 1641 return 0; 1642 1643 out_clear_rx_int: 1644 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); 1645 out_free_rx_ring: 1646 bcm_sysport_fini_rx_ring(priv); 1647 out_free_tx_ring: 1648 for (i = 0; i < dev->num_tx_queues; i++) 1649 bcm_sysport_fini_tx_ring(priv, i); 1650 free_irq(priv->irq1, dev); 1651 out_free_irq0: 1652 free_irq(priv->irq0, dev); 1653 out_phy_disconnect: 1654 phy_disconnect(priv->phydev); 1655 return ret; 1656 } 1657 1658 static void bcm_sysport_netif_stop(struct net_device *dev) 1659 { 1660 struct bcm_sysport_priv *priv = netdev_priv(dev); 1661 1662 /* stop all software from updating hardware */ 1663 netif_tx_stop_all_queues(dev); 1664 napi_disable(&priv->napi); 1665 phy_stop(priv->phydev); 1666 1667 /* mask all interrupts */ 1668 intrl2_0_mask_set(priv, 0xffffffff); 1669 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1670 intrl2_1_mask_set(priv, 0xffffffff); 1671 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1672 } 1673 1674 static int bcm_sysport_stop(struct net_device *dev) 1675 { 1676 struct bcm_sysport_priv *priv = netdev_priv(dev); 1677 unsigned int i; 1678 int ret; 1679 1680 bcm_sysport_netif_stop(dev); 1681 1682 /* Disable UniMAC RX */ 1683 umac_enable_set(priv, CMD_RX_EN, 0); 1684 1685 ret = tdma_enable_set(priv, 0); 1686 if (ret) { 1687 netdev_err(dev, "timeout disabling RDMA\n"); 1688 return ret; 1689 } 1690 1691 /* Wait for a maximum packet size to be drained */ 1692 usleep_range(2000, 3000); 1693 1694 ret = rdma_enable_set(priv, 0); 1695 if (ret) { 1696 netdev_err(dev, "timeout disabling TDMA\n"); 1697 return ret; 1698 } 1699 1700 /* Disable UniMAC TX */ 1701 umac_enable_set(priv, CMD_TX_EN, 0); 1702 1703 /* Free RX/TX rings SW structures */ 1704 for (i = 0; i < dev->num_tx_queues; i++) 1705 bcm_sysport_fini_tx_ring(priv, i); 1706 bcm_sysport_fini_rx_ring(priv); 1707 1708 free_irq(priv->irq0, dev); 1709 free_irq(priv->irq1, dev); 1710 1711 /* Disconnect from PHY */ 1712 phy_disconnect(priv->phydev); 1713 1714 return 0; 1715 } 1716 1717 static struct ethtool_ops bcm_sysport_ethtool_ops = { 1718 .get_settings = bcm_sysport_get_settings, 1719 .set_settings = bcm_sysport_set_settings, 1720 .get_drvinfo = bcm_sysport_get_drvinfo, 1721 .get_msglevel = bcm_sysport_get_msglvl, 1722 .set_msglevel = bcm_sysport_set_msglvl, 1723 .get_link = ethtool_op_get_link, 1724 .get_strings = bcm_sysport_get_strings, 1725 .get_ethtool_stats = bcm_sysport_get_stats, 1726 .get_sset_count = bcm_sysport_get_sset_count, 1727 .get_wol = bcm_sysport_get_wol, 1728 .set_wol = bcm_sysport_set_wol, 1729 .get_coalesce = bcm_sysport_get_coalesce, 1730 .set_coalesce = bcm_sysport_set_coalesce, 1731 }; 1732 1733 static const struct net_device_ops bcm_sysport_netdev_ops = { 1734 .ndo_start_xmit = bcm_sysport_xmit, 1735 .ndo_tx_timeout = bcm_sysport_tx_timeout, 1736 .ndo_open = bcm_sysport_open, 1737 .ndo_stop = bcm_sysport_stop, 1738 .ndo_set_features = bcm_sysport_set_features, 1739 .ndo_set_rx_mode = bcm_sysport_set_rx_mode, 1740 .ndo_set_mac_address = bcm_sysport_change_mac, 1741 #ifdef CONFIG_NET_POLL_CONTROLLER 1742 .ndo_poll_controller = bcm_sysport_poll_controller, 1743 #endif 1744 }; 1745 1746 #define REV_FMT "v%2x.%02x" 1747 1748 static int bcm_sysport_probe(struct platform_device *pdev) 1749 { 1750 struct bcm_sysport_priv *priv; 1751 struct device_node *dn; 1752 struct net_device *dev; 1753 const void *macaddr; 1754 struct resource *r; 1755 u32 txq, rxq; 1756 int ret; 1757 1758 dn = pdev->dev.of_node; 1759 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1760 1761 /* Read the Transmit/Receive Queue properties */ 1762 if (of_property_read_u32(dn, "systemport,num-txq", &txq)) 1763 txq = TDMA_NUM_RINGS; 1764 if (of_property_read_u32(dn, "systemport,num-rxq", &rxq)) 1765 rxq = 1; 1766 1767 dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq); 1768 if (!dev) 1769 return -ENOMEM; 1770 1771 /* Initialize private members */ 1772 priv = netdev_priv(dev); 1773 1774 priv->irq0 = platform_get_irq(pdev, 0); 1775 priv->irq1 = platform_get_irq(pdev, 1); 1776 priv->wol_irq = platform_get_irq(pdev, 2); 1777 if (priv->irq0 <= 0 || priv->irq1 <= 0) { 1778 dev_err(&pdev->dev, "invalid interrupts\n"); 1779 ret = -EINVAL; 1780 goto err; 1781 } 1782 1783 priv->base = devm_ioremap_resource(&pdev->dev, r); 1784 if (IS_ERR(priv->base)) { 1785 ret = PTR_ERR(priv->base); 1786 goto err; 1787 } 1788 1789 priv->netdev = dev; 1790 priv->pdev = pdev; 1791 1792 priv->phy_interface = of_get_phy_mode(dn); 1793 /* Default to GMII interface mode */ 1794 if (priv->phy_interface < 0) 1795 priv->phy_interface = PHY_INTERFACE_MODE_GMII; 1796 1797 /* In the case of a fixed PHY, the DT node associated 1798 * to the PHY is the Ethernet MAC DT node. 1799 */ 1800 if (of_phy_is_fixed_link(dn)) { 1801 ret = of_phy_register_fixed_link(dn); 1802 if (ret) { 1803 dev_err(&pdev->dev, "failed to register fixed PHY\n"); 1804 goto err; 1805 } 1806 1807 priv->phy_dn = dn; 1808 } 1809 1810 /* Initialize netdevice members */ 1811 macaddr = of_get_mac_address(dn); 1812 if (!macaddr || !is_valid_ether_addr(macaddr)) { 1813 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 1814 eth_hw_addr_random(dev); 1815 } else { 1816 ether_addr_copy(dev->dev_addr, macaddr); 1817 } 1818 1819 SET_NETDEV_DEV(dev, &pdev->dev); 1820 dev_set_drvdata(&pdev->dev, dev); 1821 dev->ethtool_ops = &bcm_sysport_ethtool_ops; 1822 dev->netdev_ops = &bcm_sysport_netdev_ops; 1823 netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64); 1824 1825 /* HW supported features, none enabled by default */ 1826 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA | 1827 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1828 1829 /* Request the WOL interrupt and advertise suspend if available */ 1830 priv->wol_irq_disabled = 1; 1831 ret = devm_request_irq(&pdev->dev, priv->wol_irq, 1832 bcm_sysport_wol_isr, 0, dev->name, priv); 1833 if (!ret) 1834 device_set_wakeup_capable(&pdev->dev, 1); 1835 1836 /* Set the needed headroom once and for all */ 1837 BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8); 1838 dev->needed_headroom += sizeof(struct bcm_tsb); 1839 1840 /* libphy will adjust the link state accordingly */ 1841 netif_carrier_off(dev); 1842 1843 ret = register_netdev(dev); 1844 if (ret) { 1845 dev_err(&pdev->dev, "failed to register net_device\n"); 1846 goto err; 1847 } 1848 1849 priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK; 1850 dev_info(&pdev->dev, 1851 "Broadcom SYSTEMPORT" REV_FMT 1852 " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n", 1853 (priv->rev >> 8) & 0xff, priv->rev & 0xff, 1854 priv->base, priv->irq0, priv->irq1, txq, rxq); 1855 1856 return 0; 1857 err: 1858 free_netdev(dev); 1859 return ret; 1860 } 1861 1862 static int bcm_sysport_remove(struct platform_device *pdev) 1863 { 1864 struct net_device *dev = dev_get_drvdata(&pdev->dev); 1865 1866 /* Not much to do, ndo_close has been called 1867 * and we use managed allocations 1868 */ 1869 unregister_netdev(dev); 1870 free_netdev(dev); 1871 dev_set_drvdata(&pdev->dev, NULL); 1872 1873 return 0; 1874 } 1875 1876 #ifdef CONFIG_PM_SLEEP 1877 static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv) 1878 { 1879 struct net_device *ndev = priv->netdev; 1880 unsigned int timeout = 1000; 1881 u32 reg; 1882 1883 /* Password has already been programmed */ 1884 reg = umac_readl(priv, UMAC_MPD_CTRL); 1885 reg |= MPD_EN; 1886 reg &= ~PSW_EN; 1887 if (priv->wolopts & WAKE_MAGICSECURE) 1888 reg |= PSW_EN; 1889 umac_writel(priv, reg, UMAC_MPD_CTRL); 1890 1891 /* Make sure RBUF entered WoL mode as result */ 1892 do { 1893 reg = rbuf_readl(priv, RBUF_STATUS); 1894 if (reg & RBUF_WOL_MODE) 1895 break; 1896 1897 udelay(10); 1898 } while (timeout-- > 0); 1899 1900 /* Do not leave the UniMAC RBUF matching only MPD packets */ 1901 if (!timeout) { 1902 reg = umac_readl(priv, UMAC_MPD_CTRL); 1903 reg &= ~MPD_EN; 1904 umac_writel(priv, reg, UMAC_MPD_CTRL); 1905 netif_err(priv, wol, ndev, "failed to enter WOL mode\n"); 1906 return -ETIMEDOUT; 1907 } 1908 1909 /* UniMAC receive needs to be turned on */ 1910 umac_enable_set(priv, CMD_RX_EN, 1); 1911 1912 /* Enable the interrupt wake-up source */ 1913 intrl2_0_mask_clear(priv, INTRL2_0_MPD); 1914 1915 netif_dbg(priv, wol, ndev, "entered WOL mode\n"); 1916 1917 return 0; 1918 } 1919 1920 static int bcm_sysport_suspend(struct device *d) 1921 { 1922 struct net_device *dev = dev_get_drvdata(d); 1923 struct bcm_sysport_priv *priv = netdev_priv(dev); 1924 unsigned int i; 1925 int ret = 0; 1926 u32 reg; 1927 1928 if (!netif_running(dev)) 1929 return 0; 1930 1931 bcm_sysport_netif_stop(dev); 1932 1933 phy_suspend(priv->phydev); 1934 1935 netif_device_detach(dev); 1936 1937 /* Disable UniMAC RX */ 1938 umac_enable_set(priv, CMD_RX_EN, 0); 1939 1940 ret = rdma_enable_set(priv, 0); 1941 if (ret) { 1942 netdev_err(dev, "RDMA timeout!\n"); 1943 return ret; 1944 } 1945 1946 /* Disable RXCHK if enabled */ 1947 if (priv->rx_chk_en) { 1948 reg = rxchk_readl(priv, RXCHK_CONTROL); 1949 reg &= ~RXCHK_EN; 1950 rxchk_writel(priv, reg, RXCHK_CONTROL); 1951 } 1952 1953 /* Flush RX pipe */ 1954 if (!priv->wolopts) 1955 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); 1956 1957 ret = tdma_enable_set(priv, 0); 1958 if (ret) { 1959 netdev_err(dev, "TDMA timeout!\n"); 1960 return ret; 1961 } 1962 1963 /* Wait for a packet boundary */ 1964 usleep_range(2000, 3000); 1965 1966 umac_enable_set(priv, CMD_TX_EN, 0); 1967 1968 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); 1969 1970 /* Free RX/TX rings SW structures */ 1971 for (i = 0; i < dev->num_tx_queues; i++) 1972 bcm_sysport_fini_tx_ring(priv, i); 1973 bcm_sysport_fini_rx_ring(priv); 1974 1975 /* Get prepared for Wake-on-LAN */ 1976 if (device_may_wakeup(d) && priv->wolopts) 1977 ret = bcm_sysport_suspend_to_wol(priv); 1978 1979 return ret; 1980 } 1981 1982 static int bcm_sysport_resume(struct device *d) 1983 { 1984 struct net_device *dev = dev_get_drvdata(d); 1985 struct bcm_sysport_priv *priv = netdev_priv(dev); 1986 unsigned int i; 1987 u32 reg; 1988 int ret; 1989 1990 if (!netif_running(dev)) 1991 return 0; 1992 1993 umac_reset(priv); 1994 1995 /* We may have been suspended and never received a WOL event that 1996 * would turn off MPD detection, take care of that now 1997 */ 1998 bcm_sysport_resume_from_wol(priv); 1999 2000 /* Initialize both hardware and software ring */ 2001 for (i = 0; i < dev->num_tx_queues; i++) { 2002 ret = bcm_sysport_init_tx_ring(priv, i); 2003 if (ret) { 2004 netdev_err(dev, "failed to initialize TX ring %d\n", 2005 i); 2006 goto out_free_tx_rings; 2007 } 2008 } 2009 2010 /* Initialize linked-list */ 2011 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); 2012 2013 /* Initialize RX ring */ 2014 ret = bcm_sysport_init_rx_ring(priv); 2015 if (ret) { 2016 netdev_err(dev, "failed to initialize RX ring\n"); 2017 goto out_free_rx_ring; 2018 } 2019 2020 netif_device_attach(dev); 2021 2022 /* RX pipe enable */ 2023 topctrl_writel(priv, 0, RX_FLUSH_CNTL); 2024 2025 ret = rdma_enable_set(priv, 1); 2026 if (ret) { 2027 netdev_err(dev, "failed to enable RDMA\n"); 2028 goto out_free_rx_ring; 2029 } 2030 2031 /* Enable rxhck */ 2032 if (priv->rx_chk_en) { 2033 reg = rxchk_readl(priv, RXCHK_CONTROL); 2034 reg |= RXCHK_EN; 2035 rxchk_writel(priv, reg, RXCHK_CONTROL); 2036 } 2037 2038 rbuf_init(priv); 2039 2040 /* Set maximum frame length */ 2041 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2042 2043 /* Set MAC address */ 2044 umac_set_hw_addr(priv, dev->dev_addr); 2045 2046 umac_enable_set(priv, CMD_RX_EN, 1); 2047 2048 /* TX pipe enable */ 2049 topctrl_writel(priv, 0, TX_FLUSH_CNTL); 2050 2051 umac_enable_set(priv, CMD_TX_EN, 1); 2052 2053 ret = tdma_enable_set(priv, 1); 2054 if (ret) { 2055 netdev_err(dev, "TDMA timeout!\n"); 2056 goto out_free_rx_ring; 2057 } 2058 2059 phy_resume(priv->phydev); 2060 2061 bcm_sysport_netif_start(dev); 2062 2063 return 0; 2064 2065 out_free_rx_ring: 2066 bcm_sysport_fini_rx_ring(priv); 2067 out_free_tx_rings: 2068 for (i = 0; i < dev->num_tx_queues; i++) 2069 bcm_sysport_fini_tx_ring(priv, i); 2070 return ret; 2071 } 2072 #endif 2073 2074 static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops, 2075 bcm_sysport_suspend, bcm_sysport_resume); 2076 2077 static const struct of_device_id bcm_sysport_of_match[] = { 2078 { .compatible = "brcm,systemport-v1.00" }, 2079 { .compatible = "brcm,systemport" }, 2080 { /* sentinel */ } 2081 }; 2082 MODULE_DEVICE_TABLE(of, bcm_sysport_of_match); 2083 2084 static struct platform_driver bcm_sysport_driver = { 2085 .probe = bcm_sysport_probe, 2086 .remove = bcm_sysport_remove, 2087 .driver = { 2088 .name = "brcm-systemport", 2089 .of_match_table = bcm_sysport_of_match, 2090 .pm = &bcm_sysport_pm_ops, 2091 }, 2092 }; 2093 module_platform_driver(bcm_sysport_driver); 2094 2095 MODULE_AUTHOR("Broadcom Corporation"); 2096 MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver"); 2097 MODULE_ALIAS("platform:brcm-systemport"); 2098 MODULE_LICENSE("GPL"); 2099