1 #ifndef BCM63XX_ENET_H_ 2 #define BCM63XX_ENET_H_ 3 4 #include <linux/types.h> 5 #include <linux/mii.h> 6 #include <linux/mutex.h> 7 #include <linux/phy.h> 8 #include <linux/platform_device.h> 9 10 #include <bcm63xx_regs.h> 11 #include <bcm63xx_io.h> 12 #include <bcm63xx_iudma.h> 13 14 /* default number of descriptor */ 15 #define BCMENET_DEF_RX_DESC 64 16 #define BCMENET_DEF_TX_DESC 32 17 18 /* maximum burst len for dma (4 bytes unit) */ 19 #define BCMENET_DMA_MAXBURST 16 20 #define BCMENETSW_DMA_MAXBURST 8 21 22 /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value 23 * must be low enough so that a DMA transfer of above burst length can 24 * not overflow the fifo */ 25 #define BCMENET_TX_FIFO_TRESH 32 26 27 /* 28 * hardware maximum rx/tx packet size including FCS, max mtu is 29 * actually 2047, but if we set max rx size register to 2047 we won't 30 * get overflow information if packet size is 2048 or above 31 */ 32 #define BCMENET_MAX_MTU 2046 33 34 /* 35 * MIB Counters register definitions 36 */ 37 #define ETH_MIB_TX_GD_OCTETS 0 38 #define ETH_MIB_TX_GD_PKTS 1 39 #define ETH_MIB_TX_ALL_OCTETS 2 40 #define ETH_MIB_TX_ALL_PKTS 3 41 #define ETH_MIB_TX_BRDCAST 4 42 #define ETH_MIB_TX_MULT 5 43 #define ETH_MIB_TX_64 6 44 #define ETH_MIB_TX_65_127 7 45 #define ETH_MIB_TX_128_255 8 46 #define ETH_MIB_TX_256_511 9 47 #define ETH_MIB_TX_512_1023 10 48 #define ETH_MIB_TX_1024_MAX 11 49 #define ETH_MIB_TX_JAB 12 50 #define ETH_MIB_TX_OVR 13 51 #define ETH_MIB_TX_FRAG 14 52 #define ETH_MIB_TX_UNDERRUN 15 53 #define ETH_MIB_TX_COL 16 54 #define ETH_MIB_TX_1_COL 17 55 #define ETH_MIB_TX_M_COL 18 56 #define ETH_MIB_TX_EX_COL 19 57 #define ETH_MIB_TX_LATE 20 58 #define ETH_MIB_TX_DEF 21 59 #define ETH_MIB_TX_CRS 22 60 #define ETH_MIB_TX_PAUSE 23 61 62 #define ETH_MIB_RX_GD_OCTETS 32 63 #define ETH_MIB_RX_GD_PKTS 33 64 #define ETH_MIB_RX_ALL_OCTETS 34 65 #define ETH_MIB_RX_ALL_PKTS 35 66 #define ETH_MIB_RX_BRDCAST 36 67 #define ETH_MIB_RX_MULT 37 68 #define ETH_MIB_RX_64 38 69 #define ETH_MIB_RX_65_127 39 70 #define ETH_MIB_RX_128_255 40 71 #define ETH_MIB_RX_256_511 41 72 #define ETH_MIB_RX_512_1023 42 73 #define ETH_MIB_RX_1024_MAX 43 74 #define ETH_MIB_RX_JAB 44 75 #define ETH_MIB_RX_OVR 45 76 #define ETH_MIB_RX_FRAG 46 77 #define ETH_MIB_RX_DROP 47 78 #define ETH_MIB_RX_CRC_ALIGN 48 79 #define ETH_MIB_RX_UND 49 80 #define ETH_MIB_RX_CRC 50 81 #define ETH_MIB_RX_ALIGN 51 82 #define ETH_MIB_RX_SYM 52 83 #define ETH_MIB_RX_PAUSE 53 84 #define ETH_MIB_RX_CNTRL 54 85 86 87 /* 88 * SW MIB Counters register definitions 89 */ 90 #define ETHSW_MIB_TX_ALL_OCT 0 91 #define ETHSW_MIB_TX_DROP_PKTS 2 92 #define ETHSW_MIB_TX_QOS_PKTS 3 93 #define ETHSW_MIB_TX_BRDCAST 4 94 #define ETHSW_MIB_TX_MULT 5 95 #define ETHSW_MIB_TX_UNI 6 96 #define ETHSW_MIB_TX_COL 7 97 #define ETHSW_MIB_TX_1_COL 8 98 #define ETHSW_MIB_TX_M_COL 9 99 #define ETHSW_MIB_TX_DEF 10 100 #define ETHSW_MIB_TX_LATE 11 101 #define ETHSW_MIB_TX_EX_COL 12 102 #define ETHSW_MIB_TX_PAUSE 14 103 #define ETHSW_MIB_TX_QOS_OCT 15 104 105 #define ETHSW_MIB_RX_ALL_OCT 17 106 #define ETHSW_MIB_RX_UND 19 107 #define ETHSW_MIB_RX_PAUSE 20 108 #define ETHSW_MIB_RX_64 21 109 #define ETHSW_MIB_RX_65_127 22 110 #define ETHSW_MIB_RX_128_255 23 111 #define ETHSW_MIB_RX_256_511 24 112 #define ETHSW_MIB_RX_512_1023 25 113 #define ETHSW_MIB_RX_1024_1522 26 114 #define ETHSW_MIB_RX_OVR 27 115 #define ETHSW_MIB_RX_JAB 28 116 #define ETHSW_MIB_RX_ALIGN 29 117 #define ETHSW_MIB_RX_CRC 30 118 #define ETHSW_MIB_RX_GD_OCT 31 119 #define ETHSW_MIB_RX_DROP 33 120 #define ETHSW_MIB_RX_UNI 34 121 #define ETHSW_MIB_RX_MULT 35 122 #define ETHSW_MIB_RX_BRDCAST 36 123 #define ETHSW_MIB_RX_SA_CHANGE 37 124 #define ETHSW_MIB_RX_FRAG 38 125 #define ETHSW_MIB_RX_OVR_DISC 39 126 #define ETHSW_MIB_RX_SYM 40 127 #define ETHSW_MIB_RX_QOS_PKTS 41 128 #define ETHSW_MIB_RX_QOS_OCT 42 129 #define ETHSW_MIB_RX_1523_2047 44 130 #define ETHSW_MIB_RX_2048_4095 45 131 #define ETHSW_MIB_RX_4096_8191 46 132 #define ETHSW_MIB_RX_8192_9728 47 133 134 135 struct bcm_enet_mib_counters { 136 u64 tx_gd_octets; 137 u32 tx_gd_pkts; 138 u32 tx_all_octets; 139 u32 tx_all_pkts; 140 u32 tx_unicast; 141 u32 tx_brdcast; 142 u32 tx_mult; 143 u32 tx_64; 144 u32 tx_65_127; 145 u32 tx_128_255; 146 u32 tx_256_511; 147 u32 tx_512_1023; 148 u32 tx_1024_max; 149 u32 tx_1523_2047; 150 u32 tx_2048_4095; 151 u32 tx_4096_8191; 152 u32 tx_8192_9728; 153 u32 tx_jab; 154 u32 tx_drop; 155 u32 tx_ovr; 156 u32 tx_frag; 157 u32 tx_underrun; 158 u32 tx_col; 159 u32 tx_1_col; 160 u32 tx_m_col; 161 u32 tx_ex_col; 162 u32 tx_late; 163 u32 tx_def; 164 u32 tx_crs; 165 u32 tx_pause; 166 u64 rx_gd_octets; 167 u32 rx_gd_pkts; 168 u32 rx_all_octets; 169 u32 rx_all_pkts; 170 u32 rx_brdcast; 171 u32 rx_unicast; 172 u32 rx_mult; 173 u32 rx_64; 174 u32 rx_65_127; 175 u32 rx_128_255; 176 u32 rx_256_511; 177 u32 rx_512_1023; 178 u32 rx_1024_max; 179 u32 rx_jab; 180 u32 rx_ovr; 181 u32 rx_frag; 182 u32 rx_drop; 183 u32 rx_crc_align; 184 u32 rx_und; 185 u32 rx_crc; 186 u32 rx_align; 187 u32 rx_sym; 188 u32 rx_pause; 189 u32 rx_cntrl; 190 }; 191 192 193 struct bcm_enet_priv { 194 195 /* mac id (from platform device id) */ 196 int mac_id; 197 198 /* base remapped address of device */ 199 void __iomem *base; 200 201 /* mac irq, rx_dma irq, tx_dma irq */ 202 int irq; 203 int irq_rx; 204 int irq_tx; 205 206 /* hw view of rx & tx dma ring */ 207 dma_addr_t rx_desc_dma; 208 dma_addr_t tx_desc_dma; 209 210 /* allocated size (in bytes) for rx & tx dma ring */ 211 unsigned int rx_desc_alloc_size; 212 unsigned int tx_desc_alloc_size; 213 214 215 struct napi_struct napi; 216 217 /* dma channel id for rx */ 218 int rx_chan; 219 220 /* number of dma desc in rx ring */ 221 int rx_ring_size; 222 223 /* cpu view of rx dma ring */ 224 struct bcm_enet_desc *rx_desc_cpu; 225 226 /* current number of armed descriptor given to hardware for rx */ 227 int rx_desc_count; 228 229 /* next rx descriptor to fetch from hardware */ 230 int rx_curr_desc; 231 232 /* next dirty rx descriptor to refill */ 233 int rx_dirty_desc; 234 235 /* size of allocated rx skbs */ 236 unsigned int rx_skb_size; 237 238 /* list of skb given to hw for rx */ 239 struct sk_buff **rx_skb; 240 241 /* used when rx skb allocation failed, so we defer rx queue 242 * refill */ 243 struct timer_list rx_timeout; 244 245 /* lock rx_timeout against rx normal operation */ 246 spinlock_t rx_lock; 247 248 249 /* dma channel id for tx */ 250 int tx_chan; 251 252 /* number of dma desc in tx ring */ 253 int tx_ring_size; 254 255 /* maximum dma burst size */ 256 int dma_maxburst; 257 258 /* cpu view of rx dma ring */ 259 struct bcm_enet_desc *tx_desc_cpu; 260 261 /* number of available descriptor for tx */ 262 int tx_desc_count; 263 264 /* next tx descriptor avaiable */ 265 int tx_curr_desc; 266 267 /* next dirty tx descriptor to reclaim */ 268 int tx_dirty_desc; 269 270 /* list of skb given to hw for tx */ 271 struct sk_buff **tx_skb; 272 273 /* lock used by tx reclaim and xmit */ 274 spinlock_t tx_lock; 275 276 277 /* set if internal phy is ignored and external mii interface 278 * is selected */ 279 int use_external_mii; 280 281 /* set if a phy is connected, phy address must be known, 282 * probing is not possible */ 283 int has_phy; 284 int phy_id; 285 286 /* set if connected phy has an associated irq */ 287 int has_phy_interrupt; 288 int phy_interrupt; 289 290 /* used when a phy is connected (phylib used) */ 291 struct mii_bus *mii_bus; 292 int old_link; 293 int old_duplex; 294 int old_pause; 295 296 /* used when no phy is connected */ 297 int force_speed_100; 298 int force_duplex_full; 299 300 /* pause parameters */ 301 int pause_auto; 302 int pause_rx; 303 int pause_tx; 304 305 /* stats */ 306 struct bcm_enet_mib_counters mib; 307 308 /* after mib interrupt, mib registers update is done in this 309 * work queue */ 310 struct work_struct mib_update_task; 311 312 /* lock mib update between userspace request and workqueue */ 313 struct mutex mib_update_lock; 314 315 /* mac clock */ 316 struct clk *mac_clk; 317 318 /* phy clock if internal phy is used */ 319 struct clk *phy_clk; 320 321 /* network device reference */ 322 struct net_device *net_dev; 323 324 /* platform device reference */ 325 struct platform_device *pdev; 326 327 /* maximum hardware transmit/receive size */ 328 unsigned int hw_mtu; 329 330 bool enet_is_sw; 331 332 /* port mapping for switch devices */ 333 int num_ports; 334 struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT]; 335 int sw_port_link[ENETSW_MAX_PORT]; 336 337 /* used to poll switch port state */ 338 struct timer_list swphy_poll; 339 spinlock_t enetsw_mdio_lock; 340 341 /* dma channel enable mask */ 342 u32 dma_chan_en_mask; 343 344 /* dma channel interrupt mask */ 345 u32 dma_chan_int_mask; 346 347 /* DMA engine has internal SRAM */ 348 bool dma_has_sram; 349 350 /* dma channel width */ 351 unsigned int dma_chan_width; 352 353 /* dma descriptor shift value */ 354 unsigned int dma_desc_shift; 355 }; 356 357 358 #endif /* ! BCM63XX_ENET_H_ */ 359