1 /* 2 * Driver for BCM963xx builtin Ethernet mac 3 * 4 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/clk.h> 24 #include <linux/etherdevice.h> 25 #include <linux/slab.h> 26 #include <linux/delay.h> 27 #include <linux/ethtool.h> 28 #include <linux/crc32.h> 29 #include <linux/err.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/platform_device.h> 32 #include <linux/if_vlan.h> 33 34 #include <bcm63xx_dev_enet.h> 35 #include "bcm63xx_enet.h" 36 37 static char bcm_enet_driver_name[] = "bcm63xx_enet"; 38 static char bcm_enet_driver_version[] = "1.0"; 39 40 static int copybreak __read_mostly = 128; 41 module_param(copybreak, int, 0); 42 MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 43 44 /* io memory shared between all devices */ 45 static void __iomem *bcm_enet_shared_base; 46 47 /* 48 * io helpers to access mac registers 49 */ 50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off) 51 { 52 return bcm_readl(priv->base + off); 53 } 54 55 static inline void enet_writel(struct bcm_enet_priv *priv, 56 u32 val, u32 off) 57 { 58 bcm_writel(val, priv->base + off); 59 } 60 61 /* 62 * io helpers to access shared registers 63 */ 64 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off) 65 { 66 return bcm_readl(bcm_enet_shared_base + off); 67 } 68 69 static inline void enet_dma_writel(struct bcm_enet_priv *priv, 70 u32 val, u32 off) 71 { 72 bcm_writel(val, bcm_enet_shared_base + off); 73 } 74 75 /* 76 * write given data into mii register and wait for transfer to end 77 * with timeout (average measured transfer time is 25us) 78 */ 79 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data) 80 { 81 int limit; 82 83 /* make sure mii interrupt status is cleared */ 84 enet_writel(priv, ENET_IR_MII, ENET_IR_REG); 85 86 enet_writel(priv, data, ENET_MIIDATA_REG); 87 wmb(); 88 89 /* busy wait on mii interrupt bit, with timeout */ 90 limit = 1000; 91 do { 92 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII) 93 break; 94 udelay(1); 95 } while (limit-- > 0); 96 97 return (limit < 0) ? 1 : 0; 98 } 99 100 /* 101 * MII internal read callback 102 */ 103 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id, 104 int regnum) 105 { 106 u32 tmp, val; 107 108 tmp = regnum << ENET_MIIDATA_REG_SHIFT; 109 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT; 110 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT; 111 tmp |= ENET_MIIDATA_OP_READ_MASK; 112 113 if (do_mdio_op(priv, tmp)) 114 return -1; 115 116 val = enet_readl(priv, ENET_MIIDATA_REG); 117 val &= 0xffff; 118 return val; 119 } 120 121 /* 122 * MII internal write callback 123 */ 124 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id, 125 int regnum, u16 value) 126 { 127 u32 tmp; 128 129 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT; 130 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT; 131 tmp |= regnum << ENET_MIIDATA_REG_SHIFT; 132 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT; 133 tmp |= ENET_MIIDATA_OP_WRITE_MASK; 134 135 (void)do_mdio_op(priv, tmp); 136 return 0; 137 } 138 139 /* 140 * MII read callback from phylib 141 */ 142 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id, 143 int regnum) 144 { 145 return bcm_enet_mdio_read(bus->priv, mii_id, regnum); 146 } 147 148 /* 149 * MII write callback from phylib 150 */ 151 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id, 152 int regnum, u16 value) 153 { 154 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value); 155 } 156 157 /* 158 * MII read callback from mii core 159 */ 160 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id, 161 int regnum) 162 { 163 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum); 164 } 165 166 /* 167 * MII write callback from mii core 168 */ 169 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id, 170 int regnum, int value) 171 { 172 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value); 173 } 174 175 /* 176 * refill rx queue 177 */ 178 static int bcm_enet_refill_rx(struct net_device *dev) 179 { 180 struct bcm_enet_priv *priv; 181 182 priv = netdev_priv(dev); 183 184 while (priv->rx_desc_count < priv->rx_ring_size) { 185 struct bcm_enet_desc *desc; 186 struct sk_buff *skb; 187 dma_addr_t p; 188 int desc_idx; 189 u32 len_stat; 190 191 desc_idx = priv->rx_dirty_desc; 192 desc = &priv->rx_desc_cpu[desc_idx]; 193 194 if (!priv->rx_skb[desc_idx]) { 195 skb = netdev_alloc_skb(dev, priv->rx_skb_size); 196 if (!skb) 197 break; 198 priv->rx_skb[desc_idx] = skb; 199 200 p = dma_map_single(&priv->pdev->dev, skb->data, 201 priv->rx_skb_size, 202 DMA_FROM_DEVICE); 203 desc->address = p; 204 } 205 206 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT; 207 len_stat |= DMADESC_OWNER_MASK; 208 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) { 209 len_stat |= DMADESC_WRAP_MASK; 210 priv->rx_dirty_desc = 0; 211 } else { 212 priv->rx_dirty_desc++; 213 } 214 wmb(); 215 desc->len_stat = len_stat; 216 217 priv->rx_desc_count++; 218 219 /* tell dma engine we allocated one buffer */ 220 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan)); 221 } 222 223 /* If rx ring is still empty, set a timer to try allocating 224 * again at a later time. */ 225 if (priv->rx_desc_count == 0 && netif_running(dev)) { 226 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n"); 227 priv->rx_timeout.expires = jiffies + HZ; 228 add_timer(&priv->rx_timeout); 229 } 230 231 return 0; 232 } 233 234 /* 235 * timer callback to defer refill rx queue in case we're OOM 236 */ 237 static void bcm_enet_refill_rx_timer(unsigned long data) 238 { 239 struct net_device *dev; 240 struct bcm_enet_priv *priv; 241 242 dev = (struct net_device *)data; 243 priv = netdev_priv(dev); 244 245 spin_lock(&priv->rx_lock); 246 bcm_enet_refill_rx((struct net_device *)data); 247 spin_unlock(&priv->rx_lock); 248 } 249 250 /* 251 * extract packet from rx queue 252 */ 253 static int bcm_enet_receive_queue(struct net_device *dev, int budget) 254 { 255 struct bcm_enet_priv *priv; 256 struct device *kdev; 257 int processed; 258 259 priv = netdev_priv(dev); 260 kdev = &priv->pdev->dev; 261 processed = 0; 262 263 /* don't scan ring further than number of refilled 264 * descriptor */ 265 if (budget > priv->rx_desc_count) 266 budget = priv->rx_desc_count; 267 268 do { 269 struct bcm_enet_desc *desc; 270 struct sk_buff *skb; 271 int desc_idx; 272 u32 len_stat; 273 unsigned int len; 274 275 desc_idx = priv->rx_curr_desc; 276 desc = &priv->rx_desc_cpu[desc_idx]; 277 278 /* make sure we actually read the descriptor status at 279 * each loop */ 280 rmb(); 281 282 len_stat = desc->len_stat; 283 284 /* break if dma ownership belongs to hw */ 285 if (len_stat & DMADESC_OWNER_MASK) 286 break; 287 288 processed++; 289 priv->rx_curr_desc++; 290 if (priv->rx_curr_desc == priv->rx_ring_size) 291 priv->rx_curr_desc = 0; 292 priv->rx_desc_count--; 293 294 /* if the packet does not have start of packet _and_ 295 * end of packet flag set, then just recycle it */ 296 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) { 297 dev->stats.rx_dropped++; 298 continue; 299 } 300 301 /* recycle packet if it's marked as bad */ 302 if (unlikely(len_stat & DMADESC_ERR_MASK)) { 303 dev->stats.rx_errors++; 304 305 if (len_stat & DMADESC_OVSIZE_MASK) 306 dev->stats.rx_length_errors++; 307 if (len_stat & DMADESC_CRC_MASK) 308 dev->stats.rx_crc_errors++; 309 if (len_stat & DMADESC_UNDER_MASK) 310 dev->stats.rx_frame_errors++; 311 if (len_stat & DMADESC_OV_MASK) 312 dev->stats.rx_fifo_errors++; 313 continue; 314 } 315 316 /* valid packet */ 317 skb = priv->rx_skb[desc_idx]; 318 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT; 319 /* don't include FCS */ 320 len -= 4; 321 322 if (len < copybreak) { 323 struct sk_buff *nskb; 324 325 nskb = netdev_alloc_skb_ip_align(dev, len); 326 if (!nskb) { 327 /* forget packet, just rearm desc */ 328 dev->stats.rx_dropped++; 329 continue; 330 } 331 332 dma_sync_single_for_cpu(kdev, desc->address, 333 len, DMA_FROM_DEVICE); 334 memcpy(nskb->data, skb->data, len); 335 dma_sync_single_for_device(kdev, desc->address, 336 len, DMA_FROM_DEVICE); 337 skb = nskb; 338 } else { 339 dma_unmap_single(&priv->pdev->dev, desc->address, 340 priv->rx_skb_size, DMA_FROM_DEVICE); 341 priv->rx_skb[desc_idx] = NULL; 342 } 343 344 skb_put(skb, len); 345 skb->protocol = eth_type_trans(skb, dev); 346 dev->stats.rx_packets++; 347 dev->stats.rx_bytes += len; 348 netif_receive_skb(skb); 349 350 } while (--budget > 0); 351 352 if (processed || !priv->rx_desc_count) { 353 bcm_enet_refill_rx(dev); 354 355 /* kick rx dma */ 356 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK, 357 ENETDMA_CHANCFG_REG(priv->rx_chan)); 358 } 359 360 return processed; 361 } 362 363 364 /* 365 * try to or force reclaim of transmitted buffers 366 */ 367 static int bcm_enet_tx_reclaim(struct net_device *dev, int force) 368 { 369 struct bcm_enet_priv *priv; 370 int released; 371 372 priv = netdev_priv(dev); 373 released = 0; 374 375 while (priv->tx_desc_count < priv->tx_ring_size) { 376 struct bcm_enet_desc *desc; 377 struct sk_buff *skb; 378 379 /* We run in a bh and fight against start_xmit, which 380 * is called with bh disabled */ 381 spin_lock(&priv->tx_lock); 382 383 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc]; 384 385 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) { 386 spin_unlock(&priv->tx_lock); 387 break; 388 } 389 390 /* ensure other field of the descriptor were not read 391 * before we checked ownership */ 392 rmb(); 393 394 skb = priv->tx_skb[priv->tx_dirty_desc]; 395 priv->tx_skb[priv->tx_dirty_desc] = NULL; 396 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len, 397 DMA_TO_DEVICE); 398 399 priv->tx_dirty_desc++; 400 if (priv->tx_dirty_desc == priv->tx_ring_size) 401 priv->tx_dirty_desc = 0; 402 priv->tx_desc_count++; 403 404 spin_unlock(&priv->tx_lock); 405 406 if (desc->len_stat & DMADESC_UNDER_MASK) 407 dev->stats.tx_errors++; 408 409 dev_kfree_skb(skb); 410 released++; 411 } 412 413 if (netif_queue_stopped(dev) && released) 414 netif_wake_queue(dev); 415 416 return released; 417 } 418 419 /* 420 * poll func, called by network core 421 */ 422 static int bcm_enet_poll(struct napi_struct *napi, int budget) 423 { 424 struct bcm_enet_priv *priv; 425 struct net_device *dev; 426 int tx_work_done, rx_work_done; 427 428 priv = container_of(napi, struct bcm_enet_priv, napi); 429 dev = priv->net_dev; 430 431 /* ack interrupts */ 432 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, 433 ENETDMA_IR_REG(priv->rx_chan)); 434 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, 435 ENETDMA_IR_REG(priv->tx_chan)); 436 437 /* reclaim sent skb */ 438 tx_work_done = bcm_enet_tx_reclaim(dev, 0); 439 440 spin_lock(&priv->rx_lock); 441 rx_work_done = bcm_enet_receive_queue(dev, budget); 442 spin_unlock(&priv->rx_lock); 443 444 if (rx_work_done >= budget || tx_work_done > 0) { 445 /* rx/tx queue is not yet empty/clean */ 446 return rx_work_done; 447 } 448 449 /* no more packet in rx/tx queue, remove device from poll 450 * queue */ 451 napi_complete(napi); 452 453 /* restore rx/tx interrupt */ 454 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, 455 ENETDMA_IRMASK_REG(priv->rx_chan)); 456 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, 457 ENETDMA_IRMASK_REG(priv->tx_chan)); 458 459 return rx_work_done; 460 } 461 462 /* 463 * mac interrupt handler 464 */ 465 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id) 466 { 467 struct net_device *dev; 468 struct bcm_enet_priv *priv; 469 u32 stat; 470 471 dev = dev_id; 472 priv = netdev_priv(dev); 473 474 stat = enet_readl(priv, ENET_IR_REG); 475 if (!(stat & ENET_IR_MIB)) 476 return IRQ_NONE; 477 478 /* clear & mask interrupt */ 479 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG); 480 enet_writel(priv, 0, ENET_IRMASK_REG); 481 482 /* read mib registers in workqueue */ 483 schedule_work(&priv->mib_update_task); 484 485 return IRQ_HANDLED; 486 } 487 488 /* 489 * rx/tx dma interrupt handler 490 */ 491 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id) 492 { 493 struct net_device *dev; 494 struct bcm_enet_priv *priv; 495 496 dev = dev_id; 497 priv = netdev_priv(dev); 498 499 /* mask rx/tx interrupts */ 500 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan)); 501 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan)); 502 503 napi_schedule(&priv->napi); 504 505 return IRQ_HANDLED; 506 } 507 508 /* 509 * tx request callback 510 */ 511 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) 512 { 513 struct bcm_enet_priv *priv; 514 struct bcm_enet_desc *desc; 515 u32 len_stat; 516 int ret; 517 518 priv = netdev_priv(dev); 519 520 /* lock against tx reclaim */ 521 spin_lock(&priv->tx_lock); 522 523 /* make sure the tx hw queue is not full, should not happen 524 * since we stop queue before it's the case */ 525 if (unlikely(!priv->tx_desc_count)) { 526 netif_stop_queue(dev); 527 dev_err(&priv->pdev->dev, "xmit called with no tx desc " 528 "available?\n"); 529 ret = NETDEV_TX_BUSY; 530 goto out_unlock; 531 } 532 533 /* point to the next available desc */ 534 desc = &priv->tx_desc_cpu[priv->tx_curr_desc]; 535 priv->tx_skb[priv->tx_curr_desc] = skb; 536 537 /* fill descriptor */ 538 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len, 539 DMA_TO_DEVICE); 540 541 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK; 542 len_stat |= DMADESC_ESOP_MASK | 543 DMADESC_APPEND_CRC | 544 DMADESC_OWNER_MASK; 545 546 priv->tx_curr_desc++; 547 if (priv->tx_curr_desc == priv->tx_ring_size) { 548 priv->tx_curr_desc = 0; 549 len_stat |= DMADESC_WRAP_MASK; 550 } 551 priv->tx_desc_count--; 552 553 /* dma might be already polling, make sure we update desc 554 * fields in correct order */ 555 wmb(); 556 desc->len_stat = len_stat; 557 wmb(); 558 559 /* kick tx dma */ 560 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK, 561 ENETDMA_CHANCFG_REG(priv->tx_chan)); 562 563 /* stop queue if no more desc available */ 564 if (!priv->tx_desc_count) 565 netif_stop_queue(dev); 566 567 dev->stats.tx_bytes += skb->len; 568 dev->stats.tx_packets++; 569 ret = NETDEV_TX_OK; 570 571 out_unlock: 572 spin_unlock(&priv->tx_lock); 573 return ret; 574 } 575 576 /* 577 * Change the interface's mac address. 578 */ 579 static int bcm_enet_set_mac_address(struct net_device *dev, void *p) 580 { 581 struct bcm_enet_priv *priv; 582 struct sockaddr *addr = p; 583 u32 val; 584 585 priv = netdev_priv(dev); 586 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 587 588 /* use perfect match register 0 to store my mac address */ 589 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) | 590 (dev->dev_addr[4] << 8) | dev->dev_addr[5]; 591 enet_writel(priv, val, ENET_PML_REG(0)); 592 593 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]); 594 val |= ENET_PMH_DATAVALID_MASK; 595 enet_writel(priv, val, ENET_PMH_REG(0)); 596 597 return 0; 598 } 599 600 /* 601 * Change rx mode (promiscuous/allmulti) and update multicast list 602 */ 603 static void bcm_enet_set_multicast_list(struct net_device *dev) 604 { 605 struct bcm_enet_priv *priv; 606 struct netdev_hw_addr *ha; 607 u32 val; 608 int i; 609 610 priv = netdev_priv(dev); 611 612 val = enet_readl(priv, ENET_RXCFG_REG); 613 614 if (dev->flags & IFF_PROMISC) 615 val |= ENET_RXCFG_PROMISC_MASK; 616 else 617 val &= ~ENET_RXCFG_PROMISC_MASK; 618 619 /* only 3 perfect match registers left, first one is used for 620 * own mac address */ 621 if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3) 622 val |= ENET_RXCFG_ALLMCAST_MASK; 623 else 624 val &= ~ENET_RXCFG_ALLMCAST_MASK; 625 626 /* no need to set perfect match registers if we catch all 627 * multicast */ 628 if (val & ENET_RXCFG_ALLMCAST_MASK) { 629 enet_writel(priv, val, ENET_RXCFG_REG); 630 return; 631 } 632 633 i = 0; 634 netdev_for_each_mc_addr(ha, dev) { 635 u8 *dmi_addr; 636 u32 tmp; 637 638 if (i == 3) 639 break; 640 /* update perfect match registers */ 641 dmi_addr = ha->addr; 642 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) | 643 (dmi_addr[4] << 8) | dmi_addr[5]; 644 enet_writel(priv, tmp, ENET_PML_REG(i + 1)); 645 646 tmp = (dmi_addr[0] << 8 | dmi_addr[1]); 647 tmp |= ENET_PMH_DATAVALID_MASK; 648 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1)); 649 } 650 651 for (; i < 3; i++) { 652 enet_writel(priv, 0, ENET_PML_REG(i + 1)); 653 enet_writel(priv, 0, ENET_PMH_REG(i + 1)); 654 } 655 656 enet_writel(priv, val, ENET_RXCFG_REG); 657 } 658 659 /* 660 * set mac duplex parameters 661 */ 662 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex) 663 { 664 u32 val; 665 666 val = enet_readl(priv, ENET_TXCTL_REG); 667 if (fullduplex) 668 val |= ENET_TXCTL_FD_MASK; 669 else 670 val &= ~ENET_TXCTL_FD_MASK; 671 enet_writel(priv, val, ENET_TXCTL_REG); 672 } 673 674 /* 675 * set mac flow control parameters 676 */ 677 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en) 678 { 679 u32 val; 680 681 /* rx flow control (pause frame handling) */ 682 val = enet_readl(priv, ENET_RXCFG_REG); 683 if (rx_en) 684 val |= ENET_RXCFG_ENFLOW_MASK; 685 else 686 val &= ~ENET_RXCFG_ENFLOW_MASK; 687 enet_writel(priv, val, ENET_RXCFG_REG); 688 689 /* tx flow control (pause frame generation) */ 690 val = enet_dma_readl(priv, ENETDMA_CFG_REG); 691 if (tx_en) 692 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); 693 else 694 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); 695 enet_dma_writel(priv, val, ENETDMA_CFG_REG); 696 } 697 698 /* 699 * link changed callback (from phylib) 700 */ 701 static void bcm_enet_adjust_phy_link(struct net_device *dev) 702 { 703 struct bcm_enet_priv *priv; 704 struct phy_device *phydev; 705 int status_changed; 706 707 priv = netdev_priv(dev); 708 phydev = priv->phydev; 709 status_changed = 0; 710 711 if (priv->old_link != phydev->link) { 712 status_changed = 1; 713 priv->old_link = phydev->link; 714 } 715 716 /* reflect duplex change in mac configuration */ 717 if (phydev->link && phydev->duplex != priv->old_duplex) { 718 bcm_enet_set_duplex(priv, 719 (phydev->duplex == DUPLEX_FULL) ? 1 : 0); 720 status_changed = 1; 721 priv->old_duplex = phydev->duplex; 722 } 723 724 /* enable flow control if remote advertise it (trust phylib to 725 * check that duplex is full */ 726 if (phydev->link && phydev->pause != priv->old_pause) { 727 int rx_pause_en, tx_pause_en; 728 729 if (phydev->pause) { 730 /* pause was advertised by lpa and us */ 731 rx_pause_en = 1; 732 tx_pause_en = 1; 733 } else if (!priv->pause_auto) { 734 /* pause setting overrided by user */ 735 rx_pause_en = priv->pause_rx; 736 tx_pause_en = priv->pause_tx; 737 } else { 738 rx_pause_en = 0; 739 tx_pause_en = 0; 740 } 741 742 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en); 743 status_changed = 1; 744 priv->old_pause = phydev->pause; 745 } 746 747 if (status_changed) { 748 pr_info("%s: link %s", dev->name, phydev->link ? 749 "UP" : "DOWN"); 750 if (phydev->link) 751 pr_cont(" - %d/%s - flow control %s", phydev->speed, 752 DUPLEX_FULL == phydev->duplex ? "full" : "half", 753 phydev->pause == 1 ? "rx&tx" : "off"); 754 755 pr_cont("\n"); 756 } 757 } 758 759 /* 760 * link changed callback (if phylib is not used) 761 */ 762 static void bcm_enet_adjust_link(struct net_device *dev) 763 { 764 struct bcm_enet_priv *priv; 765 766 priv = netdev_priv(dev); 767 bcm_enet_set_duplex(priv, priv->force_duplex_full); 768 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx); 769 netif_carrier_on(dev); 770 771 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n", 772 dev->name, 773 priv->force_speed_100 ? 100 : 10, 774 priv->force_duplex_full ? "full" : "half", 775 priv->pause_rx ? "rx" : "off", 776 priv->pause_tx ? "tx" : "off"); 777 } 778 779 /* 780 * open callback, allocate dma rings & buffers and start rx operation 781 */ 782 static int bcm_enet_open(struct net_device *dev) 783 { 784 struct bcm_enet_priv *priv; 785 struct sockaddr addr; 786 struct device *kdev; 787 struct phy_device *phydev; 788 int i, ret; 789 unsigned int size; 790 char phy_id[MII_BUS_ID_SIZE + 3]; 791 void *p; 792 u32 val; 793 794 priv = netdev_priv(dev); 795 kdev = &priv->pdev->dev; 796 797 if (priv->has_phy) { 798 /* connect to PHY */ 799 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 800 priv->mii_bus->id, priv->phy_id); 801 802 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link, 803 PHY_INTERFACE_MODE_MII); 804 805 if (IS_ERR(phydev)) { 806 dev_err(kdev, "could not attach to PHY\n"); 807 return PTR_ERR(phydev); 808 } 809 810 /* mask with MAC supported features */ 811 phydev->supported &= (SUPPORTED_10baseT_Half | 812 SUPPORTED_10baseT_Full | 813 SUPPORTED_100baseT_Half | 814 SUPPORTED_100baseT_Full | 815 SUPPORTED_Autoneg | 816 SUPPORTED_Pause | 817 SUPPORTED_MII); 818 phydev->advertising = phydev->supported; 819 820 if (priv->pause_auto && priv->pause_rx && priv->pause_tx) 821 phydev->advertising |= SUPPORTED_Pause; 822 else 823 phydev->advertising &= ~SUPPORTED_Pause; 824 825 dev_info(kdev, "attached PHY at address %d [%s]\n", 826 phydev->addr, phydev->drv->name); 827 828 priv->old_link = 0; 829 priv->old_duplex = -1; 830 priv->old_pause = -1; 831 priv->phydev = phydev; 832 } 833 834 /* mask all interrupts and request them */ 835 enet_writel(priv, 0, ENET_IRMASK_REG); 836 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan)); 837 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan)); 838 839 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev); 840 if (ret) 841 goto out_phy_disconnect; 842 843 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, IRQF_DISABLED, 844 dev->name, dev); 845 if (ret) 846 goto out_freeirq; 847 848 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma, 849 IRQF_DISABLED, dev->name, dev); 850 if (ret) 851 goto out_freeirq_rx; 852 853 /* initialize perfect match registers */ 854 for (i = 0; i < 4; i++) { 855 enet_writel(priv, 0, ENET_PML_REG(i)); 856 enet_writel(priv, 0, ENET_PMH_REG(i)); 857 } 858 859 /* write device mac address */ 860 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN); 861 bcm_enet_set_mac_address(dev, &addr); 862 863 /* allocate rx dma ring */ 864 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc); 865 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, 866 GFP_KERNEL | __GFP_ZERO); 867 if (!p) { 868 ret = -ENOMEM; 869 goto out_freeirq_tx; 870 } 871 872 priv->rx_desc_alloc_size = size; 873 priv->rx_desc_cpu = p; 874 875 /* allocate tx dma ring */ 876 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc); 877 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, 878 GFP_KERNEL | __GFP_ZERO); 879 if (!p) { 880 ret = -ENOMEM; 881 goto out_free_rx_ring; 882 } 883 884 priv->tx_desc_alloc_size = size; 885 priv->tx_desc_cpu = p; 886 887 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *), 888 GFP_KERNEL); 889 if (!priv->tx_skb) { 890 ret = -ENOMEM; 891 goto out_free_tx_ring; 892 } 893 894 priv->tx_desc_count = priv->tx_ring_size; 895 priv->tx_dirty_desc = 0; 896 priv->tx_curr_desc = 0; 897 spin_lock_init(&priv->tx_lock); 898 899 /* init & fill rx ring with skbs */ 900 priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *), 901 GFP_KERNEL); 902 if (!priv->rx_skb) { 903 ret = -ENOMEM; 904 goto out_free_tx_skb; 905 } 906 907 priv->rx_desc_count = 0; 908 priv->rx_dirty_desc = 0; 909 priv->rx_curr_desc = 0; 910 911 /* initialize flow control buffer allocation */ 912 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, 913 ENETDMA_BUFALLOC_REG(priv->rx_chan)); 914 915 if (bcm_enet_refill_rx(dev)) { 916 dev_err(kdev, "cannot allocate rx skb queue\n"); 917 ret = -ENOMEM; 918 goto out; 919 } 920 921 /* write rx & tx ring addresses */ 922 enet_dma_writel(priv, priv->rx_desc_dma, 923 ENETDMA_RSTART_REG(priv->rx_chan)); 924 enet_dma_writel(priv, priv->tx_desc_dma, 925 ENETDMA_RSTART_REG(priv->tx_chan)); 926 927 /* clear remaining state ram for rx & tx channel */ 928 enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan)); 929 enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan)); 930 enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan)); 931 enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan)); 932 enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan)); 933 enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan)); 934 935 /* set max rx/tx length */ 936 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG); 937 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG); 938 939 /* set dma maximum burst len */ 940 enet_dma_writel(priv, BCMENET_DMA_MAXBURST, 941 ENETDMA_MAXBURST_REG(priv->rx_chan)); 942 enet_dma_writel(priv, BCMENET_DMA_MAXBURST, 943 ENETDMA_MAXBURST_REG(priv->tx_chan)); 944 945 /* set correct transmit fifo watermark */ 946 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG); 947 948 /* set flow control low/high threshold to 1/3 / 2/3 */ 949 val = priv->rx_ring_size / 3; 950 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan)); 951 val = (priv->rx_ring_size * 2) / 3; 952 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan)); 953 954 /* all set, enable mac and interrupts, start dma engine and 955 * kick rx dma channel */ 956 wmb(); 957 val = enet_readl(priv, ENET_CTL_REG); 958 val |= ENET_CTL_ENABLE_MASK; 959 enet_writel(priv, val, ENET_CTL_REG); 960 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG); 961 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK, 962 ENETDMA_CHANCFG_REG(priv->rx_chan)); 963 964 /* watch "mib counters about to overflow" interrupt */ 965 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG); 966 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG); 967 968 /* watch "packet transferred" interrupt in rx and tx */ 969 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, 970 ENETDMA_IR_REG(priv->rx_chan)); 971 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, 972 ENETDMA_IR_REG(priv->tx_chan)); 973 974 /* make sure we enable napi before rx interrupt */ 975 napi_enable(&priv->napi); 976 977 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, 978 ENETDMA_IRMASK_REG(priv->rx_chan)); 979 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, 980 ENETDMA_IRMASK_REG(priv->tx_chan)); 981 982 if (priv->has_phy) 983 phy_start(priv->phydev); 984 else 985 bcm_enet_adjust_link(dev); 986 987 netif_start_queue(dev); 988 return 0; 989 990 out: 991 for (i = 0; i < priv->rx_ring_size; i++) { 992 struct bcm_enet_desc *desc; 993 994 if (!priv->rx_skb[i]) 995 continue; 996 997 desc = &priv->rx_desc_cpu[i]; 998 dma_unmap_single(kdev, desc->address, priv->rx_skb_size, 999 DMA_FROM_DEVICE); 1000 kfree_skb(priv->rx_skb[i]); 1001 } 1002 kfree(priv->rx_skb); 1003 1004 out_free_tx_skb: 1005 kfree(priv->tx_skb); 1006 1007 out_free_tx_ring: 1008 dma_free_coherent(kdev, priv->tx_desc_alloc_size, 1009 priv->tx_desc_cpu, priv->tx_desc_dma); 1010 1011 out_free_rx_ring: 1012 dma_free_coherent(kdev, priv->rx_desc_alloc_size, 1013 priv->rx_desc_cpu, priv->rx_desc_dma); 1014 1015 out_freeirq_tx: 1016 free_irq(priv->irq_tx, dev); 1017 1018 out_freeirq_rx: 1019 free_irq(priv->irq_rx, dev); 1020 1021 out_freeirq: 1022 free_irq(dev->irq, dev); 1023 1024 out_phy_disconnect: 1025 phy_disconnect(priv->phydev); 1026 1027 return ret; 1028 } 1029 1030 /* 1031 * disable mac 1032 */ 1033 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv) 1034 { 1035 int limit; 1036 u32 val; 1037 1038 val = enet_readl(priv, ENET_CTL_REG); 1039 val |= ENET_CTL_DISABLE_MASK; 1040 enet_writel(priv, val, ENET_CTL_REG); 1041 1042 limit = 1000; 1043 do { 1044 u32 val; 1045 1046 val = enet_readl(priv, ENET_CTL_REG); 1047 if (!(val & ENET_CTL_DISABLE_MASK)) 1048 break; 1049 udelay(1); 1050 } while (limit--); 1051 } 1052 1053 /* 1054 * disable dma in given channel 1055 */ 1056 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan) 1057 { 1058 int limit; 1059 1060 enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan)); 1061 1062 limit = 1000; 1063 do { 1064 u32 val; 1065 1066 val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan)); 1067 if (!(val & ENETDMA_CHANCFG_EN_MASK)) 1068 break; 1069 udelay(1); 1070 } while (limit--); 1071 } 1072 1073 /* 1074 * stop callback 1075 */ 1076 static int bcm_enet_stop(struct net_device *dev) 1077 { 1078 struct bcm_enet_priv *priv; 1079 struct device *kdev; 1080 int i; 1081 1082 priv = netdev_priv(dev); 1083 kdev = &priv->pdev->dev; 1084 1085 netif_stop_queue(dev); 1086 napi_disable(&priv->napi); 1087 if (priv->has_phy) 1088 phy_stop(priv->phydev); 1089 del_timer_sync(&priv->rx_timeout); 1090 1091 /* mask all interrupts */ 1092 enet_writel(priv, 0, ENET_IRMASK_REG); 1093 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan)); 1094 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan)); 1095 1096 /* make sure no mib update is scheduled */ 1097 cancel_work_sync(&priv->mib_update_task); 1098 1099 /* disable dma & mac */ 1100 bcm_enet_disable_dma(priv, priv->tx_chan); 1101 bcm_enet_disable_dma(priv, priv->rx_chan); 1102 bcm_enet_disable_mac(priv); 1103 1104 /* force reclaim of all tx buffers */ 1105 bcm_enet_tx_reclaim(dev, 1); 1106 1107 /* free the rx skb ring */ 1108 for (i = 0; i < priv->rx_ring_size; i++) { 1109 struct bcm_enet_desc *desc; 1110 1111 if (!priv->rx_skb[i]) 1112 continue; 1113 1114 desc = &priv->rx_desc_cpu[i]; 1115 dma_unmap_single(kdev, desc->address, priv->rx_skb_size, 1116 DMA_FROM_DEVICE); 1117 kfree_skb(priv->rx_skb[i]); 1118 } 1119 1120 /* free remaining allocated memory */ 1121 kfree(priv->rx_skb); 1122 kfree(priv->tx_skb); 1123 dma_free_coherent(kdev, priv->rx_desc_alloc_size, 1124 priv->rx_desc_cpu, priv->rx_desc_dma); 1125 dma_free_coherent(kdev, priv->tx_desc_alloc_size, 1126 priv->tx_desc_cpu, priv->tx_desc_dma); 1127 free_irq(priv->irq_tx, dev); 1128 free_irq(priv->irq_rx, dev); 1129 free_irq(dev->irq, dev); 1130 1131 /* release phy */ 1132 if (priv->has_phy) { 1133 phy_disconnect(priv->phydev); 1134 priv->phydev = NULL; 1135 } 1136 1137 return 0; 1138 } 1139 1140 /* 1141 * ethtool callbacks 1142 */ 1143 struct bcm_enet_stats { 1144 char stat_string[ETH_GSTRING_LEN]; 1145 int sizeof_stat; 1146 int stat_offset; 1147 int mib_reg; 1148 }; 1149 1150 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \ 1151 offsetof(struct bcm_enet_priv, m) 1152 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \ 1153 offsetof(struct net_device_stats, m) 1154 1155 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = { 1156 { "rx_packets", DEV_STAT(rx_packets), -1 }, 1157 { "tx_packets", DEV_STAT(tx_packets), -1 }, 1158 { "rx_bytes", DEV_STAT(rx_bytes), -1 }, 1159 { "tx_bytes", DEV_STAT(tx_bytes), -1 }, 1160 { "rx_errors", DEV_STAT(rx_errors), -1 }, 1161 { "tx_errors", DEV_STAT(tx_errors), -1 }, 1162 { "rx_dropped", DEV_STAT(rx_dropped), -1 }, 1163 { "tx_dropped", DEV_STAT(tx_dropped), -1 }, 1164 1165 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS}, 1166 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS }, 1167 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST }, 1168 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT }, 1169 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 }, 1170 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 }, 1171 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 }, 1172 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 }, 1173 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 }, 1174 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX }, 1175 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB }, 1176 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR }, 1177 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG }, 1178 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP }, 1179 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN }, 1180 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND }, 1181 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC }, 1182 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN }, 1183 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM }, 1184 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE }, 1185 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL }, 1186 1187 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS }, 1188 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS }, 1189 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST }, 1190 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT }, 1191 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 }, 1192 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 }, 1193 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 }, 1194 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 }, 1195 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023}, 1196 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX }, 1197 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB }, 1198 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR }, 1199 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG }, 1200 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN }, 1201 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL }, 1202 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL }, 1203 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL }, 1204 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL }, 1205 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE }, 1206 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF }, 1207 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS }, 1208 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE }, 1209 1210 }; 1211 1212 #define BCM_ENET_STATS_LEN \ 1213 (sizeof(bcm_enet_gstrings_stats) / sizeof(struct bcm_enet_stats)) 1214 1215 static const u32 unused_mib_regs[] = { 1216 ETH_MIB_TX_ALL_OCTETS, 1217 ETH_MIB_TX_ALL_PKTS, 1218 ETH_MIB_RX_ALL_OCTETS, 1219 ETH_MIB_RX_ALL_PKTS, 1220 }; 1221 1222 1223 static void bcm_enet_get_drvinfo(struct net_device *netdev, 1224 struct ethtool_drvinfo *drvinfo) 1225 { 1226 strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver)); 1227 strlcpy(drvinfo->version, bcm_enet_driver_version, 1228 sizeof(drvinfo->version)); 1229 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); 1230 strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info)); 1231 drvinfo->n_stats = BCM_ENET_STATS_LEN; 1232 } 1233 1234 static int bcm_enet_get_sset_count(struct net_device *netdev, 1235 int string_set) 1236 { 1237 switch (string_set) { 1238 case ETH_SS_STATS: 1239 return BCM_ENET_STATS_LEN; 1240 default: 1241 return -EINVAL; 1242 } 1243 } 1244 1245 static void bcm_enet_get_strings(struct net_device *netdev, 1246 u32 stringset, u8 *data) 1247 { 1248 int i; 1249 1250 switch (stringset) { 1251 case ETH_SS_STATS: 1252 for (i = 0; i < BCM_ENET_STATS_LEN; i++) { 1253 memcpy(data + i * ETH_GSTRING_LEN, 1254 bcm_enet_gstrings_stats[i].stat_string, 1255 ETH_GSTRING_LEN); 1256 } 1257 break; 1258 } 1259 } 1260 1261 static void update_mib_counters(struct bcm_enet_priv *priv) 1262 { 1263 int i; 1264 1265 for (i = 0; i < BCM_ENET_STATS_LEN; i++) { 1266 const struct bcm_enet_stats *s; 1267 u32 val; 1268 char *p; 1269 1270 s = &bcm_enet_gstrings_stats[i]; 1271 if (s->mib_reg == -1) 1272 continue; 1273 1274 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg)); 1275 p = (char *)priv + s->stat_offset; 1276 1277 if (s->sizeof_stat == sizeof(u64)) 1278 *(u64 *)p += val; 1279 else 1280 *(u32 *)p += val; 1281 } 1282 1283 /* also empty unused mib counters to make sure mib counter 1284 * overflow interrupt is cleared */ 1285 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++) 1286 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i])); 1287 } 1288 1289 static void bcm_enet_update_mib_counters_defer(struct work_struct *t) 1290 { 1291 struct bcm_enet_priv *priv; 1292 1293 priv = container_of(t, struct bcm_enet_priv, mib_update_task); 1294 mutex_lock(&priv->mib_update_lock); 1295 update_mib_counters(priv); 1296 mutex_unlock(&priv->mib_update_lock); 1297 1298 /* reenable mib interrupt */ 1299 if (netif_running(priv->net_dev)) 1300 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG); 1301 } 1302 1303 static void bcm_enet_get_ethtool_stats(struct net_device *netdev, 1304 struct ethtool_stats *stats, 1305 u64 *data) 1306 { 1307 struct bcm_enet_priv *priv; 1308 int i; 1309 1310 priv = netdev_priv(netdev); 1311 1312 mutex_lock(&priv->mib_update_lock); 1313 update_mib_counters(priv); 1314 1315 for (i = 0; i < BCM_ENET_STATS_LEN; i++) { 1316 const struct bcm_enet_stats *s; 1317 char *p; 1318 1319 s = &bcm_enet_gstrings_stats[i]; 1320 if (s->mib_reg == -1) 1321 p = (char *)&netdev->stats; 1322 else 1323 p = (char *)priv; 1324 p += s->stat_offset; 1325 data[i] = (s->sizeof_stat == sizeof(u64)) ? 1326 *(u64 *)p : *(u32 *)p; 1327 } 1328 mutex_unlock(&priv->mib_update_lock); 1329 } 1330 1331 static int bcm_enet_get_settings(struct net_device *dev, 1332 struct ethtool_cmd *cmd) 1333 { 1334 struct bcm_enet_priv *priv; 1335 1336 priv = netdev_priv(dev); 1337 1338 cmd->maxrxpkt = 0; 1339 cmd->maxtxpkt = 0; 1340 1341 if (priv->has_phy) { 1342 if (!priv->phydev) 1343 return -ENODEV; 1344 return phy_ethtool_gset(priv->phydev, cmd); 1345 } else { 1346 cmd->autoneg = 0; 1347 ethtool_cmd_speed_set(cmd, ((priv->force_speed_100) 1348 ? SPEED_100 : SPEED_10)); 1349 cmd->duplex = (priv->force_duplex_full) ? 1350 DUPLEX_FULL : DUPLEX_HALF; 1351 cmd->supported = ADVERTISED_10baseT_Half | 1352 ADVERTISED_10baseT_Full | 1353 ADVERTISED_100baseT_Half | 1354 ADVERTISED_100baseT_Full; 1355 cmd->advertising = 0; 1356 cmd->port = PORT_MII; 1357 cmd->transceiver = XCVR_EXTERNAL; 1358 } 1359 return 0; 1360 } 1361 1362 static int bcm_enet_set_settings(struct net_device *dev, 1363 struct ethtool_cmd *cmd) 1364 { 1365 struct bcm_enet_priv *priv; 1366 1367 priv = netdev_priv(dev); 1368 if (priv->has_phy) { 1369 if (!priv->phydev) 1370 return -ENODEV; 1371 return phy_ethtool_sset(priv->phydev, cmd); 1372 } else { 1373 1374 if (cmd->autoneg || 1375 (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) || 1376 cmd->port != PORT_MII) 1377 return -EINVAL; 1378 1379 priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0; 1380 priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0; 1381 1382 if (netif_running(dev)) 1383 bcm_enet_adjust_link(dev); 1384 return 0; 1385 } 1386 } 1387 1388 static void bcm_enet_get_ringparam(struct net_device *dev, 1389 struct ethtool_ringparam *ering) 1390 { 1391 struct bcm_enet_priv *priv; 1392 1393 priv = netdev_priv(dev); 1394 1395 /* rx/tx ring is actually only limited by memory */ 1396 ering->rx_max_pending = 8192; 1397 ering->tx_max_pending = 8192; 1398 ering->rx_pending = priv->rx_ring_size; 1399 ering->tx_pending = priv->tx_ring_size; 1400 } 1401 1402 static int bcm_enet_set_ringparam(struct net_device *dev, 1403 struct ethtool_ringparam *ering) 1404 { 1405 struct bcm_enet_priv *priv; 1406 int was_running; 1407 1408 priv = netdev_priv(dev); 1409 1410 was_running = 0; 1411 if (netif_running(dev)) { 1412 bcm_enet_stop(dev); 1413 was_running = 1; 1414 } 1415 1416 priv->rx_ring_size = ering->rx_pending; 1417 priv->tx_ring_size = ering->tx_pending; 1418 1419 if (was_running) { 1420 int err; 1421 1422 err = bcm_enet_open(dev); 1423 if (err) 1424 dev_close(dev); 1425 else 1426 bcm_enet_set_multicast_list(dev); 1427 } 1428 return 0; 1429 } 1430 1431 static void bcm_enet_get_pauseparam(struct net_device *dev, 1432 struct ethtool_pauseparam *ecmd) 1433 { 1434 struct bcm_enet_priv *priv; 1435 1436 priv = netdev_priv(dev); 1437 ecmd->autoneg = priv->pause_auto; 1438 ecmd->rx_pause = priv->pause_rx; 1439 ecmd->tx_pause = priv->pause_tx; 1440 } 1441 1442 static int bcm_enet_set_pauseparam(struct net_device *dev, 1443 struct ethtool_pauseparam *ecmd) 1444 { 1445 struct bcm_enet_priv *priv; 1446 1447 priv = netdev_priv(dev); 1448 1449 if (priv->has_phy) { 1450 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) { 1451 /* asymetric pause mode not supported, 1452 * actually possible but integrated PHY has RO 1453 * asym_pause bit */ 1454 return -EINVAL; 1455 } 1456 } else { 1457 /* no pause autoneg on direct mii connection */ 1458 if (ecmd->autoneg) 1459 return -EINVAL; 1460 } 1461 1462 priv->pause_auto = ecmd->autoneg; 1463 priv->pause_rx = ecmd->rx_pause; 1464 priv->pause_tx = ecmd->tx_pause; 1465 1466 return 0; 1467 } 1468 1469 static const struct ethtool_ops bcm_enet_ethtool_ops = { 1470 .get_strings = bcm_enet_get_strings, 1471 .get_sset_count = bcm_enet_get_sset_count, 1472 .get_ethtool_stats = bcm_enet_get_ethtool_stats, 1473 .get_settings = bcm_enet_get_settings, 1474 .set_settings = bcm_enet_set_settings, 1475 .get_drvinfo = bcm_enet_get_drvinfo, 1476 .get_link = ethtool_op_get_link, 1477 .get_ringparam = bcm_enet_get_ringparam, 1478 .set_ringparam = bcm_enet_set_ringparam, 1479 .get_pauseparam = bcm_enet_get_pauseparam, 1480 .set_pauseparam = bcm_enet_set_pauseparam, 1481 }; 1482 1483 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1484 { 1485 struct bcm_enet_priv *priv; 1486 1487 priv = netdev_priv(dev); 1488 if (priv->has_phy) { 1489 if (!priv->phydev) 1490 return -ENODEV; 1491 return phy_mii_ioctl(priv->phydev, rq, cmd); 1492 } else { 1493 struct mii_if_info mii; 1494 1495 mii.dev = dev; 1496 mii.mdio_read = bcm_enet_mdio_read_mii; 1497 mii.mdio_write = bcm_enet_mdio_write_mii; 1498 mii.phy_id = 0; 1499 mii.phy_id_mask = 0x3f; 1500 mii.reg_num_mask = 0x1f; 1501 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL); 1502 } 1503 } 1504 1505 /* 1506 * calculate actual hardware mtu 1507 */ 1508 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu) 1509 { 1510 int actual_mtu; 1511 1512 actual_mtu = mtu; 1513 1514 /* add ethernet header + vlan tag size */ 1515 actual_mtu += VLAN_ETH_HLEN; 1516 1517 if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU) 1518 return -EINVAL; 1519 1520 /* 1521 * setup maximum size before we get overflow mark in 1522 * descriptor, note that this will not prevent reception of 1523 * big frames, they will be split into multiple buffers 1524 * anyway 1525 */ 1526 priv->hw_mtu = actual_mtu; 1527 1528 /* 1529 * align rx buffer size to dma burst len, account FCS since 1530 * it's appended 1531 */ 1532 priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN, 1533 BCMENET_DMA_MAXBURST * 4); 1534 return 0; 1535 } 1536 1537 /* 1538 * adjust mtu, can't be called while device is running 1539 */ 1540 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu) 1541 { 1542 int ret; 1543 1544 if (netif_running(dev)) 1545 return -EBUSY; 1546 1547 ret = compute_hw_mtu(netdev_priv(dev), new_mtu); 1548 if (ret) 1549 return ret; 1550 dev->mtu = new_mtu; 1551 return 0; 1552 } 1553 1554 /* 1555 * preinit hardware to allow mii operation while device is down 1556 */ 1557 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv) 1558 { 1559 u32 val; 1560 int limit; 1561 1562 /* make sure mac is disabled */ 1563 bcm_enet_disable_mac(priv); 1564 1565 /* soft reset mac */ 1566 val = ENET_CTL_SRESET_MASK; 1567 enet_writel(priv, val, ENET_CTL_REG); 1568 wmb(); 1569 1570 limit = 1000; 1571 do { 1572 val = enet_readl(priv, ENET_CTL_REG); 1573 if (!(val & ENET_CTL_SRESET_MASK)) 1574 break; 1575 udelay(1); 1576 } while (limit--); 1577 1578 /* select correct mii interface */ 1579 val = enet_readl(priv, ENET_CTL_REG); 1580 if (priv->use_external_mii) 1581 val |= ENET_CTL_EPHYSEL_MASK; 1582 else 1583 val &= ~ENET_CTL_EPHYSEL_MASK; 1584 enet_writel(priv, val, ENET_CTL_REG); 1585 1586 /* turn on mdc clock */ 1587 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) | 1588 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG); 1589 1590 /* set mib counters to self-clear when read */ 1591 val = enet_readl(priv, ENET_MIBCTL_REG); 1592 val |= ENET_MIBCTL_RDCLEAR_MASK; 1593 enet_writel(priv, val, ENET_MIBCTL_REG); 1594 } 1595 1596 static const struct net_device_ops bcm_enet_ops = { 1597 .ndo_open = bcm_enet_open, 1598 .ndo_stop = bcm_enet_stop, 1599 .ndo_start_xmit = bcm_enet_start_xmit, 1600 .ndo_set_mac_address = bcm_enet_set_mac_address, 1601 .ndo_set_rx_mode = bcm_enet_set_multicast_list, 1602 .ndo_do_ioctl = bcm_enet_ioctl, 1603 .ndo_change_mtu = bcm_enet_change_mtu, 1604 #ifdef CONFIG_NET_POLL_CONTROLLER 1605 .ndo_poll_controller = bcm_enet_netpoll, 1606 #endif 1607 }; 1608 1609 /* 1610 * allocate netdevice, request register memory and register device. 1611 */ 1612 static int bcm_enet_probe(struct platform_device *pdev) 1613 { 1614 struct bcm_enet_priv *priv; 1615 struct net_device *dev; 1616 struct bcm63xx_enet_platform_data *pd; 1617 struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx; 1618 struct mii_bus *bus; 1619 const char *clk_name; 1620 int i, ret; 1621 1622 /* stop if shared driver failed, assume driver->probe will be 1623 * called in the same order we register devices (correct ?) */ 1624 if (!bcm_enet_shared_base) 1625 return -ENODEV; 1626 1627 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1628 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1629 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 1630 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2); 1631 if (!res_mem || !res_irq || !res_irq_rx || !res_irq_tx) 1632 return -ENODEV; 1633 1634 ret = 0; 1635 dev = alloc_etherdev(sizeof(*priv)); 1636 if (!dev) 1637 return -ENOMEM; 1638 priv = netdev_priv(dev); 1639 1640 ret = compute_hw_mtu(priv, dev->mtu); 1641 if (ret) 1642 goto out; 1643 1644 priv->base = devm_request_and_ioremap(&pdev->dev, res_mem); 1645 if (priv->base == NULL) { 1646 ret = -ENOMEM; 1647 goto out; 1648 } 1649 1650 dev->irq = priv->irq = res_irq->start; 1651 priv->irq_rx = res_irq_rx->start; 1652 priv->irq_tx = res_irq_tx->start; 1653 priv->mac_id = pdev->id; 1654 1655 /* get rx & tx dma channel id for this mac */ 1656 if (priv->mac_id == 0) { 1657 priv->rx_chan = 0; 1658 priv->tx_chan = 1; 1659 clk_name = "enet0"; 1660 } else { 1661 priv->rx_chan = 2; 1662 priv->tx_chan = 3; 1663 clk_name = "enet1"; 1664 } 1665 1666 priv->mac_clk = clk_get(&pdev->dev, clk_name); 1667 if (IS_ERR(priv->mac_clk)) { 1668 ret = PTR_ERR(priv->mac_clk); 1669 goto out; 1670 } 1671 clk_prepare_enable(priv->mac_clk); 1672 1673 /* initialize default and fetch platform data */ 1674 priv->rx_ring_size = BCMENET_DEF_RX_DESC; 1675 priv->tx_ring_size = BCMENET_DEF_TX_DESC; 1676 1677 pd = pdev->dev.platform_data; 1678 if (pd) { 1679 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); 1680 priv->has_phy = pd->has_phy; 1681 priv->phy_id = pd->phy_id; 1682 priv->has_phy_interrupt = pd->has_phy_interrupt; 1683 priv->phy_interrupt = pd->phy_interrupt; 1684 priv->use_external_mii = !pd->use_internal_phy; 1685 priv->pause_auto = pd->pause_auto; 1686 priv->pause_rx = pd->pause_rx; 1687 priv->pause_tx = pd->pause_tx; 1688 priv->force_duplex_full = pd->force_duplex_full; 1689 priv->force_speed_100 = pd->force_speed_100; 1690 } 1691 1692 if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) { 1693 /* using internal PHY, enable clock */ 1694 priv->phy_clk = clk_get(&pdev->dev, "ephy"); 1695 if (IS_ERR(priv->phy_clk)) { 1696 ret = PTR_ERR(priv->phy_clk); 1697 priv->phy_clk = NULL; 1698 goto out_put_clk_mac; 1699 } 1700 clk_prepare_enable(priv->phy_clk); 1701 } 1702 1703 /* do minimal hardware init to be able to probe mii bus */ 1704 bcm_enet_hw_preinit(priv); 1705 1706 /* MII bus registration */ 1707 if (priv->has_phy) { 1708 1709 priv->mii_bus = mdiobus_alloc(); 1710 if (!priv->mii_bus) { 1711 ret = -ENOMEM; 1712 goto out_uninit_hw; 1713 } 1714 1715 bus = priv->mii_bus; 1716 bus->name = "bcm63xx_enet MII bus"; 1717 bus->parent = &pdev->dev; 1718 bus->priv = priv; 1719 bus->read = bcm_enet_mdio_read_phylib; 1720 bus->write = bcm_enet_mdio_write_phylib; 1721 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id); 1722 1723 /* only probe bus where we think the PHY is, because 1724 * the mdio read operation return 0 instead of 0xffff 1725 * if a slave is not present on hw */ 1726 bus->phy_mask = ~(1 << priv->phy_id); 1727 1728 bus->irq = devm_kzalloc(&pdev->dev, sizeof(int) * PHY_MAX_ADDR, 1729 GFP_KERNEL); 1730 if (!bus->irq) { 1731 ret = -ENOMEM; 1732 goto out_free_mdio; 1733 } 1734 1735 if (priv->has_phy_interrupt) 1736 bus->irq[priv->phy_id] = priv->phy_interrupt; 1737 else 1738 bus->irq[priv->phy_id] = PHY_POLL; 1739 1740 ret = mdiobus_register(bus); 1741 if (ret) { 1742 dev_err(&pdev->dev, "unable to register mdio bus\n"); 1743 goto out_free_mdio; 1744 } 1745 } else { 1746 1747 /* run platform code to initialize PHY device */ 1748 if (pd->mii_config && 1749 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii, 1750 bcm_enet_mdio_write_mii)) { 1751 dev_err(&pdev->dev, "unable to configure mdio bus\n"); 1752 goto out_uninit_hw; 1753 } 1754 } 1755 1756 spin_lock_init(&priv->rx_lock); 1757 1758 /* init rx timeout (used for oom) */ 1759 init_timer(&priv->rx_timeout); 1760 priv->rx_timeout.function = bcm_enet_refill_rx_timer; 1761 priv->rx_timeout.data = (unsigned long)dev; 1762 1763 /* init the mib update lock&work */ 1764 mutex_init(&priv->mib_update_lock); 1765 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer); 1766 1767 /* zero mib counters */ 1768 for (i = 0; i < ENET_MIB_REG_COUNT; i++) 1769 enet_writel(priv, 0, ENET_MIB_REG(i)); 1770 1771 /* register netdevice */ 1772 dev->netdev_ops = &bcm_enet_ops; 1773 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); 1774 1775 SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops); 1776 SET_NETDEV_DEV(dev, &pdev->dev); 1777 1778 ret = register_netdev(dev); 1779 if (ret) 1780 goto out_unregister_mdio; 1781 1782 netif_carrier_off(dev); 1783 platform_set_drvdata(pdev, dev); 1784 priv->pdev = pdev; 1785 priv->net_dev = dev; 1786 1787 return 0; 1788 1789 out_unregister_mdio: 1790 if (priv->mii_bus) 1791 mdiobus_unregister(priv->mii_bus); 1792 1793 out_free_mdio: 1794 if (priv->mii_bus) 1795 mdiobus_free(priv->mii_bus); 1796 1797 out_uninit_hw: 1798 /* turn off mdc clock */ 1799 enet_writel(priv, 0, ENET_MIISC_REG); 1800 if (priv->phy_clk) { 1801 clk_disable_unprepare(priv->phy_clk); 1802 clk_put(priv->phy_clk); 1803 } 1804 1805 out_put_clk_mac: 1806 clk_disable_unprepare(priv->mac_clk); 1807 clk_put(priv->mac_clk); 1808 out: 1809 free_netdev(dev); 1810 return ret; 1811 } 1812 1813 1814 /* 1815 * exit func, stops hardware and unregisters netdevice 1816 */ 1817 static int bcm_enet_remove(struct platform_device *pdev) 1818 { 1819 struct bcm_enet_priv *priv; 1820 struct net_device *dev; 1821 1822 /* stop netdevice */ 1823 dev = platform_get_drvdata(pdev); 1824 priv = netdev_priv(dev); 1825 unregister_netdev(dev); 1826 1827 /* turn off mdc clock */ 1828 enet_writel(priv, 0, ENET_MIISC_REG); 1829 1830 if (priv->has_phy) { 1831 mdiobus_unregister(priv->mii_bus); 1832 mdiobus_free(priv->mii_bus); 1833 } else { 1834 struct bcm63xx_enet_platform_data *pd; 1835 1836 pd = pdev->dev.platform_data; 1837 if (pd && pd->mii_config) 1838 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii, 1839 bcm_enet_mdio_write_mii); 1840 } 1841 1842 /* disable hw block clocks */ 1843 if (priv->phy_clk) { 1844 clk_disable_unprepare(priv->phy_clk); 1845 clk_put(priv->phy_clk); 1846 } 1847 clk_disable_unprepare(priv->mac_clk); 1848 clk_put(priv->mac_clk); 1849 1850 platform_set_drvdata(pdev, NULL); 1851 free_netdev(dev); 1852 return 0; 1853 } 1854 1855 struct platform_driver bcm63xx_enet_driver = { 1856 .probe = bcm_enet_probe, 1857 .remove = bcm_enet_remove, 1858 .driver = { 1859 .name = "bcm63xx_enet", 1860 .owner = THIS_MODULE, 1861 }, 1862 }; 1863 1864 /* 1865 * reserve & remap memory space shared between all macs 1866 */ 1867 static int bcm_enet_shared_probe(struct platform_device *pdev) 1868 { 1869 struct resource *res; 1870 1871 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1872 if (!res) 1873 return -ENODEV; 1874 1875 bcm_enet_shared_base = devm_request_and_ioremap(&pdev->dev, res); 1876 if (!bcm_enet_shared_base) 1877 return -ENOMEM; 1878 1879 return 0; 1880 } 1881 1882 static int bcm_enet_shared_remove(struct platform_device *pdev) 1883 { 1884 return 0; 1885 } 1886 1887 /* 1888 * this "shared" driver is needed because both macs share a single 1889 * address space 1890 */ 1891 struct platform_driver bcm63xx_enet_shared_driver = { 1892 .probe = bcm_enet_shared_probe, 1893 .remove = bcm_enet_shared_remove, 1894 .driver = { 1895 .name = "bcm63xx_enet_shared", 1896 .owner = THIS_MODULE, 1897 }, 1898 }; 1899 1900 /* 1901 * entry point 1902 */ 1903 static int __init bcm_enet_init(void) 1904 { 1905 int ret; 1906 1907 ret = platform_driver_register(&bcm63xx_enet_shared_driver); 1908 if (ret) 1909 return ret; 1910 1911 ret = platform_driver_register(&bcm63xx_enet_driver); 1912 if (ret) 1913 platform_driver_unregister(&bcm63xx_enet_shared_driver); 1914 1915 return ret; 1916 } 1917 1918 static void __exit bcm_enet_exit(void) 1919 { 1920 platform_driver_unregister(&bcm63xx_enet_driver); 1921 platform_driver_unregister(&bcm63xx_enet_shared_driver); 1922 } 1923 1924 1925 module_init(bcm_enet_init); 1926 module_exit(bcm_enet_exit); 1927 1928 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver"); 1929 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); 1930 MODULE_LICENSE("GPL"); 1931