1 /* 2 * Driver for BCM963xx builtin Ethernet mac 3 * 4 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/clk.h> 24 #include <linux/etherdevice.h> 25 #include <linux/slab.h> 26 #include <linux/delay.h> 27 #include <linux/ethtool.h> 28 #include <linux/crc32.h> 29 #include <linux/err.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/platform_device.h> 32 #include <linux/if_vlan.h> 33 34 #include <bcm63xx_dev_enet.h> 35 #include "bcm63xx_enet.h" 36 37 static char bcm_enet_driver_name[] = "bcm63xx_enet"; 38 static char bcm_enet_driver_version[] = "1.0"; 39 40 static int copybreak __read_mostly = 128; 41 module_param(copybreak, int, 0); 42 MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 43 44 /* io registers memory shared between all devices */ 45 static void __iomem *bcm_enet_shared_base[3]; 46 47 /* 48 * io helpers to access mac registers 49 */ 50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off) 51 { 52 return bcm_readl(priv->base + off); 53 } 54 55 static inline void enet_writel(struct bcm_enet_priv *priv, 56 u32 val, u32 off) 57 { 58 bcm_writel(val, priv->base + off); 59 } 60 61 /* 62 * io helpers to access switch registers 63 */ 64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off) 65 { 66 return bcm_readl(priv->base + off); 67 } 68 69 static inline void enetsw_writel(struct bcm_enet_priv *priv, 70 u32 val, u32 off) 71 { 72 bcm_writel(val, priv->base + off); 73 } 74 75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off) 76 { 77 return bcm_readw(priv->base + off); 78 } 79 80 static inline void enetsw_writew(struct bcm_enet_priv *priv, 81 u16 val, u32 off) 82 { 83 bcm_writew(val, priv->base + off); 84 } 85 86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off) 87 { 88 return bcm_readb(priv->base + off); 89 } 90 91 static inline void enetsw_writeb(struct bcm_enet_priv *priv, 92 u8 val, u32 off) 93 { 94 bcm_writeb(val, priv->base + off); 95 } 96 97 98 /* io helpers to access shared registers */ 99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off) 100 { 101 return bcm_readl(bcm_enet_shared_base[0] + off); 102 } 103 104 static inline void enet_dma_writel(struct bcm_enet_priv *priv, 105 u32 val, u32 off) 106 { 107 bcm_writel(val, bcm_enet_shared_base[0] + off); 108 } 109 110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan) 111 { 112 return bcm_readl(bcm_enet_shared_base[1] + 113 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width); 114 } 115 116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv, 117 u32 val, u32 off, int chan) 118 { 119 bcm_writel(val, bcm_enet_shared_base[1] + 120 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width); 121 } 122 123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan) 124 { 125 return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width); 126 } 127 128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv, 129 u32 val, u32 off, int chan) 130 { 131 bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width); 132 } 133 134 /* 135 * write given data into mii register and wait for transfer to end 136 * with timeout (average measured transfer time is 25us) 137 */ 138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data) 139 { 140 int limit; 141 142 /* make sure mii interrupt status is cleared */ 143 enet_writel(priv, ENET_IR_MII, ENET_IR_REG); 144 145 enet_writel(priv, data, ENET_MIIDATA_REG); 146 wmb(); 147 148 /* busy wait on mii interrupt bit, with timeout */ 149 limit = 1000; 150 do { 151 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII) 152 break; 153 udelay(1); 154 } while (limit-- > 0); 155 156 return (limit < 0) ? 1 : 0; 157 } 158 159 /* 160 * MII internal read callback 161 */ 162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id, 163 int regnum) 164 { 165 u32 tmp, val; 166 167 tmp = regnum << ENET_MIIDATA_REG_SHIFT; 168 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT; 169 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT; 170 tmp |= ENET_MIIDATA_OP_READ_MASK; 171 172 if (do_mdio_op(priv, tmp)) 173 return -1; 174 175 val = enet_readl(priv, ENET_MIIDATA_REG); 176 val &= 0xffff; 177 return val; 178 } 179 180 /* 181 * MII internal write callback 182 */ 183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id, 184 int regnum, u16 value) 185 { 186 u32 tmp; 187 188 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT; 189 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT; 190 tmp |= regnum << ENET_MIIDATA_REG_SHIFT; 191 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT; 192 tmp |= ENET_MIIDATA_OP_WRITE_MASK; 193 194 (void)do_mdio_op(priv, tmp); 195 return 0; 196 } 197 198 /* 199 * MII read callback from phylib 200 */ 201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id, 202 int regnum) 203 { 204 return bcm_enet_mdio_read(bus->priv, mii_id, regnum); 205 } 206 207 /* 208 * MII write callback from phylib 209 */ 210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id, 211 int regnum, u16 value) 212 { 213 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value); 214 } 215 216 /* 217 * MII read callback from mii core 218 */ 219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id, 220 int regnum) 221 { 222 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum); 223 } 224 225 /* 226 * MII write callback from mii core 227 */ 228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id, 229 int regnum, int value) 230 { 231 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value); 232 } 233 234 /* 235 * refill rx queue 236 */ 237 static int bcm_enet_refill_rx(struct net_device *dev) 238 { 239 struct bcm_enet_priv *priv; 240 241 priv = netdev_priv(dev); 242 243 while (priv->rx_desc_count < priv->rx_ring_size) { 244 struct bcm_enet_desc *desc; 245 struct sk_buff *skb; 246 dma_addr_t p; 247 int desc_idx; 248 u32 len_stat; 249 250 desc_idx = priv->rx_dirty_desc; 251 desc = &priv->rx_desc_cpu[desc_idx]; 252 253 if (!priv->rx_skb[desc_idx]) { 254 skb = netdev_alloc_skb(dev, priv->rx_skb_size); 255 if (!skb) 256 break; 257 priv->rx_skb[desc_idx] = skb; 258 p = dma_map_single(&priv->pdev->dev, skb->data, 259 priv->rx_skb_size, 260 DMA_FROM_DEVICE); 261 desc->address = p; 262 } 263 264 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT; 265 len_stat |= DMADESC_OWNER_MASK; 266 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) { 267 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift); 268 priv->rx_dirty_desc = 0; 269 } else { 270 priv->rx_dirty_desc++; 271 } 272 wmb(); 273 desc->len_stat = len_stat; 274 275 priv->rx_desc_count++; 276 277 /* tell dma engine we allocated one buffer */ 278 if (priv->dma_has_sram) 279 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan)); 280 else 281 enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan); 282 } 283 284 /* If rx ring is still empty, set a timer to try allocating 285 * again at a later time. */ 286 if (priv->rx_desc_count == 0 && netif_running(dev)) { 287 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n"); 288 priv->rx_timeout.expires = jiffies + HZ; 289 add_timer(&priv->rx_timeout); 290 } 291 292 return 0; 293 } 294 295 /* 296 * timer callback to defer refill rx queue in case we're OOM 297 */ 298 static void bcm_enet_refill_rx_timer(unsigned long data) 299 { 300 struct net_device *dev; 301 struct bcm_enet_priv *priv; 302 303 dev = (struct net_device *)data; 304 priv = netdev_priv(dev); 305 306 spin_lock(&priv->rx_lock); 307 bcm_enet_refill_rx((struct net_device *)data); 308 spin_unlock(&priv->rx_lock); 309 } 310 311 /* 312 * extract packet from rx queue 313 */ 314 static int bcm_enet_receive_queue(struct net_device *dev, int budget) 315 { 316 struct bcm_enet_priv *priv; 317 struct device *kdev; 318 int processed; 319 320 priv = netdev_priv(dev); 321 kdev = &priv->pdev->dev; 322 processed = 0; 323 324 /* don't scan ring further than number of refilled 325 * descriptor */ 326 if (budget > priv->rx_desc_count) 327 budget = priv->rx_desc_count; 328 329 do { 330 struct bcm_enet_desc *desc; 331 struct sk_buff *skb; 332 int desc_idx; 333 u32 len_stat; 334 unsigned int len; 335 336 desc_idx = priv->rx_curr_desc; 337 desc = &priv->rx_desc_cpu[desc_idx]; 338 339 /* make sure we actually read the descriptor status at 340 * each loop */ 341 rmb(); 342 343 len_stat = desc->len_stat; 344 345 /* break if dma ownership belongs to hw */ 346 if (len_stat & DMADESC_OWNER_MASK) 347 break; 348 349 processed++; 350 priv->rx_curr_desc++; 351 if (priv->rx_curr_desc == priv->rx_ring_size) 352 priv->rx_curr_desc = 0; 353 priv->rx_desc_count--; 354 355 /* if the packet does not have start of packet _and_ 356 * end of packet flag set, then just recycle it */ 357 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) != 358 (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) { 359 dev->stats.rx_dropped++; 360 continue; 361 } 362 363 /* recycle packet if it's marked as bad */ 364 if (!priv->enet_is_sw && 365 unlikely(len_stat & DMADESC_ERR_MASK)) { 366 dev->stats.rx_errors++; 367 368 if (len_stat & DMADESC_OVSIZE_MASK) 369 dev->stats.rx_length_errors++; 370 if (len_stat & DMADESC_CRC_MASK) 371 dev->stats.rx_crc_errors++; 372 if (len_stat & DMADESC_UNDER_MASK) 373 dev->stats.rx_frame_errors++; 374 if (len_stat & DMADESC_OV_MASK) 375 dev->stats.rx_fifo_errors++; 376 continue; 377 } 378 379 /* valid packet */ 380 skb = priv->rx_skb[desc_idx]; 381 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT; 382 /* don't include FCS */ 383 len -= 4; 384 385 if (len < copybreak) { 386 struct sk_buff *nskb; 387 388 nskb = napi_alloc_skb(&priv->napi, len); 389 if (!nskb) { 390 /* forget packet, just rearm desc */ 391 dev->stats.rx_dropped++; 392 continue; 393 } 394 395 dma_sync_single_for_cpu(kdev, desc->address, 396 len, DMA_FROM_DEVICE); 397 memcpy(nskb->data, skb->data, len); 398 dma_sync_single_for_device(kdev, desc->address, 399 len, DMA_FROM_DEVICE); 400 skb = nskb; 401 } else { 402 dma_unmap_single(&priv->pdev->dev, desc->address, 403 priv->rx_skb_size, DMA_FROM_DEVICE); 404 priv->rx_skb[desc_idx] = NULL; 405 } 406 407 skb_put(skb, len); 408 skb->protocol = eth_type_trans(skb, dev); 409 dev->stats.rx_packets++; 410 dev->stats.rx_bytes += len; 411 netif_receive_skb(skb); 412 413 } while (--budget > 0); 414 415 if (processed || !priv->rx_desc_count) { 416 bcm_enet_refill_rx(dev); 417 418 /* kick rx dma */ 419 enet_dmac_writel(priv, priv->dma_chan_en_mask, 420 ENETDMAC_CHANCFG, priv->rx_chan); 421 } 422 423 return processed; 424 } 425 426 427 /* 428 * try to or force reclaim of transmitted buffers 429 */ 430 static int bcm_enet_tx_reclaim(struct net_device *dev, int force) 431 { 432 struct bcm_enet_priv *priv; 433 int released; 434 435 priv = netdev_priv(dev); 436 released = 0; 437 438 while (priv->tx_desc_count < priv->tx_ring_size) { 439 struct bcm_enet_desc *desc; 440 struct sk_buff *skb; 441 442 /* We run in a bh and fight against start_xmit, which 443 * is called with bh disabled */ 444 spin_lock(&priv->tx_lock); 445 446 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc]; 447 448 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) { 449 spin_unlock(&priv->tx_lock); 450 break; 451 } 452 453 /* ensure other field of the descriptor were not read 454 * before we checked ownership */ 455 rmb(); 456 457 skb = priv->tx_skb[priv->tx_dirty_desc]; 458 priv->tx_skb[priv->tx_dirty_desc] = NULL; 459 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len, 460 DMA_TO_DEVICE); 461 462 priv->tx_dirty_desc++; 463 if (priv->tx_dirty_desc == priv->tx_ring_size) 464 priv->tx_dirty_desc = 0; 465 priv->tx_desc_count++; 466 467 spin_unlock(&priv->tx_lock); 468 469 if (desc->len_stat & DMADESC_UNDER_MASK) 470 dev->stats.tx_errors++; 471 472 dev_kfree_skb(skb); 473 released++; 474 } 475 476 if (netif_queue_stopped(dev) && released) 477 netif_wake_queue(dev); 478 479 return released; 480 } 481 482 /* 483 * poll func, called by network core 484 */ 485 static int bcm_enet_poll(struct napi_struct *napi, int budget) 486 { 487 struct bcm_enet_priv *priv; 488 struct net_device *dev; 489 int rx_work_done; 490 491 priv = container_of(napi, struct bcm_enet_priv, napi); 492 dev = priv->net_dev; 493 494 /* ack interrupts */ 495 enet_dmac_writel(priv, priv->dma_chan_int_mask, 496 ENETDMAC_IR, priv->rx_chan); 497 enet_dmac_writel(priv, priv->dma_chan_int_mask, 498 ENETDMAC_IR, priv->tx_chan); 499 500 /* reclaim sent skb */ 501 bcm_enet_tx_reclaim(dev, 0); 502 503 spin_lock(&priv->rx_lock); 504 rx_work_done = bcm_enet_receive_queue(dev, budget); 505 spin_unlock(&priv->rx_lock); 506 507 if (rx_work_done >= budget) { 508 /* rx queue is not yet empty/clean */ 509 return rx_work_done; 510 } 511 512 /* no more packet in rx/tx queue, remove device from poll 513 * queue */ 514 napi_complete_done(napi, rx_work_done); 515 516 /* restore rx/tx interrupt */ 517 enet_dmac_writel(priv, priv->dma_chan_int_mask, 518 ENETDMAC_IRMASK, priv->rx_chan); 519 enet_dmac_writel(priv, priv->dma_chan_int_mask, 520 ENETDMAC_IRMASK, priv->tx_chan); 521 522 return rx_work_done; 523 } 524 525 /* 526 * mac interrupt handler 527 */ 528 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id) 529 { 530 struct net_device *dev; 531 struct bcm_enet_priv *priv; 532 u32 stat; 533 534 dev = dev_id; 535 priv = netdev_priv(dev); 536 537 stat = enet_readl(priv, ENET_IR_REG); 538 if (!(stat & ENET_IR_MIB)) 539 return IRQ_NONE; 540 541 /* clear & mask interrupt */ 542 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG); 543 enet_writel(priv, 0, ENET_IRMASK_REG); 544 545 /* read mib registers in workqueue */ 546 schedule_work(&priv->mib_update_task); 547 548 return IRQ_HANDLED; 549 } 550 551 /* 552 * rx/tx dma interrupt handler 553 */ 554 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id) 555 { 556 struct net_device *dev; 557 struct bcm_enet_priv *priv; 558 559 dev = dev_id; 560 priv = netdev_priv(dev); 561 562 /* mask rx/tx interrupts */ 563 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); 564 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); 565 566 napi_schedule(&priv->napi); 567 568 return IRQ_HANDLED; 569 } 570 571 /* 572 * tx request callback 573 */ 574 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) 575 { 576 struct bcm_enet_priv *priv; 577 struct bcm_enet_desc *desc; 578 u32 len_stat; 579 int ret; 580 581 priv = netdev_priv(dev); 582 583 /* lock against tx reclaim */ 584 spin_lock(&priv->tx_lock); 585 586 /* make sure the tx hw queue is not full, should not happen 587 * since we stop queue before it's the case */ 588 if (unlikely(!priv->tx_desc_count)) { 589 netif_stop_queue(dev); 590 dev_err(&priv->pdev->dev, "xmit called with no tx desc " 591 "available?\n"); 592 ret = NETDEV_TX_BUSY; 593 goto out_unlock; 594 } 595 596 /* pad small packets sent on a switch device */ 597 if (priv->enet_is_sw && skb->len < 64) { 598 int needed = 64 - skb->len; 599 char *data; 600 601 if (unlikely(skb_tailroom(skb) < needed)) { 602 struct sk_buff *nskb; 603 604 nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC); 605 if (!nskb) { 606 ret = NETDEV_TX_BUSY; 607 goto out_unlock; 608 } 609 dev_kfree_skb(skb); 610 skb = nskb; 611 } 612 data = skb_put_zero(skb, needed); 613 } 614 615 /* point to the next available desc */ 616 desc = &priv->tx_desc_cpu[priv->tx_curr_desc]; 617 priv->tx_skb[priv->tx_curr_desc] = skb; 618 619 /* fill descriptor */ 620 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len, 621 DMA_TO_DEVICE); 622 623 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK; 624 len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) | 625 DMADESC_APPEND_CRC | 626 DMADESC_OWNER_MASK; 627 628 priv->tx_curr_desc++; 629 if (priv->tx_curr_desc == priv->tx_ring_size) { 630 priv->tx_curr_desc = 0; 631 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift); 632 } 633 priv->tx_desc_count--; 634 635 /* dma might be already polling, make sure we update desc 636 * fields in correct order */ 637 wmb(); 638 desc->len_stat = len_stat; 639 wmb(); 640 641 /* kick tx dma */ 642 enet_dmac_writel(priv, priv->dma_chan_en_mask, 643 ENETDMAC_CHANCFG, priv->tx_chan); 644 645 /* stop queue if no more desc available */ 646 if (!priv->tx_desc_count) 647 netif_stop_queue(dev); 648 649 dev->stats.tx_bytes += skb->len; 650 dev->stats.tx_packets++; 651 ret = NETDEV_TX_OK; 652 653 out_unlock: 654 spin_unlock(&priv->tx_lock); 655 return ret; 656 } 657 658 /* 659 * Change the interface's mac address. 660 */ 661 static int bcm_enet_set_mac_address(struct net_device *dev, void *p) 662 { 663 struct bcm_enet_priv *priv; 664 struct sockaddr *addr = p; 665 u32 val; 666 667 priv = netdev_priv(dev); 668 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 669 670 /* use perfect match register 0 to store my mac address */ 671 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) | 672 (dev->dev_addr[4] << 8) | dev->dev_addr[5]; 673 enet_writel(priv, val, ENET_PML_REG(0)); 674 675 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]); 676 val |= ENET_PMH_DATAVALID_MASK; 677 enet_writel(priv, val, ENET_PMH_REG(0)); 678 679 return 0; 680 } 681 682 /* 683 * Change rx mode (promiscuous/allmulti) and update multicast list 684 */ 685 static void bcm_enet_set_multicast_list(struct net_device *dev) 686 { 687 struct bcm_enet_priv *priv; 688 struct netdev_hw_addr *ha; 689 u32 val; 690 int i; 691 692 priv = netdev_priv(dev); 693 694 val = enet_readl(priv, ENET_RXCFG_REG); 695 696 if (dev->flags & IFF_PROMISC) 697 val |= ENET_RXCFG_PROMISC_MASK; 698 else 699 val &= ~ENET_RXCFG_PROMISC_MASK; 700 701 /* only 3 perfect match registers left, first one is used for 702 * own mac address */ 703 if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3) 704 val |= ENET_RXCFG_ALLMCAST_MASK; 705 else 706 val &= ~ENET_RXCFG_ALLMCAST_MASK; 707 708 /* no need to set perfect match registers if we catch all 709 * multicast */ 710 if (val & ENET_RXCFG_ALLMCAST_MASK) { 711 enet_writel(priv, val, ENET_RXCFG_REG); 712 return; 713 } 714 715 i = 0; 716 netdev_for_each_mc_addr(ha, dev) { 717 u8 *dmi_addr; 718 u32 tmp; 719 720 if (i == 3) 721 break; 722 /* update perfect match registers */ 723 dmi_addr = ha->addr; 724 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) | 725 (dmi_addr[4] << 8) | dmi_addr[5]; 726 enet_writel(priv, tmp, ENET_PML_REG(i + 1)); 727 728 tmp = (dmi_addr[0] << 8 | dmi_addr[1]); 729 tmp |= ENET_PMH_DATAVALID_MASK; 730 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1)); 731 } 732 733 for (; i < 3; i++) { 734 enet_writel(priv, 0, ENET_PML_REG(i + 1)); 735 enet_writel(priv, 0, ENET_PMH_REG(i + 1)); 736 } 737 738 enet_writel(priv, val, ENET_RXCFG_REG); 739 } 740 741 /* 742 * set mac duplex parameters 743 */ 744 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex) 745 { 746 u32 val; 747 748 val = enet_readl(priv, ENET_TXCTL_REG); 749 if (fullduplex) 750 val |= ENET_TXCTL_FD_MASK; 751 else 752 val &= ~ENET_TXCTL_FD_MASK; 753 enet_writel(priv, val, ENET_TXCTL_REG); 754 } 755 756 /* 757 * set mac flow control parameters 758 */ 759 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en) 760 { 761 u32 val; 762 763 /* rx flow control (pause frame handling) */ 764 val = enet_readl(priv, ENET_RXCFG_REG); 765 if (rx_en) 766 val |= ENET_RXCFG_ENFLOW_MASK; 767 else 768 val &= ~ENET_RXCFG_ENFLOW_MASK; 769 enet_writel(priv, val, ENET_RXCFG_REG); 770 771 if (!priv->dma_has_sram) 772 return; 773 774 /* tx flow control (pause frame generation) */ 775 val = enet_dma_readl(priv, ENETDMA_CFG_REG); 776 if (tx_en) 777 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); 778 else 779 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); 780 enet_dma_writel(priv, val, ENETDMA_CFG_REG); 781 } 782 783 /* 784 * link changed callback (from phylib) 785 */ 786 static void bcm_enet_adjust_phy_link(struct net_device *dev) 787 { 788 struct bcm_enet_priv *priv; 789 struct phy_device *phydev; 790 int status_changed; 791 792 priv = netdev_priv(dev); 793 phydev = dev->phydev; 794 status_changed = 0; 795 796 if (priv->old_link != phydev->link) { 797 status_changed = 1; 798 priv->old_link = phydev->link; 799 } 800 801 /* reflect duplex change in mac configuration */ 802 if (phydev->link && phydev->duplex != priv->old_duplex) { 803 bcm_enet_set_duplex(priv, 804 (phydev->duplex == DUPLEX_FULL) ? 1 : 0); 805 status_changed = 1; 806 priv->old_duplex = phydev->duplex; 807 } 808 809 /* enable flow control if remote advertise it (trust phylib to 810 * check that duplex is full */ 811 if (phydev->link && phydev->pause != priv->old_pause) { 812 int rx_pause_en, tx_pause_en; 813 814 if (phydev->pause) { 815 /* pause was advertised by lpa and us */ 816 rx_pause_en = 1; 817 tx_pause_en = 1; 818 } else if (!priv->pause_auto) { 819 /* pause setting overridden by user */ 820 rx_pause_en = priv->pause_rx; 821 tx_pause_en = priv->pause_tx; 822 } else { 823 rx_pause_en = 0; 824 tx_pause_en = 0; 825 } 826 827 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en); 828 status_changed = 1; 829 priv->old_pause = phydev->pause; 830 } 831 832 if (status_changed) { 833 pr_info("%s: link %s", dev->name, phydev->link ? 834 "UP" : "DOWN"); 835 if (phydev->link) 836 pr_cont(" - %d/%s - flow control %s", phydev->speed, 837 DUPLEX_FULL == phydev->duplex ? "full" : "half", 838 phydev->pause == 1 ? "rx&tx" : "off"); 839 840 pr_cont("\n"); 841 } 842 } 843 844 /* 845 * link changed callback (if phylib is not used) 846 */ 847 static void bcm_enet_adjust_link(struct net_device *dev) 848 { 849 struct bcm_enet_priv *priv; 850 851 priv = netdev_priv(dev); 852 bcm_enet_set_duplex(priv, priv->force_duplex_full); 853 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx); 854 netif_carrier_on(dev); 855 856 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n", 857 dev->name, 858 priv->force_speed_100 ? 100 : 10, 859 priv->force_duplex_full ? "full" : "half", 860 priv->pause_rx ? "rx" : "off", 861 priv->pause_tx ? "tx" : "off"); 862 } 863 864 /* 865 * open callback, allocate dma rings & buffers and start rx operation 866 */ 867 static int bcm_enet_open(struct net_device *dev) 868 { 869 struct bcm_enet_priv *priv; 870 struct sockaddr addr; 871 struct device *kdev; 872 struct phy_device *phydev; 873 int i, ret; 874 unsigned int size; 875 char phy_id[MII_BUS_ID_SIZE + 3]; 876 void *p; 877 u32 val; 878 879 priv = netdev_priv(dev); 880 kdev = &priv->pdev->dev; 881 882 if (priv->has_phy) { 883 /* connect to PHY */ 884 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 885 priv->mii_bus->id, priv->phy_id); 886 887 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link, 888 PHY_INTERFACE_MODE_MII); 889 890 if (IS_ERR(phydev)) { 891 dev_err(kdev, "could not attach to PHY\n"); 892 return PTR_ERR(phydev); 893 } 894 895 /* mask with MAC supported features */ 896 phydev->supported &= (SUPPORTED_10baseT_Half | 897 SUPPORTED_10baseT_Full | 898 SUPPORTED_100baseT_Half | 899 SUPPORTED_100baseT_Full | 900 SUPPORTED_Autoneg | 901 SUPPORTED_Pause | 902 SUPPORTED_MII); 903 phydev->advertising = phydev->supported; 904 905 if (priv->pause_auto && priv->pause_rx && priv->pause_tx) 906 phydev->advertising |= SUPPORTED_Pause; 907 else 908 phydev->advertising &= ~SUPPORTED_Pause; 909 910 phy_attached_info(phydev); 911 912 priv->old_link = 0; 913 priv->old_duplex = -1; 914 priv->old_pause = -1; 915 } else { 916 phydev = NULL; 917 } 918 919 /* mask all interrupts and request them */ 920 enet_writel(priv, 0, ENET_IRMASK_REG); 921 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); 922 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); 923 924 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev); 925 if (ret) 926 goto out_phy_disconnect; 927 928 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0, 929 dev->name, dev); 930 if (ret) 931 goto out_freeirq; 932 933 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma, 934 0, dev->name, dev); 935 if (ret) 936 goto out_freeirq_rx; 937 938 /* initialize perfect match registers */ 939 for (i = 0; i < 4; i++) { 940 enet_writel(priv, 0, ENET_PML_REG(i)); 941 enet_writel(priv, 0, ENET_PMH_REG(i)); 942 } 943 944 /* write device mac address */ 945 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN); 946 bcm_enet_set_mac_address(dev, &addr); 947 948 /* allocate rx dma ring */ 949 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc); 950 p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL); 951 if (!p) { 952 ret = -ENOMEM; 953 goto out_freeirq_tx; 954 } 955 956 priv->rx_desc_alloc_size = size; 957 priv->rx_desc_cpu = p; 958 959 /* allocate tx dma ring */ 960 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc); 961 p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL); 962 if (!p) { 963 ret = -ENOMEM; 964 goto out_free_rx_ring; 965 } 966 967 priv->tx_desc_alloc_size = size; 968 priv->tx_desc_cpu = p; 969 970 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *), 971 GFP_KERNEL); 972 if (!priv->tx_skb) { 973 ret = -ENOMEM; 974 goto out_free_tx_ring; 975 } 976 977 priv->tx_desc_count = priv->tx_ring_size; 978 priv->tx_dirty_desc = 0; 979 priv->tx_curr_desc = 0; 980 spin_lock_init(&priv->tx_lock); 981 982 /* init & fill rx ring with skbs */ 983 priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *), 984 GFP_KERNEL); 985 if (!priv->rx_skb) { 986 ret = -ENOMEM; 987 goto out_free_tx_skb; 988 } 989 990 priv->rx_desc_count = 0; 991 priv->rx_dirty_desc = 0; 992 priv->rx_curr_desc = 0; 993 994 /* initialize flow control buffer allocation */ 995 if (priv->dma_has_sram) 996 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, 997 ENETDMA_BUFALLOC_REG(priv->rx_chan)); 998 else 999 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, 1000 ENETDMAC_BUFALLOC, priv->rx_chan); 1001 1002 if (bcm_enet_refill_rx(dev)) { 1003 dev_err(kdev, "cannot allocate rx skb queue\n"); 1004 ret = -ENOMEM; 1005 goto out; 1006 } 1007 1008 /* write rx & tx ring addresses */ 1009 if (priv->dma_has_sram) { 1010 enet_dmas_writel(priv, priv->rx_desc_dma, 1011 ENETDMAS_RSTART_REG, priv->rx_chan); 1012 enet_dmas_writel(priv, priv->tx_desc_dma, 1013 ENETDMAS_RSTART_REG, priv->tx_chan); 1014 } else { 1015 enet_dmac_writel(priv, priv->rx_desc_dma, 1016 ENETDMAC_RSTART, priv->rx_chan); 1017 enet_dmac_writel(priv, priv->tx_desc_dma, 1018 ENETDMAC_RSTART, priv->tx_chan); 1019 } 1020 1021 /* clear remaining state ram for rx & tx channel */ 1022 if (priv->dma_has_sram) { 1023 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan); 1024 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan); 1025 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan); 1026 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan); 1027 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan); 1028 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan); 1029 } else { 1030 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan); 1031 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan); 1032 } 1033 1034 /* set max rx/tx length */ 1035 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG); 1036 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG); 1037 1038 /* set dma maximum burst len */ 1039 enet_dmac_writel(priv, priv->dma_maxburst, 1040 ENETDMAC_MAXBURST, priv->rx_chan); 1041 enet_dmac_writel(priv, priv->dma_maxburst, 1042 ENETDMAC_MAXBURST, priv->tx_chan); 1043 1044 /* set correct transmit fifo watermark */ 1045 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG); 1046 1047 /* set flow control low/high threshold to 1/3 / 2/3 */ 1048 if (priv->dma_has_sram) { 1049 val = priv->rx_ring_size / 3; 1050 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan)); 1051 val = (priv->rx_ring_size * 2) / 3; 1052 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan)); 1053 } else { 1054 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan); 1055 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan); 1056 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan); 1057 } 1058 1059 /* all set, enable mac and interrupts, start dma engine and 1060 * kick rx dma channel */ 1061 wmb(); 1062 val = enet_readl(priv, ENET_CTL_REG); 1063 val |= ENET_CTL_ENABLE_MASK; 1064 enet_writel(priv, val, ENET_CTL_REG); 1065 if (priv->dma_has_sram) 1066 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG); 1067 enet_dmac_writel(priv, priv->dma_chan_en_mask, 1068 ENETDMAC_CHANCFG, priv->rx_chan); 1069 1070 /* watch "mib counters about to overflow" interrupt */ 1071 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG); 1072 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG); 1073 1074 /* watch "packet transferred" interrupt in rx and tx */ 1075 enet_dmac_writel(priv, priv->dma_chan_int_mask, 1076 ENETDMAC_IR, priv->rx_chan); 1077 enet_dmac_writel(priv, priv->dma_chan_int_mask, 1078 ENETDMAC_IR, priv->tx_chan); 1079 1080 /* make sure we enable napi before rx interrupt */ 1081 napi_enable(&priv->napi); 1082 1083 enet_dmac_writel(priv, priv->dma_chan_int_mask, 1084 ENETDMAC_IRMASK, priv->rx_chan); 1085 enet_dmac_writel(priv, priv->dma_chan_int_mask, 1086 ENETDMAC_IRMASK, priv->tx_chan); 1087 1088 if (phydev) 1089 phy_start(phydev); 1090 else 1091 bcm_enet_adjust_link(dev); 1092 1093 netif_start_queue(dev); 1094 return 0; 1095 1096 out: 1097 for (i = 0; i < priv->rx_ring_size; i++) { 1098 struct bcm_enet_desc *desc; 1099 1100 if (!priv->rx_skb[i]) 1101 continue; 1102 1103 desc = &priv->rx_desc_cpu[i]; 1104 dma_unmap_single(kdev, desc->address, priv->rx_skb_size, 1105 DMA_FROM_DEVICE); 1106 kfree_skb(priv->rx_skb[i]); 1107 } 1108 kfree(priv->rx_skb); 1109 1110 out_free_tx_skb: 1111 kfree(priv->tx_skb); 1112 1113 out_free_tx_ring: 1114 dma_free_coherent(kdev, priv->tx_desc_alloc_size, 1115 priv->tx_desc_cpu, priv->tx_desc_dma); 1116 1117 out_free_rx_ring: 1118 dma_free_coherent(kdev, priv->rx_desc_alloc_size, 1119 priv->rx_desc_cpu, priv->rx_desc_dma); 1120 1121 out_freeirq_tx: 1122 free_irq(priv->irq_tx, dev); 1123 1124 out_freeirq_rx: 1125 free_irq(priv->irq_rx, dev); 1126 1127 out_freeirq: 1128 free_irq(dev->irq, dev); 1129 1130 out_phy_disconnect: 1131 if (phydev) 1132 phy_disconnect(phydev); 1133 1134 return ret; 1135 } 1136 1137 /* 1138 * disable mac 1139 */ 1140 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv) 1141 { 1142 int limit; 1143 u32 val; 1144 1145 val = enet_readl(priv, ENET_CTL_REG); 1146 val |= ENET_CTL_DISABLE_MASK; 1147 enet_writel(priv, val, ENET_CTL_REG); 1148 1149 limit = 1000; 1150 do { 1151 u32 val; 1152 1153 val = enet_readl(priv, ENET_CTL_REG); 1154 if (!(val & ENET_CTL_DISABLE_MASK)) 1155 break; 1156 udelay(1); 1157 } while (limit--); 1158 } 1159 1160 /* 1161 * disable dma in given channel 1162 */ 1163 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan) 1164 { 1165 int limit; 1166 1167 enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan); 1168 1169 limit = 1000; 1170 do { 1171 u32 val; 1172 1173 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan); 1174 if (!(val & ENETDMAC_CHANCFG_EN_MASK)) 1175 break; 1176 udelay(1); 1177 } while (limit--); 1178 } 1179 1180 /* 1181 * stop callback 1182 */ 1183 static int bcm_enet_stop(struct net_device *dev) 1184 { 1185 struct bcm_enet_priv *priv; 1186 struct device *kdev; 1187 int i; 1188 1189 priv = netdev_priv(dev); 1190 kdev = &priv->pdev->dev; 1191 1192 netif_stop_queue(dev); 1193 napi_disable(&priv->napi); 1194 if (priv->has_phy) 1195 phy_stop(dev->phydev); 1196 del_timer_sync(&priv->rx_timeout); 1197 1198 /* mask all interrupts */ 1199 enet_writel(priv, 0, ENET_IRMASK_REG); 1200 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); 1201 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); 1202 1203 /* make sure no mib update is scheduled */ 1204 cancel_work_sync(&priv->mib_update_task); 1205 1206 /* disable dma & mac */ 1207 bcm_enet_disable_dma(priv, priv->tx_chan); 1208 bcm_enet_disable_dma(priv, priv->rx_chan); 1209 bcm_enet_disable_mac(priv); 1210 1211 /* force reclaim of all tx buffers */ 1212 bcm_enet_tx_reclaim(dev, 1); 1213 1214 /* free the rx skb ring */ 1215 for (i = 0; i < priv->rx_ring_size; i++) { 1216 struct bcm_enet_desc *desc; 1217 1218 if (!priv->rx_skb[i]) 1219 continue; 1220 1221 desc = &priv->rx_desc_cpu[i]; 1222 dma_unmap_single(kdev, desc->address, priv->rx_skb_size, 1223 DMA_FROM_DEVICE); 1224 kfree_skb(priv->rx_skb[i]); 1225 } 1226 1227 /* free remaining allocated memory */ 1228 kfree(priv->rx_skb); 1229 kfree(priv->tx_skb); 1230 dma_free_coherent(kdev, priv->rx_desc_alloc_size, 1231 priv->rx_desc_cpu, priv->rx_desc_dma); 1232 dma_free_coherent(kdev, priv->tx_desc_alloc_size, 1233 priv->tx_desc_cpu, priv->tx_desc_dma); 1234 free_irq(priv->irq_tx, dev); 1235 free_irq(priv->irq_rx, dev); 1236 free_irq(dev->irq, dev); 1237 1238 /* release phy */ 1239 if (priv->has_phy) 1240 phy_disconnect(dev->phydev); 1241 1242 return 0; 1243 } 1244 1245 /* 1246 * ethtool callbacks 1247 */ 1248 struct bcm_enet_stats { 1249 char stat_string[ETH_GSTRING_LEN]; 1250 int sizeof_stat; 1251 int stat_offset; 1252 int mib_reg; 1253 }; 1254 1255 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \ 1256 offsetof(struct bcm_enet_priv, m) 1257 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \ 1258 offsetof(struct net_device_stats, m) 1259 1260 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = { 1261 { "rx_packets", DEV_STAT(rx_packets), -1 }, 1262 { "tx_packets", DEV_STAT(tx_packets), -1 }, 1263 { "rx_bytes", DEV_STAT(rx_bytes), -1 }, 1264 { "tx_bytes", DEV_STAT(tx_bytes), -1 }, 1265 { "rx_errors", DEV_STAT(rx_errors), -1 }, 1266 { "tx_errors", DEV_STAT(tx_errors), -1 }, 1267 { "rx_dropped", DEV_STAT(rx_dropped), -1 }, 1268 { "tx_dropped", DEV_STAT(tx_dropped), -1 }, 1269 1270 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS}, 1271 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS }, 1272 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST }, 1273 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT }, 1274 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 }, 1275 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 }, 1276 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 }, 1277 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 }, 1278 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 }, 1279 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX }, 1280 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB }, 1281 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR }, 1282 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG }, 1283 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP }, 1284 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN }, 1285 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND }, 1286 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC }, 1287 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN }, 1288 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM }, 1289 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE }, 1290 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL }, 1291 1292 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS }, 1293 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS }, 1294 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST }, 1295 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT }, 1296 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 }, 1297 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 }, 1298 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 }, 1299 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 }, 1300 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023}, 1301 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX }, 1302 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB }, 1303 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR }, 1304 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG }, 1305 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN }, 1306 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL }, 1307 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL }, 1308 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL }, 1309 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL }, 1310 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE }, 1311 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF }, 1312 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS }, 1313 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE }, 1314 1315 }; 1316 1317 #define BCM_ENET_STATS_LEN ARRAY_SIZE(bcm_enet_gstrings_stats) 1318 1319 static const u32 unused_mib_regs[] = { 1320 ETH_MIB_TX_ALL_OCTETS, 1321 ETH_MIB_TX_ALL_PKTS, 1322 ETH_MIB_RX_ALL_OCTETS, 1323 ETH_MIB_RX_ALL_PKTS, 1324 }; 1325 1326 1327 static void bcm_enet_get_drvinfo(struct net_device *netdev, 1328 struct ethtool_drvinfo *drvinfo) 1329 { 1330 strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver)); 1331 strlcpy(drvinfo->version, bcm_enet_driver_version, 1332 sizeof(drvinfo->version)); 1333 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); 1334 strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info)); 1335 } 1336 1337 static int bcm_enet_get_sset_count(struct net_device *netdev, 1338 int string_set) 1339 { 1340 switch (string_set) { 1341 case ETH_SS_STATS: 1342 return BCM_ENET_STATS_LEN; 1343 default: 1344 return -EINVAL; 1345 } 1346 } 1347 1348 static void bcm_enet_get_strings(struct net_device *netdev, 1349 u32 stringset, u8 *data) 1350 { 1351 int i; 1352 1353 switch (stringset) { 1354 case ETH_SS_STATS: 1355 for (i = 0; i < BCM_ENET_STATS_LEN; i++) { 1356 memcpy(data + i * ETH_GSTRING_LEN, 1357 bcm_enet_gstrings_stats[i].stat_string, 1358 ETH_GSTRING_LEN); 1359 } 1360 break; 1361 } 1362 } 1363 1364 static void update_mib_counters(struct bcm_enet_priv *priv) 1365 { 1366 int i; 1367 1368 for (i = 0; i < BCM_ENET_STATS_LEN; i++) { 1369 const struct bcm_enet_stats *s; 1370 u32 val; 1371 char *p; 1372 1373 s = &bcm_enet_gstrings_stats[i]; 1374 if (s->mib_reg == -1) 1375 continue; 1376 1377 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg)); 1378 p = (char *)priv + s->stat_offset; 1379 1380 if (s->sizeof_stat == sizeof(u64)) 1381 *(u64 *)p += val; 1382 else 1383 *(u32 *)p += val; 1384 } 1385 1386 /* also empty unused mib counters to make sure mib counter 1387 * overflow interrupt is cleared */ 1388 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++) 1389 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i])); 1390 } 1391 1392 static void bcm_enet_update_mib_counters_defer(struct work_struct *t) 1393 { 1394 struct bcm_enet_priv *priv; 1395 1396 priv = container_of(t, struct bcm_enet_priv, mib_update_task); 1397 mutex_lock(&priv->mib_update_lock); 1398 update_mib_counters(priv); 1399 mutex_unlock(&priv->mib_update_lock); 1400 1401 /* reenable mib interrupt */ 1402 if (netif_running(priv->net_dev)) 1403 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG); 1404 } 1405 1406 static void bcm_enet_get_ethtool_stats(struct net_device *netdev, 1407 struct ethtool_stats *stats, 1408 u64 *data) 1409 { 1410 struct bcm_enet_priv *priv; 1411 int i; 1412 1413 priv = netdev_priv(netdev); 1414 1415 mutex_lock(&priv->mib_update_lock); 1416 update_mib_counters(priv); 1417 1418 for (i = 0; i < BCM_ENET_STATS_LEN; i++) { 1419 const struct bcm_enet_stats *s; 1420 char *p; 1421 1422 s = &bcm_enet_gstrings_stats[i]; 1423 if (s->mib_reg == -1) 1424 p = (char *)&netdev->stats; 1425 else 1426 p = (char *)priv; 1427 p += s->stat_offset; 1428 data[i] = (s->sizeof_stat == sizeof(u64)) ? 1429 *(u64 *)p : *(u32 *)p; 1430 } 1431 mutex_unlock(&priv->mib_update_lock); 1432 } 1433 1434 static int bcm_enet_nway_reset(struct net_device *dev) 1435 { 1436 struct bcm_enet_priv *priv; 1437 1438 priv = netdev_priv(dev); 1439 if (priv->has_phy) 1440 return phy_ethtool_nway_reset(dev); 1441 1442 return -EOPNOTSUPP; 1443 } 1444 1445 static int bcm_enet_get_link_ksettings(struct net_device *dev, 1446 struct ethtool_link_ksettings *cmd) 1447 { 1448 struct bcm_enet_priv *priv; 1449 u32 supported, advertising; 1450 1451 priv = netdev_priv(dev); 1452 1453 if (priv->has_phy) { 1454 if (!dev->phydev) 1455 return -ENODEV; 1456 1457 phy_ethtool_ksettings_get(dev->phydev, cmd); 1458 1459 return 0; 1460 } else { 1461 cmd->base.autoneg = 0; 1462 cmd->base.speed = (priv->force_speed_100) ? 1463 SPEED_100 : SPEED_10; 1464 cmd->base.duplex = (priv->force_duplex_full) ? 1465 DUPLEX_FULL : DUPLEX_HALF; 1466 supported = ADVERTISED_10baseT_Half | 1467 ADVERTISED_10baseT_Full | 1468 ADVERTISED_100baseT_Half | 1469 ADVERTISED_100baseT_Full; 1470 advertising = 0; 1471 ethtool_convert_legacy_u32_to_link_mode( 1472 cmd->link_modes.supported, supported); 1473 ethtool_convert_legacy_u32_to_link_mode( 1474 cmd->link_modes.advertising, advertising); 1475 cmd->base.port = PORT_MII; 1476 } 1477 return 0; 1478 } 1479 1480 static int bcm_enet_set_link_ksettings(struct net_device *dev, 1481 const struct ethtool_link_ksettings *cmd) 1482 { 1483 struct bcm_enet_priv *priv; 1484 1485 priv = netdev_priv(dev); 1486 if (priv->has_phy) { 1487 if (!dev->phydev) 1488 return -ENODEV; 1489 return phy_ethtool_ksettings_set(dev->phydev, cmd); 1490 } else { 1491 1492 if (cmd->base.autoneg || 1493 (cmd->base.speed != SPEED_100 && 1494 cmd->base.speed != SPEED_10) || 1495 cmd->base.port != PORT_MII) 1496 return -EINVAL; 1497 1498 priv->force_speed_100 = 1499 (cmd->base.speed == SPEED_100) ? 1 : 0; 1500 priv->force_duplex_full = 1501 (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0; 1502 1503 if (netif_running(dev)) 1504 bcm_enet_adjust_link(dev); 1505 return 0; 1506 } 1507 } 1508 1509 static void bcm_enet_get_ringparam(struct net_device *dev, 1510 struct ethtool_ringparam *ering) 1511 { 1512 struct bcm_enet_priv *priv; 1513 1514 priv = netdev_priv(dev); 1515 1516 /* rx/tx ring is actually only limited by memory */ 1517 ering->rx_max_pending = 8192; 1518 ering->tx_max_pending = 8192; 1519 ering->rx_pending = priv->rx_ring_size; 1520 ering->tx_pending = priv->tx_ring_size; 1521 } 1522 1523 static int bcm_enet_set_ringparam(struct net_device *dev, 1524 struct ethtool_ringparam *ering) 1525 { 1526 struct bcm_enet_priv *priv; 1527 int was_running; 1528 1529 priv = netdev_priv(dev); 1530 1531 was_running = 0; 1532 if (netif_running(dev)) { 1533 bcm_enet_stop(dev); 1534 was_running = 1; 1535 } 1536 1537 priv->rx_ring_size = ering->rx_pending; 1538 priv->tx_ring_size = ering->tx_pending; 1539 1540 if (was_running) { 1541 int err; 1542 1543 err = bcm_enet_open(dev); 1544 if (err) 1545 dev_close(dev); 1546 else 1547 bcm_enet_set_multicast_list(dev); 1548 } 1549 return 0; 1550 } 1551 1552 static void bcm_enet_get_pauseparam(struct net_device *dev, 1553 struct ethtool_pauseparam *ecmd) 1554 { 1555 struct bcm_enet_priv *priv; 1556 1557 priv = netdev_priv(dev); 1558 ecmd->autoneg = priv->pause_auto; 1559 ecmd->rx_pause = priv->pause_rx; 1560 ecmd->tx_pause = priv->pause_tx; 1561 } 1562 1563 static int bcm_enet_set_pauseparam(struct net_device *dev, 1564 struct ethtool_pauseparam *ecmd) 1565 { 1566 struct bcm_enet_priv *priv; 1567 1568 priv = netdev_priv(dev); 1569 1570 if (priv->has_phy) { 1571 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) { 1572 /* asymetric pause mode not supported, 1573 * actually possible but integrated PHY has RO 1574 * asym_pause bit */ 1575 return -EINVAL; 1576 } 1577 } else { 1578 /* no pause autoneg on direct mii connection */ 1579 if (ecmd->autoneg) 1580 return -EINVAL; 1581 } 1582 1583 priv->pause_auto = ecmd->autoneg; 1584 priv->pause_rx = ecmd->rx_pause; 1585 priv->pause_tx = ecmd->tx_pause; 1586 1587 return 0; 1588 } 1589 1590 static const struct ethtool_ops bcm_enet_ethtool_ops = { 1591 .get_strings = bcm_enet_get_strings, 1592 .get_sset_count = bcm_enet_get_sset_count, 1593 .get_ethtool_stats = bcm_enet_get_ethtool_stats, 1594 .nway_reset = bcm_enet_nway_reset, 1595 .get_drvinfo = bcm_enet_get_drvinfo, 1596 .get_link = ethtool_op_get_link, 1597 .get_ringparam = bcm_enet_get_ringparam, 1598 .set_ringparam = bcm_enet_set_ringparam, 1599 .get_pauseparam = bcm_enet_get_pauseparam, 1600 .set_pauseparam = bcm_enet_set_pauseparam, 1601 .get_link_ksettings = bcm_enet_get_link_ksettings, 1602 .set_link_ksettings = bcm_enet_set_link_ksettings, 1603 }; 1604 1605 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1606 { 1607 struct bcm_enet_priv *priv; 1608 1609 priv = netdev_priv(dev); 1610 if (priv->has_phy) { 1611 if (!dev->phydev) 1612 return -ENODEV; 1613 return phy_mii_ioctl(dev->phydev, rq, cmd); 1614 } else { 1615 struct mii_if_info mii; 1616 1617 mii.dev = dev; 1618 mii.mdio_read = bcm_enet_mdio_read_mii; 1619 mii.mdio_write = bcm_enet_mdio_write_mii; 1620 mii.phy_id = 0; 1621 mii.phy_id_mask = 0x3f; 1622 mii.reg_num_mask = 0x1f; 1623 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL); 1624 } 1625 } 1626 1627 /* 1628 * adjust mtu, can't be called while device is running 1629 */ 1630 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu) 1631 { 1632 struct bcm_enet_priv *priv = netdev_priv(dev); 1633 int actual_mtu = new_mtu; 1634 1635 if (netif_running(dev)) 1636 return -EBUSY; 1637 1638 /* add ethernet header + vlan tag size */ 1639 actual_mtu += VLAN_ETH_HLEN; 1640 1641 /* 1642 * setup maximum size before we get overflow mark in 1643 * descriptor, note that this will not prevent reception of 1644 * big frames, they will be split into multiple buffers 1645 * anyway 1646 */ 1647 priv->hw_mtu = actual_mtu; 1648 1649 /* 1650 * align rx buffer size to dma burst len, account FCS since 1651 * it's appended 1652 */ 1653 priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN, 1654 priv->dma_maxburst * 4); 1655 1656 dev->mtu = new_mtu; 1657 return 0; 1658 } 1659 1660 /* 1661 * preinit hardware to allow mii operation while device is down 1662 */ 1663 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv) 1664 { 1665 u32 val; 1666 int limit; 1667 1668 /* make sure mac is disabled */ 1669 bcm_enet_disable_mac(priv); 1670 1671 /* soft reset mac */ 1672 val = ENET_CTL_SRESET_MASK; 1673 enet_writel(priv, val, ENET_CTL_REG); 1674 wmb(); 1675 1676 limit = 1000; 1677 do { 1678 val = enet_readl(priv, ENET_CTL_REG); 1679 if (!(val & ENET_CTL_SRESET_MASK)) 1680 break; 1681 udelay(1); 1682 } while (limit--); 1683 1684 /* select correct mii interface */ 1685 val = enet_readl(priv, ENET_CTL_REG); 1686 if (priv->use_external_mii) 1687 val |= ENET_CTL_EPHYSEL_MASK; 1688 else 1689 val &= ~ENET_CTL_EPHYSEL_MASK; 1690 enet_writel(priv, val, ENET_CTL_REG); 1691 1692 /* turn on mdc clock */ 1693 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) | 1694 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG); 1695 1696 /* set mib counters to self-clear when read */ 1697 val = enet_readl(priv, ENET_MIBCTL_REG); 1698 val |= ENET_MIBCTL_RDCLEAR_MASK; 1699 enet_writel(priv, val, ENET_MIBCTL_REG); 1700 } 1701 1702 static const struct net_device_ops bcm_enet_ops = { 1703 .ndo_open = bcm_enet_open, 1704 .ndo_stop = bcm_enet_stop, 1705 .ndo_start_xmit = bcm_enet_start_xmit, 1706 .ndo_set_mac_address = bcm_enet_set_mac_address, 1707 .ndo_set_rx_mode = bcm_enet_set_multicast_list, 1708 .ndo_do_ioctl = bcm_enet_ioctl, 1709 .ndo_change_mtu = bcm_enet_change_mtu, 1710 }; 1711 1712 /* 1713 * allocate netdevice, request register memory and register device. 1714 */ 1715 static int bcm_enet_probe(struct platform_device *pdev) 1716 { 1717 struct bcm_enet_priv *priv; 1718 struct net_device *dev; 1719 struct bcm63xx_enet_platform_data *pd; 1720 struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx; 1721 struct mii_bus *bus; 1722 const char *clk_name; 1723 int i, ret; 1724 1725 if (!bcm_enet_shared_base[0]) 1726 return -EPROBE_DEFER; 1727 1728 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1729 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 1730 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2); 1731 if (!res_irq || !res_irq_rx || !res_irq_tx) 1732 return -ENODEV; 1733 1734 ret = 0; 1735 dev = alloc_etherdev(sizeof(*priv)); 1736 if (!dev) 1737 return -ENOMEM; 1738 priv = netdev_priv(dev); 1739 1740 priv->enet_is_sw = false; 1741 priv->dma_maxburst = BCMENET_DMA_MAXBURST; 1742 1743 ret = bcm_enet_change_mtu(dev, dev->mtu); 1744 if (ret) 1745 goto out; 1746 1747 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1748 priv->base = devm_ioremap_resource(&pdev->dev, res_mem); 1749 if (IS_ERR(priv->base)) { 1750 ret = PTR_ERR(priv->base); 1751 goto out; 1752 } 1753 1754 dev->irq = priv->irq = res_irq->start; 1755 priv->irq_rx = res_irq_rx->start; 1756 priv->irq_tx = res_irq_tx->start; 1757 priv->mac_id = pdev->id; 1758 1759 /* get rx & tx dma channel id for this mac */ 1760 if (priv->mac_id == 0) { 1761 priv->rx_chan = 0; 1762 priv->tx_chan = 1; 1763 clk_name = "enet0"; 1764 } else { 1765 priv->rx_chan = 2; 1766 priv->tx_chan = 3; 1767 clk_name = "enet1"; 1768 } 1769 1770 priv->mac_clk = devm_clk_get(&pdev->dev, clk_name); 1771 if (IS_ERR(priv->mac_clk)) { 1772 ret = PTR_ERR(priv->mac_clk); 1773 goto out; 1774 } 1775 ret = clk_prepare_enable(priv->mac_clk); 1776 if (ret) 1777 goto out; 1778 1779 /* initialize default and fetch platform data */ 1780 priv->rx_ring_size = BCMENET_DEF_RX_DESC; 1781 priv->tx_ring_size = BCMENET_DEF_TX_DESC; 1782 1783 pd = dev_get_platdata(&pdev->dev); 1784 if (pd) { 1785 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); 1786 priv->has_phy = pd->has_phy; 1787 priv->phy_id = pd->phy_id; 1788 priv->has_phy_interrupt = pd->has_phy_interrupt; 1789 priv->phy_interrupt = pd->phy_interrupt; 1790 priv->use_external_mii = !pd->use_internal_phy; 1791 priv->pause_auto = pd->pause_auto; 1792 priv->pause_rx = pd->pause_rx; 1793 priv->pause_tx = pd->pause_tx; 1794 priv->force_duplex_full = pd->force_duplex_full; 1795 priv->force_speed_100 = pd->force_speed_100; 1796 priv->dma_chan_en_mask = pd->dma_chan_en_mask; 1797 priv->dma_chan_int_mask = pd->dma_chan_int_mask; 1798 priv->dma_chan_width = pd->dma_chan_width; 1799 priv->dma_has_sram = pd->dma_has_sram; 1800 priv->dma_desc_shift = pd->dma_desc_shift; 1801 } 1802 1803 if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) { 1804 /* using internal PHY, enable clock */ 1805 priv->phy_clk = devm_clk_get(&pdev->dev, "ephy"); 1806 if (IS_ERR(priv->phy_clk)) { 1807 ret = PTR_ERR(priv->phy_clk); 1808 priv->phy_clk = NULL; 1809 goto out_disable_clk_mac; 1810 } 1811 ret = clk_prepare_enable(priv->phy_clk); 1812 if (ret) 1813 goto out_disable_clk_mac; 1814 } 1815 1816 /* do minimal hardware init to be able to probe mii bus */ 1817 bcm_enet_hw_preinit(priv); 1818 1819 /* MII bus registration */ 1820 if (priv->has_phy) { 1821 1822 priv->mii_bus = mdiobus_alloc(); 1823 if (!priv->mii_bus) { 1824 ret = -ENOMEM; 1825 goto out_uninit_hw; 1826 } 1827 1828 bus = priv->mii_bus; 1829 bus->name = "bcm63xx_enet MII bus"; 1830 bus->parent = &pdev->dev; 1831 bus->priv = priv; 1832 bus->read = bcm_enet_mdio_read_phylib; 1833 bus->write = bcm_enet_mdio_write_phylib; 1834 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id); 1835 1836 /* only probe bus where we think the PHY is, because 1837 * the mdio read operation return 0 instead of 0xffff 1838 * if a slave is not present on hw */ 1839 bus->phy_mask = ~(1 << priv->phy_id); 1840 1841 if (priv->has_phy_interrupt) 1842 bus->irq[priv->phy_id] = priv->phy_interrupt; 1843 1844 ret = mdiobus_register(bus); 1845 if (ret) { 1846 dev_err(&pdev->dev, "unable to register mdio bus\n"); 1847 goto out_free_mdio; 1848 } 1849 } else { 1850 1851 /* run platform code to initialize PHY device */ 1852 if (pd && pd->mii_config && 1853 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii, 1854 bcm_enet_mdio_write_mii)) { 1855 dev_err(&pdev->dev, "unable to configure mdio bus\n"); 1856 goto out_uninit_hw; 1857 } 1858 } 1859 1860 spin_lock_init(&priv->rx_lock); 1861 1862 /* init rx timeout (used for oom) */ 1863 setup_timer(&priv->rx_timeout, bcm_enet_refill_rx_timer, 1864 (unsigned long)dev); 1865 1866 /* init the mib update lock&work */ 1867 mutex_init(&priv->mib_update_lock); 1868 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer); 1869 1870 /* zero mib counters */ 1871 for (i = 0; i < ENET_MIB_REG_COUNT; i++) 1872 enet_writel(priv, 0, ENET_MIB_REG(i)); 1873 1874 /* register netdevice */ 1875 dev->netdev_ops = &bcm_enet_ops; 1876 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); 1877 1878 dev->ethtool_ops = &bcm_enet_ethtool_ops; 1879 /* MTU range: 46 - 2028 */ 1880 dev->min_mtu = ETH_ZLEN - ETH_HLEN; 1881 dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN; 1882 SET_NETDEV_DEV(dev, &pdev->dev); 1883 1884 ret = register_netdev(dev); 1885 if (ret) 1886 goto out_unregister_mdio; 1887 1888 netif_carrier_off(dev); 1889 platform_set_drvdata(pdev, dev); 1890 priv->pdev = pdev; 1891 priv->net_dev = dev; 1892 1893 return 0; 1894 1895 out_unregister_mdio: 1896 if (priv->mii_bus) 1897 mdiobus_unregister(priv->mii_bus); 1898 1899 out_free_mdio: 1900 if (priv->mii_bus) 1901 mdiobus_free(priv->mii_bus); 1902 1903 out_uninit_hw: 1904 /* turn off mdc clock */ 1905 enet_writel(priv, 0, ENET_MIISC_REG); 1906 clk_disable_unprepare(priv->phy_clk); 1907 1908 out_disable_clk_mac: 1909 clk_disable_unprepare(priv->mac_clk); 1910 out: 1911 free_netdev(dev); 1912 return ret; 1913 } 1914 1915 1916 /* 1917 * exit func, stops hardware and unregisters netdevice 1918 */ 1919 static int bcm_enet_remove(struct platform_device *pdev) 1920 { 1921 struct bcm_enet_priv *priv; 1922 struct net_device *dev; 1923 1924 /* stop netdevice */ 1925 dev = platform_get_drvdata(pdev); 1926 priv = netdev_priv(dev); 1927 unregister_netdev(dev); 1928 1929 /* turn off mdc clock */ 1930 enet_writel(priv, 0, ENET_MIISC_REG); 1931 1932 if (priv->has_phy) { 1933 mdiobus_unregister(priv->mii_bus); 1934 mdiobus_free(priv->mii_bus); 1935 } else { 1936 struct bcm63xx_enet_platform_data *pd; 1937 1938 pd = dev_get_platdata(&pdev->dev); 1939 if (pd && pd->mii_config) 1940 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii, 1941 bcm_enet_mdio_write_mii); 1942 } 1943 1944 /* disable hw block clocks */ 1945 clk_disable_unprepare(priv->phy_clk); 1946 clk_disable_unprepare(priv->mac_clk); 1947 1948 free_netdev(dev); 1949 return 0; 1950 } 1951 1952 struct platform_driver bcm63xx_enet_driver = { 1953 .probe = bcm_enet_probe, 1954 .remove = bcm_enet_remove, 1955 .driver = { 1956 .name = "bcm63xx_enet", 1957 .owner = THIS_MODULE, 1958 }, 1959 }; 1960 1961 /* 1962 * switch mii access callbacks 1963 */ 1964 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv, 1965 int ext, int phy_id, int location) 1966 { 1967 u32 reg; 1968 int ret; 1969 1970 spin_lock_bh(&priv->enetsw_mdio_lock); 1971 enetsw_writel(priv, 0, ENETSW_MDIOC_REG); 1972 1973 reg = ENETSW_MDIOC_RD_MASK | 1974 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) | 1975 (location << ENETSW_MDIOC_REG_SHIFT); 1976 1977 if (ext) 1978 reg |= ENETSW_MDIOC_EXT_MASK; 1979 1980 enetsw_writel(priv, reg, ENETSW_MDIOC_REG); 1981 udelay(50); 1982 ret = enetsw_readw(priv, ENETSW_MDIOD_REG); 1983 spin_unlock_bh(&priv->enetsw_mdio_lock); 1984 return ret; 1985 } 1986 1987 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv, 1988 int ext, int phy_id, int location, 1989 uint16_t data) 1990 { 1991 u32 reg; 1992 1993 spin_lock_bh(&priv->enetsw_mdio_lock); 1994 enetsw_writel(priv, 0, ENETSW_MDIOC_REG); 1995 1996 reg = ENETSW_MDIOC_WR_MASK | 1997 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) | 1998 (location << ENETSW_MDIOC_REG_SHIFT); 1999 2000 if (ext) 2001 reg |= ENETSW_MDIOC_EXT_MASK; 2002 2003 reg |= data; 2004 2005 enetsw_writel(priv, reg, ENETSW_MDIOC_REG); 2006 udelay(50); 2007 spin_unlock_bh(&priv->enetsw_mdio_lock); 2008 } 2009 2010 static inline int bcm_enet_port_is_rgmii(int portid) 2011 { 2012 return portid >= ENETSW_RGMII_PORT0; 2013 } 2014 2015 /* 2016 * enet sw PHY polling 2017 */ 2018 static void swphy_poll_timer(unsigned long data) 2019 { 2020 struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data; 2021 unsigned int i; 2022 2023 for (i = 0; i < priv->num_ports; i++) { 2024 struct bcm63xx_enetsw_port *port; 2025 int val, j, up, advertise, lpa, speed, duplex, media; 2026 int external_phy = bcm_enet_port_is_rgmii(i); 2027 u8 override; 2028 2029 port = &priv->used_ports[i]; 2030 if (!port->used) 2031 continue; 2032 2033 if (port->bypass_link) 2034 continue; 2035 2036 /* dummy read to clear */ 2037 for (j = 0; j < 2; j++) 2038 val = bcmenet_sw_mdio_read(priv, external_phy, 2039 port->phy_id, MII_BMSR); 2040 2041 if (val == 0xffff) 2042 continue; 2043 2044 up = (val & BMSR_LSTATUS) ? 1 : 0; 2045 if (!(up ^ priv->sw_port_link[i])) 2046 continue; 2047 2048 priv->sw_port_link[i] = up; 2049 2050 /* link changed */ 2051 if (!up) { 2052 dev_info(&priv->pdev->dev, "link DOWN on %s\n", 2053 port->name); 2054 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK, 2055 ENETSW_PORTOV_REG(i)); 2056 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK | 2057 ENETSW_PTCTRL_TXDIS_MASK, 2058 ENETSW_PTCTRL_REG(i)); 2059 continue; 2060 } 2061 2062 advertise = bcmenet_sw_mdio_read(priv, external_phy, 2063 port->phy_id, MII_ADVERTISE); 2064 2065 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id, 2066 MII_LPA); 2067 2068 /* figure out media and duplex from advertise and LPA values */ 2069 media = mii_nway_result(lpa & advertise); 2070 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 2071 2072 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)) 2073 speed = 100; 2074 else 2075 speed = 10; 2076 2077 if (val & BMSR_ESTATEN) { 2078 advertise = bcmenet_sw_mdio_read(priv, external_phy, 2079 port->phy_id, MII_CTRL1000); 2080 2081 lpa = bcmenet_sw_mdio_read(priv, external_phy, 2082 port->phy_id, MII_STAT1000); 2083 2084 if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF) 2085 && lpa & (LPA_1000FULL | LPA_1000HALF)) { 2086 speed = 1000; 2087 duplex = (lpa & LPA_1000FULL); 2088 } 2089 } 2090 2091 dev_info(&priv->pdev->dev, 2092 "link UP on %s, %dMbps, %s-duplex\n", 2093 port->name, speed, duplex ? "full" : "half"); 2094 2095 override = ENETSW_PORTOV_ENABLE_MASK | 2096 ENETSW_PORTOV_LINKUP_MASK; 2097 2098 if (speed == 1000) 2099 override |= ENETSW_IMPOV_1000_MASK; 2100 else if (speed == 100) 2101 override |= ENETSW_IMPOV_100_MASK; 2102 if (duplex) 2103 override |= ENETSW_IMPOV_FDX_MASK; 2104 2105 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i)); 2106 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i)); 2107 } 2108 2109 priv->swphy_poll.expires = jiffies + HZ; 2110 add_timer(&priv->swphy_poll); 2111 } 2112 2113 /* 2114 * open callback, allocate dma rings & buffers and start rx operation 2115 */ 2116 static int bcm_enetsw_open(struct net_device *dev) 2117 { 2118 struct bcm_enet_priv *priv; 2119 struct device *kdev; 2120 int i, ret; 2121 unsigned int size; 2122 void *p; 2123 u32 val; 2124 2125 priv = netdev_priv(dev); 2126 kdev = &priv->pdev->dev; 2127 2128 /* mask all interrupts and request them */ 2129 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); 2130 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); 2131 2132 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 2133 0, dev->name, dev); 2134 if (ret) 2135 goto out_freeirq; 2136 2137 if (priv->irq_tx != -1) { 2138 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma, 2139 0, dev->name, dev); 2140 if (ret) 2141 goto out_freeirq_rx; 2142 } 2143 2144 /* allocate rx dma ring */ 2145 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc); 2146 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL); 2147 if (!p) { 2148 dev_err(kdev, "cannot allocate rx ring %u\n", size); 2149 ret = -ENOMEM; 2150 goto out_freeirq_tx; 2151 } 2152 2153 memset(p, 0, size); 2154 priv->rx_desc_alloc_size = size; 2155 priv->rx_desc_cpu = p; 2156 2157 /* allocate tx dma ring */ 2158 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc); 2159 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL); 2160 if (!p) { 2161 dev_err(kdev, "cannot allocate tx ring\n"); 2162 ret = -ENOMEM; 2163 goto out_free_rx_ring; 2164 } 2165 2166 memset(p, 0, size); 2167 priv->tx_desc_alloc_size = size; 2168 priv->tx_desc_cpu = p; 2169 2170 priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size, 2171 GFP_KERNEL); 2172 if (!priv->tx_skb) { 2173 dev_err(kdev, "cannot allocate rx skb queue\n"); 2174 ret = -ENOMEM; 2175 goto out_free_tx_ring; 2176 } 2177 2178 priv->tx_desc_count = priv->tx_ring_size; 2179 priv->tx_dirty_desc = 0; 2180 priv->tx_curr_desc = 0; 2181 spin_lock_init(&priv->tx_lock); 2182 2183 /* init & fill rx ring with skbs */ 2184 priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size, 2185 GFP_KERNEL); 2186 if (!priv->rx_skb) { 2187 dev_err(kdev, "cannot allocate rx skb queue\n"); 2188 ret = -ENOMEM; 2189 goto out_free_tx_skb; 2190 } 2191 2192 priv->rx_desc_count = 0; 2193 priv->rx_dirty_desc = 0; 2194 priv->rx_curr_desc = 0; 2195 2196 /* disable all ports */ 2197 for (i = 0; i < priv->num_ports; i++) { 2198 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK, 2199 ENETSW_PORTOV_REG(i)); 2200 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK | 2201 ENETSW_PTCTRL_TXDIS_MASK, 2202 ENETSW_PTCTRL_REG(i)); 2203 2204 priv->sw_port_link[i] = 0; 2205 } 2206 2207 /* reset mib */ 2208 val = enetsw_readb(priv, ENETSW_GMCR_REG); 2209 val |= ENETSW_GMCR_RST_MIB_MASK; 2210 enetsw_writeb(priv, val, ENETSW_GMCR_REG); 2211 mdelay(1); 2212 val &= ~ENETSW_GMCR_RST_MIB_MASK; 2213 enetsw_writeb(priv, val, ENETSW_GMCR_REG); 2214 mdelay(1); 2215 2216 /* force CPU port state */ 2217 val = enetsw_readb(priv, ENETSW_IMPOV_REG); 2218 val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK; 2219 enetsw_writeb(priv, val, ENETSW_IMPOV_REG); 2220 2221 /* enable switch forward engine */ 2222 val = enetsw_readb(priv, ENETSW_SWMODE_REG); 2223 val |= ENETSW_SWMODE_FWD_EN_MASK; 2224 enetsw_writeb(priv, val, ENETSW_SWMODE_REG); 2225 2226 /* enable jumbo on all ports */ 2227 enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG); 2228 enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG); 2229 2230 /* initialize flow control buffer allocation */ 2231 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, 2232 ENETDMA_BUFALLOC_REG(priv->rx_chan)); 2233 2234 if (bcm_enet_refill_rx(dev)) { 2235 dev_err(kdev, "cannot allocate rx skb queue\n"); 2236 ret = -ENOMEM; 2237 goto out; 2238 } 2239 2240 /* write rx & tx ring addresses */ 2241 enet_dmas_writel(priv, priv->rx_desc_dma, 2242 ENETDMAS_RSTART_REG, priv->rx_chan); 2243 enet_dmas_writel(priv, priv->tx_desc_dma, 2244 ENETDMAS_RSTART_REG, priv->tx_chan); 2245 2246 /* clear remaining state ram for rx & tx channel */ 2247 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan); 2248 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan); 2249 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan); 2250 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan); 2251 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan); 2252 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan); 2253 2254 /* set dma maximum burst len */ 2255 enet_dmac_writel(priv, priv->dma_maxburst, 2256 ENETDMAC_MAXBURST, priv->rx_chan); 2257 enet_dmac_writel(priv, priv->dma_maxburst, 2258 ENETDMAC_MAXBURST, priv->tx_chan); 2259 2260 /* set flow control low/high threshold to 1/3 / 2/3 */ 2261 val = priv->rx_ring_size / 3; 2262 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan)); 2263 val = (priv->rx_ring_size * 2) / 3; 2264 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan)); 2265 2266 /* all set, enable mac and interrupts, start dma engine and 2267 * kick rx dma channel 2268 */ 2269 wmb(); 2270 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG); 2271 enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK, 2272 ENETDMAC_CHANCFG, priv->rx_chan); 2273 2274 /* watch "packet transferred" interrupt in rx and tx */ 2275 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK, 2276 ENETDMAC_IR, priv->rx_chan); 2277 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK, 2278 ENETDMAC_IR, priv->tx_chan); 2279 2280 /* make sure we enable napi before rx interrupt */ 2281 napi_enable(&priv->napi); 2282 2283 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK, 2284 ENETDMAC_IRMASK, priv->rx_chan); 2285 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK, 2286 ENETDMAC_IRMASK, priv->tx_chan); 2287 2288 netif_carrier_on(dev); 2289 netif_start_queue(dev); 2290 2291 /* apply override config for bypass_link ports here. */ 2292 for (i = 0; i < priv->num_ports; i++) { 2293 struct bcm63xx_enetsw_port *port; 2294 u8 override; 2295 port = &priv->used_ports[i]; 2296 if (!port->used) 2297 continue; 2298 2299 if (!port->bypass_link) 2300 continue; 2301 2302 override = ENETSW_PORTOV_ENABLE_MASK | 2303 ENETSW_PORTOV_LINKUP_MASK; 2304 2305 switch (port->force_speed) { 2306 case 1000: 2307 override |= ENETSW_IMPOV_1000_MASK; 2308 break; 2309 case 100: 2310 override |= ENETSW_IMPOV_100_MASK; 2311 break; 2312 case 10: 2313 break; 2314 default: 2315 pr_warn("invalid forced speed on port %s: assume 10\n", 2316 port->name); 2317 break; 2318 } 2319 2320 if (port->force_duplex_full) 2321 override |= ENETSW_IMPOV_FDX_MASK; 2322 2323 2324 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i)); 2325 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i)); 2326 } 2327 2328 /* start phy polling timer */ 2329 setup_timer(&priv->swphy_poll, swphy_poll_timer, (unsigned long)priv); 2330 mod_timer(&priv->swphy_poll, jiffies); 2331 return 0; 2332 2333 out: 2334 for (i = 0; i < priv->rx_ring_size; i++) { 2335 struct bcm_enet_desc *desc; 2336 2337 if (!priv->rx_skb[i]) 2338 continue; 2339 2340 desc = &priv->rx_desc_cpu[i]; 2341 dma_unmap_single(kdev, desc->address, priv->rx_skb_size, 2342 DMA_FROM_DEVICE); 2343 kfree_skb(priv->rx_skb[i]); 2344 } 2345 kfree(priv->rx_skb); 2346 2347 out_free_tx_skb: 2348 kfree(priv->tx_skb); 2349 2350 out_free_tx_ring: 2351 dma_free_coherent(kdev, priv->tx_desc_alloc_size, 2352 priv->tx_desc_cpu, priv->tx_desc_dma); 2353 2354 out_free_rx_ring: 2355 dma_free_coherent(kdev, priv->rx_desc_alloc_size, 2356 priv->rx_desc_cpu, priv->rx_desc_dma); 2357 2358 out_freeirq_tx: 2359 if (priv->irq_tx != -1) 2360 free_irq(priv->irq_tx, dev); 2361 2362 out_freeirq_rx: 2363 free_irq(priv->irq_rx, dev); 2364 2365 out_freeirq: 2366 return ret; 2367 } 2368 2369 /* stop callback */ 2370 static int bcm_enetsw_stop(struct net_device *dev) 2371 { 2372 struct bcm_enet_priv *priv; 2373 struct device *kdev; 2374 int i; 2375 2376 priv = netdev_priv(dev); 2377 kdev = &priv->pdev->dev; 2378 2379 del_timer_sync(&priv->swphy_poll); 2380 netif_stop_queue(dev); 2381 napi_disable(&priv->napi); 2382 del_timer_sync(&priv->rx_timeout); 2383 2384 /* mask all interrupts */ 2385 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan); 2386 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan); 2387 2388 /* disable dma & mac */ 2389 bcm_enet_disable_dma(priv, priv->tx_chan); 2390 bcm_enet_disable_dma(priv, priv->rx_chan); 2391 2392 /* force reclaim of all tx buffers */ 2393 bcm_enet_tx_reclaim(dev, 1); 2394 2395 /* free the rx skb ring */ 2396 for (i = 0; i < priv->rx_ring_size; i++) { 2397 struct bcm_enet_desc *desc; 2398 2399 if (!priv->rx_skb[i]) 2400 continue; 2401 2402 desc = &priv->rx_desc_cpu[i]; 2403 dma_unmap_single(kdev, desc->address, priv->rx_skb_size, 2404 DMA_FROM_DEVICE); 2405 kfree_skb(priv->rx_skb[i]); 2406 } 2407 2408 /* free remaining allocated memory */ 2409 kfree(priv->rx_skb); 2410 kfree(priv->tx_skb); 2411 dma_free_coherent(kdev, priv->rx_desc_alloc_size, 2412 priv->rx_desc_cpu, priv->rx_desc_dma); 2413 dma_free_coherent(kdev, priv->tx_desc_alloc_size, 2414 priv->tx_desc_cpu, priv->tx_desc_dma); 2415 if (priv->irq_tx != -1) 2416 free_irq(priv->irq_tx, dev); 2417 free_irq(priv->irq_rx, dev); 2418 2419 return 0; 2420 } 2421 2422 /* try to sort out phy external status by walking the used_port field 2423 * in the bcm_enet_priv structure. in case the phy address is not 2424 * assigned to any physical port on the switch, assume it is external 2425 * (and yell at the user). 2426 */ 2427 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id) 2428 { 2429 int i; 2430 2431 for (i = 0; i < priv->num_ports; ++i) { 2432 if (!priv->used_ports[i].used) 2433 continue; 2434 if (priv->used_ports[i].phy_id == phy_id) 2435 return bcm_enet_port_is_rgmii(i); 2436 } 2437 2438 printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n", 2439 phy_id); 2440 return 1; 2441 } 2442 2443 /* can't use bcmenet_sw_mdio_read directly as we need to sort out 2444 * external/internal status of the given phy_id first. 2445 */ 2446 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id, 2447 int location) 2448 { 2449 struct bcm_enet_priv *priv; 2450 2451 priv = netdev_priv(dev); 2452 return bcmenet_sw_mdio_read(priv, 2453 bcm_enetsw_phy_is_external(priv, phy_id), 2454 phy_id, location); 2455 } 2456 2457 /* can't use bcmenet_sw_mdio_write directly as we need to sort out 2458 * external/internal status of the given phy_id first. 2459 */ 2460 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id, 2461 int location, 2462 int val) 2463 { 2464 struct bcm_enet_priv *priv; 2465 2466 priv = netdev_priv(dev); 2467 bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id), 2468 phy_id, location, val); 2469 } 2470 2471 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2472 { 2473 struct mii_if_info mii; 2474 2475 mii.dev = dev; 2476 mii.mdio_read = bcm_enetsw_mii_mdio_read; 2477 mii.mdio_write = bcm_enetsw_mii_mdio_write; 2478 mii.phy_id = 0; 2479 mii.phy_id_mask = 0x3f; 2480 mii.reg_num_mask = 0x1f; 2481 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL); 2482 2483 } 2484 2485 static const struct net_device_ops bcm_enetsw_ops = { 2486 .ndo_open = bcm_enetsw_open, 2487 .ndo_stop = bcm_enetsw_stop, 2488 .ndo_start_xmit = bcm_enet_start_xmit, 2489 .ndo_change_mtu = bcm_enet_change_mtu, 2490 .ndo_do_ioctl = bcm_enetsw_ioctl, 2491 }; 2492 2493 2494 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = { 2495 { "rx_packets", DEV_STAT(rx_packets), -1 }, 2496 { "tx_packets", DEV_STAT(tx_packets), -1 }, 2497 { "rx_bytes", DEV_STAT(rx_bytes), -1 }, 2498 { "tx_bytes", DEV_STAT(tx_bytes), -1 }, 2499 { "rx_errors", DEV_STAT(rx_errors), -1 }, 2500 { "tx_errors", DEV_STAT(tx_errors), -1 }, 2501 { "rx_dropped", DEV_STAT(rx_dropped), -1 }, 2502 { "tx_dropped", DEV_STAT(tx_dropped), -1 }, 2503 2504 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT }, 2505 { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST }, 2506 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST }, 2507 { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT }, 2508 { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 }, 2509 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 }, 2510 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 }, 2511 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 }, 2512 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023}, 2513 { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max), 2514 ETHSW_MIB_RX_1024_1522 }, 2515 { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047), 2516 ETHSW_MIB_RX_1523_2047 }, 2517 { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095), 2518 ETHSW_MIB_RX_2048_4095 }, 2519 { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191), 2520 ETHSW_MIB_RX_4096_8191 }, 2521 { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728), 2522 ETHSW_MIB_RX_8192_9728 }, 2523 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR }, 2524 { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC }, 2525 { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP }, 2526 { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND }, 2527 { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE }, 2528 2529 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT }, 2530 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST }, 2531 { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT }, 2532 { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT }, 2533 { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE }, 2534 { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS }, 2535 2536 }; 2537 2538 #define BCM_ENETSW_STATS_LEN \ 2539 (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats)) 2540 2541 static void bcm_enetsw_get_strings(struct net_device *netdev, 2542 u32 stringset, u8 *data) 2543 { 2544 int i; 2545 2546 switch (stringset) { 2547 case ETH_SS_STATS: 2548 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) { 2549 memcpy(data + i * ETH_GSTRING_LEN, 2550 bcm_enetsw_gstrings_stats[i].stat_string, 2551 ETH_GSTRING_LEN); 2552 } 2553 break; 2554 } 2555 } 2556 2557 static int bcm_enetsw_get_sset_count(struct net_device *netdev, 2558 int string_set) 2559 { 2560 switch (string_set) { 2561 case ETH_SS_STATS: 2562 return BCM_ENETSW_STATS_LEN; 2563 default: 2564 return -EINVAL; 2565 } 2566 } 2567 2568 static void bcm_enetsw_get_drvinfo(struct net_device *netdev, 2569 struct ethtool_drvinfo *drvinfo) 2570 { 2571 strncpy(drvinfo->driver, bcm_enet_driver_name, 32); 2572 strncpy(drvinfo->version, bcm_enet_driver_version, 32); 2573 strncpy(drvinfo->fw_version, "N/A", 32); 2574 strncpy(drvinfo->bus_info, "bcm63xx", 32); 2575 } 2576 2577 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev, 2578 struct ethtool_stats *stats, 2579 u64 *data) 2580 { 2581 struct bcm_enet_priv *priv; 2582 int i; 2583 2584 priv = netdev_priv(netdev); 2585 2586 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) { 2587 const struct bcm_enet_stats *s; 2588 u32 lo, hi; 2589 char *p; 2590 int reg; 2591 2592 s = &bcm_enetsw_gstrings_stats[i]; 2593 2594 reg = s->mib_reg; 2595 if (reg == -1) 2596 continue; 2597 2598 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg)); 2599 p = (char *)priv + s->stat_offset; 2600 2601 if (s->sizeof_stat == sizeof(u64)) { 2602 hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1)); 2603 *(u64 *)p = ((u64)hi << 32 | lo); 2604 } else { 2605 *(u32 *)p = lo; 2606 } 2607 } 2608 2609 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) { 2610 const struct bcm_enet_stats *s; 2611 char *p; 2612 2613 s = &bcm_enetsw_gstrings_stats[i]; 2614 2615 if (s->mib_reg == -1) 2616 p = (char *)&netdev->stats + s->stat_offset; 2617 else 2618 p = (char *)priv + s->stat_offset; 2619 2620 data[i] = (s->sizeof_stat == sizeof(u64)) ? 2621 *(u64 *)p : *(u32 *)p; 2622 } 2623 } 2624 2625 static void bcm_enetsw_get_ringparam(struct net_device *dev, 2626 struct ethtool_ringparam *ering) 2627 { 2628 struct bcm_enet_priv *priv; 2629 2630 priv = netdev_priv(dev); 2631 2632 /* rx/tx ring is actually only limited by memory */ 2633 ering->rx_max_pending = 8192; 2634 ering->tx_max_pending = 8192; 2635 ering->rx_mini_max_pending = 0; 2636 ering->rx_jumbo_max_pending = 0; 2637 ering->rx_pending = priv->rx_ring_size; 2638 ering->tx_pending = priv->tx_ring_size; 2639 } 2640 2641 static int bcm_enetsw_set_ringparam(struct net_device *dev, 2642 struct ethtool_ringparam *ering) 2643 { 2644 struct bcm_enet_priv *priv; 2645 int was_running; 2646 2647 priv = netdev_priv(dev); 2648 2649 was_running = 0; 2650 if (netif_running(dev)) { 2651 bcm_enetsw_stop(dev); 2652 was_running = 1; 2653 } 2654 2655 priv->rx_ring_size = ering->rx_pending; 2656 priv->tx_ring_size = ering->tx_pending; 2657 2658 if (was_running) { 2659 int err; 2660 2661 err = bcm_enetsw_open(dev); 2662 if (err) 2663 dev_close(dev); 2664 } 2665 return 0; 2666 } 2667 2668 static const struct ethtool_ops bcm_enetsw_ethtool_ops = { 2669 .get_strings = bcm_enetsw_get_strings, 2670 .get_sset_count = bcm_enetsw_get_sset_count, 2671 .get_ethtool_stats = bcm_enetsw_get_ethtool_stats, 2672 .get_drvinfo = bcm_enetsw_get_drvinfo, 2673 .get_ringparam = bcm_enetsw_get_ringparam, 2674 .set_ringparam = bcm_enetsw_set_ringparam, 2675 }; 2676 2677 /* allocate netdevice, request register memory and register device. */ 2678 static int bcm_enetsw_probe(struct platform_device *pdev) 2679 { 2680 struct bcm_enet_priv *priv; 2681 struct net_device *dev; 2682 struct bcm63xx_enetsw_platform_data *pd; 2683 struct resource *res_mem; 2684 int ret, irq_rx, irq_tx; 2685 2686 if (!bcm_enet_shared_base[0]) 2687 return -EPROBE_DEFER; 2688 2689 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2690 irq_rx = platform_get_irq(pdev, 0); 2691 irq_tx = platform_get_irq(pdev, 1); 2692 if (!res_mem || irq_rx < 0) 2693 return -ENODEV; 2694 2695 ret = 0; 2696 dev = alloc_etherdev(sizeof(*priv)); 2697 if (!dev) 2698 return -ENOMEM; 2699 priv = netdev_priv(dev); 2700 memset(priv, 0, sizeof(*priv)); 2701 2702 /* initialize default and fetch platform data */ 2703 priv->enet_is_sw = true; 2704 priv->irq_rx = irq_rx; 2705 priv->irq_tx = irq_tx; 2706 priv->rx_ring_size = BCMENET_DEF_RX_DESC; 2707 priv->tx_ring_size = BCMENET_DEF_TX_DESC; 2708 priv->dma_maxburst = BCMENETSW_DMA_MAXBURST; 2709 2710 pd = dev_get_platdata(&pdev->dev); 2711 if (pd) { 2712 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); 2713 memcpy(priv->used_ports, pd->used_ports, 2714 sizeof(pd->used_ports)); 2715 priv->num_ports = pd->num_ports; 2716 priv->dma_has_sram = pd->dma_has_sram; 2717 priv->dma_chan_en_mask = pd->dma_chan_en_mask; 2718 priv->dma_chan_int_mask = pd->dma_chan_int_mask; 2719 priv->dma_chan_width = pd->dma_chan_width; 2720 } 2721 2722 ret = bcm_enet_change_mtu(dev, dev->mtu); 2723 if (ret) 2724 goto out; 2725 2726 priv->base = devm_ioremap_resource(&pdev->dev, res_mem); 2727 if (IS_ERR(priv->base)) { 2728 ret = PTR_ERR(priv->base); 2729 goto out; 2730 } 2731 2732 priv->mac_clk = devm_clk_get(&pdev->dev, "enetsw"); 2733 if (IS_ERR(priv->mac_clk)) { 2734 ret = PTR_ERR(priv->mac_clk); 2735 goto out; 2736 } 2737 ret = clk_prepare_enable(priv->mac_clk); 2738 if (ret) 2739 goto out; 2740 2741 priv->rx_chan = 0; 2742 priv->tx_chan = 1; 2743 spin_lock_init(&priv->rx_lock); 2744 2745 /* init rx timeout (used for oom) */ 2746 init_timer(&priv->rx_timeout); 2747 priv->rx_timeout.function = bcm_enet_refill_rx_timer; 2748 priv->rx_timeout.data = (unsigned long)dev; 2749 2750 /* register netdevice */ 2751 dev->netdev_ops = &bcm_enetsw_ops; 2752 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); 2753 dev->ethtool_ops = &bcm_enetsw_ethtool_ops; 2754 SET_NETDEV_DEV(dev, &pdev->dev); 2755 2756 spin_lock_init(&priv->enetsw_mdio_lock); 2757 2758 ret = register_netdev(dev); 2759 if (ret) 2760 goto out_disable_clk; 2761 2762 netif_carrier_off(dev); 2763 platform_set_drvdata(pdev, dev); 2764 priv->pdev = pdev; 2765 priv->net_dev = dev; 2766 2767 return 0; 2768 2769 out_disable_clk: 2770 clk_disable_unprepare(priv->mac_clk); 2771 out: 2772 free_netdev(dev); 2773 return ret; 2774 } 2775 2776 2777 /* exit func, stops hardware and unregisters netdevice */ 2778 static int bcm_enetsw_remove(struct platform_device *pdev) 2779 { 2780 struct bcm_enet_priv *priv; 2781 struct net_device *dev; 2782 2783 /* stop netdevice */ 2784 dev = platform_get_drvdata(pdev); 2785 priv = netdev_priv(dev); 2786 unregister_netdev(dev); 2787 2788 clk_disable_unprepare(priv->mac_clk); 2789 2790 free_netdev(dev); 2791 return 0; 2792 } 2793 2794 struct platform_driver bcm63xx_enetsw_driver = { 2795 .probe = bcm_enetsw_probe, 2796 .remove = bcm_enetsw_remove, 2797 .driver = { 2798 .name = "bcm63xx_enetsw", 2799 .owner = THIS_MODULE, 2800 }, 2801 }; 2802 2803 /* reserve & remap memory space shared between all macs */ 2804 static int bcm_enet_shared_probe(struct platform_device *pdev) 2805 { 2806 struct resource *res; 2807 void __iomem *p[3]; 2808 unsigned int i; 2809 2810 memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base)); 2811 2812 for (i = 0; i < 3; i++) { 2813 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 2814 p[i] = devm_ioremap_resource(&pdev->dev, res); 2815 if (IS_ERR(p[i])) 2816 return PTR_ERR(p[i]); 2817 } 2818 2819 memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base)); 2820 2821 return 0; 2822 } 2823 2824 static int bcm_enet_shared_remove(struct platform_device *pdev) 2825 { 2826 return 0; 2827 } 2828 2829 /* this "shared" driver is needed because both macs share a single 2830 * address space 2831 */ 2832 struct platform_driver bcm63xx_enet_shared_driver = { 2833 .probe = bcm_enet_shared_probe, 2834 .remove = bcm_enet_shared_remove, 2835 .driver = { 2836 .name = "bcm63xx_enet_shared", 2837 .owner = THIS_MODULE, 2838 }, 2839 }; 2840 2841 static struct platform_driver * const drivers[] = { 2842 &bcm63xx_enet_shared_driver, 2843 &bcm63xx_enet_driver, 2844 &bcm63xx_enetsw_driver, 2845 }; 2846 2847 /* entry point */ 2848 static int __init bcm_enet_init(void) 2849 { 2850 return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 2851 } 2852 2853 static void __exit bcm_enet_exit(void) 2854 { 2855 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 2856 } 2857 2858 2859 module_init(bcm_enet_init); 2860 module_exit(bcm_enet_exit); 2861 2862 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver"); 2863 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); 2864 MODULE_LICENSE("GPL"); 2865