1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/etherdevice.h> 8 #include <linux/if_vlan.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_net.h> 13 #include <linux/platform_device.h> 14 #include <linux/slab.h> 15 #include <linux/string.h> 16 17 #include "bcm4908_enet.h" 18 #include "unimac.h" 19 20 #define ENET_DMA_CH_RX_CFG ENET_DMA_CH0_CFG 21 #define ENET_DMA_CH_TX_CFG ENET_DMA_CH1_CFG 22 #define ENET_DMA_CH_RX_STATE_RAM ENET_DMA_CH0_STATE_RAM 23 #define ENET_DMA_CH_TX_STATE_RAM ENET_DMA_CH1_STATE_RAM 24 25 #define ENET_TX_BDS_NUM 200 26 #define ENET_RX_BDS_NUM 200 27 #define ENET_RX_BDS_NUM_MAX 8192 28 29 #define ENET_DMA_INT_DEFAULTS (ENET_DMA_CH_CFG_INT_DONE | \ 30 ENET_DMA_CH_CFG_INT_NO_DESC | \ 31 ENET_DMA_CH_CFG_INT_BUFF_DONE) 32 #define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */ 33 34 #define ENET_MTU_MAX ETH_DATA_LEN /* Is it possible to support 2044? */ 35 #define BRCM_MAX_TAG_LEN 6 36 #define ENET_MAX_ETH_OVERHEAD (ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \ 37 ETH_FCS_LEN + 4) /* 32 */ 38 39 struct bcm4908_enet_dma_ring_bd { 40 __le32 ctl; 41 __le32 addr; 42 } __packed; 43 44 struct bcm4908_enet_dma_ring_slot { 45 struct sk_buff *skb; 46 unsigned int len; 47 dma_addr_t dma_addr; 48 }; 49 50 struct bcm4908_enet_dma_ring { 51 int is_tx; 52 int read_idx; 53 int write_idx; 54 int length; 55 u16 cfg_block; 56 u16 st_ram_block; 57 struct napi_struct napi; 58 59 union { 60 void *cpu_addr; 61 struct bcm4908_enet_dma_ring_bd *buf_desc; 62 }; 63 dma_addr_t dma_addr; 64 65 struct bcm4908_enet_dma_ring_slot *slots; 66 }; 67 68 struct bcm4908_enet { 69 struct device *dev; 70 struct net_device *netdev; 71 void __iomem *base; 72 int irq_tx; 73 74 struct bcm4908_enet_dma_ring tx_ring; 75 struct bcm4908_enet_dma_ring rx_ring; 76 }; 77 78 /*** 79 * R/W ops 80 */ 81 82 static u32 enet_read(struct bcm4908_enet *enet, u16 offset) 83 { 84 return readl(enet->base + offset); 85 } 86 87 static void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value) 88 { 89 writel(value, enet->base + offset); 90 } 91 92 static void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set) 93 { 94 u32 val; 95 96 WARN_ON(set & ~mask); 97 98 val = enet_read(enet, offset); 99 val = (val & ~mask) | (set & mask); 100 enet_write(enet, offset, val); 101 } 102 103 static void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set) 104 { 105 enet_maskset(enet, offset, set, set); 106 } 107 108 static u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset) 109 { 110 return enet_read(enet, ENET_UNIMAC + offset); 111 } 112 113 static void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value) 114 { 115 enet_write(enet, ENET_UNIMAC + offset, value); 116 } 117 118 static void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set) 119 { 120 enet_set(enet, ENET_UNIMAC + offset, set); 121 } 122 123 /*** 124 * Helpers 125 */ 126 127 static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu) 128 { 129 enet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD); 130 } 131 132 /*** 133 * DMA ring ops 134 */ 135 136 static void bcm4908_enet_dma_ring_intrs_on(struct bcm4908_enet *enet, 137 struct bcm4908_enet_dma_ring *ring) 138 { 139 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS); 140 } 141 142 static void bcm4908_enet_dma_ring_intrs_off(struct bcm4908_enet *enet, 143 struct bcm4908_enet_dma_ring *ring) 144 { 145 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0); 146 } 147 148 static void bcm4908_enet_dma_ring_intrs_ack(struct bcm4908_enet *enet, 149 struct bcm4908_enet_dma_ring *ring) 150 { 151 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS); 152 } 153 154 /*** 155 * DMA 156 */ 157 158 static int bcm4908_dma_alloc_buf_descs(struct bcm4908_enet *enet, 159 struct bcm4908_enet_dma_ring *ring) 160 { 161 int size = ring->length * sizeof(struct bcm4908_enet_dma_ring_bd); 162 struct device *dev = enet->dev; 163 164 ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL); 165 if (!ring->cpu_addr) 166 return -ENOMEM; 167 168 if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) { 169 dev_err(dev, "Invalid DMA ring alignment\n"); 170 goto err_free_buf_descs; 171 } 172 173 ring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL); 174 if (!ring->slots) 175 goto err_free_buf_descs; 176 177 ring->read_idx = 0; 178 ring->write_idx = 0; 179 180 return 0; 181 182 err_free_buf_descs: 183 dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr); 184 return -ENOMEM; 185 } 186 187 static void bcm4908_enet_dma_free(struct bcm4908_enet *enet) 188 { 189 struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring; 190 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 191 struct device *dev = enet->dev; 192 int size; 193 194 size = rx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd); 195 if (rx_ring->cpu_addr) 196 dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr); 197 kfree(rx_ring->slots); 198 199 size = tx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd); 200 if (tx_ring->cpu_addr) 201 dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr); 202 kfree(tx_ring->slots); 203 } 204 205 static int bcm4908_enet_dma_alloc(struct bcm4908_enet *enet) 206 { 207 struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring; 208 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 209 struct device *dev = enet->dev; 210 int err; 211 212 tx_ring->length = ENET_TX_BDS_NUM; 213 tx_ring->is_tx = 1; 214 tx_ring->cfg_block = ENET_DMA_CH_TX_CFG; 215 tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM; 216 err = bcm4908_dma_alloc_buf_descs(enet, tx_ring); 217 if (err) { 218 dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err); 219 return err; 220 } 221 222 rx_ring->length = ENET_RX_BDS_NUM; 223 rx_ring->is_tx = 0; 224 rx_ring->cfg_block = ENET_DMA_CH_RX_CFG; 225 rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM; 226 err = bcm4908_dma_alloc_buf_descs(enet, rx_ring); 227 if (err) { 228 dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err); 229 bcm4908_enet_dma_free(enet); 230 return err; 231 } 232 233 return 0; 234 } 235 236 static void bcm4908_enet_dma_reset(struct bcm4908_enet *enet) 237 { 238 struct bcm4908_enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring }; 239 int i; 240 241 /* Disable the DMA controller and channel */ 242 for (i = 0; i < ARRAY_SIZE(rings); i++) 243 enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0); 244 enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0); 245 246 /* Reset channels state */ 247 for (i = 0; i < ARRAY_SIZE(rings); i++) { 248 struct bcm4908_enet_dma_ring *ring = rings[i]; 249 250 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0); 251 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0); 252 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0); 253 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0); 254 } 255 } 256 257 static int bcm4908_enet_dma_alloc_rx_buf(struct bcm4908_enet *enet, unsigned int idx) 258 { 259 struct bcm4908_enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx]; 260 struct bcm4908_enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx]; 261 struct device *dev = enet->dev; 262 u32 tmp; 263 int err; 264 265 slot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD; 266 267 slot->skb = netdev_alloc_skb(enet->netdev, slot->len); 268 if (!slot->skb) 269 return -ENOMEM; 270 271 slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE); 272 err = dma_mapping_error(dev, slot->dma_addr); 273 if (err) { 274 dev_err(dev, "Failed to map DMA buffer: %d\n", err); 275 kfree_skb(slot->skb); 276 slot->skb = NULL; 277 return err; 278 } 279 280 tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; 281 tmp |= DMA_CTL_STATUS_OWN; 282 if (idx == enet->rx_ring.length - 1) 283 tmp |= DMA_CTL_STATUS_WRAP; 284 buf_desc->ctl = cpu_to_le32(tmp); 285 buf_desc->addr = cpu_to_le32(slot->dma_addr); 286 287 return 0; 288 } 289 290 static void bcm4908_enet_dma_ring_init(struct bcm4908_enet *enet, 291 struct bcm4908_enet_dma_ring *ring) 292 { 293 int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */ 294 int reset_subch = ring->is_tx ? 1 : 0; 295 296 /* Reset the DMA channel */ 297 enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch)); 298 enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0); 299 300 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0); 301 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN); 302 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0); 303 304 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 305 (uint32_t)ring->dma_addr); 306 } 307 308 static void bcm4908_enet_dma_uninit(struct bcm4908_enet *enet) 309 { 310 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 311 struct bcm4908_enet_dma_ring_slot *slot; 312 struct device *dev = enet->dev; 313 int i; 314 315 for (i = rx_ring->length - 1; i >= 0; i--) { 316 slot = &rx_ring->slots[i]; 317 if (!slot->skb) 318 continue; 319 dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE); 320 kfree_skb(slot->skb); 321 slot->skb = NULL; 322 } 323 } 324 325 static int bcm4908_enet_dma_init(struct bcm4908_enet *enet) 326 { 327 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 328 struct device *dev = enet->dev; 329 int err; 330 int i; 331 332 for (i = 0; i < rx_ring->length; i++) { 333 err = bcm4908_enet_dma_alloc_rx_buf(enet, i); 334 if (err) { 335 dev_err(dev, "Failed to alloc RX buffer: %d\n", err); 336 bcm4908_enet_dma_uninit(enet); 337 return err; 338 } 339 } 340 341 bcm4908_enet_dma_ring_init(enet, &enet->tx_ring); 342 bcm4908_enet_dma_ring_init(enet, &enet->rx_ring); 343 344 return 0; 345 } 346 347 static void bcm4908_enet_dma_tx_ring_enable(struct bcm4908_enet *enet, 348 struct bcm4908_enet_dma_ring *ring) 349 { 350 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); 351 } 352 353 static void bcm4908_enet_dma_tx_ring_disable(struct bcm4908_enet *enet, 354 struct bcm4908_enet_dma_ring *ring) 355 { 356 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0); 357 } 358 359 static void bcm4908_enet_dma_rx_ring_enable(struct bcm4908_enet *enet, 360 struct bcm4908_enet_dma_ring *ring) 361 { 362 enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); 363 } 364 365 static void bcm4908_enet_dma_rx_ring_disable(struct bcm4908_enet *enet, 366 struct bcm4908_enet_dma_ring *ring) 367 { 368 unsigned long deadline; 369 u32 tmp; 370 371 enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0); 372 373 deadline = jiffies + usecs_to_jiffies(2000); 374 do { 375 tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG); 376 if (!(tmp & ENET_DMA_CH_CFG_ENABLE)) 377 return; 378 enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0); 379 usleep_range(10, 30); 380 } while (!time_after_eq(jiffies, deadline)); 381 382 dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n"); 383 } 384 385 /*** 386 * Ethernet driver 387 */ 388 389 static void bcm4908_enet_gmac_init(struct bcm4908_enet *enet) 390 { 391 u32 cmd; 392 393 bcm4908_enet_set_mtu(enet, enet->netdev->mtu); 394 395 cmd = enet_umac_read(enet, UMAC_CMD); 396 enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET); 397 enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET); 398 399 enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH); 400 enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0); 401 402 enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB); 403 enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0); 404 405 cmd = enet_umac_read(enet, UMAC_CMD); 406 cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT); 407 cmd &= ~CMD_TX_EN; 408 cmd &= ~CMD_RX_EN; 409 cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT; 410 enet_umac_write(enet, UMAC_CMD, cmd); 411 412 enet_maskset(enet, ENET_GMAC_STATUS, 413 ENET_GMAC_STATUS_ETH_SPEED_MASK | 414 ENET_GMAC_STATUS_HD | 415 ENET_GMAC_STATUS_AUTO_CFG_EN | 416 ENET_GMAC_STATUS_LINK_UP, 417 ENET_GMAC_STATUS_ETH_SPEED_1000 | 418 ENET_GMAC_STATUS_AUTO_CFG_EN | 419 ENET_GMAC_STATUS_LINK_UP); 420 } 421 422 static irqreturn_t bcm4908_enet_irq_handler(int irq, void *dev_id) 423 { 424 struct bcm4908_enet *enet = dev_id; 425 struct bcm4908_enet_dma_ring *ring; 426 427 ring = (irq == enet->irq_tx) ? &enet->tx_ring : &enet->rx_ring; 428 429 bcm4908_enet_dma_ring_intrs_off(enet, ring); 430 bcm4908_enet_dma_ring_intrs_ack(enet, ring); 431 432 napi_schedule(&ring->napi); 433 434 return IRQ_HANDLED; 435 } 436 437 static int bcm4908_enet_open(struct net_device *netdev) 438 { 439 struct bcm4908_enet *enet = netdev_priv(netdev); 440 struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring; 441 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 442 struct device *dev = enet->dev; 443 int err; 444 445 err = request_irq(netdev->irq, bcm4908_enet_irq_handler, 0, "enet", enet); 446 if (err) { 447 dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err); 448 return err; 449 } 450 451 if (enet->irq_tx > 0) { 452 err = request_irq(enet->irq_tx, bcm4908_enet_irq_handler, 0, 453 "tx", enet); 454 if (err) { 455 dev_err(dev, "Failed to request IRQ %d: %d\n", 456 enet->irq_tx, err); 457 free_irq(netdev->irq, enet); 458 return err; 459 } 460 } 461 462 bcm4908_enet_gmac_init(enet); 463 bcm4908_enet_dma_reset(enet); 464 bcm4908_enet_dma_init(enet); 465 466 enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN); 467 468 enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN); 469 enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0); 470 471 if (enet->irq_tx > 0) { 472 napi_enable(&tx_ring->napi); 473 bcm4908_enet_dma_ring_intrs_ack(enet, tx_ring); 474 bcm4908_enet_dma_ring_intrs_on(enet, tx_ring); 475 } 476 477 bcm4908_enet_dma_rx_ring_enable(enet, rx_ring); 478 napi_enable(&rx_ring->napi); 479 netif_carrier_on(netdev); 480 netif_start_queue(netdev); 481 bcm4908_enet_dma_ring_intrs_ack(enet, rx_ring); 482 bcm4908_enet_dma_ring_intrs_on(enet, rx_ring); 483 484 return 0; 485 } 486 487 static int bcm4908_enet_stop(struct net_device *netdev) 488 { 489 struct bcm4908_enet *enet = netdev_priv(netdev); 490 struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring; 491 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 492 493 netif_stop_queue(netdev); 494 netif_carrier_off(netdev); 495 napi_disable(&rx_ring->napi); 496 napi_disable(&tx_ring->napi); 497 498 bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring); 499 bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring); 500 501 bcm4908_enet_dma_uninit(enet); 502 503 free_irq(enet->irq_tx, enet); 504 free_irq(enet->netdev->irq, enet); 505 506 return 0; 507 } 508 509 static int bcm4908_enet_start_xmit(struct sk_buff *skb, struct net_device *netdev) 510 { 511 struct bcm4908_enet *enet = netdev_priv(netdev); 512 struct bcm4908_enet_dma_ring *ring = &enet->tx_ring; 513 struct bcm4908_enet_dma_ring_slot *slot; 514 struct device *dev = enet->dev; 515 struct bcm4908_enet_dma_ring_bd *buf_desc; 516 int free_buf_descs; 517 u32 tmp; 518 519 /* Free transmitted skbs */ 520 if (enet->irq_tx < 0 && 521 !(le32_to_cpu(ring->buf_desc[ring->read_idx].ctl) & DMA_CTL_STATUS_OWN)) 522 napi_schedule(&enet->tx_ring.napi); 523 524 /* Don't use the last empty buf descriptor */ 525 if (ring->read_idx <= ring->write_idx) 526 free_buf_descs = ring->read_idx - ring->write_idx + ring->length; 527 else 528 free_buf_descs = ring->read_idx - ring->write_idx; 529 if (free_buf_descs < 2) { 530 netif_stop_queue(netdev); 531 return NETDEV_TX_BUSY; 532 } 533 534 /* Hardware removes OWN bit after sending data */ 535 buf_desc = &ring->buf_desc[ring->write_idx]; 536 if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) { 537 netif_stop_queue(netdev); 538 return NETDEV_TX_BUSY; 539 } 540 541 slot = &ring->slots[ring->write_idx]; 542 slot->skb = skb; 543 slot->len = skb->len; 544 slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE); 545 if (unlikely(dma_mapping_error(dev, slot->dma_addr))) 546 return NETDEV_TX_BUSY; 547 548 tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; 549 tmp |= DMA_CTL_STATUS_OWN; 550 tmp |= DMA_CTL_STATUS_SOP; 551 tmp |= DMA_CTL_STATUS_EOP; 552 tmp |= DMA_CTL_STATUS_APPEND_CRC; 553 if (ring->write_idx + 1 == ring->length - 1) 554 tmp |= DMA_CTL_STATUS_WRAP; 555 556 buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr); 557 buf_desc->ctl = cpu_to_le32(tmp); 558 559 bcm4908_enet_dma_tx_ring_enable(enet, &enet->tx_ring); 560 561 if (++ring->write_idx == ring->length - 1) 562 ring->write_idx = 0; 563 enet->netdev->stats.tx_bytes += skb->len; 564 enet->netdev->stats.tx_packets++; 565 566 return NETDEV_TX_OK; 567 } 568 569 static int bcm4908_enet_poll_rx(struct napi_struct *napi, int weight) 570 { 571 struct bcm4908_enet_dma_ring *rx_ring = container_of(napi, struct bcm4908_enet_dma_ring, napi); 572 struct bcm4908_enet *enet = container_of(rx_ring, struct bcm4908_enet, rx_ring); 573 struct device *dev = enet->dev; 574 int handled = 0; 575 576 while (handled < weight) { 577 struct bcm4908_enet_dma_ring_bd *buf_desc; 578 struct bcm4908_enet_dma_ring_slot slot; 579 u32 ctl; 580 int len; 581 int err; 582 583 buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx]; 584 ctl = le32_to_cpu(buf_desc->ctl); 585 if (ctl & DMA_CTL_STATUS_OWN) 586 break; 587 588 slot = enet->rx_ring.slots[enet->rx_ring.read_idx]; 589 590 /* Provide new buffer before unpinning the old one */ 591 err = bcm4908_enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx); 592 if (err) 593 break; 594 595 if (++enet->rx_ring.read_idx == enet->rx_ring.length) 596 enet->rx_ring.read_idx = 0; 597 598 len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; 599 600 if (len < ETH_ZLEN || 601 (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) { 602 kfree_skb(slot.skb); 603 enet->netdev->stats.rx_dropped++; 604 break; 605 } 606 607 dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE); 608 609 skb_put(slot.skb, len - ETH_FCS_LEN); 610 slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev); 611 netif_receive_skb(slot.skb); 612 613 enet->netdev->stats.rx_packets++; 614 enet->netdev->stats.rx_bytes += len; 615 616 handled++; 617 } 618 619 if (handled < weight) { 620 napi_complete_done(napi, handled); 621 bcm4908_enet_dma_ring_intrs_on(enet, rx_ring); 622 } 623 624 /* Hardware could disable ring if it run out of descriptors */ 625 bcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring); 626 627 return handled; 628 } 629 630 static int bcm4908_enet_poll_tx(struct napi_struct *napi, int weight) 631 { 632 struct bcm4908_enet_dma_ring *tx_ring = container_of(napi, struct bcm4908_enet_dma_ring, napi); 633 struct bcm4908_enet *enet = container_of(tx_ring, struct bcm4908_enet, tx_ring); 634 struct bcm4908_enet_dma_ring_bd *buf_desc; 635 struct bcm4908_enet_dma_ring_slot *slot; 636 struct device *dev = enet->dev; 637 unsigned int bytes = 0; 638 int handled = 0; 639 640 while (handled < weight && tx_ring->read_idx != tx_ring->write_idx) { 641 buf_desc = &tx_ring->buf_desc[tx_ring->read_idx]; 642 if (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN) 643 break; 644 slot = &tx_ring->slots[tx_ring->read_idx]; 645 646 dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE); 647 dev_kfree_skb(slot->skb); 648 bytes += slot->len; 649 if (++tx_ring->read_idx == tx_ring->length) 650 tx_ring->read_idx = 0; 651 652 handled++; 653 } 654 655 if (handled < weight) { 656 napi_complete_done(napi, handled); 657 bcm4908_enet_dma_ring_intrs_on(enet, tx_ring); 658 } 659 660 if (netif_queue_stopped(enet->netdev)) 661 netif_wake_queue(enet->netdev); 662 663 return handled; 664 } 665 666 static int bcm4908_enet_change_mtu(struct net_device *netdev, int new_mtu) 667 { 668 struct bcm4908_enet *enet = netdev_priv(netdev); 669 670 bcm4908_enet_set_mtu(enet, new_mtu); 671 672 return 0; 673 } 674 675 static const struct net_device_ops bcm4908_enet_netdev_ops = { 676 .ndo_open = bcm4908_enet_open, 677 .ndo_stop = bcm4908_enet_stop, 678 .ndo_start_xmit = bcm4908_enet_start_xmit, 679 .ndo_set_mac_address = eth_mac_addr, 680 .ndo_change_mtu = bcm4908_enet_change_mtu, 681 }; 682 683 static int bcm4908_enet_probe(struct platform_device *pdev) 684 { 685 struct device *dev = &pdev->dev; 686 struct net_device *netdev; 687 struct bcm4908_enet *enet; 688 const u8 *mac; 689 int err; 690 691 netdev = devm_alloc_etherdev(dev, sizeof(*enet)); 692 if (!netdev) 693 return -ENOMEM; 694 695 enet = netdev_priv(netdev); 696 enet->dev = dev; 697 enet->netdev = netdev; 698 699 enet->base = devm_platform_ioremap_resource(pdev, 0); 700 if (IS_ERR(enet->base)) { 701 dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base)); 702 return PTR_ERR(enet->base); 703 } 704 705 netdev->irq = platform_get_irq_byname(pdev, "rx"); 706 if (netdev->irq < 0) 707 return netdev->irq; 708 709 enet->irq_tx = platform_get_irq_byname(pdev, "tx"); 710 711 dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 712 713 err = bcm4908_enet_dma_alloc(enet); 714 if (err) 715 return err; 716 717 SET_NETDEV_DEV(netdev, &pdev->dev); 718 mac = of_get_mac_address(dev->of_node); 719 if (!IS_ERR(mac)) 720 ether_addr_copy(netdev->dev_addr, mac); 721 else 722 eth_hw_addr_random(netdev); 723 netdev->netdev_ops = &bcm4908_enet_netdev_ops; 724 netdev->min_mtu = ETH_ZLEN; 725 netdev->mtu = ETH_DATA_LEN; 726 netdev->max_mtu = ENET_MTU_MAX; 727 netif_tx_napi_add(netdev, &enet->tx_ring.napi, bcm4908_enet_poll_tx, NAPI_POLL_WEIGHT); 728 netif_napi_add(netdev, &enet->rx_ring.napi, bcm4908_enet_poll_rx, NAPI_POLL_WEIGHT); 729 730 err = register_netdev(netdev); 731 if (err) { 732 bcm4908_enet_dma_free(enet); 733 return err; 734 } 735 736 platform_set_drvdata(pdev, enet); 737 738 return 0; 739 } 740 741 static int bcm4908_enet_remove(struct platform_device *pdev) 742 { 743 struct bcm4908_enet *enet = platform_get_drvdata(pdev); 744 745 unregister_netdev(enet->netdev); 746 netif_napi_del(&enet->rx_ring.napi); 747 netif_napi_del(&enet->tx_ring.napi); 748 bcm4908_enet_dma_free(enet); 749 750 return 0; 751 } 752 753 static const struct of_device_id bcm4908_enet_of_match[] = { 754 { .compatible = "brcm,bcm4908-enet"}, 755 {}, 756 }; 757 758 static struct platform_driver bcm4908_enet_driver = { 759 .driver = { 760 .name = "bcm4908_enet", 761 .of_match_table = bcm4908_enet_of_match, 762 }, 763 .probe = bcm4908_enet_probe, 764 .remove = bcm4908_enet_remove, 765 }; 766 module_platform_driver(bcm4908_enet_driver); 767 768 MODULE_LICENSE("GPL v2"); 769 MODULE_DEVICE_TABLE(of, bcm4908_enet_of_match); 770