1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/etherdevice.h> 8 #include <linux/if_vlan.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/slab.h> 14 #include <linux/string.h> 15 16 #include "bcm4908_enet.h" 17 #include "unimac.h" 18 19 #define ENET_DMA_CH_RX_CFG ENET_DMA_CH0_CFG 20 #define ENET_DMA_CH_TX_CFG ENET_DMA_CH1_CFG 21 #define ENET_DMA_CH_RX_STATE_RAM ENET_DMA_CH0_STATE_RAM 22 #define ENET_DMA_CH_TX_STATE_RAM ENET_DMA_CH1_STATE_RAM 23 24 #define ENET_TX_BDS_NUM 200 25 #define ENET_RX_BDS_NUM 200 26 #define ENET_RX_BDS_NUM_MAX 8192 27 28 #define ENET_DMA_INT_DEFAULTS (ENET_DMA_CH_CFG_INT_DONE | \ 29 ENET_DMA_CH_CFG_INT_NO_DESC | \ 30 ENET_DMA_CH_CFG_INT_BUFF_DONE) 31 #define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */ 32 33 #define ENET_MTU_MAX ETH_DATA_LEN /* Is it possible to support 2044? */ 34 #define BRCM_MAX_TAG_LEN 6 35 #define ENET_MAX_ETH_OVERHEAD (ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \ 36 ETH_FCS_LEN + 4) /* 32 */ 37 38 struct bcm4908_enet_dma_ring_bd { 39 __le32 ctl; 40 __le32 addr; 41 } __packed; 42 43 struct bcm4908_enet_dma_ring_slot { 44 struct sk_buff *skb; 45 unsigned int len; 46 dma_addr_t dma_addr; 47 }; 48 49 struct bcm4908_enet_dma_ring { 50 int is_tx; 51 int read_idx; 52 int write_idx; 53 int length; 54 u16 cfg_block; 55 u16 st_ram_block; 56 57 union { 58 void *cpu_addr; 59 struct bcm4908_enet_dma_ring_bd *buf_desc; 60 }; 61 dma_addr_t dma_addr; 62 63 struct bcm4908_enet_dma_ring_slot *slots; 64 }; 65 66 struct bcm4908_enet { 67 struct device *dev; 68 struct net_device *netdev; 69 struct napi_struct napi; 70 void __iomem *base; 71 72 struct bcm4908_enet_dma_ring tx_ring; 73 struct bcm4908_enet_dma_ring rx_ring; 74 }; 75 76 /*** 77 * R/W ops 78 */ 79 80 static u32 enet_read(struct bcm4908_enet *enet, u16 offset) 81 { 82 return readl(enet->base + offset); 83 } 84 85 static void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value) 86 { 87 writel(value, enet->base + offset); 88 } 89 90 static void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set) 91 { 92 u32 val; 93 94 WARN_ON(set & ~mask); 95 96 val = enet_read(enet, offset); 97 val = (val & ~mask) | (set & mask); 98 enet_write(enet, offset, val); 99 } 100 101 static void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set) 102 { 103 enet_maskset(enet, offset, set, set); 104 } 105 106 static u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset) 107 { 108 return enet_read(enet, ENET_UNIMAC + offset); 109 } 110 111 static void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value) 112 { 113 enet_write(enet, ENET_UNIMAC + offset, value); 114 } 115 116 static void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set) 117 { 118 enet_set(enet, ENET_UNIMAC + offset, set); 119 } 120 121 /*** 122 * Helpers 123 */ 124 125 static void bcm4908_enet_intrs_on(struct bcm4908_enet *enet) 126 { 127 enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS); 128 } 129 130 static void bcm4908_enet_intrs_off(struct bcm4908_enet *enet) 131 { 132 enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0); 133 } 134 135 static void bcm4908_enet_intrs_ack(struct bcm4908_enet *enet) 136 { 137 enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS); 138 } 139 140 static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu) 141 { 142 enet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD); 143 } 144 145 /*** 146 * DMA 147 */ 148 149 static int bcm4908_dma_alloc_buf_descs(struct bcm4908_enet *enet, 150 struct bcm4908_enet_dma_ring *ring) 151 { 152 int size = ring->length * sizeof(struct bcm4908_enet_dma_ring_bd); 153 struct device *dev = enet->dev; 154 155 ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL); 156 if (!ring->cpu_addr) 157 return -ENOMEM; 158 159 if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) { 160 dev_err(dev, "Invalid DMA ring alignment\n"); 161 goto err_free_buf_descs; 162 } 163 164 ring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL); 165 if (!ring->slots) 166 goto err_free_buf_descs; 167 168 ring->read_idx = 0; 169 ring->write_idx = 0; 170 171 return 0; 172 173 err_free_buf_descs: 174 dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr); 175 return -ENOMEM; 176 } 177 178 static void bcm4908_enet_dma_free(struct bcm4908_enet *enet) 179 { 180 struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring; 181 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 182 struct device *dev = enet->dev; 183 int size; 184 185 size = rx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd); 186 if (rx_ring->cpu_addr) 187 dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr); 188 kfree(rx_ring->slots); 189 190 size = tx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd); 191 if (tx_ring->cpu_addr) 192 dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr); 193 kfree(tx_ring->slots); 194 } 195 196 static int bcm4908_enet_dma_alloc(struct bcm4908_enet *enet) 197 { 198 struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring; 199 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 200 struct device *dev = enet->dev; 201 int err; 202 203 tx_ring->length = ENET_TX_BDS_NUM; 204 tx_ring->is_tx = 1; 205 tx_ring->cfg_block = ENET_DMA_CH_TX_CFG; 206 tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM; 207 err = bcm4908_dma_alloc_buf_descs(enet, tx_ring); 208 if (err) { 209 dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err); 210 return err; 211 } 212 213 rx_ring->length = ENET_RX_BDS_NUM; 214 rx_ring->is_tx = 0; 215 rx_ring->cfg_block = ENET_DMA_CH_RX_CFG; 216 rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM; 217 err = bcm4908_dma_alloc_buf_descs(enet, rx_ring); 218 if (err) { 219 dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err); 220 bcm4908_enet_dma_free(enet); 221 return err; 222 } 223 224 return 0; 225 } 226 227 static void bcm4908_enet_dma_reset(struct bcm4908_enet *enet) 228 { 229 struct bcm4908_enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring }; 230 int i; 231 232 /* Disable the DMA controller and channel */ 233 for (i = 0; i < ARRAY_SIZE(rings); i++) 234 enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0); 235 enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0); 236 237 /* Reset channels state */ 238 for (i = 0; i < ARRAY_SIZE(rings); i++) { 239 struct bcm4908_enet_dma_ring *ring = rings[i]; 240 241 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0); 242 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0); 243 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0); 244 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0); 245 } 246 } 247 248 static int bcm4908_enet_dma_alloc_rx_buf(struct bcm4908_enet *enet, unsigned int idx) 249 { 250 struct bcm4908_enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx]; 251 struct bcm4908_enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx]; 252 struct device *dev = enet->dev; 253 u32 tmp; 254 int err; 255 256 slot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD; 257 258 slot->skb = netdev_alloc_skb(enet->netdev, slot->len); 259 if (!slot->skb) 260 return -ENOMEM; 261 262 slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE); 263 err = dma_mapping_error(dev, slot->dma_addr); 264 if (err) { 265 dev_err(dev, "Failed to map DMA buffer: %d\n", err); 266 kfree_skb(slot->skb); 267 slot->skb = NULL; 268 return err; 269 } 270 271 tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; 272 tmp |= DMA_CTL_STATUS_OWN; 273 if (idx == enet->rx_ring.length - 1) 274 tmp |= DMA_CTL_STATUS_WRAP; 275 buf_desc->ctl = cpu_to_le32(tmp); 276 buf_desc->addr = cpu_to_le32(slot->dma_addr); 277 278 return 0; 279 } 280 281 static void bcm4908_enet_dma_ring_init(struct bcm4908_enet *enet, 282 struct bcm4908_enet_dma_ring *ring) 283 { 284 int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */ 285 int reset_subch = ring->is_tx ? 1 : 0; 286 287 /* Reset the DMA channel */ 288 enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch)); 289 enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0); 290 291 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0); 292 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN); 293 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0); 294 295 enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 296 (uint32_t)ring->dma_addr); 297 } 298 299 static void bcm4908_enet_dma_uninit(struct bcm4908_enet *enet) 300 { 301 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 302 struct bcm4908_enet_dma_ring_slot *slot; 303 struct device *dev = enet->dev; 304 int i; 305 306 for (i = rx_ring->length - 1; i >= 0; i--) { 307 slot = &rx_ring->slots[i]; 308 if (!slot->skb) 309 continue; 310 dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE); 311 kfree_skb(slot->skb); 312 slot->skb = NULL; 313 } 314 } 315 316 static int bcm4908_enet_dma_init(struct bcm4908_enet *enet) 317 { 318 struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; 319 struct device *dev = enet->dev; 320 int err; 321 int i; 322 323 for (i = 0; i < rx_ring->length; i++) { 324 err = bcm4908_enet_dma_alloc_rx_buf(enet, i); 325 if (err) { 326 dev_err(dev, "Failed to alloc RX buffer: %d\n", err); 327 bcm4908_enet_dma_uninit(enet); 328 return err; 329 } 330 } 331 332 bcm4908_enet_dma_ring_init(enet, &enet->tx_ring); 333 bcm4908_enet_dma_ring_init(enet, &enet->rx_ring); 334 335 return 0; 336 } 337 338 static void bcm4908_enet_dma_tx_ring_enable(struct bcm4908_enet *enet, 339 struct bcm4908_enet_dma_ring *ring) 340 { 341 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); 342 } 343 344 static void bcm4908_enet_dma_tx_ring_disable(struct bcm4908_enet *enet, 345 struct bcm4908_enet_dma_ring *ring) 346 { 347 enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0); 348 } 349 350 static void bcm4908_enet_dma_rx_ring_enable(struct bcm4908_enet *enet, 351 struct bcm4908_enet_dma_ring *ring) 352 { 353 enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); 354 } 355 356 static void bcm4908_enet_dma_rx_ring_disable(struct bcm4908_enet *enet, 357 struct bcm4908_enet_dma_ring *ring) 358 { 359 unsigned long deadline; 360 u32 tmp; 361 362 enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0); 363 364 deadline = jiffies + usecs_to_jiffies(2000); 365 do { 366 tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG); 367 if (!(tmp & ENET_DMA_CH_CFG_ENABLE)) 368 return; 369 enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0); 370 usleep_range(10, 30); 371 } while (!time_after_eq(jiffies, deadline)); 372 373 dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n"); 374 } 375 376 /*** 377 * Ethernet driver 378 */ 379 380 static void bcm4908_enet_gmac_init(struct bcm4908_enet *enet) 381 { 382 u32 cmd; 383 384 bcm4908_enet_set_mtu(enet, enet->netdev->mtu); 385 386 cmd = enet_umac_read(enet, UMAC_CMD); 387 enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET); 388 enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET); 389 390 enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH); 391 enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0); 392 393 enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB); 394 enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0); 395 396 cmd = enet_umac_read(enet, UMAC_CMD); 397 cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT); 398 cmd &= ~CMD_TX_EN; 399 cmd &= ~CMD_RX_EN; 400 cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT; 401 enet_umac_write(enet, UMAC_CMD, cmd); 402 403 enet_maskset(enet, ENET_GMAC_STATUS, 404 ENET_GMAC_STATUS_ETH_SPEED_MASK | 405 ENET_GMAC_STATUS_HD | 406 ENET_GMAC_STATUS_AUTO_CFG_EN | 407 ENET_GMAC_STATUS_LINK_UP, 408 ENET_GMAC_STATUS_ETH_SPEED_1000 | 409 ENET_GMAC_STATUS_AUTO_CFG_EN | 410 ENET_GMAC_STATUS_LINK_UP); 411 } 412 413 static irqreturn_t bcm4908_enet_irq_handler(int irq, void *dev_id) 414 { 415 struct bcm4908_enet *enet = dev_id; 416 417 bcm4908_enet_intrs_off(enet); 418 bcm4908_enet_intrs_ack(enet); 419 420 napi_schedule(&enet->napi); 421 422 return IRQ_HANDLED; 423 } 424 425 static int bcm4908_enet_open(struct net_device *netdev) 426 { 427 struct bcm4908_enet *enet = netdev_priv(netdev); 428 struct device *dev = enet->dev; 429 int err; 430 431 err = request_irq(netdev->irq, bcm4908_enet_irq_handler, 0, "enet", enet); 432 if (err) { 433 dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err); 434 return err; 435 } 436 437 bcm4908_enet_gmac_init(enet); 438 bcm4908_enet_dma_reset(enet); 439 bcm4908_enet_dma_init(enet); 440 441 enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN); 442 443 enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN); 444 enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0); 445 bcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring); 446 447 napi_enable(&enet->napi); 448 netif_carrier_on(netdev); 449 netif_start_queue(netdev); 450 451 bcm4908_enet_intrs_ack(enet); 452 bcm4908_enet_intrs_on(enet); 453 454 return 0; 455 } 456 457 static int bcm4908_enet_stop(struct net_device *netdev) 458 { 459 struct bcm4908_enet *enet = netdev_priv(netdev); 460 461 netif_stop_queue(netdev); 462 netif_carrier_off(netdev); 463 napi_disable(&enet->napi); 464 465 bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring); 466 bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring); 467 468 bcm4908_enet_dma_uninit(enet); 469 470 free_irq(enet->netdev->irq, enet); 471 472 return 0; 473 } 474 475 static int bcm4908_enet_start_xmit(struct sk_buff *skb, struct net_device *netdev) 476 { 477 struct bcm4908_enet *enet = netdev_priv(netdev); 478 struct bcm4908_enet_dma_ring *ring = &enet->tx_ring; 479 struct bcm4908_enet_dma_ring_slot *slot; 480 struct device *dev = enet->dev; 481 struct bcm4908_enet_dma_ring_bd *buf_desc; 482 int free_buf_descs; 483 u32 tmp; 484 485 /* Free transmitted skbs */ 486 while (ring->read_idx != ring->write_idx) { 487 buf_desc = &ring->buf_desc[ring->read_idx]; 488 if (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN) 489 break; 490 slot = &ring->slots[ring->read_idx]; 491 492 dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE); 493 dev_kfree_skb(slot->skb); 494 if (++ring->read_idx == ring->length) 495 ring->read_idx = 0; 496 } 497 498 /* Don't use the last empty buf descriptor */ 499 if (ring->read_idx <= ring->write_idx) 500 free_buf_descs = ring->read_idx - ring->write_idx + ring->length; 501 else 502 free_buf_descs = ring->read_idx - ring->write_idx; 503 if (free_buf_descs < 2) 504 return NETDEV_TX_BUSY; 505 506 /* Hardware removes OWN bit after sending data */ 507 buf_desc = &ring->buf_desc[ring->write_idx]; 508 if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) { 509 netif_stop_queue(netdev); 510 return NETDEV_TX_BUSY; 511 } 512 513 slot = &ring->slots[ring->write_idx]; 514 slot->skb = skb; 515 slot->len = skb->len; 516 slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE); 517 if (unlikely(dma_mapping_error(dev, slot->dma_addr))) 518 return NETDEV_TX_BUSY; 519 520 tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; 521 tmp |= DMA_CTL_STATUS_OWN; 522 tmp |= DMA_CTL_STATUS_SOP; 523 tmp |= DMA_CTL_STATUS_EOP; 524 tmp |= DMA_CTL_STATUS_APPEND_CRC; 525 if (ring->write_idx + 1 == ring->length - 1) 526 tmp |= DMA_CTL_STATUS_WRAP; 527 528 buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr); 529 buf_desc->ctl = cpu_to_le32(tmp); 530 531 bcm4908_enet_dma_tx_ring_enable(enet, &enet->tx_ring); 532 533 if (++ring->write_idx == ring->length - 1) 534 ring->write_idx = 0; 535 enet->netdev->stats.tx_bytes += skb->len; 536 enet->netdev->stats.tx_packets++; 537 538 return NETDEV_TX_OK; 539 } 540 541 static int bcm4908_enet_poll(struct napi_struct *napi, int weight) 542 { 543 struct bcm4908_enet *enet = container_of(napi, struct bcm4908_enet, napi); 544 struct device *dev = enet->dev; 545 int handled = 0; 546 547 while (handled < weight) { 548 struct bcm4908_enet_dma_ring_bd *buf_desc; 549 struct bcm4908_enet_dma_ring_slot slot; 550 u32 ctl; 551 int len; 552 int err; 553 554 buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx]; 555 ctl = le32_to_cpu(buf_desc->ctl); 556 if (ctl & DMA_CTL_STATUS_OWN) 557 break; 558 559 slot = enet->rx_ring.slots[enet->rx_ring.read_idx]; 560 561 /* Provide new buffer before unpinning the old one */ 562 err = bcm4908_enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx); 563 if (err) 564 break; 565 566 if (++enet->rx_ring.read_idx == enet->rx_ring.length) 567 enet->rx_ring.read_idx = 0; 568 569 len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; 570 571 if (len < ETH_ZLEN || 572 (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) { 573 kfree_skb(slot.skb); 574 enet->netdev->stats.rx_dropped++; 575 break; 576 } 577 578 dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE); 579 580 skb_put(slot.skb, len - ETH_FCS_LEN); 581 slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev); 582 netif_receive_skb(slot.skb); 583 584 enet->netdev->stats.rx_packets++; 585 enet->netdev->stats.rx_bytes += len; 586 587 handled++; 588 } 589 590 if (handled < weight) { 591 napi_complete_done(napi, handled); 592 bcm4908_enet_intrs_on(enet); 593 } 594 595 return handled; 596 } 597 598 static int bcm4908_enet_change_mtu(struct net_device *netdev, int new_mtu) 599 { 600 struct bcm4908_enet *enet = netdev_priv(netdev); 601 602 bcm4908_enet_set_mtu(enet, new_mtu); 603 604 return 0; 605 } 606 607 static const struct net_device_ops bcm4908_enet_netdev_ops = { 608 .ndo_open = bcm4908_enet_open, 609 .ndo_stop = bcm4908_enet_stop, 610 .ndo_start_xmit = bcm4908_enet_start_xmit, 611 .ndo_set_mac_address = eth_mac_addr, 612 .ndo_change_mtu = bcm4908_enet_change_mtu, 613 }; 614 615 static int bcm4908_enet_probe(struct platform_device *pdev) 616 { 617 struct device *dev = &pdev->dev; 618 struct net_device *netdev; 619 struct bcm4908_enet *enet; 620 int err; 621 622 netdev = devm_alloc_etherdev(dev, sizeof(*enet)); 623 if (!netdev) 624 return -ENOMEM; 625 626 enet = netdev_priv(netdev); 627 enet->dev = dev; 628 enet->netdev = netdev; 629 630 enet->base = devm_platform_ioremap_resource(pdev, 0); 631 if (IS_ERR(enet->base)) { 632 dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base)); 633 return PTR_ERR(enet->base); 634 } 635 636 netdev->irq = platform_get_irq_byname(pdev, "rx"); 637 if (netdev->irq < 0) 638 return netdev->irq; 639 640 dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 641 642 err = bcm4908_enet_dma_alloc(enet); 643 if (err) 644 return err; 645 646 SET_NETDEV_DEV(netdev, &pdev->dev); 647 eth_hw_addr_random(netdev); 648 netdev->netdev_ops = &bcm4908_enet_netdev_ops; 649 netdev->min_mtu = ETH_ZLEN; 650 netdev->mtu = ETH_DATA_LEN; 651 netdev->max_mtu = ENET_MTU_MAX; 652 netif_napi_add(netdev, &enet->napi, bcm4908_enet_poll, 64); 653 654 err = register_netdev(netdev); 655 if (err) { 656 bcm4908_enet_dma_free(enet); 657 return err; 658 } 659 660 platform_set_drvdata(pdev, enet); 661 662 return 0; 663 } 664 665 static int bcm4908_enet_remove(struct platform_device *pdev) 666 { 667 struct bcm4908_enet *enet = platform_get_drvdata(pdev); 668 669 unregister_netdev(enet->netdev); 670 netif_napi_del(&enet->napi); 671 bcm4908_enet_dma_free(enet); 672 673 return 0; 674 } 675 676 static const struct of_device_id bcm4908_enet_of_match[] = { 677 { .compatible = "brcm,bcm4908-enet"}, 678 {}, 679 }; 680 681 static struct platform_driver bcm4908_enet_driver = { 682 .driver = { 683 .name = "bcm4908_enet", 684 .of_match_table = bcm4908_enet_of_match, 685 }, 686 .probe = bcm4908_enet_probe, 687 .remove = bcm4908_enet_remove, 688 }; 689 module_platform_driver(bcm4908_enet_driver); 690 691 MODULE_LICENSE("GPL v2"); 692 MODULE_DEVICE_TABLE(of, bcm4908_enet_of_match); 693