1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) "bcmasp_intf: " fmt 3 4 #include <asm/byteorder.h> 5 #include <linux/brcmphy.h> 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/etherdevice.h> 9 #include <linux/netdevice.h> 10 #include <linux/of_net.h> 11 #include <linux/of_mdio.h> 12 #include <linux/phy.h> 13 #include <linux/phy_fixed.h> 14 #include <linux/ptp_classify.h> 15 #include <linux/platform_device.h> 16 #include <net/ip.h> 17 #include <net/ipv6.h> 18 19 #include "bcmasp.h" 20 #include "bcmasp_intf_defs.h" 21 22 static int incr_ring(int index, int ring_count) 23 { 24 index++; 25 if (index == ring_count) 26 return 0; 27 28 return index; 29 } 30 31 /* Points to last byte of descriptor */ 32 static dma_addr_t incr_last_byte(dma_addr_t addr, dma_addr_t beg, 33 int ring_count) 34 { 35 dma_addr_t end = beg + (ring_count * DESC_SIZE); 36 37 addr += DESC_SIZE; 38 if (addr > end) 39 return beg + DESC_SIZE - 1; 40 41 return addr; 42 } 43 44 /* Points to first byte of descriptor */ 45 static dma_addr_t incr_first_byte(dma_addr_t addr, dma_addr_t beg, 46 int ring_count) 47 { 48 dma_addr_t end = beg + (ring_count * DESC_SIZE); 49 50 addr += DESC_SIZE; 51 if (addr >= end) 52 return beg; 53 54 return addr; 55 } 56 57 static void bcmasp_enable_tx(struct bcmasp_intf *intf, int en) 58 { 59 if (en) { 60 tx_spb_ctrl_wl(intf, TX_SPB_CTRL_ENABLE_EN, TX_SPB_CTRL_ENABLE); 61 tx_epkt_core_wl(intf, (TX_EPKT_C_CFG_MISC_EN | 62 TX_EPKT_C_CFG_MISC_PT | 63 (intf->port << TX_EPKT_C_CFG_MISC_PS_SHIFT)), 64 TX_EPKT_C_CFG_MISC); 65 } else { 66 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 67 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 68 } 69 } 70 71 static void bcmasp_enable_rx(struct bcmasp_intf *intf, int en) 72 { 73 if (en) 74 rx_edpkt_cfg_wl(intf, RX_EDPKT_CFG_ENABLE_EN, 75 RX_EDPKT_CFG_ENABLE); 76 else 77 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 78 } 79 80 static void bcmasp_set_rx_mode(struct net_device *dev) 81 { 82 unsigned char mask[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 83 struct bcmasp_intf *intf = netdev_priv(dev); 84 struct netdev_hw_addr *ha; 85 int ret; 86 87 spin_lock_bh(&intf->parent->mda_lock); 88 89 bcmasp_disable_all_filters(intf); 90 91 if (dev->flags & IFF_PROMISC) 92 goto set_promisc; 93 94 bcmasp_set_promisc(intf, 0); 95 96 bcmasp_set_broad(intf, 1); 97 98 bcmasp_set_oaddr(intf, dev->dev_addr, 1); 99 100 if (dev->flags & IFF_ALLMULTI) { 101 bcmasp_set_allmulti(intf, 1); 102 } else { 103 bcmasp_set_allmulti(intf, 0); 104 105 netdev_for_each_mc_addr(ha, dev) { 106 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 107 if (ret) { 108 intf->mib.mc_filters_full_cnt++; 109 goto set_promisc; 110 } 111 } 112 } 113 114 netdev_for_each_uc_addr(ha, dev) { 115 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 116 if (ret) { 117 intf->mib.uc_filters_full_cnt++; 118 goto set_promisc; 119 } 120 } 121 122 spin_unlock_bh(&intf->parent->mda_lock); 123 return; 124 125 set_promisc: 126 bcmasp_set_promisc(intf, 1); 127 intf->mib.promisc_filters_cnt++; 128 129 /* disable all filters used by this port */ 130 bcmasp_disable_all_filters(intf); 131 132 spin_unlock_bh(&intf->parent->mda_lock); 133 } 134 135 static void bcmasp_clean_txcb(struct bcmasp_intf *intf, int index) 136 { 137 struct bcmasp_tx_cb *txcb = &intf->tx_cbs[index]; 138 139 txcb->skb = NULL; 140 dma_unmap_addr_set(txcb, dma_addr, 0); 141 dma_unmap_len_set(txcb, dma_len, 0); 142 txcb->last = false; 143 } 144 145 static int tx_spb_ring_full(struct bcmasp_intf *intf, int cnt) 146 { 147 int next_index, i; 148 149 /* Check if we have enough room for cnt descriptors */ 150 for (i = 0; i < cnt; i++) { 151 next_index = incr_ring(intf->tx_spb_index, DESC_RING_COUNT); 152 if (next_index == intf->tx_spb_clean_index) 153 return 1; 154 } 155 156 return 0; 157 } 158 159 static struct sk_buff *bcmasp_csum_offload(struct net_device *dev, 160 struct sk_buff *skb, 161 bool *csum_hw) 162 { 163 struct bcmasp_intf *intf = netdev_priv(dev); 164 u32 header = 0, header2 = 0, epkt = 0; 165 struct bcmasp_pkt_offload *offload; 166 unsigned int header_cnt = 0; 167 u8 ip_proto; 168 int ret; 169 170 if (skb->ip_summed != CHECKSUM_PARTIAL) 171 return skb; 172 173 ret = skb_cow_head(skb, sizeof(*offload)); 174 if (ret < 0) { 175 intf->mib.tx_realloc_offload_failed++; 176 goto help; 177 } 178 179 switch (skb->protocol) { 180 case htons(ETH_P_IP): 181 header |= PKT_OFFLOAD_HDR_SIZE_2((ip_hdrlen(skb) >> 8) & 0xf); 182 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(ip_hdrlen(skb) & 0xff); 183 epkt |= PKT_OFFLOAD_EPKT_IP(0) | PKT_OFFLOAD_EPKT_CSUM_L2; 184 ip_proto = ip_hdr(skb)->protocol; 185 header_cnt += 2; 186 break; 187 case htons(ETH_P_IPV6): 188 header |= PKT_OFFLOAD_HDR_SIZE_2((IP6_HLEN >> 8) & 0xf); 189 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(IP6_HLEN & 0xff); 190 epkt |= PKT_OFFLOAD_EPKT_IP(1) | PKT_OFFLOAD_EPKT_CSUM_L2; 191 ip_proto = ipv6_hdr(skb)->nexthdr; 192 header_cnt += 2; 193 break; 194 default: 195 goto help; 196 } 197 198 switch (ip_proto) { 199 case IPPROTO_TCP: 200 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(tcp_hdrlen(skb)); 201 epkt |= PKT_OFFLOAD_EPKT_TP(0) | PKT_OFFLOAD_EPKT_CSUM_L3; 202 header_cnt++; 203 break; 204 case IPPROTO_UDP: 205 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(UDP_HLEN); 206 epkt |= PKT_OFFLOAD_EPKT_TP(1) | PKT_OFFLOAD_EPKT_CSUM_L3; 207 header_cnt++; 208 break; 209 default: 210 goto help; 211 } 212 213 offload = (struct bcmasp_pkt_offload *)skb_push(skb, sizeof(*offload)); 214 215 header |= PKT_OFFLOAD_HDR_OP | PKT_OFFLOAD_HDR_COUNT(header_cnt) | 216 PKT_OFFLOAD_HDR_SIZE_1(ETH_HLEN); 217 epkt |= PKT_OFFLOAD_EPKT_OP; 218 219 offload->nop = htonl(PKT_OFFLOAD_NOP); 220 offload->header = htonl(header); 221 offload->header2 = htonl(header2); 222 offload->epkt = htonl(epkt); 223 offload->end = htonl(PKT_OFFLOAD_END_OP); 224 *csum_hw = true; 225 226 return skb; 227 228 help: 229 skb_checksum_help(skb); 230 231 return skb; 232 } 233 234 static unsigned long bcmasp_rx_edpkt_dma_rq(struct bcmasp_intf *intf) 235 { 236 return rx_edpkt_dma_rq(intf, RX_EDPKT_DMA_VALID); 237 } 238 239 static void bcmasp_rx_edpkt_cfg_wq(struct bcmasp_intf *intf, dma_addr_t addr) 240 { 241 rx_edpkt_cfg_wq(intf, addr, RX_EDPKT_RING_BUFFER_READ); 242 } 243 244 static void bcmasp_rx_edpkt_dma_wq(struct bcmasp_intf *intf, dma_addr_t addr) 245 { 246 rx_edpkt_dma_wq(intf, addr, RX_EDPKT_DMA_READ); 247 } 248 249 static unsigned long bcmasp_tx_spb_dma_rq(struct bcmasp_intf *intf) 250 { 251 return tx_spb_dma_rq(intf, TX_SPB_DMA_READ); 252 } 253 254 static void bcmasp_tx_spb_dma_wq(struct bcmasp_intf *intf, dma_addr_t addr) 255 { 256 tx_spb_dma_wq(intf, addr, TX_SPB_DMA_VALID); 257 } 258 259 static const struct bcmasp_intf_ops bcmasp_intf_ops = { 260 .rx_desc_read = bcmasp_rx_edpkt_dma_rq, 261 .rx_buffer_write = bcmasp_rx_edpkt_cfg_wq, 262 .rx_desc_write = bcmasp_rx_edpkt_dma_wq, 263 .tx_read = bcmasp_tx_spb_dma_rq, 264 .tx_write = bcmasp_tx_spb_dma_wq, 265 }; 266 267 static netdev_tx_t bcmasp_xmit(struct sk_buff *skb, struct net_device *dev) 268 { 269 struct bcmasp_intf *intf = netdev_priv(dev); 270 unsigned int total_bytes, size; 271 int spb_index, nr_frags, i, j; 272 struct bcmasp_tx_cb *txcb; 273 dma_addr_t mapping, valid; 274 struct bcmasp_desc *desc; 275 bool csum_hw = false; 276 struct device *kdev; 277 skb_frag_t *frag; 278 279 kdev = &intf->parent->pdev->dev; 280 281 nr_frags = skb_shinfo(skb)->nr_frags; 282 283 if (tx_spb_ring_full(intf, nr_frags + 1)) { 284 netif_stop_queue(dev); 285 if (net_ratelimit()) 286 netdev_err(dev, "Tx Ring Full!\n"); 287 return NETDEV_TX_BUSY; 288 } 289 290 /* Save skb len before adding csum offload header */ 291 total_bytes = skb->len; 292 skb = bcmasp_csum_offload(dev, skb, &csum_hw); 293 if (!skb) 294 return NETDEV_TX_OK; 295 296 spb_index = intf->tx_spb_index; 297 valid = intf->tx_spb_dma_valid; 298 for (i = 0; i <= nr_frags; i++) { 299 if (!i) { 300 size = skb_headlen(skb); 301 if (!nr_frags && size < (ETH_ZLEN + ETH_FCS_LEN)) { 302 if (skb_put_padto(skb, ETH_ZLEN + ETH_FCS_LEN)) 303 return NETDEV_TX_OK; 304 size = skb->len; 305 } 306 mapping = dma_map_single(kdev, skb->data, size, 307 DMA_TO_DEVICE); 308 } else { 309 frag = &skb_shinfo(skb)->frags[i - 1]; 310 size = skb_frag_size(frag); 311 mapping = skb_frag_dma_map(kdev, frag, 0, size, 312 DMA_TO_DEVICE); 313 } 314 315 if (dma_mapping_error(kdev, mapping)) { 316 intf->mib.tx_dma_failed++; 317 spb_index = intf->tx_spb_index; 318 for (j = 0; j < i; j++) { 319 bcmasp_clean_txcb(intf, spb_index); 320 spb_index = incr_ring(spb_index, 321 DESC_RING_COUNT); 322 } 323 /* Rewind so we do not have a hole */ 324 spb_index = intf->tx_spb_index; 325 dev_kfree_skb(skb); 326 return NETDEV_TX_OK; 327 } 328 329 txcb = &intf->tx_cbs[spb_index]; 330 desc = &intf->tx_spb_cpu[spb_index]; 331 memset(desc, 0, sizeof(*desc)); 332 txcb->skb = skb; 333 txcb->bytes_sent = total_bytes; 334 dma_unmap_addr_set(txcb, dma_addr, mapping); 335 dma_unmap_len_set(txcb, dma_len, size); 336 if (!i) { 337 desc->flags |= DESC_SOF; 338 if (csum_hw) 339 desc->flags |= DESC_EPKT_CMD; 340 } 341 342 if (i == nr_frags) { 343 desc->flags |= DESC_EOF; 344 txcb->last = true; 345 } 346 347 desc->buf = mapping; 348 desc->size = size; 349 desc->flags |= DESC_INT_EN; 350 351 netif_dbg(intf, tx_queued, dev, 352 "%s dma_buf=%pad dma_len=0x%x flags=0x%x index=0x%x\n", 353 __func__, &mapping, desc->size, desc->flags, 354 spb_index); 355 356 spb_index = incr_ring(spb_index, DESC_RING_COUNT); 357 valid = incr_last_byte(valid, intf->tx_spb_dma_addr, 358 DESC_RING_COUNT); 359 } 360 361 /* Ensure all descriptors have been written to DRAM for the 362 * hardware to see up-to-date contents. 363 */ 364 wmb(); 365 366 intf->tx_spb_index = spb_index; 367 intf->tx_spb_dma_valid = valid; 368 bcmasp_intf_tx_write(intf, intf->tx_spb_dma_valid); 369 370 if (tx_spb_ring_full(intf, MAX_SKB_FRAGS + 1)) 371 netif_stop_queue(dev); 372 373 return NETDEV_TX_OK; 374 } 375 376 static void bcmasp_netif_start(struct net_device *dev) 377 { 378 struct bcmasp_intf *intf = netdev_priv(dev); 379 380 bcmasp_set_rx_mode(dev); 381 napi_enable(&intf->tx_napi); 382 napi_enable(&intf->rx_napi); 383 384 bcmasp_enable_rx_irq(intf, 1); 385 bcmasp_enable_tx_irq(intf, 1); 386 387 phy_start(dev->phydev); 388 } 389 390 static void umac_reset(struct bcmasp_intf *intf) 391 { 392 umac_wl(intf, 0x0, UMC_CMD); 393 umac_wl(intf, UMC_CMD_SW_RESET, UMC_CMD); 394 usleep_range(10, 100); 395 /* We hold the umac in reset and bring it out of 396 * reset when phy link is up. 397 */ 398 } 399 400 static void umac_set_hw_addr(struct bcmasp_intf *intf, 401 const unsigned char *addr) 402 { 403 u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | 404 addr[3]; 405 u32 mac1 = (addr[4] << 8) | addr[5]; 406 407 umac_wl(intf, mac0, UMC_MAC0); 408 umac_wl(intf, mac1, UMC_MAC1); 409 } 410 411 static void umac_enable_set(struct bcmasp_intf *intf, u32 mask, 412 unsigned int enable) 413 { 414 u32 reg; 415 416 reg = umac_rl(intf, UMC_CMD); 417 if (reg & UMC_CMD_SW_RESET) 418 return; 419 if (enable) 420 reg |= mask; 421 else 422 reg &= ~mask; 423 umac_wl(intf, reg, UMC_CMD); 424 425 /* UniMAC stops on a packet boundary, wait for a full-sized packet 426 * to be processed (1 msec). 427 */ 428 if (enable == 0) 429 usleep_range(1000, 2000); 430 } 431 432 static void umac_init(struct bcmasp_intf *intf) 433 { 434 umac_wl(intf, 0x800, UMC_FRM_LEN); 435 umac_wl(intf, 0xffff, UMC_PAUSE_CNTRL); 436 umac_wl(intf, 0x800, UMC_RX_MAX_PKT_SZ); 437 } 438 439 static int bcmasp_tx_reclaim(struct bcmasp_intf *intf) 440 { 441 struct bcmasp_intf_stats64 *stats = &intf->stats64; 442 struct device *kdev = &intf->parent->pdev->dev; 443 unsigned long read, released = 0; 444 struct bcmasp_tx_cb *txcb; 445 struct bcmasp_desc *desc; 446 dma_addr_t mapping; 447 448 read = bcmasp_intf_tx_read(intf); 449 while (intf->tx_spb_dma_read != read) { 450 txcb = &intf->tx_cbs[intf->tx_spb_clean_index]; 451 mapping = dma_unmap_addr(txcb, dma_addr); 452 453 dma_unmap_single(kdev, mapping, 454 dma_unmap_len(txcb, dma_len), 455 DMA_TO_DEVICE); 456 457 if (txcb->last) { 458 dev_consume_skb_any(txcb->skb); 459 460 u64_stats_update_begin(&stats->syncp); 461 u64_stats_inc(&stats->tx_packets); 462 u64_stats_add(&stats->tx_bytes, txcb->bytes_sent); 463 u64_stats_update_end(&stats->syncp); 464 } 465 466 desc = &intf->tx_spb_cpu[intf->tx_spb_clean_index]; 467 468 netif_dbg(intf, tx_done, intf->ndev, 469 "%s dma_buf=%pad dma_len=0x%x flags=0x%x c_index=0x%x\n", 470 __func__, &mapping, desc->size, desc->flags, 471 intf->tx_spb_clean_index); 472 473 bcmasp_clean_txcb(intf, intf->tx_spb_clean_index); 474 released++; 475 476 intf->tx_spb_clean_index = incr_ring(intf->tx_spb_clean_index, 477 DESC_RING_COUNT); 478 intf->tx_spb_dma_read = incr_first_byte(intf->tx_spb_dma_read, 479 intf->tx_spb_dma_addr, 480 DESC_RING_COUNT); 481 } 482 483 return released; 484 } 485 486 static int bcmasp_tx_poll(struct napi_struct *napi, int budget) 487 { 488 struct bcmasp_intf *intf = 489 container_of(napi, struct bcmasp_intf, tx_napi); 490 int released = 0; 491 492 released = bcmasp_tx_reclaim(intf); 493 494 napi_complete(&intf->tx_napi); 495 496 bcmasp_enable_tx_irq(intf, 1); 497 498 if (released) 499 netif_wake_queue(intf->ndev); 500 501 return 0; 502 } 503 504 static int bcmasp_rx_poll(struct napi_struct *napi, int budget) 505 { 506 struct bcmasp_intf *intf = 507 container_of(napi, struct bcmasp_intf, rx_napi); 508 struct bcmasp_intf_stats64 *stats = &intf->stats64; 509 struct device *kdev = &intf->parent->pdev->dev; 510 unsigned long processed = 0; 511 struct bcmasp_desc *desc; 512 struct sk_buff *skb; 513 dma_addr_t valid; 514 void *data; 515 u64 flags; 516 u32 len; 517 518 valid = bcmasp_intf_rx_desc_read(intf) + 1; 519 if (valid == intf->rx_edpkt_dma_addr + DESC_RING_SIZE) 520 valid = intf->rx_edpkt_dma_addr; 521 522 while ((processed < budget) && (valid != intf->rx_edpkt_dma_read)) { 523 desc = &intf->rx_edpkt_cpu[intf->rx_edpkt_index]; 524 525 /* Ensure that descriptor has been fully written to DRAM by 526 * hardware before reading by the CPU 527 */ 528 rmb(); 529 530 /* Calculate virt addr by offsetting from physical addr */ 531 data = intf->rx_ring_cpu + 532 (DESC_ADDR(desc->buf) - intf->rx_ring_dma); 533 534 flags = DESC_FLAGS(desc->buf); 535 if (unlikely(flags & (DESC_CRC_ERR | DESC_RX_SYM_ERR))) { 536 if (net_ratelimit()) { 537 netif_err(intf, rx_status, intf->ndev, 538 "flags=0x%llx\n", flags); 539 } 540 541 u64_stats_update_begin(&stats->syncp); 542 if (flags & DESC_CRC_ERR) 543 u64_stats_inc(&stats->rx_crc_errs); 544 if (flags & DESC_RX_SYM_ERR) 545 u64_stats_inc(&stats->rx_sym_errs); 546 u64_stats_update_end(&stats->syncp); 547 548 goto next; 549 } 550 551 dma_sync_single_for_cpu(kdev, DESC_ADDR(desc->buf), desc->size, 552 DMA_FROM_DEVICE); 553 554 len = desc->size; 555 556 skb = napi_alloc_skb(napi, len); 557 if (!skb) { 558 u64_stats_update_begin(&stats->syncp); 559 u64_stats_inc(&stats->rx_dropped); 560 u64_stats_update_end(&stats->syncp); 561 intf->mib.alloc_rx_skb_failed++; 562 563 goto next; 564 } 565 566 skb_put(skb, len); 567 memcpy(skb->data, data, len); 568 569 skb_pull(skb, 2); 570 len -= 2; 571 if (likely(intf->crc_fwd)) { 572 skb_trim(skb, len - ETH_FCS_LEN); 573 len -= ETH_FCS_LEN; 574 } 575 576 if ((intf->ndev->features & NETIF_F_RXCSUM) && 577 (desc->buf & DESC_CHKSUM)) 578 skb->ip_summed = CHECKSUM_UNNECESSARY; 579 580 skb->protocol = eth_type_trans(skb, intf->ndev); 581 582 napi_gro_receive(napi, skb); 583 584 u64_stats_update_begin(&stats->syncp); 585 u64_stats_inc(&stats->rx_packets); 586 u64_stats_add(&stats->rx_bytes, len); 587 u64_stats_update_end(&stats->syncp); 588 589 next: 590 bcmasp_intf_rx_buffer_write(intf, (DESC_ADDR(desc->buf) + 591 desc->size)); 592 593 processed++; 594 intf->rx_edpkt_dma_read = 595 incr_first_byte(intf->rx_edpkt_dma_read, 596 intf->rx_edpkt_dma_addr, 597 DESC_RING_COUNT); 598 intf->rx_edpkt_index = incr_ring(intf->rx_edpkt_index, 599 DESC_RING_COUNT); 600 } 601 602 bcmasp_intf_rx_desc_write(intf, intf->rx_edpkt_dma_read); 603 604 if (processed < budget) { 605 napi_complete_done(&intf->rx_napi, processed); 606 bcmasp_enable_rx_irq(intf, 1); 607 } 608 609 return processed; 610 } 611 612 static void bcmasp_adj_link(struct net_device *dev) 613 { 614 struct bcmasp_intf *intf = netdev_priv(dev); 615 struct phy_device *phydev = dev->phydev; 616 u32 cmd_bits = 0, reg; 617 int changed = 0; 618 619 if (intf->old_link != phydev->link) { 620 changed = 1; 621 intf->old_link = phydev->link; 622 } 623 624 if (intf->old_duplex != phydev->duplex) { 625 changed = 1; 626 intf->old_duplex = phydev->duplex; 627 } 628 629 switch (phydev->speed) { 630 case SPEED_2500: 631 cmd_bits = UMC_CMD_SPEED_2500; 632 break; 633 case SPEED_1000: 634 cmd_bits = UMC_CMD_SPEED_1000; 635 break; 636 case SPEED_100: 637 cmd_bits = UMC_CMD_SPEED_100; 638 break; 639 case SPEED_10: 640 cmd_bits = UMC_CMD_SPEED_10; 641 break; 642 default: 643 break; 644 } 645 cmd_bits <<= UMC_CMD_SPEED_SHIFT; 646 647 if (phydev->duplex == DUPLEX_HALF) 648 cmd_bits |= UMC_CMD_HD_EN; 649 650 if (intf->old_pause != phydev->pause) { 651 changed = 1; 652 intf->old_pause = phydev->pause; 653 } 654 655 if (!phydev->pause) 656 cmd_bits |= UMC_CMD_RX_PAUSE_IGNORE | UMC_CMD_TX_PAUSE_IGNORE; 657 658 if (!changed) 659 return; 660 661 if (phydev->link) { 662 reg = umac_rl(intf, UMC_CMD); 663 reg &= ~((UMC_CMD_SPEED_MASK << UMC_CMD_SPEED_SHIFT) | 664 UMC_CMD_HD_EN | UMC_CMD_RX_PAUSE_IGNORE | 665 UMC_CMD_TX_PAUSE_IGNORE); 666 reg |= cmd_bits; 667 if (reg & UMC_CMD_SW_RESET) { 668 reg &= ~UMC_CMD_SW_RESET; 669 umac_wl(intf, reg, UMC_CMD); 670 udelay(2); 671 reg |= UMC_CMD_TX_EN | UMC_CMD_RX_EN | UMC_CMD_PROMISC; 672 } 673 umac_wl(intf, reg, UMC_CMD); 674 675 intf->eee.eee_active = phy_init_eee(phydev, 0) >= 0; 676 bcmasp_eee_enable_set(intf, intf->eee.eee_active); 677 } 678 679 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 680 if (phydev->link) 681 reg |= RGMII_LINK; 682 else 683 reg &= ~RGMII_LINK; 684 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 685 686 if (changed) 687 phy_print_status(phydev); 688 } 689 690 static int bcmasp_init_rx(struct bcmasp_intf *intf) 691 { 692 struct device *kdev = &intf->parent->pdev->dev; 693 struct page *buffer_pg; 694 dma_addr_t dma; 695 void *p; 696 u32 reg; 697 int ret; 698 699 intf->rx_buf_order = get_order(RING_BUFFER_SIZE); 700 buffer_pg = alloc_pages(GFP_KERNEL, intf->rx_buf_order); 701 702 dma = dma_map_page(kdev, buffer_pg, 0, RING_BUFFER_SIZE, 703 DMA_FROM_DEVICE); 704 if (dma_mapping_error(kdev, dma)) { 705 __free_pages(buffer_pg, intf->rx_buf_order); 706 return -ENOMEM; 707 } 708 intf->rx_ring_cpu = page_to_virt(buffer_pg); 709 intf->rx_ring_dma = dma; 710 intf->rx_ring_dma_valid = intf->rx_ring_dma + RING_BUFFER_SIZE - 1; 711 712 p = dma_alloc_coherent(kdev, DESC_RING_SIZE, &intf->rx_edpkt_dma_addr, 713 GFP_KERNEL); 714 if (!p) { 715 ret = -ENOMEM; 716 goto free_rx_ring; 717 } 718 intf->rx_edpkt_cpu = p; 719 720 netif_napi_add(intf->ndev, &intf->rx_napi, bcmasp_rx_poll); 721 722 intf->rx_edpkt_dma_read = intf->rx_edpkt_dma_addr; 723 intf->rx_edpkt_index = 0; 724 725 /* Make sure channels are disabled */ 726 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 727 728 /* Rx SPB */ 729 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_READ); 730 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_WRITE); 731 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_BASE); 732 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 733 RX_EDPKT_RING_BUFFER_END); 734 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 735 RX_EDPKT_RING_BUFFER_VALID); 736 737 /* EDPKT */ 738 rx_edpkt_cfg_wl(intf, (RX_EDPKT_CFG_CFG0_RBUF_4K << 739 RX_EDPKT_CFG_CFG0_DBUF_SHIFT) | 740 (RX_EDPKT_CFG_CFG0_64_ALN << 741 RX_EDPKT_CFG_CFG0_BALN_SHIFT) | 742 (RX_EDPKT_CFG_CFG0_EFRM_STUF), 743 RX_EDPKT_CFG_CFG0); 744 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_WRITE); 745 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_READ); 746 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_BASE); 747 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr + (DESC_RING_SIZE - 1), 748 RX_EDPKT_DMA_END); 749 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr + (DESC_RING_SIZE - 1), 750 RX_EDPKT_DMA_VALID); 751 752 reg = UMAC2FB_CFG_DEFAULT_EN | 753 ((intf->channel + 11) << UMAC2FB_CFG_CHID_SHIFT); 754 reg |= (0xd << UMAC2FB_CFG_OK_SEND_SHIFT); 755 umac2fb_wl(intf, reg, UMAC2FB_CFG); 756 757 return 0; 758 759 free_rx_ring: 760 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 761 DMA_FROM_DEVICE); 762 __free_pages(virt_to_page(intf->rx_ring_cpu), intf->rx_buf_order); 763 764 return ret; 765 } 766 767 static void bcmasp_reclaim_free_all_rx(struct bcmasp_intf *intf) 768 { 769 struct device *kdev = &intf->parent->pdev->dev; 770 771 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 772 intf->rx_edpkt_dma_addr); 773 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 774 DMA_FROM_DEVICE); 775 __free_pages(virt_to_page(intf->rx_ring_cpu), intf->rx_buf_order); 776 } 777 778 static int bcmasp_init_tx(struct bcmasp_intf *intf) 779 { 780 struct device *kdev = &intf->parent->pdev->dev; 781 void *p; 782 int ret; 783 784 p = dma_alloc_coherent(kdev, DESC_RING_SIZE, &intf->tx_spb_dma_addr, 785 GFP_KERNEL); 786 if (!p) 787 return -ENOMEM; 788 789 intf->tx_spb_cpu = p; 790 intf->tx_spb_dma_valid = intf->tx_spb_dma_addr + DESC_RING_SIZE - 1; 791 intf->tx_spb_dma_read = intf->tx_spb_dma_addr; 792 793 intf->tx_cbs = kcalloc(DESC_RING_COUNT, sizeof(struct bcmasp_tx_cb), 794 GFP_KERNEL); 795 if (!intf->tx_cbs) { 796 ret = -ENOMEM; 797 goto free_tx_spb; 798 } 799 800 intf->tx_spb_index = 0; 801 intf->tx_spb_clean_index = 0; 802 memset(intf->tx_cbs, 0, sizeof(struct bcmasp_tx_cb) * DESC_RING_COUNT); 803 804 netif_napi_add_tx(intf->ndev, &intf->tx_napi, bcmasp_tx_poll); 805 806 /* Make sure channels are disabled */ 807 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 808 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 809 810 /* Tx SPB */ 811 tx_spb_ctrl_wl(intf, ((intf->channel + 8) << TX_SPB_CTRL_XF_BID_SHIFT), 812 TX_SPB_CTRL_XF_CTRL2); 813 tx_pause_ctrl_wl(intf, (1 << (intf->channel + 8)), TX_PAUSE_MAP_VECTOR); 814 tx_spb_top_wl(intf, 0x1e, TX_SPB_TOP_BLKOUT); 815 tx_spb_top_wl(intf, 0x0, TX_SPB_TOP_SPRE_BW_CTRL); 816 817 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_READ); 818 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_BASE); 819 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_END); 820 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID); 821 822 return 0; 823 824 free_tx_spb: 825 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 826 intf->tx_spb_dma_addr); 827 828 return ret; 829 } 830 831 static void bcmasp_reclaim_free_all_tx(struct bcmasp_intf *intf) 832 { 833 struct device *kdev = &intf->parent->pdev->dev; 834 835 /* Free descriptors */ 836 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 837 intf->tx_spb_dma_addr); 838 839 /* Free cbs */ 840 kfree(intf->tx_cbs); 841 } 842 843 static void bcmasp_ephy_enable_set(struct bcmasp_intf *intf, bool enable) 844 { 845 u32 mask = RGMII_EPHY_CFG_IDDQ_BIAS | RGMII_EPHY_CFG_EXT_PWRDOWN | 846 RGMII_EPHY_CFG_IDDQ_GLOBAL; 847 u32 reg; 848 849 reg = rgmii_rl(intf, RGMII_EPHY_CNTRL); 850 if (enable) { 851 reg &= ~RGMII_EPHY_CK25_DIS; 852 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 853 mdelay(1); 854 855 reg &= ~mask; 856 reg |= RGMII_EPHY_RESET; 857 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 858 mdelay(1); 859 860 reg &= ~RGMII_EPHY_RESET; 861 } else { 862 reg |= mask | RGMII_EPHY_RESET; 863 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 864 mdelay(1); 865 reg |= RGMII_EPHY_CK25_DIS; 866 } 867 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 868 mdelay(1); 869 870 /* Set or clear the LED control override to avoid lighting up LEDs 871 * while the EPHY is powered off and drawing unnecessary current. 872 */ 873 reg = rgmii_rl(intf, RGMII_SYS_LED_CNTRL); 874 if (enable) 875 reg &= ~RGMII_SYS_LED_CNTRL_LINK_OVRD; 876 else 877 reg |= RGMII_SYS_LED_CNTRL_LINK_OVRD; 878 rgmii_wl(intf, reg, RGMII_SYS_LED_CNTRL); 879 } 880 881 static void bcmasp_rgmii_mode_en_set(struct bcmasp_intf *intf, bool enable) 882 { 883 u32 reg; 884 885 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 886 reg &= ~RGMII_OOB_DIS; 887 if (enable) 888 reg |= RGMII_MODE_EN; 889 else 890 reg &= ~RGMII_MODE_EN; 891 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 892 } 893 894 static void bcmasp_netif_deinit(struct net_device *dev) 895 { 896 struct bcmasp_intf *intf = netdev_priv(dev); 897 u32 reg, timeout = 1000; 898 899 napi_disable(&intf->tx_napi); 900 901 bcmasp_enable_tx(intf, 0); 902 903 /* Flush any TX packets in the pipe */ 904 tx_spb_dma_wl(intf, TX_SPB_DMA_FIFO_FLUSH, TX_SPB_DMA_FIFO_CTRL); 905 do { 906 reg = tx_spb_dma_rl(intf, TX_SPB_DMA_FIFO_STATUS); 907 if (!(reg & TX_SPB_DMA_FIFO_FLUSH)) 908 break; 909 usleep_range(1000, 2000); 910 } while (timeout-- > 0); 911 tx_spb_dma_wl(intf, 0x0, TX_SPB_DMA_FIFO_CTRL); 912 913 bcmasp_tx_reclaim(intf); 914 915 umac_enable_set(intf, UMC_CMD_TX_EN, 0); 916 917 phy_stop(dev->phydev); 918 919 umac_enable_set(intf, UMC_CMD_RX_EN, 0); 920 921 bcmasp_flush_rx_port(intf); 922 usleep_range(1000, 2000); 923 bcmasp_enable_rx(intf, 0); 924 925 napi_disable(&intf->rx_napi); 926 927 /* Disable interrupts */ 928 bcmasp_enable_tx_irq(intf, 0); 929 bcmasp_enable_rx_irq(intf, 0); 930 931 netif_napi_del(&intf->tx_napi); 932 bcmasp_reclaim_free_all_tx(intf); 933 934 netif_napi_del(&intf->rx_napi); 935 bcmasp_reclaim_free_all_rx(intf); 936 } 937 938 static int bcmasp_stop(struct net_device *dev) 939 { 940 struct bcmasp_intf *intf = netdev_priv(dev); 941 942 netif_dbg(intf, ifdown, dev, "bcmasp stop\n"); 943 944 /* Stop tx from updating HW */ 945 netif_tx_disable(dev); 946 947 bcmasp_netif_deinit(dev); 948 949 phy_disconnect(dev->phydev); 950 951 /* Disable internal EPHY or external PHY */ 952 if (intf->internal_phy) 953 bcmasp_ephy_enable_set(intf, false); 954 else 955 bcmasp_rgmii_mode_en_set(intf, false); 956 957 /* Disable the interface clocks */ 958 bcmasp_core_clock_set_intf(intf, false); 959 960 clk_disable_unprepare(intf->parent->clk); 961 962 return 0; 963 } 964 965 static void bcmasp_configure_port(struct bcmasp_intf *intf) 966 { 967 u32 reg, id_mode_dis = 0; 968 969 reg = rgmii_rl(intf, RGMII_PORT_CNTRL); 970 reg &= ~RGMII_PORT_MODE_MASK; 971 972 switch (intf->phy_interface) { 973 case PHY_INTERFACE_MODE_RGMII: 974 /* RGMII_NO_ID: TXC transitions at the same time as TXD 975 * (requires PCB or receiver-side delay) 976 * RGMII: Add 2ns delay on TXC (90 degree shift) 977 * 978 * ID is implicitly disabled for 100Mbps (RG)MII operation. 979 */ 980 id_mode_dis = RGMII_ID_MODE_DIS; 981 fallthrough; 982 case PHY_INTERFACE_MODE_RGMII_TXID: 983 reg |= RGMII_PORT_MODE_EXT_GPHY; 984 break; 985 case PHY_INTERFACE_MODE_MII: 986 reg |= RGMII_PORT_MODE_EXT_EPHY; 987 break; 988 default: 989 break; 990 } 991 992 if (intf->internal_phy) 993 reg |= RGMII_PORT_MODE_EPHY; 994 995 rgmii_wl(intf, reg, RGMII_PORT_CNTRL); 996 997 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 998 reg &= ~RGMII_ID_MODE_DIS; 999 reg |= id_mode_dis; 1000 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 1001 } 1002 1003 static int bcmasp_netif_init(struct net_device *dev, bool phy_connect) 1004 { 1005 struct bcmasp_intf *intf = netdev_priv(dev); 1006 phy_interface_t phy_iface = intf->phy_interface; 1007 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 1008 PHY_BRCM_DIS_TXCRXC_NOENRGY | 1009 PHY_BRCM_IDDQ_SUSPEND; 1010 struct phy_device *phydev = NULL; 1011 int ret; 1012 1013 /* Always enable interface clocks */ 1014 bcmasp_core_clock_set_intf(intf, true); 1015 1016 /* Enable internal PHY or external PHY before any MAC activity */ 1017 if (intf->internal_phy) 1018 bcmasp_ephy_enable_set(intf, true); 1019 else 1020 bcmasp_rgmii_mode_en_set(intf, true); 1021 bcmasp_configure_port(intf); 1022 1023 /* This is an ugly quirk but we have not been correctly 1024 * interpreting the phy_interface values and we have done that 1025 * across different drivers, so at least we are consistent in 1026 * our mistakes. 1027 * 1028 * When the Generic PHY driver is in use either the PHY has 1029 * been strapped or programmed correctly by the boot loader so 1030 * we should stick to our incorrect interpretation since we 1031 * have validated it. 1032 * 1033 * Now when a dedicated PHY driver is in use, we need to 1034 * reverse the meaning of the phy_interface_mode values to 1035 * something that the PHY driver will interpret and act on such 1036 * that we have two mistakes canceling themselves so to speak. 1037 * We only do this for the two modes that GENET driver 1038 * officially supports on Broadcom STB chips: 1039 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. 1040 * Other modes are not *officially* supported with the boot 1041 * loader and the scripted environment generating Device Tree 1042 * blobs for those platforms. 1043 * 1044 * Note that internal PHY and fixed-link configurations are not 1045 * affected because they use different phy_interface_t values 1046 * or the Generic PHY driver. 1047 */ 1048 switch (phy_iface) { 1049 case PHY_INTERFACE_MODE_RGMII: 1050 phy_iface = PHY_INTERFACE_MODE_RGMII_ID; 1051 break; 1052 case PHY_INTERFACE_MODE_RGMII_TXID: 1053 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID; 1054 break; 1055 default: 1056 break; 1057 } 1058 1059 if (phy_connect) { 1060 phydev = of_phy_connect(dev, intf->phy_dn, 1061 bcmasp_adj_link, phy_flags, 1062 phy_iface); 1063 if (!phydev) { 1064 ret = -ENODEV; 1065 netdev_err(dev, "could not attach to PHY\n"); 1066 goto err_phy_disable; 1067 } 1068 1069 /* Indicate that the MAC is responsible for PHY PM */ 1070 phydev->mac_managed_pm = true; 1071 } else if (!intf->wolopts) { 1072 ret = phy_resume(dev->phydev); 1073 if (ret) 1074 goto err_phy_disable; 1075 } 1076 1077 umac_reset(intf); 1078 1079 umac_init(intf); 1080 1081 umac_set_hw_addr(intf, dev->dev_addr); 1082 1083 intf->old_duplex = -1; 1084 intf->old_link = -1; 1085 intf->old_pause = -1; 1086 1087 ret = bcmasp_init_tx(intf); 1088 if (ret) 1089 goto err_phy_disconnect; 1090 1091 /* Turn on asp */ 1092 bcmasp_enable_tx(intf, 1); 1093 1094 ret = bcmasp_init_rx(intf); 1095 if (ret) 1096 goto err_reclaim_tx; 1097 1098 bcmasp_enable_rx(intf, 1); 1099 1100 intf->crc_fwd = !!(umac_rl(intf, UMC_CMD) & UMC_CMD_CRC_FWD); 1101 1102 bcmasp_netif_start(dev); 1103 1104 netif_start_queue(dev); 1105 1106 return 0; 1107 1108 err_reclaim_tx: 1109 bcmasp_reclaim_free_all_tx(intf); 1110 err_phy_disconnect: 1111 if (phydev) 1112 phy_disconnect(phydev); 1113 err_phy_disable: 1114 if (intf->internal_phy) 1115 bcmasp_ephy_enable_set(intf, false); 1116 else 1117 bcmasp_rgmii_mode_en_set(intf, false); 1118 return ret; 1119 } 1120 1121 static int bcmasp_open(struct net_device *dev) 1122 { 1123 struct bcmasp_intf *intf = netdev_priv(dev); 1124 int ret; 1125 1126 netif_dbg(intf, ifup, dev, "bcmasp open\n"); 1127 1128 ret = clk_prepare_enable(intf->parent->clk); 1129 if (ret) 1130 return ret; 1131 1132 ret = bcmasp_netif_init(dev, true); 1133 if (ret) 1134 clk_disable_unprepare(intf->parent->clk); 1135 1136 return ret; 1137 } 1138 1139 static void bcmasp_tx_timeout(struct net_device *dev, unsigned int txqueue) 1140 { 1141 struct bcmasp_intf *intf = netdev_priv(dev); 1142 1143 netif_dbg(intf, tx_err, dev, "transmit timeout!\n"); 1144 intf->mib.tx_timeout_cnt++; 1145 } 1146 1147 static int bcmasp_get_phys_port_name(struct net_device *dev, 1148 char *name, size_t len) 1149 { 1150 struct bcmasp_intf *intf = netdev_priv(dev); 1151 1152 if (snprintf(name, len, "p%d", intf->port) >= len) 1153 return -EINVAL; 1154 1155 return 0; 1156 } 1157 1158 static void bcmasp_get_stats64(struct net_device *dev, 1159 struct rtnl_link_stats64 *stats) 1160 { 1161 struct bcmasp_intf *intf = netdev_priv(dev); 1162 struct bcmasp_intf_stats64 *lstats; 1163 unsigned int start; 1164 1165 lstats = &intf->stats64; 1166 1167 do { 1168 start = u64_stats_fetch_begin(&lstats->syncp); 1169 stats->rx_packets = u64_stats_read(&lstats->rx_packets); 1170 stats->rx_bytes = u64_stats_read(&lstats->rx_bytes); 1171 stats->rx_dropped = u64_stats_read(&lstats->rx_dropped); 1172 stats->rx_crc_errors = u64_stats_read(&lstats->rx_crc_errs); 1173 stats->rx_frame_errors = u64_stats_read(&lstats->rx_sym_errs); 1174 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors; 1175 1176 stats->tx_packets = u64_stats_read(&lstats->tx_packets); 1177 stats->tx_bytes = u64_stats_read(&lstats->tx_bytes); 1178 } while (u64_stats_fetch_retry(&lstats->syncp, start)); 1179 } 1180 1181 static const struct net_device_ops bcmasp_netdev_ops = { 1182 .ndo_open = bcmasp_open, 1183 .ndo_stop = bcmasp_stop, 1184 .ndo_start_xmit = bcmasp_xmit, 1185 .ndo_tx_timeout = bcmasp_tx_timeout, 1186 .ndo_set_rx_mode = bcmasp_set_rx_mode, 1187 .ndo_get_phys_port_name = bcmasp_get_phys_port_name, 1188 .ndo_eth_ioctl = phy_do_ioctl_running, 1189 .ndo_set_mac_address = eth_mac_addr, 1190 .ndo_get_stats64 = bcmasp_get_stats64, 1191 }; 1192 1193 static void bcmasp_map_res(struct bcmasp_priv *priv, struct bcmasp_intf *intf) 1194 { 1195 /* Per port */ 1196 intf->res.umac = priv->base + UMC_OFFSET(intf); 1197 intf->res.umac2fb = priv->base + (priv->hw_info->umac2fb + 1198 (intf->port * 0x4)); 1199 intf->res.rgmii = priv->base + RGMII_OFFSET(intf); 1200 1201 /* Per ch */ 1202 intf->tx_spb_dma = priv->base + TX_SPB_DMA_OFFSET(intf); 1203 intf->res.tx_spb_ctrl = priv->base + TX_SPB_CTRL_OFFSET(intf); 1204 intf->res.tx_spb_top = priv->base + TX_SPB_TOP_OFFSET(intf); 1205 intf->res.tx_epkt_core = priv->base + TX_EPKT_C_OFFSET(intf); 1206 intf->res.tx_pause_ctrl = priv->base + TX_PAUSE_CTRL_OFFSET(intf); 1207 1208 intf->rx_edpkt_dma = priv->base + RX_EDPKT_DMA_OFFSET(intf); 1209 intf->rx_edpkt_cfg = priv->base + RX_EDPKT_CFG_OFFSET(intf); 1210 } 1211 1212 #define MAX_IRQ_STR_LEN 64 1213 struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv, 1214 struct device_node *ndev_dn, int i) 1215 { 1216 struct device *dev = &priv->pdev->dev; 1217 struct bcmasp_intf *intf; 1218 struct net_device *ndev; 1219 int ch, port, ret; 1220 1221 if (of_property_read_u32(ndev_dn, "reg", &port)) { 1222 dev_warn(dev, "%s: invalid port number\n", ndev_dn->name); 1223 goto err; 1224 } 1225 1226 if (of_property_read_u32(ndev_dn, "brcm,channel", &ch)) { 1227 dev_warn(dev, "%s: invalid ch number\n", ndev_dn->name); 1228 goto err; 1229 } 1230 1231 ndev = alloc_etherdev(sizeof(struct bcmasp_intf)); 1232 if (!ndev) { 1233 dev_warn(dev, "%s: unable to alloc ndev\n", ndev_dn->name); 1234 goto err; 1235 } 1236 intf = netdev_priv(ndev); 1237 1238 intf->parent = priv; 1239 intf->ndev = ndev; 1240 intf->channel = ch; 1241 intf->port = port; 1242 intf->ndev_dn = ndev_dn; 1243 intf->index = i; 1244 1245 ret = of_get_phy_mode(ndev_dn, &intf->phy_interface); 1246 if (ret < 0) { 1247 dev_err(dev, "invalid PHY mode property\n"); 1248 goto err_free_netdev; 1249 } 1250 1251 if (intf->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 1252 intf->internal_phy = true; 1253 1254 intf->phy_dn = of_parse_phandle(ndev_dn, "phy-handle", 0); 1255 if (!intf->phy_dn && of_phy_is_fixed_link(ndev_dn)) { 1256 ret = of_phy_register_fixed_link(ndev_dn); 1257 if (ret) { 1258 dev_warn(dev, "%s: failed to register fixed PHY\n", 1259 ndev_dn->name); 1260 goto err_free_netdev; 1261 } 1262 intf->phy_dn = ndev_dn; 1263 } 1264 1265 /* Map resource */ 1266 bcmasp_map_res(priv, intf); 1267 1268 if ((!phy_interface_mode_is_rgmii(intf->phy_interface) && 1269 intf->phy_interface != PHY_INTERFACE_MODE_MII && 1270 intf->phy_interface != PHY_INTERFACE_MODE_INTERNAL) || 1271 (intf->port != 1 && intf->internal_phy)) { 1272 netdev_err(intf->ndev, "invalid PHY mode: %s for port %d\n", 1273 phy_modes(intf->phy_interface), intf->port); 1274 ret = -EINVAL; 1275 goto err_free_netdev; 1276 } 1277 1278 ret = of_get_ethdev_address(ndev_dn, ndev); 1279 if (ret) { 1280 netdev_warn(ndev, "using random Ethernet MAC\n"); 1281 eth_hw_addr_random(ndev); 1282 } 1283 1284 SET_NETDEV_DEV(ndev, dev); 1285 intf->ops = &bcmasp_intf_ops; 1286 ndev->netdev_ops = &bcmasp_netdev_ops; 1287 ndev->ethtool_ops = &bcmasp_ethtool_ops; 1288 intf->msg_enable = netif_msg_init(-1, NETIF_MSG_DRV | 1289 NETIF_MSG_PROBE | 1290 NETIF_MSG_LINK); 1291 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 1292 NETIF_F_RXCSUM; 1293 ndev->hw_features |= ndev->features; 1294 ndev->needed_headroom += sizeof(struct bcmasp_pkt_offload); 1295 1296 return intf; 1297 1298 err_free_netdev: 1299 free_netdev(ndev); 1300 err: 1301 return NULL; 1302 } 1303 1304 void bcmasp_interface_destroy(struct bcmasp_intf *intf) 1305 { 1306 if (intf->ndev->reg_state == NETREG_REGISTERED) 1307 unregister_netdev(intf->ndev); 1308 if (of_phy_is_fixed_link(intf->ndev_dn)) 1309 of_phy_deregister_fixed_link(intf->ndev_dn); 1310 free_netdev(intf->ndev); 1311 } 1312 1313 static void bcmasp_suspend_to_wol(struct bcmasp_intf *intf) 1314 { 1315 struct net_device *ndev = intf->ndev; 1316 u32 reg; 1317 1318 reg = umac_rl(intf, UMC_MPD_CTRL); 1319 if (intf->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) 1320 reg |= UMC_MPD_CTRL_MPD_EN; 1321 reg &= ~UMC_MPD_CTRL_PSW_EN; 1322 if (intf->wolopts & WAKE_MAGICSECURE) { 1323 /* Program the SecureOn password */ 1324 umac_wl(intf, get_unaligned_be16(&intf->sopass[0]), 1325 UMC_PSW_MS); 1326 umac_wl(intf, get_unaligned_be32(&intf->sopass[2]), 1327 UMC_PSW_LS); 1328 reg |= UMC_MPD_CTRL_PSW_EN; 1329 } 1330 umac_wl(intf, reg, UMC_MPD_CTRL); 1331 1332 if (intf->wolopts & WAKE_FILTER) 1333 bcmasp_netfilt_suspend(intf); 1334 1335 /* Bring UniMAC out of reset if needed and enable RX */ 1336 reg = umac_rl(intf, UMC_CMD); 1337 if (reg & UMC_CMD_SW_RESET) 1338 reg &= ~UMC_CMD_SW_RESET; 1339 1340 reg |= UMC_CMD_RX_EN | UMC_CMD_PROMISC; 1341 umac_wl(intf, reg, UMC_CMD); 1342 1343 umac_enable_set(intf, UMC_CMD_RX_EN, 1); 1344 1345 if (intf->parent->wol_irq > 0) { 1346 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1347 ASP_WAKEUP_INTR2_MASK_CLEAR); 1348 } 1349 1350 netif_dbg(intf, wol, ndev, "entered WOL mode\n"); 1351 } 1352 1353 int bcmasp_interface_suspend(struct bcmasp_intf *intf) 1354 { 1355 struct device *kdev = &intf->parent->pdev->dev; 1356 struct net_device *dev = intf->ndev; 1357 int ret = 0; 1358 1359 if (!netif_running(dev)) 1360 return 0; 1361 1362 netif_device_detach(dev); 1363 1364 bcmasp_netif_deinit(dev); 1365 1366 if (!intf->wolopts) { 1367 ret = phy_suspend(dev->phydev); 1368 if (ret) 1369 goto out; 1370 1371 if (intf->internal_phy) 1372 bcmasp_ephy_enable_set(intf, false); 1373 else 1374 bcmasp_rgmii_mode_en_set(intf, false); 1375 1376 /* If Wake-on-LAN is disabled, we can safely 1377 * disable the network interface clocks. 1378 */ 1379 bcmasp_core_clock_set_intf(intf, false); 1380 } 1381 1382 if (device_may_wakeup(kdev) && intf->wolopts) 1383 bcmasp_suspend_to_wol(intf); 1384 1385 clk_disable_unprepare(intf->parent->clk); 1386 1387 return ret; 1388 1389 out: 1390 bcmasp_netif_init(dev, false); 1391 return ret; 1392 } 1393 1394 static void bcmasp_resume_from_wol(struct bcmasp_intf *intf) 1395 { 1396 u32 reg; 1397 1398 reg = umac_rl(intf, UMC_MPD_CTRL); 1399 reg &= ~UMC_MPD_CTRL_MPD_EN; 1400 umac_wl(intf, reg, UMC_MPD_CTRL); 1401 1402 if (intf->parent->wol_irq > 0) { 1403 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1404 ASP_WAKEUP_INTR2_MASK_SET); 1405 } 1406 } 1407 1408 int bcmasp_interface_resume(struct bcmasp_intf *intf) 1409 { 1410 struct net_device *dev = intf->ndev; 1411 int ret; 1412 1413 if (!netif_running(dev)) 1414 return 0; 1415 1416 ret = clk_prepare_enable(intf->parent->clk); 1417 if (ret) 1418 return ret; 1419 1420 ret = bcmasp_netif_init(dev, false); 1421 if (ret) 1422 goto out; 1423 1424 bcmasp_resume_from_wol(intf); 1425 1426 if (intf->eee.eee_enabled) 1427 bcmasp_eee_enable_set(intf, true); 1428 1429 netif_device_attach(dev); 1430 1431 return 0; 1432 1433 out: 1434 clk_disable_unprepare(intf->parent->clk); 1435 return ret; 1436 } 1437