1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) "bcmasp_intf: " fmt 3 4 #include <asm/byteorder.h> 5 #include <linux/brcmphy.h> 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/etherdevice.h> 9 #include <linux/netdevice.h> 10 #include <linux/of_net.h> 11 #include <linux/of_mdio.h> 12 #include <linux/phy.h> 13 #include <linux/phy_fixed.h> 14 #include <linux/ptp_classify.h> 15 #include <linux/platform_device.h> 16 #include <net/ip.h> 17 #include <net/ipv6.h> 18 19 #include "bcmasp.h" 20 #include "bcmasp_intf_defs.h" 21 22 static int incr_ring(int index, int ring_count) 23 { 24 index++; 25 if (index == ring_count) 26 return 0; 27 28 return index; 29 } 30 31 /* Points to last byte of descriptor */ 32 static dma_addr_t incr_last_byte(dma_addr_t addr, dma_addr_t beg, 33 int ring_count) 34 { 35 dma_addr_t end = beg + (ring_count * DESC_SIZE); 36 37 addr += DESC_SIZE; 38 if (addr > end) 39 return beg + DESC_SIZE - 1; 40 41 return addr; 42 } 43 44 /* Points to first byte of descriptor */ 45 static dma_addr_t incr_first_byte(dma_addr_t addr, dma_addr_t beg, 46 int ring_count) 47 { 48 dma_addr_t end = beg + (ring_count * DESC_SIZE); 49 50 addr += DESC_SIZE; 51 if (addr >= end) 52 return beg; 53 54 return addr; 55 } 56 57 static void bcmasp_enable_tx(struct bcmasp_intf *intf, int en) 58 { 59 if (en) { 60 tx_spb_ctrl_wl(intf, TX_SPB_CTRL_ENABLE_EN, TX_SPB_CTRL_ENABLE); 61 tx_epkt_core_wl(intf, (TX_EPKT_C_CFG_MISC_EN | 62 TX_EPKT_C_CFG_MISC_PT | 63 (intf->port << TX_EPKT_C_CFG_MISC_PS_SHIFT)), 64 TX_EPKT_C_CFG_MISC); 65 } else { 66 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 67 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 68 } 69 } 70 71 static void bcmasp_enable_rx(struct bcmasp_intf *intf, int en) 72 { 73 if (en) 74 rx_edpkt_cfg_wl(intf, RX_EDPKT_CFG_ENABLE_EN, 75 RX_EDPKT_CFG_ENABLE); 76 else 77 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 78 } 79 80 static void bcmasp_set_rx_mode(struct net_device *dev) 81 { 82 unsigned char mask[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 83 struct bcmasp_intf *intf = netdev_priv(dev); 84 struct netdev_hw_addr *ha; 85 int ret; 86 87 spin_lock_bh(&intf->parent->mda_lock); 88 89 bcmasp_disable_all_filters(intf); 90 91 if (dev->flags & IFF_PROMISC) 92 goto set_promisc; 93 94 bcmasp_set_promisc(intf, 0); 95 96 bcmasp_set_broad(intf, 1); 97 98 bcmasp_set_oaddr(intf, dev->dev_addr, 1); 99 100 if (dev->flags & IFF_ALLMULTI) { 101 bcmasp_set_allmulti(intf, 1); 102 } else { 103 bcmasp_set_allmulti(intf, 0); 104 105 netdev_for_each_mc_addr(ha, dev) { 106 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 107 if (ret) { 108 intf->mib.mc_filters_full_cnt++; 109 goto set_promisc; 110 } 111 } 112 } 113 114 netdev_for_each_uc_addr(ha, dev) { 115 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 116 if (ret) { 117 intf->mib.uc_filters_full_cnt++; 118 goto set_promisc; 119 } 120 } 121 122 spin_unlock_bh(&intf->parent->mda_lock); 123 return; 124 125 set_promisc: 126 bcmasp_set_promisc(intf, 1); 127 intf->mib.promisc_filters_cnt++; 128 129 /* disable all filters used by this port */ 130 bcmasp_disable_all_filters(intf); 131 132 spin_unlock_bh(&intf->parent->mda_lock); 133 } 134 135 static void bcmasp_clean_txcb(struct bcmasp_intf *intf, int index) 136 { 137 struct bcmasp_tx_cb *txcb = &intf->tx_cbs[index]; 138 139 txcb->skb = NULL; 140 dma_unmap_addr_set(txcb, dma_addr, 0); 141 dma_unmap_len_set(txcb, dma_len, 0); 142 txcb->last = false; 143 } 144 145 static int tx_spb_ring_full(struct bcmasp_intf *intf, int cnt) 146 { 147 int next_index, i; 148 149 /* Check if we have enough room for cnt descriptors */ 150 for (i = 0; i < cnt; i++) { 151 next_index = incr_ring(intf->tx_spb_index, DESC_RING_COUNT); 152 if (next_index == intf->tx_spb_clean_index) 153 return 1; 154 } 155 156 return 0; 157 } 158 159 static struct sk_buff *bcmasp_csum_offload(struct net_device *dev, 160 struct sk_buff *skb, 161 bool *csum_hw) 162 { 163 struct bcmasp_intf *intf = netdev_priv(dev); 164 u32 header = 0, header2 = 0, epkt = 0; 165 struct bcmasp_pkt_offload *offload; 166 unsigned int header_cnt = 0; 167 u8 ip_proto; 168 int ret; 169 170 if (skb->ip_summed != CHECKSUM_PARTIAL) 171 return skb; 172 173 ret = skb_cow_head(skb, sizeof(*offload)); 174 if (ret < 0) { 175 intf->mib.tx_realloc_offload_failed++; 176 goto help; 177 } 178 179 switch (skb->protocol) { 180 case htons(ETH_P_IP): 181 header |= PKT_OFFLOAD_HDR_SIZE_2((ip_hdrlen(skb) >> 8) & 0xf); 182 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(ip_hdrlen(skb) & 0xff); 183 epkt |= PKT_OFFLOAD_EPKT_IP(0) | PKT_OFFLOAD_EPKT_CSUM_L2; 184 ip_proto = ip_hdr(skb)->protocol; 185 header_cnt += 2; 186 break; 187 case htons(ETH_P_IPV6): 188 header |= PKT_OFFLOAD_HDR_SIZE_2((IP6_HLEN >> 8) & 0xf); 189 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(IP6_HLEN & 0xff); 190 epkt |= PKT_OFFLOAD_EPKT_IP(1) | PKT_OFFLOAD_EPKT_CSUM_L2; 191 ip_proto = ipv6_hdr(skb)->nexthdr; 192 header_cnt += 2; 193 break; 194 default: 195 goto help; 196 } 197 198 switch (ip_proto) { 199 case IPPROTO_TCP: 200 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(tcp_hdrlen(skb)); 201 epkt |= PKT_OFFLOAD_EPKT_TP(0) | PKT_OFFLOAD_EPKT_CSUM_L3; 202 header_cnt++; 203 break; 204 case IPPROTO_UDP: 205 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(UDP_HLEN); 206 epkt |= PKT_OFFLOAD_EPKT_TP(1) | PKT_OFFLOAD_EPKT_CSUM_L3; 207 header_cnt++; 208 break; 209 default: 210 goto help; 211 } 212 213 offload = (struct bcmasp_pkt_offload *)skb_push(skb, sizeof(*offload)); 214 215 header |= PKT_OFFLOAD_HDR_OP | PKT_OFFLOAD_HDR_COUNT(header_cnt) | 216 PKT_OFFLOAD_HDR_SIZE_1(ETH_HLEN); 217 epkt |= PKT_OFFLOAD_EPKT_OP; 218 219 offload->nop = htonl(PKT_OFFLOAD_NOP); 220 offload->header = htonl(header); 221 offload->header2 = htonl(header2); 222 offload->epkt = htonl(epkt); 223 offload->end = htonl(PKT_OFFLOAD_END_OP); 224 *csum_hw = true; 225 226 return skb; 227 228 help: 229 skb_checksum_help(skb); 230 231 return skb; 232 } 233 234 static unsigned long bcmasp_rx_edpkt_dma_rq(struct bcmasp_intf *intf) 235 { 236 return rx_edpkt_dma_rq(intf, RX_EDPKT_DMA_VALID); 237 } 238 239 static void bcmasp_rx_edpkt_cfg_wq(struct bcmasp_intf *intf, dma_addr_t addr) 240 { 241 rx_edpkt_cfg_wq(intf, addr, RX_EDPKT_RING_BUFFER_READ); 242 } 243 244 static void bcmasp_rx_edpkt_dma_wq(struct bcmasp_intf *intf, dma_addr_t addr) 245 { 246 rx_edpkt_dma_wq(intf, addr, RX_EDPKT_DMA_READ); 247 } 248 249 static unsigned long bcmasp_tx_spb_dma_rq(struct bcmasp_intf *intf) 250 { 251 return tx_spb_dma_rq(intf, TX_SPB_DMA_READ); 252 } 253 254 static void bcmasp_tx_spb_dma_wq(struct bcmasp_intf *intf, dma_addr_t addr) 255 { 256 tx_spb_dma_wq(intf, addr, TX_SPB_DMA_VALID); 257 } 258 259 static const struct bcmasp_intf_ops bcmasp_intf_ops = { 260 .rx_desc_read = bcmasp_rx_edpkt_dma_rq, 261 .rx_buffer_write = bcmasp_rx_edpkt_cfg_wq, 262 .rx_desc_write = bcmasp_rx_edpkt_dma_wq, 263 .tx_read = bcmasp_tx_spb_dma_rq, 264 .tx_write = bcmasp_tx_spb_dma_wq, 265 }; 266 267 static netdev_tx_t bcmasp_xmit(struct sk_buff *skb, struct net_device *dev) 268 { 269 struct bcmasp_intf *intf = netdev_priv(dev); 270 unsigned int total_bytes, size; 271 int spb_index, nr_frags, i, j; 272 struct bcmasp_tx_cb *txcb; 273 dma_addr_t mapping, valid; 274 struct bcmasp_desc *desc; 275 bool csum_hw = false; 276 struct device *kdev; 277 skb_frag_t *frag; 278 279 kdev = &intf->parent->pdev->dev; 280 281 nr_frags = skb_shinfo(skb)->nr_frags; 282 283 if (tx_spb_ring_full(intf, nr_frags + 1)) { 284 netif_stop_queue(dev); 285 if (net_ratelimit()) 286 netdev_err(dev, "Tx Ring Full!\n"); 287 return NETDEV_TX_BUSY; 288 } 289 290 /* Save skb len before adding csum offload header */ 291 total_bytes = skb->len; 292 skb = bcmasp_csum_offload(dev, skb, &csum_hw); 293 if (!skb) 294 return NETDEV_TX_OK; 295 296 spb_index = intf->tx_spb_index; 297 valid = intf->tx_spb_dma_valid; 298 for (i = 0; i <= nr_frags; i++) { 299 if (!i) { 300 size = skb_headlen(skb); 301 if (!nr_frags && size < (ETH_ZLEN + ETH_FCS_LEN)) { 302 if (skb_put_padto(skb, ETH_ZLEN + ETH_FCS_LEN)) 303 return NETDEV_TX_OK; 304 size = skb->len; 305 } 306 mapping = dma_map_single(kdev, skb->data, size, 307 DMA_TO_DEVICE); 308 } else { 309 frag = &skb_shinfo(skb)->frags[i - 1]; 310 size = skb_frag_size(frag); 311 mapping = skb_frag_dma_map(kdev, frag, 0, size, 312 DMA_TO_DEVICE); 313 } 314 315 if (dma_mapping_error(kdev, mapping)) { 316 intf->mib.tx_dma_failed++; 317 spb_index = intf->tx_spb_index; 318 for (j = 0; j < i; j++) { 319 bcmasp_clean_txcb(intf, spb_index); 320 spb_index = incr_ring(spb_index, 321 DESC_RING_COUNT); 322 } 323 /* Rewind so we do not have a hole */ 324 spb_index = intf->tx_spb_index; 325 return NETDEV_TX_OK; 326 } 327 328 txcb = &intf->tx_cbs[spb_index]; 329 desc = &intf->tx_spb_cpu[spb_index]; 330 memset(desc, 0, sizeof(*desc)); 331 txcb->skb = skb; 332 txcb->bytes_sent = total_bytes; 333 dma_unmap_addr_set(txcb, dma_addr, mapping); 334 dma_unmap_len_set(txcb, dma_len, size); 335 if (!i) { 336 desc->flags |= DESC_SOF; 337 if (csum_hw) 338 desc->flags |= DESC_EPKT_CMD; 339 } 340 341 if (i == nr_frags) { 342 desc->flags |= DESC_EOF; 343 txcb->last = true; 344 } 345 346 desc->buf = mapping; 347 desc->size = size; 348 desc->flags |= DESC_INT_EN; 349 350 netif_dbg(intf, tx_queued, dev, 351 "%s dma_buf=%pad dma_len=0x%x flags=0x%x index=0x%x\n", 352 __func__, &mapping, desc->size, desc->flags, 353 spb_index); 354 355 spb_index = incr_ring(spb_index, DESC_RING_COUNT); 356 valid = incr_last_byte(valid, intf->tx_spb_dma_addr, 357 DESC_RING_COUNT); 358 } 359 360 /* Ensure all descriptors have been written to DRAM for the 361 * hardware to see up-to-date contents. 362 */ 363 wmb(); 364 365 intf->tx_spb_index = spb_index; 366 intf->tx_spb_dma_valid = valid; 367 bcmasp_intf_tx_write(intf, intf->tx_spb_dma_valid); 368 369 if (tx_spb_ring_full(intf, MAX_SKB_FRAGS + 1)) 370 netif_stop_queue(dev); 371 372 return NETDEV_TX_OK; 373 } 374 375 static void bcmasp_netif_start(struct net_device *dev) 376 { 377 struct bcmasp_intf *intf = netdev_priv(dev); 378 379 bcmasp_set_rx_mode(dev); 380 napi_enable(&intf->tx_napi); 381 napi_enable(&intf->rx_napi); 382 383 bcmasp_enable_rx_irq(intf, 1); 384 bcmasp_enable_tx_irq(intf, 1); 385 386 phy_start(dev->phydev); 387 } 388 389 static void umac_reset(struct bcmasp_intf *intf) 390 { 391 umac_wl(intf, 0x0, UMC_CMD); 392 umac_wl(intf, UMC_CMD_SW_RESET, UMC_CMD); 393 usleep_range(10, 100); 394 /* We hold the umac in reset and bring it out of 395 * reset when phy link is up. 396 */ 397 } 398 399 static void umac_set_hw_addr(struct bcmasp_intf *intf, 400 const unsigned char *addr) 401 { 402 u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | 403 addr[3]; 404 u32 mac1 = (addr[4] << 8) | addr[5]; 405 406 umac_wl(intf, mac0, UMC_MAC0); 407 umac_wl(intf, mac1, UMC_MAC1); 408 } 409 410 static void umac_enable_set(struct bcmasp_intf *intf, u32 mask, 411 unsigned int enable) 412 { 413 u32 reg; 414 415 reg = umac_rl(intf, UMC_CMD); 416 if (reg & UMC_CMD_SW_RESET) 417 return; 418 if (enable) 419 reg |= mask; 420 else 421 reg &= ~mask; 422 umac_wl(intf, reg, UMC_CMD); 423 424 /* UniMAC stops on a packet boundary, wait for a full-sized packet 425 * to be processed (1 msec). 426 */ 427 if (enable == 0) 428 usleep_range(1000, 2000); 429 } 430 431 static void umac_init(struct bcmasp_intf *intf) 432 { 433 umac_wl(intf, 0x800, UMC_FRM_LEN); 434 umac_wl(intf, 0xffff, UMC_PAUSE_CNTRL); 435 umac_wl(intf, 0x800, UMC_RX_MAX_PKT_SZ); 436 } 437 438 static int bcmasp_tx_poll(struct napi_struct *napi, int budget) 439 { 440 struct bcmasp_intf *intf = 441 container_of(napi, struct bcmasp_intf, tx_napi); 442 struct bcmasp_intf_stats64 *stats = &intf->stats64; 443 struct device *kdev = &intf->parent->pdev->dev; 444 unsigned long read, released = 0; 445 struct bcmasp_tx_cb *txcb; 446 struct bcmasp_desc *desc; 447 dma_addr_t mapping; 448 449 read = bcmasp_intf_tx_read(intf); 450 while (intf->tx_spb_dma_read != read) { 451 txcb = &intf->tx_cbs[intf->tx_spb_clean_index]; 452 mapping = dma_unmap_addr(txcb, dma_addr); 453 454 dma_unmap_single(kdev, mapping, 455 dma_unmap_len(txcb, dma_len), 456 DMA_TO_DEVICE); 457 458 if (txcb->last) { 459 dev_consume_skb_any(txcb->skb); 460 461 u64_stats_update_begin(&stats->syncp); 462 u64_stats_inc(&stats->tx_packets); 463 u64_stats_add(&stats->tx_bytes, txcb->bytes_sent); 464 u64_stats_update_end(&stats->syncp); 465 } 466 467 desc = &intf->tx_spb_cpu[intf->tx_spb_clean_index]; 468 469 netif_dbg(intf, tx_done, intf->ndev, 470 "%s dma_buf=%pad dma_len=0x%x flags=0x%x c_index=0x%x\n", 471 __func__, &mapping, desc->size, desc->flags, 472 intf->tx_spb_clean_index); 473 474 bcmasp_clean_txcb(intf, intf->tx_spb_clean_index); 475 released++; 476 477 intf->tx_spb_clean_index = incr_ring(intf->tx_spb_clean_index, 478 DESC_RING_COUNT); 479 intf->tx_spb_dma_read = incr_first_byte(intf->tx_spb_dma_read, 480 intf->tx_spb_dma_addr, 481 DESC_RING_COUNT); 482 } 483 484 /* Ensure all descriptors have been written to DRAM for the hardware 485 * to see updated contents. 486 */ 487 wmb(); 488 489 napi_complete(&intf->tx_napi); 490 491 bcmasp_enable_tx_irq(intf, 1); 492 493 if (released) 494 netif_wake_queue(intf->ndev); 495 496 return 0; 497 } 498 499 static int bcmasp_rx_poll(struct napi_struct *napi, int budget) 500 { 501 struct bcmasp_intf *intf = 502 container_of(napi, struct bcmasp_intf, rx_napi); 503 struct bcmasp_intf_stats64 *stats = &intf->stats64; 504 struct device *kdev = &intf->parent->pdev->dev; 505 unsigned long processed = 0; 506 struct bcmasp_desc *desc; 507 struct sk_buff *skb; 508 dma_addr_t valid; 509 void *data; 510 u64 flags; 511 u32 len; 512 513 valid = bcmasp_intf_rx_desc_read(intf) + 1; 514 if (valid == intf->rx_edpkt_dma_addr + DESC_RING_SIZE) 515 valid = intf->rx_edpkt_dma_addr; 516 517 while ((processed < budget) && (valid != intf->rx_edpkt_dma_read)) { 518 desc = &intf->rx_edpkt_cpu[intf->rx_edpkt_index]; 519 520 /* Ensure that descriptor has been fully written to DRAM by 521 * hardware before reading by the CPU 522 */ 523 rmb(); 524 525 /* Calculate virt addr by offsetting from physical addr */ 526 data = intf->rx_ring_cpu + 527 (DESC_ADDR(desc->buf) - intf->rx_ring_dma); 528 529 flags = DESC_FLAGS(desc->buf); 530 if (unlikely(flags & (DESC_CRC_ERR | DESC_RX_SYM_ERR))) { 531 if (net_ratelimit()) { 532 netif_err(intf, rx_status, intf->ndev, 533 "flags=0x%llx\n", flags); 534 } 535 536 u64_stats_update_begin(&stats->syncp); 537 if (flags & DESC_CRC_ERR) 538 u64_stats_inc(&stats->rx_crc_errs); 539 if (flags & DESC_RX_SYM_ERR) 540 u64_stats_inc(&stats->rx_sym_errs); 541 u64_stats_update_end(&stats->syncp); 542 543 goto next; 544 } 545 546 dma_sync_single_for_cpu(kdev, DESC_ADDR(desc->buf), desc->size, 547 DMA_FROM_DEVICE); 548 549 len = desc->size; 550 551 skb = napi_alloc_skb(napi, len); 552 if (!skb) { 553 u64_stats_update_begin(&stats->syncp); 554 u64_stats_inc(&stats->rx_dropped); 555 u64_stats_update_end(&stats->syncp); 556 intf->mib.alloc_rx_skb_failed++; 557 558 goto next; 559 } 560 561 skb_put(skb, len); 562 memcpy(skb->data, data, len); 563 564 skb_pull(skb, 2); 565 len -= 2; 566 if (likely(intf->crc_fwd)) { 567 skb_trim(skb, len - ETH_FCS_LEN); 568 len -= ETH_FCS_LEN; 569 } 570 571 if ((intf->ndev->features & NETIF_F_RXCSUM) && 572 (desc->buf & DESC_CHKSUM)) 573 skb->ip_summed = CHECKSUM_UNNECESSARY; 574 575 skb->protocol = eth_type_trans(skb, intf->ndev); 576 577 napi_gro_receive(napi, skb); 578 579 u64_stats_update_begin(&stats->syncp); 580 u64_stats_inc(&stats->rx_packets); 581 u64_stats_add(&stats->rx_bytes, len); 582 u64_stats_update_end(&stats->syncp); 583 584 next: 585 bcmasp_intf_rx_buffer_write(intf, (DESC_ADDR(desc->buf) + 586 desc->size)); 587 588 processed++; 589 intf->rx_edpkt_dma_read = 590 incr_first_byte(intf->rx_edpkt_dma_read, 591 intf->rx_edpkt_dma_addr, 592 DESC_RING_COUNT); 593 intf->rx_edpkt_index = incr_ring(intf->rx_edpkt_index, 594 DESC_RING_COUNT); 595 } 596 597 bcmasp_intf_rx_desc_write(intf, intf->rx_edpkt_dma_read); 598 599 if (processed < budget) { 600 napi_complete_done(&intf->rx_napi, processed); 601 bcmasp_enable_rx_irq(intf, 1); 602 } 603 604 return processed; 605 } 606 607 static void bcmasp_adj_link(struct net_device *dev) 608 { 609 struct bcmasp_intf *intf = netdev_priv(dev); 610 struct phy_device *phydev = dev->phydev; 611 u32 cmd_bits = 0, reg; 612 int changed = 0; 613 614 if (intf->old_link != phydev->link) { 615 changed = 1; 616 intf->old_link = phydev->link; 617 } 618 619 if (intf->old_duplex != phydev->duplex) { 620 changed = 1; 621 intf->old_duplex = phydev->duplex; 622 } 623 624 switch (phydev->speed) { 625 case SPEED_2500: 626 cmd_bits = UMC_CMD_SPEED_2500; 627 break; 628 case SPEED_1000: 629 cmd_bits = UMC_CMD_SPEED_1000; 630 break; 631 case SPEED_100: 632 cmd_bits = UMC_CMD_SPEED_100; 633 break; 634 case SPEED_10: 635 cmd_bits = UMC_CMD_SPEED_10; 636 break; 637 default: 638 break; 639 } 640 cmd_bits <<= UMC_CMD_SPEED_SHIFT; 641 642 if (phydev->duplex == DUPLEX_HALF) 643 cmd_bits |= UMC_CMD_HD_EN; 644 645 if (intf->old_pause != phydev->pause) { 646 changed = 1; 647 intf->old_pause = phydev->pause; 648 } 649 650 if (!phydev->pause) 651 cmd_bits |= UMC_CMD_RX_PAUSE_IGNORE | UMC_CMD_TX_PAUSE_IGNORE; 652 653 if (!changed) 654 return; 655 656 if (phydev->link) { 657 reg = umac_rl(intf, UMC_CMD); 658 reg &= ~((UMC_CMD_SPEED_MASK << UMC_CMD_SPEED_SHIFT) | 659 UMC_CMD_HD_EN | UMC_CMD_RX_PAUSE_IGNORE | 660 UMC_CMD_TX_PAUSE_IGNORE); 661 reg |= cmd_bits; 662 if (reg & UMC_CMD_SW_RESET) { 663 reg &= ~UMC_CMD_SW_RESET; 664 umac_wl(intf, reg, UMC_CMD); 665 udelay(2); 666 reg |= UMC_CMD_TX_EN | UMC_CMD_RX_EN | UMC_CMD_PROMISC; 667 } 668 umac_wl(intf, reg, UMC_CMD); 669 670 intf->eee.eee_active = phy_init_eee(phydev, 0) >= 0; 671 bcmasp_eee_enable_set(intf, intf->eee.eee_active); 672 } 673 674 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 675 if (phydev->link) 676 reg |= RGMII_LINK; 677 else 678 reg &= ~RGMII_LINK; 679 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 680 681 if (changed) 682 phy_print_status(phydev); 683 } 684 685 static int bcmasp_init_rx(struct bcmasp_intf *intf) 686 { 687 struct device *kdev = &intf->parent->pdev->dev; 688 struct page *buffer_pg; 689 dma_addr_t dma; 690 void *p; 691 u32 reg; 692 int ret; 693 694 intf->rx_buf_order = get_order(RING_BUFFER_SIZE); 695 buffer_pg = alloc_pages(GFP_KERNEL, intf->rx_buf_order); 696 697 dma = dma_map_page(kdev, buffer_pg, 0, RING_BUFFER_SIZE, 698 DMA_FROM_DEVICE); 699 if (dma_mapping_error(kdev, dma)) { 700 __free_pages(buffer_pg, intf->rx_buf_order); 701 return -ENOMEM; 702 } 703 intf->rx_ring_cpu = page_to_virt(buffer_pg); 704 intf->rx_ring_dma = dma; 705 intf->rx_ring_dma_valid = intf->rx_ring_dma + RING_BUFFER_SIZE - 1; 706 707 p = dma_alloc_coherent(kdev, DESC_RING_SIZE, &intf->rx_edpkt_dma_addr, 708 GFP_KERNEL); 709 if (!p) { 710 ret = -ENOMEM; 711 goto free_rx_ring; 712 } 713 intf->rx_edpkt_cpu = p; 714 715 netif_napi_add(intf->ndev, &intf->rx_napi, bcmasp_rx_poll); 716 717 intf->rx_edpkt_dma_read = intf->rx_edpkt_dma_addr; 718 intf->rx_edpkt_index = 0; 719 720 /* Make sure channels are disabled */ 721 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 722 723 /* Rx SPB */ 724 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_READ); 725 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_WRITE); 726 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_BASE); 727 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 728 RX_EDPKT_RING_BUFFER_END); 729 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 730 RX_EDPKT_RING_BUFFER_VALID); 731 732 /* EDPKT */ 733 rx_edpkt_cfg_wl(intf, (RX_EDPKT_CFG_CFG0_RBUF_4K << 734 RX_EDPKT_CFG_CFG0_DBUF_SHIFT) | 735 (RX_EDPKT_CFG_CFG0_64_ALN << 736 RX_EDPKT_CFG_CFG0_BALN_SHIFT) | 737 (RX_EDPKT_CFG_CFG0_EFRM_STUF), 738 RX_EDPKT_CFG_CFG0); 739 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_WRITE); 740 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_READ); 741 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_BASE); 742 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr + (DESC_RING_SIZE - 1), 743 RX_EDPKT_DMA_END); 744 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr + (DESC_RING_SIZE - 1), 745 RX_EDPKT_DMA_VALID); 746 747 reg = UMAC2FB_CFG_DEFAULT_EN | 748 ((intf->channel + 11) << UMAC2FB_CFG_CHID_SHIFT); 749 reg |= (0xd << UMAC2FB_CFG_OK_SEND_SHIFT); 750 umac2fb_wl(intf, reg, UMAC2FB_CFG); 751 752 return 0; 753 754 free_rx_ring: 755 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 756 DMA_FROM_DEVICE); 757 __free_pages(virt_to_page(intf->rx_ring_cpu), intf->rx_buf_order); 758 759 return ret; 760 } 761 762 static void bcmasp_reclaim_free_all_rx(struct bcmasp_intf *intf) 763 { 764 struct device *kdev = &intf->parent->pdev->dev; 765 766 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 767 intf->rx_edpkt_dma_addr); 768 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 769 DMA_FROM_DEVICE); 770 __free_pages(virt_to_page(intf->rx_ring_cpu), intf->rx_buf_order); 771 } 772 773 static int bcmasp_init_tx(struct bcmasp_intf *intf) 774 { 775 struct device *kdev = &intf->parent->pdev->dev; 776 void *p; 777 int ret; 778 779 p = dma_alloc_coherent(kdev, DESC_RING_SIZE, &intf->tx_spb_dma_addr, 780 GFP_KERNEL); 781 if (!p) 782 return -ENOMEM; 783 784 intf->tx_spb_cpu = p; 785 intf->tx_spb_dma_valid = intf->tx_spb_dma_addr + DESC_RING_SIZE - 1; 786 intf->tx_spb_dma_read = intf->tx_spb_dma_addr; 787 788 intf->tx_cbs = kcalloc(DESC_RING_COUNT, sizeof(struct bcmasp_tx_cb), 789 GFP_KERNEL); 790 if (!intf->tx_cbs) { 791 ret = -ENOMEM; 792 goto free_tx_spb; 793 } 794 795 intf->tx_spb_index = 0; 796 intf->tx_spb_clean_index = 0; 797 798 netif_napi_add_tx(intf->ndev, &intf->tx_napi, bcmasp_tx_poll); 799 800 /* Make sure channels are disabled */ 801 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 802 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 803 804 /* Tx SPB */ 805 tx_spb_ctrl_wl(intf, ((intf->channel + 8) << TX_SPB_CTRL_XF_BID_SHIFT), 806 TX_SPB_CTRL_XF_CTRL2); 807 tx_pause_ctrl_wl(intf, (1 << (intf->channel + 8)), TX_PAUSE_MAP_VECTOR); 808 tx_spb_top_wl(intf, 0x1e, TX_SPB_TOP_BLKOUT); 809 tx_spb_top_wl(intf, 0x0, TX_SPB_TOP_SPRE_BW_CTRL); 810 811 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_READ); 812 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_BASE); 813 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_END); 814 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID); 815 816 return 0; 817 818 free_tx_spb: 819 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 820 intf->tx_spb_dma_addr); 821 822 return ret; 823 } 824 825 static void bcmasp_reclaim_free_all_tx(struct bcmasp_intf *intf) 826 { 827 struct device *kdev = &intf->parent->pdev->dev; 828 829 /* Free descriptors */ 830 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 831 intf->tx_spb_dma_addr); 832 833 /* Free cbs */ 834 kfree(intf->tx_cbs); 835 } 836 837 static void bcmasp_ephy_enable_set(struct bcmasp_intf *intf, bool enable) 838 { 839 u32 mask = RGMII_EPHY_CFG_IDDQ_BIAS | RGMII_EPHY_CFG_EXT_PWRDOWN | 840 RGMII_EPHY_CFG_IDDQ_GLOBAL; 841 u32 reg; 842 843 reg = rgmii_rl(intf, RGMII_EPHY_CNTRL); 844 if (enable) { 845 reg &= ~RGMII_EPHY_CK25_DIS; 846 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 847 mdelay(1); 848 849 reg &= ~mask; 850 reg |= RGMII_EPHY_RESET; 851 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 852 mdelay(1); 853 854 reg &= ~RGMII_EPHY_RESET; 855 } else { 856 reg |= mask | RGMII_EPHY_RESET; 857 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 858 mdelay(1); 859 reg |= RGMII_EPHY_CK25_DIS; 860 } 861 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 862 mdelay(1); 863 864 /* Set or clear the LED control override to avoid lighting up LEDs 865 * while the EPHY is powered off and drawing unnecessary current. 866 */ 867 reg = rgmii_rl(intf, RGMII_SYS_LED_CNTRL); 868 if (enable) 869 reg &= ~RGMII_SYS_LED_CNTRL_LINK_OVRD; 870 else 871 reg |= RGMII_SYS_LED_CNTRL_LINK_OVRD; 872 rgmii_wl(intf, reg, RGMII_SYS_LED_CNTRL); 873 } 874 875 static void bcmasp_rgmii_mode_en_set(struct bcmasp_intf *intf, bool enable) 876 { 877 u32 reg; 878 879 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 880 reg &= ~RGMII_OOB_DIS; 881 if (enable) 882 reg |= RGMII_MODE_EN; 883 else 884 reg &= ~RGMII_MODE_EN; 885 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 886 } 887 888 static void bcmasp_netif_deinit(struct net_device *dev) 889 { 890 struct bcmasp_intf *intf = netdev_priv(dev); 891 u32 reg, timeout = 1000; 892 893 napi_disable(&intf->tx_napi); 894 895 bcmasp_enable_tx(intf, 0); 896 897 /* Flush any TX packets in the pipe */ 898 tx_spb_dma_wl(intf, TX_SPB_DMA_FIFO_FLUSH, TX_SPB_DMA_FIFO_CTRL); 899 do { 900 reg = tx_spb_dma_rl(intf, TX_SPB_DMA_FIFO_STATUS); 901 if (!(reg & TX_SPB_DMA_FIFO_FLUSH)) 902 break; 903 usleep_range(1000, 2000); 904 } while (timeout-- > 0); 905 tx_spb_dma_wl(intf, 0x0, TX_SPB_DMA_FIFO_CTRL); 906 907 umac_enable_set(intf, UMC_CMD_TX_EN, 0); 908 909 phy_stop(dev->phydev); 910 911 umac_enable_set(intf, UMC_CMD_RX_EN, 0); 912 913 bcmasp_flush_rx_port(intf); 914 usleep_range(1000, 2000); 915 bcmasp_enable_rx(intf, 0); 916 917 napi_disable(&intf->rx_napi); 918 919 /* Disable interrupts */ 920 bcmasp_enable_tx_irq(intf, 0); 921 bcmasp_enable_rx_irq(intf, 0); 922 923 netif_napi_del(&intf->tx_napi); 924 bcmasp_reclaim_free_all_tx(intf); 925 926 netif_napi_del(&intf->rx_napi); 927 bcmasp_reclaim_free_all_rx(intf); 928 } 929 930 static int bcmasp_stop(struct net_device *dev) 931 { 932 struct bcmasp_intf *intf = netdev_priv(dev); 933 934 netif_dbg(intf, ifdown, dev, "bcmasp stop\n"); 935 936 /* Stop tx from updating HW */ 937 netif_tx_disable(dev); 938 939 bcmasp_netif_deinit(dev); 940 941 phy_disconnect(dev->phydev); 942 943 /* Disable internal EPHY or external PHY */ 944 if (intf->internal_phy) 945 bcmasp_ephy_enable_set(intf, false); 946 else 947 bcmasp_rgmii_mode_en_set(intf, false); 948 949 /* Disable the interface clocks */ 950 bcmasp_core_clock_set_intf(intf, false); 951 952 clk_disable_unprepare(intf->parent->clk); 953 954 return 0; 955 } 956 957 static void bcmasp_configure_port(struct bcmasp_intf *intf) 958 { 959 u32 reg, id_mode_dis = 0; 960 961 reg = rgmii_rl(intf, RGMII_PORT_CNTRL); 962 reg &= ~RGMII_PORT_MODE_MASK; 963 964 switch (intf->phy_interface) { 965 case PHY_INTERFACE_MODE_RGMII: 966 /* RGMII_NO_ID: TXC transitions at the same time as TXD 967 * (requires PCB or receiver-side delay) 968 * RGMII: Add 2ns delay on TXC (90 degree shift) 969 * 970 * ID is implicitly disabled for 100Mbps (RG)MII operation. 971 */ 972 id_mode_dis = RGMII_ID_MODE_DIS; 973 fallthrough; 974 case PHY_INTERFACE_MODE_RGMII_TXID: 975 reg |= RGMII_PORT_MODE_EXT_GPHY; 976 break; 977 case PHY_INTERFACE_MODE_MII: 978 reg |= RGMII_PORT_MODE_EXT_EPHY; 979 break; 980 default: 981 break; 982 } 983 984 if (intf->internal_phy) 985 reg |= RGMII_PORT_MODE_EPHY; 986 987 rgmii_wl(intf, reg, RGMII_PORT_CNTRL); 988 989 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 990 reg &= ~RGMII_ID_MODE_DIS; 991 reg |= id_mode_dis; 992 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 993 } 994 995 static int bcmasp_netif_init(struct net_device *dev, bool phy_connect) 996 { 997 struct bcmasp_intf *intf = netdev_priv(dev); 998 phy_interface_t phy_iface = intf->phy_interface; 999 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 1000 PHY_BRCM_DIS_TXCRXC_NOENRGY | 1001 PHY_BRCM_IDDQ_SUSPEND; 1002 struct phy_device *phydev = NULL; 1003 int ret; 1004 1005 /* Always enable interface clocks */ 1006 bcmasp_core_clock_set_intf(intf, true); 1007 1008 /* Enable internal PHY or external PHY before any MAC activity */ 1009 if (intf->internal_phy) 1010 bcmasp_ephy_enable_set(intf, true); 1011 else 1012 bcmasp_rgmii_mode_en_set(intf, true); 1013 bcmasp_configure_port(intf); 1014 1015 /* This is an ugly quirk but we have not been correctly 1016 * interpreting the phy_interface values and we have done that 1017 * across different drivers, so at least we are consistent in 1018 * our mistakes. 1019 * 1020 * When the Generic PHY driver is in use either the PHY has 1021 * been strapped or programmed correctly by the boot loader so 1022 * we should stick to our incorrect interpretation since we 1023 * have validated it. 1024 * 1025 * Now when a dedicated PHY driver is in use, we need to 1026 * reverse the meaning of the phy_interface_mode values to 1027 * something that the PHY driver will interpret and act on such 1028 * that we have two mistakes canceling themselves so to speak. 1029 * We only do this for the two modes that GENET driver 1030 * officially supports on Broadcom STB chips: 1031 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. 1032 * Other modes are not *officially* supported with the boot 1033 * loader and the scripted environment generating Device Tree 1034 * blobs for those platforms. 1035 * 1036 * Note that internal PHY and fixed-link configurations are not 1037 * affected because they use different phy_interface_t values 1038 * or the Generic PHY driver. 1039 */ 1040 switch (phy_iface) { 1041 case PHY_INTERFACE_MODE_RGMII: 1042 phy_iface = PHY_INTERFACE_MODE_RGMII_ID; 1043 break; 1044 case PHY_INTERFACE_MODE_RGMII_TXID: 1045 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID; 1046 break; 1047 default: 1048 break; 1049 } 1050 1051 if (phy_connect) { 1052 phydev = of_phy_connect(dev, intf->phy_dn, 1053 bcmasp_adj_link, phy_flags, 1054 phy_iface); 1055 if (!phydev) { 1056 ret = -ENODEV; 1057 netdev_err(dev, "could not attach to PHY\n"); 1058 goto err_phy_disable; 1059 } 1060 1061 /* Indicate that the MAC is responsible for PHY PM */ 1062 phydev->mac_managed_pm = true; 1063 } else if (!intf->wolopts) { 1064 ret = phy_resume(dev->phydev); 1065 if (ret) 1066 goto err_phy_disable; 1067 } 1068 1069 umac_reset(intf); 1070 1071 umac_init(intf); 1072 1073 umac_set_hw_addr(intf, dev->dev_addr); 1074 1075 intf->old_duplex = -1; 1076 intf->old_link = -1; 1077 intf->old_pause = -1; 1078 1079 ret = bcmasp_init_tx(intf); 1080 if (ret) 1081 goto err_phy_disconnect; 1082 1083 /* Turn on asp */ 1084 bcmasp_enable_tx(intf, 1); 1085 1086 ret = bcmasp_init_rx(intf); 1087 if (ret) 1088 goto err_reclaim_tx; 1089 1090 bcmasp_enable_rx(intf, 1); 1091 1092 intf->crc_fwd = !!(umac_rl(intf, UMC_CMD) & UMC_CMD_CRC_FWD); 1093 1094 bcmasp_netif_start(dev); 1095 1096 netif_start_queue(dev); 1097 1098 return 0; 1099 1100 err_reclaim_tx: 1101 bcmasp_reclaim_free_all_tx(intf); 1102 err_phy_disconnect: 1103 if (phydev) 1104 phy_disconnect(phydev); 1105 err_phy_disable: 1106 if (intf->internal_phy) 1107 bcmasp_ephy_enable_set(intf, false); 1108 else 1109 bcmasp_rgmii_mode_en_set(intf, false); 1110 return ret; 1111 } 1112 1113 static int bcmasp_open(struct net_device *dev) 1114 { 1115 struct bcmasp_intf *intf = netdev_priv(dev); 1116 int ret; 1117 1118 netif_dbg(intf, ifup, dev, "bcmasp open\n"); 1119 1120 ret = clk_prepare_enable(intf->parent->clk); 1121 if (ret) 1122 return ret; 1123 1124 ret = bcmasp_netif_init(dev, true); 1125 if (ret) 1126 clk_disable_unprepare(intf->parent->clk); 1127 1128 return ret; 1129 } 1130 1131 static void bcmasp_tx_timeout(struct net_device *dev, unsigned int txqueue) 1132 { 1133 struct bcmasp_intf *intf = netdev_priv(dev); 1134 1135 netif_dbg(intf, tx_err, dev, "transmit timeout!\n"); 1136 intf->mib.tx_timeout_cnt++; 1137 } 1138 1139 static int bcmasp_get_phys_port_name(struct net_device *dev, 1140 char *name, size_t len) 1141 { 1142 struct bcmasp_intf *intf = netdev_priv(dev); 1143 1144 if (snprintf(name, len, "p%d", intf->port) >= len) 1145 return -EINVAL; 1146 1147 return 0; 1148 } 1149 1150 static void bcmasp_get_stats64(struct net_device *dev, 1151 struct rtnl_link_stats64 *stats) 1152 { 1153 struct bcmasp_intf *intf = netdev_priv(dev); 1154 struct bcmasp_intf_stats64 *lstats; 1155 unsigned int start; 1156 1157 lstats = &intf->stats64; 1158 1159 do { 1160 start = u64_stats_fetch_begin(&lstats->syncp); 1161 stats->rx_packets = u64_stats_read(&lstats->rx_packets); 1162 stats->rx_bytes = u64_stats_read(&lstats->rx_bytes); 1163 stats->rx_dropped = u64_stats_read(&lstats->rx_dropped); 1164 stats->rx_crc_errors = u64_stats_read(&lstats->rx_crc_errs); 1165 stats->rx_frame_errors = u64_stats_read(&lstats->rx_sym_errs); 1166 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors; 1167 1168 stats->tx_packets = u64_stats_read(&lstats->tx_packets); 1169 stats->tx_bytes = u64_stats_read(&lstats->tx_bytes); 1170 } while (u64_stats_fetch_retry(&lstats->syncp, start)); 1171 } 1172 1173 static const struct net_device_ops bcmasp_netdev_ops = { 1174 .ndo_open = bcmasp_open, 1175 .ndo_stop = bcmasp_stop, 1176 .ndo_start_xmit = bcmasp_xmit, 1177 .ndo_tx_timeout = bcmasp_tx_timeout, 1178 .ndo_set_rx_mode = bcmasp_set_rx_mode, 1179 .ndo_get_phys_port_name = bcmasp_get_phys_port_name, 1180 .ndo_eth_ioctl = phy_do_ioctl_running, 1181 .ndo_set_mac_address = eth_mac_addr, 1182 .ndo_get_stats64 = bcmasp_get_stats64, 1183 }; 1184 1185 static void bcmasp_map_res(struct bcmasp_priv *priv, struct bcmasp_intf *intf) 1186 { 1187 /* Per port */ 1188 intf->res.umac = priv->base + UMC_OFFSET(intf); 1189 intf->res.umac2fb = priv->base + (priv->hw_info->umac2fb + 1190 (intf->port * 0x4)); 1191 intf->res.rgmii = priv->base + RGMII_OFFSET(intf); 1192 1193 /* Per ch */ 1194 intf->tx_spb_dma = priv->base + TX_SPB_DMA_OFFSET(intf); 1195 intf->res.tx_spb_ctrl = priv->base + TX_SPB_CTRL_OFFSET(intf); 1196 intf->res.tx_spb_top = priv->base + TX_SPB_TOP_OFFSET(intf); 1197 intf->res.tx_epkt_core = priv->base + TX_EPKT_C_OFFSET(intf); 1198 intf->res.tx_pause_ctrl = priv->base + TX_PAUSE_CTRL_OFFSET(intf); 1199 1200 intf->rx_edpkt_dma = priv->base + RX_EDPKT_DMA_OFFSET(intf); 1201 intf->rx_edpkt_cfg = priv->base + RX_EDPKT_CFG_OFFSET(intf); 1202 } 1203 1204 #define MAX_IRQ_STR_LEN 64 1205 struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv, 1206 struct device_node *ndev_dn, int i) 1207 { 1208 struct device *dev = &priv->pdev->dev; 1209 struct bcmasp_intf *intf; 1210 struct net_device *ndev; 1211 int ch, port, ret; 1212 1213 if (of_property_read_u32(ndev_dn, "reg", &port)) { 1214 dev_warn(dev, "%s: invalid port number\n", ndev_dn->name); 1215 goto err; 1216 } 1217 1218 if (of_property_read_u32(ndev_dn, "brcm,channel", &ch)) { 1219 dev_warn(dev, "%s: invalid ch number\n", ndev_dn->name); 1220 goto err; 1221 } 1222 1223 ndev = alloc_etherdev(sizeof(struct bcmasp_intf)); 1224 if (!ndev) { 1225 dev_warn(dev, "%s: unable to alloc ndev\n", ndev_dn->name); 1226 goto err; 1227 } 1228 intf = netdev_priv(ndev); 1229 1230 intf->parent = priv; 1231 intf->ndev = ndev; 1232 intf->channel = ch; 1233 intf->port = port; 1234 intf->ndev_dn = ndev_dn; 1235 intf->index = i; 1236 1237 ret = of_get_phy_mode(ndev_dn, &intf->phy_interface); 1238 if (ret < 0) { 1239 dev_err(dev, "invalid PHY mode property\n"); 1240 goto err_free_netdev; 1241 } 1242 1243 if (intf->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 1244 intf->internal_phy = true; 1245 1246 intf->phy_dn = of_parse_phandle(ndev_dn, "phy-handle", 0); 1247 if (!intf->phy_dn && of_phy_is_fixed_link(ndev_dn)) { 1248 ret = of_phy_register_fixed_link(ndev_dn); 1249 if (ret) { 1250 dev_warn(dev, "%s: failed to register fixed PHY\n", 1251 ndev_dn->name); 1252 goto err_free_netdev; 1253 } 1254 intf->phy_dn = ndev_dn; 1255 } 1256 1257 /* Map resource */ 1258 bcmasp_map_res(priv, intf); 1259 1260 if ((!phy_interface_mode_is_rgmii(intf->phy_interface) && 1261 intf->phy_interface != PHY_INTERFACE_MODE_MII && 1262 intf->phy_interface != PHY_INTERFACE_MODE_INTERNAL) || 1263 (intf->port != 1 && intf->internal_phy)) { 1264 netdev_err(intf->ndev, "invalid PHY mode: %s for port %d\n", 1265 phy_modes(intf->phy_interface), intf->port); 1266 ret = -EINVAL; 1267 goto err_free_netdev; 1268 } 1269 1270 ret = of_get_ethdev_address(ndev_dn, ndev); 1271 if (ret) { 1272 netdev_warn(ndev, "using random Ethernet MAC\n"); 1273 eth_hw_addr_random(ndev); 1274 } 1275 1276 SET_NETDEV_DEV(ndev, dev); 1277 intf->ops = &bcmasp_intf_ops; 1278 ndev->netdev_ops = &bcmasp_netdev_ops; 1279 ndev->ethtool_ops = &bcmasp_ethtool_ops; 1280 intf->msg_enable = netif_msg_init(-1, NETIF_MSG_DRV | 1281 NETIF_MSG_PROBE | 1282 NETIF_MSG_LINK); 1283 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 1284 NETIF_F_RXCSUM; 1285 ndev->hw_features |= ndev->features; 1286 ndev->needed_headroom += sizeof(struct bcmasp_pkt_offload); 1287 1288 return intf; 1289 1290 err_free_netdev: 1291 free_netdev(ndev); 1292 err: 1293 return NULL; 1294 } 1295 1296 void bcmasp_interface_destroy(struct bcmasp_intf *intf) 1297 { 1298 if (intf->ndev->reg_state == NETREG_REGISTERED) 1299 unregister_netdev(intf->ndev); 1300 if (of_phy_is_fixed_link(intf->ndev_dn)) 1301 of_phy_deregister_fixed_link(intf->ndev_dn); 1302 free_netdev(intf->ndev); 1303 } 1304 1305 static void bcmasp_suspend_to_wol(struct bcmasp_intf *intf) 1306 { 1307 struct net_device *ndev = intf->ndev; 1308 u32 reg; 1309 1310 reg = umac_rl(intf, UMC_MPD_CTRL); 1311 if (intf->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) 1312 reg |= UMC_MPD_CTRL_MPD_EN; 1313 reg &= ~UMC_MPD_CTRL_PSW_EN; 1314 if (intf->wolopts & WAKE_MAGICSECURE) { 1315 /* Program the SecureOn password */ 1316 umac_wl(intf, get_unaligned_be16(&intf->sopass[0]), 1317 UMC_PSW_MS); 1318 umac_wl(intf, get_unaligned_be32(&intf->sopass[2]), 1319 UMC_PSW_LS); 1320 reg |= UMC_MPD_CTRL_PSW_EN; 1321 } 1322 umac_wl(intf, reg, UMC_MPD_CTRL); 1323 1324 if (intf->wolopts & WAKE_FILTER) 1325 bcmasp_netfilt_suspend(intf); 1326 1327 /* Bring UniMAC out of reset if needed and enable RX */ 1328 reg = umac_rl(intf, UMC_CMD); 1329 if (reg & UMC_CMD_SW_RESET) 1330 reg &= ~UMC_CMD_SW_RESET; 1331 1332 reg |= UMC_CMD_RX_EN | UMC_CMD_PROMISC; 1333 umac_wl(intf, reg, UMC_CMD); 1334 1335 umac_enable_set(intf, UMC_CMD_RX_EN, 1); 1336 1337 if (intf->parent->wol_irq > 0) { 1338 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1339 ASP_WAKEUP_INTR2_MASK_CLEAR); 1340 } 1341 1342 netif_dbg(intf, wol, ndev, "entered WOL mode\n"); 1343 } 1344 1345 int bcmasp_interface_suspend(struct bcmasp_intf *intf) 1346 { 1347 struct device *kdev = &intf->parent->pdev->dev; 1348 struct net_device *dev = intf->ndev; 1349 int ret = 0; 1350 1351 if (!netif_running(dev)) 1352 return 0; 1353 1354 netif_device_detach(dev); 1355 1356 bcmasp_netif_deinit(dev); 1357 1358 if (!intf->wolopts) { 1359 ret = phy_suspend(dev->phydev); 1360 if (ret) 1361 goto out; 1362 1363 if (intf->internal_phy) 1364 bcmasp_ephy_enable_set(intf, false); 1365 else 1366 bcmasp_rgmii_mode_en_set(intf, false); 1367 1368 /* If Wake-on-LAN is disabled, we can safely 1369 * disable the network interface clocks. 1370 */ 1371 bcmasp_core_clock_set_intf(intf, false); 1372 } 1373 1374 if (device_may_wakeup(kdev) && intf->wolopts) 1375 bcmasp_suspend_to_wol(intf); 1376 1377 clk_disable_unprepare(intf->parent->clk); 1378 1379 return ret; 1380 1381 out: 1382 bcmasp_netif_init(dev, false); 1383 return ret; 1384 } 1385 1386 static void bcmasp_resume_from_wol(struct bcmasp_intf *intf) 1387 { 1388 u32 reg; 1389 1390 reg = umac_rl(intf, UMC_MPD_CTRL); 1391 reg &= ~UMC_MPD_CTRL_MPD_EN; 1392 umac_wl(intf, reg, UMC_MPD_CTRL); 1393 1394 if (intf->parent->wol_irq > 0) { 1395 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1396 ASP_WAKEUP_INTR2_MASK_SET); 1397 } 1398 } 1399 1400 int bcmasp_interface_resume(struct bcmasp_intf *intf) 1401 { 1402 struct net_device *dev = intf->ndev; 1403 int ret; 1404 1405 if (!netif_running(dev)) 1406 return 0; 1407 1408 ret = clk_prepare_enable(intf->parent->clk); 1409 if (ret) 1410 return ret; 1411 1412 ret = bcmasp_netif_init(dev, false); 1413 if (ret) 1414 goto out; 1415 1416 bcmasp_resume_from_wol(intf); 1417 1418 if (intf->eee.eee_enabled) 1419 bcmasp_eee_enable_set(intf, true); 1420 1421 netif_device_attach(dev); 1422 1423 return 0; 1424 1425 out: 1426 clk_disable_unprepare(intf->parent->clk); 1427 return ret; 1428 } 1429