1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Broadcom STB ASP 2.0 Driver 4 * 5 * Copyright (c) 2023 Broadcom 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/if_vlan.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/platform_device.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_platform.h> 17 #include <linux/clk.h> 18 19 #include "bcmasp.h" 20 #include "bcmasp_intf_defs.h" 21 22 static void _intr2_mask_clear(struct bcmasp_priv *priv, u32 mask) 23 { 24 intr2_core_wl(priv, mask, ASP_INTR2_MASK_CLEAR); 25 priv->irq_mask &= ~mask; 26 } 27 28 static void _intr2_mask_set(struct bcmasp_priv *priv, u32 mask) 29 { 30 intr2_core_wl(priv, mask, ASP_INTR2_MASK_SET); 31 priv->irq_mask |= mask; 32 } 33 34 void bcmasp_enable_tx_irq(struct bcmasp_intf *intf, int en) 35 { 36 struct bcmasp_priv *priv = intf->parent; 37 38 if (en) 39 _intr2_mask_clear(priv, ASP_INTR2_TX_DESC(intf->channel)); 40 else 41 _intr2_mask_set(priv, ASP_INTR2_TX_DESC(intf->channel)); 42 } 43 EXPORT_SYMBOL_GPL(bcmasp_enable_tx_irq); 44 45 void bcmasp_enable_rx_irq(struct bcmasp_intf *intf, int en) 46 { 47 struct bcmasp_priv *priv = intf->parent; 48 49 if (en) 50 _intr2_mask_clear(priv, ASP_INTR2_RX_ECH(intf->channel)); 51 else 52 _intr2_mask_set(priv, ASP_INTR2_RX_ECH(intf->channel)); 53 } 54 EXPORT_SYMBOL_GPL(bcmasp_enable_rx_irq); 55 56 static void bcmasp_intr2_mask_set_all(struct bcmasp_priv *priv) 57 { 58 _intr2_mask_set(priv, 0xffffffff); 59 priv->irq_mask = 0xffffffff; 60 } 61 62 static void bcmasp_intr2_clear_all(struct bcmasp_priv *priv) 63 { 64 intr2_core_wl(priv, 0xffffffff, ASP_INTR2_CLEAR); 65 } 66 67 static void bcmasp_intr2_handling(struct bcmasp_intf *intf, u32 status) 68 { 69 if (status & ASP_INTR2_RX_ECH(intf->channel)) { 70 if (likely(napi_schedule_prep(&intf->rx_napi))) { 71 bcmasp_enable_rx_irq(intf, 0); 72 __napi_schedule_irqoff(&intf->rx_napi); 73 } 74 } 75 76 if (status & ASP_INTR2_TX_DESC(intf->channel)) { 77 if (likely(napi_schedule_prep(&intf->tx_napi))) { 78 bcmasp_enable_tx_irq(intf, 0); 79 __napi_schedule_irqoff(&intf->tx_napi); 80 } 81 } 82 } 83 84 static irqreturn_t bcmasp_isr(int irq, void *data) 85 { 86 struct bcmasp_priv *priv = data; 87 struct bcmasp_intf *intf; 88 u32 status; 89 90 status = intr2_core_rl(priv, ASP_INTR2_STATUS) & 91 ~intr2_core_rl(priv, ASP_INTR2_MASK_STATUS); 92 93 intr2_core_wl(priv, status, ASP_INTR2_CLEAR); 94 95 if (unlikely(status == 0)) { 96 dev_warn(&priv->pdev->dev, "l2 spurious interrupt\n"); 97 return IRQ_NONE; 98 } 99 100 /* Handle intferfaces */ 101 list_for_each_entry(intf, &priv->intfs, list) 102 bcmasp_intr2_handling(intf, status); 103 104 return IRQ_HANDLED; 105 } 106 107 void bcmasp_flush_rx_port(struct bcmasp_intf *intf) 108 { 109 struct bcmasp_priv *priv = intf->parent; 110 u32 mask; 111 112 switch (intf->port) { 113 case 0: 114 mask = ASP_CTRL_UMAC0_FLUSH_MASK; 115 break; 116 case 1: 117 mask = ASP_CTRL_UMAC1_FLUSH_MASK; 118 break; 119 case 2: 120 mask = ASP_CTRL_SPB_FLUSH_MASK; 121 break; 122 default: 123 /* Not valid port */ 124 return; 125 } 126 127 rx_ctrl_core_wl(priv, mask, priv->hw_info->rx_ctrl_flush); 128 } 129 130 static void bcmasp_netfilt_hw_en_wake(struct bcmasp_priv *priv, 131 struct bcmasp_net_filter *nfilt) 132 { 133 rx_filter_core_wl(priv, ASP_RX_FILTER_NET_OFFSET_L3_1(64), 134 ASP_RX_FILTER_NET_OFFSET(nfilt->hw_index)); 135 136 rx_filter_core_wl(priv, ASP_RX_FILTER_NET_OFFSET_L2(32) | 137 ASP_RX_FILTER_NET_OFFSET_L3_0(32) | 138 ASP_RX_FILTER_NET_OFFSET_L3_1(96) | 139 ASP_RX_FILTER_NET_OFFSET_L4(32), 140 ASP_RX_FILTER_NET_OFFSET(nfilt->hw_index + 1)); 141 142 rx_filter_core_wl(priv, ASP_RX_FILTER_NET_CFG_CH(nfilt->port + 8) | 143 ASP_RX_FILTER_NET_CFG_EN | 144 ASP_RX_FILTER_NET_CFG_L2_EN | 145 ASP_RX_FILTER_NET_CFG_L3_EN | 146 ASP_RX_FILTER_NET_CFG_L4_EN | 147 ASP_RX_FILTER_NET_CFG_L3_FRM(2) | 148 ASP_RX_FILTER_NET_CFG_L4_FRM(2) | 149 ASP_RX_FILTER_NET_CFG_UMC(nfilt->port), 150 ASP_RX_FILTER_NET_CFG(nfilt->hw_index)); 151 152 rx_filter_core_wl(priv, ASP_RX_FILTER_NET_CFG_CH(nfilt->port + 8) | 153 ASP_RX_FILTER_NET_CFG_EN | 154 ASP_RX_FILTER_NET_CFG_L2_EN | 155 ASP_RX_FILTER_NET_CFG_L3_EN | 156 ASP_RX_FILTER_NET_CFG_L4_EN | 157 ASP_RX_FILTER_NET_CFG_L3_FRM(2) | 158 ASP_RX_FILTER_NET_CFG_L4_FRM(2) | 159 ASP_RX_FILTER_NET_CFG_UMC(nfilt->port), 160 ASP_RX_FILTER_NET_CFG(nfilt->hw_index + 1)); 161 } 162 163 #define MAX_WAKE_FILTER_SIZE 256 164 enum asp_netfilt_reg_type { 165 ASP_NETFILT_MATCH = 0, 166 ASP_NETFILT_MASK, 167 ASP_NETFILT_MAX 168 }; 169 170 static int bcmasp_netfilt_get_reg_offset(struct bcmasp_priv *priv, 171 struct bcmasp_net_filter *nfilt, 172 enum asp_netfilt_reg_type reg_type, 173 u32 offset) 174 { 175 u32 block_index, filter_sel; 176 177 if (offset < 32) { 178 block_index = ASP_RX_FILTER_NET_L2; 179 filter_sel = nfilt->hw_index; 180 } else if (offset < 64) { 181 block_index = ASP_RX_FILTER_NET_L2; 182 filter_sel = nfilt->hw_index + 1; 183 } else if (offset < 96) { 184 block_index = ASP_RX_FILTER_NET_L3_0; 185 filter_sel = nfilt->hw_index; 186 } else if (offset < 128) { 187 block_index = ASP_RX_FILTER_NET_L3_0; 188 filter_sel = nfilt->hw_index + 1; 189 } else if (offset < 160) { 190 block_index = ASP_RX_FILTER_NET_L3_1; 191 filter_sel = nfilt->hw_index; 192 } else if (offset < 192) { 193 block_index = ASP_RX_FILTER_NET_L3_1; 194 filter_sel = nfilt->hw_index + 1; 195 } else if (offset < 224) { 196 block_index = ASP_RX_FILTER_NET_L4; 197 filter_sel = nfilt->hw_index; 198 } else if (offset < 256) { 199 block_index = ASP_RX_FILTER_NET_L4; 200 filter_sel = nfilt->hw_index + 1; 201 } else { 202 return -EINVAL; 203 } 204 205 switch (reg_type) { 206 case ASP_NETFILT_MATCH: 207 return ASP_RX_FILTER_NET_PAT(filter_sel, block_index, 208 (offset % 32)); 209 case ASP_NETFILT_MASK: 210 return ASP_RX_FILTER_NET_MASK(filter_sel, block_index, 211 (offset % 32)); 212 default: 213 return -EINVAL; 214 } 215 } 216 217 static void bcmasp_netfilt_wr(struct bcmasp_priv *priv, 218 struct bcmasp_net_filter *nfilt, 219 enum asp_netfilt_reg_type reg_type, 220 u32 val, u32 offset) 221 { 222 int reg_offset; 223 224 /* HW only accepts 4 byte aligned writes */ 225 if (!IS_ALIGNED(offset, 4) || offset > MAX_WAKE_FILTER_SIZE) 226 return; 227 228 reg_offset = bcmasp_netfilt_get_reg_offset(priv, nfilt, reg_type, 229 offset); 230 231 rx_filter_core_wl(priv, val, reg_offset); 232 } 233 234 static u32 bcmasp_netfilt_rd(struct bcmasp_priv *priv, 235 struct bcmasp_net_filter *nfilt, 236 enum asp_netfilt_reg_type reg_type, 237 u32 offset) 238 { 239 int reg_offset; 240 241 /* HW only accepts 4 byte aligned writes */ 242 if (!IS_ALIGNED(offset, 4) || offset > MAX_WAKE_FILTER_SIZE) 243 return 0; 244 245 reg_offset = bcmasp_netfilt_get_reg_offset(priv, nfilt, reg_type, 246 offset); 247 248 return rx_filter_core_rl(priv, reg_offset); 249 } 250 251 static int bcmasp_netfilt_wr_m_wake(struct bcmasp_priv *priv, 252 struct bcmasp_net_filter *nfilt, 253 u32 offset, void *match, void *mask, 254 size_t size) 255 { 256 u32 shift, mask_val = 0, match_val = 0; 257 bool first_byte = true; 258 259 if ((offset + size) > MAX_WAKE_FILTER_SIZE) 260 return -EINVAL; 261 262 while (size--) { 263 /* The HW only accepts 4 byte aligned writes, so if we 264 * begin unaligned or if remaining bytes less than 4, 265 * we need to read then write to avoid losing current 266 * register state 267 */ 268 if (first_byte && (!IS_ALIGNED(offset, 4) || size < 3)) { 269 match_val = bcmasp_netfilt_rd(priv, nfilt, 270 ASP_NETFILT_MATCH, 271 ALIGN_DOWN(offset, 4)); 272 mask_val = bcmasp_netfilt_rd(priv, nfilt, 273 ASP_NETFILT_MASK, 274 ALIGN_DOWN(offset, 4)); 275 } 276 277 shift = (3 - (offset % 4)) * 8; 278 match_val &= ~GENMASK(shift + 7, shift); 279 mask_val &= ~GENMASK(shift + 7, shift); 280 match_val |= (u32)(*((u8 *)match) << shift); 281 mask_val |= (u32)(*((u8 *)mask) << shift); 282 283 /* If last byte or last byte of word, write to reg */ 284 if (!size || ((offset % 4) == 3)) { 285 bcmasp_netfilt_wr(priv, nfilt, ASP_NETFILT_MATCH, 286 match_val, ALIGN_DOWN(offset, 4)); 287 bcmasp_netfilt_wr(priv, nfilt, ASP_NETFILT_MASK, 288 mask_val, ALIGN_DOWN(offset, 4)); 289 first_byte = true; 290 } else { 291 first_byte = false; 292 } 293 294 offset++; 295 match++; 296 mask++; 297 } 298 299 return 0; 300 } 301 302 static void bcmasp_netfilt_reset_hw(struct bcmasp_priv *priv, 303 struct bcmasp_net_filter *nfilt) 304 { 305 int i; 306 307 for (i = 0; i < MAX_WAKE_FILTER_SIZE; i += 4) { 308 bcmasp_netfilt_wr(priv, nfilt, ASP_NETFILT_MATCH, 0, i); 309 bcmasp_netfilt_wr(priv, nfilt, ASP_NETFILT_MASK, 0, i); 310 } 311 } 312 313 static void bcmasp_netfilt_tcpip4_wr(struct bcmasp_priv *priv, 314 struct bcmasp_net_filter *nfilt, 315 struct ethtool_tcpip4_spec *match, 316 struct ethtool_tcpip4_spec *mask, 317 u32 offset) 318 { 319 __be16 val_16, mask_16; 320 321 val_16 = htons(ETH_P_IP); 322 mask_16 = htons(0xFFFF); 323 bcmasp_netfilt_wr_m_wake(priv, nfilt, (ETH_ALEN * 2) + offset, 324 &val_16, &mask_16, sizeof(val_16)); 325 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 1, 326 &match->tos, &mask->tos, 327 sizeof(match->tos)); 328 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 12, 329 &match->ip4src, &mask->ip4src, 330 sizeof(match->ip4src)); 331 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 16, 332 &match->ip4dst, &mask->ip4dst, 333 sizeof(match->ip4dst)); 334 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 20, 335 &match->psrc, &mask->psrc, 336 sizeof(match->psrc)); 337 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 22, 338 &match->pdst, &mask->pdst, 339 sizeof(match->pdst)); 340 } 341 342 static void bcmasp_netfilt_tcpip6_wr(struct bcmasp_priv *priv, 343 struct bcmasp_net_filter *nfilt, 344 struct ethtool_tcpip6_spec *match, 345 struct ethtool_tcpip6_spec *mask, 346 u32 offset) 347 { 348 __be16 val_16, mask_16; 349 350 val_16 = htons(ETH_P_IPV6); 351 mask_16 = htons(0xFFFF); 352 bcmasp_netfilt_wr_m_wake(priv, nfilt, (ETH_ALEN * 2) + offset, 353 &val_16, &mask_16, sizeof(val_16)); 354 val_16 = htons(match->tclass << 4); 355 mask_16 = htons(mask->tclass << 4); 356 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset, 357 &val_16, &mask_16, sizeof(val_16)); 358 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 8, 359 &match->ip6src, &mask->ip6src, 360 sizeof(match->ip6src)); 361 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 24, 362 &match->ip6dst, &mask->ip6dst, 363 sizeof(match->ip6dst)); 364 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 40, 365 &match->psrc, &mask->psrc, 366 sizeof(match->psrc)); 367 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 42, 368 &match->pdst, &mask->pdst, 369 sizeof(match->pdst)); 370 } 371 372 static int bcmasp_netfilt_wr_to_hw(struct bcmasp_priv *priv, 373 struct bcmasp_net_filter *nfilt) 374 { 375 struct ethtool_rx_flow_spec *fs = &nfilt->fs; 376 unsigned int offset = 0; 377 __be16 val_16, mask_16; 378 u8 val_8, mask_8; 379 380 /* Currently only supports wake filters */ 381 if (!nfilt->wake_filter) 382 return -EINVAL; 383 384 bcmasp_netfilt_reset_hw(priv, nfilt); 385 386 if (fs->flow_type & FLOW_MAC_EXT) { 387 bcmasp_netfilt_wr_m_wake(priv, nfilt, 0, &fs->h_ext.h_dest, 388 &fs->m_ext.h_dest, 389 sizeof(fs->h_ext.h_dest)); 390 } 391 392 if ((fs->flow_type & FLOW_EXT) && 393 (fs->m_ext.vlan_etype || fs->m_ext.vlan_tci)) { 394 bcmasp_netfilt_wr_m_wake(priv, nfilt, (ETH_ALEN * 2), 395 &fs->h_ext.vlan_etype, 396 &fs->m_ext.vlan_etype, 397 sizeof(fs->h_ext.vlan_etype)); 398 bcmasp_netfilt_wr_m_wake(priv, nfilt, ((ETH_ALEN * 2) + 2), 399 &fs->h_ext.vlan_tci, 400 &fs->m_ext.vlan_tci, 401 sizeof(fs->h_ext.vlan_tci)); 402 offset += VLAN_HLEN; 403 } 404 405 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 406 case ETHER_FLOW: 407 bcmasp_netfilt_wr_m_wake(priv, nfilt, 0, 408 &fs->h_u.ether_spec.h_dest, 409 &fs->m_u.ether_spec.h_dest, 410 sizeof(fs->h_u.ether_spec.h_dest)); 411 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_ALEN, 412 &fs->h_u.ether_spec.h_source, 413 &fs->m_u.ether_spec.h_source, 414 sizeof(fs->h_u.ether_spec.h_source)); 415 bcmasp_netfilt_wr_m_wake(priv, nfilt, (ETH_ALEN * 2) + offset, 416 &fs->h_u.ether_spec.h_proto, 417 &fs->m_u.ether_spec.h_proto, 418 sizeof(fs->h_u.ether_spec.h_proto)); 419 420 break; 421 case IP_USER_FLOW: 422 val_16 = htons(ETH_P_IP); 423 mask_16 = htons(0xFFFF); 424 bcmasp_netfilt_wr_m_wake(priv, nfilt, (ETH_ALEN * 2) + offset, 425 &val_16, &mask_16, sizeof(val_16)); 426 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 1, 427 &fs->h_u.usr_ip4_spec.tos, 428 &fs->m_u.usr_ip4_spec.tos, 429 sizeof(fs->h_u.usr_ip4_spec.tos)); 430 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 9, 431 &fs->h_u.usr_ip4_spec.proto, 432 &fs->m_u.usr_ip4_spec.proto, 433 sizeof(fs->h_u.usr_ip4_spec.proto)); 434 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 12, 435 &fs->h_u.usr_ip4_spec.ip4src, 436 &fs->m_u.usr_ip4_spec.ip4src, 437 sizeof(fs->h_u.usr_ip4_spec.ip4src)); 438 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 16, 439 &fs->h_u.usr_ip4_spec.ip4dst, 440 &fs->m_u.usr_ip4_spec.ip4dst, 441 sizeof(fs->h_u.usr_ip4_spec.ip4dst)); 442 if (!fs->m_u.usr_ip4_spec.l4_4_bytes) 443 break; 444 445 /* Only supports 20 byte IPv4 header */ 446 val_8 = 0x45; 447 mask_8 = 0xFF; 448 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset, 449 &val_8, &mask_8, sizeof(val_8)); 450 bcmasp_netfilt_wr_m_wake(priv, nfilt, 451 ETH_HLEN + 20 + offset, 452 &fs->h_u.usr_ip4_spec.l4_4_bytes, 453 &fs->m_u.usr_ip4_spec.l4_4_bytes, 454 sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes) 455 ); 456 break; 457 case TCP_V4_FLOW: 458 val_8 = IPPROTO_TCP; 459 mask_8 = 0xFF; 460 bcmasp_netfilt_tcpip4_wr(priv, nfilt, &fs->h_u.tcp_ip4_spec, 461 &fs->m_u.tcp_ip4_spec, offset); 462 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 9, 463 &val_8, &mask_8, sizeof(val_8)); 464 break; 465 case UDP_V4_FLOW: 466 val_8 = IPPROTO_UDP; 467 mask_8 = 0xFF; 468 bcmasp_netfilt_tcpip4_wr(priv, nfilt, &fs->h_u.udp_ip4_spec, 469 &fs->m_u.udp_ip4_spec, offset); 470 471 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 9, 472 &val_8, &mask_8, sizeof(val_8)); 473 break; 474 case TCP_V6_FLOW: 475 val_8 = IPPROTO_TCP; 476 mask_8 = 0xFF; 477 bcmasp_netfilt_tcpip6_wr(priv, nfilt, &fs->h_u.tcp_ip6_spec, 478 &fs->m_u.tcp_ip6_spec, offset); 479 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 6, 480 &val_8, &mask_8, sizeof(val_8)); 481 break; 482 case UDP_V6_FLOW: 483 val_8 = IPPROTO_UDP; 484 mask_8 = 0xFF; 485 bcmasp_netfilt_tcpip6_wr(priv, nfilt, &fs->h_u.udp_ip6_spec, 486 &fs->m_u.udp_ip6_spec, offset); 487 bcmasp_netfilt_wr_m_wake(priv, nfilt, ETH_HLEN + offset + 6, 488 &val_8, &mask_8, sizeof(val_8)); 489 break; 490 } 491 492 bcmasp_netfilt_hw_en_wake(priv, nfilt); 493 494 return 0; 495 } 496 497 void bcmasp_netfilt_suspend(struct bcmasp_intf *intf) 498 { 499 struct bcmasp_priv *priv = intf->parent; 500 bool write = false; 501 int ret, i; 502 503 /* Write all filters to HW */ 504 for (i = 0; i < NUM_NET_FILTERS; i++) { 505 /* If the filter does not match the port, skip programming. */ 506 if (!priv->net_filters[i].claimed || 507 priv->net_filters[i].port != intf->port) 508 continue; 509 510 if (i > 0 && (i % 2) && 511 priv->net_filters[i].wake_filter && 512 priv->net_filters[i - 1].wake_filter) 513 continue; 514 515 ret = bcmasp_netfilt_wr_to_hw(priv, &priv->net_filters[i]); 516 if (!ret) 517 write = true; 518 } 519 520 /* Successfully programmed at least one wake filter 521 * so enable top level wake config 522 */ 523 if (write) 524 rx_filter_core_wl(priv, (ASP_RX_FILTER_OPUT_EN | 525 ASP_RX_FILTER_LNR_MD | 526 ASP_RX_FILTER_GEN_WK_EN | 527 ASP_RX_FILTER_NT_FLT_EN), 528 ASP_RX_FILTER_BLK_CTRL); 529 } 530 531 void bcmasp_netfilt_get_all_active(struct bcmasp_intf *intf, u32 *rule_locs, 532 u32 *rule_cnt) 533 { 534 struct bcmasp_priv *priv = intf->parent; 535 int j = 0, i; 536 537 for (i = 0; i < NUM_NET_FILTERS; i++) { 538 if (!priv->net_filters[i].claimed || 539 priv->net_filters[i].port != intf->port) 540 continue; 541 542 if (i > 0 && (i % 2) && 543 priv->net_filters[i].wake_filter && 544 priv->net_filters[i - 1].wake_filter) 545 continue; 546 547 rule_locs[j++] = priv->net_filters[i].fs.location; 548 } 549 550 *rule_cnt = j; 551 } 552 553 int bcmasp_netfilt_get_active(struct bcmasp_intf *intf) 554 { 555 struct bcmasp_priv *priv = intf->parent; 556 int cnt = 0, i; 557 558 for (i = 0; i < NUM_NET_FILTERS; i++) { 559 if (!priv->net_filters[i].claimed || 560 priv->net_filters[i].port != intf->port) 561 continue; 562 563 /* Skip over a wake filter pair */ 564 if (i > 0 && (i % 2) && 565 priv->net_filters[i].wake_filter && 566 priv->net_filters[i - 1].wake_filter) 567 continue; 568 569 cnt++; 570 } 571 572 return cnt; 573 } 574 575 bool bcmasp_netfilt_check_dup(struct bcmasp_intf *intf, 576 struct ethtool_rx_flow_spec *fs) 577 { 578 struct bcmasp_priv *priv = intf->parent; 579 struct ethtool_rx_flow_spec *cur; 580 size_t fs_size = 0; 581 int i; 582 583 for (i = 0; i < NUM_NET_FILTERS; i++) { 584 if (!priv->net_filters[i].claimed || 585 priv->net_filters[i].port != intf->port) 586 continue; 587 588 cur = &priv->net_filters[i].fs; 589 590 if (cur->flow_type != fs->flow_type || 591 cur->ring_cookie != fs->ring_cookie) 592 continue; 593 594 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 595 case ETHER_FLOW: 596 fs_size = sizeof(struct ethhdr); 597 break; 598 case IP_USER_FLOW: 599 fs_size = sizeof(struct ethtool_usrip4_spec); 600 break; 601 case TCP_V6_FLOW: 602 case UDP_V6_FLOW: 603 fs_size = sizeof(struct ethtool_tcpip6_spec); 604 break; 605 case TCP_V4_FLOW: 606 case UDP_V4_FLOW: 607 fs_size = sizeof(struct ethtool_tcpip4_spec); 608 break; 609 default: 610 continue; 611 } 612 613 if (memcmp(&cur->h_u, &fs->h_u, fs_size) || 614 memcmp(&cur->m_u, &fs->m_u, fs_size)) 615 continue; 616 617 if (cur->flow_type & FLOW_EXT) { 618 if (cur->h_ext.vlan_etype != fs->h_ext.vlan_etype || 619 cur->m_ext.vlan_etype != fs->m_ext.vlan_etype || 620 cur->h_ext.vlan_tci != fs->h_ext.vlan_tci || 621 cur->m_ext.vlan_tci != fs->m_ext.vlan_tci || 622 cur->h_ext.data[0] != fs->h_ext.data[0]) 623 continue; 624 } 625 if (cur->flow_type & FLOW_MAC_EXT) { 626 if (memcmp(&cur->h_ext.h_dest, 627 &fs->h_ext.h_dest, ETH_ALEN) || 628 memcmp(&cur->m_ext.h_dest, 629 &fs->m_ext.h_dest, ETH_ALEN)) 630 continue; 631 } 632 633 return true; 634 } 635 636 return false; 637 } 638 639 /* If no network filter found, return open filter. 640 * If no more open filters return NULL 641 */ 642 struct bcmasp_net_filter *bcmasp_netfilt_get_init(struct bcmasp_intf *intf, 643 u32 loc, bool wake_filter, 644 bool init) 645 { 646 struct bcmasp_net_filter *nfilter = NULL; 647 struct bcmasp_priv *priv = intf->parent; 648 int i, open_index = -1; 649 650 /* Check whether we exceed the filter table capacity */ 651 if (loc != RX_CLS_LOC_ANY && loc >= NUM_NET_FILTERS) 652 return ERR_PTR(-EINVAL); 653 654 /* If the filter location is busy (already claimed) and we are initializing 655 * the filter (insertion), return a busy error code. 656 */ 657 if (loc != RX_CLS_LOC_ANY && init && priv->net_filters[loc].claimed) 658 return ERR_PTR(-EBUSY); 659 660 /* We need two filters for wake-up, so we cannot use an odd filter */ 661 if (wake_filter && loc != RX_CLS_LOC_ANY && (loc % 2)) 662 return ERR_PTR(-EINVAL); 663 664 /* Initialize the loop index based on the desired location or from 0 */ 665 i = loc == RX_CLS_LOC_ANY ? 0 : loc; 666 667 for ( ; i < NUM_NET_FILTERS; i++) { 668 /* Found matching network filter */ 669 if (!init && 670 priv->net_filters[i].claimed && 671 priv->net_filters[i].hw_index == i && 672 priv->net_filters[i].port == intf->port) 673 return &priv->net_filters[i]; 674 675 /* If we don't need a new filter or new filter already found */ 676 if (!init || open_index >= 0) 677 continue; 678 679 /* Wake filter conslidates two filters to cover more bytes 680 * Wake filter is open if... 681 * 1. It is an even filter 682 * 2. The current and next filter is not claimed 683 */ 684 if (wake_filter && !(i % 2) && !priv->net_filters[i].claimed && 685 !priv->net_filters[i + 1].claimed) 686 open_index = i; 687 else if (!priv->net_filters[i].claimed) 688 open_index = i; 689 } 690 691 if (open_index >= 0) { 692 nfilter = &priv->net_filters[open_index]; 693 nfilter->claimed = true; 694 nfilter->port = intf->port; 695 nfilter->hw_index = open_index; 696 } 697 698 if (wake_filter && open_index >= 0) { 699 /* Claim next filter */ 700 priv->net_filters[open_index + 1].claimed = true; 701 priv->net_filters[open_index + 1].wake_filter = true; 702 nfilter->wake_filter = true; 703 } 704 705 return nfilter ? nfilter : ERR_PTR(-EINVAL); 706 } 707 708 void bcmasp_netfilt_release(struct bcmasp_intf *intf, 709 struct bcmasp_net_filter *nfilt) 710 { 711 struct bcmasp_priv *priv = intf->parent; 712 713 if (nfilt->wake_filter) { 714 memset(&priv->net_filters[nfilt->hw_index + 1], 0, 715 sizeof(struct bcmasp_net_filter)); 716 } 717 718 memset(nfilt, 0, sizeof(struct bcmasp_net_filter)); 719 } 720 721 static void bcmasp_addr_to_uint(unsigned char *addr, u32 *high, u32 *low) 722 { 723 *high = (u32)(addr[0] << 8 | addr[1]); 724 *low = (u32)(addr[2] << 24 | addr[3] << 16 | addr[4] << 8 | 725 addr[5]); 726 } 727 728 static void bcmasp_set_mda_filter(struct bcmasp_intf *intf, 729 const unsigned char *addr, 730 unsigned char *mask, 731 unsigned int i) 732 { 733 struct bcmasp_priv *priv = intf->parent; 734 u32 addr_h, addr_l, mask_h, mask_l; 735 736 /* Set local copy */ 737 ether_addr_copy(priv->mda_filters[i].mask, mask); 738 ether_addr_copy(priv->mda_filters[i].addr, addr); 739 740 /* Write to HW */ 741 bcmasp_addr_to_uint(priv->mda_filters[i].mask, &mask_h, &mask_l); 742 bcmasp_addr_to_uint(priv->mda_filters[i].addr, &addr_h, &addr_l); 743 rx_filter_core_wl(priv, addr_h, ASP_RX_FILTER_MDA_PAT_H(i)); 744 rx_filter_core_wl(priv, addr_l, ASP_RX_FILTER_MDA_PAT_L(i)); 745 rx_filter_core_wl(priv, mask_h, ASP_RX_FILTER_MDA_MSK_H(i)); 746 rx_filter_core_wl(priv, mask_l, ASP_RX_FILTER_MDA_MSK_L(i)); 747 } 748 749 static void bcmasp_en_mda_filter(struct bcmasp_intf *intf, bool en, 750 unsigned int i) 751 { 752 struct bcmasp_priv *priv = intf->parent; 753 754 if (priv->mda_filters[i].en == en) 755 return; 756 757 priv->mda_filters[i].en = en; 758 priv->mda_filters[i].port = intf->port; 759 760 rx_filter_core_wl(priv, ((intf->channel + 8) | 761 (en << ASP_RX_FILTER_MDA_CFG_EN_SHIFT) | 762 ASP_RX_FILTER_MDA_CFG_UMC_SEL(intf->port)), 763 ASP_RX_FILTER_MDA_CFG(i)); 764 } 765 766 /* There are 32 MDA filters shared between all ports, we reserve 4 filters per 767 * port for the following. 768 * - Promisc: Filter to allow all packets when promisc is enabled 769 * - All Multicast 770 * - Broadcast 771 * - Own address 772 * 773 * The reserved filters are identified as so. 774 * - Promisc: (index * 4) + 0 775 * - All Multicast: (index * 4) + 1 776 * - Broadcast: (index * 4) + 2 777 * - Own address: (index * 4) + 3 778 */ 779 enum asp_rx_filter_id { 780 ASP_RX_FILTER_MDA_PROMISC = 0, 781 ASP_RX_FILTER_MDA_ALLMULTI, 782 ASP_RX_FILTER_MDA_BROADCAST, 783 ASP_RX_FILTER_MDA_OWN_ADDR, 784 ASP_RX_FILTER_MDA_RES_MAX, 785 }; 786 787 #define ASP_RX_FILT_MDA(intf, name) (((intf)->index * \ 788 ASP_RX_FILTER_MDA_RES_MAX) \ 789 + ASP_RX_FILTER_MDA_##name) 790 791 static int bcmasp_total_res_mda_cnt(struct bcmasp_priv *priv) 792 { 793 return list_count_nodes(&priv->intfs) * ASP_RX_FILTER_MDA_RES_MAX; 794 } 795 796 void bcmasp_set_promisc(struct bcmasp_intf *intf, bool en) 797 { 798 unsigned int i = ASP_RX_FILT_MDA(intf, PROMISC); 799 unsigned char promisc[ETH_ALEN]; 800 801 eth_zero_addr(promisc); 802 /* Set mask to 00:00:00:00:00:00 to match all packets */ 803 bcmasp_set_mda_filter(intf, promisc, promisc, i); 804 bcmasp_en_mda_filter(intf, en, i); 805 } 806 807 void bcmasp_set_allmulti(struct bcmasp_intf *intf, bool en) 808 { 809 unsigned char allmulti[] = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00}; 810 unsigned int i = ASP_RX_FILT_MDA(intf, ALLMULTI); 811 812 /* Set mask to 01:00:00:00:00:00 to match all multicast */ 813 bcmasp_set_mda_filter(intf, allmulti, allmulti, i); 814 bcmasp_en_mda_filter(intf, en, i); 815 } 816 817 void bcmasp_set_broad(struct bcmasp_intf *intf, bool en) 818 { 819 unsigned int i = ASP_RX_FILT_MDA(intf, BROADCAST); 820 unsigned char addr[ETH_ALEN]; 821 822 eth_broadcast_addr(addr); 823 bcmasp_set_mda_filter(intf, addr, addr, i); 824 bcmasp_en_mda_filter(intf, en, i); 825 } 826 827 void bcmasp_set_oaddr(struct bcmasp_intf *intf, const unsigned char *addr, 828 bool en) 829 { 830 unsigned char mask[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 831 unsigned int i = ASP_RX_FILT_MDA(intf, OWN_ADDR); 832 833 bcmasp_set_mda_filter(intf, addr, mask, i); 834 bcmasp_en_mda_filter(intf, en, i); 835 } 836 837 void bcmasp_disable_all_filters(struct bcmasp_intf *intf) 838 { 839 struct bcmasp_priv *priv = intf->parent; 840 unsigned int i; 841 int res_count; 842 843 res_count = bcmasp_total_res_mda_cnt(intf->parent); 844 845 /* Disable all filters held by this port */ 846 for (i = res_count; i < NUM_MDA_FILTERS; i++) { 847 if (priv->mda_filters[i].en && 848 priv->mda_filters[i].port == intf->port) 849 bcmasp_en_mda_filter(intf, 0, i); 850 } 851 } 852 853 static int bcmasp_combine_set_filter(struct bcmasp_intf *intf, 854 unsigned char *addr, unsigned char *mask, 855 int i) 856 { 857 struct bcmasp_priv *priv = intf->parent; 858 u64 addr1, addr2, mask1, mask2, mask3; 859 860 /* Switch to u64 to help with the calculations */ 861 addr1 = ether_addr_to_u64(priv->mda_filters[i].addr); 862 mask1 = ether_addr_to_u64(priv->mda_filters[i].mask); 863 addr2 = ether_addr_to_u64(addr); 864 mask2 = ether_addr_to_u64(mask); 865 866 /* Check if one filter resides within the other */ 867 mask3 = mask1 & mask2; 868 if (mask3 == mask1 && ((addr1 & mask1) == (addr2 & mask1))) { 869 /* Filter 2 resides within filter 1, so everything is good */ 870 return 0; 871 } else if (mask3 == mask2 && ((addr1 & mask2) == (addr2 & mask2))) { 872 /* Filter 1 resides within filter 2, so swap filters */ 873 bcmasp_set_mda_filter(intf, addr, mask, i); 874 return 0; 875 } 876 877 /* Unable to combine */ 878 return -EINVAL; 879 } 880 881 int bcmasp_set_en_mda_filter(struct bcmasp_intf *intf, unsigned char *addr, 882 unsigned char *mask) 883 { 884 struct bcmasp_priv *priv = intf->parent; 885 int ret, res_count; 886 unsigned int i; 887 888 res_count = bcmasp_total_res_mda_cnt(intf->parent); 889 890 for (i = res_count; i < NUM_MDA_FILTERS; i++) { 891 /* If filter not enabled or belongs to another port skip */ 892 if (!priv->mda_filters[i].en || 893 priv->mda_filters[i].port != intf->port) 894 continue; 895 896 /* Attempt to combine filters */ 897 ret = bcmasp_combine_set_filter(intf, addr, mask, i); 898 if (!ret) { 899 intf->mib.filters_combine_cnt++; 900 return 0; 901 } 902 } 903 904 /* Create new filter if possible */ 905 for (i = res_count; i < NUM_MDA_FILTERS; i++) { 906 if (priv->mda_filters[i].en) 907 continue; 908 909 bcmasp_set_mda_filter(intf, addr, mask, i); 910 bcmasp_en_mda_filter(intf, 1, i); 911 return 0; 912 } 913 914 /* No room for new filter */ 915 return -EINVAL; 916 } 917 918 static void bcmasp_core_init_filters(struct bcmasp_priv *priv) 919 { 920 unsigned int i; 921 922 /* Disable all filters and reset software view since the HW 923 * can lose context while in deep sleep suspend states 924 */ 925 for (i = 0; i < NUM_MDA_FILTERS; i++) { 926 rx_filter_core_wl(priv, 0x0, ASP_RX_FILTER_MDA_CFG(i)); 927 priv->mda_filters[i].en = 0; 928 } 929 930 for (i = 0; i < NUM_NET_FILTERS; i++) 931 rx_filter_core_wl(priv, 0x0, ASP_RX_FILTER_NET_CFG(i)); 932 933 /* Top level filter enable bit should be enabled at all times, set 934 * GEN_WAKE_CLEAR to clear the network filter wake-up which would 935 * otherwise be sticky 936 */ 937 rx_filter_core_wl(priv, (ASP_RX_FILTER_OPUT_EN | 938 ASP_RX_FILTER_MDA_EN | 939 ASP_RX_FILTER_GEN_WK_CLR | 940 ASP_RX_FILTER_NT_FLT_EN), 941 ASP_RX_FILTER_BLK_CTRL); 942 } 943 944 /* ASP core initialization */ 945 static void bcmasp_core_init(struct bcmasp_priv *priv) 946 { 947 tx_analytics_core_wl(priv, 0x0, ASP_TX_ANALYTICS_CTRL); 948 rx_analytics_core_wl(priv, 0x4, ASP_RX_ANALYTICS_CTRL); 949 950 rx_edpkt_core_wl(priv, (ASP_EDPKT_HDR_SZ_128 << ASP_EDPKT_HDR_SZ_SHIFT), 951 ASP_EDPKT_HDR_CFG); 952 rx_edpkt_core_wl(priv, 953 (ASP_EDPKT_ENDI_BT_SWP_WD << ASP_EDPKT_ENDI_DESC_SHIFT), 954 ASP_EDPKT_ENDI); 955 956 rx_edpkt_core_wl(priv, 0x1b, ASP_EDPKT_BURST_BUF_PSCAL_TOUT); 957 rx_edpkt_core_wl(priv, 0x3e8, ASP_EDPKT_BURST_BUF_WRITE_TOUT); 958 rx_edpkt_core_wl(priv, 0x3e8, ASP_EDPKT_BURST_BUF_READ_TOUT); 959 960 rx_edpkt_core_wl(priv, ASP_EDPKT_ENABLE_EN, ASP_EDPKT_ENABLE); 961 962 /* Disable and clear both UniMAC's wake-up interrupts to avoid 963 * sticky interrupts. 964 */ 965 _intr2_mask_set(priv, ASP_INTR2_UMC0_WAKE | ASP_INTR2_UMC1_WAKE); 966 intr2_core_wl(priv, ASP_INTR2_UMC0_WAKE | ASP_INTR2_UMC1_WAKE, 967 ASP_INTR2_CLEAR); 968 } 969 970 static void bcmasp_core_clock_select(struct bcmasp_priv *priv, bool slow) 971 { 972 u32 reg; 973 974 reg = ctrl_core_rl(priv, ASP_CTRL_CORE_CLOCK_SELECT); 975 if (slow) 976 reg &= ~ASP_CTRL_CORE_CLOCK_SELECT_MAIN; 977 else 978 reg |= ASP_CTRL_CORE_CLOCK_SELECT_MAIN; 979 ctrl_core_wl(priv, reg, ASP_CTRL_CORE_CLOCK_SELECT); 980 } 981 982 static void bcmasp_core_clock_set_ll(struct bcmasp_priv *priv, u32 clr, u32 set) 983 { 984 u32 reg; 985 986 reg = ctrl_core_rl(priv, ASP_CTRL_CLOCK_CTRL); 987 reg &= ~clr; 988 reg |= set; 989 ctrl_core_wl(priv, reg, ASP_CTRL_CLOCK_CTRL); 990 991 reg = ctrl_core_rl(priv, ASP_CTRL_SCRATCH_0); 992 reg &= ~clr; 993 reg |= set; 994 ctrl_core_wl(priv, reg, ASP_CTRL_SCRATCH_0); 995 } 996 997 static void bcmasp_core_clock_set(struct bcmasp_priv *priv, u32 clr, u32 set) 998 { 999 unsigned long flags; 1000 1001 spin_lock_irqsave(&priv->clk_lock, flags); 1002 bcmasp_core_clock_set_ll(priv, clr, set); 1003 spin_unlock_irqrestore(&priv->clk_lock, flags); 1004 } 1005 1006 void bcmasp_core_clock_set_intf(struct bcmasp_intf *intf, bool en) 1007 { 1008 u32 intf_mask = ASP_CTRL_CLOCK_CTRL_ASP_RGMII_DIS(intf->port); 1009 struct bcmasp_priv *priv = intf->parent; 1010 unsigned long flags; 1011 u32 reg; 1012 1013 /* When enabling an interface, if the RX or TX clocks were not enabled, 1014 * enable them. Conversely, while disabling an interface, if this is 1015 * the last one enabled, we can turn off the shared RX and TX clocks as 1016 * well. We control enable bits which is why we test for equality on 1017 * the RGMII clock bit mask. 1018 */ 1019 spin_lock_irqsave(&priv->clk_lock, flags); 1020 if (en) { 1021 intf_mask |= ASP_CTRL_CLOCK_CTRL_ASP_TX_DISABLE | 1022 ASP_CTRL_CLOCK_CTRL_ASP_RX_DISABLE; 1023 bcmasp_core_clock_set_ll(priv, intf_mask, 0); 1024 } else { 1025 reg = ctrl_core_rl(priv, ASP_CTRL_SCRATCH_0) | intf_mask; 1026 if ((reg & ASP_CTRL_CLOCK_CTRL_ASP_RGMII_MASK) == 1027 ASP_CTRL_CLOCK_CTRL_ASP_RGMII_MASK) 1028 intf_mask |= ASP_CTRL_CLOCK_CTRL_ASP_TX_DISABLE | 1029 ASP_CTRL_CLOCK_CTRL_ASP_RX_DISABLE; 1030 bcmasp_core_clock_set_ll(priv, 0, intf_mask); 1031 } 1032 spin_unlock_irqrestore(&priv->clk_lock, flags); 1033 } 1034 1035 static irqreturn_t bcmasp_isr_wol(int irq, void *data) 1036 { 1037 struct bcmasp_priv *priv = data; 1038 u32 status; 1039 1040 /* No L3 IRQ, so we good */ 1041 if (priv->wol_irq <= 0) 1042 goto irq_handled; 1043 1044 status = wakeup_intr2_core_rl(priv, ASP_WAKEUP_INTR2_STATUS) & 1045 ~wakeup_intr2_core_rl(priv, ASP_WAKEUP_INTR2_MASK_STATUS); 1046 wakeup_intr2_core_wl(priv, status, ASP_WAKEUP_INTR2_CLEAR); 1047 1048 irq_handled: 1049 pm_wakeup_event(&priv->pdev->dev, 0); 1050 return IRQ_HANDLED; 1051 } 1052 1053 static int bcmasp_get_and_request_irq(struct bcmasp_priv *priv, int i) 1054 { 1055 struct platform_device *pdev = priv->pdev; 1056 int irq, ret; 1057 1058 irq = platform_get_irq_optional(pdev, i); 1059 if (irq < 0) 1060 return irq; 1061 1062 ret = devm_request_irq(&pdev->dev, irq, bcmasp_isr_wol, 0, 1063 pdev->name, priv); 1064 if (ret) 1065 return ret; 1066 1067 return irq; 1068 } 1069 1070 static void bcmasp_init_wol_shared(struct bcmasp_priv *priv) 1071 { 1072 struct platform_device *pdev = priv->pdev; 1073 struct device *dev = &pdev->dev; 1074 int irq; 1075 1076 irq = bcmasp_get_and_request_irq(priv, 1); 1077 if (irq < 0) { 1078 dev_warn(dev, "Failed to init WoL irq: %d\n", irq); 1079 return; 1080 } 1081 1082 priv->wol_irq = irq; 1083 priv->wol_irq_enabled_mask = 0; 1084 device_set_wakeup_capable(&pdev->dev, 1); 1085 } 1086 1087 static void bcmasp_enable_wol_shared(struct bcmasp_intf *intf, bool en) 1088 { 1089 struct bcmasp_priv *priv = intf->parent; 1090 struct device *dev = &priv->pdev->dev; 1091 1092 if (en) { 1093 if (priv->wol_irq_enabled_mask) { 1094 set_bit(intf->port, &priv->wol_irq_enabled_mask); 1095 return; 1096 } 1097 1098 /* First enable */ 1099 set_bit(intf->port, &priv->wol_irq_enabled_mask); 1100 enable_irq_wake(priv->wol_irq); 1101 device_set_wakeup_enable(dev, 1); 1102 } else { 1103 if (!priv->wol_irq_enabled_mask) 1104 return; 1105 1106 clear_bit(intf->port, &priv->wol_irq_enabled_mask); 1107 if (priv->wol_irq_enabled_mask) 1108 return; 1109 1110 /* Last disable */ 1111 disable_irq_wake(priv->wol_irq); 1112 device_set_wakeup_enable(dev, 0); 1113 } 1114 } 1115 1116 static void bcmasp_wol_irq_destroy_shared(struct bcmasp_priv *priv) 1117 { 1118 if (priv->wol_irq > 0) 1119 free_irq(priv->wol_irq, priv); 1120 } 1121 1122 static void bcmasp_init_wol_per_intf(struct bcmasp_priv *priv) 1123 { 1124 struct platform_device *pdev = priv->pdev; 1125 struct device *dev = &pdev->dev; 1126 struct bcmasp_intf *intf; 1127 int irq; 1128 1129 list_for_each_entry(intf, &priv->intfs, list) { 1130 irq = bcmasp_get_and_request_irq(priv, intf->port + 1); 1131 if (irq < 0) { 1132 dev_warn(dev, "Failed to init WoL irq(port %d): %d\n", 1133 intf->port, irq); 1134 continue; 1135 } 1136 1137 intf->wol_irq = irq; 1138 intf->wol_irq_enabled = false; 1139 device_set_wakeup_capable(&pdev->dev, 1); 1140 } 1141 } 1142 1143 static void bcmasp_enable_wol_per_intf(struct bcmasp_intf *intf, bool en) 1144 { 1145 struct device *dev = &intf->parent->pdev->dev; 1146 1147 if (en ^ intf->wol_irq_enabled) 1148 irq_set_irq_wake(intf->wol_irq, en); 1149 1150 intf->wol_irq_enabled = en; 1151 device_set_wakeup_enable(dev, en); 1152 } 1153 1154 static void bcmasp_wol_irq_destroy_per_intf(struct bcmasp_priv *priv) 1155 { 1156 struct bcmasp_intf *intf; 1157 1158 list_for_each_entry(intf, &priv->intfs, list) { 1159 if (intf->wol_irq > 0) 1160 free_irq(intf->wol_irq, priv); 1161 } 1162 } 1163 1164 static struct bcmasp_hw_info v20_hw_info = { 1165 .rx_ctrl_flush = ASP_RX_CTRL_FLUSH, 1166 .umac2fb = UMAC2FB_OFFSET, 1167 .rx_ctrl_fb_out_frame_count = ASP_RX_CTRL_FB_OUT_FRAME_COUNT, 1168 .rx_ctrl_fb_filt_out_frame_count = ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT, 1169 .rx_ctrl_fb_rx_fifo_depth = ASP_RX_CTRL_FB_RX_FIFO_DEPTH, 1170 }; 1171 1172 static const struct bcmasp_plat_data v20_plat_data = { 1173 .init_wol = bcmasp_init_wol_per_intf, 1174 .enable_wol = bcmasp_enable_wol_per_intf, 1175 .destroy_wol = bcmasp_wol_irq_destroy_per_intf, 1176 .hw_info = &v20_hw_info, 1177 }; 1178 1179 static struct bcmasp_hw_info v21_hw_info = { 1180 .rx_ctrl_flush = ASP_RX_CTRL_FLUSH_2_1, 1181 .umac2fb = UMAC2FB_OFFSET_2_1, 1182 .rx_ctrl_fb_out_frame_count = ASP_RX_CTRL_FB_OUT_FRAME_COUNT_2_1, 1183 .rx_ctrl_fb_filt_out_frame_count = 1184 ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT_2_1, 1185 .rx_ctrl_fb_rx_fifo_depth = ASP_RX_CTRL_FB_RX_FIFO_DEPTH_2_1, 1186 }; 1187 1188 static const struct bcmasp_plat_data v21_plat_data = { 1189 .init_wol = bcmasp_init_wol_shared, 1190 .enable_wol = bcmasp_enable_wol_shared, 1191 .destroy_wol = bcmasp_wol_irq_destroy_shared, 1192 .hw_info = &v21_hw_info, 1193 }; 1194 1195 static const struct of_device_id bcmasp_of_match[] = { 1196 { .compatible = "brcm,asp-v2.0", .data = &v20_plat_data }, 1197 { .compatible = "brcm,asp-v2.1", .data = &v21_plat_data }, 1198 { /* sentinel */ }, 1199 }; 1200 MODULE_DEVICE_TABLE(of, bcmasp_of_match); 1201 1202 static const struct of_device_id bcmasp_mdio_of_match[] = { 1203 { .compatible = "brcm,asp-v2.1-mdio", }, 1204 { .compatible = "brcm,asp-v2.0-mdio", }, 1205 { /* sentinel */ }, 1206 }; 1207 MODULE_DEVICE_TABLE(of, bcmasp_mdio_of_match); 1208 1209 static void bcmasp_remove_intfs(struct bcmasp_priv *priv) 1210 { 1211 struct bcmasp_intf *intf, *n; 1212 1213 list_for_each_entry_safe(intf, n, &priv->intfs, list) { 1214 list_del(&intf->list); 1215 bcmasp_interface_destroy(intf); 1216 } 1217 } 1218 1219 static int bcmasp_probe(struct platform_device *pdev) 1220 { 1221 struct device_node *ports_node, *intf_node; 1222 const struct bcmasp_plat_data *pdata; 1223 struct device *dev = &pdev->dev; 1224 struct bcmasp_priv *priv; 1225 struct bcmasp_intf *intf; 1226 int ret = 0, count = 0; 1227 unsigned int i; 1228 1229 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1230 if (!priv) 1231 return -ENOMEM; 1232 1233 priv->irq = platform_get_irq(pdev, 0); 1234 if (priv->irq <= 0) 1235 return -EINVAL; 1236 1237 priv->clk = devm_clk_get_optional_enabled(dev, "sw_asp"); 1238 if (IS_ERR(priv->clk)) 1239 return dev_err_probe(dev, PTR_ERR(priv->clk), 1240 "failed to request clock\n"); 1241 1242 /* Base from parent node */ 1243 priv->base = devm_platform_ioremap_resource(pdev, 0); 1244 if (IS_ERR(priv->base)) 1245 return dev_err_probe(dev, PTR_ERR(priv->base), "failed to iomap\n"); 1246 1247 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 1248 if (ret) 1249 return dev_err_probe(dev, ret, "unable to set DMA mask: %d\n", ret); 1250 1251 dev_set_drvdata(&pdev->dev, priv); 1252 priv->pdev = pdev; 1253 spin_lock_init(&priv->mda_lock); 1254 spin_lock_init(&priv->clk_lock); 1255 mutex_init(&priv->wol_lock); 1256 mutex_init(&priv->net_lock); 1257 INIT_LIST_HEAD(&priv->intfs); 1258 1259 pdata = device_get_match_data(&pdev->dev); 1260 if (!pdata) 1261 return dev_err_probe(dev, -EINVAL, "unable to find platform data\n"); 1262 1263 priv->init_wol = pdata->init_wol; 1264 priv->enable_wol = pdata->enable_wol; 1265 priv->destroy_wol = pdata->destroy_wol; 1266 priv->hw_info = pdata->hw_info; 1267 1268 /* Enable all clocks to ensure successful probing */ 1269 bcmasp_core_clock_set(priv, ASP_CTRL_CLOCK_CTRL_ASP_ALL_DISABLE, 0); 1270 1271 /* Switch to the main clock */ 1272 bcmasp_core_clock_select(priv, false); 1273 1274 bcmasp_intr2_mask_set_all(priv); 1275 bcmasp_intr2_clear_all(priv); 1276 1277 ret = devm_request_irq(&pdev->dev, priv->irq, bcmasp_isr, 0, 1278 pdev->name, priv); 1279 if (ret) 1280 return dev_err_probe(dev, ret, "failed to request ASP interrupt: %d", ret); 1281 1282 /* Register mdio child nodes */ 1283 of_platform_populate(dev->of_node, bcmasp_mdio_of_match, NULL, dev); 1284 1285 /* ASP specific initialization, Needs to be done regardless of 1286 * how many interfaces come up. 1287 */ 1288 bcmasp_core_init(priv); 1289 bcmasp_core_init_filters(priv); 1290 1291 ports_node = of_find_node_by_name(dev->of_node, "ethernet-ports"); 1292 if (!ports_node) { 1293 dev_warn(dev, "No ports found\n"); 1294 return -EINVAL; 1295 } 1296 1297 i = 0; 1298 for_each_available_child_of_node(ports_node, intf_node) { 1299 intf = bcmasp_interface_create(priv, intf_node, i); 1300 if (!intf) { 1301 dev_err(dev, "Cannot create eth interface %d\n", i); 1302 bcmasp_remove_intfs(priv); 1303 goto of_put_exit; 1304 } 1305 list_add_tail(&intf->list, &priv->intfs); 1306 i++; 1307 } 1308 1309 /* Check and enable WoL */ 1310 priv->init_wol(priv); 1311 1312 /* Drop the clock reference count now and let ndo_open()/ndo_close() 1313 * manage it for us from now on. 1314 */ 1315 bcmasp_core_clock_set(priv, 0, ASP_CTRL_CLOCK_CTRL_ASP_ALL_DISABLE); 1316 1317 clk_disable_unprepare(priv->clk); 1318 1319 /* Now do the registration of the network ports which will take care 1320 * of managing the clock properly. 1321 */ 1322 list_for_each_entry(intf, &priv->intfs, list) { 1323 ret = register_netdev(intf->ndev); 1324 if (ret) { 1325 netdev_err(intf->ndev, 1326 "failed to register net_device: %d\n", ret); 1327 priv->destroy_wol(priv); 1328 bcmasp_remove_intfs(priv); 1329 goto of_put_exit; 1330 } 1331 count++; 1332 } 1333 1334 dev_info(dev, "Initialized %d port(s)\n", count); 1335 1336 of_put_exit: 1337 of_node_put(ports_node); 1338 return ret; 1339 } 1340 1341 static int bcmasp_remove(struct platform_device *pdev) 1342 { 1343 struct bcmasp_priv *priv = dev_get_drvdata(&pdev->dev); 1344 1345 if (!priv) 1346 return 0; 1347 1348 priv->destroy_wol(priv); 1349 bcmasp_remove_intfs(priv); 1350 1351 return 0; 1352 } 1353 1354 static void bcmasp_shutdown(struct platform_device *pdev) 1355 { 1356 bcmasp_remove(pdev); 1357 } 1358 1359 static int __maybe_unused bcmasp_suspend(struct device *d) 1360 { 1361 struct bcmasp_priv *priv = dev_get_drvdata(d); 1362 struct bcmasp_intf *intf; 1363 int ret; 1364 1365 list_for_each_entry(intf, &priv->intfs, list) { 1366 ret = bcmasp_interface_suspend(intf); 1367 if (ret) 1368 break; 1369 } 1370 1371 ret = clk_prepare_enable(priv->clk); 1372 if (ret) 1373 return ret; 1374 1375 /* Whether Wake-on-LAN is enabled or not, we can always disable 1376 * the shared TX clock 1377 */ 1378 bcmasp_core_clock_set(priv, 0, ASP_CTRL_CLOCK_CTRL_ASP_TX_DISABLE); 1379 1380 bcmasp_core_clock_select(priv, true); 1381 1382 clk_disable_unprepare(priv->clk); 1383 1384 return ret; 1385 } 1386 1387 static int __maybe_unused bcmasp_resume(struct device *d) 1388 { 1389 struct bcmasp_priv *priv = dev_get_drvdata(d); 1390 struct bcmasp_intf *intf; 1391 int ret; 1392 1393 ret = clk_prepare_enable(priv->clk); 1394 if (ret) 1395 return ret; 1396 1397 /* Switch to the main clock domain */ 1398 bcmasp_core_clock_select(priv, false); 1399 1400 /* Re-enable all clocks for re-initialization */ 1401 bcmasp_core_clock_set(priv, ASP_CTRL_CLOCK_CTRL_ASP_ALL_DISABLE, 0); 1402 1403 bcmasp_core_init(priv); 1404 bcmasp_core_init_filters(priv); 1405 1406 /* And disable them to let the network devices take care of them */ 1407 bcmasp_core_clock_set(priv, 0, ASP_CTRL_CLOCK_CTRL_ASP_ALL_DISABLE); 1408 1409 clk_disable_unprepare(priv->clk); 1410 1411 list_for_each_entry(intf, &priv->intfs, list) { 1412 ret = bcmasp_interface_resume(intf); 1413 if (ret) 1414 break; 1415 } 1416 1417 return ret; 1418 } 1419 1420 static SIMPLE_DEV_PM_OPS(bcmasp_pm_ops, 1421 bcmasp_suspend, bcmasp_resume); 1422 1423 static struct platform_driver bcmasp_driver = { 1424 .probe = bcmasp_probe, 1425 .remove = bcmasp_remove, 1426 .shutdown = bcmasp_shutdown, 1427 .driver = { 1428 .name = "brcm,asp-v2", 1429 .of_match_table = bcmasp_of_match, 1430 .pm = &bcmasp_pm_ops, 1431 }, 1432 }; 1433 module_platform_driver(bcmasp_driver); 1434 1435 MODULE_DESCRIPTION("Broadcom ASP 2.0 Ethernet controller driver"); 1436 MODULE_ALIAS("platform:brcm,asp-v2"); 1437 MODULE_LICENSE("GPL"); 1438