1 /* atl2.h -- atl2 driver definitions
2  *
3  * Copyright(c) 2007 Atheros Corporation. All rights reserved.
4  * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com>
5  * Copyright(c) 2007 Chris Snook <csnook@redhat.com>
6  *
7  * Derived from Intel e1000 driver
8  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms of the GNU General Public License as published by the Free
12  * Software Foundation; either version 2 of the License, or (at your option)
13  * any later version.
14  *
15  * This program is distributed in the hope that it will be useful, but WITHOUT
16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18  * more details.
19  *
20  * You should have received a copy of the GNU General Public License along with
21  * this program; if not, write to the Free Software Foundation, Inc., 59
22  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
23  */
24 
25 #ifndef _ATL2_H_
26 #define _ATL2_H_
27 
28 #include <linux/atomic.h>
29 #include <linux/netdevice.h>
30 
31 #ifndef _ATL2_HW_H_
32 #define _ATL2_HW_H_
33 
34 #ifndef _ATL2_OSDEP_H_
35 #define _ATL2_OSDEP_H_
36 
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/if_ether.h>
41 
42 #include "atlx.h"
43 
44 #ifdef ETHTOOL_OPS_COMPAT
45 int ethtool_ioctl(struct ifreq *ifr);
46 #endif
47 
48 #define PCI_COMMAND_REGISTER	PCI_COMMAND
49 #define CMD_MEM_WRT_INVALIDATE	PCI_COMMAND_INVALIDATE
50 
51 #define ATL2_WRITE_REG(a, reg, value) (iowrite32((value), \
52 	((a)->hw_addr + (reg))))
53 
54 #define ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr))
55 
56 #define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg)))
57 
58 #define ATL2_WRITE_REGB(a, reg, value) (iowrite8((value), \
59 	((a)->hw_addr + (reg))))
60 
61 #define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg)))
62 
63 #define ATL2_WRITE_REGW(a, reg, value) (iowrite16((value), \
64 	((a)->hw_addr + (reg))))
65 
66 #define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg)))
67 
68 #define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \
69 	(iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2))))
70 
71 #define ATL2_READ_REG_ARRAY(a, reg, offset) \
72 	(ioread32(((a)->hw_addr + (reg)) + ((offset) << 2)))
73 
74 #endif /* _ATL2_OSDEP_H_ */
75 
76 struct atl2_adapter;
77 struct atl2_hw;
78 
79 /* function prototype */
80 static s32 atl2_reset_hw(struct atl2_hw *hw);
81 static s32 atl2_read_mac_addr(struct atl2_hw *hw);
82 static s32 atl2_init_hw(struct atl2_hw *hw);
83 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
84 	u16 *duplex);
85 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr);
86 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value);
87 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data);
88 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data);
89 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value);
90 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value);
91 static void atl2_set_mac_addr(struct atl2_hw *hw);
92 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue);
93 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value);
94 static s32 atl2_phy_init(struct atl2_hw *hw);
95 static int atl2_check_eeprom_exist(struct atl2_hw *hw);
96 static void atl2_force_ps(struct atl2_hw *hw);
97 
98 /* register definition */
99 
100 /* Block IDLE Status Register */
101 #define IDLE_STATUS_RXMAC	1	/* 1: RXMAC is non-IDLE */
102 #define IDLE_STATUS_TXMAC	2	/* 1: TXMAC is non-IDLE */
103 #define IDLE_STATUS_DMAR	8	/* 1: DMAR is non-IDLE */
104 #define IDLE_STATUS_DMAW	4	/* 1: DMAW is non-IDLE */
105 
106 /* MDIO Control Register */
107 #define MDIO_WAIT_TIMES		10
108 
109 /* MAC Control Register */
110 #define MAC_CTRL_DBG_TX_BKPRESURE	0x100000	/* 1: TX max backoff */
111 #define MAC_CTRL_MACLP_CLK_PHY		0x8000000	/* 1: 25MHz from phy */
112 #define MAC_CTRL_HALF_LEFT_BUF_SHIFT	28
113 #define MAC_CTRL_HALF_LEFT_BUF_MASK	0xF		/* MAC retry buf x32B */
114 
115 /* Internal SRAM Partition Register */
116 #define REG_SRAM_TXRAM_END	0x1500	/* Internal tail address of TXRAM
117 					 * default: 2byte*1024 */
118 #define REG_SRAM_RXRAM_END	0x1502	/* Internal tail address of RXRAM
119 					 * default: 2byte*1024 */
120 
121 /* Descriptor Control register */
122 #define REG_TXD_BASE_ADDR_LO	0x1544	/* The base address of the Transmit
123 					 * Data Mem low 32-bit(dword align) */
124 #define REG_TXD_MEM_SIZE	0x1548	/* Transmit Data Memory size(by
125 					 * double word , max 256KB) */
126 #define REG_TXS_BASE_ADDR_LO	0x154C	/* The base address of the Transmit
127 					 * Status Memory low 32-bit(dword word
128 					 * align) */
129 #define REG_TXS_MEM_SIZE	0x1550	/* double word unit, max 4*2047
130 					 * bytes. */
131 #define REG_RXD_BASE_ADDR_LO	0x1554	/* The base address of the Transmit
132 					 * Status Memory low 32-bit(unit 8
133 					 * bytes) */
134 #define REG_RXD_BUF_NUM		0x1558	/* Receive Data & Status Memory buffer
135 					 * number (unit 1536bytes, max
136 					 * 1536*2047) */
137 
138 /* DMAR Control Register */
139 #define REG_DMAR	0x1580
140 #define     DMAR_EN	0x1	/* 1: Enable DMAR */
141 
142 /* TX Cur-Through (early tx threshold) Control Register */
143 #define REG_TX_CUT_THRESH	0x1590	/* TxMac begin transmit packet
144 					 * threshold(unit word) */
145 
146 /* DMAW Control Register */
147 #define REG_DMAW	0x15A0
148 #define     DMAW_EN	0x1
149 
150 /* Flow control register */
151 #define REG_PAUSE_ON_TH		0x15A8	/* RXD high watermark of overflow
152 					 * threshold configuration register */
153 #define REG_PAUSE_OFF_TH	0x15AA	/* RXD lower watermark of overflow
154 					 * threshold configuration register */
155 
156 /* Mailbox Register */
157 #define REG_MB_TXD_WR_IDX	0x15f0	/* double word align */
158 #define REG_MB_RXD_RD_IDX	0x15F4	/* RXD Read index (unit: 1536byets) */
159 
160 /* Interrupt Status Register */
161 #define ISR_TIMER	1	/* Interrupt when Timer counts down to zero */
162 #define ISR_MANUAL	2	/* Software manual interrupt, for debug. Set
163 				 * when SW_MAN_INT_EN is set in Table 51
164 				 * Selene Master Control Register
165 				 * (Offset 0x1400). */
166 #define ISR_RXF_OV	4	/* RXF overflow interrupt */
167 #define ISR_TXF_UR	8	/* TXF underrun interrupt */
168 #define ISR_TXS_OV	0x10	/* Internal transmit status buffer full
169 				 * interrupt */
170 #define ISR_RXS_OV	0x20	/* Internal receive status buffer full
171 				 * interrupt */
172 #define ISR_LINK_CHG	0x40	/* Link Status Change Interrupt */
173 #define ISR_HOST_TXD_UR	0x80
174 #define ISR_HOST_RXD_OV	0x100	/* Host rx data memory full , one pulse */
175 #define ISR_DMAR_TO_RST	0x200	/* DMAR op timeout interrupt. SW should
176 				 * do Reset */
177 #define ISR_DMAW_TO_RST	0x400
178 #define ISR_PHY		0x800	/* phy interrupt */
179 #define ISR_TS_UPDATE	0x10000	/* interrupt after new tx pkt status written
180 				 * to host */
181 #define ISR_RS_UPDATE	0x20000	/* interrupt ater new rx pkt status written
182 				 * to host. */
183 #define ISR_TX_EARLY	0x40000	/* interrupt when txmac begin transmit one
184 				 * packet */
185 
186 #define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | ISR_HOST_TXD_UR |\
187 	ISR_TS_UPDATE | ISR_TX_EARLY)
188 #define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | ISR_HOST_RXD_OV |\
189 	 ISR_RS_UPDATE)
190 
191 #define IMR_NORMAL_MASK		(\
192 	/*ISR_LINK_CHG		|*/\
193 	ISR_MANUAL		|\
194 	ISR_DMAR_TO_RST		|\
195 	ISR_DMAW_TO_RST		|\
196 	ISR_PHY			|\
197 	ISR_PHY_LINKDOWN	|\
198 	ISR_TS_UPDATE		|\
199 	ISR_RS_UPDATE)
200 
201 /* Receive MAC Statistics Registers */
202 #define REG_STS_RX_PAUSE	0x1700	/* Num pause packets received */
203 #define REG_STS_RXD_OV		0x1704	/* Num frames dropped due to RX
204 					 * FIFO overflow */
205 #define REG_STS_RXS_OV		0x1708	/* Num frames dropped due to RX
206 					 * Status Buffer Overflow */
207 #define REG_STS_RX_FILTER	0x170C	/* Num packets dropped due to
208 					 * address filtering */
209 
210 /* MII definitions */
211 
212 /* PHY Common Register */
213 #define MII_SMARTSPEED	0x14
214 #define MII_DBG_ADDR	0x1D
215 #define MII_DBG_DATA	0x1E
216 
217 /* PCI Command Register Bit Definitions */
218 #define PCI_REG_COMMAND		0x04
219 #define CMD_IO_SPACE		0x0001
220 #define CMD_MEMORY_SPACE	0x0002
221 #define CMD_BUS_MASTER		0x0004
222 
223 #define MEDIA_TYPE_100M_FULL	1
224 #define MEDIA_TYPE_100M_HALF	2
225 #define MEDIA_TYPE_10M_FULL	3
226 #define MEDIA_TYPE_10M_HALF	4
227 
228 #define AUTONEG_ADVERTISE_SPEED_DEFAULT	0x000F	/* Everything */
229 
230 /* The size (in bytes) of a ethernet packet */
231 #define ENET_HEADER_SIZE		14
232 #define MAXIMUM_ETHERNET_FRAME_SIZE	1518	/* with FCS */
233 #define MINIMUM_ETHERNET_FRAME_SIZE	64	/* with FCS */
234 #define ETHERNET_FCS_SIZE		4
235 #define MAX_JUMBO_FRAME_SIZE		0x2000
236 #define VLAN_SIZE                                               4
237 
238 struct tx_pkt_header {
239 	unsigned pkt_size:11;
240 	unsigned:4;			/* reserved */
241 	unsigned ins_vlan:1;		/* txmac should insert vlan */
242 	unsigned short vlan;		/* vlan tag */
243 };
244 /* FIXME: replace above bitfields with MASK/SHIFT defines below */
245 #define TX_PKT_HEADER_SIZE_MASK		0x7FF
246 #define TX_PKT_HEADER_SIZE_SHIFT	0
247 #define TX_PKT_HEADER_INS_VLAN_MASK	0x1
248 #define TX_PKT_HEADER_INS_VLAN_SHIFT	15
249 #define TX_PKT_HEADER_VLAN_TAG_MASK	0xFFFF
250 #define TX_PKT_HEADER_VLAN_TAG_SHIFT	16
251 
252 struct tx_pkt_status {
253 	unsigned pkt_size:11;
254 	unsigned:5;		/* reserved */
255 	unsigned ok:1;		/* current packet transmitted without error */
256 	unsigned bcast:1;	/* broadcast packet */
257 	unsigned mcast:1;	/* multicast packet */
258 	unsigned pause:1;	/* transmiited a pause frame */
259 	unsigned ctrl:1;
260 	unsigned defer:1;    	/* current packet is xmitted with defer */
261 	unsigned exc_defer:1;
262 	unsigned single_col:1;
263 	unsigned multi_col:1;
264 	unsigned late_col:1;
265 	unsigned abort_col:1;
266 	unsigned underun:1;	/* current packet is aborted
267 				 * due to txram underrun */
268 	unsigned:3;		/* reserved */
269 	unsigned update:1;	/* always 1'b1 in tx_status_buf */
270 };
271 /* FIXME: replace above bitfields with MASK/SHIFT defines below */
272 #define TX_PKT_STATUS_SIZE_MASK		0x7FF
273 #define TX_PKT_STATUS_SIZE_SHIFT	0
274 #define TX_PKT_STATUS_OK_MASK		0x1
275 #define TX_PKT_STATUS_OK_SHIFT		16
276 #define TX_PKT_STATUS_BCAST_MASK	0x1
277 #define TX_PKT_STATUS_BCAST_SHIFT	17
278 #define TX_PKT_STATUS_MCAST_MASK	0x1
279 #define TX_PKT_STATUS_MCAST_SHIFT	18
280 #define TX_PKT_STATUS_PAUSE_MASK	0x1
281 #define TX_PKT_STATUS_PAUSE_SHIFT	19
282 #define TX_PKT_STATUS_CTRL_MASK		0x1
283 #define TX_PKT_STATUS_CTRL_SHIFT	20
284 #define TX_PKT_STATUS_DEFER_MASK	0x1
285 #define TX_PKT_STATUS_DEFER_SHIFT	21
286 #define TX_PKT_STATUS_EXC_DEFER_MASK	0x1
287 #define TX_PKT_STATUS_EXC_DEFER_SHIFT	22
288 #define TX_PKT_STATUS_SINGLE_COL_MASK	0x1
289 #define TX_PKT_STATUS_SINGLE_COL_SHIFT	23
290 #define TX_PKT_STATUS_MULTI_COL_MASK	0x1
291 #define TX_PKT_STATUS_MULTI_COL_SHIFT	24
292 #define TX_PKT_STATUS_LATE_COL_MASK	0x1
293 #define TX_PKT_STATUS_LATE_COL_SHIFT	25
294 #define TX_PKT_STATUS_ABORT_COL_MASK	0x1
295 #define TX_PKT_STATUS_ABORT_COL_SHIFT	26
296 #define TX_PKT_STATUS_UNDERRUN_MASK	0x1
297 #define TX_PKT_STATUS_UNDERRUN_SHIFT	27
298 #define TX_PKT_STATUS_UPDATE_MASK	0x1
299 #define TX_PKT_STATUS_UPDATE_SHIFT	31
300 
301 struct rx_pkt_status {
302 	unsigned pkt_size:11;	/* packet size, max 2047 bytes */
303 	unsigned:5;		/* reserved */
304 	unsigned ok:1;		/* current packet received ok without error */
305 	unsigned bcast:1;	/* current packet is broadcast */
306 	unsigned mcast:1;	/* current packet is multicast */
307 	unsigned pause:1;
308 	unsigned ctrl:1;
309 	unsigned crc:1;		/* received a packet with crc error */
310 	unsigned code:1;	/* received a packet with code error */
311 	unsigned runt:1;	/* received a packet less than 64 bytes
312 				 * with good crc */
313 	unsigned frag:1;	/* received a packet less than 64 bytes
314 				 * with bad crc */
315 	unsigned trunc:1;	/* current frame truncated due to rxram full */
316 	unsigned align:1;	/* this packet is alignment error */
317 	unsigned vlan:1;	/* this packet has vlan */
318 	unsigned:3;		/* reserved */
319 	unsigned update:1;
320 	unsigned short vtag;	/* vlan tag */
321 	unsigned:16;
322 };
323 /* FIXME: replace above bitfields with MASK/SHIFT defines below */
324 #define RX_PKT_STATUS_SIZE_MASK		0x7FF
325 #define RX_PKT_STATUS_SIZE_SHIFT	0
326 #define RX_PKT_STATUS_OK_MASK		0x1
327 #define RX_PKT_STATUS_OK_SHIFT		16
328 #define RX_PKT_STATUS_BCAST_MASK	0x1
329 #define RX_PKT_STATUS_BCAST_SHIFT	17
330 #define RX_PKT_STATUS_MCAST_MASK	0x1
331 #define RX_PKT_STATUS_MCAST_SHIFT	18
332 #define RX_PKT_STATUS_PAUSE_MASK	0x1
333 #define RX_PKT_STATUS_PAUSE_SHIFT	19
334 #define RX_PKT_STATUS_CTRL_MASK		0x1
335 #define RX_PKT_STATUS_CTRL_SHIFT	20
336 #define RX_PKT_STATUS_CRC_MASK		0x1
337 #define RX_PKT_STATUS_CRC_SHIFT		21
338 #define RX_PKT_STATUS_CODE_MASK		0x1
339 #define RX_PKT_STATUS_CODE_SHIFT	22
340 #define RX_PKT_STATUS_RUNT_MASK		0x1
341 #define RX_PKT_STATUS_RUNT_SHIFT	23
342 #define RX_PKT_STATUS_FRAG_MASK		0x1
343 #define RX_PKT_STATUS_FRAG_SHIFT	24
344 #define RX_PKT_STATUS_TRUNK_MASK	0x1
345 #define RX_PKT_STATUS_TRUNK_SHIFT	25
346 #define RX_PKT_STATUS_ALIGN_MASK	0x1
347 #define RX_PKT_STATUS_ALIGN_SHIFT	26
348 #define RX_PKT_STATUS_VLAN_MASK		0x1
349 #define RX_PKT_STATUS_VLAN_SHIFT	27
350 #define RX_PKT_STATUS_UPDATE_MASK	0x1
351 #define RX_PKT_STATUS_UPDATE_SHIFT	31
352 #define RX_PKT_STATUS_VLAN_TAG_MASK	0xFFFF
353 #define RX_PKT_STATUS_VLAN_TAG_SHIFT	32
354 
355 struct rx_desc {
356 	struct rx_pkt_status	status;
357 	unsigned char     	packet[1536-sizeof(struct rx_pkt_status)];
358 };
359 
360 enum atl2_speed_duplex {
361 	atl2_10_half = 0,
362 	atl2_10_full = 1,
363 	atl2_100_half = 2,
364 	atl2_100_full = 3
365 };
366 
367 struct atl2_spi_flash_dev {
368 	const char *manu_name;	/* manufacturer id */
369 	/* op-code */
370 	u8 cmdWRSR;
371 	u8 cmdREAD;
372 	u8 cmdPROGRAM;
373 	u8 cmdWREN;
374 	u8 cmdWRDI;
375 	u8 cmdRDSR;
376 	u8 cmdRDID;
377 	u8 cmdSECTOR_ERASE;
378 	u8 cmdCHIP_ERASE;
379 };
380 
381 /* Structure containing variables used by the shared code (atl2_hw.c) */
382 struct atl2_hw {
383 	u8 __iomem *hw_addr;
384 	void *back;
385 
386 	u8 preamble_len;
387 	u8 max_retry;          /* Retransmission maximum, afterwards the
388 				* packet will be discarded. */
389 	u8 jam_ipg;            /* IPG to start JAM for collision based flow
390 				* control in half-duplex mode. In unit of
391 				* 8-bit time. */
392 	u8 ipgt;               /* Desired back to back inter-packet gap. The
393 				* default is 96-bit time. */
394 	u8 min_ifg;            /* Minimum number of IFG to enforce in between
395 				* RX frames. Frame gap below such IFP is
396 				* dropped. */
397 	u8 ipgr1;              /* 64bit Carrier-Sense window */
398 	u8 ipgr2;              /* 96-bit IPG window */
399 	u8 retry_buf;          /* When half-duplex mode, should hold some
400 				* bytes for mac retry . (8*4bytes unit) */
401 
402 	u16 fc_rxd_hi;
403 	u16 fc_rxd_lo;
404 	u16 lcol;              /* Collision Window */
405 	u16 max_frame_size;
406 
407 	u16 MediaType;
408 	u16 autoneg_advertised;
409 	u16 pci_cmd_word;
410 
411 	u16 mii_autoneg_adv_reg;
412 
413 	u32 mem_rang;
414 	u32 txcw;
415 	u32 mc_filter_type;
416 	u32 num_mc_addrs;
417 	u32 collision_delta;
418 	u32 tx_packet_delta;
419 	u16 phy_spd_default;
420 
421 	u16 device_id;
422 	u16 vendor_id;
423 	u16 subsystem_id;
424 	u16 subsystem_vendor_id;
425 	u8 revision_id;
426 
427 	/* spi flash */
428 	u8 flash_vendor;
429 
430 	u8 dma_fairness;
431 	u8 mac_addr[ETH_ALEN];
432 	u8 perm_mac_addr[ETH_ALEN];
433 
434 	/* FIXME */
435 	/* bool phy_preamble_sup; */
436 	bool phy_configured;
437 };
438 
439 #endif /* _ATL2_HW_H_ */
440 
441 struct atl2_ring_header {
442     /* pointer to the descriptor ring memory */
443     void *desc;
444     /* physical address of the descriptor ring */
445     dma_addr_t dma;
446     /* length of descriptor ring in bytes */
447     unsigned int size;
448 };
449 
450 /* board specific private data structure */
451 struct atl2_adapter {
452 	/* OS defined structs */
453 	struct net_device *netdev;
454 	struct pci_dev *pdev;
455 	u32 wol;
456 	u16 link_speed;
457 	u16 link_duplex;
458 
459 	spinlock_t stats_lock;
460 
461 	struct work_struct reset_task;
462 	struct work_struct link_chg_task;
463 	struct timer_list watchdog_timer;
464 	struct timer_list phy_config_timer;
465 
466 	unsigned long cfg_phy;
467 	bool mac_disabled;
468 
469 	/* All Descriptor memory */
470 	dma_addr_t	ring_dma;
471 	void		*ring_vir_addr;
472 	int		ring_size;
473 
474 	struct tx_pkt_header	*txd_ring;
475 	dma_addr_t	txd_dma;
476 
477 	struct tx_pkt_status	*txs_ring;
478 	dma_addr_t	txs_dma;
479 
480 	struct rx_desc	*rxd_ring;
481 	dma_addr_t	rxd_dma;
482 
483 	u32 txd_ring_size;         /* bytes per unit */
484 	u32 txs_ring_size;         /* dwords per unit */
485 	u32 rxd_ring_size;         /* 1536 bytes per unit */
486 
487 	/* read /write ptr: */
488 	/* host */
489 	u32 txd_write_ptr;
490 	u32 txs_next_clear;
491 	u32 rxd_read_ptr;
492 
493 	/* nic */
494 	atomic_t txd_read_ptr;
495 	atomic_t txs_write_ptr;
496 	u32 rxd_write_ptr;
497 
498 	/* Interrupt Moderator timer ( 2us resolution) */
499 	u16 imt;
500 	/* Interrupt Clear timer (2us resolution) */
501 	u16 ict;
502 
503 	unsigned long flags;
504 	/* structs defined in atl2_hw.h */
505 	u32 bd_number;     /* board number */
506 	bool pci_using_64;
507 	bool have_msi;
508 	struct atl2_hw hw;
509 
510 	u32 usr_cmd;
511 	/* FIXME */
512 	/* u32 regs_buff[ATL2_REGS_LEN]; */
513 	u32 pci_state[16];
514 
515 	u32 *config_space;
516 };
517 
518 enum atl2_state_t {
519 	__ATL2_TESTING,
520 	__ATL2_RESETTING,
521 	__ATL2_DOWN
522 };
523 
524 #endif /* _ATL2_H_ */
525