1 /* 2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved. 3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com> 4 * 5 * Derived from Intel e1000 driver 6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the Free 10 * Software Foundation; either version 2 of the License, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program; if not, write to the Free Software Foundation, Inc., 59 20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 21 */ 22 23 #include <linux/atomic.h> 24 #include <linux/crc32.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/hardirq.h> 29 #include <linux/if_vlan.h> 30 #include <linux/in.h> 31 #include <linux/interrupt.h> 32 #include <linux/ip.h> 33 #include <linux/irqflags.h> 34 #include <linux/irqreturn.h> 35 #include <linux/mii.h> 36 #include <linux/net.h> 37 #include <linux/netdevice.h> 38 #include <linux/pci.h> 39 #include <linux/pci_ids.h> 40 #include <linux/pm.h> 41 #include <linux/skbuff.h> 42 #include <linux/slab.h> 43 #include <linux/spinlock.h> 44 #include <linux/string.h> 45 #include <linux/tcp.h> 46 #include <linux/timer.h> 47 #include <linux/types.h> 48 #include <linux/workqueue.h> 49 50 #include "atl2.h" 51 52 #define ATL2_DRV_VERSION "2.2.3" 53 54 static const char atl2_driver_name[] = "atl2"; 55 static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver"; 56 static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation."; 57 static const char atl2_driver_version[] = ATL2_DRV_VERSION; 58 59 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>"); 60 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver"); 61 MODULE_LICENSE("GPL"); 62 MODULE_VERSION(ATL2_DRV_VERSION); 63 64 /* 65 * atl2_pci_tbl - PCI Device ID Table 66 */ 67 static DEFINE_PCI_DEVICE_TABLE(atl2_pci_tbl) = { 68 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)}, 69 /* required last entry */ 70 {0,} 71 }; 72 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl); 73 74 static void atl2_set_ethtool_ops(struct net_device *netdev); 75 76 static void atl2_check_options(struct atl2_adapter *adapter); 77 78 /** 79 * atl2_sw_init - Initialize general software structures (struct atl2_adapter) 80 * @adapter: board private structure to initialize 81 * 82 * atl2_sw_init initializes the Adapter private data structure. 83 * Fields are initialized based on PCI device information and 84 * OS network device settings (MTU size). 85 */ 86 static int atl2_sw_init(struct atl2_adapter *adapter) 87 { 88 struct atl2_hw *hw = &adapter->hw; 89 struct pci_dev *pdev = adapter->pdev; 90 91 /* PCI config space info */ 92 hw->vendor_id = pdev->vendor; 93 hw->device_id = pdev->device; 94 hw->subsystem_vendor_id = pdev->subsystem_vendor; 95 hw->subsystem_id = pdev->subsystem_device; 96 hw->revision_id = pdev->revision; 97 98 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 99 100 adapter->wol = 0; 101 adapter->ict = 50000; /* ~100ms */ 102 adapter->link_speed = SPEED_0; /* hardware init */ 103 adapter->link_duplex = FULL_DUPLEX; 104 105 hw->phy_configured = false; 106 hw->preamble_len = 7; 107 hw->ipgt = 0x60; 108 hw->min_ifg = 0x50; 109 hw->ipgr1 = 0x40; 110 hw->ipgr2 = 0x60; 111 hw->retry_buf = 2; 112 hw->max_retry = 0xf; 113 hw->lcol = 0x37; 114 hw->jam_ipg = 7; 115 hw->fc_rxd_hi = 0; 116 hw->fc_rxd_lo = 0; 117 hw->max_frame_size = adapter->netdev->mtu; 118 119 spin_lock_init(&adapter->stats_lock); 120 121 set_bit(__ATL2_DOWN, &adapter->flags); 122 123 return 0; 124 } 125 126 /** 127 * atl2_set_multi - Multicast and Promiscuous mode set 128 * @netdev: network interface device structure 129 * 130 * The set_multi entry point is called whenever the multicast address 131 * list or the network interface flags are updated. This routine is 132 * responsible for configuring the hardware for proper multicast, 133 * promiscuous mode, and all-multi behavior. 134 */ 135 static void atl2_set_multi(struct net_device *netdev) 136 { 137 struct atl2_adapter *adapter = netdev_priv(netdev); 138 struct atl2_hw *hw = &adapter->hw; 139 struct netdev_hw_addr *ha; 140 u32 rctl; 141 u32 hash_value; 142 143 /* Check for Promiscuous and All Multicast modes */ 144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); 145 146 if (netdev->flags & IFF_PROMISC) { 147 rctl |= MAC_CTRL_PROMIS_EN; 148 } else if (netdev->flags & IFF_ALLMULTI) { 149 rctl |= MAC_CTRL_MC_ALL_EN; 150 rctl &= ~MAC_CTRL_PROMIS_EN; 151 } else 152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); 153 154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); 155 156 /* clear the old settings from the multicast hash table */ 157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 159 160 /* comoute mc addresses' hash value ,and put it into hash table */ 161 netdev_for_each_mc_addr(ha, netdev) { 162 hash_value = atl2_hash_mc_addr(hw, ha->addr); 163 atl2_hash_set(hw, hash_value); 164 } 165 } 166 167 static void init_ring_ptrs(struct atl2_adapter *adapter) 168 { 169 /* Read / Write Ptr Initialize: */ 170 adapter->txd_write_ptr = 0; 171 atomic_set(&adapter->txd_read_ptr, 0); 172 173 adapter->rxd_read_ptr = 0; 174 adapter->rxd_write_ptr = 0; 175 176 atomic_set(&adapter->txs_write_ptr, 0); 177 adapter->txs_next_clear = 0; 178 } 179 180 /** 181 * atl2_configure - Configure Transmit&Receive Unit after Reset 182 * @adapter: board private structure 183 * 184 * Configure the Tx /Rx unit of the MAC after a reset. 185 */ 186 static int atl2_configure(struct atl2_adapter *adapter) 187 { 188 struct atl2_hw *hw = &adapter->hw; 189 u32 value; 190 191 /* clear interrupt status */ 192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); 193 194 /* set MAC Address */ 195 value = (((u32)hw->mac_addr[2]) << 24) | 196 (((u32)hw->mac_addr[3]) << 16) | 197 (((u32)hw->mac_addr[4]) << 8) | 198 (((u32)hw->mac_addr[5])); 199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); 200 value = (((u32)hw->mac_addr[0]) << 8) | 201 (((u32)hw->mac_addr[1])); 202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); 203 204 /* HI base address */ 205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32)); 207 208 /* LO base address */ 209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, 210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL)); 211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, 212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL)); 213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, 214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL)); 215 216 /* element count */ 217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); 218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); 219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); 220 221 /* config Internal SRAM */ 222 /* 223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); 224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); 225 */ 226 227 /* config IPG/IFG */ 228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << 229 MAC_IPG_IFG_IPGT_SHIFT) | 230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << 231 MAC_IPG_IFG_MIFG_SHIFT) | 232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << 233 MAC_IPG_IFG_IPGR1_SHIFT)| 234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << 235 MAC_IPG_IFG_IPGR2_SHIFT); 236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); 237 238 /* config Half-Duplex Control */ 239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | 240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << 241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | 242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | 243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | 244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << 245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); 246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); 247 248 /* set Interrupt Moderator Timer */ 249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); 250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); 251 252 /* set Interrupt Clear Timer */ 253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); 254 255 /* set MTU */ 256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + 257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE); 258 259 /* 1590 */ 260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); 261 262 /* flow control */ 263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); 264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); 265 266 /* Init mailbox */ 267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); 268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); 269 270 /* enable DMA read/write */ 271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); 272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); 273 274 value = ATL2_READ_REG(&adapter->hw, REG_ISR); 275 if ((value & ISR_PHY_LINKDOWN) != 0) 276 value = 1; /* config failed */ 277 else 278 value = 0; 279 280 /* clear all interrupt status */ 281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); 282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 283 return value; 284 } 285 286 /** 287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources 288 * @adapter: board private structure 289 * 290 * Return 0 on success, negative on failure 291 */ 292 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter) 293 { 294 struct pci_dev *pdev = adapter->pdev; 295 int size; 296 u8 offset = 0; 297 298 /* real ring DMA buffer */ 299 adapter->ring_size = size = 300 adapter->txd_ring_size * 1 + 7 + /* dword align */ 301 adapter->txs_ring_size * 4 + 7 + /* dword align */ 302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */ 303 304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size, 305 &adapter->ring_dma); 306 if (!adapter->ring_vir_addr) 307 return -ENOMEM; 308 memset(adapter->ring_vir_addr, 0, adapter->ring_size); 309 310 /* Init TXD Ring */ 311 adapter->txd_dma = adapter->ring_dma ; 312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0; 313 adapter->txd_dma += offset; 314 adapter->txd_ring = adapter->ring_vir_addr + offset; 315 316 /* Init TXS Ring */ 317 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size; 318 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0; 319 adapter->txs_dma += offset; 320 adapter->txs_ring = (struct tx_pkt_status *) 321 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset)); 322 323 /* Init RXD Ring */ 324 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4; 325 offset = (adapter->rxd_dma & 127) ? 326 (128 - (adapter->rxd_dma & 127)) : 0; 327 if (offset > 7) 328 offset -= 8; 329 else 330 offset += (128 - 8); 331 332 adapter->rxd_dma += offset; 333 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) + 334 (adapter->txs_ring_size * 4 + offset)); 335 336 /* 337 * Read / Write Ptr Initialize: 338 * init_ring_ptrs(adapter); 339 */ 340 return 0; 341 } 342 343 /** 344 * atl2_irq_enable - Enable default interrupt generation settings 345 * @adapter: board private structure 346 */ 347 static inline void atl2_irq_enable(struct atl2_adapter *adapter) 348 { 349 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); 350 ATL2_WRITE_FLUSH(&adapter->hw); 351 } 352 353 /** 354 * atl2_irq_disable - Mask off interrupt generation on the NIC 355 * @adapter: board private structure 356 */ 357 static inline void atl2_irq_disable(struct atl2_adapter *adapter) 358 { 359 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); 360 ATL2_WRITE_FLUSH(&adapter->hw); 361 synchronize_irq(adapter->pdev->irq); 362 } 363 364 static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl) 365 { 366 if (features & NETIF_F_HW_VLAN_CTAG_RX) { 367 /* enable VLAN tag insert/strip */ 368 *ctrl |= MAC_CTRL_RMV_VLAN; 369 } else { 370 /* disable VLAN tag insert/strip */ 371 *ctrl &= ~MAC_CTRL_RMV_VLAN; 372 } 373 } 374 375 static void atl2_vlan_mode(struct net_device *netdev, 376 netdev_features_t features) 377 { 378 struct atl2_adapter *adapter = netdev_priv(netdev); 379 u32 ctrl; 380 381 atl2_irq_disable(adapter); 382 383 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); 384 __atl2_vlan_mode(features, &ctrl); 385 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); 386 387 atl2_irq_enable(adapter); 388 } 389 390 static void atl2_restore_vlan(struct atl2_adapter *adapter) 391 { 392 atl2_vlan_mode(adapter->netdev, adapter->netdev->features); 393 } 394 395 static netdev_features_t atl2_fix_features(struct net_device *netdev, 396 netdev_features_t features) 397 { 398 /* 399 * Since there is no support for separate rx/tx vlan accel 400 * enable/disable make sure tx flag is always in same state as rx. 401 */ 402 if (features & NETIF_F_HW_VLAN_CTAG_RX) 403 features |= NETIF_F_HW_VLAN_CTAG_TX; 404 else 405 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 406 407 return features; 408 } 409 410 static int atl2_set_features(struct net_device *netdev, 411 netdev_features_t features) 412 { 413 netdev_features_t changed = netdev->features ^ features; 414 415 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 416 atl2_vlan_mode(netdev, features); 417 418 return 0; 419 } 420 421 static void atl2_intr_rx(struct atl2_adapter *adapter) 422 { 423 struct net_device *netdev = adapter->netdev; 424 struct rx_desc *rxd; 425 struct sk_buff *skb; 426 427 do { 428 rxd = adapter->rxd_ring+adapter->rxd_write_ptr; 429 if (!rxd->status.update) 430 break; /* end of tx */ 431 432 /* clear this flag at once */ 433 rxd->status.update = 0; 434 435 if (rxd->status.ok && rxd->status.pkt_size >= 60) { 436 int rx_size = (int)(rxd->status.pkt_size - 4); 437 /* alloc new buffer */ 438 skb = netdev_alloc_skb_ip_align(netdev, rx_size); 439 if (NULL == skb) { 440 /* 441 * Check that some rx space is free. If not, 442 * free one and mark stats->rx_dropped++. 443 */ 444 netdev->stats.rx_dropped++; 445 break; 446 } 447 memcpy(skb->data, rxd->packet, rx_size); 448 skb_put(skb, rx_size); 449 skb->protocol = eth_type_trans(skb, netdev); 450 if (rxd->status.vlan) { 451 u16 vlan_tag = (rxd->status.vtag>>4) | 452 ((rxd->status.vtag&7) << 13) | 453 ((rxd->status.vtag&8) << 9); 454 455 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 456 } 457 netif_rx(skb); 458 netdev->stats.rx_bytes += rx_size; 459 netdev->stats.rx_packets++; 460 } else { 461 netdev->stats.rx_errors++; 462 463 if (rxd->status.ok && rxd->status.pkt_size <= 60) 464 netdev->stats.rx_length_errors++; 465 if (rxd->status.mcast) 466 netdev->stats.multicast++; 467 if (rxd->status.crc) 468 netdev->stats.rx_crc_errors++; 469 if (rxd->status.align) 470 netdev->stats.rx_frame_errors++; 471 } 472 473 /* advance write ptr */ 474 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size) 475 adapter->rxd_write_ptr = 0; 476 } while (1); 477 478 /* update mailbox? */ 479 adapter->rxd_read_ptr = adapter->rxd_write_ptr; 480 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); 481 } 482 483 static void atl2_intr_tx(struct atl2_adapter *adapter) 484 { 485 struct net_device *netdev = adapter->netdev; 486 u32 txd_read_ptr; 487 u32 txs_write_ptr; 488 struct tx_pkt_status *txs; 489 struct tx_pkt_header *txph; 490 int free_hole = 0; 491 492 do { 493 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 494 txs = adapter->txs_ring + txs_write_ptr; 495 if (!txs->update) 496 break; /* tx stop here */ 497 498 free_hole = 1; 499 txs->update = 0; 500 501 if (++txs_write_ptr == adapter->txs_ring_size) 502 txs_write_ptr = 0; 503 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr); 504 505 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr); 506 txph = (struct tx_pkt_header *) 507 (((u8 *)adapter->txd_ring) + txd_read_ptr); 508 509 if (txph->pkt_size != txs->pkt_size) { 510 struct tx_pkt_status *old_txs = txs; 511 printk(KERN_WARNING 512 "%s: txs packet size not consistent with txd" 513 " txd_:0x%08x, txs_:0x%08x!\n", 514 adapter->netdev->name, 515 *(u32 *)txph, *(u32 *)txs); 516 printk(KERN_WARNING 517 "txd read ptr: 0x%x\n", 518 txd_read_ptr); 519 txs = adapter->txs_ring + txs_write_ptr; 520 printk(KERN_WARNING 521 "txs-behind:0x%08x\n", 522 *(u32 *)txs); 523 if (txs_write_ptr < 2) { 524 txs = adapter->txs_ring + 525 (adapter->txs_ring_size + 526 txs_write_ptr - 2); 527 } else { 528 txs = adapter->txs_ring + (txs_write_ptr - 2); 529 } 530 printk(KERN_WARNING 531 "txs-before:0x%08x\n", 532 *(u32 *)txs); 533 txs = old_txs; 534 } 535 536 /* 4for TPH */ 537 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3); 538 if (txd_read_ptr >= adapter->txd_ring_size) 539 txd_read_ptr -= adapter->txd_ring_size; 540 541 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr); 542 543 /* tx statistics: */ 544 if (txs->ok) { 545 netdev->stats.tx_bytes += txs->pkt_size; 546 netdev->stats.tx_packets++; 547 } 548 else 549 netdev->stats.tx_errors++; 550 551 if (txs->defer) 552 netdev->stats.collisions++; 553 if (txs->abort_col) 554 netdev->stats.tx_aborted_errors++; 555 if (txs->late_col) 556 netdev->stats.tx_window_errors++; 557 if (txs->underun) 558 netdev->stats.tx_fifo_errors++; 559 } while (1); 560 561 if (free_hole) { 562 if (netif_queue_stopped(adapter->netdev) && 563 netif_carrier_ok(adapter->netdev)) 564 netif_wake_queue(adapter->netdev); 565 } 566 } 567 568 static void atl2_check_for_link(struct atl2_adapter *adapter) 569 { 570 struct net_device *netdev = adapter->netdev; 571 u16 phy_data = 0; 572 573 spin_lock(&adapter->stats_lock); 574 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 575 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 576 spin_unlock(&adapter->stats_lock); 577 578 /* notify upper layer link down ASAP */ 579 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */ 580 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 581 printk(KERN_INFO "%s: %s NIC Link is Down\n", 582 atl2_driver_name, netdev->name); 583 adapter->link_speed = SPEED_0; 584 netif_carrier_off(netdev); 585 netif_stop_queue(netdev); 586 } 587 } 588 schedule_work(&adapter->link_chg_task); 589 } 590 591 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter) 592 { 593 u16 phy_data; 594 spin_lock(&adapter->stats_lock); 595 atl2_read_phy_reg(&adapter->hw, 19, &phy_data); 596 spin_unlock(&adapter->stats_lock); 597 } 598 599 /** 600 * atl2_intr - Interrupt Handler 601 * @irq: interrupt number 602 * @data: pointer to a network interface device structure 603 */ 604 static irqreturn_t atl2_intr(int irq, void *data) 605 { 606 struct atl2_adapter *adapter = netdev_priv(data); 607 struct atl2_hw *hw = &adapter->hw; 608 u32 status; 609 610 status = ATL2_READ_REG(hw, REG_ISR); 611 if (0 == status) 612 return IRQ_NONE; 613 614 /* link event */ 615 if (status & ISR_PHY) 616 atl2_clear_phy_int(adapter); 617 618 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 619 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); 620 621 /* check if PCIE PHY Link down */ 622 if (status & ISR_PHY_LINKDOWN) { 623 if (netif_running(adapter->netdev)) { /* reset MAC */ 624 ATL2_WRITE_REG(hw, REG_ISR, 0); 625 ATL2_WRITE_REG(hw, REG_IMR, 0); 626 ATL2_WRITE_FLUSH(hw); 627 schedule_work(&adapter->reset_task); 628 return IRQ_HANDLED; 629 } 630 } 631 632 /* check if DMA read/write error? */ 633 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 634 ATL2_WRITE_REG(hw, REG_ISR, 0); 635 ATL2_WRITE_REG(hw, REG_IMR, 0); 636 ATL2_WRITE_FLUSH(hw); 637 schedule_work(&adapter->reset_task); 638 return IRQ_HANDLED; 639 } 640 641 /* link event */ 642 if (status & (ISR_PHY | ISR_MANUAL)) { 643 adapter->netdev->stats.tx_carrier_errors++; 644 atl2_check_for_link(adapter); 645 } 646 647 /* transmit event */ 648 if (status & ISR_TX_EVENT) 649 atl2_intr_tx(adapter); 650 651 /* rx exception */ 652 if (status & ISR_RX_EVENT) 653 atl2_intr_rx(adapter); 654 655 /* re-enable Interrupt */ 656 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 657 return IRQ_HANDLED; 658 } 659 660 static int atl2_request_irq(struct atl2_adapter *adapter) 661 { 662 struct net_device *netdev = adapter->netdev; 663 int flags, err = 0; 664 665 flags = IRQF_SHARED; 666 adapter->have_msi = true; 667 err = pci_enable_msi(adapter->pdev); 668 if (err) 669 adapter->have_msi = false; 670 671 if (adapter->have_msi) 672 flags &= ~IRQF_SHARED; 673 674 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name, 675 netdev); 676 } 677 678 /** 679 * atl2_free_ring_resources - Free Tx / RX descriptor Resources 680 * @adapter: board private structure 681 * 682 * Free all transmit software resources 683 */ 684 static void atl2_free_ring_resources(struct atl2_adapter *adapter) 685 { 686 struct pci_dev *pdev = adapter->pdev; 687 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, 688 adapter->ring_dma); 689 } 690 691 /** 692 * atl2_open - Called when a network interface is made active 693 * @netdev: network interface device structure 694 * 695 * Returns 0 on success, negative value on failure 696 * 697 * The open entry point is called when a network interface is made 698 * active by the system (IFF_UP). At this point all resources needed 699 * for transmit and receive operations are allocated, the interrupt 700 * handler is registered with the OS, the watchdog timer is started, 701 * and the stack is notified that the interface is ready. 702 */ 703 static int atl2_open(struct net_device *netdev) 704 { 705 struct atl2_adapter *adapter = netdev_priv(netdev); 706 int err; 707 u32 val; 708 709 /* disallow open during test */ 710 if (test_bit(__ATL2_TESTING, &adapter->flags)) 711 return -EBUSY; 712 713 /* allocate transmit descriptors */ 714 err = atl2_setup_ring_resources(adapter); 715 if (err) 716 return err; 717 718 err = atl2_init_hw(&adapter->hw); 719 if (err) { 720 err = -EIO; 721 goto err_init_hw; 722 } 723 724 /* hardware has been reset, we need to reload some things */ 725 atl2_set_multi(netdev); 726 init_ring_ptrs(adapter); 727 728 atl2_restore_vlan(adapter); 729 730 if (atl2_configure(adapter)) { 731 err = -EIO; 732 goto err_config; 733 } 734 735 err = atl2_request_irq(adapter); 736 if (err) 737 goto err_req_irq; 738 739 clear_bit(__ATL2_DOWN, &adapter->flags); 740 741 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ)); 742 743 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 744 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, 745 val | MASTER_CTRL_MANUAL_INT); 746 747 atl2_irq_enable(adapter); 748 749 return 0; 750 751 err_init_hw: 752 err_req_irq: 753 err_config: 754 atl2_free_ring_resources(adapter); 755 atl2_reset_hw(&adapter->hw); 756 757 return err; 758 } 759 760 static void atl2_down(struct atl2_adapter *adapter) 761 { 762 struct net_device *netdev = adapter->netdev; 763 764 /* signal that we're down so the interrupt handler does not 765 * reschedule our watchdog timer */ 766 set_bit(__ATL2_DOWN, &adapter->flags); 767 768 netif_tx_disable(netdev); 769 770 /* reset MAC to disable all RX/TX */ 771 atl2_reset_hw(&adapter->hw); 772 msleep(1); 773 774 atl2_irq_disable(adapter); 775 776 del_timer_sync(&adapter->watchdog_timer); 777 del_timer_sync(&adapter->phy_config_timer); 778 clear_bit(0, &adapter->cfg_phy); 779 780 netif_carrier_off(netdev); 781 adapter->link_speed = SPEED_0; 782 adapter->link_duplex = -1; 783 } 784 785 static void atl2_free_irq(struct atl2_adapter *adapter) 786 { 787 struct net_device *netdev = adapter->netdev; 788 789 free_irq(adapter->pdev->irq, netdev); 790 791 #ifdef CONFIG_PCI_MSI 792 if (adapter->have_msi) 793 pci_disable_msi(adapter->pdev); 794 #endif 795 } 796 797 /** 798 * atl2_close - Disables a network interface 799 * @netdev: network interface device structure 800 * 801 * Returns 0, this is not allowed to fail 802 * 803 * The close entry point is called when an interface is de-activated 804 * by the OS. The hardware is still under the drivers control, but 805 * needs to be disabled. A global MAC reset is issued to stop the 806 * hardware, and all transmit and receive resources are freed. 807 */ 808 static int atl2_close(struct net_device *netdev) 809 { 810 struct atl2_adapter *adapter = netdev_priv(netdev); 811 812 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 813 814 atl2_down(adapter); 815 atl2_free_irq(adapter); 816 atl2_free_ring_resources(adapter); 817 818 return 0; 819 } 820 821 static inline int TxsFreeUnit(struct atl2_adapter *adapter) 822 { 823 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 824 825 return (adapter->txs_next_clear >= txs_write_ptr) ? 826 (int) (adapter->txs_ring_size - adapter->txs_next_clear + 827 txs_write_ptr - 1) : 828 (int) (txs_write_ptr - adapter->txs_next_clear - 1); 829 } 830 831 static inline int TxdFreeBytes(struct atl2_adapter *adapter) 832 { 833 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr); 834 835 return (adapter->txd_write_ptr >= txd_read_ptr) ? 836 (int) (adapter->txd_ring_size - adapter->txd_write_ptr + 837 txd_read_ptr - 1) : 838 (int) (txd_read_ptr - adapter->txd_write_ptr - 1); 839 } 840 841 static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb, 842 struct net_device *netdev) 843 { 844 struct atl2_adapter *adapter = netdev_priv(netdev); 845 struct tx_pkt_header *txph; 846 u32 offset, copy_len; 847 int txs_unused; 848 int txbuf_unused; 849 850 if (test_bit(__ATL2_DOWN, &adapter->flags)) { 851 dev_kfree_skb_any(skb); 852 return NETDEV_TX_OK; 853 } 854 855 if (unlikely(skb->len <= 0)) { 856 dev_kfree_skb_any(skb); 857 return NETDEV_TX_OK; 858 } 859 860 txs_unused = TxsFreeUnit(adapter); 861 txbuf_unused = TxdFreeBytes(adapter); 862 863 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused || 864 txs_unused < 1) { 865 /* not enough resources */ 866 netif_stop_queue(netdev); 867 return NETDEV_TX_BUSY; 868 } 869 870 offset = adapter->txd_write_ptr; 871 872 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset); 873 874 *(u32 *)txph = 0; 875 txph->pkt_size = skb->len; 876 877 offset += 4; 878 if (offset >= adapter->txd_ring_size) 879 offset -= adapter->txd_ring_size; 880 copy_len = adapter->txd_ring_size - offset; 881 if (copy_len >= skb->len) { 882 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len); 883 offset += ((u32)(skb->len + 3) & ~3); 884 } else { 885 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len); 886 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len, 887 skb->len-copy_len); 888 offset = ((u32)(skb->len-copy_len + 3) & ~3); 889 } 890 #ifdef NETIF_F_HW_VLAN_CTAG_TX 891 if (vlan_tx_tag_present(skb)) { 892 u16 vlan_tag = vlan_tx_tag_get(skb); 893 vlan_tag = (vlan_tag << 4) | 894 (vlan_tag >> 13) | 895 ((vlan_tag >> 9) & 0x8); 896 txph->ins_vlan = 1; 897 txph->vlan = vlan_tag; 898 } 899 #endif 900 if (offset >= adapter->txd_ring_size) 901 offset -= adapter->txd_ring_size; 902 adapter->txd_write_ptr = offset; 903 904 /* clear txs before send */ 905 adapter->txs_ring[adapter->txs_next_clear].update = 0; 906 if (++adapter->txs_next_clear == adapter->txs_ring_size) 907 adapter->txs_next_clear = 0; 908 909 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, 910 (adapter->txd_write_ptr >> 2)); 911 912 mmiowb(); 913 dev_kfree_skb_any(skb); 914 return NETDEV_TX_OK; 915 } 916 917 /** 918 * atl2_change_mtu - Change the Maximum Transfer Unit 919 * @netdev: network interface device structure 920 * @new_mtu: new value for maximum frame size 921 * 922 * Returns 0 on success, negative on failure 923 */ 924 static int atl2_change_mtu(struct net_device *netdev, int new_mtu) 925 { 926 struct atl2_adapter *adapter = netdev_priv(netdev); 927 struct atl2_hw *hw = &adapter->hw; 928 929 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE))) 930 return -EINVAL; 931 932 /* set MTU */ 933 if (hw->max_frame_size != new_mtu) { 934 netdev->mtu = new_mtu; 935 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE + 936 VLAN_SIZE + ETHERNET_FCS_SIZE); 937 } 938 939 return 0; 940 } 941 942 /** 943 * atl2_set_mac - Change the Ethernet Address of the NIC 944 * @netdev: network interface device structure 945 * @p: pointer to an address structure 946 * 947 * Returns 0 on success, negative on failure 948 */ 949 static int atl2_set_mac(struct net_device *netdev, void *p) 950 { 951 struct atl2_adapter *adapter = netdev_priv(netdev); 952 struct sockaddr *addr = p; 953 954 if (!is_valid_ether_addr(addr->sa_data)) 955 return -EADDRNOTAVAIL; 956 957 if (netif_running(netdev)) 958 return -EBUSY; 959 960 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 961 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); 962 963 atl2_set_mac_addr(&adapter->hw); 964 965 return 0; 966 } 967 968 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 969 { 970 struct atl2_adapter *adapter = netdev_priv(netdev); 971 struct mii_ioctl_data *data = if_mii(ifr); 972 unsigned long flags; 973 974 switch (cmd) { 975 case SIOCGMIIPHY: 976 data->phy_id = 0; 977 break; 978 case SIOCGMIIREG: 979 spin_lock_irqsave(&adapter->stats_lock, flags); 980 if (atl2_read_phy_reg(&adapter->hw, 981 data->reg_num & 0x1F, &data->val_out)) { 982 spin_unlock_irqrestore(&adapter->stats_lock, flags); 983 return -EIO; 984 } 985 spin_unlock_irqrestore(&adapter->stats_lock, flags); 986 break; 987 case SIOCSMIIREG: 988 if (data->reg_num & ~(0x1F)) 989 return -EFAULT; 990 spin_lock_irqsave(&adapter->stats_lock, flags); 991 if (atl2_write_phy_reg(&adapter->hw, data->reg_num, 992 data->val_in)) { 993 spin_unlock_irqrestore(&adapter->stats_lock, flags); 994 return -EIO; 995 } 996 spin_unlock_irqrestore(&adapter->stats_lock, flags); 997 break; 998 default: 999 return -EOPNOTSUPP; 1000 } 1001 return 0; 1002 } 1003 1004 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1005 { 1006 switch (cmd) { 1007 case SIOCGMIIPHY: 1008 case SIOCGMIIREG: 1009 case SIOCSMIIREG: 1010 return atl2_mii_ioctl(netdev, ifr, cmd); 1011 #ifdef ETHTOOL_OPS_COMPAT 1012 case SIOCETHTOOL: 1013 return ethtool_ioctl(ifr); 1014 #endif 1015 default: 1016 return -EOPNOTSUPP; 1017 } 1018 } 1019 1020 /** 1021 * atl2_tx_timeout - Respond to a Tx Hang 1022 * @netdev: network interface device structure 1023 */ 1024 static void atl2_tx_timeout(struct net_device *netdev) 1025 { 1026 struct atl2_adapter *adapter = netdev_priv(netdev); 1027 1028 /* Do the reset outside of interrupt context */ 1029 schedule_work(&adapter->reset_task); 1030 } 1031 1032 /** 1033 * atl2_watchdog - Timer Call-back 1034 * @data: pointer to netdev cast into an unsigned long 1035 */ 1036 static void atl2_watchdog(unsigned long data) 1037 { 1038 struct atl2_adapter *adapter = (struct atl2_adapter *) data; 1039 1040 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1041 u32 drop_rxd, drop_rxs; 1042 unsigned long flags; 1043 1044 spin_lock_irqsave(&adapter->stats_lock, flags); 1045 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); 1046 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); 1047 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1048 1049 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs; 1050 1051 /* Reset the timer */ 1052 mod_timer(&adapter->watchdog_timer, 1053 round_jiffies(jiffies + 4 * HZ)); 1054 } 1055 } 1056 1057 /** 1058 * atl2_phy_config - Timer Call-back 1059 * @data: pointer to netdev cast into an unsigned long 1060 */ 1061 static void atl2_phy_config(unsigned long data) 1062 { 1063 struct atl2_adapter *adapter = (struct atl2_adapter *) data; 1064 struct atl2_hw *hw = &adapter->hw; 1065 unsigned long flags; 1066 1067 spin_lock_irqsave(&adapter->stats_lock, flags); 1068 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 1069 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN | 1070 MII_CR_RESTART_AUTO_NEG); 1071 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1072 clear_bit(0, &adapter->cfg_phy); 1073 } 1074 1075 static int atl2_up(struct atl2_adapter *adapter) 1076 { 1077 struct net_device *netdev = adapter->netdev; 1078 int err = 0; 1079 u32 val; 1080 1081 /* hardware has been reset, we need to reload some things */ 1082 1083 err = atl2_init_hw(&adapter->hw); 1084 if (err) { 1085 err = -EIO; 1086 return err; 1087 } 1088 1089 atl2_set_multi(netdev); 1090 init_ring_ptrs(adapter); 1091 1092 atl2_restore_vlan(adapter); 1093 1094 if (atl2_configure(adapter)) { 1095 err = -EIO; 1096 goto err_up; 1097 } 1098 1099 clear_bit(__ATL2_DOWN, &adapter->flags); 1100 1101 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 1102 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | 1103 MASTER_CTRL_MANUAL_INT); 1104 1105 atl2_irq_enable(adapter); 1106 1107 err_up: 1108 return err; 1109 } 1110 1111 static void atl2_reinit_locked(struct atl2_adapter *adapter) 1112 { 1113 WARN_ON(in_interrupt()); 1114 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1115 msleep(1); 1116 atl2_down(adapter); 1117 atl2_up(adapter); 1118 clear_bit(__ATL2_RESETTING, &adapter->flags); 1119 } 1120 1121 static void atl2_reset_task(struct work_struct *work) 1122 { 1123 struct atl2_adapter *adapter; 1124 adapter = container_of(work, struct atl2_adapter, reset_task); 1125 1126 atl2_reinit_locked(adapter); 1127 } 1128 1129 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter) 1130 { 1131 u32 value; 1132 struct atl2_hw *hw = &adapter->hw; 1133 struct net_device *netdev = adapter->netdev; 1134 1135 /* Config MAC CTRL Register */ 1136 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1137 1138 /* duplex */ 1139 if (FULL_DUPLEX == adapter->link_duplex) 1140 value |= MAC_CTRL_DUPLX; 1141 1142 /* flow control */ 1143 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 1144 1145 /* PAD & CRC */ 1146 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1147 1148 /* preamble length */ 1149 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << 1150 MAC_CTRL_PRMLEN_SHIFT); 1151 1152 /* vlan */ 1153 __atl2_vlan_mode(netdev->features, &value); 1154 1155 /* filter mode */ 1156 value |= MAC_CTRL_BC_EN; 1157 if (netdev->flags & IFF_PROMISC) 1158 value |= MAC_CTRL_PROMIS_EN; 1159 else if (netdev->flags & IFF_ALLMULTI) 1160 value |= MAC_CTRL_MC_ALL_EN; 1161 1162 /* half retry buffer */ 1163 value |= (((u32)(adapter->hw.retry_buf & 1164 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1165 1166 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1167 } 1168 1169 static int atl2_check_link(struct atl2_adapter *adapter) 1170 { 1171 struct atl2_hw *hw = &adapter->hw; 1172 struct net_device *netdev = adapter->netdev; 1173 int ret_val; 1174 u16 speed, duplex, phy_data; 1175 int reconfig = 0; 1176 1177 /* MII_BMSR must read twise */ 1178 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1179 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1180 if (!(phy_data&BMSR_LSTATUS)) { /* link down */ 1181 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 1182 u32 value; 1183 /* disable rx */ 1184 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1185 value &= ~MAC_CTRL_RX_EN; 1186 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1187 adapter->link_speed = SPEED_0; 1188 netif_carrier_off(netdev); 1189 netif_stop_queue(netdev); 1190 } 1191 return 0; 1192 } 1193 1194 /* Link Up */ 1195 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1196 if (ret_val) 1197 return ret_val; 1198 switch (hw->MediaType) { 1199 case MEDIA_TYPE_100M_FULL: 1200 if (speed != SPEED_100 || duplex != FULL_DUPLEX) 1201 reconfig = 1; 1202 break; 1203 case MEDIA_TYPE_100M_HALF: 1204 if (speed != SPEED_100 || duplex != HALF_DUPLEX) 1205 reconfig = 1; 1206 break; 1207 case MEDIA_TYPE_10M_FULL: 1208 if (speed != SPEED_10 || duplex != FULL_DUPLEX) 1209 reconfig = 1; 1210 break; 1211 case MEDIA_TYPE_10M_HALF: 1212 if (speed != SPEED_10 || duplex != HALF_DUPLEX) 1213 reconfig = 1; 1214 break; 1215 } 1216 /* link result is our setting */ 1217 if (reconfig == 0) { 1218 if (adapter->link_speed != speed || 1219 adapter->link_duplex != duplex) { 1220 adapter->link_speed = speed; 1221 adapter->link_duplex = duplex; 1222 atl2_setup_mac_ctrl(adapter); 1223 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n", 1224 atl2_driver_name, netdev->name, 1225 adapter->link_speed, 1226 adapter->link_duplex == FULL_DUPLEX ? 1227 "Full Duplex" : "Half Duplex"); 1228 } 1229 1230 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */ 1231 netif_carrier_on(netdev); 1232 netif_wake_queue(netdev); 1233 } 1234 return 0; 1235 } 1236 1237 /* change original link status */ 1238 if (netif_carrier_ok(netdev)) { 1239 u32 value; 1240 /* disable rx */ 1241 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1242 value &= ~MAC_CTRL_RX_EN; 1243 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1244 1245 adapter->link_speed = SPEED_0; 1246 netif_carrier_off(netdev); 1247 netif_stop_queue(netdev); 1248 } 1249 1250 /* auto-neg, insert timer to re-config phy 1251 * (if interval smaller than 5 seconds, something strange) */ 1252 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1253 if (!test_and_set_bit(0, &adapter->cfg_phy)) 1254 mod_timer(&adapter->phy_config_timer, 1255 round_jiffies(jiffies + 5 * HZ)); 1256 } 1257 1258 return 0; 1259 } 1260 1261 /** 1262 * atl2_link_chg_task - deal with link change event Out of interrupt context 1263 */ 1264 static void atl2_link_chg_task(struct work_struct *work) 1265 { 1266 struct atl2_adapter *adapter; 1267 unsigned long flags; 1268 1269 adapter = container_of(work, struct atl2_adapter, link_chg_task); 1270 1271 spin_lock_irqsave(&adapter->stats_lock, flags); 1272 atl2_check_link(adapter); 1273 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1274 } 1275 1276 static void atl2_setup_pcicmd(struct pci_dev *pdev) 1277 { 1278 u16 cmd; 1279 1280 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1281 1282 if (cmd & PCI_COMMAND_INTX_DISABLE) 1283 cmd &= ~PCI_COMMAND_INTX_DISABLE; 1284 if (cmd & PCI_COMMAND_IO) 1285 cmd &= ~PCI_COMMAND_IO; 1286 if (0 == (cmd & PCI_COMMAND_MEMORY)) 1287 cmd |= PCI_COMMAND_MEMORY; 1288 if (0 == (cmd & PCI_COMMAND_MASTER)) 1289 cmd |= PCI_COMMAND_MASTER; 1290 pci_write_config_word(pdev, PCI_COMMAND, cmd); 1291 1292 /* 1293 * some motherboards BIOS(PXE/EFI) driver may set PME 1294 * while they transfer control to OS (Windows/Linux) 1295 * so we should clear this bit before NIC work normally 1296 */ 1297 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); 1298 } 1299 1300 #ifdef CONFIG_NET_POLL_CONTROLLER 1301 static void atl2_poll_controller(struct net_device *netdev) 1302 { 1303 disable_irq(netdev->irq); 1304 atl2_intr(netdev->irq, netdev); 1305 enable_irq(netdev->irq); 1306 } 1307 #endif 1308 1309 1310 static const struct net_device_ops atl2_netdev_ops = { 1311 .ndo_open = atl2_open, 1312 .ndo_stop = atl2_close, 1313 .ndo_start_xmit = atl2_xmit_frame, 1314 .ndo_set_rx_mode = atl2_set_multi, 1315 .ndo_validate_addr = eth_validate_addr, 1316 .ndo_set_mac_address = atl2_set_mac, 1317 .ndo_change_mtu = atl2_change_mtu, 1318 .ndo_fix_features = atl2_fix_features, 1319 .ndo_set_features = atl2_set_features, 1320 .ndo_do_ioctl = atl2_ioctl, 1321 .ndo_tx_timeout = atl2_tx_timeout, 1322 #ifdef CONFIG_NET_POLL_CONTROLLER 1323 .ndo_poll_controller = atl2_poll_controller, 1324 #endif 1325 }; 1326 1327 /** 1328 * atl2_probe - Device Initialization Routine 1329 * @pdev: PCI device information struct 1330 * @ent: entry in atl2_pci_tbl 1331 * 1332 * Returns 0 on success, negative on failure 1333 * 1334 * atl2_probe initializes an adapter identified by a pci_dev structure. 1335 * The OS initialization, configuring of the adapter private structure, 1336 * and a hardware reset occur. 1337 */ 1338 static int atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1339 { 1340 struct net_device *netdev; 1341 struct atl2_adapter *adapter; 1342 static int cards_found; 1343 unsigned long mmio_start; 1344 int mmio_len; 1345 int err; 1346 1347 cards_found = 0; 1348 1349 err = pci_enable_device(pdev); 1350 if (err) 1351 return err; 1352 1353 /* 1354 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA 1355 * until the kernel has the proper infrastructure to support 64-bit DMA 1356 * on these devices. 1357 */ 1358 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) && 1359 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 1360 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n"); 1361 goto err_dma; 1362 } 1363 1364 /* Mark all PCI regions associated with PCI device 1365 * pdev as being reserved by owner atl2_driver_name */ 1366 err = pci_request_regions(pdev, atl2_driver_name); 1367 if (err) 1368 goto err_pci_reg; 1369 1370 /* Enables bus-mastering on the device and calls 1371 * pcibios_set_master to do the needed arch specific settings */ 1372 pci_set_master(pdev); 1373 1374 err = -ENOMEM; 1375 netdev = alloc_etherdev(sizeof(struct atl2_adapter)); 1376 if (!netdev) 1377 goto err_alloc_etherdev; 1378 1379 SET_NETDEV_DEV(netdev, &pdev->dev); 1380 1381 pci_set_drvdata(pdev, netdev); 1382 adapter = netdev_priv(netdev); 1383 adapter->netdev = netdev; 1384 adapter->pdev = pdev; 1385 adapter->hw.back = adapter; 1386 1387 mmio_start = pci_resource_start(pdev, 0x0); 1388 mmio_len = pci_resource_len(pdev, 0x0); 1389 1390 adapter->hw.mem_rang = (u32)mmio_len; 1391 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 1392 if (!adapter->hw.hw_addr) { 1393 err = -EIO; 1394 goto err_ioremap; 1395 } 1396 1397 atl2_setup_pcicmd(pdev); 1398 1399 netdev->netdev_ops = &atl2_netdev_ops; 1400 atl2_set_ethtool_ops(netdev); 1401 netdev->watchdog_timeo = 5 * HZ; 1402 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 1403 1404 netdev->mem_start = mmio_start; 1405 netdev->mem_end = mmio_start + mmio_len; 1406 adapter->bd_number = cards_found; 1407 adapter->pci_using_64 = false; 1408 1409 /* setup the private structure */ 1410 err = atl2_sw_init(adapter); 1411 if (err) 1412 goto err_sw_init; 1413 1414 err = -EIO; 1415 1416 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX; 1417 netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 1418 1419 /* Init PHY as early as possible due to power saving issue */ 1420 atl2_phy_init(&adapter->hw); 1421 1422 /* reset the controller to 1423 * put the device in a known good starting state */ 1424 1425 if (atl2_reset_hw(&adapter->hw)) { 1426 err = -EIO; 1427 goto err_reset; 1428 } 1429 1430 /* copy the MAC address out of the EEPROM */ 1431 atl2_read_mac_addr(&adapter->hw); 1432 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); 1433 if (!is_valid_ether_addr(netdev->dev_addr)) { 1434 err = -EIO; 1435 goto err_eeprom; 1436 } 1437 1438 atl2_check_options(adapter); 1439 1440 init_timer(&adapter->watchdog_timer); 1441 adapter->watchdog_timer.function = atl2_watchdog; 1442 adapter->watchdog_timer.data = (unsigned long) adapter; 1443 1444 init_timer(&adapter->phy_config_timer); 1445 adapter->phy_config_timer.function = atl2_phy_config; 1446 adapter->phy_config_timer.data = (unsigned long) adapter; 1447 1448 INIT_WORK(&adapter->reset_task, atl2_reset_task); 1449 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task); 1450 1451 strcpy(netdev->name, "eth%d"); /* ?? */ 1452 err = register_netdev(netdev); 1453 if (err) 1454 goto err_register; 1455 1456 /* assume we have no link for now */ 1457 netif_carrier_off(netdev); 1458 netif_stop_queue(netdev); 1459 1460 cards_found++; 1461 1462 return 0; 1463 1464 err_reset: 1465 err_register: 1466 err_sw_init: 1467 err_eeprom: 1468 iounmap(adapter->hw.hw_addr); 1469 err_ioremap: 1470 free_netdev(netdev); 1471 err_alloc_etherdev: 1472 pci_release_regions(pdev); 1473 err_pci_reg: 1474 err_dma: 1475 pci_disable_device(pdev); 1476 return err; 1477 } 1478 1479 /** 1480 * atl2_remove - Device Removal Routine 1481 * @pdev: PCI device information struct 1482 * 1483 * atl2_remove is called by the PCI subsystem to alert the driver 1484 * that it should release a PCI device. The could be caused by a 1485 * Hot-Plug event, or because the driver is going to be removed from 1486 * memory. 1487 */ 1488 /* FIXME: write the original MAC address back in case it was changed from a 1489 * BIOS-set value, as in atl1 -- CHS */ 1490 static void atl2_remove(struct pci_dev *pdev) 1491 { 1492 struct net_device *netdev = pci_get_drvdata(pdev); 1493 struct atl2_adapter *adapter = netdev_priv(netdev); 1494 1495 /* flush_scheduled work may reschedule our watchdog task, so 1496 * explicitly disable watchdog tasks from being rescheduled */ 1497 set_bit(__ATL2_DOWN, &adapter->flags); 1498 1499 del_timer_sync(&adapter->watchdog_timer); 1500 del_timer_sync(&adapter->phy_config_timer); 1501 cancel_work_sync(&adapter->reset_task); 1502 cancel_work_sync(&adapter->link_chg_task); 1503 1504 unregister_netdev(netdev); 1505 1506 atl2_force_ps(&adapter->hw); 1507 1508 iounmap(adapter->hw.hw_addr); 1509 pci_release_regions(pdev); 1510 1511 free_netdev(netdev); 1512 1513 pci_disable_device(pdev); 1514 } 1515 1516 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state) 1517 { 1518 struct net_device *netdev = pci_get_drvdata(pdev); 1519 struct atl2_adapter *adapter = netdev_priv(netdev); 1520 struct atl2_hw *hw = &adapter->hw; 1521 u16 speed, duplex; 1522 u32 ctrl = 0; 1523 u32 wufc = adapter->wol; 1524 1525 #ifdef CONFIG_PM 1526 int retval = 0; 1527 #endif 1528 1529 netif_device_detach(netdev); 1530 1531 if (netif_running(netdev)) { 1532 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 1533 atl2_down(adapter); 1534 } 1535 1536 #ifdef CONFIG_PM 1537 retval = pci_save_state(pdev); 1538 if (retval) 1539 return retval; 1540 #endif 1541 1542 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1543 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1544 if (ctrl & BMSR_LSTATUS) 1545 wufc &= ~ATLX_WUFC_LNKC; 1546 1547 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) { 1548 u32 ret_val; 1549 /* get current link speed & duplex */ 1550 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1551 if (ret_val) { 1552 printk(KERN_DEBUG 1553 "%s: get speed&duplex error while suspend\n", 1554 atl2_driver_name); 1555 goto wol_dis; 1556 } 1557 1558 ctrl = 0; 1559 1560 /* turn on magic packet wol */ 1561 if (wufc & ATLX_WUFC_MAG) 1562 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); 1563 1564 /* ignore Link Chg event when Link is up */ 1565 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1566 1567 /* Config MAC CTRL Register */ 1568 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1569 if (FULL_DUPLEX == adapter->link_duplex) 1570 ctrl |= MAC_CTRL_DUPLX; 1571 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1572 ctrl |= (((u32)adapter->hw.preamble_len & 1573 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 1574 ctrl |= (((u32)(adapter->hw.retry_buf & 1575 MAC_CTRL_HALF_LEFT_BUF_MASK)) << 1576 MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1577 if (wufc & ATLX_WUFC_MAG) { 1578 /* magic packet maybe Broadcast&multicast&Unicast */ 1579 ctrl |= MAC_CTRL_BC_EN; 1580 } 1581 1582 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); 1583 1584 /* pcie patch */ 1585 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1586 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1587 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1588 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1589 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1590 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1591 1592 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1593 goto suspend_exit; 1594 } 1595 1596 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) { 1597 /* link is down, so only LINK CHG WOL event enable */ 1598 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 1599 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1600 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); 1601 1602 /* pcie patch */ 1603 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1604 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1605 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1606 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1607 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1608 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1609 1610 hw->phy_configured = false; /* re-init PHY when resume */ 1611 1612 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1613 1614 goto suspend_exit; 1615 } 1616 1617 wol_dis: 1618 /* WOL disabled */ 1619 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); 1620 1621 /* pcie patch */ 1622 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1623 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1624 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1625 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1626 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1627 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1628 1629 atl2_force_ps(hw); 1630 hw->phy_configured = false; /* re-init PHY when resume */ 1631 1632 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1633 1634 suspend_exit: 1635 if (netif_running(netdev)) 1636 atl2_free_irq(adapter); 1637 1638 pci_disable_device(pdev); 1639 1640 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1641 1642 return 0; 1643 } 1644 1645 #ifdef CONFIG_PM 1646 static int atl2_resume(struct pci_dev *pdev) 1647 { 1648 struct net_device *netdev = pci_get_drvdata(pdev); 1649 struct atl2_adapter *adapter = netdev_priv(netdev); 1650 u32 err; 1651 1652 pci_set_power_state(pdev, PCI_D0); 1653 pci_restore_state(pdev); 1654 1655 err = pci_enable_device(pdev); 1656 if (err) { 1657 printk(KERN_ERR 1658 "atl2: Cannot enable PCI device from suspend\n"); 1659 return err; 1660 } 1661 1662 pci_set_master(pdev); 1663 1664 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ 1665 1666 pci_enable_wake(pdev, PCI_D3hot, 0); 1667 pci_enable_wake(pdev, PCI_D3cold, 0); 1668 1669 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); 1670 1671 if (netif_running(netdev)) { 1672 err = atl2_request_irq(adapter); 1673 if (err) 1674 return err; 1675 } 1676 1677 atl2_reset_hw(&adapter->hw); 1678 1679 if (netif_running(netdev)) 1680 atl2_up(adapter); 1681 1682 netif_device_attach(netdev); 1683 1684 return 0; 1685 } 1686 #endif 1687 1688 static void atl2_shutdown(struct pci_dev *pdev) 1689 { 1690 atl2_suspend(pdev, PMSG_SUSPEND); 1691 } 1692 1693 static struct pci_driver atl2_driver = { 1694 .name = atl2_driver_name, 1695 .id_table = atl2_pci_tbl, 1696 .probe = atl2_probe, 1697 .remove = atl2_remove, 1698 /* Power Management Hooks */ 1699 .suspend = atl2_suspend, 1700 #ifdef CONFIG_PM 1701 .resume = atl2_resume, 1702 #endif 1703 .shutdown = atl2_shutdown, 1704 }; 1705 1706 /** 1707 * atl2_init_module - Driver Registration Routine 1708 * 1709 * atl2_init_module is the first routine called when the driver is 1710 * loaded. All it does is register with the PCI subsystem. 1711 */ 1712 static int __init atl2_init_module(void) 1713 { 1714 printk(KERN_INFO "%s - version %s\n", atl2_driver_string, 1715 atl2_driver_version); 1716 printk(KERN_INFO "%s\n", atl2_copyright); 1717 return pci_register_driver(&atl2_driver); 1718 } 1719 module_init(atl2_init_module); 1720 1721 /** 1722 * atl2_exit_module - Driver Exit Cleanup Routine 1723 * 1724 * atl2_exit_module is called just before the driver is removed 1725 * from memory. 1726 */ 1727 static void __exit atl2_exit_module(void) 1728 { 1729 pci_unregister_driver(&atl2_driver); 1730 } 1731 module_exit(atl2_exit_module); 1732 1733 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1734 { 1735 struct atl2_adapter *adapter = hw->back; 1736 pci_read_config_word(adapter->pdev, reg, value); 1737 } 1738 1739 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1740 { 1741 struct atl2_adapter *adapter = hw->back; 1742 pci_write_config_word(adapter->pdev, reg, *value); 1743 } 1744 1745 static int atl2_get_settings(struct net_device *netdev, 1746 struct ethtool_cmd *ecmd) 1747 { 1748 struct atl2_adapter *adapter = netdev_priv(netdev); 1749 struct atl2_hw *hw = &adapter->hw; 1750 1751 ecmd->supported = (SUPPORTED_10baseT_Half | 1752 SUPPORTED_10baseT_Full | 1753 SUPPORTED_100baseT_Half | 1754 SUPPORTED_100baseT_Full | 1755 SUPPORTED_Autoneg | 1756 SUPPORTED_TP); 1757 ecmd->advertising = ADVERTISED_TP; 1758 1759 ecmd->advertising |= ADVERTISED_Autoneg; 1760 ecmd->advertising |= hw->autoneg_advertised; 1761 1762 ecmd->port = PORT_TP; 1763 ecmd->phy_address = 0; 1764 ecmd->transceiver = XCVR_INTERNAL; 1765 1766 if (adapter->link_speed != SPEED_0) { 1767 ethtool_cmd_speed_set(ecmd, adapter->link_speed); 1768 if (adapter->link_duplex == FULL_DUPLEX) 1769 ecmd->duplex = DUPLEX_FULL; 1770 else 1771 ecmd->duplex = DUPLEX_HALF; 1772 } else { 1773 ethtool_cmd_speed_set(ecmd, -1); 1774 ecmd->duplex = -1; 1775 } 1776 1777 ecmd->autoneg = AUTONEG_ENABLE; 1778 return 0; 1779 } 1780 1781 static int atl2_set_settings(struct net_device *netdev, 1782 struct ethtool_cmd *ecmd) 1783 { 1784 struct atl2_adapter *adapter = netdev_priv(netdev); 1785 struct atl2_hw *hw = &adapter->hw; 1786 1787 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1788 msleep(1); 1789 1790 if (ecmd->autoneg == AUTONEG_ENABLE) { 1791 #define MY_ADV_MASK (ADVERTISE_10_HALF | \ 1792 ADVERTISE_10_FULL | \ 1793 ADVERTISE_100_HALF| \ 1794 ADVERTISE_100_FULL) 1795 1796 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) { 1797 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; 1798 hw->autoneg_advertised = MY_ADV_MASK; 1799 } else if ((ecmd->advertising & MY_ADV_MASK) == 1800 ADVERTISE_100_FULL) { 1801 hw->MediaType = MEDIA_TYPE_100M_FULL; 1802 hw->autoneg_advertised = ADVERTISE_100_FULL; 1803 } else if ((ecmd->advertising & MY_ADV_MASK) == 1804 ADVERTISE_100_HALF) { 1805 hw->MediaType = MEDIA_TYPE_100M_HALF; 1806 hw->autoneg_advertised = ADVERTISE_100_HALF; 1807 } else if ((ecmd->advertising & MY_ADV_MASK) == 1808 ADVERTISE_10_FULL) { 1809 hw->MediaType = MEDIA_TYPE_10M_FULL; 1810 hw->autoneg_advertised = ADVERTISE_10_FULL; 1811 } else if ((ecmd->advertising & MY_ADV_MASK) == 1812 ADVERTISE_10_HALF) { 1813 hw->MediaType = MEDIA_TYPE_10M_HALF; 1814 hw->autoneg_advertised = ADVERTISE_10_HALF; 1815 } else { 1816 clear_bit(__ATL2_RESETTING, &adapter->flags); 1817 return -EINVAL; 1818 } 1819 ecmd->advertising = hw->autoneg_advertised | 1820 ADVERTISED_TP | ADVERTISED_Autoneg; 1821 } else { 1822 clear_bit(__ATL2_RESETTING, &adapter->flags); 1823 return -EINVAL; 1824 } 1825 1826 /* reset the link */ 1827 if (netif_running(adapter->netdev)) { 1828 atl2_down(adapter); 1829 atl2_up(adapter); 1830 } else 1831 atl2_reset_hw(&adapter->hw); 1832 1833 clear_bit(__ATL2_RESETTING, &adapter->flags); 1834 return 0; 1835 } 1836 1837 static u32 atl2_get_msglevel(struct net_device *netdev) 1838 { 1839 return 0; 1840 } 1841 1842 /* 1843 * It's sane for this to be empty, but we might want to take advantage of this. 1844 */ 1845 static void atl2_set_msglevel(struct net_device *netdev, u32 data) 1846 { 1847 } 1848 1849 static int atl2_get_regs_len(struct net_device *netdev) 1850 { 1851 #define ATL2_REGS_LEN 42 1852 return sizeof(u32) * ATL2_REGS_LEN; 1853 } 1854 1855 static void atl2_get_regs(struct net_device *netdev, 1856 struct ethtool_regs *regs, void *p) 1857 { 1858 struct atl2_adapter *adapter = netdev_priv(netdev); 1859 struct atl2_hw *hw = &adapter->hw; 1860 u32 *regs_buff = p; 1861 u16 phy_data; 1862 1863 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN); 1864 1865 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 1866 1867 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); 1868 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 1869 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); 1870 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); 1871 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); 1872 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); 1873 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); 1874 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); 1875 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); 1876 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); 1877 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); 1878 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); 1879 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); 1880 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); 1881 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); 1882 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 1883 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); 1884 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); 1885 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); 1886 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); 1887 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); 1888 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); 1889 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); 1890 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); 1891 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); 1892 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); 1893 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); 1894 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); 1895 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); 1896 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); 1897 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); 1898 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); 1899 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); 1900 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); 1901 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); 1902 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); 1903 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); 1904 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); 1905 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); 1906 1907 atl2_read_phy_reg(hw, MII_BMCR, &phy_data); 1908 regs_buff[40] = (u32)phy_data; 1909 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1910 regs_buff[41] = (u32)phy_data; 1911 } 1912 1913 static int atl2_get_eeprom_len(struct net_device *netdev) 1914 { 1915 struct atl2_adapter *adapter = netdev_priv(netdev); 1916 1917 if (!atl2_check_eeprom_exist(&adapter->hw)) 1918 return 512; 1919 else 1920 return 0; 1921 } 1922 1923 static int atl2_get_eeprom(struct net_device *netdev, 1924 struct ethtool_eeprom *eeprom, u8 *bytes) 1925 { 1926 struct atl2_adapter *adapter = netdev_priv(netdev); 1927 struct atl2_hw *hw = &adapter->hw; 1928 u32 *eeprom_buff; 1929 int first_dword, last_dword; 1930 int ret_val = 0; 1931 int i; 1932 1933 if (eeprom->len == 0) 1934 return -EINVAL; 1935 1936 if (atl2_check_eeprom_exist(hw)) 1937 return -EINVAL; 1938 1939 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 1940 1941 first_dword = eeprom->offset >> 2; 1942 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1943 1944 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1), 1945 GFP_KERNEL); 1946 if (!eeprom_buff) 1947 return -ENOMEM; 1948 1949 for (i = first_dword; i < last_dword; i++) { 1950 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) { 1951 ret_val = -EIO; 1952 goto free; 1953 } 1954 } 1955 1956 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), 1957 eeprom->len); 1958 free: 1959 kfree(eeprom_buff); 1960 1961 return ret_val; 1962 } 1963 1964 static int atl2_set_eeprom(struct net_device *netdev, 1965 struct ethtool_eeprom *eeprom, u8 *bytes) 1966 { 1967 struct atl2_adapter *adapter = netdev_priv(netdev); 1968 struct atl2_hw *hw = &adapter->hw; 1969 u32 *eeprom_buff; 1970 u32 *ptr; 1971 int max_len, first_dword, last_dword, ret_val = 0; 1972 int i; 1973 1974 if (eeprom->len == 0) 1975 return -EOPNOTSUPP; 1976 1977 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 1978 return -EFAULT; 1979 1980 max_len = 512; 1981 1982 first_dword = eeprom->offset >> 2; 1983 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1984 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 1985 if (!eeprom_buff) 1986 return -ENOMEM; 1987 1988 ptr = eeprom_buff; 1989 1990 if (eeprom->offset & 3) { 1991 /* need read/modify/write of first changed EEPROM word */ 1992 /* only the second byte of the word is being modified */ 1993 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) { 1994 ret_val = -EIO; 1995 goto out; 1996 } 1997 ptr++; 1998 } 1999 if (((eeprom->offset + eeprom->len) & 3)) { 2000 /* 2001 * need read/modify/write of last changed EEPROM word 2002 * only the first byte of the word is being modified 2003 */ 2004 if (!atl2_read_eeprom(hw, last_dword * 4, 2005 &(eeprom_buff[last_dword - first_dword]))) { 2006 ret_val = -EIO; 2007 goto out; 2008 } 2009 } 2010 2011 /* Device's eeprom is always little-endian, word addressable */ 2012 memcpy(ptr, bytes, eeprom->len); 2013 2014 for (i = 0; i < last_dword - first_dword + 1; i++) { 2015 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) { 2016 ret_val = -EIO; 2017 goto out; 2018 } 2019 } 2020 out: 2021 kfree(eeprom_buff); 2022 return ret_val; 2023 } 2024 2025 static void atl2_get_drvinfo(struct net_device *netdev, 2026 struct ethtool_drvinfo *drvinfo) 2027 { 2028 struct atl2_adapter *adapter = netdev_priv(netdev); 2029 2030 strlcpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver)); 2031 strlcpy(drvinfo->version, atl2_driver_version, 2032 sizeof(drvinfo->version)); 2033 strlcpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version)); 2034 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 2035 sizeof(drvinfo->bus_info)); 2036 drvinfo->n_stats = 0; 2037 drvinfo->testinfo_len = 0; 2038 drvinfo->regdump_len = atl2_get_regs_len(netdev); 2039 drvinfo->eedump_len = atl2_get_eeprom_len(netdev); 2040 } 2041 2042 static void atl2_get_wol(struct net_device *netdev, 2043 struct ethtool_wolinfo *wol) 2044 { 2045 struct atl2_adapter *adapter = netdev_priv(netdev); 2046 2047 wol->supported = WAKE_MAGIC; 2048 wol->wolopts = 0; 2049 2050 if (adapter->wol & ATLX_WUFC_EX) 2051 wol->wolopts |= WAKE_UCAST; 2052 if (adapter->wol & ATLX_WUFC_MC) 2053 wol->wolopts |= WAKE_MCAST; 2054 if (adapter->wol & ATLX_WUFC_BC) 2055 wol->wolopts |= WAKE_BCAST; 2056 if (adapter->wol & ATLX_WUFC_MAG) 2057 wol->wolopts |= WAKE_MAGIC; 2058 if (adapter->wol & ATLX_WUFC_LNKC) 2059 wol->wolopts |= WAKE_PHY; 2060 } 2061 2062 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2063 { 2064 struct atl2_adapter *adapter = netdev_priv(netdev); 2065 2066 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2067 return -EOPNOTSUPP; 2068 2069 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)) 2070 return -EOPNOTSUPP; 2071 2072 /* these settings will always override what we currently have */ 2073 adapter->wol = 0; 2074 2075 if (wol->wolopts & WAKE_MAGIC) 2076 adapter->wol |= ATLX_WUFC_MAG; 2077 if (wol->wolopts & WAKE_PHY) 2078 adapter->wol |= ATLX_WUFC_LNKC; 2079 2080 return 0; 2081 } 2082 2083 static int atl2_nway_reset(struct net_device *netdev) 2084 { 2085 struct atl2_adapter *adapter = netdev_priv(netdev); 2086 if (netif_running(netdev)) 2087 atl2_reinit_locked(adapter); 2088 return 0; 2089 } 2090 2091 static const struct ethtool_ops atl2_ethtool_ops = { 2092 .get_settings = atl2_get_settings, 2093 .set_settings = atl2_set_settings, 2094 .get_drvinfo = atl2_get_drvinfo, 2095 .get_regs_len = atl2_get_regs_len, 2096 .get_regs = atl2_get_regs, 2097 .get_wol = atl2_get_wol, 2098 .set_wol = atl2_set_wol, 2099 .get_msglevel = atl2_get_msglevel, 2100 .set_msglevel = atl2_set_msglevel, 2101 .nway_reset = atl2_nway_reset, 2102 .get_link = ethtool_op_get_link, 2103 .get_eeprom_len = atl2_get_eeprom_len, 2104 .get_eeprom = atl2_get_eeprom, 2105 .set_eeprom = atl2_set_eeprom, 2106 }; 2107 2108 static void atl2_set_ethtool_ops(struct net_device *netdev) 2109 { 2110 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops); 2111 } 2112 2113 #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \ 2114 (((a) & 0xff00ff00) >> 8)) 2115 #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16)) 2116 #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8)) 2117 2118 /* 2119 * Reset the transmit and receive units; mask and clear all interrupts. 2120 * 2121 * hw - Struct containing variables accessed by shared code 2122 * return : 0 or idle status (if error) 2123 */ 2124 static s32 atl2_reset_hw(struct atl2_hw *hw) 2125 { 2126 u32 icr; 2127 u16 pci_cfg_cmd_word; 2128 int i; 2129 2130 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ 2131 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2132 if ((pci_cfg_cmd_word & 2133 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) != 2134 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) { 2135 pci_cfg_cmd_word |= 2136 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER); 2137 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2138 } 2139 2140 /* Clear Interrupt mask to stop board from generating 2141 * interrupts & Clear any pending interrupt events 2142 */ 2143 /* FIXME */ 2144 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */ 2145 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */ 2146 2147 /* Issue Soft Reset to the MAC. This will reset the chip's 2148 * transmit, receive, DMA. It will not effect 2149 * the current PCI configuration. The global reset bit is self- 2150 * clearing, and should clear within a microsecond. 2151 */ 2152 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); 2153 wmb(); 2154 msleep(1); /* delay about 1ms */ 2155 2156 /* Wait at least 10ms for All module to be Idle */ 2157 for (i = 0; i < 10; i++) { 2158 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); 2159 if (!icr) 2160 break; 2161 msleep(1); /* delay 1 ms */ 2162 cpu_relax(); 2163 } 2164 2165 if (icr) 2166 return icr; 2167 2168 return 0; 2169 } 2170 2171 #define CUSTOM_SPI_CS_SETUP 2 2172 #define CUSTOM_SPI_CLK_HI 2 2173 #define CUSTOM_SPI_CLK_LO 2 2174 #define CUSTOM_SPI_CS_HOLD 2 2175 #define CUSTOM_SPI_CS_HI 3 2176 2177 static struct atl2_spi_flash_dev flash_table[] = 2178 { 2179 /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */ 2180 {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 }, 2181 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 }, 2182 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 }, 2183 }; 2184 2185 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf) 2186 { 2187 int i; 2188 u32 value; 2189 2190 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); 2191 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); 2192 2193 value = SPI_FLASH_CTRL_WAIT_READY | 2194 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << 2195 SPI_FLASH_CTRL_CS_SETUP_SHIFT | 2196 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << 2197 SPI_FLASH_CTRL_CLK_HI_SHIFT | 2198 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << 2199 SPI_FLASH_CTRL_CLK_LO_SHIFT | 2200 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << 2201 SPI_FLASH_CTRL_CS_HOLD_SHIFT | 2202 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << 2203 SPI_FLASH_CTRL_CS_HI_SHIFT | 2204 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT; 2205 2206 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2207 2208 value |= SPI_FLASH_CTRL_START; 2209 2210 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2211 2212 for (i = 0; i < 10; i++) { 2213 msleep(1); 2214 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2215 if (!(value & SPI_FLASH_CTRL_START)) 2216 break; 2217 } 2218 2219 if (value & SPI_FLASH_CTRL_START) 2220 return false; 2221 2222 *buf = ATL2_READ_REG(hw, REG_SPI_DATA); 2223 2224 return true; 2225 } 2226 2227 /* 2228 * get_permanent_address 2229 * return 0 if get valid mac address, 2230 */ 2231 static int get_permanent_address(struct atl2_hw *hw) 2232 { 2233 u32 Addr[2]; 2234 u32 i, Control; 2235 u16 Register; 2236 u8 EthAddr[ETH_ALEN]; 2237 bool KeyValid; 2238 2239 if (is_valid_ether_addr(hw->perm_mac_addr)) 2240 return 0; 2241 2242 Addr[0] = 0; 2243 Addr[1] = 0; 2244 2245 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ 2246 Register = 0; 2247 KeyValid = false; 2248 2249 /* Read out all EEPROM content */ 2250 i = 0; 2251 while (1) { 2252 if (atl2_read_eeprom(hw, i + 0x100, &Control)) { 2253 if (KeyValid) { 2254 if (Register == REG_MAC_STA_ADDR) 2255 Addr[0] = Control; 2256 else if (Register == 2257 (REG_MAC_STA_ADDR + 4)) 2258 Addr[1] = Control; 2259 KeyValid = false; 2260 } else if ((Control & 0xff) == 0x5A) { 2261 KeyValid = true; 2262 Register = (u16) (Control >> 16); 2263 } else { 2264 /* assume data end while encount an invalid KEYWORD */ 2265 break; 2266 } 2267 } else { 2268 break; /* read error */ 2269 } 2270 i += 4; 2271 } 2272 2273 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2274 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2275 2276 if (is_valid_ether_addr(EthAddr)) { 2277 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2278 return 0; 2279 } 2280 return 1; 2281 } 2282 2283 /* see if SPI flash exists? */ 2284 Addr[0] = 0; 2285 Addr[1] = 0; 2286 Register = 0; 2287 KeyValid = false; 2288 i = 0; 2289 while (1) { 2290 if (atl2_spi_read(hw, i + 0x1f000, &Control)) { 2291 if (KeyValid) { 2292 if (Register == REG_MAC_STA_ADDR) 2293 Addr[0] = Control; 2294 else if (Register == (REG_MAC_STA_ADDR + 4)) 2295 Addr[1] = Control; 2296 KeyValid = false; 2297 } else if ((Control & 0xff) == 0x5A) { 2298 KeyValid = true; 2299 Register = (u16) (Control >> 16); 2300 } else { 2301 break; /* data end */ 2302 } 2303 } else { 2304 break; /* read error */ 2305 } 2306 i += 4; 2307 } 2308 2309 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2310 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]); 2311 if (is_valid_ether_addr(EthAddr)) { 2312 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2313 return 0; 2314 } 2315 /* maybe MAC-address is from BIOS */ 2316 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 2317 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4); 2318 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2319 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2320 2321 if (is_valid_ether_addr(EthAddr)) { 2322 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2323 return 0; 2324 } 2325 2326 return 1; 2327 } 2328 2329 /* 2330 * Reads the adapter's MAC address from the EEPROM 2331 * 2332 * hw - Struct containing variables accessed by shared code 2333 */ 2334 static s32 atl2_read_mac_addr(struct atl2_hw *hw) 2335 { 2336 if (get_permanent_address(hw)) { 2337 /* for test */ 2338 /* FIXME: shouldn't we use eth_random_addr() here? */ 2339 hw->perm_mac_addr[0] = 0x00; 2340 hw->perm_mac_addr[1] = 0x13; 2341 hw->perm_mac_addr[2] = 0x74; 2342 hw->perm_mac_addr[3] = 0x00; 2343 hw->perm_mac_addr[4] = 0x5c; 2344 hw->perm_mac_addr[5] = 0x38; 2345 } 2346 2347 memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN); 2348 2349 return 0; 2350 } 2351 2352 /* 2353 * Hashes an address to determine its location in the multicast table 2354 * 2355 * hw - Struct containing variables accessed by shared code 2356 * mc_addr - the multicast address to hash 2357 * 2358 * atl2_hash_mc_addr 2359 * purpose 2360 * set hash value for a multicast address 2361 * hash calcu processing : 2362 * 1. calcu 32bit CRC for multicast address 2363 * 2. reverse crc with MSB to LSB 2364 */ 2365 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) 2366 { 2367 u32 crc32, value; 2368 int i; 2369 2370 value = 0; 2371 crc32 = ether_crc_le(6, mc_addr); 2372 2373 for (i = 0; i < 32; i++) 2374 value |= (((crc32 >> i) & 1) << (31 - i)); 2375 2376 return value; 2377 } 2378 2379 /* 2380 * Sets the bit in the multicast table corresponding to the hash value. 2381 * 2382 * hw - Struct containing variables accessed by shared code 2383 * hash_value - Multicast address hash value 2384 */ 2385 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value) 2386 { 2387 u32 hash_bit, hash_reg; 2388 u32 mta; 2389 2390 /* The HASH Table is a register array of 2 32-bit registers. 2391 * It is treated like an array of 64 bits. We want to set 2392 * bit BitArray[hash_value]. So we figure out what register 2393 * the bit is in, read it, OR in the new bit, then write 2394 * back the new value. The register is determined by the 2395 * upper 7 bits of the hash value and the bit within that 2396 * register are determined by the lower 5 bits of the value. 2397 */ 2398 hash_reg = (hash_value >> 31) & 0x1; 2399 hash_bit = (hash_value >> 26) & 0x1F; 2400 2401 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); 2402 2403 mta |= (1 << hash_bit); 2404 2405 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); 2406 } 2407 2408 /* 2409 * atl2_init_pcie - init PCIE module 2410 */ 2411 static void atl2_init_pcie(struct atl2_hw *hw) 2412 { 2413 u32 value; 2414 value = LTSSM_TEST_MODE_DEF; 2415 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); 2416 2417 value = PCIE_DLL_TX_CTRL1_DEF; 2418 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); 2419 } 2420 2421 static void atl2_init_flash_opcode(struct atl2_hw *hw) 2422 { 2423 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) 2424 hw->flash_vendor = 0; /* ATMEL */ 2425 2426 /* Init OP table */ 2427 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, 2428 flash_table[hw->flash_vendor].cmdPROGRAM); 2429 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, 2430 flash_table[hw->flash_vendor].cmdSECTOR_ERASE); 2431 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, 2432 flash_table[hw->flash_vendor].cmdCHIP_ERASE); 2433 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, 2434 flash_table[hw->flash_vendor].cmdRDID); 2435 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, 2436 flash_table[hw->flash_vendor].cmdWREN); 2437 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, 2438 flash_table[hw->flash_vendor].cmdRDSR); 2439 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, 2440 flash_table[hw->flash_vendor].cmdWRSR); 2441 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, 2442 flash_table[hw->flash_vendor].cmdREAD); 2443 } 2444 2445 /******************************************************************** 2446 * Performs basic configuration of the adapter. 2447 * 2448 * hw - Struct containing variables accessed by shared code 2449 * Assumes that the controller has previously been reset and is in a 2450 * post-reset uninitialized state. Initializes multicast table, 2451 * and Calls routines to setup link 2452 * Leaves the transmit and receive units disabled and uninitialized. 2453 ********************************************************************/ 2454 static s32 atl2_init_hw(struct atl2_hw *hw) 2455 { 2456 u32 ret_val = 0; 2457 2458 atl2_init_pcie(hw); 2459 2460 /* Zero out the Multicast HASH table */ 2461 /* clear the old settings from the multicast hash table */ 2462 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 2463 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 2464 2465 atl2_init_flash_opcode(hw); 2466 2467 ret_val = atl2_phy_init(hw); 2468 2469 return ret_val; 2470 } 2471 2472 /* 2473 * Detects the current speed and duplex settings of the hardware. 2474 * 2475 * hw - Struct containing variables accessed by shared code 2476 * speed - Speed of the connection 2477 * duplex - Duplex setting of the connection 2478 */ 2479 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, 2480 u16 *duplex) 2481 { 2482 s32 ret_val; 2483 u16 phy_data; 2484 2485 /* Read PHY Specific Status Register (17) */ 2486 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); 2487 if (ret_val) 2488 return ret_val; 2489 2490 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) 2491 return ATLX_ERR_PHY_RES; 2492 2493 switch (phy_data & MII_ATLX_PSSR_SPEED) { 2494 case MII_ATLX_PSSR_100MBS: 2495 *speed = SPEED_100; 2496 break; 2497 case MII_ATLX_PSSR_10MBS: 2498 *speed = SPEED_10; 2499 break; 2500 default: 2501 return ATLX_ERR_PHY_SPEED; 2502 break; 2503 } 2504 2505 if (phy_data & MII_ATLX_PSSR_DPLX) 2506 *duplex = FULL_DUPLEX; 2507 else 2508 *duplex = HALF_DUPLEX; 2509 2510 return 0; 2511 } 2512 2513 /* 2514 * Reads the value from a PHY register 2515 * hw - Struct containing variables accessed by shared code 2516 * reg_addr - address of the PHY register to read 2517 */ 2518 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) 2519 { 2520 u32 val; 2521 int i; 2522 2523 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 2524 MDIO_START | 2525 MDIO_SUP_PREAMBLE | 2526 MDIO_RW | 2527 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2528 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2529 2530 wmb(); 2531 2532 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2533 udelay(2); 2534 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2535 if (!(val & (MDIO_START | MDIO_BUSY))) 2536 break; 2537 wmb(); 2538 } 2539 if (!(val & (MDIO_START | MDIO_BUSY))) { 2540 *phy_data = (u16)val; 2541 return 0; 2542 } 2543 2544 return ATLX_ERR_PHY; 2545 } 2546 2547 /* 2548 * Writes a value to a PHY register 2549 * hw - Struct containing variables accessed by shared code 2550 * reg_addr - address of the PHY register to write 2551 * data - data to write to the PHY 2552 */ 2553 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) 2554 { 2555 int i; 2556 u32 val; 2557 2558 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 2559 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 2560 MDIO_SUP_PREAMBLE | 2561 MDIO_START | 2562 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2563 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2564 2565 wmb(); 2566 2567 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2568 udelay(2); 2569 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2570 if (!(val & (MDIO_START | MDIO_BUSY))) 2571 break; 2572 2573 wmb(); 2574 } 2575 2576 if (!(val & (MDIO_START | MDIO_BUSY))) 2577 return 0; 2578 2579 return ATLX_ERR_PHY; 2580 } 2581 2582 /* 2583 * Configures PHY autoneg and flow control advertisement settings 2584 * 2585 * hw - Struct containing variables accessed by shared code 2586 */ 2587 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) 2588 { 2589 s32 ret_val; 2590 s16 mii_autoneg_adv_reg; 2591 2592 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2593 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 2594 2595 /* Need to parse autoneg_advertised and set up 2596 * the appropriate PHY registers. First we will parse for 2597 * autoneg_advertised software override. Since we can advertise 2598 * a plethora of combinations, we need to check each bit 2599 * individually. 2600 */ 2601 2602 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 2603 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2604 * the 1000Base-T Control Register (Address 9). */ 2605 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 2606 2607 /* Need to parse MediaType and setup the 2608 * appropriate PHY registers. */ 2609 switch (hw->MediaType) { 2610 case MEDIA_TYPE_AUTO_SENSOR: 2611 mii_autoneg_adv_reg |= 2612 (MII_AR_10T_HD_CAPS | 2613 MII_AR_10T_FD_CAPS | 2614 MII_AR_100TX_HD_CAPS| 2615 MII_AR_100TX_FD_CAPS); 2616 hw->autoneg_advertised = 2617 ADVERTISE_10_HALF | 2618 ADVERTISE_10_FULL | 2619 ADVERTISE_100_HALF| 2620 ADVERTISE_100_FULL; 2621 break; 2622 case MEDIA_TYPE_100M_FULL: 2623 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 2624 hw->autoneg_advertised = ADVERTISE_100_FULL; 2625 break; 2626 case MEDIA_TYPE_100M_HALF: 2627 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 2628 hw->autoneg_advertised = ADVERTISE_100_HALF; 2629 break; 2630 case MEDIA_TYPE_10M_FULL: 2631 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 2632 hw->autoneg_advertised = ADVERTISE_10_FULL; 2633 break; 2634 default: 2635 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 2636 hw->autoneg_advertised = ADVERTISE_10_HALF; 2637 break; 2638 } 2639 2640 /* flow control fixed to enable all */ 2641 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 2642 2643 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 2644 2645 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 2646 2647 if (ret_val) 2648 return ret_val; 2649 2650 return 0; 2651 } 2652 2653 /* 2654 * Resets the PHY and make all config validate 2655 * 2656 * hw - Struct containing variables accessed by shared code 2657 * 2658 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) 2659 */ 2660 static s32 atl2_phy_commit(struct atl2_hw *hw) 2661 { 2662 s32 ret_val; 2663 u16 phy_data; 2664 2665 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2666 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); 2667 if (ret_val) { 2668 u32 val; 2669 int i; 2670 /* pcie serdes link may be down ! */ 2671 for (i = 0; i < 25; i++) { 2672 msleep(1); 2673 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2674 if (!(val & (MDIO_START | MDIO_BUSY))) 2675 break; 2676 } 2677 2678 if (0 != (val & (MDIO_START | MDIO_BUSY))) { 2679 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n"); 2680 return ret_val; 2681 } 2682 } 2683 return 0; 2684 } 2685 2686 static s32 atl2_phy_init(struct atl2_hw *hw) 2687 { 2688 s32 ret_val; 2689 u16 phy_val; 2690 2691 if (hw->phy_configured) 2692 return 0; 2693 2694 /* Enable PHY */ 2695 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); 2696 ATL2_WRITE_FLUSH(hw); 2697 msleep(1); 2698 2699 /* check if the PHY is in powersaving mode */ 2700 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2701 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2702 2703 /* 024E / 124E 0r 0274 / 1274 ? */ 2704 if (phy_val & 0x1000) { 2705 phy_val &= ~0x1000; 2706 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); 2707 } 2708 2709 msleep(1); 2710 2711 /*Enable PHY LinkChange Interrupt */ 2712 ret_val = atl2_write_phy_reg(hw, 18, 0xC00); 2713 if (ret_val) 2714 return ret_val; 2715 2716 /* setup AutoNeg parameters */ 2717 ret_val = atl2_phy_setup_autoneg_adv(hw); 2718 if (ret_val) 2719 return ret_val; 2720 2721 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */ 2722 ret_val = atl2_phy_commit(hw); 2723 if (ret_val) 2724 return ret_val; 2725 2726 hw->phy_configured = true; 2727 2728 return ret_val; 2729 } 2730 2731 static void atl2_set_mac_addr(struct atl2_hw *hw) 2732 { 2733 u32 value; 2734 /* 00-0B-6A-F6-00-DC 2735 * 0: 6AF600DC 1: 000B 2736 * low dword */ 2737 value = (((u32)hw->mac_addr[2]) << 24) | 2738 (((u32)hw->mac_addr[3]) << 16) | 2739 (((u32)hw->mac_addr[4]) << 8) | 2740 (((u32)hw->mac_addr[5])); 2741 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); 2742 /* hight dword */ 2743 value = (((u32)hw->mac_addr[0]) << 8) | 2744 (((u32)hw->mac_addr[1])); 2745 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); 2746 } 2747 2748 /* 2749 * check_eeprom_exist 2750 * return 0 if eeprom exist 2751 */ 2752 static int atl2_check_eeprom_exist(struct atl2_hw *hw) 2753 { 2754 u32 value; 2755 2756 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2757 if (value & SPI_FLASH_CTRL_EN_VPD) { 2758 value &= ~SPI_FLASH_CTRL_EN_VPD; 2759 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2760 } 2761 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); 2762 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 2763 } 2764 2765 /* FIXME: This doesn't look right. -- CHS */ 2766 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) 2767 { 2768 return true; 2769 } 2770 2771 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) 2772 { 2773 int i; 2774 u32 Control; 2775 2776 if (Offset & 0x3) 2777 return false; /* address do not align */ 2778 2779 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); 2780 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 2781 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); 2782 2783 for (i = 0; i < 10; i++) { 2784 msleep(2); 2785 Control = ATL2_READ_REG(hw, REG_VPD_CAP); 2786 if (Control & VPD_CAP_VPD_FLAG) 2787 break; 2788 } 2789 2790 if (Control & VPD_CAP_VPD_FLAG) { 2791 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); 2792 return true; 2793 } 2794 return false; /* timeout */ 2795 } 2796 2797 static void atl2_force_ps(struct atl2_hw *hw) 2798 { 2799 u16 phy_val; 2800 2801 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2802 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2803 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); 2804 2805 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); 2806 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); 2807 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); 2808 atl2_write_phy_reg(hw, MII_DBG_DATA, 0); 2809 } 2810 2811 /* This is the only thing that needs to be changed to adjust the 2812 * maximum number of ports that the driver can manage. 2813 */ 2814 #define ATL2_MAX_NIC 4 2815 2816 #define OPTION_UNSET -1 2817 #define OPTION_DISABLED 0 2818 #define OPTION_ENABLED 1 2819 2820 /* All parameters are treated the same, as an integer array of values. 2821 * This macro just reduces the need to repeat the same declaration code 2822 * over and over (plus this helps to avoid typo bugs). 2823 */ 2824 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET} 2825 #ifndef module_param_array 2826 /* Module Parameters are always initialized to -1, so that the driver 2827 * can tell the difference between no user specified value or the 2828 * user asking for the default value. 2829 * The true default values are loaded in when atl2_check_options is called. 2830 * 2831 * This is a GCC extension to ANSI C. 2832 * See the item "Labeled Elements in Initializers" in the section 2833 * "Extensions to the C Language Family" of the GCC documentation. 2834 */ 2835 2836 #define ATL2_PARAM(X, desc) \ 2837 static const int X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \ 2838 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \ 2839 MODULE_PARM_DESC(X, desc); 2840 #else 2841 #define ATL2_PARAM(X, desc) \ 2842 static int X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \ 2843 static unsigned int num_##X; \ 2844 module_param_array_named(X, X, int, &num_##X, 0); \ 2845 MODULE_PARM_DESC(X, desc); 2846 #endif 2847 2848 /* 2849 * Transmit Memory Size 2850 * Valid Range: 64-2048 2851 * Default Value: 128 2852 */ 2853 #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */ 2854 #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */ 2855 #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */ 2856 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory"); 2857 2858 /* 2859 * Receive Memory Block Count 2860 * Valid Range: 16-512 2861 * Default Value: 128 2862 */ 2863 #define ATL2_MIN_RXD_COUNT 16 2864 #define ATL2_MAX_RXD_COUNT 512 2865 #define ATL2_DEFAULT_RXD_COUNT 64 2866 ATL2_PARAM(RxMemBlock, "Number of receive memory block"); 2867 2868 /* 2869 * User Specified MediaType Override 2870 * 2871 * Valid Range: 0-5 2872 * - 0 - auto-negotiate at all supported speeds 2873 * - 1 - only link at 1000Mbps Full Duplex 2874 * - 2 - only link at 100Mbps Full Duplex 2875 * - 3 - only link at 100Mbps Half Duplex 2876 * - 4 - only link at 10Mbps Full Duplex 2877 * - 5 - only link at 10Mbps Half Duplex 2878 * Default Value: 0 2879 */ 2880 ATL2_PARAM(MediaType, "MediaType Select"); 2881 2882 /* 2883 * Interrupt Moderate Timer in units of 2048 ns (~2 us) 2884 * Valid Range: 10-65535 2885 * Default Value: 45000(90ms) 2886 */ 2887 #define INT_MOD_DEFAULT_CNT 100 /* 200us */ 2888 #define INT_MOD_MAX_CNT 65000 2889 #define INT_MOD_MIN_CNT 50 2890 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer"); 2891 2892 /* 2893 * FlashVendor 2894 * Valid Range: 0-2 2895 * 0 - Atmel 2896 * 1 - SST 2897 * 2 - ST 2898 */ 2899 ATL2_PARAM(FlashVendor, "SPI Flash Vendor"); 2900 2901 #define AUTONEG_ADV_DEFAULT 0x2F 2902 #define AUTONEG_ADV_MASK 0x2F 2903 #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL 2904 2905 #define FLASH_VENDOR_DEFAULT 0 2906 #define FLASH_VENDOR_MIN 0 2907 #define FLASH_VENDOR_MAX 2 2908 2909 struct atl2_option { 2910 enum { enable_option, range_option, list_option } type; 2911 char *name; 2912 char *err; 2913 int def; 2914 union { 2915 struct { /* range_option info */ 2916 int min; 2917 int max; 2918 } r; 2919 struct { /* list_option info */ 2920 int nr; 2921 struct atl2_opt_list { int i; char *str; } *p; 2922 } l; 2923 } arg; 2924 }; 2925 2926 static int atl2_validate_option(int *value, struct atl2_option *opt) 2927 { 2928 int i; 2929 struct atl2_opt_list *ent; 2930 2931 if (*value == OPTION_UNSET) { 2932 *value = opt->def; 2933 return 0; 2934 } 2935 2936 switch (opt->type) { 2937 case enable_option: 2938 switch (*value) { 2939 case OPTION_ENABLED: 2940 printk(KERN_INFO "%s Enabled\n", opt->name); 2941 return 0; 2942 break; 2943 case OPTION_DISABLED: 2944 printk(KERN_INFO "%s Disabled\n", opt->name); 2945 return 0; 2946 break; 2947 } 2948 break; 2949 case range_option: 2950 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 2951 printk(KERN_INFO "%s set to %i\n", opt->name, *value); 2952 return 0; 2953 } 2954 break; 2955 case list_option: 2956 for (i = 0; i < opt->arg.l.nr; i++) { 2957 ent = &opt->arg.l.p[i]; 2958 if (*value == ent->i) { 2959 if (ent->str[0] != '\0') 2960 printk(KERN_INFO "%s\n", ent->str); 2961 return 0; 2962 } 2963 } 2964 break; 2965 default: 2966 BUG(); 2967 } 2968 2969 printk(KERN_INFO "Invalid %s specified (%i) %s\n", 2970 opt->name, *value, opt->err); 2971 *value = opt->def; 2972 return -1; 2973 } 2974 2975 /** 2976 * atl2_check_options - Range Checking for Command Line Parameters 2977 * @adapter: board private structure 2978 * 2979 * This routine checks all command line parameters for valid user 2980 * input. If an invalid value is given, or if no user specified 2981 * value exists, a default value is used. The final value is stored 2982 * in a variable in the adapter structure. 2983 */ 2984 static void atl2_check_options(struct atl2_adapter *adapter) 2985 { 2986 int val; 2987 struct atl2_option opt; 2988 int bd = adapter->bd_number; 2989 if (bd >= ATL2_MAX_NIC) { 2990 printk(KERN_NOTICE "Warning: no configuration for board #%i\n", 2991 bd); 2992 printk(KERN_NOTICE "Using defaults for all values\n"); 2993 #ifndef module_param_array 2994 bd = ATL2_MAX_NIC; 2995 #endif 2996 } 2997 2998 /* Bytes of Transmit Memory */ 2999 opt.type = range_option; 3000 opt.name = "Bytes of Transmit Memory"; 3001 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE); 3002 opt.def = ATL2_DEFAULT_TX_MEMSIZE; 3003 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE; 3004 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE; 3005 #ifdef module_param_array 3006 if (num_TxMemSize > bd) { 3007 #endif 3008 val = TxMemSize[bd]; 3009 atl2_validate_option(&val, &opt); 3010 adapter->txd_ring_size = ((u32) val) * 1024; 3011 #ifdef module_param_array 3012 } else 3013 adapter->txd_ring_size = ((u32)opt.def) * 1024; 3014 #endif 3015 /* txs ring size: */ 3016 adapter->txs_ring_size = adapter->txd_ring_size / 128; 3017 if (adapter->txs_ring_size > 160) 3018 adapter->txs_ring_size = 160; 3019 3020 /* Receive Memory Block Count */ 3021 opt.type = range_option; 3022 opt.name = "Number of receive memory block"; 3023 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT); 3024 opt.def = ATL2_DEFAULT_RXD_COUNT; 3025 opt.arg.r.min = ATL2_MIN_RXD_COUNT; 3026 opt.arg.r.max = ATL2_MAX_RXD_COUNT; 3027 #ifdef module_param_array 3028 if (num_RxMemBlock > bd) { 3029 #endif 3030 val = RxMemBlock[bd]; 3031 atl2_validate_option(&val, &opt); 3032 adapter->rxd_ring_size = (u32)val; 3033 /* FIXME */ 3034 /* ((u16)val)&~1; */ /* even number */ 3035 #ifdef module_param_array 3036 } else 3037 adapter->rxd_ring_size = (u32)opt.def; 3038 #endif 3039 /* init RXD Flow control value */ 3040 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7; 3041 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) > 3042 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) : 3043 (adapter->rxd_ring_size / 12); 3044 3045 /* Interrupt Moderate Timer */ 3046 opt.type = range_option; 3047 opt.name = "Interrupt Moderate Timer"; 3048 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT); 3049 opt.def = INT_MOD_DEFAULT_CNT; 3050 opt.arg.r.min = INT_MOD_MIN_CNT; 3051 opt.arg.r.max = INT_MOD_MAX_CNT; 3052 #ifdef module_param_array 3053 if (num_IntModTimer > bd) { 3054 #endif 3055 val = IntModTimer[bd]; 3056 atl2_validate_option(&val, &opt); 3057 adapter->imt = (u16) val; 3058 #ifdef module_param_array 3059 } else 3060 adapter->imt = (u16)(opt.def); 3061 #endif 3062 /* Flash Vendor */ 3063 opt.type = range_option; 3064 opt.name = "SPI Flash Vendor"; 3065 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT); 3066 opt.def = FLASH_VENDOR_DEFAULT; 3067 opt.arg.r.min = FLASH_VENDOR_MIN; 3068 opt.arg.r.max = FLASH_VENDOR_MAX; 3069 #ifdef module_param_array 3070 if (num_FlashVendor > bd) { 3071 #endif 3072 val = FlashVendor[bd]; 3073 atl2_validate_option(&val, &opt); 3074 adapter->hw.flash_vendor = (u8) val; 3075 #ifdef module_param_array 3076 } else 3077 adapter->hw.flash_vendor = (u8)(opt.def); 3078 #endif 3079 /* MediaType */ 3080 opt.type = range_option; 3081 opt.name = "Speed/Duplex Selection"; 3082 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR); 3083 opt.def = MEDIA_TYPE_AUTO_SENSOR; 3084 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR; 3085 opt.arg.r.max = MEDIA_TYPE_10M_HALF; 3086 #ifdef module_param_array 3087 if (num_MediaType > bd) { 3088 #endif 3089 val = MediaType[bd]; 3090 atl2_validate_option(&val, &opt); 3091 adapter->hw.MediaType = (u16) val; 3092 #ifdef module_param_array 3093 } else 3094 adapter->hw.MediaType = (u16)(opt.def); 3095 #endif 3096 } 3097