1 /* 2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved. 3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com> 4 * 5 * Derived from Intel e1000 driver 6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the Free 10 * Software Foundation; either version 2 of the License, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program; if not, write to the Free Software Foundation, Inc., 59 20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 21 */ 22 23 #include <linux/atomic.h> 24 #include <linux/crc32.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/hardirq.h> 29 #include <linux/if_vlan.h> 30 #include <linux/in.h> 31 #include <linux/interrupt.h> 32 #include <linux/ip.h> 33 #include <linux/irqflags.h> 34 #include <linux/irqreturn.h> 35 #include <linux/mii.h> 36 #include <linux/net.h> 37 #include <linux/netdevice.h> 38 #include <linux/pci.h> 39 #include <linux/pci_ids.h> 40 #include <linux/pm.h> 41 #include <linux/skbuff.h> 42 #include <linux/slab.h> 43 #include <linux/spinlock.h> 44 #include <linux/string.h> 45 #include <linux/tcp.h> 46 #include <linux/timer.h> 47 #include <linux/types.h> 48 #include <linux/workqueue.h> 49 50 #include "atl2.h" 51 52 #define ATL2_DRV_VERSION "2.2.3" 53 54 static const char atl2_driver_name[] = "atl2"; 55 static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver"; 56 static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation."; 57 static const char atl2_driver_version[] = ATL2_DRV_VERSION; 58 59 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>"); 60 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver"); 61 MODULE_LICENSE("GPL"); 62 MODULE_VERSION(ATL2_DRV_VERSION); 63 64 /* 65 * atl2_pci_tbl - PCI Device ID Table 66 */ 67 static DEFINE_PCI_DEVICE_TABLE(atl2_pci_tbl) = { 68 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)}, 69 /* required last entry */ 70 {0,} 71 }; 72 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl); 73 74 static void atl2_set_ethtool_ops(struct net_device *netdev); 75 76 static void atl2_check_options(struct atl2_adapter *adapter); 77 78 /** 79 * atl2_sw_init - Initialize general software structures (struct atl2_adapter) 80 * @adapter: board private structure to initialize 81 * 82 * atl2_sw_init initializes the Adapter private data structure. 83 * Fields are initialized based on PCI device information and 84 * OS network device settings (MTU size). 85 */ 86 static int atl2_sw_init(struct atl2_adapter *adapter) 87 { 88 struct atl2_hw *hw = &adapter->hw; 89 struct pci_dev *pdev = adapter->pdev; 90 91 /* PCI config space info */ 92 hw->vendor_id = pdev->vendor; 93 hw->device_id = pdev->device; 94 hw->subsystem_vendor_id = pdev->subsystem_vendor; 95 hw->subsystem_id = pdev->subsystem_device; 96 hw->revision_id = pdev->revision; 97 98 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 99 100 adapter->wol = 0; 101 adapter->ict = 50000; /* ~100ms */ 102 adapter->link_speed = SPEED_0; /* hardware init */ 103 adapter->link_duplex = FULL_DUPLEX; 104 105 hw->phy_configured = false; 106 hw->preamble_len = 7; 107 hw->ipgt = 0x60; 108 hw->min_ifg = 0x50; 109 hw->ipgr1 = 0x40; 110 hw->ipgr2 = 0x60; 111 hw->retry_buf = 2; 112 hw->max_retry = 0xf; 113 hw->lcol = 0x37; 114 hw->jam_ipg = 7; 115 hw->fc_rxd_hi = 0; 116 hw->fc_rxd_lo = 0; 117 hw->max_frame_size = adapter->netdev->mtu; 118 119 spin_lock_init(&adapter->stats_lock); 120 121 set_bit(__ATL2_DOWN, &adapter->flags); 122 123 return 0; 124 } 125 126 /** 127 * atl2_set_multi - Multicast and Promiscuous mode set 128 * @netdev: network interface device structure 129 * 130 * The set_multi entry point is called whenever the multicast address 131 * list or the network interface flags are updated. This routine is 132 * responsible for configuring the hardware for proper multicast, 133 * promiscuous mode, and all-multi behavior. 134 */ 135 static void atl2_set_multi(struct net_device *netdev) 136 { 137 struct atl2_adapter *adapter = netdev_priv(netdev); 138 struct atl2_hw *hw = &adapter->hw; 139 struct netdev_hw_addr *ha; 140 u32 rctl; 141 u32 hash_value; 142 143 /* Check for Promiscuous and All Multicast modes */ 144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); 145 146 if (netdev->flags & IFF_PROMISC) { 147 rctl |= MAC_CTRL_PROMIS_EN; 148 } else if (netdev->flags & IFF_ALLMULTI) { 149 rctl |= MAC_CTRL_MC_ALL_EN; 150 rctl &= ~MAC_CTRL_PROMIS_EN; 151 } else 152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); 153 154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); 155 156 /* clear the old settings from the multicast hash table */ 157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 159 160 /* comoute mc addresses' hash value ,and put it into hash table */ 161 netdev_for_each_mc_addr(ha, netdev) { 162 hash_value = atl2_hash_mc_addr(hw, ha->addr); 163 atl2_hash_set(hw, hash_value); 164 } 165 } 166 167 static void init_ring_ptrs(struct atl2_adapter *adapter) 168 { 169 /* Read / Write Ptr Initialize: */ 170 adapter->txd_write_ptr = 0; 171 atomic_set(&adapter->txd_read_ptr, 0); 172 173 adapter->rxd_read_ptr = 0; 174 adapter->rxd_write_ptr = 0; 175 176 atomic_set(&adapter->txs_write_ptr, 0); 177 adapter->txs_next_clear = 0; 178 } 179 180 /** 181 * atl2_configure - Configure Transmit&Receive Unit after Reset 182 * @adapter: board private structure 183 * 184 * Configure the Tx /Rx unit of the MAC after a reset. 185 */ 186 static int atl2_configure(struct atl2_adapter *adapter) 187 { 188 struct atl2_hw *hw = &adapter->hw; 189 u32 value; 190 191 /* clear interrupt status */ 192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); 193 194 /* set MAC Address */ 195 value = (((u32)hw->mac_addr[2]) << 24) | 196 (((u32)hw->mac_addr[3]) << 16) | 197 (((u32)hw->mac_addr[4]) << 8) | 198 (((u32)hw->mac_addr[5])); 199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); 200 value = (((u32)hw->mac_addr[0]) << 8) | 201 (((u32)hw->mac_addr[1])); 202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); 203 204 /* HI base address */ 205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32)); 207 208 /* LO base address */ 209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, 210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL)); 211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, 212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL)); 213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, 214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL)); 215 216 /* element count */ 217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); 218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); 219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); 220 221 /* config Internal SRAM */ 222 /* 223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); 224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); 225 */ 226 227 /* config IPG/IFG */ 228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << 229 MAC_IPG_IFG_IPGT_SHIFT) | 230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << 231 MAC_IPG_IFG_MIFG_SHIFT) | 232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << 233 MAC_IPG_IFG_IPGR1_SHIFT)| 234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << 235 MAC_IPG_IFG_IPGR2_SHIFT); 236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); 237 238 /* config Half-Duplex Control */ 239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | 240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << 241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | 242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | 243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | 244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << 245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); 246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); 247 248 /* set Interrupt Moderator Timer */ 249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); 250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); 251 252 /* set Interrupt Clear Timer */ 253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); 254 255 /* set MTU */ 256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + 257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE); 258 259 /* 1590 */ 260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); 261 262 /* flow control */ 263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); 264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); 265 266 /* Init mailbox */ 267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); 268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); 269 270 /* enable DMA read/write */ 271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); 272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); 273 274 value = ATL2_READ_REG(&adapter->hw, REG_ISR); 275 if ((value & ISR_PHY_LINKDOWN) != 0) 276 value = 1; /* config failed */ 277 else 278 value = 0; 279 280 /* clear all interrupt status */ 281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); 282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 283 return value; 284 } 285 286 /** 287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources 288 * @adapter: board private structure 289 * 290 * Return 0 on success, negative on failure 291 */ 292 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter) 293 { 294 struct pci_dev *pdev = adapter->pdev; 295 int size; 296 u8 offset = 0; 297 298 /* real ring DMA buffer */ 299 adapter->ring_size = size = 300 adapter->txd_ring_size * 1 + 7 + /* dword align */ 301 adapter->txs_ring_size * 4 + 7 + /* dword align */ 302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */ 303 304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size, 305 &adapter->ring_dma); 306 if (!adapter->ring_vir_addr) 307 return -ENOMEM; 308 memset(adapter->ring_vir_addr, 0, adapter->ring_size); 309 310 /* Init TXD Ring */ 311 adapter->txd_dma = adapter->ring_dma ; 312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0; 313 adapter->txd_dma += offset; 314 adapter->txd_ring = adapter->ring_vir_addr + offset; 315 316 /* Init TXS Ring */ 317 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size; 318 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0; 319 adapter->txs_dma += offset; 320 adapter->txs_ring = (struct tx_pkt_status *) 321 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset)); 322 323 /* Init RXD Ring */ 324 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4; 325 offset = (adapter->rxd_dma & 127) ? 326 (128 - (adapter->rxd_dma & 127)) : 0; 327 if (offset > 7) 328 offset -= 8; 329 else 330 offset += (128 - 8); 331 332 adapter->rxd_dma += offset; 333 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) + 334 (adapter->txs_ring_size * 4 + offset)); 335 336 /* 337 * Read / Write Ptr Initialize: 338 * init_ring_ptrs(adapter); 339 */ 340 return 0; 341 } 342 343 /** 344 * atl2_irq_enable - Enable default interrupt generation settings 345 * @adapter: board private structure 346 */ 347 static inline void atl2_irq_enable(struct atl2_adapter *adapter) 348 { 349 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); 350 ATL2_WRITE_FLUSH(&adapter->hw); 351 } 352 353 /** 354 * atl2_irq_disable - Mask off interrupt generation on the NIC 355 * @adapter: board private structure 356 */ 357 static inline void atl2_irq_disable(struct atl2_adapter *adapter) 358 { 359 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); 360 ATL2_WRITE_FLUSH(&adapter->hw); 361 synchronize_irq(adapter->pdev->irq); 362 } 363 364 static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl) 365 { 366 if (features & NETIF_F_HW_VLAN_RX) { 367 /* enable VLAN tag insert/strip */ 368 *ctrl |= MAC_CTRL_RMV_VLAN; 369 } else { 370 /* disable VLAN tag insert/strip */ 371 *ctrl &= ~MAC_CTRL_RMV_VLAN; 372 } 373 } 374 375 static void atl2_vlan_mode(struct net_device *netdev, 376 netdev_features_t features) 377 { 378 struct atl2_adapter *adapter = netdev_priv(netdev); 379 u32 ctrl; 380 381 atl2_irq_disable(adapter); 382 383 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); 384 __atl2_vlan_mode(features, &ctrl); 385 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); 386 387 atl2_irq_enable(adapter); 388 } 389 390 static void atl2_restore_vlan(struct atl2_adapter *adapter) 391 { 392 atl2_vlan_mode(adapter->netdev, adapter->netdev->features); 393 } 394 395 static netdev_features_t atl2_fix_features(struct net_device *netdev, 396 netdev_features_t features) 397 { 398 /* 399 * Since there is no support for separate rx/tx vlan accel 400 * enable/disable make sure tx flag is always in same state as rx. 401 */ 402 if (features & NETIF_F_HW_VLAN_RX) 403 features |= NETIF_F_HW_VLAN_TX; 404 else 405 features &= ~NETIF_F_HW_VLAN_TX; 406 407 return features; 408 } 409 410 static int atl2_set_features(struct net_device *netdev, 411 netdev_features_t features) 412 { 413 netdev_features_t changed = netdev->features ^ features; 414 415 if (changed & NETIF_F_HW_VLAN_RX) 416 atl2_vlan_mode(netdev, features); 417 418 return 0; 419 } 420 421 static void atl2_intr_rx(struct atl2_adapter *adapter) 422 { 423 struct net_device *netdev = adapter->netdev; 424 struct rx_desc *rxd; 425 struct sk_buff *skb; 426 427 do { 428 rxd = adapter->rxd_ring+adapter->rxd_write_ptr; 429 if (!rxd->status.update) 430 break; /* end of tx */ 431 432 /* clear this flag at once */ 433 rxd->status.update = 0; 434 435 if (rxd->status.ok && rxd->status.pkt_size >= 60) { 436 int rx_size = (int)(rxd->status.pkt_size - 4); 437 /* alloc new buffer */ 438 skb = netdev_alloc_skb_ip_align(netdev, rx_size); 439 if (NULL == skb) { 440 printk(KERN_WARNING 441 "%s: Mem squeeze, deferring packet.\n", 442 netdev->name); 443 /* 444 * Check that some rx space is free. If not, 445 * free one and mark stats->rx_dropped++. 446 */ 447 netdev->stats.rx_dropped++; 448 break; 449 } 450 memcpy(skb->data, rxd->packet, rx_size); 451 skb_put(skb, rx_size); 452 skb->protocol = eth_type_trans(skb, netdev); 453 if (rxd->status.vlan) { 454 u16 vlan_tag = (rxd->status.vtag>>4) | 455 ((rxd->status.vtag&7) << 13) | 456 ((rxd->status.vtag&8) << 9); 457 458 __vlan_hwaccel_put_tag(skb, vlan_tag); 459 } 460 netif_rx(skb); 461 netdev->stats.rx_bytes += rx_size; 462 netdev->stats.rx_packets++; 463 } else { 464 netdev->stats.rx_errors++; 465 466 if (rxd->status.ok && rxd->status.pkt_size <= 60) 467 netdev->stats.rx_length_errors++; 468 if (rxd->status.mcast) 469 netdev->stats.multicast++; 470 if (rxd->status.crc) 471 netdev->stats.rx_crc_errors++; 472 if (rxd->status.align) 473 netdev->stats.rx_frame_errors++; 474 } 475 476 /* advance write ptr */ 477 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size) 478 adapter->rxd_write_ptr = 0; 479 } while (1); 480 481 /* update mailbox? */ 482 adapter->rxd_read_ptr = adapter->rxd_write_ptr; 483 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); 484 } 485 486 static void atl2_intr_tx(struct atl2_adapter *adapter) 487 { 488 struct net_device *netdev = adapter->netdev; 489 u32 txd_read_ptr; 490 u32 txs_write_ptr; 491 struct tx_pkt_status *txs; 492 struct tx_pkt_header *txph; 493 int free_hole = 0; 494 495 do { 496 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 497 txs = adapter->txs_ring + txs_write_ptr; 498 if (!txs->update) 499 break; /* tx stop here */ 500 501 free_hole = 1; 502 txs->update = 0; 503 504 if (++txs_write_ptr == adapter->txs_ring_size) 505 txs_write_ptr = 0; 506 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr); 507 508 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr); 509 txph = (struct tx_pkt_header *) 510 (((u8 *)adapter->txd_ring) + txd_read_ptr); 511 512 if (txph->pkt_size != txs->pkt_size) { 513 struct tx_pkt_status *old_txs = txs; 514 printk(KERN_WARNING 515 "%s: txs packet size not consistent with txd" 516 " txd_:0x%08x, txs_:0x%08x!\n", 517 adapter->netdev->name, 518 *(u32 *)txph, *(u32 *)txs); 519 printk(KERN_WARNING 520 "txd read ptr: 0x%x\n", 521 txd_read_ptr); 522 txs = adapter->txs_ring + txs_write_ptr; 523 printk(KERN_WARNING 524 "txs-behind:0x%08x\n", 525 *(u32 *)txs); 526 if (txs_write_ptr < 2) { 527 txs = adapter->txs_ring + 528 (adapter->txs_ring_size + 529 txs_write_ptr - 2); 530 } else { 531 txs = adapter->txs_ring + (txs_write_ptr - 2); 532 } 533 printk(KERN_WARNING 534 "txs-before:0x%08x\n", 535 *(u32 *)txs); 536 txs = old_txs; 537 } 538 539 /* 4for TPH */ 540 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3); 541 if (txd_read_ptr >= adapter->txd_ring_size) 542 txd_read_ptr -= adapter->txd_ring_size; 543 544 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr); 545 546 /* tx statistics: */ 547 if (txs->ok) { 548 netdev->stats.tx_bytes += txs->pkt_size; 549 netdev->stats.tx_packets++; 550 } 551 else 552 netdev->stats.tx_errors++; 553 554 if (txs->defer) 555 netdev->stats.collisions++; 556 if (txs->abort_col) 557 netdev->stats.tx_aborted_errors++; 558 if (txs->late_col) 559 netdev->stats.tx_window_errors++; 560 if (txs->underun) 561 netdev->stats.tx_fifo_errors++; 562 } while (1); 563 564 if (free_hole) { 565 if (netif_queue_stopped(adapter->netdev) && 566 netif_carrier_ok(adapter->netdev)) 567 netif_wake_queue(adapter->netdev); 568 } 569 } 570 571 static void atl2_check_for_link(struct atl2_adapter *adapter) 572 { 573 struct net_device *netdev = adapter->netdev; 574 u16 phy_data = 0; 575 576 spin_lock(&adapter->stats_lock); 577 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 578 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 579 spin_unlock(&adapter->stats_lock); 580 581 /* notify upper layer link down ASAP */ 582 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */ 583 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 584 printk(KERN_INFO "%s: %s NIC Link is Down\n", 585 atl2_driver_name, netdev->name); 586 adapter->link_speed = SPEED_0; 587 netif_carrier_off(netdev); 588 netif_stop_queue(netdev); 589 } 590 } 591 schedule_work(&adapter->link_chg_task); 592 } 593 594 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter) 595 { 596 u16 phy_data; 597 spin_lock(&adapter->stats_lock); 598 atl2_read_phy_reg(&adapter->hw, 19, &phy_data); 599 spin_unlock(&adapter->stats_lock); 600 } 601 602 /** 603 * atl2_intr - Interrupt Handler 604 * @irq: interrupt number 605 * @data: pointer to a network interface device structure 606 */ 607 static irqreturn_t atl2_intr(int irq, void *data) 608 { 609 struct atl2_adapter *adapter = netdev_priv(data); 610 struct atl2_hw *hw = &adapter->hw; 611 u32 status; 612 613 status = ATL2_READ_REG(hw, REG_ISR); 614 if (0 == status) 615 return IRQ_NONE; 616 617 /* link event */ 618 if (status & ISR_PHY) 619 atl2_clear_phy_int(adapter); 620 621 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 622 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); 623 624 /* check if PCIE PHY Link down */ 625 if (status & ISR_PHY_LINKDOWN) { 626 if (netif_running(adapter->netdev)) { /* reset MAC */ 627 ATL2_WRITE_REG(hw, REG_ISR, 0); 628 ATL2_WRITE_REG(hw, REG_IMR, 0); 629 ATL2_WRITE_FLUSH(hw); 630 schedule_work(&adapter->reset_task); 631 return IRQ_HANDLED; 632 } 633 } 634 635 /* check if DMA read/write error? */ 636 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 637 ATL2_WRITE_REG(hw, REG_ISR, 0); 638 ATL2_WRITE_REG(hw, REG_IMR, 0); 639 ATL2_WRITE_FLUSH(hw); 640 schedule_work(&adapter->reset_task); 641 return IRQ_HANDLED; 642 } 643 644 /* link event */ 645 if (status & (ISR_PHY | ISR_MANUAL)) { 646 adapter->netdev->stats.tx_carrier_errors++; 647 atl2_check_for_link(adapter); 648 } 649 650 /* transmit event */ 651 if (status & ISR_TX_EVENT) 652 atl2_intr_tx(adapter); 653 654 /* rx exception */ 655 if (status & ISR_RX_EVENT) 656 atl2_intr_rx(adapter); 657 658 /* re-enable Interrupt */ 659 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 660 return IRQ_HANDLED; 661 } 662 663 static int atl2_request_irq(struct atl2_adapter *adapter) 664 { 665 struct net_device *netdev = adapter->netdev; 666 int flags, err = 0; 667 668 flags = IRQF_SHARED; 669 adapter->have_msi = true; 670 err = pci_enable_msi(adapter->pdev); 671 if (err) 672 adapter->have_msi = false; 673 674 if (adapter->have_msi) 675 flags &= ~IRQF_SHARED; 676 677 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name, 678 netdev); 679 } 680 681 /** 682 * atl2_free_ring_resources - Free Tx / RX descriptor Resources 683 * @adapter: board private structure 684 * 685 * Free all transmit software resources 686 */ 687 static void atl2_free_ring_resources(struct atl2_adapter *adapter) 688 { 689 struct pci_dev *pdev = adapter->pdev; 690 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, 691 adapter->ring_dma); 692 } 693 694 /** 695 * atl2_open - Called when a network interface is made active 696 * @netdev: network interface device structure 697 * 698 * Returns 0 on success, negative value on failure 699 * 700 * The open entry point is called when a network interface is made 701 * active by the system (IFF_UP). At this point all resources needed 702 * for transmit and receive operations are allocated, the interrupt 703 * handler is registered with the OS, the watchdog timer is started, 704 * and the stack is notified that the interface is ready. 705 */ 706 static int atl2_open(struct net_device *netdev) 707 { 708 struct atl2_adapter *adapter = netdev_priv(netdev); 709 int err; 710 u32 val; 711 712 /* disallow open during test */ 713 if (test_bit(__ATL2_TESTING, &adapter->flags)) 714 return -EBUSY; 715 716 /* allocate transmit descriptors */ 717 err = atl2_setup_ring_resources(adapter); 718 if (err) 719 return err; 720 721 err = atl2_init_hw(&adapter->hw); 722 if (err) { 723 err = -EIO; 724 goto err_init_hw; 725 } 726 727 /* hardware has been reset, we need to reload some things */ 728 atl2_set_multi(netdev); 729 init_ring_ptrs(adapter); 730 731 atl2_restore_vlan(adapter); 732 733 if (atl2_configure(adapter)) { 734 err = -EIO; 735 goto err_config; 736 } 737 738 err = atl2_request_irq(adapter); 739 if (err) 740 goto err_req_irq; 741 742 clear_bit(__ATL2_DOWN, &adapter->flags); 743 744 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ)); 745 746 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 747 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, 748 val | MASTER_CTRL_MANUAL_INT); 749 750 atl2_irq_enable(adapter); 751 752 return 0; 753 754 err_init_hw: 755 err_req_irq: 756 err_config: 757 atl2_free_ring_resources(adapter); 758 atl2_reset_hw(&adapter->hw); 759 760 return err; 761 } 762 763 static void atl2_down(struct atl2_adapter *adapter) 764 { 765 struct net_device *netdev = adapter->netdev; 766 767 /* signal that we're down so the interrupt handler does not 768 * reschedule our watchdog timer */ 769 set_bit(__ATL2_DOWN, &adapter->flags); 770 771 netif_tx_disable(netdev); 772 773 /* reset MAC to disable all RX/TX */ 774 atl2_reset_hw(&adapter->hw); 775 msleep(1); 776 777 atl2_irq_disable(adapter); 778 779 del_timer_sync(&adapter->watchdog_timer); 780 del_timer_sync(&adapter->phy_config_timer); 781 clear_bit(0, &adapter->cfg_phy); 782 783 netif_carrier_off(netdev); 784 adapter->link_speed = SPEED_0; 785 adapter->link_duplex = -1; 786 } 787 788 static void atl2_free_irq(struct atl2_adapter *adapter) 789 { 790 struct net_device *netdev = adapter->netdev; 791 792 free_irq(adapter->pdev->irq, netdev); 793 794 #ifdef CONFIG_PCI_MSI 795 if (adapter->have_msi) 796 pci_disable_msi(adapter->pdev); 797 #endif 798 } 799 800 /** 801 * atl2_close - Disables a network interface 802 * @netdev: network interface device structure 803 * 804 * Returns 0, this is not allowed to fail 805 * 806 * The close entry point is called when an interface is de-activated 807 * by the OS. The hardware is still under the drivers control, but 808 * needs to be disabled. A global MAC reset is issued to stop the 809 * hardware, and all transmit and receive resources are freed. 810 */ 811 static int atl2_close(struct net_device *netdev) 812 { 813 struct atl2_adapter *adapter = netdev_priv(netdev); 814 815 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 816 817 atl2_down(adapter); 818 atl2_free_irq(adapter); 819 atl2_free_ring_resources(adapter); 820 821 return 0; 822 } 823 824 static inline int TxsFreeUnit(struct atl2_adapter *adapter) 825 { 826 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 827 828 return (adapter->txs_next_clear >= txs_write_ptr) ? 829 (int) (adapter->txs_ring_size - adapter->txs_next_clear + 830 txs_write_ptr - 1) : 831 (int) (txs_write_ptr - adapter->txs_next_clear - 1); 832 } 833 834 static inline int TxdFreeBytes(struct atl2_adapter *adapter) 835 { 836 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr); 837 838 return (adapter->txd_write_ptr >= txd_read_ptr) ? 839 (int) (adapter->txd_ring_size - adapter->txd_write_ptr + 840 txd_read_ptr - 1) : 841 (int) (txd_read_ptr - adapter->txd_write_ptr - 1); 842 } 843 844 static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb, 845 struct net_device *netdev) 846 { 847 struct atl2_adapter *adapter = netdev_priv(netdev); 848 struct tx_pkt_header *txph; 849 u32 offset, copy_len; 850 int txs_unused; 851 int txbuf_unused; 852 853 if (test_bit(__ATL2_DOWN, &adapter->flags)) { 854 dev_kfree_skb_any(skb); 855 return NETDEV_TX_OK; 856 } 857 858 if (unlikely(skb->len <= 0)) { 859 dev_kfree_skb_any(skb); 860 return NETDEV_TX_OK; 861 } 862 863 txs_unused = TxsFreeUnit(adapter); 864 txbuf_unused = TxdFreeBytes(adapter); 865 866 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused || 867 txs_unused < 1) { 868 /* not enough resources */ 869 netif_stop_queue(netdev); 870 return NETDEV_TX_BUSY; 871 } 872 873 offset = adapter->txd_write_ptr; 874 875 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset); 876 877 *(u32 *)txph = 0; 878 txph->pkt_size = skb->len; 879 880 offset += 4; 881 if (offset >= adapter->txd_ring_size) 882 offset -= adapter->txd_ring_size; 883 copy_len = adapter->txd_ring_size - offset; 884 if (copy_len >= skb->len) { 885 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len); 886 offset += ((u32)(skb->len + 3) & ~3); 887 } else { 888 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len); 889 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len, 890 skb->len-copy_len); 891 offset = ((u32)(skb->len-copy_len + 3) & ~3); 892 } 893 #ifdef NETIF_F_HW_VLAN_TX 894 if (vlan_tx_tag_present(skb)) { 895 u16 vlan_tag = vlan_tx_tag_get(skb); 896 vlan_tag = (vlan_tag << 4) | 897 (vlan_tag >> 13) | 898 ((vlan_tag >> 9) & 0x8); 899 txph->ins_vlan = 1; 900 txph->vlan = vlan_tag; 901 } 902 #endif 903 if (offset >= adapter->txd_ring_size) 904 offset -= adapter->txd_ring_size; 905 adapter->txd_write_ptr = offset; 906 907 /* clear txs before send */ 908 adapter->txs_ring[adapter->txs_next_clear].update = 0; 909 if (++adapter->txs_next_clear == adapter->txs_ring_size) 910 adapter->txs_next_clear = 0; 911 912 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, 913 (adapter->txd_write_ptr >> 2)); 914 915 mmiowb(); 916 dev_kfree_skb_any(skb); 917 return NETDEV_TX_OK; 918 } 919 920 /** 921 * atl2_change_mtu - Change the Maximum Transfer Unit 922 * @netdev: network interface device structure 923 * @new_mtu: new value for maximum frame size 924 * 925 * Returns 0 on success, negative on failure 926 */ 927 static int atl2_change_mtu(struct net_device *netdev, int new_mtu) 928 { 929 struct atl2_adapter *adapter = netdev_priv(netdev); 930 struct atl2_hw *hw = &adapter->hw; 931 932 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE))) 933 return -EINVAL; 934 935 /* set MTU */ 936 if (hw->max_frame_size != new_mtu) { 937 netdev->mtu = new_mtu; 938 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE + 939 VLAN_SIZE + ETHERNET_FCS_SIZE); 940 } 941 942 return 0; 943 } 944 945 /** 946 * atl2_set_mac - Change the Ethernet Address of the NIC 947 * @netdev: network interface device structure 948 * @p: pointer to an address structure 949 * 950 * Returns 0 on success, negative on failure 951 */ 952 static int atl2_set_mac(struct net_device *netdev, void *p) 953 { 954 struct atl2_adapter *adapter = netdev_priv(netdev); 955 struct sockaddr *addr = p; 956 957 if (!is_valid_ether_addr(addr->sa_data)) 958 return -EADDRNOTAVAIL; 959 960 if (netif_running(netdev)) 961 return -EBUSY; 962 963 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 964 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); 965 966 atl2_set_mac_addr(&adapter->hw); 967 968 return 0; 969 } 970 971 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 972 { 973 struct atl2_adapter *adapter = netdev_priv(netdev); 974 struct mii_ioctl_data *data = if_mii(ifr); 975 unsigned long flags; 976 977 switch (cmd) { 978 case SIOCGMIIPHY: 979 data->phy_id = 0; 980 break; 981 case SIOCGMIIREG: 982 spin_lock_irqsave(&adapter->stats_lock, flags); 983 if (atl2_read_phy_reg(&adapter->hw, 984 data->reg_num & 0x1F, &data->val_out)) { 985 spin_unlock_irqrestore(&adapter->stats_lock, flags); 986 return -EIO; 987 } 988 spin_unlock_irqrestore(&adapter->stats_lock, flags); 989 break; 990 case SIOCSMIIREG: 991 if (data->reg_num & ~(0x1F)) 992 return -EFAULT; 993 spin_lock_irqsave(&adapter->stats_lock, flags); 994 if (atl2_write_phy_reg(&adapter->hw, data->reg_num, 995 data->val_in)) { 996 spin_unlock_irqrestore(&adapter->stats_lock, flags); 997 return -EIO; 998 } 999 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1000 break; 1001 default: 1002 return -EOPNOTSUPP; 1003 } 1004 return 0; 1005 } 1006 1007 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1008 { 1009 switch (cmd) { 1010 case SIOCGMIIPHY: 1011 case SIOCGMIIREG: 1012 case SIOCSMIIREG: 1013 return atl2_mii_ioctl(netdev, ifr, cmd); 1014 #ifdef ETHTOOL_OPS_COMPAT 1015 case SIOCETHTOOL: 1016 return ethtool_ioctl(ifr); 1017 #endif 1018 default: 1019 return -EOPNOTSUPP; 1020 } 1021 } 1022 1023 /** 1024 * atl2_tx_timeout - Respond to a Tx Hang 1025 * @netdev: network interface device structure 1026 */ 1027 static void atl2_tx_timeout(struct net_device *netdev) 1028 { 1029 struct atl2_adapter *adapter = netdev_priv(netdev); 1030 1031 /* Do the reset outside of interrupt context */ 1032 schedule_work(&adapter->reset_task); 1033 } 1034 1035 /** 1036 * atl2_watchdog - Timer Call-back 1037 * @data: pointer to netdev cast into an unsigned long 1038 */ 1039 static void atl2_watchdog(unsigned long data) 1040 { 1041 struct atl2_adapter *adapter = (struct atl2_adapter *) data; 1042 1043 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1044 u32 drop_rxd, drop_rxs; 1045 unsigned long flags; 1046 1047 spin_lock_irqsave(&adapter->stats_lock, flags); 1048 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); 1049 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); 1050 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1051 1052 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs; 1053 1054 /* Reset the timer */ 1055 mod_timer(&adapter->watchdog_timer, 1056 round_jiffies(jiffies + 4 * HZ)); 1057 } 1058 } 1059 1060 /** 1061 * atl2_phy_config - Timer Call-back 1062 * @data: pointer to netdev cast into an unsigned long 1063 */ 1064 static void atl2_phy_config(unsigned long data) 1065 { 1066 struct atl2_adapter *adapter = (struct atl2_adapter *) data; 1067 struct atl2_hw *hw = &adapter->hw; 1068 unsigned long flags; 1069 1070 spin_lock_irqsave(&adapter->stats_lock, flags); 1071 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 1072 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN | 1073 MII_CR_RESTART_AUTO_NEG); 1074 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1075 clear_bit(0, &adapter->cfg_phy); 1076 } 1077 1078 static int atl2_up(struct atl2_adapter *adapter) 1079 { 1080 struct net_device *netdev = adapter->netdev; 1081 int err = 0; 1082 u32 val; 1083 1084 /* hardware has been reset, we need to reload some things */ 1085 1086 err = atl2_init_hw(&adapter->hw); 1087 if (err) { 1088 err = -EIO; 1089 return err; 1090 } 1091 1092 atl2_set_multi(netdev); 1093 init_ring_ptrs(adapter); 1094 1095 atl2_restore_vlan(adapter); 1096 1097 if (atl2_configure(adapter)) { 1098 err = -EIO; 1099 goto err_up; 1100 } 1101 1102 clear_bit(__ATL2_DOWN, &adapter->flags); 1103 1104 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 1105 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | 1106 MASTER_CTRL_MANUAL_INT); 1107 1108 atl2_irq_enable(adapter); 1109 1110 err_up: 1111 return err; 1112 } 1113 1114 static void atl2_reinit_locked(struct atl2_adapter *adapter) 1115 { 1116 WARN_ON(in_interrupt()); 1117 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1118 msleep(1); 1119 atl2_down(adapter); 1120 atl2_up(adapter); 1121 clear_bit(__ATL2_RESETTING, &adapter->flags); 1122 } 1123 1124 static void atl2_reset_task(struct work_struct *work) 1125 { 1126 struct atl2_adapter *adapter; 1127 adapter = container_of(work, struct atl2_adapter, reset_task); 1128 1129 atl2_reinit_locked(adapter); 1130 } 1131 1132 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter) 1133 { 1134 u32 value; 1135 struct atl2_hw *hw = &adapter->hw; 1136 struct net_device *netdev = adapter->netdev; 1137 1138 /* Config MAC CTRL Register */ 1139 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1140 1141 /* duplex */ 1142 if (FULL_DUPLEX == adapter->link_duplex) 1143 value |= MAC_CTRL_DUPLX; 1144 1145 /* flow control */ 1146 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 1147 1148 /* PAD & CRC */ 1149 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1150 1151 /* preamble length */ 1152 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << 1153 MAC_CTRL_PRMLEN_SHIFT); 1154 1155 /* vlan */ 1156 __atl2_vlan_mode(netdev->features, &value); 1157 1158 /* filter mode */ 1159 value |= MAC_CTRL_BC_EN; 1160 if (netdev->flags & IFF_PROMISC) 1161 value |= MAC_CTRL_PROMIS_EN; 1162 else if (netdev->flags & IFF_ALLMULTI) 1163 value |= MAC_CTRL_MC_ALL_EN; 1164 1165 /* half retry buffer */ 1166 value |= (((u32)(adapter->hw.retry_buf & 1167 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1168 1169 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1170 } 1171 1172 static int atl2_check_link(struct atl2_adapter *adapter) 1173 { 1174 struct atl2_hw *hw = &adapter->hw; 1175 struct net_device *netdev = adapter->netdev; 1176 int ret_val; 1177 u16 speed, duplex, phy_data; 1178 int reconfig = 0; 1179 1180 /* MII_BMSR must read twise */ 1181 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1182 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1183 if (!(phy_data&BMSR_LSTATUS)) { /* link down */ 1184 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 1185 u32 value; 1186 /* disable rx */ 1187 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1188 value &= ~MAC_CTRL_RX_EN; 1189 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1190 adapter->link_speed = SPEED_0; 1191 netif_carrier_off(netdev); 1192 netif_stop_queue(netdev); 1193 } 1194 return 0; 1195 } 1196 1197 /* Link Up */ 1198 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1199 if (ret_val) 1200 return ret_val; 1201 switch (hw->MediaType) { 1202 case MEDIA_TYPE_100M_FULL: 1203 if (speed != SPEED_100 || duplex != FULL_DUPLEX) 1204 reconfig = 1; 1205 break; 1206 case MEDIA_TYPE_100M_HALF: 1207 if (speed != SPEED_100 || duplex != HALF_DUPLEX) 1208 reconfig = 1; 1209 break; 1210 case MEDIA_TYPE_10M_FULL: 1211 if (speed != SPEED_10 || duplex != FULL_DUPLEX) 1212 reconfig = 1; 1213 break; 1214 case MEDIA_TYPE_10M_HALF: 1215 if (speed != SPEED_10 || duplex != HALF_DUPLEX) 1216 reconfig = 1; 1217 break; 1218 } 1219 /* link result is our setting */ 1220 if (reconfig == 0) { 1221 if (adapter->link_speed != speed || 1222 adapter->link_duplex != duplex) { 1223 adapter->link_speed = speed; 1224 adapter->link_duplex = duplex; 1225 atl2_setup_mac_ctrl(adapter); 1226 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n", 1227 atl2_driver_name, netdev->name, 1228 adapter->link_speed, 1229 adapter->link_duplex == FULL_DUPLEX ? 1230 "Full Duplex" : "Half Duplex"); 1231 } 1232 1233 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */ 1234 netif_carrier_on(netdev); 1235 netif_wake_queue(netdev); 1236 } 1237 return 0; 1238 } 1239 1240 /* change original link status */ 1241 if (netif_carrier_ok(netdev)) { 1242 u32 value; 1243 /* disable rx */ 1244 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1245 value &= ~MAC_CTRL_RX_EN; 1246 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1247 1248 adapter->link_speed = SPEED_0; 1249 netif_carrier_off(netdev); 1250 netif_stop_queue(netdev); 1251 } 1252 1253 /* auto-neg, insert timer to re-config phy 1254 * (if interval smaller than 5 seconds, something strange) */ 1255 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1256 if (!test_and_set_bit(0, &adapter->cfg_phy)) 1257 mod_timer(&adapter->phy_config_timer, 1258 round_jiffies(jiffies + 5 * HZ)); 1259 } 1260 1261 return 0; 1262 } 1263 1264 /** 1265 * atl2_link_chg_task - deal with link change event Out of interrupt context 1266 */ 1267 static void atl2_link_chg_task(struct work_struct *work) 1268 { 1269 struct atl2_adapter *adapter; 1270 unsigned long flags; 1271 1272 adapter = container_of(work, struct atl2_adapter, link_chg_task); 1273 1274 spin_lock_irqsave(&adapter->stats_lock, flags); 1275 atl2_check_link(adapter); 1276 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1277 } 1278 1279 static void atl2_setup_pcicmd(struct pci_dev *pdev) 1280 { 1281 u16 cmd; 1282 1283 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1284 1285 if (cmd & PCI_COMMAND_INTX_DISABLE) 1286 cmd &= ~PCI_COMMAND_INTX_DISABLE; 1287 if (cmd & PCI_COMMAND_IO) 1288 cmd &= ~PCI_COMMAND_IO; 1289 if (0 == (cmd & PCI_COMMAND_MEMORY)) 1290 cmd |= PCI_COMMAND_MEMORY; 1291 if (0 == (cmd & PCI_COMMAND_MASTER)) 1292 cmd |= PCI_COMMAND_MASTER; 1293 pci_write_config_word(pdev, PCI_COMMAND, cmd); 1294 1295 /* 1296 * some motherboards BIOS(PXE/EFI) driver may set PME 1297 * while they transfer control to OS (Windows/Linux) 1298 * so we should clear this bit before NIC work normally 1299 */ 1300 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); 1301 } 1302 1303 #ifdef CONFIG_NET_POLL_CONTROLLER 1304 static void atl2_poll_controller(struct net_device *netdev) 1305 { 1306 disable_irq(netdev->irq); 1307 atl2_intr(netdev->irq, netdev); 1308 enable_irq(netdev->irq); 1309 } 1310 #endif 1311 1312 1313 static const struct net_device_ops atl2_netdev_ops = { 1314 .ndo_open = atl2_open, 1315 .ndo_stop = atl2_close, 1316 .ndo_start_xmit = atl2_xmit_frame, 1317 .ndo_set_rx_mode = atl2_set_multi, 1318 .ndo_validate_addr = eth_validate_addr, 1319 .ndo_set_mac_address = atl2_set_mac, 1320 .ndo_change_mtu = atl2_change_mtu, 1321 .ndo_fix_features = atl2_fix_features, 1322 .ndo_set_features = atl2_set_features, 1323 .ndo_do_ioctl = atl2_ioctl, 1324 .ndo_tx_timeout = atl2_tx_timeout, 1325 #ifdef CONFIG_NET_POLL_CONTROLLER 1326 .ndo_poll_controller = atl2_poll_controller, 1327 #endif 1328 }; 1329 1330 /** 1331 * atl2_probe - Device Initialization Routine 1332 * @pdev: PCI device information struct 1333 * @ent: entry in atl2_pci_tbl 1334 * 1335 * Returns 0 on success, negative on failure 1336 * 1337 * atl2_probe initializes an adapter identified by a pci_dev structure. 1338 * The OS initialization, configuring of the adapter private structure, 1339 * and a hardware reset occur. 1340 */ 1341 static int atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1342 { 1343 struct net_device *netdev; 1344 struct atl2_adapter *adapter; 1345 static int cards_found; 1346 unsigned long mmio_start; 1347 int mmio_len; 1348 int err; 1349 1350 cards_found = 0; 1351 1352 err = pci_enable_device(pdev); 1353 if (err) 1354 return err; 1355 1356 /* 1357 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA 1358 * until the kernel has the proper infrastructure to support 64-bit DMA 1359 * on these devices. 1360 */ 1361 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) && 1362 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 1363 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n"); 1364 goto err_dma; 1365 } 1366 1367 /* Mark all PCI regions associated with PCI device 1368 * pdev as being reserved by owner atl2_driver_name */ 1369 err = pci_request_regions(pdev, atl2_driver_name); 1370 if (err) 1371 goto err_pci_reg; 1372 1373 /* Enables bus-mastering on the device and calls 1374 * pcibios_set_master to do the needed arch specific settings */ 1375 pci_set_master(pdev); 1376 1377 err = -ENOMEM; 1378 netdev = alloc_etherdev(sizeof(struct atl2_adapter)); 1379 if (!netdev) 1380 goto err_alloc_etherdev; 1381 1382 SET_NETDEV_DEV(netdev, &pdev->dev); 1383 1384 pci_set_drvdata(pdev, netdev); 1385 adapter = netdev_priv(netdev); 1386 adapter->netdev = netdev; 1387 adapter->pdev = pdev; 1388 adapter->hw.back = adapter; 1389 1390 mmio_start = pci_resource_start(pdev, 0x0); 1391 mmio_len = pci_resource_len(pdev, 0x0); 1392 1393 adapter->hw.mem_rang = (u32)mmio_len; 1394 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 1395 if (!adapter->hw.hw_addr) { 1396 err = -EIO; 1397 goto err_ioremap; 1398 } 1399 1400 atl2_setup_pcicmd(pdev); 1401 1402 netdev->netdev_ops = &atl2_netdev_ops; 1403 atl2_set_ethtool_ops(netdev); 1404 netdev->watchdog_timeo = 5 * HZ; 1405 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 1406 1407 netdev->mem_start = mmio_start; 1408 netdev->mem_end = mmio_start + mmio_len; 1409 adapter->bd_number = cards_found; 1410 adapter->pci_using_64 = false; 1411 1412 /* setup the private structure */ 1413 err = atl2_sw_init(adapter); 1414 if (err) 1415 goto err_sw_init; 1416 1417 err = -EIO; 1418 1419 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_RX; 1420 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX); 1421 1422 /* Init PHY as early as possible due to power saving issue */ 1423 atl2_phy_init(&adapter->hw); 1424 1425 /* reset the controller to 1426 * put the device in a known good starting state */ 1427 1428 if (atl2_reset_hw(&adapter->hw)) { 1429 err = -EIO; 1430 goto err_reset; 1431 } 1432 1433 /* copy the MAC address out of the EEPROM */ 1434 atl2_read_mac_addr(&adapter->hw); 1435 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); 1436 /* FIXME: do we still need this? */ 1437 #ifdef ETHTOOL_GPERMADDR 1438 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len); 1439 1440 if (!is_valid_ether_addr(netdev->perm_addr)) { 1441 #else 1442 if (!is_valid_ether_addr(netdev->dev_addr)) { 1443 #endif 1444 err = -EIO; 1445 goto err_eeprom; 1446 } 1447 1448 atl2_check_options(adapter); 1449 1450 init_timer(&adapter->watchdog_timer); 1451 adapter->watchdog_timer.function = atl2_watchdog; 1452 adapter->watchdog_timer.data = (unsigned long) adapter; 1453 1454 init_timer(&adapter->phy_config_timer); 1455 adapter->phy_config_timer.function = atl2_phy_config; 1456 adapter->phy_config_timer.data = (unsigned long) adapter; 1457 1458 INIT_WORK(&adapter->reset_task, atl2_reset_task); 1459 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task); 1460 1461 strcpy(netdev->name, "eth%d"); /* ?? */ 1462 err = register_netdev(netdev); 1463 if (err) 1464 goto err_register; 1465 1466 /* assume we have no link for now */ 1467 netif_carrier_off(netdev); 1468 netif_stop_queue(netdev); 1469 1470 cards_found++; 1471 1472 return 0; 1473 1474 err_reset: 1475 err_register: 1476 err_sw_init: 1477 err_eeprom: 1478 iounmap(adapter->hw.hw_addr); 1479 err_ioremap: 1480 free_netdev(netdev); 1481 err_alloc_etherdev: 1482 pci_release_regions(pdev); 1483 err_pci_reg: 1484 err_dma: 1485 pci_disable_device(pdev); 1486 return err; 1487 } 1488 1489 /** 1490 * atl2_remove - Device Removal Routine 1491 * @pdev: PCI device information struct 1492 * 1493 * atl2_remove is called by the PCI subsystem to alert the driver 1494 * that it should release a PCI device. The could be caused by a 1495 * Hot-Plug event, or because the driver is going to be removed from 1496 * memory. 1497 */ 1498 /* FIXME: write the original MAC address back in case it was changed from a 1499 * BIOS-set value, as in atl1 -- CHS */ 1500 static void atl2_remove(struct pci_dev *pdev) 1501 { 1502 struct net_device *netdev = pci_get_drvdata(pdev); 1503 struct atl2_adapter *adapter = netdev_priv(netdev); 1504 1505 /* flush_scheduled work may reschedule our watchdog task, so 1506 * explicitly disable watchdog tasks from being rescheduled */ 1507 set_bit(__ATL2_DOWN, &adapter->flags); 1508 1509 del_timer_sync(&adapter->watchdog_timer); 1510 del_timer_sync(&adapter->phy_config_timer); 1511 cancel_work_sync(&adapter->reset_task); 1512 cancel_work_sync(&adapter->link_chg_task); 1513 1514 unregister_netdev(netdev); 1515 1516 atl2_force_ps(&adapter->hw); 1517 1518 iounmap(adapter->hw.hw_addr); 1519 pci_release_regions(pdev); 1520 1521 free_netdev(netdev); 1522 1523 pci_disable_device(pdev); 1524 } 1525 1526 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state) 1527 { 1528 struct net_device *netdev = pci_get_drvdata(pdev); 1529 struct atl2_adapter *adapter = netdev_priv(netdev); 1530 struct atl2_hw *hw = &adapter->hw; 1531 u16 speed, duplex; 1532 u32 ctrl = 0; 1533 u32 wufc = adapter->wol; 1534 1535 #ifdef CONFIG_PM 1536 int retval = 0; 1537 #endif 1538 1539 netif_device_detach(netdev); 1540 1541 if (netif_running(netdev)) { 1542 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 1543 atl2_down(adapter); 1544 } 1545 1546 #ifdef CONFIG_PM 1547 retval = pci_save_state(pdev); 1548 if (retval) 1549 return retval; 1550 #endif 1551 1552 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1553 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1554 if (ctrl & BMSR_LSTATUS) 1555 wufc &= ~ATLX_WUFC_LNKC; 1556 1557 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) { 1558 u32 ret_val; 1559 /* get current link speed & duplex */ 1560 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1561 if (ret_val) { 1562 printk(KERN_DEBUG 1563 "%s: get speed&duplex error while suspend\n", 1564 atl2_driver_name); 1565 goto wol_dis; 1566 } 1567 1568 ctrl = 0; 1569 1570 /* turn on magic packet wol */ 1571 if (wufc & ATLX_WUFC_MAG) 1572 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); 1573 1574 /* ignore Link Chg event when Link is up */ 1575 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1576 1577 /* Config MAC CTRL Register */ 1578 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1579 if (FULL_DUPLEX == adapter->link_duplex) 1580 ctrl |= MAC_CTRL_DUPLX; 1581 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1582 ctrl |= (((u32)adapter->hw.preamble_len & 1583 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 1584 ctrl |= (((u32)(adapter->hw.retry_buf & 1585 MAC_CTRL_HALF_LEFT_BUF_MASK)) << 1586 MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1587 if (wufc & ATLX_WUFC_MAG) { 1588 /* magic packet maybe Broadcast&multicast&Unicast */ 1589 ctrl |= MAC_CTRL_BC_EN; 1590 } 1591 1592 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); 1593 1594 /* pcie patch */ 1595 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1596 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1597 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1598 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1599 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1600 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1601 1602 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1603 goto suspend_exit; 1604 } 1605 1606 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) { 1607 /* link is down, so only LINK CHG WOL event enable */ 1608 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 1609 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1610 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); 1611 1612 /* pcie patch */ 1613 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1614 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1615 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1616 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1617 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1618 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1619 1620 hw->phy_configured = false; /* re-init PHY when resume */ 1621 1622 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1623 1624 goto suspend_exit; 1625 } 1626 1627 wol_dis: 1628 /* WOL disabled */ 1629 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); 1630 1631 /* pcie patch */ 1632 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1633 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1634 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1635 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1636 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1637 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1638 1639 atl2_force_ps(hw); 1640 hw->phy_configured = false; /* re-init PHY when resume */ 1641 1642 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1643 1644 suspend_exit: 1645 if (netif_running(netdev)) 1646 atl2_free_irq(adapter); 1647 1648 pci_disable_device(pdev); 1649 1650 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1651 1652 return 0; 1653 } 1654 1655 #ifdef CONFIG_PM 1656 static int atl2_resume(struct pci_dev *pdev) 1657 { 1658 struct net_device *netdev = pci_get_drvdata(pdev); 1659 struct atl2_adapter *adapter = netdev_priv(netdev); 1660 u32 err; 1661 1662 pci_set_power_state(pdev, PCI_D0); 1663 pci_restore_state(pdev); 1664 1665 err = pci_enable_device(pdev); 1666 if (err) { 1667 printk(KERN_ERR 1668 "atl2: Cannot enable PCI device from suspend\n"); 1669 return err; 1670 } 1671 1672 pci_set_master(pdev); 1673 1674 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ 1675 1676 pci_enable_wake(pdev, PCI_D3hot, 0); 1677 pci_enable_wake(pdev, PCI_D3cold, 0); 1678 1679 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); 1680 1681 if (netif_running(netdev)) { 1682 err = atl2_request_irq(adapter); 1683 if (err) 1684 return err; 1685 } 1686 1687 atl2_reset_hw(&adapter->hw); 1688 1689 if (netif_running(netdev)) 1690 atl2_up(adapter); 1691 1692 netif_device_attach(netdev); 1693 1694 return 0; 1695 } 1696 #endif 1697 1698 static void atl2_shutdown(struct pci_dev *pdev) 1699 { 1700 atl2_suspend(pdev, PMSG_SUSPEND); 1701 } 1702 1703 static struct pci_driver atl2_driver = { 1704 .name = atl2_driver_name, 1705 .id_table = atl2_pci_tbl, 1706 .probe = atl2_probe, 1707 .remove = atl2_remove, 1708 /* Power Management Hooks */ 1709 .suspend = atl2_suspend, 1710 #ifdef CONFIG_PM 1711 .resume = atl2_resume, 1712 #endif 1713 .shutdown = atl2_shutdown, 1714 }; 1715 1716 /** 1717 * atl2_init_module - Driver Registration Routine 1718 * 1719 * atl2_init_module is the first routine called when the driver is 1720 * loaded. All it does is register with the PCI subsystem. 1721 */ 1722 static int __init atl2_init_module(void) 1723 { 1724 printk(KERN_INFO "%s - version %s\n", atl2_driver_string, 1725 atl2_driver_version); 1726 printk(KERN_INFO "%s\n", atl2_copyright); 1727 return pci_register_driver(&atl2_driver); 1728 } 1729 module_init(atl2_init_module); 1730 1731 /** 1732 * atl2_exit_module - Driver Exit Cleanup Routine 1733 * 1734 * atl2_exit_module is called just before the driver is removed 1735 * from memory. 1736 */ 1737 static void __exit atl2_exit_module(void) 1738 { 1739 pci_unregister_driver(&atl2_driver); 1740 } 1741 module_exit(atl2_exit_module); 1742 1743 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1744 { 1745 struct atl2_adapter *adapter = hw->back; 1746 pci_read_config_word(adapter->pdev, reg, value); 1747 } 1748 1749 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1750 { 1751 struct atl2_adapter *adapter = hw->back; 1752 pci_write_config_word(adapter->pdev, reg, *value); 1753 } 1754 1755 static int atl2_get_settings(struct net_device *netdev, 1756 struct ethtool_cmd *ecmd) 1757 { 1758 struct atl2_adapter *adapter = netdev_priv(netdev); 1759 struct atl2_hw *hw = &adapter->hw; 1760 1761 ecmd->supported = (SUPPORTED_10baseT_Half | 1762 SUPPORTED_10baseT_Full | 1763 SUPPORTED_100baseT_Half | 1764 SUPPORTED_100baseT_Full | 1765 SUPPORTED_Autoneg | 1766 SUPPORTED_TP); 1767 ecmd->advertising = ADVERTISED_TP; 1768 1769 ecmd->advertising |= ADVERTISED_Autoneg; 1770 ecmd->advertising |= hw->autoneg_advertised; 1771 1772 ecmd->port = PORT_TP; 1773 ecmd->phy_address = 0; 1774 ecmd->transceiver = XCVR_INTERNAL; 1775 1776 if (adapter->link_speed != SPEED_0) { 1777 ethtool_cmd_speed_set(ecmd, adapter->link_speed); 1778 if (adapter->link_duplex == FULL_DUPLEX) 1779 ecmd->duplex = DUPLEX_FULL; 1780 else 1781 ecmd->duplex = DUPLEX_HALF; 1782 } else { 1783 ethtool_cmd_speed_set(ecmd, -1); 1784 ecmd->duplex = -1; 1785 } 1786 1787 ecmd->autoneg = AUTONEG_ENABLE; 1788 return 0; 1789 } 1790 1791 static int atl2_set_settings(struct net_device *netdev, 1792 struct ethtool_cmd *ecmd) 1793 { 1794 struct atl2_adapter *adapter = netdev_priv(netdev); 1795 struct atl2_hw *hw = &adapter->hw; 1796 1797 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1798 msleep(1); 1799 1800 if (ecmd->autoneg == AUTONEG_ENABLE) { 1801 #define MY_ADV_MASK (ADVERTISE_10_HALF | \ 1802 ADVERTISE_10_FULL | \ 1803 ADVERTISE_100_HALF| \ 1804 ADVERTISE_100_FULL) 1805 1806 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) { 1807 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; 1808 hw->autoneg_advertised = MY_ADV_MASK; 1809 } else if ((ecmd->advertising & MY_ADV_MASK) == 1810 ADVERTISE_100_FULL) { 1811 hw->MediaType = MEDIA_TYPE_100M_FULL; 1812 hw->autoneg_advertised = ADVERTISE_100_FULL; 1813 } else if ((ecmd->advertising & MY_ADV_MASK) == 1814 ADVERTISE_100_HALF) { 1815 hw->MediaType = MEDIA_TYPE_100M_HALF; 1816 hw->autoneg_advertised = ADVERTISE_100_HALF; 1817 } else if ((ecmd->advertising & MY_ADV_MASK) == 1818 ADVERTISE_10_FULL) { 1819 hw->MediaType = MEDIA_TYPE_10M_FULL; 1820 hw->autoneg_advertised = ADVERTISE_10_FULL; 1821 } else if ((ecmd->advertising & MY_ADV_MASK) == 1822 ADVERTISE_10_HALF) { 1823 hw->MediaType = MEDIA_TYPE_10M_HALF; 1824 hw->autoneg_advertised = ADVERTISE_10_HALF; 1825 } else { 1826 clear_bit(__ATL2_RESETTING, &adapter->flags); 1827 return -EINVAL; 1828 } 1829 ecmd->advertising = hw->autoneg_advertised | 1830 ADVERTISED_TP | ADVERTISED_Autoneg; 1831 } else { 1832 clear_bit(__ATL2_RESETTING, &adapter->flags); 1833 return -EINVAL; 1834 } 1835 1836 /* reset the link */ 1837 if (netif_running(adapter->netdev)) { 1838 atl2_down(adapter); 1839 atl2_up(adapter); 1840 } else 1841 atl2_reset_hw(&adapter->hw); 1842 1843 clear_bit(__ATL2_RESETTING, &adapter->flags); 1844 return 0; 1845 } 1846 1847 static u32 atl2_get_msglevel(struct net_device *netdev) 1848 { 1849 return 0; 1850 } 1851 1852 /* 1853 * It's sane for this to be empty, but we might want to take advantage of this. 1854 */ 1855 static void atl2_set_msglevel(struct net_device *netdev, u32 data) 1856 { 1857 } 1858 1859 static int atl2_get_regs_len(struct net_device *netdev) 1860 { 1861 #define ATL2_REGS_LEN 42 1862 return sizeof(u32) * ATL2_REGS_LEN; 1863 } 1864 1865 static void atl2_get_regs(struct net_device *netdev, 1866 struct ethtool_regs *regs, void *p) 1867 { 1868 struct atl2_adapter *adapter = netdev_priv(netdev); 1869 struct atl2_hw *hw = &adapter->hw; 1870 u32 *regs_buff = p; 1871 u16 phy_data; 1872 1873 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN); 1874 1875 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 1876 1877 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); 1878 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 1879 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); 1880 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); 1881 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); 1882 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); 1883 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); 1884 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); 1885 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); 1886 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); 1887 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); 1888 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); 1889 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); 1890 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); 1891 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); 1892 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 1893 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); 1894 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); 1895 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); 1896 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); 1897 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); 1898 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); 1899 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); 1900 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); 1901 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); 1902 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); 1903 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); 1904 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); 1905 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); 1906 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); 1907 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); 1908 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); 1909 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); 1910 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); 1911 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); 1912 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); 1913 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); 1914 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); 1915 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); 1916 1917 atl2_read_phy_reg(hw, MII_BMCR, &phy_data); 1918 regs_buff[40] = (u32)phy_data; 1919 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1920 regs_buff[41] = (u32)phy_data; 1921 } 1922 1923 static int atl2_get_eeprom_len(struct net_device *netdev) 1924 { 1925 struct atl2_adapter *adapter = netdev_priv(netdev); 1926 1927 if (!atl2_check_eeprom_exist(&adapter->hw)) 1928 return 512; 1929 else 1930 return 0; 1931 } 1932 1933 static int atl2_get_eeprom(struct net_device *netdev, 1934 struct ethtool_eeprom *eeprom, u8 *bytes) 1935 { 1936 struct atl2_adapter *adapter = netdev_priv(netdev); 1937 struct atl2_hw *hw = &adapter->hw; 1938 u32 *eeprom_buff; 1939 int first_dword, last_dword; 1940 int ret_val = 0; 1941 int i; 1942 1943 if (eeprom->len == 0) 1944 return -EINVAL; 1945 1946 if (atl2_check_eeprom_exist(hw)) 1947 return -EINVAL; 1948 1949 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 1950 1951 first_dword = eeprom->offset >> 2; 1952 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1953 1954 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1), 1955 GFP_KERNEL); 1956 if (!eeprom_buff) 1957 return -ENOMEM; 1958 1959 for (i = first_dword; i < last_dword; i++) { 1960 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) { 1961 ret_val = -EIO; 1962 goto free; 1963 } 1964 } 1965 1966 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), 1967 eeprom->len); 1968 free: 1969 kfree(eeprom_buff); 1970 1971 return ret_val; 1972 } 1973 1974 static int atl2_set_eeprom(struct net_device *netdev, 1975 struct ethtool_eeprom *eeprom, u8 *bytes) 1976 { 1977 struct atl2_adapter *adapter = netdev_priv(netdev); 1978 struct atl2_hw *hw = &adapter->hw; 1979 u32 *eeprom_buff; 1980 u32 *ptr; 1981 int max_len, first_dword, last_dword, ret_val = 0; 1982 int i; 1983 1984 if (eeprom->len == 0) 1985 return -EOPNOTSUPP; 1986 1987 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 1988 return -EFAULT; 1989 1990 max_len = 512; 1991 1992 first_dword = eeprom->offset >> 2; 1993 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1994 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 1995 if (!eeprom_buff) 1996 return -ENOMEM; 1997 1998 ptr = eeprom_buff; 1999 2000 if (eeprom->offset & 3) { 2001 /* need read/modify/write of first changed EEPROM word */ 2002 /* only the second byte of the word is being modified */ 2003 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) { 2004 ret_val = -EIO; 2005 goto out; 2006 } 2007 ptr++; 2008 } 2009 if (((eeprom->offset + eeprom->len) & 3)) { 2010 /* 2011 * need read/modify/write of last changed EEPROM word 2012 * only the first byte of the word is being modified 2013 */ 2014 if (!atl2_read_eeprom(hw, last_dword * 4, 2015 &(eeprom_buff[last_dword - first_dword]))) { 2016 ret_val = -EIO; 2017 goto out; 2018 } 2019 } 2020 2021 /* Device's eeprom is always little-endian, word addressable */ 2022 memcpy(ptr, bytes, eeprom->len); 2023 2024 for (i = 0; i < last_dword - first_dword + 1; i++) { 2025 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) { 2026 ret_val = -EIO; 2027 goto out; 2028 } 2029 } 2030 out: 2031 kfree(eeprom_buff); 2032 return ret_val; 2033 } 2034 2035 static void atl2_get_drvinfo(struct net_device *netdev, 2036 struct ethtool_drvinfo *drvinfo) 2037 { 2038 struct atl2_adapter *adapter = netdev_priv(netdev); 2039 2040 strlcpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver)); 2041 strlcpy(drvinfo->version, atl2_driver_version, 2042 sizeof(drvinfo->version)); 2043 strlcpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version)); 2044 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 2045 sizeof(drvinfo->bus_info)); 2046 drvinfo->n_stats = 0; 2047 drvinfo->testinfo_len = 0; 2048 drvinfo->regdump_len = atl2_get_regs_len(netdev); 2049 drvinfo->eedump_len = atl2_get_eeprom_len(netdev); 2050 } 2051 2052 static void atl2_get_wol(struct net_device *netdev, 2053 struct ethtool_wolinfo *wol) 2054 { 2055 struct atl2_adapter *adapter = netdev_priv(netdev); 2056 2057 wol->supported = WAKE_MAGIC; 2058 wol->wolopts = 0; 2059 2060 if (adapter->wol & ATLX_WUFC_EX) 2061 wol->wolopts |= WAKE_UCAST; 2062 if (adapter->wol & ATLX_WUFC_MC) 2063 wol->wolopts |= WAKE_MCAST; 2064 if (adapter->wol & ATLX_WUFC_BC) 2065 wol->wolopts |= WAKE_BCAST; 2066 if (adapter->wol & ATLX_WUFC_MAG) 2067 wol->wolopts |= WAKE_MAGIC; 2068 if (adapter->wol & ATLX_WUFC_LNKC) 2069 wol->wolopts |= WAKE_PHY; 2070 } 2071 2072 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2073 { 2074 struct atl2_adapter *adapter = netdev_priv(netdev); 2075 2076 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2077 return -EOPNOTSUPP; 2078 2079 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)) 2080 return -EOPNOTSUPP; 2081 2082 /* these settings will always override what we currently have */ 2083 adapter->wol = 0; 2084 2085 if (wol->wolopts & WAKE_MAGIC) 2086 adapter->wol |= ATLX_WUFC_MAG; 2087 if (wol->wolopts & WAKE_PHY) 2088 adapter->wol |= ATLX_WUFC_LNKC; 2089 2090 return 0; 2091 } 2092 2093 static int atl2_nway_reset(struct net_device *netdev) 2094 { 2095 struct atl2_adapter *adapter = netdev_priv(netdev); 2096 if (netif_running(netdev)) 2097 atl2_reinit_locked(adapter); 2098 return 0; 2099 } 2100 2101 static const struct ethtool_ops atl2_ethtool_ops = { 2102 .get_settings = atl2_get_settings, 2103 .set_settings = atl2_set_settings, 2104 .get_drvinfo = atl2_get_drvinfo, 2105 .get_regs_len = atl2_get_regs_len, 2106 .get_regs = atl2_get_regs, 2107 .get_wol = atl2_get_wol, 2108 .set_wol = atl2_set_wol, 2109 .get_msglevel = atl2_get_msglevel, 2110 .set_msglevel = atl2_set_msglevel, 2111 .nway_reset = atl2_nway_reset, 2112 .get_link = ethtool_op_get_link, 2113 .get_eeprom_len = atl2_get_eeprom_len, 2114 .get_eeprom = atl2_get_eeprom, 2115 .set_eeprom = atl2_set_eeprom, 2116 }; 2117 2118 static void atl2_set_ethtool_ops(struct net_device *netdev) 2119 { 2120 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops); 2121 } 2122 2123 #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \ 2124 (((a) & 0xff00ff00) >> 8)) 2125 #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16)) 2126 #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8)) 2127 2128 /* 2129 * Reset the transmit and receive units; mask and clear all interrupts. 2130 * 2131 * hw - Struct containing variables accessed by shared code 2132 * return : 0 or idle status (if error) 2133 */ 2134 static s32 atl2_reset_hw(struct atl2_hw *hw) 2135 { 2136 u32 icr; 2137 u16 pci_cfg_cmd_word; 2138 int i; 2139 2140 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ 2141 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2142 if ((pci_cfg_cmd_word & 2143 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) != 2144 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) { 2145 pci_cfg_cmd_word |= 2146 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER); 2147 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2148 } 2149 2150 /* Clear Interrupt mask to stop board from generating 2151 * interrupts & Clear any pending interrupt events 2152 */ 2153 /* FIXME */ 2154 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */ 2155 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */ 2156 2157 /* Issue Soft Reset to the MAC. This will reset the chip's 2158 * transmit, receive, DMA. It will not effect 2159 * the current PCI configuration. The global reset bit is self- 2160 * clearing, and should clear within a microsecond. 2161 */ 2162 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); 2163 wmb(); 2164 msleep(1); /* delay about 1ms */ 2165 2166 /* Wait at least 10ms for All module to be Idle */ 2167 for (i = 0; i < 10; i++) { 2168 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); 2169 if (!icr) 2170 break; 2171 msleep(1); /* delay 1 ms */ 2172 cpu_relax(); 2173 } 2174 2175 if (icr) 2176 return icr; 2177 2178 return 0; 2179 } 2180 2181 #define CUSTOM_SPI_CS_SETUP 2 2182 #define CUSTOM_SPI_CLK_HI 2 2183 #define CUSTOM_SPI_CLK_LO 2 2184 #define CUSTOM_SPI_CS_HOLD 2 2185 #define CUSTOM_SPI_CS_HI 3 2186 2187 static struct atl2_spi_flash_dev flash_table[] = 2188 { 2189 /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */ 2190 {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 }, 2191 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 }, 2192 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 }, 2193 }; 2194 2195 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf) 2196 { 2197 int i; 2198 u32 value; 2199 2200 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); 2201 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); 2202 2203 value = SPI_FLASH_CTRL_WAIT_READY | 2204 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << 2205 SPI_FLASH_CTRL_CS_SETUP_SHIFT | 2206 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << 2207 SPI_FLASH_CTRL_CLK_HI_SHIFT | 2208 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << 2209 SPI_FLASH_CTRL_CLK_LO_SHIFT | 2210 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << 2211 SPI_FLASH_CTRL_CS_HOLD_SHIFT | 2212 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << 2213 SPI_FLASH_CTRL_CS_HI_SHIFT | 2214 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT; 2215 2216 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2217 2218 value |= SPI_FLASH_CTRL_START; 2219 2220 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2221 2222 for (i = 0; i < 10; i++) { 2223 msleep(1); 2224 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2225 if (!(value & SPI_FLASH_CTRL_START)) 2226 break; 2227 } 2228 2229 if (value & SPI_FLASH_CTRL_START) 2230 return false; 2231 2232 *buf = ATL2_READ_REG(hw, REG_SPI_DATA); 2233 2234 return true; 2235 } 2236 2237 /* 2238 * get_permanent_address 2239 * return 0 if get valid mac address, 2240 */ 2241 static int get_permanent_address(struct atl2_hw *hw) 2242 { 2243 u32 Addr[2]; 2244 u32 i, Control; 2245 u16 Register; 2246 u8 EthAddr[ETH_ALEN]; 2247 bool KeyValid; 2248 2249 if (is_valid_ether_addr(hw->perm_mac_addr)) 2250 return 0; 2251 2252 Addr[0] = 0; 2253 Addr[1] = 0; 2254 2255 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ 2256 Register = 0; 2257 KeyValid = false; 2258 2259 /* Read out all EEPROM content */ 2260 i = 0; 2261 while (1) { 2262 if (atl2_read_eeprom(hw, i + 0x100, &Control)) { 2263 if (KeyValid) { 2264 if (Register == REG_MAC_STA_ADDR) 2265 Addr[0] = Control; 2266 else if (Register == 2267 (REG_MAC_STA_ADDR + 4)) 2268 Addr[1] = Control; 2269 KeyValid = false; 2270 } else if ((Control & 0xff) == 0x5A) { 2271 KeyValid = true; 2272 Register = (u16) (Control >> 16); 2273 } else { 2274 /* assume data end while encount an invalid KEYWORD */ 2275 break; 2276 } 2277 } else { 2278 break; /* read error */ 2279 } 2280 i += 4; 2281 } 2282 2283 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2284 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2285 2286 if (is_valid_ether_addr(EthAddr)) { 2287 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2288 return 0; 2289 } 2290 return 1; 2291 } 2292 2293 /* see if SPI flash exists? */ 2294 Addr[0] = 0; 2295 Addr[1] = 0; 2296 Register = 0; 2297 KeyValid = false; 2298 i = 0; 2299 while (1) { 2300 if (atl2_spi_read(hw, i + 0x1f000, &Control)) { 2301 if (KeyValid) { 2302 if (Register == REG_MAC_STA_ADDR) 2303 Addr[0] = Control; 2304 else if (Register == (REG_MAC_STA_ADDR + 4)) 2305 Addr[1] = Control; 2306 KeyValid = false; 2307 } else if ((Control & 0xff) == 0x5A) { 2308 KeyValid = true; 2309 Register = (u16) (Control >> 16); 2310 } else { 2311 break; /* data end */ 2312 } 2313 } else { 2314 break; /* read error */ 2315 } 2316 i += 4; 2317 } 2318 2319 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2320 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]); 2321 if (is_valid_ether_addr(EthAddr)) { 2322 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2323 return 0; 2324 } 2325 /* maybe MAC-address is from BIOS */ 2326 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 2327 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4); 2328 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2329 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2330 2331 if (is_valid_ether_addr(EthAddr)) { 2332 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2333 return 0; 2334 } 2335 2336 return 1; 2337 } 2338 2339 /* 2340 * Reads the adapter's MAC address from the EEPROM 2341 * 2342 * hw - Struct containing variables accessed by shared code 2343 */ 2344 static s32 atl2_read_mac_addr(struct atl2_hw *hw) 2345 { 2346 if (get_permanent_address(hw)) { 2347 /* for test */ 2348 /* FIXME: shouldn't we use eth_random_addr() here? */ 2349 hw->perm_mac_addr[0] = 0x00; 2350 hw->perm_mac_addr[1] = 0x13; 2351 hw->perm_mac_addr[2] = 0x74; 2352 hw->perm_mac_addr[3] = 0x00; 2353 hw->perm_mac_addr[4] = 0x5c; 2354 hw->perm_mac_addr[5] = 0x38; 2355 } 2356 2357 memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN); 2358 2359 return 0; 2360 } 2361 2362 /* 2363 * Hashes an address to determine its location in the multicast table 2364 * 2365 * hw - Struct containing variables accessed by shared code 2366 * mc_addr - the multicast address to hash 2367 * 2368 * atl2_hash_mc_addr 2369 * purpose 2370 * set hash value for a multicast address 2371 * hash calcu processing : 2372 * 1. calcu 32bit CRC for multicast address 2373 * 2. reverse crc with MSB to LSB 2374 */ 2375 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) 2376 { 2377 u32 crc32, value; 2378 int i; 2379 2380 value = 0; 2381 crc32 = ether_crc_le(6, mc_addr); 2382 2383 for (i = 0; i < 32; i++) 2384 value |= (((crc32 >> i) & 1) << (31 - i)); 2385 2386 return value; 2387 } 2388 2389 /* 2390 * Sets the bit in the multicast table corresponding to the hash value. 2391 * 2392 * hw - Struct containing variables accessed by shared code 2393 * hash_value - Multicast address hash value 2394 */ 2395 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value) 2396 { 2397 u32 hash_bit, hash_reg; 2398 u32 mta; 2399 2400 /* The HASH Table is a register array of 2 32-bit registers. 2401 * It is treated like an array of 64 bits. We want to set 2402 * bit BitArray[hash_value]. So we figure out what register 2403 * the bit is in, read it, OR in the new bit, then write 2404 * back the new value. The register is determined by the 2405 * upper 7 bits of the hash value and the bit within that 2406 * register are determined by the lower 5 bits of the value. 2407 */ 2408 hash_reg = (hash_value >> 31) & 0x1; 2409 hash_bit = (hash_value >> 26) & 0x1F; 2410 2411 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); 2412 2413 mta |= (1 << hash_bit); 2414 2415 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); 2416 } 2417 2418 /* 2419 * atl2_init_pcie - init PCIE module 2420 */ 2421 static void atl2_init_pcie(struct atl2_hw *hw) 2422 { 2423 u32 value; 2424 value = LTSSM_TEST_MODE_DEF; 2425 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); 2426 2427 value = PCIE_DLL_TX_CTRL1_DEF; 2428 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); 2429 } 2430 2431 static void atl2_init_flash_opcode(struct atl2_hw *hw) 2432 { 2433 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) 2434 hw->flash_vendor = 0; /* ATMEL */ 2435 2436 /* Init OP table */ 2437 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, 2438 flash_table[hw->flash_vendor].cmdPROGRAM); 2439 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, 2440 flash_table[hw->flash_vendor].cmdSECTOR_ERASE); 2441 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, 2442 flash_table[hw->flash_vendor].cmdCHIP_ERASE); 2443 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, 2444 flash_table[hw->flash_vendor].cmdRDID); 2445 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, 2446 flash_table[hw->flash_vendor].cmdWREN); 2447 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, 2448 flash_table[hw->flash_vendor].cmdRDSR); 2449 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, 2450 flash_table[hw->flash_vendor].cmdWRSR); 2451 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, 2452 flash_table[hw->flash_vendor].cmdREAD); 2453 } 2454 2455 /******************************************************************** 2456 * Performs basic configuration of the adapter. 2457 * 2458 * hw - Struct containing variables accessed by shared code 2459 * Assumes that the controller has previously been reset and is in a 2460 * post-reset uninitialized state. Initializes multicast table, 2461 * and Calls routines to setup link 2462 * Leaves the transmit and receive units disabled and uninitialized. 2463 ********************************************************************/ 2464 static s32 atl2_init_hw(struct atl2_hw *hw) 2465 { 2466 u32 ret_val = 0; 2467 2468 atl2_init_pcie(hw); 2469 2470 /* Zero out the Multicast HASH table */ 2471 /* clear the old settings from the multicast hash table */ 2472 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 2473 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 2474 2475 atl2_init_flash_opcode(hw); 2476 2477 ret_val = atl2_phy_init(hw); 2478 2479 return ret_val; 2480 } 2481 2482 /* 2483 * Detects the current speed and duplex settings of the hardware. 2484 * 2485 * hw - Struct containing variables accessed by shared code 2486 * speed - Speed of the connection 2487 * duplex - Duplex setting of the connection 2488 */ 2489 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, 2490 u16 *duplex) 2491 { 2492 s32 ret_val; 2493 u16 phy_data; 2494 2495 /* Read PHY Specific Status Register (17) */ 2496 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); 2497 if (ret_val) 2498 return ret_val; 2499 2500 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) 2501 return ATLX_ERR_PHY_RES; 2502 2503 switch (phy_data & MII_ATLX_PSSR_SPEED) { 2504 case MII_ATLX_PSSR_100MBS: 2505 *speed = SPEED_100; 2506 break; 2507 case MII_ATLX_PSSR_10MBS: 2508 *speed = SPEED_10; 2509 break; 2510 default: 2511 return ATLX_ERR_PHY_SPEED; 2512 break; 2513 } 2514 2515 if (phy_data & MII_ATLX_PSSR_DPLX) 2516 *duplex = FULL_DUPLEX; 2517 else 2518 *duplex = HALF_DUPLEX; 2519 2520 return 0; 2521 } 2522 2523 /* 2524 * Reads the value from a PHY register 2525 * hw - Struct containing variables accessed by shared code 2526 * reg_addr - address of the PHY register to read 2527 */ 2528 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) 2529 { 2530 u32 val; 2531 int i; 2532 2533 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 2534 MDIO_START | 2535 MDIO_SUP_PREAMBLE | 2536 MDIO_RW | 2537 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2538 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2539 2540 wmb(); 2541 2542 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2543 udelay(2); 2544 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2545 if (!(val & (MDIO_START | MDIO_BUSY))) 2546 break; 2547 wmb(); 2548 } 2549 if (!(val & (MDIO_START | MDIO_BUSY))) { 2550 *phy_data = (u16)val; 2551 return 0; 2552 } 2553 2554 return ATLX_ERR_PHY; 2555 } 2556 2557 /* 2558 * Writes a value to a PHY register 2559 * hw - Struct containing variables accessed by shared code 2560 * reg_addr - address of the PHY register to write 2561 * data - data to write to the PHY 2562 */ 2563 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) 2564 { 2565 int i; 2566 u32 val; 2567 2568 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 2569 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 2570 MDIO_SUP_PREAMBLE | 2571 MDIO_START | 2572 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2573 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2574 2575 wmb(); 2576 2577 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2578 udelay(2); 2579 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2580 if (!(val & (MDIO_START | MDIO_BUSY))) 2581 break; 2582 2583 wmb(); 2584 } 2585 2586 if (!(val & (MDIO_START | MDIO_BUSY))) 2587 return 0; 2588 2589 return ATLX_ERR_PHY; 2590 } 2591 2592 /* 2593 * Configures PHY autoneg and flow control advertisement settings 2594 * 2595 * hw - Struct containing variables accessed by shared code 2596 */ 2597 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) 2598 { 2599 s32 ret_val; 2600 s16 mii_autoneg_adv_reg; 2601 2602 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2603 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 2604 2605 /* Need to parse autoneg_advertised and set up 2606 * the appropriate PHY registers. First we will parse for 2607 * autoneg_advertised software override. Since we can advertise 2608 * a plethora of combinations, we need to check each bit 2609 * individually. 2610 */ 2611 2612 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 2613 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2614 * the 1000Base-T Control Register (Address 9). */ 2615 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 2616 2617 /* Need to parse MediaType and setup the 2618 * appropriate PHY registers. */ 2619 switch (hw->MediaType) { 2620 case MEDIA_TYPE_AUTO_SENSOR: 2621 mii_autoneg_adv_reg |= 2622 (MII_AR_10T_HD_CAPS | 2623 MII_AR_10T_FD_CAPS | 2624 MII_AR_100TX_HD_CAPS| 2625 MII_AR_100TX_FD_CAPS); 2626 hw->autoneg_advertised = 2627 ADVERTISE_10_HALF | 2628 ADVERTISE_10_FULL | 2629 ADVERTISE_100_HALF| 2630 ADVERTISE_100_FULL; 2631 break; 2632 case MEDIA_TYPE_100M_FULL: 2633 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 2634 hw->autoneg_advertised = ADVERTISE_100_FULL; 2635 break; 2636 case MEDIA_TYPE_100M_HALF: 2637 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 2638 hw->autoneg_advertised = ADVERTISE_100_HALF; 2639 break; 2640 case MEDIA_TYPE_10M_FULL: 2641 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 2642 hw->autoneg_advertised = ADVERTISE_10_FULL; 2643 break; 2644 default: 2645 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 2646 hw->autoneg_advertised = ADVERTISE_10_HALF; 2647 break; 2648 } 2649 2650 /* flow control fixed to enable all */ 2651 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 2652 2653 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 2654 2655 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 2656 2657 if (ret_val) 2658 return ret_val; 2659 2660 return 0; 2661 } 2662 2663 /* 2664 * Resets the PHY and make all config validate 2665 * 2666 * hw - Struct containing variables accessed by shared code 2667 * 2668 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) 2669 */ 2670 static s32 atl2_phy_commit(struct atl2_hw *hw) 2671 { 2672 s32 ret_val; 2673 u16 phy_data; 2674 2675 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2676 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); 2677 if (ret_val) { 2678 u32 val; 2679 int i; 2680 /* pcie serdes link may be down ! */ 2681 for (i = 0; i < 25; i++) { 2682 msleep(1); 2683 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2684 if (!(val & (MDIO_START | MDIO_BUSY))) 2685 break; 2686 } 2687 2688 if (0 != (val & (MDIO_START | MDIO_BUSY))) { 2689 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n"); 2690 return ret_val; 2691 } 2692 } 2693 return 0; 2694 } 2695 2696 static s32 atl2_phy_init(struct atl2_hw *hw) 2697 { 2698 s32 ret_val; 2699 u16 phy_val; 2700 2701 if (hw->phy_configured) 2702 return 0; 2703 2704 /* Enable PHY */ 2705 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); 2706 ATL2_WRITE_FLUSH(hw); 2707 msleep(1); 2708 2709 /* check if the PHY is in powersaving mode */ 2710 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2711 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2712 2713 /* 024E / 124E 0r 0274 / 1274 ? */ 2714 if (phy_val & 0x1000) { 2715 phy_val &= ~0x1000; 2716 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); 2717 } 2718 2719 msleep(1); 2720 2721 /*Enable PHY LinkChange Interrupt */ 2722 ret_val = atl2_write_phy_reg(hw, 18, 0xC00); 2723 if (ret_val) 2724 return ret_val; 2725 2726 /* setup AutoNeg parameters */ 2727 ret_val = atl2_phy_setup_autoneg_adv(hw); 2728 if (ret_val) 2729 return ret_val; 2730 2731 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */ 2732 ret_val = atl2_phy_commit(hw); 2733 if (ret_val) 2734 return ret_val; 2735 2736 hw->phy_configured = true; 2737 2738 return ret_val; 2739 } 2740 2741 static void atl2_set_mac_addr(struct atl2_hw *hw) 2742 { 2743 u32 value; 2744 /* 00-0B-6A-F6-00-DC 2745 * 0: 6AF600DC 1: 000B 2746 * low dword */ 2747 value = (((u32)hw->mac_addr[2]) << 24) | 2748 (((u32)hw->mac_addr[3]) << 16) | 2749 (((u32)hw->mac_addr[4]) << 8) | 2750 (((u32)hw->mac_addr[5])); 2751 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); 2752 /* hight dword */ 2753 value = (((u32)hw->mac_addr[0]) << 8) | 2754 (((u32)hw->mac_addr[1])); 2755 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); 2756 } 2757 2758 /* 2759 * check_eeprom_exist 2760 * return 0 if eeprom exist 2761 */ 2762 static int atl2_check_eeprom_exist(struct atl2_hw *hw) 2763 { 2764 u32 value; 2765 2766 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2767 if (value & SPI_FLASH_CTRL_EN_VPD) { 2768 value &= ~SPI_FLASH_CTRL_EN_VPD; 2769 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2770 } 2771 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); 2772 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 2773 } 2774 2775 /* FIXME: This doesn't look right. -- CHS */ 2776 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) 2777 { 2778 return true; 2779 } 2780 2781 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) 2782 { 2783 int i; 2784 u32 Control; 2785 2786 if (Offset & 0x3) 2787 return false; /* address do not align */ 2788 2789 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); 2790 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 2791 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); 2792 2793 for (i = 0; i < 10; i++) { 2794 msleep(2); 2795 Control = ATL2_READ_REG(hw, REG_VPD_CAP); 2796 if (Control & VPD_CAP_VPD_FLAG) 2797 break; 2798 } 2799 2800 if (Control & VPD_CAP_VPD_FLAG) { 2801 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); 2802 return true; 2803 } 2804 return false; /* timeout */ 2805 } 2806 2807 static void atl2_force_ps(struct atl2_hw *hw) 2808 { 2809 u16 phy_val; 2810 2811 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2812 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2813 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); 2814 2815 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); 2816 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); 2817 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); 2818 atl2_write_phy_reg(hw, MII_DBG_DATA, 0); 2819 } 2820 2821 /* This is the only thing that needs to be changed to adjust the 2822 * maximum number of ports that the driver can manage. 2823 */ 2824 #define ATL2_MAX_NIC 4 2825 2826 #define OPTION_UNSET -1 2827 #define OPTION_DISABLED 0 2828 #define OPTION_ENABLED 1 2829 2830 /* All parameters are treated the same, as an integer array of values. 2831 * This macro just reduces the need to repeat the same declaration code 2832 * over and over (plus this helps to avoid typo bugs). 2833 */ 2834 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET} 2835 #ifndef module_param_array 2836 /* Module Parameters are always initialized to -1, so that the driver 2837 * can tell the difference between no user specified value or the 2838 * user asking for the default value. 2839 * The true default values are loaded in when atl2_check_options is called. 2840 * 2841 * This is a GCC extension to ANSI C. 2842 * See the item "Labeled Elements in Initializers" in the section 2843 * "Extensions to the C Language Family" of the GCC documentation. 2844 */ 2845 2846 #define ATL2_PARAM(X, desc) \ 2847 static const int X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \ 2848 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \ 2849 MODULE_PARM_DESC(X, desc); 2850 #else 2851 #define ATL2_PARAM(X, desc) \ 2852 static int X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \ 2853 static unsigned int num_##X; \ 2854 module_param_array_named(X, X, int, &num_##X, 0); \ 2855 MODULE_PARM_DESC(X, desc); 2856 #endif 2857 2858 /* 2859 * Transmit Memory Size 2860 * Valid Range: 64-2048 2861 * Default Value: 128 2862 */ 2863 #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */ 2864 #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */ 2865 #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */ 2866 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory"); 2867 2868 /* 2869 * Receive Memory Block Count 2870 * Valid Range: 16-512 2871 * Default Value: 128 2872 */ 2873 #define ATL2_MIN_RXD_COUNT 16 2874 #define ATL2_MAX_RXD_COUNT 512 2875 #define ATL2_DEFAULT_RXD_COUNT 64 2876 ATL2_PARAM(RxMemBlock, "Number of receive memory block"); 2877 2878 /* 2879 * User Specified MediaType Override 2880 * 2881 * Valid Range: 0-5 2882 * - 0 - auto-negotiate at all supported speeds 2883 * - 1 - only link at 1000Mbps Full Duplex 2884 * - 2 - only link at 100Mbps Full Duplex 2885 * - 3 - only link at 100Mbps Half Duplex 2886 * - 4 - only link at 10Mbps Full Duplex 2887 * - 5 - only link at 10Mbps Half Duplex 2888 * Default Value: 0 2889 */ 2890 ATL2_PARAM(MediaType, "MediaType Select"); 2891 2892 /* 2893 * Interrupt Moderate Timer in units of 2048 ns (~2 us) 2894 * Valid Range: 10-65535 2895 * Default Value: 45000(90ms) 2896 */ 2897 #define INT_MOD_DEFAULT_CNT 100 /* 200us */ 2898 #define INT_MOD_MAX_CNT 65000 2899 #define INT_MOD_MIN_CNT 50 2900 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer"); 2901 2902 /* 2903 * FlashVendor 2904 * Valid Range: 0-2 2905 * 0 - Atmel 2906 * 1 - SST 2907 * 2 - ST 2908 */ 2909 ATL2_PARAM(FlashVendor, "SPI Flash Vendor"); 2910 2911 #define AUTONEG_ADV_DEFAULT 0x2F 2912 #define AUTONEG_ADV_MASK 0x2F 2913 #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL 2914 2915 #define FLASH_VENDOR_DEFAULT 0 2916 #define FLASH_VENDOR_MIN 0 2917 #define FLASH_VENDOR_MAX 2 2918 2919 struct atl2_option { 2920 enum { enable_option, range_option, list_option } type; 2921 char *name; 2922 char *err; 2923 int def; 2924 union { 2925 struct { /* range_option info */ 2926 int min; 2927 int max; 2928 } r; 2929 struct { /* list_option info */ 2930 int nr; 2931 struct atl2_opt_list { int i; char *str; } *p; 2932 } l; 2933 } arg; 2934 }; 2935 2936 static int atl2_validate_option(int *value, struct atl2_option *opt) 2937 { 2938 int i; 2939 struct atl2_opt_list *ent; 2940 2941 if (*value == OPTION_UNSET) { 2942 *value = opt->def; 2943 return 0; 2944 } 2945 2946 switch (opt->type) { 2947 case enable_option: 2948 switch (*value) { 2949 case OPTION_ENABLED: 2950 printk(KERN_INFO "%s Enabled\n", opt->name); 2951 return 0; 2952 break; 2953 case OPTION_DISABLED: 2954 printk(KERN_INFO "%s Disabled\n", opt->name); 2955 return 0; 2956 break; 2957 } 2958 break; 2959 case range_option: 2960 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 2961 printk(KERN_INFO "%s set to %i\n", opt->name, *value); 2962 return 0; 2963 } 2964 break; 2965 case list_option: 2966 for (i = 0; i < opt->arg.l.nr; i++) { 2967 ent = &opt->arg.l.p[i]; 2968 if (*value == ent->i) { 2969 if (ent->str[0] != '\0') 2970 printk(KERN_INFO "%s\n", ent->str); 2971 return 0; 2972 } 2973 } 2974 break; 2975 default: 2976 BUG(); 2977 } 2978 2979 printk(KERN_INFO "Invalid %s specified (%i) %s\n", 2980 opt->name, *value, opt->err); 2981 *value = opt->def; 2982 return -1; 2983 } 2984 2985 /** 2986 * atl2_check_options - Range Checking for Command Line Parameters 2987 * @adapter: board private structure 2988 * 2989 * This routine checks all command line parameters for valid user 2990 * input. If an invalid value is given, or if no user specified 2991 * value exists, a default value is used. The final value is stored 2992 * in a variable in the adapter structure. 2993 */ 2994 static void atl2_check_options(struct atl2_adapter *adapter) 2995 { 2996 int val; 2997 struct atl2_option opt; 2998 int bd = adapter->bd_number; 2999 if (bd >= ATL2_MAX_NIC) { 3000 printk(KERN_NOTICE "Warning: no configuration for board #%i\n", 3001 bd); 3002 printk(KERN_NOTICE "Using defaults for all values\n"); 3003 #ifndef module_param_array 3004 bd = ATL2_MAX_NIC; 3005 #endif 3006 } 3007 3008 /* Bytes of Transmit Memory */ 3009 opt.type = range_option; 3010 opt.name = "Bytes of Transmit Memory"; 3011 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE); 3012 opt.def = ATL2_DEFAULT_TX_MEMSIZE; 3013 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE; 3014 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE; 3015 #ifdef module_param_array 3016 if (num_TxMemSize > bd) { 3017 #endif 3018 val = TxMemSize[bd]; 3019 atl2_validate_option(&val, &opt); 3020 adapter->txd_ring_size = ((u32) val) * 1024; 3021 #ifdef module_param_array 3022 } else 3023 adapter->txd_ring_size = ((u32)opt.def) * 1024; 3024 #endif 3025 /* txs ring size: */ 3026 adapter->txs_ring_size = adapter->txd_ring_size / 128; 3027 if (adapter->txs_ring_size > 160) 3028 adapter->txs_ring_size = 160; 3029 3030 /* Receive Memory Block Count */ 3031 opt.type = range_option; 3032 opt.name = "Number of receive memory block"; 3033 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT); 3034 opt.def = ATL2_DEFAULT_RXD_COUNT; 3035 opt.arg.r.min = ATL2_MIN_RXD_COUNT; 3036 opt.arg.r.max = ATL2_MAX_RXD_COUNT; 3037 #ifdef module_param_array 3038 if (num_RxMemBlock > bd) { 3039 #endif 3040 val = RxMemBlock[bd]; 3041 atl2_validate_option(&val, &opt); 3042 adapter->rxd_ring_size = (u32)val; 3043 /* FIXME */ 3044 /* ((u16)val)&~1; */ /* even number */ 3045 #ifdef module_param_array 3046 } else 3047 adapter->rxd_ring_size = (u32)opt.def; 3048 #endif 3049 /* init RXD Flow control value */ 3050 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7; 3051 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) > 3052 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) : 3053 (adapter->rxd_ring_size / 12); 3054 3055 /* Interrupt Moderate Timer */ 3056 opt.type = range_option; 3057 opt.name = "Interrupt Moderate Timer"; 3058 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT); 3059 opt.def = INT_MOD_DEFAULT_CNT; 3060 opt.arg.r.min = INT_MOD_MIN_CNT; 3061 opt.arg.r.max = INT_MOD_MAX_CNT; 3062 #ifdef module_param_array 3063 if (num_IntModTimer > bd) { 3064 #endif 3065 val = IntModTimer[bd]; 3066 atl2_validate_option(&val, &opt); 3067 adapter->imt = (u16) val; 3068 #ifdef module_param_array 3069 } else 3070 adapter->imt = (u16)(opt.def); 3071 #endif 3072 /* Flash Vendor */ 3073 opt.type = range_option; 3074 opt.name = "SPI Flash Vendor"; 3075 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT); 3076 opt.def = FLASH_VENDOR_DEFAULT; 3077 opt.arg.r.min = FLASH_VENDOR_MIN; 3078 opt.arg.r.max = FLASH_VENDOR_MAX; 3079 #ifdef module_param_array 3080 if (num_FlashVendor > bd) { 3081 #endif 3082 val = FlashVendor[bd]; 3083 atl2_validate_option(&val, &opt); 3084 adapter->hw.flash_vendor = (u8) val; 3085 #ifdef module_param_array 3086 } else 3087 adapter->hw.flash_vendor = (u8)(opt.def); 3088 #endif 3089 /* MediaType */ 3090 opt.type = range_option; 3091 opt.name = "Speed/Duplex Selection"; 3092 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR); 3093 opt.def = MEDIA_TYPE_AUTO_SENSOR; 3094 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR; 3095 opt.arg.r.max = MEDIA_TYPE_10M_HALF; 3096 #ifdef module_param_array 3097 if (num_MediaType > bd) { 3098 #endif 3099 val = MediaType[bd]; 3100 atl2_validate_option(&val, &opt); 3101 adapter->hw.MediaType = (u16) val; 3102 #ifdef module_param_array 3103 } else 3104 adapter->hw.MediaType = (u16)(opt.def); 3105 #endif 3106 } 3107