1 /* 2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved. 3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com> 4 * 5 * Derived from Intel e1000 driver 6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the Free 10 * Software Foundation; either version 2 of the License, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program; if not, write to the Free Software Foundation, Inc., 59 20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 21 */ 22 23 #include <linux/atomic.h> 24 #include <linux/crc32.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/hardirq.h> 29 #include <linux/if_vlan.h> 30 #include <linux/in.h> 31 #include <linux/interrupt.h> 32 #include <linux/ip.h> 33 #include <linux/irqflags.h> 34 #include <linux/irqreturn.h> 35 #include <linux/mii.h> 36 #include <linux/net.h> 37 #include <linux/netdevice.h> 38 #include <linux/pci.h> 39 #include <linux/pci_ids.h> 40 #include <linux/pm.h> 41 #include <linux/skbuff.h> 42 #include <linux/slab.h> 43 #include <linux/spinlock.h> 44 #include <linux/string.h> 45 #include <linux/tcp.h> 46 #include <linux/timer.h> 47 #include <linux/types.h> 48 #include <linux/workqueue.h> 49 50 #include "atl2.h" 51 52 #define ATL2_DRV_VERSION "2.2.3" 53 54 static const char atl2_driver_name[] = "atl2"; 55 static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver"; 56 static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation."; 57 static const char atl2_driver_version[] = ATL2_DRV_VERSION; 58 static const struct ethtool_ops atl2_ethtool_ops; 59 60 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>"); 61 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver"); 62 MODULE_LICENSE("GPL"); 63 MODULE_VERSION(ATL2_DRV_VERSION); 64 65 /* 66 * atl2_pci_tbl - PCI Device ID Table 67 */ 68 static const struct pci_device_id atl2_pci_tbl[] = { 69 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)}, 70 /* required last entry */ 71 {0,} 72 }; 73 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl); 74 75 static void atl2_check_options(struct atl2_adapter *adapter); 76 77 /** 78 * atl2_sw_init - Initialize general software structures (struct atl2_adapter) 79 * @adapter: board private structure to initialize 80 * 81 * atl2_sw_init initializes the Adapter private data structure. 82 * Fields are initialized based on PCI device information and 83 * OS network device settings (MTU size). 84 */ 85 static int atl2_sw_init(struct atl2_adapter *adapter) 86 { 87 struct atl2_hw *hw = &adapter->hw; 88 struct pci_dev *pdev = adapter->pdev; 89 90 /* PCI config space info */ 91 hw->vendor_id = pdev->vendor; 92 hw->device_id = pdev->device; 93 hw->subsystem_vendor_id = pdev->subsystem_vendor; 94 hw->subsystem_id = pdev->subsystem_device; 95 hw->revision_id = pdev->revision; 96 97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 98 99 adapter->wol = 0; 100 adapter->ict = 50000; /* ~100ms */ 101 adapter->link_speed = SPEED_0; /* hardware init */ 102 adapter->link_duplex = FULL_DUPLEX; 103 104 hw->phy_configured = false; 105 hw->preamble_len = 7; 106 hw->ipgt = 0x60; 107 hw->min_ifg = 0x50; 108 hw->ipgr1 = 0x40; 109 hw->ipgr2 = 0x60; 110 hw->retry_buf = 2; 111 hw->max_retry = 0xf; 112 hw->lcol = 0x37; 113 hw->jam_ipg = 7; 114 hw->fc_rxd_hi = 0; 115 hw->fc_rxd_lo = 0; 116 hw->max_frame_size = adapter->netdev->mtu; 117 118 spin_lock_init(&adapter->stats_lock); 119 120 set_bit(__ATL2_DOWN, &adapter->flags); 121 122 return 0; 123 } 124 125 /** 126 * atl2_set_multi - Multicast and Promiscuous mode set 127 * @netdev: network interface device structure 128 * 129 * The set_multi entry point is called whenever the multicast address 130 * list or the network interface flags are updated. This routine is 131 * responsible for configuring the hardware for proper multicast, 132 * promiscuous mode, and all-multi behavior. 133 */ 134 static void atl2_set_multi(struct net_device *netdev) 135 { 136 struct atl2_adapter *adapter = netdev_priv(netdev); 137 struct atl2_hw *hw = &adapter->hw; 138 struct netdev_hw_addr *ha; 139 u32 rctl; 140 u32 hash_value; 141 142 /* Check for Promiscuous and All Multicast modes */ 143 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); 144 145 if (netdev->flags & IFF_PROMISC) { 146 rctl |= MAC_CTRL_PROMIS_EN; 147 } else if (netdev->flags & IFF_ALLMULTI) { 148 rctl |= MAC_CTRL_MC_ALL_EN; 149 rctl &= ~MAC_CTRL_PROMIS_EN; 150 } else 151 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); 152 153 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); 154 155 /* clear the old settings from the multicast hash table */ 156 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 157 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 158 159 /* comoute mc addresses' hash value ,and put it into hash table */ 160 netdev_for_each_mc_addr(ha, netdev) { 161 hash_value = atl2_hash_mc_addr(hw, ha->addr); 162 atl2_hash_set(hw, hash_value); 163 } 164 } 165 166 static void init_ring_ptrs(struct atl2_adapter *adapter) 167 { 168 /* Read / Write Ptr Initialize: */ 169 adapter->txd_write_ptr = 0; 170 atomic_set(&adapter->txd_read_ptr, 0); 171 172 adapter->rxd_read_ptr = 0; 173 adapter->rxd_write_ptr = 0; 174 175 atomic_set(&adapter->txs_write_ptr, 0); 176 adapter->txs_next_clear = 0; 177 } 178 179 /** 180 * atl2_configure - Configure Transmit&Receive Unit after Reset 181 * @adapter: board private structure 182 * 183 * Configure the Tx /Rx unit of the MAC after a reset. 184 */ 185 static int atl2_configure(struct atl2_adapter *adapter) 186 { 187 struct atl2_hw *hw = &adapter->hw; 188 u32 value; 189 190 /* clear interrupt status */ 191 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); 192 193 /* set MAC Address */ 194 value = (((u32)hw->mac_addr[2]) << 24) | 195 (((u32)hw->mac_addr[3]) << 16) | 196 (((u32)hw->mac_addr[4]) << 8) | 197 (((u32)hw->mac_addr[5])); 198 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); 199 value = (((u32)hw->mac_addr[0]) << 8) | 200 (((u32)hw->mac_addr[1])); 201 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); 202 203 /* HI base address */ 204 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 205 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32)); 206 207 /* LO base address */ 208 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, 209 (u32)(adapter->txd_dma & 0x00000000ffffffffULL)); 210 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, 211 (u32)(adapter->txs_dma & 0x00000000ffffffffULL)); 212 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, 213 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL)); 214 215 /* element count */ 216 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); 217 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); 218 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); 219 220 /* config Internal SRAM */ 221 /* 222 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); 223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); 224 */ 225 226 /* config IPG/IFG */ 227 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << 228 MAC_IPG_IFG_IPGT_SHIFT) | 229 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << 230 MAC_IPG_IFG_MIFG_SHIFT) | 231 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << 232 MAC_IPG_IFG_IPGR1_SHIFT)| 233 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << 234 MAC_IPG_IFG_IPGR2_SHIFT); 235 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); 236 237 /* config Half-Duplex Control */ 238 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | 239 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << 240 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | 241 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | 242 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | 243 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << 244 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); 245 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); 246 247 /* set Interrupt Moderator Timer */ 248 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); 249 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); 250 251 /* set Interrupt Clear Timer */ 252 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); 253 254 /* set MTU */ 255 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + 256 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE); 257 258 /* 1590 */ 259 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); 260 261 /* flow control */ 262 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); 263 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); 264 265 /* Init mailbox */ 266 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); 267 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); 268 269 /* enable DMA read/write */ 270 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); 271 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); 272 273 value = ATL2_READ_REG(&adapter->hw, REG_ISR); 274 if ((value & ISR_PHY_LINKDOWN) != 0) 275 value = 1; /* config failed */ 276 else 277 value = 0; 278 279 /* clear all interrupt status */ 280 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); 281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 282 return value; 283 } 284 285 /** 286 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources 287 * @adapter: board private structure 288 * 289 * Return 0 on success, negative on failure 290 */ 291 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter) 292 { 293 struct pci_dev *pdev = adapter->pdev; 294 int size; 295 u8 offset = 0; 296 297 /* real ring DMA buffer */ 298 adapter->ring_size = size = 299 adapter->txd_ring_size * 1 + 7 + /* dword align */ 300 adapter->txs_ring_size * 4 + 7 + /* dword align */ 301 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */ 302 303 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size, 304 &adapter->ring_dma); 305 if (!adapter->ring_vir_addr) 306 return -ENOMEM; 307 memset(adapter->ring_vir_addr, 0, adapter->ring_size); 308 309 /* Init TXD Ring */ 310 adapter->txd_dma = adapter->ring_dma ; 311 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0; 312 adapter->txd_dma += offset; 313 adapter->txd_ring = adapter->ring_vir_addr + offset; 314 315 /* Init TXS Ring */ 316 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size; 317 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0; 318 adapter->txs_dma += offset; 319 adapter->txs_ring = (struct tx_pkt_status *) 320 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset)); 321 322 /* Init RXD Ring */ 323 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4; 324 offset = (adapter->rxd_dma & 127) ? 325 (128 - (adapter->rxd_dma & 127)) : 0; 326 if (offset > 7) 327 offset -= 8; 328 else 329 offset += (128 - 8); 330 331 adapter->rxd_dma += offset; 332 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) + 333 (adapter->txs_ring_size * 4 + offset)); 334 335 /* 336 * Read / Write Ptr Initialize: 337 * init_ring_ptrs(adapter); 338 */ 339 return 0; 340 } 341 342 /** 343 * atl2_irq_enable - Enable default interrupt generation settings 344 * @adapter: board private structure 345 */ 346 static inline void atl2_irq_enable(struct atl2_adapter *adapter) 347 { 348 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); 349 ATL2_WRITE_FLUSH(&adapter->hw); 350 } 351 352 /** 353 * atl2_irq_disable - Mask off interrupt generation on the NIC 354 * @adapter: board private structure 355 */ 356 static inline void atl2_irq_disable(struct atl2_adapter *adapter) 357 { 358 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); 359 ATL2_WRITE_FLUSH(&adapter->hw); 360 synchronize_irq(adapter->pdev->irq); 361 } 362 363 static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl) 364 { 365 if (features & NETIF_F_HW_VLAN_CTAG_RX) { 366 /* enable VLAN tag insert/strip */ 367 *ctrl |= MAC_CTRL_RMV_VLAN; 368 } else { 369 /* disable VLAN tag insert/strip */ 370 *ctrl &= ~MAC_CTRL_RMV_VLAN; 371 } 372 } 373 374 static void atl2_vlan_mode(struct net_device *netdev, 375 netdev_features_t features) 376 { 377 struct atl2_adapter *adapter = netdev_priv(netdev); 378 u32 ctrl; 379 380 atl2_irq_disable(adapter); 381 382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); 383 __atl2_vlan_mode(features, &ctrl); 384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); 385 386 atl2_irq_enable(adapter); 387 } 388 389 static void atl2_restore_vlan(struct atl2_adapter *adapter) 390 { 391 atl2_vlan_mode(adapter->netdev, adapter->netdev->features); 392 } 393 394 static netdev_features_t atl2_fix_features(struct net_device *netdev, 395 netdev_features_t features) 396 { 397 /* 398 * Since there is no support for separate rx/tx vlan accel 399 * enable/disable make sure tx flag is always in same state as rx. 400 */ 401 if (features & NETIF_F_HW_VLAN_CTAG_RX) 402 features |= NETIF_F_HW_VLAN_CTAG_TX; 403 else 404 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 405 406 return features; 407 } 408 409 static int atl2_set_features(struct net_device *netdev, 410 netdev_features_t features) 411 { 412 netdev_features_t changed = netdev->features ^ features; 413 414 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 415 atl2_vlan_mode(netdev, features); 416 417 return 0; 418 } 419 420 static void atl2_intr_rx(struct atl2_adapter *adapter) 421 { 422 struct net_device *netdev = adapter->netdev; 423 struct rx_desc *rxd; 424 struct sk_buff *skb; 425 426 do { 427 rxd = adapter->rxd_ring+adapter->rxd_write_ptr; 428 if (!rxd->status.update) 429 break; /* end of tx */ 430 431 /* clear this flag at once */ 432 rxd->status.update = 0; 433 434 if (rxd->status.ok && rxd->status.pkt_size >= 60) { 435 int rx_size = (int)(rxd->status.pkt_size - 4); 436 /* alloc new buffer */ 437 skb = netdev_alloc_skb_ip_align(netdev, rx_size); 438 if (NULL == skb) { 439 /* 440 * Check that some rx space is free. If not, 441 * free one and mark stats->rx_dropped++. 442 */ 443 netdev->stats.rx_dropped++; 444 break; 445 } 446 memcpy(skb->data, rxd->packet, rx_size); 447 skb_put(skb, rx_size); 448 skb->protocol = eth_type_trans(skb, netdev); 449 if (rxd->status.vlan) { 450 u16 vlan_tag = (rxd->status.vtag>>4) | 451 ((rxd->status.vtag&7) << 13) | 452 ((rxd->status.vtag&8) << 9); 453 454 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 455 } 456 netif_rx(skb); 457 netdev->stats.rx_bytes += rx_size; 458 netdev->stats.rx_packets++; 459 } else { 460 netdev->stats.rx_errors++; 461 462 if (rxd->status.ok && rxd->status.pkt_size <= 60) 463 netdev->stats.rx_length_errors++; 464 if (rxd->status.mcast) 465 netdev->stats.multicast++; 466 if (rxd->status.crc) 467 netdev->stats.rx_crc_errors++; 468 if (rxd->status.align) 469 netdev->stats.rx_frame_errors++; 470 } 471 472 /* advance write ptr */ 473 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size) 474 adapter->rxd_write_ptr = 0; 475 } while (1); 476 477 /* update mailbox? */ 478 adapter->rxd_read_ptr = adapter->rxd_write_ptr; 479 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); 480 } 481 482 static void atl2_intr_tx(struct atl2_adapter *adapter) 483 { 484 struct net_device *netdev = adapter->netdev; 485 u32 txd_read_ptr; 486 u32 txs_write_ptr; 487 struct tx_pkt_status *txs; 488 struct tx_pkt_header *txph; 489 int free_hole = 0; 490 491 do { 492 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 493 txs = adapter->txs_ring + txs_write_ptr; 494 if (!txs->update) 495 break; /* tx stop here */ 496 497 free_hole = 1; 498 txs->update = 0; 499 500 if (++txs_write_ptr == adapter->txs_ring_size) 501 txs_write_ptr = 0; 502 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr); 503 504 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr); 505 txph = (struct tx_pkt_header *) 506 (((u8 *)adapter->txd_ring) + txd_read_ptr); 507 508 if (txph->pkt_size != txs->pkt_size) { 509 struct tx_pkt_status *old_txs = txs; 510 printk(KERN_WARNING 511 "%s: txs packet size not consistent with txd" 512 " txd_:0x%08x, txs_:0x%08x!\n", 513 adapter->netdev->name, 514 *(u32 *)txph, *(u32 *)txs); 515 printk(KERN_WARNING 516 "txd read ptr: 0x%x\n", 517 txd_read_ptr); 518 txs = adapter->txs_ring + txs_write_ptr; 519 printk(KERN_WARNING 520 "txs-behind:0x%08x\n", 521 *(u32 *)txs); 522 if (txs_write_ptr < 2) { 523 txs = adapter->txs_ring + 524 (adapter->txs_ring_size + 525 txs_write_ptr - 2); 526 } else { 527 txs = adapter->txs_ring + (txs_write_ptr - 2); 528 } 529 printk(KERN_WARNING 530 "txs-before:0x%08x\n", 531 *(u32 *)txs); 532 txs = old_txs; 533 } 534 535 /* 4for TPH */ 536 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3); 537 if (txd_read_ptr >= adapter->txd_ring_size) 538 txd_read_ptr -= adapter->txd_ring_size; 539 540 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr); 541 542 /* tx statistics: */ 543 if (txs->ok) { 544 netdev->stats.tx_bytes += txs->pkt_size; 545 netdev->stats.tx_packets++; 546 } 547 else 548 netdev->stats.tx_errors++; 549 550 if (txs->defer) 551 netdev->stats.collisions++; 552 if (txs->abort_col) 553 netdev->stats.tx_aborted_errors++; 554 if (txs->late_col) 555 netdev->stats.tx_window_errors++; 556 if (txs->underun) 557 netdev->stats.tx_fifo_errors++; 558 } while (1); 559 560 if (free_hole) { 561 if (netif_queue_stopped(adapter->netdev) && 562 netif_carrier_ok(adapter->netdev)) 563 netif_wake_queue(adapter->netdev); 564 } 565 } 566 567 static void atl2_check_for_link(struct atl2_adapter *adapter) 568 { 569 struct net_device *netdev = adapter->netdev; 570 u16 phy_data = 0; 571 572 spin_lock(&adapter->stats_lock); 573 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 574 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 575 spin_unlock(&adapter->stats_lock); 576 577 /* notify upper layer link down ASAP */ 578 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */ 579 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 580 printk(KERN_INFO "%s: %s NIC Link is Down\n", 581 atl2_driver_name, netdev->name); 582 adapter->link_speed = SPEED_0; 583 netif_carrier_off(netdev); 584 netif_stop_queue(netdev); 585 } 586 } 587 schedule_work(&adapter->link_chg_task); 588 } 589 590 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter) 591 { 592 u16 phy_data; 593 spin_lock(&adapter->stats_lock); 594 atl2_read_phy_reg(&adapter->hw, 19, &phy_data); 595 spin_unlock(&adapter->stats_lock); 596 } 597 598 /** 599 * atl2_intr - Interrupt Handler 600 * @irq: interrupt number 601 * @data: pointer to a network interface device structure 602 */ 603 static irqreturn_t atl2_intr(int irq, void *data) 604 { 605 struct atl2_adapter *adapter = netdev_priv(data); 606 struct atl2_hw *hw = &adapter->hw; 607 u32 status; 608 609 status = ATL2_READ_REG(hw, REG_ISR); 610 if (0 == status) 611 return IRQ_NONE; 612 613 /* link event */ 614 if (status & ISR_PHY) 615 atl2_clear_phy_int(adapter); 616 617 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 618 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); 619 620 /* check if PCIE PHY Link down */ 621 if (status & ISR_PHY_LINKDOWN) { 622 if (netif_running(adapter->netdev)) { /* reset MAC */ 623 ATL2_WRITE_REG(hw, REG_ISR, 0); 624 ATL2_WRITE_REG(hw, REG_IMR, 0); 625 ATL2_WRITE_FLUSH(hw); 626 schedule_work(&adapter->reset_task); 627 return IRQ_HANDLED; 628 } 629 } 630 631 /* check if DMA read/write error? */ 632 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 633 ATL2_WRITE_REG(hw, REG_ISR, 0); 634 ATL2_WRITE_REG(hw, REG_IMR, 0); 635 ATL2_WRITE_FLUSH(hw); 636 schedule_work(&adapter->reset_task); 637 return IRQ_HANDLED; 638 } 639 640 /* link event */ 641 if (status & (ISR_PHY | ISR_MANUAL)) { 642 adapter->netdev->stats.tx_carrier_errors++; 643 atl2_check_for_link(adapter); 644 } 645 646 /* transmit event */ 647 if (status & ISR_TX_EVENT) 648 atl2_intr_tx(adapter); 649 650 /* rx exception */ 651 if (status & ISR_RX_EVENT) 652 atl2_intr_rx(adapter); 653 654 /* re-enable Interrupt */ 655 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 656 return IRQ_HANDLED; 657 } 658 659 static int atl2_request_irq(struct atl2_adapter *adapter) 660 { 661 struct net_device *netdev = adapter->netdev; 662 int flags, err = 0; 663 664 flags = IRQF_SHARED; 665 adapter->have_msi = true; 666 err = pci_enable_msi(adapter->pdev); 667 if (err) 668 adapter->have_msi = false; 669 670 if (adapter->have_msi) 671 flags &= ~IRQF_SHARED; 672 673 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name, 674 netdev); 675 } 676 677 /** 678 * atl2_free_ring_resources - Free Tx / RX descriptor Resources 679 * @adapter: board private structure 680 * 681 * Free all transmit software resources 682 */ 683 static void atl2_free_ring_resources(struct atl2_adapter *adapter) 684 { 685 struct pci_dev *pdev = adapter->pdev; 686 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, 687 adapter->ring_dma); 688 } 689 690 /** 691 * atl2_open - Called when a network interface is made active 692 * @netdev: network interface device structure 693 * 694 * Returns 0 on success, negative value on failure 695 * 696 * The open entry point is called when a network interface is made 697 * active by the system (IFF_UP). At this point all resources needed 698 * for transmit and receive operations are allocated, the interrupt 699 * handler is registered with the OS, the watchdog timer is started, 700 * and the stack is notified that the interface is ready. 701 */ 702 static int atl2_open(struct net_device *netdev) 703 { 704 struct atl2_adapter *adapter = netdev_priv(netdev); 705 int err; 706 u32 val; 707 708 /* disallow open during test */ 709 if (test_bit(__ATL2_TESTING, &adapter->flags)) 710 return -EBUSY; 711 712 /* allocate transmit descriptors */ 713 err = atl2_setup_ring_resources(adapter); 714 if (err) 715 return err; 716 717 err = atl2_init_hw(&adapter->hw); 718 if (err) { 719 err = -EIO; 720 goto err_init_hw; 721 } 722 723 /* hardware has been reset, we need to reload some things */ 724 atl2_set_multi(netdev); 725 init_ring_ptrs(adapter); 726 727 atl2_restore_vlan(adapter); 728 729 if (atl2_configure(adapter)) { 730 err = -EIO; 731 goto err_config; 732 } 733 734 err = atl2_request_irq(adapter); 735 if (err) 736 goto err_req_irq; 737 738 clear_bit(__ATL2_DOWN, &adapter->flags); 739 740 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ)); 741 742 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 743 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, 744 val | MASTER_CTRL_MANUAL_INT); 745 746 atl2_irq_enable(adapter); 747 748 return 0; 749 750 err_init_hw: 751 err_req_irq: 752 err_config: 753 atl2_free_ring_resources(adapter); 754 atl2_reset_hw(&adapter->hw); 755 756 return err; 757 } 758 759 static void atl2_down(struct atl2_adapter *adapter) 760 { 761 struct net_device *netdev = adapter->netdev; 762 763 /* signal that we're down so the interrupt handler does not 764 * reschedule our watchdog timer */ 765 set_bit(__ATL2_DOWN, &adapter->flags); 766 767 netif_tx_disable(netdev); 768 769 /* reset MAC to disable all RX/TX */ 770 atl2_reset_hw(&adapter->hw); 771 msleep(1); 772 773 atl2_irq_disable(adapter); 774 775 del_timer_sync(&adapter->watchdog_timer); 776 del_timer_sync(&adapter->phy_config_timer); 777 clear_bit(0, &adapter->cfg_phy); 778 779 netif_carrier_off(netdev); 780 adapter->link_speed = SPEED_0; 781 adapter->link_duplex = -1; 782 } 783 784 static void atl2_free_irq(struct atl2_adapter *adapter) 785 { 786 struct net_device *netdev = adapter->netdev; 787 788 free_irq(adapter->pdev->irq, netdev); 789 790 #ifdef CONFIG_PCI_MSI 791 if (adapter->have_msi) 792 pci_disable_msi(adapter->pdev); 793 #endif 794 } 795 796 /** 797 * atl2_close - Disables a network interface 798 * @netdev: network interface device structure 799 * 800 * Returns 0, this is not allowed to fail 801 * 802 * The close entry point is called when an interface is de-activated 803 * by the OS. The hardware is still under the drivers control, but 804 * needs to be disabled. A global MAC reset is issued to stop the 805 * hardware, and all transmit and receive resources are freed. 806 */ 807 static int atl2_close(struct net_device *netdev) 808 { 809 struct atl2_adapter *adapter = netdev_priv(netdev); 810 811 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 812 813 atl2_down(adapter); 814 atl2_free_irq(adapter); 815 atl2_free_ring_resources(adapter); 816 817 return 0; 818 } 819 820 static inline int TxsFreeUnit(struct atl2_adapter *adapter) 821 { 822 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 823 824 return (adapter->txs_next_clear >= txs_write_ptr) ? 825 (int) (adapter->txs_ring_size - adapter->txs_next_clear + 826 txs_write_ptr - 1) : 827 (int) (txs_write_ptr - adapter->txs_next_clear - 1); 828 } 829 830 static inline int TxdFreeBytes(struct atl2_adapter *adapter) 831 { 832 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr); 833 834 return (adapter->txd_write_ptr >= txd_read_ptr) ? 835 (int) (adapter->txd_ring_size - adapter->txd_write_ptr + 836 txd_read_ptr - 1) : 837 (int) (txd_read_ptr - adapter->txd_write_ptr - 1); 838 } 839 840 static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb, 841 struct net_device *netdev) 842 { 843 struct atl2_adapter *adapter = netdev_priv(netdev); 844 struct tx_pkt_header *txph; 845 u32 offset, copy_len; 846 int txs_unused; 847 int txbuf_unused; 848 849 if (test_bit(__ATL2_DOWN, &adapter->flags)) { 850 dev_kfree_skb_any(skb); 851 return NETDEV_TX_OK; 852 } 853 854 if (unlikely(skb->len <= 0)) { 855 dev_kfree_skb_any(skb); 856 return NETDEV_TX_OK; 857 } 858 859 txs_unused = TxsFreeUnit(adapter); 860 txbuf_unused = TxdFreeBytes(adapter); 861 862 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused || 863 txs_unused < 1) { 864 /* not enough resources */ 865 netif_stop_queue(netdev); 866 return NETDEV_TX_BUSY; 867 } 868 869 offset = adapter->txd_write_ptr; 870 871 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset); 872 873 *(u32 *)txph = 0; 874 txph->pkt_size = skb->len; 875 876 offset += 4; 877 if (offset >= adapter->txd_ring_size) 878 offset -= adapter->txd_ring_size; 879 copy_len = adapter->txd_ring_size - offset; 880 if (copy_len >= skb->len) { 881 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len); 882 offset += ((u32)(skb->len + 3) & ~3); 883 } else { 884 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len); 885 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len, 886 skb->len-copy_len); 887 offset = ((u32)(skb->len-copy_len + 3) & ~3); 888 } 889 #ifdef NETIF_F_HW_VLAN_CTAG_TX 890 if (skb_vlan_tag_present(skb)) { 891 u16 vlan_tag = skb_vlan_tag_get(skb); 892 vlan_tag = (vlan_tag << 4) | 893 (vlan_tag >> 13) | 894 ((vlan_tag >> 9) & 0x8); 895 txph->ins_vlan = 1; 896 txph->vlan = vlan_tag; 897 } 898 #endif 899 if (offset >= adapter->txd_ring_size) 900 offset -= adapter->txd_ring_size; 901 adapter->txd_write_ptr = offset; 902 903 /* clear txs before send */ 904 adapter->txs_ring[adapter->txs_next_clear].update = 0; 905 if (++adapter->txs_next_clear == adapter->txs_ring_size) 906 adapter->txs_next_clear = 0; 907 908 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, 909 (adapter->txd_write_ptr >> 2)); 910 911 mmiowb(); 912 dev_kfree_skb_any(skb); 913 return NETDEV_TX_OK; 914 } 915 916 /** 917 * atl2_change_mtu - Change the Maximum Transfer Unit 918 * @netdev: network interface device structure 919 * @new_mtu: new value for maximum frame size 920 * 921 * Returns 0 on success, negative on failure 922 */ 923 static int atl2_change_mtu(struct net_device *netdev, int new_mtu) 924 { 925 struct atl2_adapter *adapter = netdev_priv(netdev); 926 struct atl2_hw *hw = &adapter->hw; 927 928 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE))) 929 return -EINVAL; 930 931 /* set MTU */ 932 if (hw->max_frame_size != new_mtu) { 933 netdev->mtu = new_mtu; 934 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE + 935 VLAN_SIZE + ETHERNET_FCS_SIZE); 936 } 937 938 return 0; 939 } 940 941 /** 942 * atl2_set_mac - Change the Ethernet Address of the NIC 943 * @netdev: network interface device structure 944 * @p: pointer to an address structure 945 * 946 * Returns 0 on success, negative on failure 947 */ 948 static int atl2_set_mac(struct net_device *netdev, void *p) 949 { 950 struct atl2_adapter *adapter = netdev_priv(netdev); 951 struct sockaddr *addr = p; 952 953 if (!is_valid_ether_addr(addr->sa_data)) 954 return -EADDRNOTAVAIL; 955 956 if (netif_running(netdev)) 957 return -EBUSY; 958 959 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 960 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); 961 962 atl2_set_mac_addr(&adapter->hw); 963 964 return 0; 965 } 966 967 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 968 { 969 struct atl2_adapter *adapter = netdev_priv(netdev); 970 struct mii_ioctl_data *data = if_mii(ifr); 971 unsigned long flags; 972 973 switch (cmd) { 974 case SIOCGMIIPHY: 975 data->phy_id = 0; 976 break; 977 case SIOCGMIIREG: 978 spin_lock_irqsave(&adapter->stats_lock, flags); 979 if (atl2_read_phy_reg(&adapter->hw, 980 data->reg_num & 0x1F, &data->val_out)) { 981 spin_unlock_irqrestore(&adapter->stats_lock, flags); 982 return -EIO; 983 } 984 spin_unlock_irqrestore(&adapter->stats_lock, flags); 985 break; 986 case SIOCSMIIREG: 987 if (data->reg_num & ~(0x1F)) 988 return -EFAULT; 989 spin_lock_irqsave(&adapter->stats_lock, flags); 990 if (atl2_write_phy_reg(&adapter->hw, data->reg_num, 991 data->val_in)) { 992 spin_unlock_irqrestore(&adapter->stats_lock, flags); 993 return -EIO; 994 } 995 spin_unlock_irqrestore(&adapter->stats_lock, flags); 996 break; 997 default: 998 return -EOPNOTSUPP; 999 } 1000 return 0; 1001 } 1002 1003 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1004 { 1005 switch (cmd) { 1006 case SIOCGMIIPHY: 1007 case SIOCGMIIREG: 1008 case SIOCSMIIREG: 1009 return atl2_mii_ioctl(netdev, ifr, cmd); 1010 #ifdef ETHTOOL_OPS_COMPAT 1011 case SIOCETHTOOL: 1012 return ethtool_ioctl(ifr); 1013 #endif 1014 default: 1015 return -EOPNOTSUPP; 1016 } 1017 } 1018 1019 /** 1020 * atl2_tx_timeout - Respond to a Tx Hang 1021 * @netdev: network interface device structure 1022 */ 1023 static void atl2_tx_timeout(struct net_device *netdev) 1024 { 1025 struct atl2_adapter *adapter = netdev_priv(netdev); 1026 1027 /* Do the reset outside of interrupt context */ 1028 schedule_work(&adapter->reset_task); 1029 } 1030 1031 /** 1032 * atl2_watchdog - Timer Call-back 1033 * @data: pointer to netdev cast into an unsigned long 1034 */ 1035 static void atl2_watchdog(unsigned long data) 1036 { 1037 struct atl2_adapter *adapter = (struct atl2_adapter *) data; 1038 1039 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1040 u32 drop_rxd, drop_rxs; 1041 unsigned long flags; 1042 1043 spin_lock_irqsave(&adapter->stats_lock, flags); 1044 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); 1045 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); 1046 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1047 1048 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs; 1049 1050 /* Reset the timer */ 1051 mod_timer(&adapter->watchdog_timer, 1052 round_jiffies(jiffies + 4 * HZ)); 1053 } 1054 } 1055 1056 /** 1057 * atl2_phy_config - Timer Call-back 1058 * @data: pointer to netdev cast into an unsigned long 1059 */ 1060 static void atl2_phy_config(unsigned long data) 1061 { 1062 struct atl2_adapter *adapter = (struct atl2_adapter *) data; 1063 struct atl2_hw *hw = &adapter->hw; 1064 unsigned long flags; 1065 1066 spin_lock_irqsave(&adapter->stats_lock, flags); 1067 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 1068 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN | 1069 MII_CR_RESTART_AUTO_NEG); 1070 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1071 clear_bit(0, &adapter->cfg_phy); 1072 } 1073 1074 static int atl2_up(struct atl2_adapter *adapter) 1075 { 1076 struct net_device *netdev = adapter->netdev; 1077 int err = 0; 1078 u32 val; 1079 1080 /* hardware has been reset, we need to reload some things */ 1081 1082 err = atl2_init_hw(&adapter->hw); 1083 if (err) { 1084 err = -EIO; 1085 return err; 1086 } 1087 1088 atl2_set_multi(netdev); 1089 init_ring_ptrs(adapter); 1090 1091 atl2_restore_vlan(adapter); 1092 1093 if (atl2_configure(adapter)) { 1094 err = -EIO; 1095 goto err_up; 1096 } 1097 1098 clear_bit(__ATL2_DOWN, &adapter->flags); 1099 1100 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 1101 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | 1102 MASTER_CTRL_MANUAL_INT); 1103 1104 atl2_irq_enable(adapter); 1105 1106 err_up: 1107 return err; 1108 } 1109 1110 static void atl2_reinit_locked(struct atl2_adapter *adapter) 1111 { 1112 WARN_ON(in_interrupt()); 1113 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1114 msleep(1); 1115 atl2_down(adapter); 1116 atl2_up(adapter); 1117 clear_bit(__ATL2_RESETTING, &adapter->flags); 1118 } 1119 1120 static void atl2_reset_task(struct work_struct *work) 1121 { 1122 struct atl2_adapter *adapter; 1123 adapter = container_of(work, struct atl2_adapter, reset_task); 1124 1125 atl2_reinit_locked(adapter); 1126 } 1127 1128 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter) 1129 { 1130 u32 value; 1131 struct atl2_hw *hw = &adapter->hw; 1132 struct net_device *netdev = adapter->netdev; 1133 1134 /* Config MAC CTRL Register */ 1135 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1136 1137 /* duplex */ 1138 if (FULL_DUPLEX == adapter->link_duplex) 1139 value |= MAC_CTRL_DUPLX; 1140 1141 /* flow control */ 1142 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 1143 1144 /* PAD & CRC */ 1145 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1146 1147 /* preamble length */ 1148 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << 1149 MAC_CTRL_PRMLEN_SHIFT); 1150 1151 /* vlan */ 1152 __atl2_vlan_mode(netdev->features, &value); 1153 1154 /* filter mode */ 1155 value |= MAC_CTRL_BC_EN; 1156 if (netdev->flags & IFF_PROMISC) 1157 value |= MAC_CTRL_PROMIS_EN; 1158 else if (netdev->flags & IFF_ALLMULTI) 1159 value |= MAC_CTRL_MC_ALL_EN; 1160 1161 /* half retry buffer */ 1162 value |= (((u32)(adapter->hw.retry_buf & 1163 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1164 1165 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1166 } 1167 1168 static int atl2_check_link(struct atl2_adapter *adapter) 1169 { 1170 struct atl2_hw *hw = &adapter->hw; 1171 struct net_device *netdev = adapter->netdev; 1172 int ret_val; 1173 u16 speed, duplex, phy_data; 1174 int reconfig = 0; 1175 1176 /* MII_BMSR must read twise */ 1177 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1178 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1179 if (!(phy_data&BMSR_LSTATUS)) { /* link down */ 1180 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 1181 u32 value; 1182 /* disable rx */ 1183 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1184 value &= ~MAC_CTRL_RX_EN; 1185 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1186 adapter->link_speed = SPEED_0; 1187 netif_carrier_off(netdev); 1188 netif_stop_queue(netdev); 1189 } 1190 return 0; 1191 } 1192 1193 /* Link Up */ 1194 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1195 if (ret_val) 1196 return ret_val; 1197 switch (hw->MediaType) { 1198 case MEDIA_TYPE_100M_FULL: 1199 if (speed != SPEED_100 || duplex != FULL_DUPLEX) 1200 reconfig = 1; 1201 break; 1202 case MEDIA_TYPE_100M_HALF: 1203 if (speed != SPEED_100 || duplex != HALF_DUPLEX) 1204 reconfig = 1; 1205 break; 1206 case MEDIA_TYPE_10M_FULL: 1207 if (speed != SPEED_10 || duplex != FULL_DUPLEX) 1208 reconfig = 1; 1209 break; 1210 case MEDIA_TYPE_10M_HALF: 1211 if (speed != SPEED_10 || duplex != HALF_DUPLEX) 1212 reconfig = 1; 1213 break; 1214 } 1215 /* link result is our setting */ 1216 if (reconfig == 0) { 1217 if (adapter->link_speed != speed || 1218 adapter->link_duplex != duplex) { 1219 adapter->link_speed = speed; 1220 adapter->link_duplex = duplex; 1221 atl2_setup_mac_ctrl(adapter); 1222 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n", 1223 atl2_driver_name, netdev->name, 1224 adapter->link_speed, 1225 adapter->link_duplex == FULL_DUPLEX ? 1226 "Full Duplex" : "Half Duplex"); 1227 } 1228 1229 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */ 1230 netif_carrier_on(netdev); 1231 netif_wake_queue(netdev); 1232 } 1233 return 0; 1234 } 1235 1236 /* change original link status */ 1237 if (netif_carrier_ok(netdev)) { 1238 u32 value; 1239 /* disable rx */ 1240 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1241 value &= ~MAC_CTRL_RX_EN; 1242 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1243 1244 adapter->link_speed = SPEED_0; 1245 netif_carrier_off(netdev); 1246 netif_stop_queue(netdev); 1247 } 1248 1249 /* auto-neg, insert timer to re-config phy 1250 * (if interval smaller than 5 seconds, something strange) */ 1251 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1252 if (!test_and_set_bit(0, &adapter->cfg_phy)) 1253 mod_timer(&adapter->phy_config_timer, 1254 round_jiffies(jiffies + 5 * HZ)); 1255 } 1256 1257 return 0; 1258 } 1259 1260 /** 1261 * atl2_link_chg_task - deal with link change event Out of interrupt context 1262 */ 1263 static void atl2_link_chg_task(struct work_struct *work) 1264 { 1265 struct atl2_adapter *adapter; 1266 unsigned long flags; 1267 1268 adapter = container_of(work, struct atl2_adapter, link_chg_task); 1269 1270 spin_lock_irqsave(&adapter->stats_lock, flags); 1271 atl2_check_link(adapter); 1272 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1273 } 1274 1275 static void atl2_setup_pcicmd(struct pci_dev *pdev) 1276 { 1277 u16 cmd; 1278 1279 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1280 1281 if (cmd & PCI_COMMAND_INTX_DISABLE) 1282 cmd &= ~PCI_COMMAND_INTX_DISABLE; 1283 if (cmd & PCI_COMMAND_IO) 1284 cmd &= ~PCI_COMMAND_IO; 1285 if (0 == (cmd & PCI_COMMAND_MEMORY)) 1286 cmd |= PCI_COMMAND_MEMORY; 1287 if (0 == (cmd & PCI_COMMAND_MASTER)) 1288 cmd |= PCI_COMMAND_MASTER; 1289 pci_write_config_word(pdev, PCI_COMMAND, cmd); 1290 1291 /* 1292 * some motherboards BIOS(PXE/EFI) driver may set PME 1293 * while they transfer control to OS (Windows/Linux) 1294 * so we should clear this bit before NIC work normally 1295 */ 1296 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); 1297 } 1298 1299 #ifdef CONFIG_NET_POLL_CONTROLLER 1300 static void atl2_poll_controller(struct net_device *netdev) 1301 { 1302 disable_irq(netdev->irq); 1303 atl2_intr(netdev->irq, netdev); 1304 enable_irq(netdev->irq); 1305 } 1306 #endif 1307 1308 1309 static const struct net_device_ops atl2_netdev_ops = { 1310 .ndo_open = atl2_open, 1311 .ndo_stop = atl2_close, 1312 .ndo_start_xmit = atl2_xmit_frame, 1313 .ndo_set_rx_mode = atl2_set_multi, 1314 .ndo_validate_addr = eth_validate_addr, 1315 .ndo_set_mac_address = atl2_set_mac, 1316 .ndo_change_mtu = atl2_change_mtu, 1317 .ndo_fix_features = atl2_fix_features, 1318 .ndo_set_features = atl2_set_features, 1319 .ndo_do_ioctl = atl2_ioctl, 1320 .ndo_tx_timeout = atl2_tx_timeout, 1321 #ifdef CONFIG_NET_POLL_CONTROLLER 1322 .ndo_poll_controller = atl2_poll_controller, 1323 #endif 1324 }; 1325 1326 /** 1327 * atl2_probe - Device Initialization Routine 1328 * @pdev: PCI device information struct 1329 * @ent: entry in atl2_pci_tbl 1330 * 1331 * Returns 0 on success, negative on failure 1332 * 1333 * atl2_probe initializes an adapter identified by a pci_dev structure. 1334 * The OS initialization, configuring of the adapter private structure, 1335 * and a hardware reset occur. 1336 */ 1337 static int atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1338 { 1339 struct net_device *netdev; 1340 struct atl2_adapter *adapter; 1341 static int cards_found; 1342 unsigned long mmio_start; 1343 int mmio_len; 1344 int err; 1345 1346 cards_found = 0; 1347 1348 err = pci_enable_device(pdev); 1349 if (err) 1350 return err; 1351 1352 /* 1353 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA 1354 * until the kernel has the proper infrastructure to support 64-bit DMA 1355 * on these devices. 1356 */ 1357 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) && 1358 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 1359 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n"); 1360 goto err_dma; 1361 } 1362 1363 /* Mark all PCI regions associated with PCI device 1364 * pdev as being reserved by owner atl2_driver_name */ 1365 err = pci_request_regions(pdev, atl2_driver_name); 1366 if (err) 1367 goto err_pci_reg; 1368 1369 /* Enables bus-mastering on the device and calls 1370 * pcibios_set_master to do the needed arch specific settings */ 1371 pci_set_master(pdev); 1372 1373 err = -ENOMEM; 1374 netdev = alloc_etherdev(sizeof(struct atl2_adapter)); 1375 if (!netdev) 1376 goto err_alloc_etherdev; 1377 1378 SET_NETDEV_DEV(netdev, &pdev->dev); 1379 1380 pci_set_drvdata(pdev, netdev); 1381 adapter = netdev_priv(netdev); 1382 adapter->netdev = netdev; 1383 adapter->pdev = pdev; 1384 adapter->hw.back = adapter; 1385 1386 mmio_start = pci_resource_start(pdev, 0x0); 1387 mmio_len = pci_resource_len(pdev, 0x0); 1388 1389 adapter->hw.mem_rang = (u32)mmio_len; 1390 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 1391 if (!adapter->hw.hw_addr) { 1392 err = -EIO; 1393 goto err_ioremap; 1394 } 1395 1396 atl2_setup_pcicmd(pdev); 1397 1398 netdev->netdev_ops = &atl2_netdev_ops; 1399 netdev->ethtool_ops = &atl2_ethtool_ops; 1400 netdev->watchdog_timeo = 5 * HZ; 1401 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 1402 1403 netdev->mem_start = mmio_start; 1404 netdev->mem_end = mmio_start + mmio_len; 1405 adapter->bd_number = cards_found; 1406 adapter->pci_using_64 = false; 1407 1408 /* setup the private structure */ 1409 err = atl2_sw_init(adapter); 1410 if (err) 1411 goto err_sw_init; 1412 1413 err = -EIO; 1414 1415 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX; 1416 netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 1417 1418 /* Init PHY as early as possible due to power saving issue */ 1419 atl2_phy_init(&adapter->hw); 1420 1421 /* reset the controller to 1422 * put the device in a known good starting state */ 1423 1424 if (atl2_reset_hw(&adapter->hw)) { 1425 err = -EIO; 1426 goto err_reset; 1427 } 1428 1429 /* copy the MAC address out of the EEPROM */ 1430 atl2_read_mac_addr(&adapter->hw); 1431 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); 1432 if (!is_valid_ether_addr(netdev->dev_addr)) { 1433 err = -EIO; 1434 goto err_eeprom; 1435 } 1436 1437 atl2_check_options(adapter); 1438 1439 setup_timer(&adapter->watchdog_timer, atl2_watchdog, 1440 (unsigned long)adapter); 1441 1442 setup_timer(&adapter->phy_config_timer, atl2_phy_config, 1443 (unsigned long)adapter); 1444 1445 INIT_WORK(&adapter->reset_task, atl2_reset_task); 1446 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task); 1447 1448 strcpy(netdev->name, "eth%d"); /* ?? */ 1449 err = register_netdev(netdev); 1450 if (err) 1451 goto err_register; 1452 1453 /* assume we have no link for now */ 1454 netif_carrier_off(netdev); 1455 netif_stop_queue(netdev); 1456 1457 cards_found++; 1458 1459 return 0; 1460 1461 err_reset: 1462 err_register: 1463 err_sw_init: 1464 err_eeprom: 1465 iounmap(adapter->hw.hw_addr); 1466 err_ioremap: 1467 free_netdev(netdev); 1468 err_alloc_etherdev: 1469 pci_release_regions(pdev); 1470 err_pci_reg: 1471 err_dma: 1472 pci_disable_device(pdev); 1473 return err; 1474 } 1475 1476 /** 1477 * atl2_remove - Device Removal Routine 1478 * @pdev: PCI device information struct 1479 * 1480 * atl2_remove is called by the PCI subsystem to alert the driver 1481 * that it should release a PCI device. The could be caused by a 1482 * Hot-Plug event, or because the driver is going to be removed from 1483 * memory. 1484 */ 1485 /* FIXME: write the original MAC address back in case it was changed from a 1486 * BIOS-set value, as in atl1 -- CHS */ 1487 static void atl2_remove(struct pci_dev *pdev) 1488 { 1489 struct net_device *netdev = pci_get_drvdata(pdev); 1490 struct atl2_adapter *adapter = netdev_priv(netdev); 1491 1492 /* flush_scheduled work may reschedule our watchdog task, so 1493 * explicitly disable watchdog tasks from being rescheduled */ 1494 set_bit(__ATL2_DOWN, &adapter->flags); 1495 1496 del_timer_sync(&adapter->watchdog_timer); 1497 del_timer_sync(&adapter->phy_config_timer); 1498 cancel_work_sync(&adapter->reset_task); 1499 cancel_work_sync(&adapter->link_chg_task); 1500 1501 unregister_netdev(netdev); 1502 1503 atl2_force_ps(&adapter->hw); 1504 1505 iounmap(adapter->hw.hw_addr); 1506 pci_release_regions(pdev); 1507 1508 free_netdev(netdev); 1509 1510 pci_disable_device(pdev); 1511 } 1512 1513 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state) 1514 { 1515 struct net_device *netdev = pci_get_drvdata(pdev); 1516 struct atl2_adapter *adapter = netdev_priv(netdev); 1517 struct atl2_hw *hw = &adapter->hw; 1518 u16 speed, duplex; 1519 u32 ctrl = 0; 1520 u32 wufc = adapter->wol; 1521 1522 #ifdef CONFIG_PM 1523 int retval = 0; 1524 #endif 1525 1526 netif_device_detach(netdev); 1527 1528 if (netif_running(netdev)) { 1529 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 1530 atl2_down(adapter); 1531 } 1532 1533 #ifdef CONFIG_PM 1534 retval = pci_save_state(pdev); 1535 if (retval) 1536 return retval; 1537 #endif 1538 1539 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1540 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1541 if (ctrl & BMSR_LSTATUS) 1542 wufc &= ~ATLX_WUFC_LNKC; 1543 1544 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) { 1545 u32 ret_val; 1546 /* get current link speed & duplex */ 1547 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1548 if (ret_val) { 1549 printk(KERN_DEBUG 1550 "%s: get speed&duplex error while suspend\n", 1551 atl2_driver_name); 1552 goto wol_dis; 1553 } 1554 1555 ctrl = 0; 1556 1557 /* turn on magic packet wol */ 1558 if (wufc & ATLX_WUFC_MAG) 1559 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); 1560 1561 /* ignore Link Chg event when Link is up */ 1562 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1563 1564 /* Config MAC CTRL Register */ 1565 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1566 if (FULL_DUPLEX == adapter->link_duplex) 1567 ctrl |= MAC_CTRL_DUPLX; 1568 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1569 ctrl |= (((u32)adapter->hw.preamble_len & 1570 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 1571 ctrl |= (((u32)(adapter->hw.retry_buf & 1572 MAC_CTRL_HALF_LEFT_BUF_MASK)) << 1573 MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1574 if (wufc & ATLX_WUFC_MAG) { 1575 /* magic packet maybe Broadcast&multicast&Unicast */ 1576 ctrl |= MAC_CTRL_BC_EN; 1577 } 1578 1579 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); 1580 1581 /* pcie patch */ 1582 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1583 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1584 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1585 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1586 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1587 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1588 1589 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1590 goto suspend_exit; 1591 } 1592 1593 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) { 1594 /* link is down, so only LINK CHG WOL event enable */ 1595 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 1596 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1597 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); 1598 1599 /* pcie patch */ 1600 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1601 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1602 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1603 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1604 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1605 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1606 1607 hw->phy_configured = false; /* re-init PHY when resume */ 1608 1609 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1610 1611 goto suspend_exit; 1612 } 1613 1614 wol_dis: 1615 /* WOL disabled */ 1616 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); 1617 1618 /* pcie patch */ 1619 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1620 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1621 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1622 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1623 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1624 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1625 1626 atl2_force_ps(hw); 1627 hw->phy_configured = false; /* re-init PHY when resume */ 1628 1629 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1630 1631 suspend_exit: 1632 if (netif_running(netdev)) 1633 atl2_free_irq(adapter); 1634 1635 pci_disable_device(pdev); 1636 1637 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1638 1639 return 0; 1640 } 1641 1642 #ifdef CONFIG_PM 1643 static int atl2_resume(struct pci_dev *pdev) 1644 { 1645 struct net_device *netdev = pci_get_drvdata(pdev); 1646 struct atl2_adapter *adapter = netdev_priv(netdev); 1647 u32 err; 1648 1649 pci_set_power_state(pdev, PCI_D0); 1650 pci_restore_state(pdev); 1651 1652 err = pci_enable_device(pdev); 1653 if (err) { 1654 printk(KERN_ERR 1655 "atl2: Cannot enable PCI device from suspend\n"); 1656 return err; 1657 } 1658 1659 pci_set_master(pdev); 1660 1661 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ 1662 1663 pci_enable_wake(pdev, PCI_D3hot, 0); 1664 pci_enable_wake(pdev, PCI_D3cold, 0); 1665 1666 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); 1667 1668 if (netif_running(netdev)) { 1669 err = atl2_request_irq(adapter); 1670 if (err) 1671 return err; 1672 } 1673 1674 atl2_reset_hw(&adapter->hw); 1675 1676 if (netif_running(netdev)) 1677 atl2_up(adapter); 1678 1679 netif_device_attach(netdev); 1680 1681 return 0; 1682 } 1683 #endif 1684 1685 static void atl2_shutdown(struct pci_dev *pdev) 1686 { 1687 atl2_suspend(pdev, PMSG_SUSPEND); 1688 } 1689 1690 static struct pci_driver atl2_driver = { 1691 .name = atl2_driver_name, 1692 .id_table = atl2_pci_tbl, 1693 .probe = atl2_probe, 1694 .remove = atl2_remove, 1695 /* Power Management Hooks */ 1696 .suspend = atl2_suspend, 1697 #ifdef CONFIG_PM 1698 .resume = atl2_resume, 1699 #endif 1700 .shutdown = atl2_shutdown, 1701 }; 1702 1703 /** 1704 * atl2_init_module - Driver Registration Routine 1705 * 1706 * atl2_init_module is the first routine called when the driver is 1707 * loaded. All it does is register with the PCI subsystem. 1708 */ 1709 static int __init atl2_init_module(void) 1710 { 1711 printk(KERN_INFO "%s - version %s\n", atl2_driver_string, 1712 atl2_driver_version); 1713 printk(KERN_INFO "%s\n", atl2_copyright); 1714 return pci_register_driver(&atl2_driver); 1715 } 1716 module_init(atl2_init_module); 1717 1718 /** 1719 * atl2_exit_module - Driver Exit Cleanup Routine 1720 * 1721 * atl2_exit_module is called just before the driver is removed 1722 * from memory. 1723 */ 1724 static void __exit atl2_exit_module(void) 1725 { 1726 pci_unregister_driver(&atl2_driver); 1727 } 1728 module_exit(atl2_exit_module); 1729 1730 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1731 { 1732 struct atl2_adapter *adapter = hw->back; 1733 pci_read_config_word(adapter->pdev, reg, value); 1734 } 1735 1736 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1737 { 1738 struct atl2_adapter *adapter = hw->back; 1739 pci_write_config_word(adapter->pdev, reg, *value); 1740 } 1741 1742 static int atl2_get_settings(struct net_device *netdev, 1743 struct ethtool_cmd *ecmd) 1744 { 1745 struct atl2_adapter *adapter = netdev_priv(netdev); 1746 struct atl2_hw *hw = &adapter->hw; 1747 1748 ecmd->supported = (SUPPORTED_10baseT_Half | 1749 SUPPORTED_10baseT_Full | 1750 SUPPORTED_100baseT_Half | 1751 SUPPORTED_100baseT_Full | 1752 SUPPORTED_Autoneg | 1753 SUPPORTED_TP); 1754 ecmd->advertising = ADVERTISED_TP; 1755 1756 ecmd->advertising |= ADVERTISED_Autoneg; 1757 ecmd->advertising |= hw->autoneg_advertised; 1758 1759 ecmd->port = PORT_TP; 1760 ecmd->phy_address = 0; 1761 ecmd->transceiver = XCVR_INTERNAL; 1762 1763 if (adapter->link_speed != SPEED_0) { 1764 ethtool_cmd_speed_set(ecmd, adapter->link_speed); 1765 if (adapter->link_duplex == FULL_DUPLEX) 1766 ecmd->duplex = DUPLEX_FULL; 1767 else 1768 ecmd->duplex = DUPLEX_HALF; 1769 } else { 1770 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN); 1771 ecmd->duplex = DUPLEX_UNKNOWN; 1772 } 1773 1774 ecmd->autoneg = AUTONEG_ENABLE; 1775 return 0; 1776 } 1777 1778 static int atl2_set_settings(struct net_device *netdev, 1779 struct ethtool_cmd *ecmd) 1780 { 1781 struct atl2_adapter *adapter = netdev_priv(netdev); 1782 struct atl2_hw *hw = &adapter->hw; 1783 1784 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1785 msleep(1); 1786 1787 if (ecmd->autoneg == AUTONEG_ENABLE) { 1788 #define MY_ADV_MASK (ADVERTISE_10_HALF | \ 1789 ADVERTISE_10_FULL | \ 1790 ADVERTISE_100_HALF| \ 1791 ADVERTISE_100_FULL) 1792 1793 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) { 1794 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; 1795 hw->autoneg_advertised = MY_ADV_MASK; 1796 } else if ((ecmd->advertising & MY_ADV_MASK) == 1797 ADVERTISE_100_FULL) { 1798 hw->MediaType = MEDIA_TYPE_100M_FULL; 1799 hw->autoneg_advertised = ADVERTISE_100_FULL; 1800 } else if ((ecmd->advertising & MY_ADV_MASK) == 1801 ADVERTISE_100_HALF) { 1802 hw->MediaType = MEDIA_TYPE_100M_HALF; 1803 hw->autoneg_advertised = ADVERTISE_100_HALF; 1804 } else if ((ecmd->advertising & MY_ADV_MASK) == 1805 ADVERTISE_10_FULL) { 1806 hw->MediaType = MEDIA_TYPE_10M_FULL; 1807 hw->autoneg_advertised = ADVERTISE_10_FULL; 1808 } else if ((ecmd->advertising & MY_ADV_MASK) == 1809 ADVERTISE_10_HALF) { 1810 hw->MediaType = MEDIA_TYPE_10M_HALF; 1811 hw->autoneg_advertised = ADVERTISE_10_HALF; 1812 } else { 1813 clear_bit(__ATL2_RESETTING, &adapter->flags); 1814 return -EINVAL; 1815 } 1816 ecmd->advertising = hw->autoneg_advertised | 1817 ADVERTISED_TP | ADVERTISED_Autoneg; 1818 } else { 1819 clear_bit(__ATL2_RESETTING, &adapter->flags); 1820 return -EINVAL; 1821 } 1822 1823 /* reset the link */ 1824 if (netif_running(adapter->netdev)) { 1825 atl2_down(adapter); 1826 atl2_up(adapter); 1827 } else 1828 atl2_reset_hw(&adapter->hw); 1829 1830 clear_bit(__ATL2_RESETTING, &adapter->flags); 1831 return 0; 1832 } 1833 1834 static u32 atl2_get_msglevel(struct net_device *netdev) 1835 { 1836 return 0; 1837 } 1838 1839 /* 1840 * It's sane for this to be empty, but we might want to take advantage of this. 1841 */ 1842 static void atl2_set_msglevel(struct net_device *netdev, u32 data) 1843 { 1844 } 1845 1846 static int atl2_get_regs_len(struct net_device *netdev) 1847 { 1848 #define ATL2_REGS_LEN 42 1849 return sizeof(u32) * ATL2_REGS_LEN; 1850 } 1851 1852 static void atl2_get_regs(struct net_device *netdev, 1853 struct ethtool_regs *regs, void *p) 1854 { 1855 struct atl2_adapter *adapter = netdev_priv(netdev); 1856 struct atl2_hw *hw = &adapter->hw; 1857 u32 *regs_buff = p; 1858 u16 phy_data; 1859 1860 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN); 1861 1862 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 1863 1864 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); 1865 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 1866 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); 1867 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); 1868 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); 1869 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); 1870 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); 1871 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); 1872 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); 1873 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); 1874 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); 1875 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); 1876 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); 1877 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); 1878 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); 1879 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 1880 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); 1881 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); 1882 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); 1883 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); 1884 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); 1885 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); 1886 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); 1887 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); 1888 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); 1889 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); 1890 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); 1891 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); 1892 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); 1893 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); 1894 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); 1895 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); 1896 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); 1897 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); 1898 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); 1899 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); 1900 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); 1901 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); 1902 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); 1903 1904 atl2_read_phy_reg(hw, MII_BMCR, &phy_data); 1905 regs_buff[40] = (u32)phy_data; 1906 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1907 regs_buff[41] = (u32)phy_data; 1908 } 1909 1910 static int atl2_get_eeprom_len(struct net_device *netdev) 1911 { 1912 struct atl2_adapter *adapter = netdev_priv(netdev); 1913 1914 if (!atl2_check_eeprom_exist(&adapter->hw)) 1915 return 512; 1916 else 1917 return 0; 1918 } 1919 1920 static int atl2_get_eeprom(struct net_device *netdev, 1921 struct ethtool_eeprom *eeprom, u8 *bytes) 1922 { 1923 struct atl2_adapter *adapter = netdev_priv(netdev); 1924 struct atl2_hw *hw = &adapter->hw; 1925 u32 *eeprom_buff; 1926 int first_dword, last_dword; 1927 int ret_val = 0; 1928 int i; 1929 1930 if (eeprom->len == 0) 1931 return -EINVAL; 1932 1933 if (atl2_check_eeprom_exist(hw)) 1934 return -EINVAL; 1935 1936 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 1937 1938 first_dword = eeprom->offset >> 2; 1939 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1940 1941 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1), 1942 GFP_KERNEL); 1943 if (!eeprom_buff) 1944 return -ENOMEM; 1945 1946 for (i = first_dword; i < last_dword; i++) { 1947 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) { 1948 ret_val = -EIO; 1949 goto free; 1950 } 1951 } 1952 1953 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), 1954 eeprom->len); 1955 free: 1956 kfree(eeprom_buff); 1957 1958 return ret_val; 1959 } 1960 1961 static int atl2_set_eeprom(struct net_device *netdev, 1962 struct ethtool_eeprom *eeprom, u8 *bytes) 1963 { 1964 struct atl2_adapter *adapter = netdev_priv(netdev); 1965 struct atl2_hw *hw = &adapter->hw; 1966 u32 *eeprom_buff; 1967 u32 *ptr; 1968 int max_len, first_dword, last_dword, ret_val = 0; 1969 int i; 1970 1971 if (eeprom->len == 0) 1972 return -EOPNOTSUPP; 1973 1974 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 1975 return -EFAULT; 1976 1977 max_len = 512; 1978 1979 first_dword = eeprom->offset >> 2; 1980 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1981 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 1982 if (!eeprom_buff) 1983 return -ENOMEM; 1984 1985 ptr = eeprom_buff; 1986 1987 if (eeprom->offset & 3) { 1988 /* need read/modify/write of first changed EEPROM word */ 1989 /* only the second byte of the word is being modified */ 1990 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) { 1991 ret_val = -EIO; 1992 goto out; 1993 } 1994 ptr++; 1995 } 1996 if (((eeprom->offset + eeprom->len) & 3)) { 1997 /* 1998 * need read/modify/write of last changed EEPROM word 1999 * only the first byte of the word is being modified 2000 */ 2001 if (!atl2_read_eeprom(hw, last_dword * 4, 2002 &(eeprom_buff[last_dword - first_dword]))) { 2003 ret_val = -EIO; 2004 goto out; 2005 } 2006 } 2007 2008 /* Device's eeprom is always little-endian, word addressable */ 2009 memcpy(ptr, bytes, eeprom->len); 2010 2011 for (i = 0; i < last_dword - first_dword + 1; i++) { 2012 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) { 2013 ret_val = -EIO; 2014 goto out; 2015 } 2016 } 2017 out: 2018 kfree(eeprom_buff); 2019 return ret_val; 2020 } 2021 2022 static void atl2_get_drvinfo(struct net_device *netdev, 2023 struct ethtool_drvinfo *drvinfo) 2024 { 2025 struct atl2_adapter *adapter = netdev_priv(netdev); 2026 2027 strlcpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver)); 2028 strlcpy(drvinfo->version, atl2_driver_version, 2029 sizeof(drvinfo->version)); 2030 strlcpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version)); 2031 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 2032 sizeof(drvinfo->bus_info)); 2033 } 2034 2035 static void atl2_get_wol(struct net_device *netdev, 2036 struct ethtool_wolinfo *wol) 2037 { 2038 struct atl2_adapter *adapter = netdev_priv(netdev); 2039 2040 wol->supported = WAKE_MAGIC; 2041 wol->wolopts = 0; 2042 2043 if (adapter->wol & ATLX_WUFC_EX) 2044 wol->wolopts |= WAKE_UCAST; 2045 if (adapter->wol & ATLX_WUFC_MC) 2046 wol->wolopts |= WAKE_MCAST; 2047 if (adapter->wol & ATLX_WUFC_BC) 2048 wol->wolopts |= WAKE_BCAST; 2049 if (adapter->wol & ATLX_WUFC_MAG) 2050 wol->wolopts |= WAKE_MAGIC; 2051 if (adapter->wol & ATLX_WUFC_LNKC) 2052 wol->wolopts |= WAKE_PHY; 2053 } 2054 2055 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2056 { 2057 struct atl2_adapter *adapter = netdev_priv(netdev); 2058 2059 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2060 return -EOPNOTSUPP; 2061 2062 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)) 2063 return -EOPNOTSUPP; 2064 2065 /* these settings will always override what we currently have */ 2066 adapter->wol = 0; 2067 2068 if (wol->wolopts & WAKE_MAGIC) 2069 adapter->wol |= ATLX_WUFC_MAG; 2070 if (wol->wolopts & WAKE_PHY) 2071 adapter->wol |= ATLX_WUFC_LNKC; 2072 2073 return 0; 2074 } 2075 2076 static int atl2_nway_reset(struct net_device *netdev) 2077 { 2078 struct atl2_adapter *adapter = netdev_priv(netdev); 2079 if (netif_running(netdev)) 2080 atl2_reinit_locked(adapter); 2081 return 0; 2082 } 2083 2084 static const struct ethtool_ops atl2_ethtool_ops = { 2085 .get_settings = atl2_get_settings, 2086 .set_settings = atl2_set_settings, 2087 .get_drvinfo = atl2_get_drvinfo, 2088 .get_regs_len = atl2_get_regs_len, 2089 .get_regs = atl2_get_regs, 2090 .get_wol = atl2_get_wol, 2091 .set_wol = atl2_set_wol, 2092 .get_msglevel = atl2_get_msglevel, 2093 .set_msglevel = atl2_set_msglevel, 2094 .nway_reset = atl2_nway_reset, 2095 .get_link = ethtool_op_get_link, 2096 .get_eeprom_len = atl2_get_eeprom_len, 2097 .get_eeprom = atl2_get_eeprom, 2098 .set_eeprom = atl2_set_eeprom, 2099 }; 2100 2101 #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \ 2102 (((a) & 0xff00ff00) >> 8)) 2103 #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16)) 2104 #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8)) 2105 2106 /* 2107 * Reset the transmit and receive units; mask and clear all interrupts. 2108 * 2109 * hw - Struct containing variables accessed by shared code 2110 * return : 0 or idle status (if error) 2111 */ 2112 static s32 atl2_reset_hw(struct atl2_hw *hw) 2113 { 2114 u32 icr; 2115 u16 pci_cfg_cmd_word; 2116 int i; 2117 2118 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ 2119 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2120 if ((pci_cfg_cmd_word & 2121 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) != 2122 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) { 2123 pci_cfg_cmd_word |= 2124 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER); 2125 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2126 } 2127 2128 /* Clear Interrupt mask to stop board from generating 2129 * interrupts & Clear any pending interrupt events 2130 */ 2131 /* FIXME */ 2132 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */ 2133 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */ 2134 2135 /* Issue Soft Reset to the MAC. This will reset the chip's 2136 * transmit, receive, DMA. It will not effect 2137 * the current PCI configuration. The global reset bit is self- 2138 * clearing, and should clear within a microsecond. 2139 */ 2140 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); 2141 wmb(); 2142 msleep(1); /* delay about 1ms */ 2143 2144 /* Wait at least 10ms for All module to be Idle */ 2145 for (i = 0; i < 10; i++) { 2146 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); 2147 if (!icr) 2148 break; 2149 msleep(1); /* delay 1 ms */ 2150 cpu_relax(); 2151 } 2152 2153 if (icr) 2154 return icr; 2155 2156 return 0; 2157 } 2158 2159 #define CUSTOM_SPI_CS_SETUP 2 2160 #define CUSTOM_SPI_CLK_HI 2 2161 #define CUSTOM_SPI_CLK_LO 2 2162 #define CUSTOM_SPI_CS_HOLD 2 2163 #define CUSTOM_SPI_CS_HI 3 2164 2165 static struct atl2_spi_flash_dev flash_table[] = 2166 { 2167 /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */ 2168 {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 }, 2169 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 }, 2170 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 }, 2171 }; 2172 2173 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf) 2174 { 2175 int i; 2176 u32 value; 2177 2178 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); 2179 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); 2180 2181 value = SPI_FLASH_CTRL_WAIT_READY | 2182 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << 2183 SPI_FLASH_CTRL_CS_SETUP_SHIFT | 2184 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << 2185 SPI_FLASH_CTRL_CLK_HI_SHIFT | 2186 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << 2187 SPI_FLASH_CTRL_CLK_LO_SHIFT | 2188 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << 2189 SPI_FLASH_CTRL_CS_HOLD_SHIFT | 2190 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << 2191 SPI_FLASH_CTRL_CS_HI_SHIFT | 2192 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT; 2193 2194 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2195 2196 value |= SPI_FLASH_CTRL_START; 2197 2198 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2199 2200 for (i = 0; i < 10; i++) { 2201 msleep(1); 2202 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2203 if (!(value & SPI_FLASH_CTRL_START)) 2204 break; 2205 } 2206 2207 if (value & SPI_FLASH_CTRL_START) 2208 return false; 2209 2210 *buf = ATL2_READ_REG(hw, REG_SPI_DATA); 2211 2212 return true; 2213 } 2214 2215 /* 2216 * get_permanent_address 2217 * return 0 if get valid mac address, 2218 */ 2219 static int get_permanent_address(struct atl2_hw *hw) 2220 { 2221 u32 Addr[2]; 2222 u32 i, Control; 2223 u16 Register; 2224 u8 EthAddr[ETH_ALEN]; 2225 bool KeyValid; 2226 2227 if (is_valid_ether_addr(hw->perm_mac_addr)) 2228 return 0; 2229 2230 Addr[0] = 0; 2231 Addr[1] = 0; 2232 2233 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ 2234 Register = 0; 2235 KeyValid = false; 2236 2237 /* Read out all EEPROM content */ 2238 i = 0; 2239 while (1) { 2240 if (atl2_read_eeprom(hw, i + 0x100, &Control)) { 2241 if (KeyValid) { 2242 if (Register == REG_MAC_STA_ADDR) 2243 Addr[0] = Control; 2244 else if (Register == 2245 (REG_MAC_STA_ADDR + 4)) 2246 Addr[1] = Control; 2247 KeyValid = false; 2248 } else if ((Control & 0xff) == 0x5A) { 2249 KeyValid = true; 2250 Register = (u16) (Control >> 16); 2251 } else { 2252 /* assume data end while encount an invalid KEYWORD */ 2253 break; 2254 } 2255 } else { 2256 break; /* read error */ 2257 } 2258 i += 4; 2259 } 2260 2261 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2262 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2263 2264 if (is_valid_ether_addr(EthAddr)) { 2265 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2266 return 0; 2267 } 2268 return 1; 2269 } 2270 2271 /* see if SPI flash exists? */ 2272 Addr[0] = 0; 2273 Addr[1] = 0; 2274 Register = 0; 2275 KeyValid = false; 2276 i = 0; 2277 while (1) { 2278 if (atl2_spi_read(hw, i + 0x1f000, &Control)) { 2279 if (KeyValid) { 2280 if (Register == REG_MAC_STA_ADDR) 2281 Addr[0] = Control; 2282 else if (Register == (REG_MAC_STA_ADDR + 4)) 2283 Addr[1] = Control; 2284 KeyValid = false; 2285 } else if ((Control & 0xff) == 0x5A) { 2286 KeyValid = true; 2287 Register = (u16) (Control >> 16); 2288 } else { 2289 break; /* data end */ 2290 } 2291 } else { 2292 break; /* read error */ 2293 } 2294 i += 4; 2295 } 2296 2297 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2298 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]); 2299 if (is_valid_ether_addr(EthAddr)) { 2300 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2301 return 0; 2302 } 2303 /* maybe MAC-address is from BIOS */ 2304 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 2305 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4); 2306 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2307 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2308 2309 if (is_valid_ether_addr(EthAddr)) { 2310 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2311 return 0; 2312 } 2313 2314 return 1; 2315 } 2316 2317 /* 2318 * Reads the adapter's MAC address from the EEPROM 2319 * 2320 * hw - Struct containing variables accessed by shared code 2321 */ 2322 static s32 atl2_read_mac_addr(struct atl2_hw *hw) 2323 { 2324 if (get_permanent_address(hw)) { 2325 /* for test */ 2326 /* FIXME: shouldn't we use eth_random_addr() here? */ 2327 hw->perm_mac_addr[0] = 0x00; 2328 hw->perm_mac_addr[1] = 0x13; 2329 hw->perm_mac_addr[2] = 0x74; 2330 hw->perm_mac_addr[3] = 0x00; 2331 hw->perm_mac_addr[4] = 0x5c; 2332 hw->perm_mac_addr[5] = 0x38; 2333 } 2334 2335 memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN); 2336 2337 return 0; 2338 } 2339 2340 /* 2341 * Hashes an address to determine its location in the multicast table 2342 * 2343 * hw - Struct containing variables accessed by shared code 2344 * mc_addr - the multicast address to hash 2345 * 2346 * atl2_hash_mc_addr 2347 * purpose 2348 * set hash value for a multicast address 2349 * hash calcu processing : 2350 * 1. calcu 32bit CRC for multicast address 2351 * 2. reverse crc with MSB to LSB 2352 */ 2353 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) 2354 { 2355 u32 crc32, value; 2356 int i; 2357 2358 value = 0; 2359 crc32 = ether_crc_le(6, mc_addr); 2360 2361 for (i = 0; i < 32; i++) 2362 value |= (((crc32 >> i) & 1) << (31 - i)); 2363 2364 return value; 2365 } 2366 2367 /* 2368 * Sets the bit in the multicast table corresponding to the hash value. 2369 * 2370 * hw - Struct containing variables accessed by shared code 2371 * hash_value - Multicast address hash value 2372 */ 2373 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value) 2374 { 2375 u32 hash_bit, hash_reg; 2376 u32 mta; 2377 2378 /* The HASH Table is a register array of 2 32-bit registers. 2379 * It is treated like an array of 64 bits. We want to set 2380 * bit BitArray[hash_value]. So we figure out what register 2381 * the bit is in, read it, OR in the new bit, then write 2382 * back the new value. The register is determined by the 2383 * upper 7 bits of the hash value and the bit within that 2384 * register are determined by the lower 5 bits of the value. 2385 */ 2386 hash_reg = (hash_value >> 31) & 0x1; 2387 hash_bit = (hash_value >> 26) & 0x1F; 2388 2389 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); 2390 2391 mta |= (1 << hash_bit); 2392 2393 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); 2394 } 2395 2396 /* 2397 * atl2_init_pcie - init PCIE module 2398 */ 2399 static void atl2_init_pcie(struct atl2_hw *hw) 2400 { 2401 u32 value; 2402 value = LTSSM_TEST_MODE_DEF; 2403 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); 2404 2405 value = PCIE_DLL_TX_CTRL1_DEF; 2406 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); 2407 } 2408 2409 static void atl2_init_flash_opcode(struct atl2_hw *hw) 2410 { 2411 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) 2412 hw->flash_vendor = 0; /* ATMEL */ 2413 2414 /* Init OP table */ 2415 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, 2416 flash_table[hw->flash_vendor].cmdPROGRAM); 2417 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, 2418 flash_table[hw->flash_vendor].cmdSECTOR_ERASE); 2419 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, 2420 flash_table[hw->flash_vendor].cmdCHIP_ERASE); 2421 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, 2422 flash_table[hw->flash_vendor].cmdRDID); 2423 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, 2424 flash_table[hw->flash_vendor].cmdWREN); 2425 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, 2426 flash_table[hw->flash_vendor].cmdRDSR); 2427 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, 2428 flash_table[hw->flash_vendor].cmdWRSR); 2429 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, 2430 flash_table[hw->flash_vendor].cmdREAD); 2431 } 2432 2433 /******************************************************************** 2434 * Performs basic configuration of the adapter. 2435 * 2436 * hw - Struct containing variables accessed by shared code 2437 * Assumes that the controller has previously been reset and is in a 2438 * post-reset uninitialized state. Initializes multicast table, 2439 * and Calls routines to setup link 2440 * Leaves the transmit and receive units disabled and uninitialized. 2441 ********************************************************************/ 2442 static s32 atl2_init_hw(struct atl2_hw *hw) 2443 { 2444 u32 ret_val = 0; 2445 2446 atl2_init_pcie(hw); 2447 2448 /* Zero out the Multicast HASH table */ 2449 /* clear the old settings from the multicast hash table */ 2450 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 2451 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 2452 2453 atl2_init_flash_opcode(hw); 2454 2455 ret_val = atl2_phy_init(hw); 2456 2457 return ret_val; 2458 } 2459 2460 /* 2461 * Detects the current speed and duplex settings of the hardware. 2462 * 2463 * hw - Struct containing variables accessed by shared code 2464 * speed - Speed of the connection 2465 * duplex - Duplex setting of the connection 2466 */ 2467 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, 2468 u16 *duplex) 2469 { 2470 s32 ret_val; 2471 u16 phy_data; 2472 2473 /* Read PHY Specific Status Register (17) */ 2474 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); 2475 if (ret_val) 2476 return ret_val; 2477 2478 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) 2479 return ATLX_ERR_PHY_RES; 2480 2481 switch (phy_data & MII_ATLX_PSSR_SPEED) { 2482 case MII_ATLX_PSSR_100MBS: 2483 *speed = SPEED_100; 2484 break; 2485 case MII_ATLX_PSSR_10MBS: 2486 *speed = SPEED_10; 2487 break; 2488 default: 2489 return ATLX_ERR_PHY_SPEED; 2490 } 2491 2492 if (phy_data & MII_ATLX_PSSR_DPLX) 2493 *duplex = FULL_DUPLEX; 2494 else 2495 *duplex = HALF_DUPLEX; 2496 2497 return 0; 2498 } 2499 2500 /* 2501 * Reads the value from a PHY register 2502 * hw - Struct containing variables accessed by shared code 2503 * reg_addr - address of the PHY register to read 2504 */ 2505 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) 2506 { 2507 u32 val; 2508 int i; 2509 2510 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 2511 MDIO_START | 2512 MDIO_SUP_PREAMBLE | 2513 MDIO_RW | 2514 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2515 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2516 2517 wmb(); 2518 2519 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2520 udelay(2); 2521 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2522 if (!(val & (MDIO_START | MDIO_BUSY))) 2523 break; 2524 wmb(); 2525 } 2526 if (!(val & (MDIO_START | MDIO_BUSY))) { 2527 *phy_data = (u16)val; 2528 return 0; 2529 } 2530 2531 return ATLX_ERR_PHY; 2532 } 2533 2534 /* 2535 * Writes a value to a PHY register 2536 * hw - Struct containing variables accessed by shared code 2537 * reg_addr - address of the PHY register to write 2538 * data - data to write to the PHY 2539 */ 2540 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) 2541 { 2542 int i; 2543 u32 val; 2544 2545 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 2546 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 2547 MDIO_SUP_PREAMBLE | 2548 MDIO_START | 2549 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2550 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2551 2552 wmb(); 2553 2554 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2555 udelay(2); 2556 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2557 if (!(val & (MDIO_START | MDIO_BUSY))) 2558 break; 2559 2560 wmb(); 2561 } 2562 2563 if (!(val & (MDIO_START | MDIO_BUSY))) 2564 return 0; 2565 2566 return ATLX_ERR_PHY; 2567 } 2568 2569 /* 2570 * Configures PHY autoneg and flow control advertisement settings 2571 * 2572 * hw - Struct containing variables accessed by shared code 2573 */ 2574 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) 2575 { 2576 s32 ret_val; 2577 s16 mii_autoneg_adv_reg; 2578 2579 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2580 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 2581 2582 /* Need to parse autoneg_advertised and set up 2583 * the appropriate PHY registers. First we will parse for 2584 * autoneg_advertised software override. Since we can advertise 2585 * a plethora of combinations, we need to check each bit 2586 * individually. 2587 */ 2588 2589 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 2590 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2591 * the 1000Base-T Control Register (Address 9). */ 2592 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 2593 2594 /* Need to parse MediaType and setup the 2595 * appropriate PHY registers. */ 2596 switch (hw->MediaType) { 2597 case MEDIA_TYPE_AUTO_SENSOR: 2598 mii_autoneg_adv_reg |= 2599 (MII_AR_10T_HD_CAPS | 2600 MII_AR_10T_FD_CAPS | 2601 MII_AR_100TX_HD_CAPS| 2602 MII_AR_100TX_FD_CAPS); 2603 hw->autoneg_advertised = 2604 ADVERTISE_10_HALF | 2605 ADVERTISE_10_FULL | 2606 ADVERTISE_100_HALF| 2607 ADVERTISE_100_FULL; 2608 break; 2609 case MEDIA_TYPE_100M_FULL: 2610 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 2611 hw->autoneg_advertised = ADVERTISE_100_FULL; 2612 break; 2613 case MEDIA_TYPE_100M_HALF: 2614 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 2615 hw->autoneg_advertised = ADVERTISE_100_HALF; 2616 break; 2617 case MEDIA_TYPE_10M_FULL: 2618 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 2619 hw->autoneg_advertised = ADVERTISE_10_FULL; 2620 break; 2621 default: 2622 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 2623 hw->autoneg_advertised = ADVERTISE_10_HALF; 2624 break; 2625 } 2626 2627 /* flow control fixed to enable all */ 2628 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 2629 2630 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 2631 2632 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 2633 2634 if (ret_val) 2635 return ret_val; 2636 2637 return 0; 2638 } 2639 2640 /* 2641 * Resets the PHY and make all config validate 2642 * 2643 * hw - Struct containing variables accessed by shared code 2644 * 2645 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) 2646 */ 2647 static s32 atl2_phy_commit(struct atl2_hw *hw) 2648 { 2649 s32 ret_val; 2650 u16 phy_data; 2651 2652 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2653 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); 2654 if (ret_val) { 2655 u32 val; 2656 int i; 2657 /* pcie serdes link may be down ! */ 2658 for (i = 0; i < 25; i++) { 2659 msleep(1); 2660 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2661 if (!(val & (MDIO_START | MDIO_BUSY))) 2662 break; 2663 } 2664 2665 if (0 != (val & (MDIO_START | MDIO_BUSY))) { 2666 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n"); 2667 return ret_val; 2668 } 2669 } 2670 return 0; 2671 } 2672 2673 static s32 atl2_phy_init(struct atl2_hw *hw) 2674 { 2675 s32 ret_val; 2676 u16 phy_val; 2677 2678 if (hw->phy_configured) 2679 return 0; 2680 2681 /* Enable PHY */ 2682 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); 2683 ATL2_WRITE_FLUSH(hw); 2684 msleep(1); 2685 2686 /* check if the PHY is in powersaving mode */ 2687 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2688 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2689 2690 /* 024E / 124E 0r 0274 / 1274 ? */ 2691 if (phy_val & 0x1000) { 2692 phy_val &= ~0x1000; 2693 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); 2694 } 2695 2696 msleep(1); 2697 2698 /*Enable PHY LinkChange Interrupt */ 2699 ret_val = atl2_write_phy_reg(hw, 18, 0xC00); 2700 if (ret_val) 2701 return ret_val; 2702 2703 /* setup AutoNeg parameters */ 2704 ret_val = atl2_phy_setup_autoneg_adv(hw); 2705 if (ret_val) 2706 return ret_val; 2707 2708 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */ 2709 ret_val = atl2_phy_commit(hw); 2710 if (ret_val) 2711 return ret_val; 2712 2713 hw->phy_configured = true; 2714 2715 return ret_val; 2716 } 2717 2718 static void atl2_set_mac_addr(struct atl2_hw *hw) 2719 { 2720 u32 value; 2721 /* 00-0B-6A-F6-00-DC 2722 * 0: 6AF600DC 1: 000B 2723 * low dword */ 2724 value = (((u32)hw->mac_addr[2]) << 24) | 2725 (((u32)hw->mac_addr[3]) << 16) | 2726 (((u32)hw->mac_addr[4]) << 8) | 2727 (((u32)hw->mac_addr[5])); 2728 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); 2729 /* hight dword */ 2730 value = (((u32)hw->mac_addr[0]) << 8) | 2731 (((u32)hw->mac_addr[1])); 2732 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); 2733 } 2734 2735 /* 2736 * check_eeprom_exist 2737 * return 0 if eeprom exist 2738 */ 2739 static int atl2_check_eeprom_exist(struct atl2_hw *hw) 2740 { 2741 u32 value; 2742 2743 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2744 if (value & SPI_FLASH_CTRL_EN_VPD) { 2745 value &= ~SPI_FLASH_CTRL_EN_VPD; 2746 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2747 } 2748 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); 2749 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 2750 } 2751 2752 /* FIXME: This doesn't look right. -- CHS */ 2753 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) 2754 { 2755 return true; 2756 } 2757 2758 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) 2759 { 2760 int i; 2761 u32 Control; 2762 2763 if (Offset & 0x3) 2764 return false; /* address do not align */ 2765 2766 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); 2767 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 2768 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); 2769 2770 for (i = 0; i < 10; i++) { 2771 msleep(2); 2772 Control = ATL2_READ_REG(hw, REG_VPD_CAP); 2773 if (Control & VPD_CAP_VPD_FLAG) 2774 break; 2775 } 2776 2777 if (Control & VPD_CAP_VPD_FLAG) { 2778 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); 2779 return true; 2780 } 2781 return false; /* timeout */ 2782 } 2783 2784 static void atl2_force_ps(struct atl2_hw *hw) 2785 { 2786 u16 phy_val; 2787 2788 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2789 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2790 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); 2791 2792 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); 2793 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); 2794 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); 2795 atl2_write_phy_reg(hw, MII_DBG_DATA, 0); 2796 } 2797 2798 /* This is the only thing that needs to be changed to adjust the 2799 * maximum number of ports that the driver can manage. 2800 */ 2801 #define ATL2_MAX_NIC 4 2802 2803 #define OPTION_UNSET -1 2804 #define OPTION_DISABLED 0 2805 #define OPTION_ENABLED 1 2806 2807 /* All parameters are treated the same, as an integer array of values. 2808 * This macro just reduces the need to repeat the same declaration code 2809 * over and over (plus this helps to avoid typo bugs). 2810 */ 2811 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET} 2812 #ifndef module_param_array 2813 /* Module Parameters are always initialized to -1, so that the driver 2814 * can tell the difference between no user specified value or the 2815 * user asking for the default value. 2816 * The true default values are loaded in when atl2_check_options is called. 2817 * 2818 * This is a GCC extension to ANSI C. 2819 * See the item "Labeled Elements in Initializers" in the section 2820 * "Extensions to the C Language Family" of the GCC documentation. 2821 */ 2822 2823 #define ATL2_PARAM(X, desc) \ 2824 static const int X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \ 2825 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \ 2826 MODULE_PARM_DESC(X, desc); 2827 #else 2828 #define ATL2_PARAM(X, desc) \ 2829 static int X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \ 2830 static unsigned int num_##X; \ 2831 module_param_array_named(X, X, int, &num_##X, 0); \ 2832 MODULE_PARM_DESC(X, desc); 2833 #endif 2834 2835 /* 2836 * Transmit Memory Size 2837 * Valid Range: 64-2048 2838 * Default Value: 128 2839 */ 2840 #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */ 2841 #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */ 2842 #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */ 2843 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory"); 2844 2845 /* 2846 * Receive Memory Block Count 2847 * Valid Range: 16-512 2848 * Default Value: 128 2849 */ 2850 #define ATL2_MIN_RXD_COUNT 16 2851 #define ATL2_MAX_RXD_COUNT 512 2852 #define ATL2_DEFAULT_RXD_COUNT 64 2853 ATL2_PARAM(RxMemBlock, "Number of receive memory block"); 2854 2855 /* 2856 * User Specified MediaType Override 2857 * 2858 * Valid Range: 0-5 2859 * - 0 - auto-negotiate at all supported speeds 2860 * - 1 - only link at 1000Mbps Full Duplex 2861 * - 2 - only link at 100Mbps Full Duplex 2862 * - 3 - only link at 100Mbps Half Duplex 2863 * - 4 - only link at 10Mbps Full Duplex 2864 * - 5 - only link at 10Mbps Half Duplex 2865 * Default Value: 0 2866 */ 2867 ATL2_PARAM(MediaType, "MediaType Select"); 2868 2869 /* 2870 * Interrupt Moderate Timer in units of 2048 ns (~2 us) 2871 * Valid Range: 10-65535 2872 * Default Value: 45000(90ms) 2873 */ 2874 #define INT_MOD_DEFAULT_CNT 100 /* 200us */ 2875 #define INT_MOD_MAX_CNT 65000 2876 #define INT_MOD_MIN_CNT 50 2877 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer"); 2878 2879 /* 2880 * FlashVendor 2881 * Valid Range: 0-2 2882 * 0 - Atmel 2883 * 1 - SST 2884 * 2 - ST 2885 */ 2886 ATL2_PARAM(FlashVendor, "SPI Flash Vendor"); 2887 2888 #define AUTONEG_ADV_DEFAULT 0x2F 2889 #define AUTONEG_ADV_MASK 0x2F 2890 #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL 2891 2892 #define FLASH_VENDOR_DEFAULT 0 2893 #define FLASH_VENDOR_MIN 0 2894 #define FLASH_VENDOR_MAX 2 2895 2896 struct atl2_option { 2897 enum { enable_option, range_option, list_option } type; 2898 char *name; 2899 char *err; 2900 int def; 2901 union { 2902 struct { /* range_option info */ 2903 int min; 2904 int max; 2905 } r; 2906 struct { /* list_option info */ 2907 int nr; 2908 struct atl2_opt_list { int i; char *str; } *p; 2909 } l; 2910 } arg; 2911 }; 2912 2913 static int atl2_validate_option(int *value, struct atl2_option *opt) 2914 { 2915 int i; 2916 struct atl2_opt_list *ent; 2917 2918 if (*value == OPTION_UNSET) { 2919 *value = opt->def; 2920 return 0; 2921 } 2922 2923 switch (opt->type) { 2924 case enable_option: 2925 switch (*value) { 2926 case OPTION_ENABLED: 2927 printk(KERN_INFO "%s Enabled\n", opt->name); 2928 return 0; 2929 case OPTION_DISABLED: 2930 printk(KERN_INFO "%s Disabled\n", opt->name); 2931 return 0; 2932 } 2933 break; 2934 case range_option: 2935 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 2936 printk(KERN_INFO "%s set to %i\n", opt->name, *value); 2937 return 0; 2938 } 2939 break; 2940 case list_option: 2941 for (i = 0; i < opt->arg.l.nr; i++) { 2942 ent = &opt->arg.l.p[i]; 2943 if (*value == ent->i) { 2944 if (ent->str[0] != '\0') 2945 printk(KERN_INFO "%s\n", ent->str); 2946 return 0; 2947 } 2948 } 2949 break; 2950 default: 2951 BUG(); 2952 } 2953 2954 printk(KERN_INFO "Invalid %s specified (%i) %s\n", 2955 opt->name, *value, opt->err); 2956 *value = opt->def; 2957 return -1; 2958 } 2959 2960 /** 2961 * atl2_check_options - Range Checking for Command Line Parameters 2962 * @adapter: board private structure 2963 * 2964 * This routine checks all command line parameters for valid user 2965 * input. If an invalid value is given, or if no user specified 2966 * value exists, a default value is used. The final value is stored 2967 * in a variable in the adapter structure. 2968 */ 2969 static void atl2_check_options(struct atl2_adapter *adapter) 2970 { 2971 int val; 2972 struct atl2_option opt; 2973 int bd = adapter->bd_number; 2974 if (bd >= ATL2_MAX_NIC) { 2975 printk(KERN_NOTICE "Warning: no configuration for board #%i\n", 2976 bd); 2977 printk(KERN_NOTICE "Using defaults for all values\n"); 2978 #ifndef module_param_array 2979 bd = ATL2_MAX_NIC; 2980 #endif 2981 } 2982 2983 /* Bytes of Transmit Memory */ 2984 opt.type = range_option; 2985 opt.name = "Bytes of Transmit Memory"; 2986 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE); 2987 opt.def = ATL2_DEFAULT_TX_MEMSIZE; 2988 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE; 2989 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE; 2990 #ifdef module_param_array 2991 if (num_TxMemSize > bd) { 2992 #endif 2993 val = TxMemSize[bd]; 2994 atl2_validate_option(&val, &opt); 2995 adapter->txd_ring_size = ((u32) val) * 1024; 2996 #ifdef module_param_array 2997 } else 2998 adapter->txd_ring_size = ((u32)opt.def) * 1024; 2999 #endif 3000 /* txs ring size: */ 3001 adapter->txs_ring_size = adapter->txd_ring_size / 128; 3002 if (adapter->txs_ring_size > 160) 3003 adapter->txs_ring_size = 160; 3004 3005 /* Receive Memory Block Count */ 3006 opt.type = range_option; 3007 opt.name = "Number of receive memory block"; 3008 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT); 3009 opt.def = ATL2_DEFAULT_RXD_COUNT; 3010 opt.arg.r.min = ATL2_MIN_RXD_COUNT; 3011 opt.arg.r.max = ATL2_MAX_RXD_COUNT; 3012 #ifdef module_param_array 3013 if (num_RxMemBlock > bd) { 3014 #endif 3015 val = RxMemBlock[bd]; 3016 atl2_validate_option(&val, &opt); 3017 adapter->rxd_ring_size = (u32)val; 3018 /* FIXME */ 3019 /* ((u16)val)&~1; */ /* even number */ 3020 #ifdef module_param_array 3021 } else 3022 adapter->rxd_ring_size = (u32)opt.def; 3023 #endif 3024 /* init RXD Flow control value */ 3025 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7; 3026 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) > 3027 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) : 3028 (adapter->rxd_ring_size / 12); 3029 3030 /* Interrupt Moderate Timer */ 3031 opt.type = range_option; 3032 opt.name = "Interrupt Moderate Timer"; 3033 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT); 3034 opt.def = INT_MOD_DEFAULT_CNT; 3035 opt.arg.r.min = INT_MOD_MIN_CNT; 3036 opt.arg.r.max = INT_MOD_MAX_CNT; 3037 #ifdef module_param_array 3038 if (num_IntModTimer > bd) { 3039 #endif 3040 val = IntModTimer[bd]; 3041 atl2_validate_option(&val, &opt); 3042 adapter->imt = (u16) val; 3043 #ifdef module_param_array 3044 } else 3045 adapter->imt = (u16)(opt.def); 3046 #endif 3047 /* Flash Vendor */ 3048 opt.type = range_option; 3049 opt.name = "SPI Flash Vendor"; 3050 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT); 3051 opt.def = FLASH_VENDOR_DEFAULT; 3052 opt.arg.r.min = FLASH_VENDOR_MIN; 3053 opt.arg.r.max = FLASH_VENDOR_MAX; 3054 #ifdef module_param_array 3055 if (num_FlashVendor > bd) { 3056 #endif 3057 val = FlashVendor[bd]; 3058 atl2_validate_option(&val, &opt); 3059 adapter->hw.flash_vendor = (u8) val; 3060 #ifdef module_param_array 3061 } else 3062 adapter->hw.flash_vendor = (u8)(opt.def); 3063 #endif 3064 /* MediaType */ 3065 opt.type = range_option; 3066 opt.name = "Speed/Duplex Selection"; 3067 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR); 3068 opt.def = MEDIA_TYPE_AUTO_SENSOR; 3069 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR; 3070 opt.arg.r.max = MEDIA_TYPE_10M_HALF; 3071 #ifdef module_param_array 3072 if (num_MediaType > bd) { 3073 #endif 3074 val = MediaType[bd]; 3075 atl2_validate_option(&val, &opt); 3076 adapter->hw.MediaType = (u16) val; 3077 #ifdef module_param_array 3078 } else 3079 adapter->hw.MediaType = (u16)(opt.def); 3080 #endif 3081 } 3082