11a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 22b133ad6SJeff Kirsher /* 32b133ad6SJeff Kirsher * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. 42b133ad6SJeff Kirsher * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com> 52b133ad6SJeff Kirsher * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com> 62b133ad6SJeff Kirsher * 72b133ad6SJeff Kirsher * Derived from Intel e1000 driver 82b133ad6SJeff Kirsher * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 92b133ad6SJeff Kirsher */ 102b133ad6SJeff Kirsher 112b133ad6SJeff Kirsher #ifndef ATL1_H 122b133ad6SJeff Kirsher #define ATL1_H 132b133ad6SJeff Kirsher 142b133ad6SJeff Kirsher #include <linux/compiler.h> 152b133ad6SJeff Kirsher #include <linux/ethtool.h> 162b133ad6SJeff Kirsher #include <linux/if_vlan.h> 172b133ad6SJeff Kirsher #include <linux/mii.h> 182b133ad6SJeff Kirsher #include <linux/module.h> 192b133ad6SJeff Kirsher #include <linux/skbuff.h> 202b133ad6SJeff Kirsher #include <linux/spinlock.h> 212b133ad6SJeff Kirsher #include <linux/timer.h> 222b133ad6SJeff Kirsher #include <linux/types.h> 232b133ad6SJeff Kirsher #include <linux/workqueue.h> 242b133ad6SJeff Kirsher 252b133ad6SJeff Kirsher #include "atlx.h" 262b133ad6SJeff Kirsher 272b133ad6SJeff Kirsher #define ATLX_DRIVER_NAME "atl1" 282b133ad6SJeff Kirsher 292b133ad6SJeff Kirsher MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver"); 302b133ad6SJeff Kirsher 312b133ad6SJeff Kirsher #define atlx_adapter atl1_adapter 322b133ad6SJeff Kirsher #define atlx_check_for_link atl1_check_for_link 332b133ad6SJeff Kirsher #define atlx_check_link atl1_check_link 342b133ad6SJeff Kirsher #define atlx_hash_mc_addr atl1_hash_mc_addr 352b133ad6SJeff Kirsher #define atlx_hash_set atl1_hash_set 362b133ad6SJeff Kirsher #define atlx_hw atl1_hw 372b133ad6SJeff Kirsher #define atlx_mii_ioctl atl1_mii_ioctl 382b133ad6SJeff Kirsher #define atlx_read_phy_reg atl1_read_phy_reg 392b133ad6SJeff Kirsher #define atlx_set_mac atl1_set_mac 402b133ad6SJeff Kirsher #define atlx_set_mac_addr atl1_set_mac_addr 412b133ad6SJeff Kirsher 422b133ad6SJeff Kirsher struct atl1_adapter; 432b133ad6SJeff Kirsher struct atl1_hw; 442b133ad6SJeff Kirsher 452b133ad6SJeff Kirsher /* function prototypes needed by multiple files */ 462b133ad6SJeff Kirsher static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr); 472b133ad6SJeff Kirsher static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value); 482b133ad6SJeff Kirsher static void atl1_set_mac_addr(struct atl1_hw *hw); 492b133ad6SJeff Kirsher static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 502b133ad6SJeff Kirsher int cmd); 512b133ad6SJeff Kirsher static u32 atl1_check_link(struct atl1_adapter *adapter); 522b133ad6SJeff Kirsher 532b133ad6SJeff Kirsher /* hardware definitions specific to L1 */ 542b133ad6SJeff Kirsher 552b133ad6SJeff Kirsher /* Block IDLE Status Register */ 562b133ad6SJeff Kirsher #define IDLE_STATUS_RXMAC 0x1 572b133ad6SJeff Kirsher #define IDLE_STATUS_TXMAC 0x2 582b133ad6SJeff Kirsher #define IDLE_STATUS_RXQ 0x4 592b133ad6SJeff Kirsher #define IDLE_STATUS_TXQ 0x8 602b133ad6SJeff Kirsher #define IDLE_STATUS_DMAR 0x10 612b133ad6SJeff Kirsher #define IDLE_STATUS_DMAW 0x20 622b133ad6SJeff Kirsher #define IDLE_STATUS_SMB 0x40 632b133ad6SJeff Kirsher #define IDLE_STATUS_CMB 0x80 642b133ad6SJeff Kirsher 652b133ad6SJeff Kirsher /* MDIO Control Register */ 662b133ad6SJeff Kirsher #define MDIO_WAIT_TIMES 30 672b133ad6SJeff Kirsher 682b133ad6SJeff Kirsher /* MAC Control Register */ 692b133ad6SJeff Kirsher #define MAC_CTRL_TX_PAUSE 0x10000 702b133ad6SJeff Kirsher #define MAC_CTRL_SCNT 0x20000 712b133ad6SJeff Kirsher #define MAC_CTRL_SRST_TX 0x40000 722b133ad6SJeff Kirsher #define MAC_CTRL_TX_SIMURST 0x80000 732b133ad6SJeff Kirsher #define MAC_CTRL_SPEED_SHIFT 20 742b133ad6SJeff Kirsher #define MAC_CTRL_SPEED_MASK 0x300000 752b133ad6SJeff Kirsher #define MAC_CTRL_SPEED_1000 0x2 762b133ad6SJeff Kirsher #define MAC_CTRL_SPEED_10_100 0x1 772b133ad6SJeff Kirsher #define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 782b133ad6SJeff Kirsher #define MAC_CTRL_TX_HUGE 0x800000 792b133ad6SJeff Kirsher #define MAC_CTRL_RX_CHKSUM_EN 0x1000000 802b133ad6SJeff Kirsher #define MAC_CTRL_DBG 0x8000000 812b133ad6SJeff Kirsher 822b133ad6SJeff Kirsher /* Wake-On-Lan control register */ 832b133ad6SJeff Kirsher #define WOL_CLK_SWITCH_EN 0x8000 842b133ad6SJeff Kirsher #define WOL_PT5_EN 0x200000 852b133ad6SJeff Kirsher #define WOL_PT6_EN 0x400000 862b133ad6SJeff Kirsher #define WOL_PT5_MATCH 0x8000000 872b133ad6SJeff Kirsher #define WOL_PT6_MATCH 0x10000000 882b133ad6SJeff Kirsher 892b133ad6SJeff Kirsher /* WOL Length ( 2 DWORD ) */ 902b133ad6SJeff Kirsher #define REG_WOL_PATTERN_LEN 0x14A4 912b133ad6SJeff Kirsher #define WOL_PT_LEN_MASK 0x7F 922b133ad6SJeff Kirsher #define WOL_PT0_LEN_SHIFT 0 932b133ad6SJeff Kirsher #define WOL_PT1_LEN_SHIFT 8 942b133ad6SJeff Kirsher #define WOL_PT2_LEN_SHIFT 16 952b133ad6SJeff Kirsher #define WOL_PT3_LEN_SHIFT 24 962b133ad6SJeff Kirsher #define WOL_PT4_LEN_SHIFT 0 972b133ad6SJeff Kirsher #define WOL_PT5_LEN_SHIFT 8 982b133ad6SJeff Kirsher #define WOL_PT6_LEN_SHIFT 16 992b133ad6SJeff Kirsher 1002b133ad6SJeff Kirsher /* Internal SRAM Partition Registers, low 32 bits */ 1012b133ad6SJeff Kirsher #define REG_SRAM_RFD_LEN 0x1504 1022b133ad6SJeff Kirsher #define REG_SRAM_RRD_ADDR 0x1508 1032b133ad6SJeff Kirsher #define REG_SRAM_RRD_LEN 0x150C 1042b133ad6SJeff Kirsher #define REG_SRAM_TPD_ADDR 0x1510 1052b133ad6SJeff Kirsher #define REG_SRAM_TPD_LEN 0x1514 1062b133ad6SJeff Kirsher #define REG_SRAM_TRD_ADDR 0x1518 1072b133ad6SJeff Kirsher #define REG_SRAM_TRD_LEN 0x151C 1082b133ad6SJeff Kirsher #define REG_SRAM_RXF_ADDR 0x1520 1092b133ad6SJeff Kirsher #define REG_SRAM_RXF_LEN 0x1524 1102b133ad6SJeff Kirsher #define REG_SRAM_TXF_ADDR 0x1528 1112b133ad6SJeff Kirsher #define REG_SRAM_TXF_LEN 0x152C 1122b133ad6SJeff Kirsher #define REG_SRAM_TCPH_PATH_ADDR 0x1530 1132b133ad6SJeff Kirsher #define SRAM_TCPH_ADDR_MASK 0xFFF 1142b133ad6SJeff Kirsher #define SRAM_TCPH_ADDR_SHIFT 0 1152b133ad6SJeff Kirsher #define SRAM_PATH_ADDR_MASK 0xFFF 1162b133ad6SJeff Kirsher #define SRAM_PATH_ADDR_SHIFT 16 1172b133ad6SJeff Kirsher 1182b133ad6SJeff Kirsher /* Load Ptr Register */ 1192b133ad6SJeff Kirsher #define REG_LOAD_PTR 0x1534 1202b133ad6SJeff Kirsher 1212b133ad6SJeff Kirsher /* Descriptor Control registers, low 32 bits */ 1222b133ad6SJeff Kirsher #define REG_DESC_RFD_ADDR_LO 0x1544 1232b133ad6SJeff Kirsher #define REG_DESC_RRD_ADDR_LO 0x1548 1242b133ad6SJeff Kirsher #define REG_DESC_TPD_ADDR_LO 0x154C 1252b133ad6SJeff Kirsher #define REG_DESC_CMB_ADDR_LO 0x1550 1262b133ad6SJeff Kirsher #define REG_DESC_SMB_ADDR_LO 0x1554 1272b133ad6SJeff Kirsher #define REG_DESC_RFD_RRD_RING_SIZE 0x1558 1282b133ad6SJeff Kirsher #define DESC_RFD_RING_SIZE_MASK 0x7FF 1292b133ad6SJeff Kirsher #define DESC_RFD_RING_SIZE_SHIFT 0 1302b133ad6SJeff Kirsher #define DESC_RRD_RING_SIZE_MASK 0x7FF 1312b133ad6SJeff Kirsher #define DESC_RRD_RING_SIZE_SHIFT 16 1322b133ad6SJeff Kirsher #define REG_DESC_TPD_RING_SIZE 0x155C 1332b133ad6SJeff Kirsher #define DESC_TPD_RING_SIZE_MASK 0x3FF 1342b133ad6SJeff Kirsher #define DESC_TPD_RING_SIZE_SHIFT 0 1352b133ad6SJeff Kirsher 1362b133ad6SJeff Kirsher /* TXQ Control Register */ 1372b133ad6SJeff Kirsher #define REG_TXQ_CTRL 0x1580 1382b133ad6SJeff Kirsher #define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0 1392b133ad6SJeff Kirsher #define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1F 1402b133ad6SJeff Kirsher #define TXQ_CTRL_EN 0x20 1412b133ad6SJeff Kirsher #define TXQ_CTRL_ENH_MODE 0x40 1422b133ad6SJeff Kirsher #define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8 1432b133ad6SJeff Kirsher #define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3F 1442b133ad6SJeff Kirsher #define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 1452b133ad6SJeff Kirsher #define TXQ_CTRL_TXF_BURST_NUM_MASK 0xFFFF 1462b133ad6SJeff Kirsher 1472b133ad6SJeff Kirsher /* Jumbo packet Threshold for task offload */ 1482b133ad6SJeff Kirsher #define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584 1492b133ad6SJeff Kirsher #define TX_JUMBO_TASK_TH_MASK 0x7FF 1502b133ad6SJeff Kirsher #define TX_JUMBO_TASK_TH_SHIFT 0 1512b133ad6SJeff Kirsher #define TX_TPD_MIN_IPG_MASK 0x1F 1522b133ad6SJeff Kirsher #define TX_TPD_MIN_IPG_SHIFT 16 1532b133ad6SJeff Kirsher 1542b133ad6SJeff Kirsher /* RXQ Control Register */ 1552b133ad6SJeff Kirsher #define REG_RXQ_CTRL 0x15A0 1562b133ad6SJeff Kirsher #define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0 1572b133ad6SJeff Kirsher #define RXQ_CTRL_RFD_BURST_NUM_MASK 0xFF 1582b133ad6SJeff Kirsher #define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8 1592b133ad6SJeff Kirsher #define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xFF 1602b133ad6SJeff Kirsher #define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16 1612b133ad6SJeff Kirsher #define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1F 1622b133ad6SJeff Kirsher #define RXQ_CTRL_CUT_THRU_EN 0x40000000 1632b133ad6SJeff Kirsher #define RXQ_CTRL_EN 0x80000000 1642b133ad6SJeff Kirsher 1652b133ad6SJeff Kirsher /* Rx jumbo packet threshold and rrd retirement timer */ 1662b133ad6SJeff Kirsher #define REG_RXQ_JMBOSZ_RRDTIM 0x15A4 1672b133ad6SJeff Kirsher #define RXQ_JMBOSZ_TH_MASK 0x7FF 1682b133ad6SJeff Kirsher #define RXQ_JMBOSZ_TH_SHIFT 0 1692b133ad6SJeff Kirsher #define RXQ_JMBO_LKAH_MASK 0xF 1702b133ad6SJeff Kirsher #define RXQ_JMBO_LKAH_SHIFT 11 1712b133ad6SJeff Kirsher #define RXQ_RRD_TIMER_MASK 0xFFFF 1722b133ad6SJeff Kirsher #define RXQ_RRD_TIMER_SHIFT 16 1732b133ad6SJeff Kirsher 1742b133ad6SJeff Kirsher /* RFD flow control register */ 1752b133ad6SJeff Kirsher #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8 1762b133ad6SJeff Kirsher #define RXQ_RXF_PAUSE_TH_HI_SHIFT 16 1772b133ad6SJeff Kirsher #define RXQ_RXF_PAUSE_TH_HI_MASK 0xFFF 1782b133ad6SJeff Kirsher #define RXQ_RXF_PAUSE_TH_LO_SHIFT 0 1792b133ad6SJeff Kirsher #define RXQ_RXF_PAUSE_TH_LO_MASK 0xFFF 1802b133ad6SJeff Kirsher 1812b133ad6SJeff Kirsher /* RRD flow control register */ 1822b133ad6SJeff Kirsher #define REG_RXQ_RRD_PAUSE_THRESH 0x15AC 1832b133ad6SJeff Kirsher #define RXQ_RRD_PAUSE_TH_HI_SHIFT 0 1842b133ad6SJeff Kirsher #define RXQ_RRD_PAUSE_TH_HI_MASK 0xFFF 1852b133ad6SJeff Kirsher #define RXQ_RRD_PAUSE_TH_LO_SHIFT 16 1862b133ad6SJeff Kirsher #define RXQ_RRD_PAUSE_TH_LO_MASK 0xFFF 1872b133ad6SJeff Kirsher 1882b133ad6SJeff Kirsher /* DMA Engine Control Register */ 1892b133ad6SJeff Kirsher #define REG_DMA_CTRL 0x15C0 1902b133ad6SJeff Kirsher #define DMA_CTRL_DMAR_IN_ORDER 0x1 1912b133ad6SJeff Kirsher #define DMA_CTRL_DMAR_ENH_ORDER 0x2 1922b133ad6SJeff Kirsher #define DMA_CTRL_DMAR_OUT_ORDER 0x4 1932b133ad6SJeff Kirsher #define DMA_CTRL_RCB_VALUE 0x8 1942b133ad6SJeff Kirsher #define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4 1952b133ad6SJeff Kirsher #define DMA_CTRL_DMAR_BURST_LEN_MASK 7 1962b133ad6SJeff Kirsher #define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7 1972b133ad6SJeff Kirsher #define DMA_CTRL_DMAW_BURST_LEN_MASK 7 1982b133ad6SJeff Kirsher #define DMA_CTRL_DMAR_EN 0x400 1992b133ad6SJeff Kirsher #define DMA_CTRL_DMAW_EN 0x800 2002b133ad6SJeff Kirsher 2012b133ad6SJeff Kirsher /* CMB/SMB Control Register */ 2022b133ad6SJeff Kirsher #define REG_CSMB_CTRL 0x15D0 2032b133ad6SJeff Kirsher #define CSMB_CTRL_CMB_NOW 1 2042b133ad6SJeff Kirsher #define CSMB_CTRL_SMB_NOW 2 2052b133ad6SJeff Kirsher #define CSMB_CTRL_CMB_EN 4 2062b133ad6SJeff Kirsher #define CSMB_CTRL_SMB_EN 8 2072b133ad6SJeff Kirsher 2082b133ad6SJeff Kirsher /* CMB DMA Write Threshold Register */ 2092b133ad6SJeff Kirsher #define REG_CMB_WRITE_TH 0x15D4 2102b133ad6SJeff Kirsher #define CMB_RRD_TH_SHIFT 0 2112b133ad6SJeff Kirsher #define CMB_RRD_TH_MASK 0x7FF 2122b133ad6SJeff Kirsher #define CMB_TPD_TH_SHIFT 16 2132b133ad6SJeff Kirsher #define CMB_TPD_TH_MASK 0x7FF 2142b133ad6SJeff Kirsher 2152b133ad6SJeff Kirsher /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */ 2162b133ad6SJeff Kirsher #define REG_CMB_WRITE_TIMER 0x15D8 2172b133ad6SJeff Kirsher #define CMB_RX_TM_SHIFT 0 2182b133ad6SJeff Kirsher #define CMB_RX_TM_MASK 0xFFFF 2192b133ad6SJeff Kirsher #define CMB_TX_TM_SHIFT 16 2202b133ad6SJeff Kirsher #define CMB_TX_TM_MASK 0xFFFF 2212b133ad6SJeff Kirsher 2222b133ad6SJeff Kirsher /* Number of packet received since last CMB write */ 2232b133ad6SJeff Kirsher #define REG_CMB_RX_PKT_CNT 0x15DC 2242b133ad6SJeff Kirsher 2252b133ad6SJeff Kirsher /* Number of packet transmitted since last CMB write */ 2262b133ad6SJeff Kirsher #define REG_CMB_TX_PKT_CNT 0x15E0 2272b133ad6SJeff Kirsher 2282b133ad6SJeff Kirsher /* SMB auto DMA timer register */ 2292b133ad6SJeff Kirsher #define REG_SMB_TIMER 0x15E4 2302b133ad6SJeff Kirsher 2312b133ad6SJeff Kirsher /* Mailbox Register */ 2322b133ad6SJeff Kirsher #define REG_MAILBOX 0x15F0 2332b133ad6SJeff Kirsher #define MB_RFD_PROD_INDX_SHIFT 0 2342b133ad6SJeff Kirsher #define MB_RFD_PROD_INDX_MASK 0x7FF 2352b133ad6SJeff Kirsher #define MB_RRD_CONS_INDX_SHIFT 11 2362b133ad6SJeff Kirsher #define MB_RRD_CONS_INDX_MASK 0x7FF 2372b133ad6SJeff Kirsher #define MB_TPD_PROD_INDX_SHIFT 22 2382b133ad6SJeff Kirsher #define MB_TPD_PROD_INDX_MASK 0x3FF 2392b133ad6SJeff Kirsher 2402b133ad6SJeff Kirsher /* Interrupt Status Register */ 2412b133ad6SJeff Kirsher #define ISR_SMB 0x1 2422b133ad6SJeff Kirsher #define ISR_TIMER 0x2 2432b133ad6SJeff Kirsher #define ISR_MANUAL 0x4 2442b133ad6SJeff Kirsher #define ISR_RXF_OV 0x8 2452b133ad6SJeff Kirsher #define ISR_RFD_UNRUN 0x10 2462b133ad6SJeff Kirsher #define ISR_RRD_OV 0x20 2472b133ad6SJeff Kirsher #define ISR_TXF_UNRUN 0x40 2482b133ad6SJeff Kirsher #define ISR_LINK 0x80 2492b133ad6SJeff Kirsher #define ISR_HOST_RFD_UNRUN 0x100 2502b133ad6SJeff Kirsher #define ISR_HOST_RRD_OV 0x200 2512b133ad6SJeff Kirsher #define ISR_DMAR_TO_RST 0x400 2522b133ad6SJeff Kirsher #define ISR_DMAW_TO_RST 0x800 2532b133ad6SJeff Kirsher #define ISR_GPHY 0x1000 2542b133ad6SJeff Kirsher #define ISR_RX_PKT 0x10000 2552b133ad6SJeff Kirsher #define ISR_TX_PKT 0x20000 2562b133ad6SJeff Kirsher #define ISR_TX_DMA 0x40000 2572b133ad6SJeff Kirsher #define ISR_RX_DMA 0x80000 2582b133ad6SJeff Kirsher #define ISR_CMB_RX 0x100000 2592b133ad6SJeff Kirsher #define ISR_CMB_TX 0x200000 2602b133ad6SJeff Kirsher #define ISR_MAC_RX 0x400000 2612b133ad6SJeff Kirsher #define ISR_MAC_TX 0x800000 2622b133ad6SJeff Kirsher #define ISR_DIS_SMB 0x20000000 2632b133ad6SJeff Kirsher #define ISR_DIS_DMA 0x40000000 2642b133ad6SJeff Kirsher 26573650f28STony Zelenoff /* Normal Interrupt mask without RX/TX enabled */ 26673650f28STony Zelenoff #define IMR_NORXTX_MASK (\ 2672b133ad6SJeff Kirsher ISR_SMB |\ 2682b133ad6SJeff Kirsher ISR_GPHY |\ 2692b133ad6SJeff Kirsher ISR_PHY_LINKDOWN|\ 2702b133ad6SJeff Kirsher ISR_DMAR_TO_RST |\ 27173650f28STony Zelenoff ISR_DMAW_TO_RST) 27273650f28STony Zelenoff 27373650f28STony Zelenoff /* Normal Interrupt mask */ 27473650f28STony Zelenoff #define IMR_NORMAL_MASK (\ 27573650f28STony Zelenoff IMR_NORXTX_MASK |\ 2762b133ad6SJeff Kirsher ISR_CMB_TX |\ 2772b133ad6SJeff Kirsher ISR_CMB_RX) 2782b133ad6SJeff Kirsher 2792b133ad6SJeff Kirsher /* Debug Interrupt Mask (enable all interrupt) */ 2802b133ad6SJeff Kirsher #define IMR_DEBUG_MASK (\ 2812b133ad6SJeff Kirsher ISR_SMB |\ 2822b133ad6SJeff Kirsher ISR_TIMER |\ 2832b133ad6SJeff Kirsher ISR_MANUAL |\ 2842b133ad6SJeff Kirsher ISR_RXF_OV |\ 2852b133ad6SJeff Kirsher ISR_RFD_UNRUN |\ 2862b133ad6SJeff Kirsher ISR_RRD_OV |\ 2872b133ad6SJeff Kirsher ISR_TXF_UNRUN |\ 2882b133ad6SJeff Kirsher ISR_LINK |\ 2892b133ad6SJeff Kirsher ISR_CMB_TX |\ 2902b133ad6SJeff Kirsher ISR_CMB_RX |\ 2912b133ad6SJeff Kirsher ISR_RX_PKT |\ 2922b133ad6SJeff Kirsher ISR_TX_PKT |\ 2932b133ad6SJeff Kirsher ISR_MAC_RX |\ 2942b133ad6SJeff Kirsher ISR_MAC_TX) 2952b133ad6SJeff Kirsher 2962b133ad6SJeff Kirsher #define MEDIA_TYPE_1000M_FULL 1 2972b133ad6SJeff Kirsher #define MEDIA_TYPE_100M_FULL 2 2982b133ad6SJeff Kirsher #define MEDIA_TYPE_100M_HALF 3 2992b133ad6SJeff Kirsher #define MEDIA_TYPE_10M_FULL 4 3002b133ad6SJeff Kirsher #define MEDIA_TYPE_10M_HALF 5 3012b133ad6SJeff Kirsher 3022b133ad6SJeff Kirsher #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */ 3032b133ad6SJeff Kirsher 3042b133ad6SJeff Kirsher #define MAX_JUMBO_FRAME_SIZE 10240 3052b133ad6SJeff Kirsher 3062b133ad6SJeff Kirsher #define ATL1_EEDUMP_LEN 48 3072b133ad6SJeff Kirsher 3082b133ad6SJeff Kirsher /* Statistics counters collected by the MAC */ 3092b133ad6SJeff Kirsher struct stats_msg_block { 3102b133ad6SJeff Kirsher /* rx */ 3112b133ad6SJeff Kirsher u32 rx_ok; /* good RX packets */ 3122b133ad6SJeff Kirsher u32 rx_bcast; /* good RX broadcast packets */ 3132b133ad6SJeff Kirsher u32 rx_mcast; /* good RX multicast packets */ 3142b133ad6SJeff Kirsher u32 rx_pause; /* RX pause frames */ 3152b133ad6SJeff Kirsher u32 rx_ctrl; /* RX control packets other than pause frames */ 3162b133ad6SJeff Kirsher u32 rx_fcs_err; /* RX packets with bad FCS */ 3172b133ad6SJeff Kirsher u32 rx_len_err; /* RX packets with length != actual size */ 3182b133ad6SJeff Kirsher u32 rx_byte_cnt; /* good bytes received. FCS is NOT included */ 3192b133ad6SJeff Kirsher u32 rx_runt; /* RX packets < 64 bytes with good FCS */ 3202b133ad6SJeff Kirsher u32 rx_frag; /* RX packets < 64 bytes with bad FCS */ 3212b133ad6SJeff Kirsher u32 rx_sz_64; /* 64 byte RX packets */ 3222b133ad6SJeff Kirsher u32 rx_sz_65_127; 3232b133ad6SJeff Kirsher u32 rx_sz_128_255; 3242b133ad6SJeff Kirsher u32 rx_sz_256_511; 3252b133ad6SJeff Kirsher u32 rx_sz_512_1023; 3262b133ad6SJeff Kirsher u32 rx_sz_1024_1518; 3272b133ad6SJeff Kirsher u32 rx_sz_1519_max; /* 1519 byte to MTU RX packets */ 3282b133ad6SJeff Kirsher u32 rx_sz_ov; /* truncated RX packets > MTU */ 3292b133ad6SJeff Kirsher u32 rx_rxf_ov; /* frames dropped due to RX FIFO overflow */ 3302b133ad6SJeff Kirsher u32 rx_rrd_ov; /* frames dropped due to RRD overflow */ 3312b133ad6SJeff Kirsher u32 rx_align_err; /* alignment errors */ 3322b133ad6SJeff Kirsher u32 rx_bcast_byte_cnt; /* RX broadcast bytes, excluding FCS */ 3332b133ad6SJeff Kirsher u32 rx_mcast_byte_cnt; /* RX multicast bytes, excluding FCS */ 3342b133ad6SJeff Kirsher u32 rx_err_addr; /* packets dropped due to address filtering */ 3352b133ad6SJeff Kirsher 3362b133ad6SJeff Kirsher /* tx */ 3372b133ad6SJeff Kirsher u32 tx_ok; /* good TX packets */ 3382b133ad6SJeff Kirsher u32 tx_bcast; /* good TX broadcast packets */ 3392b133ad6SJeff Kirsher u32 tx_mcast; /* good TX multicast packets */ 3402b133ad6SJeff Kirsher u32 tx_pause; /* TX pause frames */ 3412b133ad6SJeff Kirsher u32 tx_exc_defer; /* TX packets deferred excessively */ 3422b133ad6SJeff Kirsher u32 tx_ctrl; /* TX control frames, excluding pause frames */ 3432b133ad6SJeff Kirsher u32 tx_defer; /* TX packets deferred */ 3442b133ad6SJeff Kirsher u32 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */ 3452b133ad6SJeff Kirsher u32 tx_sz_64; /* 64 byte TX packets */ 3462b133ad6SJeff Kirsher u32 tx_sz_65_127; 3472b133ad6SJeff Kirsher u32 tx_sz_128_255; 3482b133ad6SJeff Kirsher u32 tx_sz_256_511; 3492b133ad6SJeff Kirsher u32 tx_sz_512_1023; 3502b133ad6SJeff Kirsher u32 tx_sz_1024_1518; 3512b133ad6SJeff Kirsher u32 tx_sz_1519_max; /* 1519 byte to MTU TX packets */ 3522b133ad6SJeff Kirsher u32 tx_1_col; /* packets TX after a single collision */ 3532b133ad6SJeff Kirsher u32 tx_2_col; /* packets TX after multiple collisions */ 3542b133ad6SJeff Kirsher u32 tx_late_col; /* TX packets with late collisions */ 3552b133ad6SJeff Kirsher u32 tx_abort_col; /* TX packets aborted w/excessive collisions */ 3562b133ad6SJeff Kirsher u32 tx_underrun; /* TX packets aborted due to TX FIFO underrun 3572b133ad6SJeff Kirsher * or TRD FIFO underrun */ 3582b133ad6SJeff Kirsher u32 tx_rd_eop; /* reads beyond the EOP into the next frame 3592b133ad6SJeff Kirsher * when TRD was not written timely */ 3602b133ad6SJeff Kirsher u32 tx_len_err; /* TX packets where length != actual size */ 3612b133ad6SJeff Kirsher u32 tx_trunc; /* TX packets truncated due to size > MTU */ 3622b133ad6SJeff Kirsher u32 tx_bcast_byte; /* broadcast bytes transmitted, excluding FCS */ 3632b133ad6SJeff Kirsher u32 tx_mcast_byte; /* multicast bytes transmitted, excluding FCS */ 3642b133ad6SJeff Kirsher u32 smb_updated; /* 1: SMB Updated. This is used by software to 3652b133ad6SJeff Kirsher * indicate the statistics update. Software 3662b133ad6SJeff Kirsher * should clear this bit after retrieving the 3672b133ad6SJeff Kirsher * statistics information. */ 3682b133ad6SJeff Kirsher }; 3692b133ad6SJeff Kirsher 3702b133ad6SJeff Kirsher /* Coalescing Message Block */ 3712b133ad6SJeff Kirsher struct coals_msg_block { 3722b133ad6SJeff Kirsher u32 int_stats; /* interrupt status */ 3732b133ad6SJeff Kirsher u16 rrd_prod_idx; /* TRD Producer Index. */ 3742b133ad6SJeff Kirsher u16 rfd_cons_idx; /* RFD Consumer Index. */ 3752b133ad6SJeff Kirsher u16 update; /* Selene sets this bit every time it DMAs the 3762b133ad6SJeff Kirsher * CMB to host memory. Software should clear 3772b133ad6SJeff Kirsher * this bit when CMB info is processed. */ 3782b133ad6SJeff Kirsher u16 tpd_cons_idx; /* TPD Consumer Index. */ 3792b133ad6SJeff Kirsher }; 3802b133ad6SJeff Kirsher 3812b133ad6SJeff Kirsher /* RRD descriptor */ 3822b133ad6SJeff Kirsher struct rx_return_desc { 3832b133ad6SJeff Kirsher u8 num_buf; /* Number of RFD buffers used by the received packet */ 3842b133ad6SJeff Kirsher u8 resved; 3852b133ad6SJeff Kirsher u16 buf_indx; /* RFD Index of the first buffer */ 3862b133ad6SJeff Kirsher union { 3872b133ad6SJeff Kirsher u32 valid; 3882b133ad6SJeff Kirsher struct { 3892b133ad6SJeff Kirsher u16 rx_chksum; 3902b133ad6SJeff Kirsher u16 pkt_size; 3912b133ad6SJeff Kirsher } xsum_sz; 3922b133ad6SJeff Kirsher } xsz; 3932b133ad6SJeff Kirsher 3942b133ad6SJeff Kirsher u16 pkt_flg; /* Packet flags */ 3952b133ad6SJeff Kirsher u16 err_flg; /* Error flags */ 3962b133ad6SJeff Kirsher u16 resved2; 3972b133ad6SJeff Kirsher u16 vlan_tag; /* VLAN TAG */ 3982b133ad6SJeff Kirsher }; 3992b133ad6SJeff Kirsher 4002b133ad6SJeff Kirsher #define PACKET_FLAG_ETH_TYPE 0x0080 4012b133ad6SJeff Kirsher #define PACKET_FLAG_VLAN_INS 0x0100 4022b133ad6SJeff Kirsher #define PACKET_FLAG_ERR 0x0200 4032b133ad6SJeff Kirsher #define PACKET_FLAG_IPV4 0x0400 4042b133ad6SJeff Kirsher #define PACKET_FLAG_UDP 0x0800 4052b133ad6SJeff Kirsher #define PACKET_FLAG_TCP 0x1000 4062b133ad6SJeff Kirsher #define PACKET_FLAG_BCAST 0x2000 4072b133ad6SJeff Kirsher #define PACKET_FLAG_MCAST 0x4000 4082b133ad6SJeff Kirsher #define PACKET_FLAG_PAUSE 0x8000 4092b133ad6SJeff Kirsher 4102b133ad6SJeff Kirsher #define ERR_FLAG_CRC 0x0001 4112b133ad6SJeff Kirsher #define ERR_FLAG_CODE 0x0002 4122b133ad6SJeff Kirsher #define ERR_FLAG_DRIBBLE 0x0004 4132b133ad6SJeff Kirsher #define ERR_FLAG_RUNT 0x0008 4142b133ad6SJeff Kirsher #define ERR_FLAG_OV 0x0010 4152b133ad6SJeff Kirsher #define ERR_FLAG_TRUNC 0x0020 4162b133ad6SJeff Kirsher #define ERR_FLAG_IP_CHKSUM 0x0040 4172b133ad6SJeff Kirsher #define ERR_FLAG_L4_CHKSUM 0x0080 4182b133ad6SJeff Kirsher #define ERR_FLAG_LEN 0x0100 4192b133ad6SJeff Kirsher #define ERR_FLAG_DES_ADDR 0x0200 4202b133ad6SJeff Kirsher 4212b133ad6SJeff Kirsher /* RFD descriptor */ 4222b133ad6SJeff Kirsher struct rx_free_desc { 4232b133ad6SJeff Kirsher __le64 buffer_addr; /* Address of the descriptor's data buffer */ 4242b133ad6SJeff Kirsher __le16 buf_len; /* Size of the receive buffer in host memory */ 4252b133ad6SJeff Kirsher u16 coalese; /* Update consumer index to host after the 4262b133ad6SJeff Kirsher * reception of this frame */ 4272b133ad6SJeff Kirsher /* __packed is required */ 4282b133ad6SJeff Kirsher } __packed; 4292b133ad6SJeff Kirsher 4302b133ad6SJeff Kirsher /* 4312b133ad6SJeff Kirsher * The L1 transmit packet descriptor is comprised of four 32-bit words. 4322b133ad6SJeff Kirsher * 4332b133ad6SJeff Kirsher * 31 0 4342b133ad6SJeff Kirsher * +---------------------------------------+ 4352b133ad6SJeff Kirsher * | Word 0: Buffer addr lo | 4362b133ad6SJeff Kirsher * +---------------------------------------+ 4372b133ad6SJeff Kirsher * | Word 1: Buffer addr hi | 4382b133ad6SJeff Kirsher * +---------------------------------------+ 4392b133ad6SJeff Kirsher * | Word 2 | 4402b133ad6SJeff Kirsher * +---------------------------------------+ 4412b133ad6SJeff Kirsher * | Word 3 | 4422b133ad6SJeff Kirsher * +---------------------------------------+ 4432b133ad6SJeff Kirsher * 4442b133ad6SJeff Kirsher * Words 0 and 1 combine to form a 64-bit buffer address. 4452b133ad6SJeff Kirsher * 4462b133ad6SJeff Kirsher * Word 2 is self explanatory in the #define block below. 4472b133ad6SJeff Kirsher * 4482b133ad6SJeff Kirsher * Word 3 has two forms, depending upon the state of bits 3 and 4. 4492b133ad6SJeff Kirsher * If bits 3 and 4 are both zero, then bits 14:31 are unused by the 4502b133ad6SJeff Kirsher * hardware. Otherwise, if either bit 3 or 4 is set, the definition 4512b133ad6SJeff Kirsher * of bits 14:31 vary according to the following depiction. 4522b133ad6SJeff Kirsher * 4532b133ad6SJeff Kirsher * 0 End of packet 0 End of packet 4542b133ad6SJeff Kirsher * 1 Coalesce 1 Coalesce 4552b133ad6SJeff Kirsher * 2 Insert VLAN tag 2 Insert VLAN tag 4562b133ad6SJeff Kirsher * 3 Custom csum enable = 0 3 Custom csum enable = 1 4572b133ad6SJeff Kirsher * 4 Segment enable = 1 4 Segment enable = 0 4582b133ad6SJeff Kirsher * 5 Generate IP checksum 5 Generate IP checksum 4592b133ad6SJeff Kirsher * 6 Generate TCP checksum 6 Generate TCP checksum 4602b133ad6SJeff Kirsher * 7 Generate UDP checksum 7 Generate UDP checksum 4612b133ad6SJeff Kirsher * 8 VLAN tagged 8 VLAN tagged 4622b133ad6SJeff Kirsher * 9 Ethernet frame type 9 Ethernet frame type 4632b133ad6SJeff Kirsher * 10-+ 10-+ 4642b133ad6SJeff Kirsher * 11 | IP hdr length (10:13) 11 | IP hdr length (10:13) 4652b133ad6SJeff Kirsher * 12 | (num 32-bit words) 12 | (num 32-bit words) 4662b133ad6SJeff Kirsher * 13-+ 13-+ 4672b133ad6SJeff Kirsher * 14-+ 14 Unused 4682b133ad6SJeff Kirsher * 15 | TCP hdr length (14:17) 15 Unused 4692b133ad6SJeff Kirsher * 16 | (num 32-bit words) 16-+ 4702b133ad6SJeff Kirsher * 17-+ 17 | 4712b133ad6SJeff Kirsher * 18 Header TPD flag 18 | 4722b133ad6SJeff Kirsher * 19-+ 19 | Payload offset 4732b133ad6SJeff Kirsher * 20 | 20 | (16:23) 4742b133ad6SJeff Kirsher * 21 | 21 | 4752b133ad6SJeff Kirsher * 22 | 22 | 4762b133ad6SJeff Kirsher * 23 | 23-+ 4772b133ad6SJeff Kirsher * 24 | 24-+ 4782b133ad6SJeff Kirsher * 25 | MSS (19:31) 25 | 4792b133ad6SJeff Kirsher * 26 | 26 | 4802b133ad6SJeff Kirsher * 27 | 27 | Custom csum offset 4812b133ad6SJeff Kirsher * 28 | 28 | (24:31) 4822b133ad6SJeff Kirsher * 29 | 29 | 4832b133ad6SJeff Kirsher * 30 | 30 | 4842b133ad6SJeff Kirsher * 31-+ 31-+ 4852b133ad6SJeff Kirsher */ 4862b133ad6SJeff Kirsher 4872b133ad6SJeff Kirsher /* tpd word 2 */ 4882b133ad6SJeff Kirsher #define TPD_BUFLEN_MASK 0x3FFF 4892b133ad6SJeff Kirsher #define TPD_BUFLEN_SHIFT 0 4902b133ad6SJeff Kirsher #define TPD_DMAINT_MASK 0x0001 4912b133ad6SJeff Kirsher #define TPD_DMAINT_SHIFT 14 4922b133ad6SJeff Kirsher #define TPD_PKTNT_MASK 0x0001 4932b133ad6SJeff Kirsher #define TPD_PKTINT_SHIFT 15 4942b133ad6SJeff Kirsher #define TPD_VLANTAG_MASK 0xFFFF 4952b133ad6SJeff Kirsher #define TPD_VLANTAG_SHIFT 16 4962b133ad6SJeff Kirsher 4972b133ad6SJeff Kirsher /* tpd word 3 bits 0:13 */ 4982b133ad6SJeff Kirsher #define TPD_EOP_MASK 0x0001 4992b133ad6SJeff Kirsher #define TPD_EOP_SHIFT 0 5002b133ad6SJeff Kirsher #define TPD_COALESCE_MASK 0x0001 5012b133ad6SJeff Kirsher #define TPD_COALESCE_SHIFT 1 5022b133ad6SJeff Kirsher #define TPD_INS_VL_TAG_MASK 0x0001 5032b133ad6SJeff Kirsher #define TPD_INS_VL_TAG_SHIFT 2 5042b133ad6SJeff Kirsher #define TPD_CUST_CSUM_EN_MASK 0x0001 5052b133ad6SJeff Kirsher #define TPD_CUST_CSUM_EN_SHIFT 3 5062b133ad6SJeff Kirsher #define TPD_SEGMENT_EN_MASK 0x0001 5072b133ad6SJeff Kirsher #define TPD_SEGMENT_EN_SHIFT 4 5082b133ad6SJeff Kirsher #define TPD_IP_CSUM_MASK 0x0001 5092b133ad6SJeff Kirsher #define TPD_IP_CSUM_SHIFT 5 5102b133ad6SJeff Kirsher #define TPD_TCP_CSUM_MASK 0x0001 5112b133ad6SJeff Kirsher #define TPD_TCP_CSUM_SHIFT 6 5122b133ad6SJeff Kirsher #define TPD_UDP_CSUM_MASK 0x0001 5132b133ad6SJeff Kirsher #define TPD_UDP_CSUM_SHIFT 7 5142b133ad6SJeff Kirsher #define TPD_VL_TAGGED_MASK 0x0001 5152b133ad6SJeff Kirsher #define TPD_VL_TAGGED_SHIFT 8 5162b133ad6SJeff Kirsher #define TPD_ETHTYPE_MASK 0x0001 5172b133ad6SJeff Kirsher #define TPD_ETHTYPE_SHIFT 9 5182b133ad6SJeff Kirsher #define TPD_IPHL_MASK 0x000F 5192b133ad6SJeff Kirsher #define TPD_IPHL_SHIFT 10 5202b133ad6SJeff Kirsher 5212b133ad6SJeff Kirsher /* tpd word 3 bits 14:31 if segment enabled */ 5222b133ad6SJeff Kirsher #define TPD_TCPHDRLEN_MASK 0x000F 5232b133ad6SJeff Kirsher #define TPD_TCPHDRLEN_SHIFT 14 5242b133ad6SJeff Kirsher #define TPD_HDRFLAG_MASK 0x0001 5252b133ad6SJeff Kirsher #define TPD_HDRFLAG_SHIFT 18 5262b133ad6SJeff Kirsher #define TPD_MSS_MASK 0x1FFF 5272b133ad6SJeff Kirsher #define TPD_MSS_SHIFT 19 5282b133ad6SJeff Kirsher 5292b133ad6SJeff Kirsher /* tpd word 3 bits 16:31 if custom csum enabled */ 5302b133ad6SJeff Kirsher #define TPD_PLOADOFFSET_MASK 0x00FF 5312b133ad6SJeff Kirsher #define TPD_PLOADOFFSET_SHIFT 16 5322b133ad6SJeff Kirsher #define TPD_CCSUMOFFSET_MASK 0x00FF 5332b133ad6SJeff Kirsher #define TPD_CCSUMOFFSET_SHIFT 24 5342b133ad6SJeff Kirsher 5352b133ad6SJeff Kirsher struct tx_packet_desc { 5362b133ad6SJeff Kirsher __le64 buffer_addr; 5372b133ad6SJeff Kirsher __le32 word2; 5382b133ad6SJeff Kirsher __le32 word3; 5392b133ad6SJeff Kirsher }; 5402b133ad6SJeff Kirsher 5412b133ad6SJeff Kirsher /* DMA Order Settings */ 5422b133ad6SJeff Kirsher enum atl1_dma_order { 5432b133ad6SJeff Kirsher atl1_dma_ord_in = 1, 5442b133ad6SJeff Kirsher atl1_dma_ord_enh = 2, 5452b133ad6SJeff Kirsher atl1_dma_ord_out = 4 5462b133ad6SJeff Kirsher }; 5472b133ad6SJeff Kirsher 5482b133ad6SJeff Kirsher enum atl1_dma_rcb { 5492b133ad6SJeff Kirsher atl1_rcb_64 = 0, 5502b133ad6SJeff Kirsher atl1_rcb_128 = 1 5512b133ad6SJeff Kirsher }; 5522b133ad6SJeff Kirsher 5532b133ad6SJeff Kirsher enum atl1_dma_req_block { 5542b133ad6SJeff Kirsher atl1_dma_req_128 = 0, 5552b133ad6SJeff Kirsher atl1_dma_req_256 = 1, 5562b133ad6SJeff Kirsher atl1_dma_req_512 = 2, 5572b133ad6SJeff Kirsher atl1_dma_req_1024 = 3, 5582b133ad6SJeff Kirsher atl1_dma_req_2048 = 4, 5592b133ad6SJeff Kirsher atl1_dma_req_4096 = 5 5602b133ad6SJeff Kirsher }; 5612b133ad6SJeff Kirsher 5622b133ad6SJeff Kirsher #define ATL1_MAX_INTR 3 5632b133ad6SJeff Kirsher #define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */ 5642b133ad6SJeff Kirsher 5652b133ad6SJeff Kirsher #define ATL1_DEFAULT_TPD 256 5662b133ad6SJeff Kirsher #define ATL1_MAX_TPD 1024 5672b133ad6SJeff Kirsher #define ATL1_MIN_TPD 64 5682b133ad6SJeff Kirsher #define ATL1_DEFAULT_RFD 512 5692b133ad6SJeff Kirsher #define ATL1_MIN_RFD 128 5702b133ad6SJeff Kirsher #define ATL1_MAX_RFD 2048 5712b133ad6SJeff Kirsher #define ATL1_REG_COUNT 1538 5722b133ad6SJeff Kirsher 5732b133ad6SJeff Kirsher #define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) 5742b133ad6SJeff Kirsher #define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc) 5752b133ad6SJeff Kirsher #define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc) 5762b133ad6SJeff Kirsher #define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc) 5772b133ad6SJeff Kirsher 5782b133ad6SJeff Kirsher /* 5792b133ad6SJeff Kirsher * atl1_ring_header represents a single, contiguous block of DMA space 5802b133ad6SJeff Kirsher * mapped for the three descriptor rings (tpd, rfd, rrd) and the two 5812b133ad6SJeff Kirsher * message blocks (cmb, smb) described below 5822b133ad6SJeff Kirsher */ 5832b133ad6SJeff Kirsher struct atl1_ring_header { 5842b133ad6SJeff Kirsher void *desc; /* virtual address */ 5852b133ad6SJeff Kirsher dma_addr_t dma; /* physical address*/ 5862b133ad6SJeff Kirsher unsigned int size; /* length in bytes */ 5872b133ad6SJeff Kirsher }; 5882b133ad6SJeff Kirsher 5892b133ad6SJeff Kirsher /* 5902b133ad6SJeff Kirsher * atl1_buffer is wrapper around a pointer to a socket buffer 5912b133ad6SJeff Kirsher * so a DMA handle can be stored along with the skb 5922b133ad6SJeff Kirsher */ 5932b133ad6SJeff Kirsher struct atl1_buffer { 5942b133ad6SJeff Kirsher struct sk_buff *skb; /* socket buffer */ 5952b133ad6SJeff Kirsher u16 length; /* rx buffer length */ 5962b133ad6SJeff Kirsher u16 alloced; /* 1 if skb allocated */ 5972b133ad6SJeff Kirsher dma_addr_t dma; 5982b133ad6SJeff Kirsher }; 5992b133ad6SJeff Kirsher 6002b133ad6SJeff Kirsher /* transmit packet descriptor (tpd) ring */ 6012b133ad6SJeff Kirsher struct atl1_tpd_ring { 6022b133ad6SJeff Kirsher void *desc; /* descriptor ring virtual address */ 6032b133ad6SJeff Kirsher dma_addr_t dma; /* descriptor ring physical address */ 6042b133ad6SJeff Kirsher u16 size; /* descriptor ring length in bytes */ 6052b133ad6SJeff Kirsher u16 count; /* number of descriptors in the ring */ 6062b133ad6SJeff Kirsher u16 hw_idx; /* hardware index */ 6072b133ad6SJeff Kirsher atomic_t next_to_clean; 6082b133ad6SJeff Kirsher atomic_t next_to_use; 6092b133ad6SJeff Kirsher struct atl1_buffer *buffer_info; 6102b133ad6SJeff Kirsher }; 6112b133ad6SJeff Kirsher 6122b133ad6SJeff Kirsher /* receive free descriptor (rfd) ring */ 6132b133ad6SJeff Kirsher struct atl1_rfd_ring { 6142b133ad6SJeff Kirsher void *desc; /* descriptor ring virtual address */ 6152b133ad6SJeff Kirsher dma_addr_t dma; /* descriptor ring physical address */ 6162b133ad6SJeff Kirsher u16 size; /* descriptor ring length in bytes */ 6172b133ad6SJeff Kirsher u16 count; /* number of descriptors in the ring */ 6182b133ad6SJeff Kirsher atomic_t next_to_use; 6192b133ad6SJeff Kirsher u16 next_to_clean; 6202b133ad6SJeff Kirsher struct atl1_buffer *buffer_info; 6212b133ad6SJeff Kirsher }; 6222b133ad6SJeff Kirsher 6232b133ad6SJeff Kirsher /* receive return descriptor (rrd) ring */ 6242b133ad6SJeff Kirsher struct atl1_rrd_ring { 6252b133ad6SJeff Kirsher void *desc; /* descriptor ring virtual address */ 6262b133ad6SJeff Kirsher dma_addr_t dma; /* descriptor ring physical address */ 6272b133ad6SJeff Kirsher unsigned int size; /* descriptor ring length in bytes */ 6282b133ad6SJeff Kirsher u16 count; /* number of descriptors in the ring */ 6292b133ad6SJeff Kirsher u16 next_to_use; 6302b133ad6SJeff Kirsher atomic_t next_to_clean; 6312b133ad6SJeff Kirsher }; 6322b133ad6SJeff Kirsher 6332b133ad6SJeff Kirsher /* coalescing message block (cmb) */ 6342b133ad6SJeff Kirsher struct atl1_cmb { 6352b133ad6SJeff Kirsher struct coals_msg_block *cmb; 6362b133ad6SJeff Kirsher dma_addr_t dma; 6372b133ad6SJeff Kirsher }; 6382b133ad6SJeff Kirsher 6392b133ad6SJeff Kirsher /* statistics message block (smb) */ 6402b133ad6SJeff Kirsher struct atl1_smb { 6412b133ad6SJeff Kirsher struct stats_msg_block *smb; 6422b133ad6SJeff Kirsher dma_addr_t dma; 6432b133ad6SJeff Kirsher }; 6442b133ad6SJeff Kirsher 6452b133ad6SJeff Kirsher /* Statistics counters */ 6462b133ad6SJeff Kirsher struct atl1_sft_stats { 6472b133ad6SJeff Kirsher u64 rx_packets; 6482b133ad6SJeff Kirsher u64 tx_packets; 6492b133ad6SJeff Kirsher u64 rx_bytes; 6502b133ad6SJeff Kirsher u64 tx_bytes; 6512b133ad6SJeff Kirsher u64 multicast; 6522b133ad6SJeff Kirsher u64 collisions; 6532b133ad6SJeff Kirsher u64 rx_errors; 6542b133ad6SJeff Kirsher u64 rx_length_errors; 6552b133ad6SJeff Kirsher u64 rx_crc_errors; 656e3d21ea1SSabrina Dubroca u64 rx_dropped; 6572b133ad6SJeff Kirsher u64 rx_frame_errors; 6582b133ad6SJeff Kirsher u64 rx_fifo_errors; 6592b133ad6SJeff Kirsher u64 rx_missed_errors; 6602b133ad6SJeff Kirsher u64 tx_errors; 6612b133ad6SJeff Kirsher u64 tx_fifo_errors; 6622b133ad6SJeff Kirsher u64 tx_aborted_errors; 6632b133ad6SJeff Kirsher u64 tx_window_errors; 6642b133ad6SJeff Kirsher u64 tx_carrier_errors; 6652b133ad6SJeff Kirsher u64 tx_pause; /* TX pause frames */ 6662b133ad6SJeff Kirsher u64 excecol; /* TX packets w/ excessive collisions */ 6672b133ad6SJeff Kirsher u64 deffer; /* TX packets deferred */ 6682b133ad6SJeff Kirsher u64 scc; /* packets TX after a single collision */ 6692b133ad6SJeff Kirsher u64 mcc; /* packets TX after multiple collisions */ 6702b133ad6SJeff Kirsher u64 latecol; /* TX packets w/ late collisions */ 67166c03171SColin Ian King u64 tx_underrun; /* TX packets aborted due to TX FIFO underrun 6722b133ad6SJeff Kirsher * or TRD FIFO underrun */ 6732b133ad6SJeff Kirsher u64 tx_trunc; /* TX packets truncated due to size > MTU */ 6742b133ad6SJeff Kirsher u64 rx_pause; /* num Pause packets received. */ 6752b133ad6SJeff Kirsher u64 rx_rrd_ov; 6762b133ad6SJeff Kirsher u64 rx_trunc; 6772b133ad6SJeff Kirsher }; 6782b133ad6SJeff Kirsher 6792b133ad6SJeff Kirsher /* hardware structure */ 6802b133ad6SJeff Kirsher struct atl1_hw { 6812b133ad6SJeff Kirsher u8 __iomem *hw_addr; 6822b133ad6SJeff Kirsher struct atl1_adapter *back; 6832b133ad6SJeff Kirsher enum atl1_dma_order dma_ord; 6842b133ad6SJeff Kirsher enum atl1_dma_rcb rcb_value; 6852b133ad6SJeff Kirsher enum atl1_dma_req_block dmar_block; 6862b133ad6SJeff Kirsher enum atl1_dma_req_block dmaw_block; 6872b133ad6SJeff Kirsher u8 preamble_len; 6882b133ad6SJeff Kirsher u8 max_retry; 6892b133ad6SJeff Kirsher u8 jam_ipg; /* IPG to start JAM for collision based flow 6902b133ad6SJeff Kirsher * control in half-duplex mode. In units of 6912b133ad6SJeff Kirsher * 8-bit time */ 6922b133ad6SJeff Kirsher u8 ipgt; /* Desired back to back inter-packet gap. 6932b133ad6SJeff Kirsher * The default is 96-bit time */ 6942b133ad6SJeff Kirsher u8 min_ifg; /* Minimum number of IFG to enforce in between 6952b133ad6SJeff Kirsher * receive frames. Frame gap below such IFP 6962b133ad6SJeff Kirsher * is dropped */ 6972b133ad6SJeff Kirsher u8 ipgr1; /* 64bit Carrier-Sense window */ 6982b133ad6SJeff Kirsher u8 ipgr2; /* 96-bit IPG window */ 6992b133ad6SJeff Kirsher u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned 7002b133ad6SJeff Kirsher * burst. Each TPD is 16 bytes long */ 7012b133ad6SJeff Kirsher u8 rfd_burst; /* Number of RFD to prefetch in cache-aligned 7022b133ad6SJeff Kirsher * burst. Each RFD is 12 bytes long */ 7032b133ad6SJeff Kirsher u8 rfd_fetch_gap; 7042b133ad6SJeff Kirsher u8 rrd_burst; /* Threshold number of RRDs that can be retired 7052b133ad6SJeff Kirsher * in a burst. Each RRD is 16 bytes long */ 7062b133ad6SJeff Kirsher u8 tpd_fetch_th; 7072b133ad6SJeff Kirsher u8 tpd_fetch_gap; 7082b133ad6SJeff Kirsher u16 tx_jumbo_task_th; 7092b133ad6SJeff Kirsher u16 txf_burst; /* Number of data bytes to read in a cache- 7102b133ad6SJeff Kirsher * aligned burst. Each SRAM entry is 8 bytes */ 7112b133ad6SJeff Kirsher u16 rx_jumbo_th; /* Jumbo packet size for non-VLAN packet. VLAN 7122b133ad6SJeff Kirsher * packets should add 4 bytes */ 7132b133ad6SJeff Kirsher u16 rx_jumbo_lkah; 7142b133ad6SJeff Kirsher u16 rrd_ret_timer; /* RRD retirement timer. Decrement by 1 after 7152b133ad6SJeff Kirsher * every 512ns passes. */ 7162b133ad6SJeff Kirsher u16 lcol; /* Collision Window */ 7172b133ad6SJeff Kirsher 7182b133ad6SJeff Kirsher u16 cmb_tpd; 7192b133ad6SJeff Kirsher u16 cmb_rrd; 7202b133ad6SJeff Kirsher u16 cmb_rx_timer; 7212b133ad6SJeff Kirsher u16 cmb_tx_timer; 7222b133ad6SJeff Kirsher u32 smb_timer; 7232b133ad6SJeff Kirsher u16 media_type; 7242b133ad6SJeff Kirsher u16 autoneg_advertised; 7252b133ad6SJeff Kirsher 7262b133ad6SJeff Kirsher u16 mii_autoneg_adv_reg; 7272b133ad6SJeff Kirsher u16 mii_1000t_ctrl_reg; 7282b133ad6SJeff Kirsher 7292b133ad6SJeff Kirsher u32 max_frame_size; 7302b133ad6SJeff Kirsher u32 min_frame_size; 7312b133ad6SJeff Kirsher 7322b133ad6SJeff Kirsher u16 dev_rev; 7332b133ad6SJeff Kirsher 7342b133ad6SJeff Kirsher /* spi flash */ 7352b133ad6SJeff Kirsher u8 flash_vendor; 7362b133ad6SJeff Kirsher 7372b133ad6SJeff Kirsher u8 mac_addr[ETH_ALEN]; 7382b133ad6SJeff Kirsher u8 perm_mac_addr[ETH_ALEN]; 7392b133ad6SJeff Kirsher 7402b133ad6SJeff Kirsher bool phy_configured; 7412b133ad6SJeff Kirsher }; 7422b133ad6SJeff Kirsher 7432b133ad6SJeff Kirsher struct atl1_adapter { 7442b133ad6SJeff Kirsher struct net_device *netdev; 7452b133ad6SJeff Kirsher struct pci_dev *pdev; 7462b133ad6SJeff Kirsher 7472b133ad6SJeff Kirsher struct atl1_sft_stats soft_stats; 7482b133ad6SJeff Kirsher u32 rx_buffer_len; 7492b133ad6SJeff Kirsher u32 wol; 7502b133ad6SJeff Kirsher u16 link_speed; 7512b133ad6SJeff Kirsher u16 link_duplex; 7522b133ad6SJeff Kirsher spinlock_t lock; 7536294512bSTony Zelenoff struct napi_struct napi; 75403662e41STony Zelenoff struct work_struct reset_dev_task; 7552b133ad6SJeff Kirsher struct work_struct link_chg_task; 7562b133ad6SJeff Kirsher 7572b133ad6SJeff Kirsher struct timer_list phy_config_timer; 7582b133ad6SJeff Kirsher bool phy_timer_pending; 7592b133ad6SJeff Kirsher 7602b133ad6SJeff Kirsher /* all descriptor rings' memory */ 7612b133ad6SJeff Kirsher struct atl1_ring_header ring_header; 7622b133ad6SJeff Kirsher 7632b133ad6SJeff Kirsher /* TX */ 7642b133ad6SJeff Kirsher struct atl1_tpd_ring tpd_ring; 7652b133ad6SJeff Kirsher spinlock_t mb_lock; 7662b133ad6SJeff Kirsher 7672b133ad6SJeff Kirsher /* RX */ 7682b133ad6SJeff Kirsher struct atl1_rfd_ring rfd_ring; 7692b133ad6SJeff Kirsher struct atl1_rrd_ring rrd_ring; 7702b133ad6SJeff Kirsher u64 hw_csum_err; 7712b133ad6SJeff Kirsher u64 hw_csum_good; 7722b133ad6SJeff Kirsher u32 msg_enable; 7732b133ad6SJeff Kirsher u16 imt; /* interrupt moderator timer (2us resolution) */ 7742b133ad6SJeff Kirsher u16 ict; /* interrupt clear timer (2us resolution */ 7752b133ad6SJeff Kirsher struct mii_if_info mii; /* MII interface info */ 7762b133ad6SJeff Kirsher 777aa45ba90STony Zelenoff /* 778aa45ba90STony Zelenoff * Use this value to check is napi handler allowed to 779aa45ba90STony Zelenoff * enable ints or not 780aa45ba90STony Zelenoff */ 781aa45ba90STony Zelenoff bool int_enabled; 782aa45ba90STony Zelenoff 7832b133ad6SJeff Kirsher u32 bd_number; /* board number */ 7842b133ad6SJeff Kirsher bool pci_using_64; 7852b133ad6SJeff Kirsher struct atl1_hw hw; 7862b133ad6SJeff Kirsher struct atl1_smb smb; 7872b133ad6SJeff Kirsher struct atl1_cmb cmb; 7882b133ad6SJeff Kirsher }; 7892b133ad6SJeff Kirsher 7902b133ad6SJeff Kirsher #endif /* ATL1_H */ 791