1 /*
2  * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3  * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4  * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
5  *
6  * Derived from Intel e1000 driver
7  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8  *
9  * This program is free software; you can redistribute it and/or modify it
10  * under the terms of the GNU General Public License as published by the Free
11  * Software Foundation; either version 2 of the License, or (at your option)
12  * any later version.
13  *
14  * This program is distributed in the hope that it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License along with
20  * this program; if not, write to the Free Software Foundation, Inc., 59
21  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
22  *
23  * The full GNU General Public License is included in this distribution in the
24  * file called COPYING.
25  *
26  * Contact Information:
27  * Xiong Huang <xiong.huang@atheros.com>
28  * Jie Yang <jie.yang@atheros.com>
29  * Chris Snook <csnook@redhat.com>
30  * Jay Cliburn <jcliburn@gmail.com>
31  *
32  * This version is adapted from the Attansic reference driver.
33  *
34  * TODO:
35  * Add more ethtool functions.
36  * Fix abstruse irq enable/disable condition described here:
37  *	http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
38  *
39  * NEEDS TESTING:
40  * VLAN
41  * multicast
42  * promiscuous mode
43  * interrupt coalescing
44  * SMP torture testing
45  */
46 
47 #include <linux/atomic.h>
48 #include <asm/byteorder.h>
49 
50 #include <linux/compiler.h>
51 #include <linux/crc32.h>
52 #include <linux/delay.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/etherdevice.h>
55 #include <linux/hardirq.h>
56 #include <linux/if_ether.h>
57 #include <linux/if_vlan.h>
58 #include <linux/in.h>
59 #include <linux/interrupt.h>
60 #include <linux/ip.h>
61 #include <linux/irqflags.h>
62 #include <linux/irqreturn.h>
63 #include <linux/jiffies.h>
64 #include <linux/mii.h>
65 #include <linux/module.h>
66 #include <linux/moduleparam.h>
67 #include <linux/net.h>
68 #include <linux/netdevice.h>
69 #include <linux/pci.h>
70 #include <linux/pci_ids.h>
71 #include <linux/pm.h>
72 #include <linux/skbuff.h>
73 #include <linux/slab.h>
74 #include <linux/spinlock.h>
75 #include <linux/string.h>
76 #include <linux/tcp.h>
77 #include <linux/timer.h>
78 #include <linux/types.h>
79 #include <linux/workqueue.h>
80 
81 #include <net/checksum.h>
82 
83 #include "atl1.h"
84 
85 #define ATLX_DRIVER_VERSION "2.1.3"
86 MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, "
87 	      "Chris Snook <csnook@redhat.com>, "
88 	      "Jay Cliburn <jcliburn@gmail.com>");
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(ATLX_DRIVER_VERSION);
91 
92 /* Temporary hack for merging atl1 and atl2 */
93 #include "atlx.c"
94 
95 static const struct ethtool_ops atl1_ethtool_ops;
96 
97 /*
98  * This is the only thing that needs to be changed to adjust the
99  * maximum number of ports that the driver can manage.
100  */
101 #define ATL1_MAX_NIC 4
102 
103 #define OPTION_UNSET    -1
104 #define OPTION_DISABLED 0
105 #define OPTION_ENABLED  1
106 
107 #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
108 
109 /*
110  * Interrupt Moderate Timer in units of 2 us
111  *
112  * Valid Range: 10-65535
113  *
114  * Default Value: 100 (200us)
115  */
116 static int int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
117 static unsigned int num_int_mod_timer;
118 module_param_array_named(int_mod_timer, int_mod_timer, int,
119 	&num_int_mod_timer, 0);
120 MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
121 
122 #define DEFAULT_INT_MOD_CNT	100	/* 200us */
123 #define MAX_INT_MOD_CNT		65000
124 #define MIN_INT_MOD_CNT		50
125 
126 struct atl1_option {
127 	enum { enable_option, range_option, list_option } type;
128 	char *name;
129 	char *err;
130 	int def;
131 	union {
132 		struct {	/* range_option info */
133 			int min;
134 			int max;
135 		} r;
136 		struct {	/* list_option info */
137 			int nr;
138 			struct atl1_opt_list {
139 				int i;
140 				char *str;
141 			} *p;
142 		} l;
143 	} arg;
144 };
145 
146 static int atl1_validate_option(int *value, struct atl1_option *opt,
147 				struct pci_dev *pdev)
148 {
149 	if (*value == OPTION_UNSET) {
150 		*value = opt->def;
151 		return 0;
152 	}
153 
154 	switch (opt->type) {
155 	case enable_option:
156 		switch (*value) {
157 		case OPTION_ENABLED:
158 			dev_info(&pdev->dev, "%s enabled\n", opt->name);
159 			return 0;
160 		case OPTION_DISABLED:
161 			dev_info(&pdev->dev, "%s disabled\n", opt->name);
162 			return 0;
163 		}
164 		break;
165 	case range_option:
166 		if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
167 			dev_info(&pdev->dev, "%s set to %i\n", opt->name,
168 				*value);
169 			return 0;
170 		}
171 		break;
172 	case list_option:{
173 			int i;
174 			struct atl1_opt_list *ent;
175 
176 			for (i = 0; i < opt->arg.l.nr; i++) {
177 				ent = &opt->arg.l.p[i];
178 				if (*value == ent->i) {
179 					if (ent->str[0] != '\0')
180 						dev_info(&pdev->dev, "%s\n",
181 							ent->str);
182 					return 0;
183 				}
184 			}
185 		}
186 		break;
187 
188 	default:
189 		break;
190 	}
191 
192 	dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
193 		opt->name, *value, opt->err);
194 	*value = opt->def;
195 	return -1;
196 }
197 
198 /**
199  * atl1_check_options - Range Checking for Command Line Parameters
200  * @adapter: board private structure
201  *
202  * This routine checks all command line parameters for valid user
203  * input.  If an invalid value is given, or if no user specified
204  * value exists, a default value is used.  The final value is stored
205  * in a variable in the adapter structure.
206  */
207 static void atl1_check_options(struct atl1_adapter *adapter)
208 {
209 	struct pci_dev *pdev = adapter->pdev;
210 	int bd = adapter->bd_number;
211 	if (bd >= ATL1_MAX_NIC) {
212 		dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
213 		dev_notice(&pdev->dev, "using defaults for all values\n");
214 	}
215 	{			/* Interrupt Moderate Timer */
216 		struct atl1_option opt = {
217 			.type = range_option,
218 			.name = "Interrupt Moderator Timer",
219 			.err = "using default of "
220 				__MODULE_STRING(DEFAULT_INT_MOD_CNT),
221 			.def = DEFAULT_INT_MOD_CNT,
222 			.arg = {.r = {.min = MIN_INT_MOD_CNT,
223 					.max = MAX_INT_MOD_CNT} }
224 		};
225 		int val;
226 		if (num_int_mod_timer > bd) {
227 			val = int_mod_timer[bd];
228 			atl1_validate_option(&val, &opt, pdev);
229 			adapter->imt = (u16) val;
230 		} else
231 			adapter->imt = (u16) (opt.def);
232 	}
233 }
234 
235 /*
236  * atl1_pci_tbl - PCI Device ID Table
237  */
238 static DEFINE_PCI_DEVICE_TABLE(atl1_pci_tbl) = {
239 	{PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
240 	/* required last entry */
241 	{0,}
242 };
243 MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
244 
245 static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
246 	NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
247 
248 static int debug = -1;
249 module_param(debug, int, 0);
250 MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
251 
252 /*
253  * Reset the transmit and receive units; mask and clear all interrupts.
254  * hw - Struct containing variables accessed by shared code
255  * return : 0  or  idle status (if error)
256  */
257 static s32 atl1_reset_hw(struct atl1_hw *hw)
258 {
259 	struct pci_dev *pdev = hw->back->pdev;
260 	struct atl1_adapter *adapter = hw->back;
261 	u32 icr;
262 	int i;
263 
264 	/*
265 	 * Clear Interrupt mask to stop board from generating
266 	 * interrupts & Clear any pending interrupt events
267 	 */
268 	/*
269 	 * atlx_irq_disable(adapter);
270 	 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
271 	 */
272 
273 	/*
274 	 * Issue Soft Reset to the MAC.  This will reset the chip's
275 	 * transmit, receive, DMA.  It will not effect
276 	 * the current PCI configuration.  The global reset bit is self-
277 	 * clearing, and should clear within a microsecond.
278 	 */
279 	iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
280 	ioread32(hw->hw_addr + REG_MASTER_CTRL);
281 
282 	iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
283 	ioread16(hw->hw_addr + REG_PHY_ENABLE);
284 
285 	/* delay about 1ms */
286 	msleep(1);
287 
288 	/* Wait at least 10ms for All module to be Idle */
289 	for (i = 0; i < 10; i++) {
290 		icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
291 		if (!icr)
292 			break;
293 		/* delay 1 ms */
294 		msleep(1);
295 		/* FIXME: still the right way to do this? */
296 		cpu_relax();
297 	}
298 
299 	if (icr) {
300 		if (netif_msg_hw(adapter))
301 			dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
302 		return icr;
303 	}
304 
305 	return 0;
306 }
307 
308 /* function about EEPROM
309  *
310  * check_eeprom_exist
311  * return 0 if eeprom exist
312  */
313 static int atl1_check_eeprom_exist(struct atl1_hw *hw)
314 {
315 	u32 value;
316 	value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
317 	if (value & SPI_FLASH_CTRL_EN_VPD) {
318 		value &= ~SPI_FLASH_CTRL_EN_VPD;
319 		iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
320 	}
321 
322 	value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
323 	return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
324 }
325 
326 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
327 {
328 	int i;
329 	u32 control;
330 
331 	if (offset & 3)
332 		/* address do not align */
333 		return false;
334 
335 	iowrite32(0, hw->hw_addr + REG_VPD_DATA);
336 	control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
337 	iowrite32(control, hw->hw_addr + REG_VPD_CAP);
338 	ioread32(hw->hw_addr + REG_VPD_CAP);
339 
340 	for (i = 0; i < 10; i++) {
341 		msleep(2);
342 		control = ioread32(hw->hw_addr + REG_VPD_CAP);
343 		if (control & VPD_CAP_VPD_FLAG)
344 			break;
345 	}
346 	if (control & VPD_CAP_VPD_FLAG) {
347 		*p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
348 		return true;
349 	}
350 	/* timeout */
351 	return false;
352 }
353 
354 /*
355  * Reads the value from a PHY register
356  * hw - Struct containing variables accessed by shared code
357  * reg_addr - address of the PHY register to read
358  */
359 static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
360 {
361 	u32 val;
362 	int i;
363 
364 	val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
365 		MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
366 		MDIO_CLK_SEL_SHIFT;
367 	iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
368 	ioread32(hw->hw_addr + REG_MDIO_CTRL);
369 
370 	for (i = 0; i < MDIO_WAIT_TIMES; i++) {
371 		udelay(2);
372 		val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
373 		if (!(val & (MDIO_START | MDIO_BUSY)))
374 			break;
375 	}
376 	if (!(val & (MDIO_START | MDIO_BUSY))) {
377 		*phy_data = (u16) val;
378 		return 0;
379 	}
380 	return ATLX_ERR_PHY;
381 }
382 
383 #define CUSTOM_SPI_CS_SETUP	2
384 #define CUSTOM_SPI_CLK_HI	2
385 #define CUSTOM_SPI_CLK_LO	2
386 #define CUSTOM_SPI_CS_HOLD	2
387 #define CUSTOM_SPI_CS_HI	3
388 
389 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
390 {
391 	int i;
392 	u32 value;
393 
394 	iowrite32(0, hw->hw_addr + REG_SPI_DATA);
395 	iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
396 
397 	value = SPI_FLASH_CTRL_WAIT_READY |
398 	    (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
399 	    SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
400 					     SPI_FLASH_CTRL_CLK_HI_MASK) <<
401 	    SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
402 					   SPI_FLASH_CTRL_CLK_LO_MASK) <<
403 	    SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
404 					   SPI_FLASH_CTRL_CS_HOLD_MASK) <<
405 	    SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
406 					    SPI_FLASH_CTRL_CS_HI_MASK) <<
407 	    SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
408 	    SPI_FLASH_CTRL_INS_SHIFT;
409 
410 	iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
411 
412 	value |= SPI_FLASH_CTRL_START;
413 	iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
414 	ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
415 
416 	for (i = 0; i < 10; i++) {
417 		msleep(1);
418 		value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
419 		if (!(value & SPI_FLASH_CTRL_START))
420 			break;
421 	}
422 
423 	if (value & SPI_FLASH_CTRL_START)
424 		return false;
425 
426 	*buf = ioread32(hw->hw_addr + REG_SPI_DATA);
427 
428 	return true;
429 }
430 
431 /*
432  * get_permanent_address
433  * return 0 if get valid mac address,
434  */
435 static int atl1_get_permanent_address(struct atl1_hw *hw)
436 {
437 	u32 addr[2];
438 	u32 i, control;
439 	u16 reg;
440 	u8 eth_addr[ETH_ALEN];
441 	bool key_valid;
442 
443 	if (is_valid_ether_addr(hw->perm_mac_addr))
444 		return 0;
445 
446 	/* init */
447 	addr[0] = addr[1] = 0;
448 
449 	if (!atl1_check_eeprom_exist(hw)) {
450 		reg = 0;
451 		key_valid = false;
452 		/* Read out all EEPROM content */
453 		i = 0;
454 		while (1) {
455 			if (atl1_read_eeprom(hw, i + 0x100, &control)) {
456 				if (key_valid) {
457 					if (reg == REG_MAC_STA_ADDR)
458 						addr[0] = control;
459 					else if (reg == (REG_MAC_STA_ADDR + 4))
460 						addr[1] = control;
461 					key_valid = false;
462 				} else if ((control & 0xff) == 0x5A) {
463 					key_valid = true;
464 					reg = (u16) (control >> 16);
465 				} else
466 					break;
467 			} else
468 				/* read error */
469 				break;
470 			i += 4;
471 		}
472 
473 		*(u32 *) &eth_addr[2] = swab32(addr[0]);
474 		*(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
475 		if (is_valid_ether_addr(eth_addr)) {
476 			memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
477 			return 0;
478 		}
479 	}
480 
481 	/* see if SPI FLAGS exist ? */
482 	addr[0] = addr[1] = 0;
483 	reg = 0;
484 	key_valid = false;
485 	i = 0;
486 	while (1) {
487 		if (atl1_spi_read(hw, i + 0x1f000, &control)) {
488 			if (key_valid) {
489 				if (reg == REG_MAC_STA_ADDR)
490 					addr[0] = control;
491 				else if (reg == (REG_MAC_STA_ADDR + 4))
492 					addr[1] = control;
493 				key_valid = false;
494 			} else if ((control & 0xff) == 0x5A) {
495 				key_valid = true;
496 				reg = (u16) (control >> 16);
497 			} else
498 				/* data end */
499 				break;
500 		} else
501 			/* read error */
502 			break;
503 		i += 4;
504 	}
505 
506 	*(u32 *) &eth_addr[2] = swab32(addr[0]);
507 	*(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
508 	if (is_valid_ether_addr(eth_addr)) {
509 		memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
510 		return 0;
511 	}
512 
513 	/*
514 	 * On some motherboards, the MAC address is written by the
515 	 * BIOS directly to the MAC register during POST, and is
516 	 * not stored in eeprom.  If all else thus far has failed
517 	 * to fetch the permanent MAC address, try reading it directly.
518 	 */
519 	addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
520 	addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
521 	*(u32 *) &eth_addr[2] = swab32(addr[0]);
522 	*(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
523 	if (is_valid_ether_addr(eth_addr)) {
524 		memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
525 		return 0;
526 	}
527 
528 	return 1;
529 }
530 
531 /*
532  * Reads the adapter's MAC address from the EEPROM
533  * hw - Struct containing variables accessed by shared code
534  */
535 static s32 atl1_read_mac_addr(struct atl1_hw *hw)
536 {
537 	s32 ret = 0;
538 	u16 i;
539 
540 	if (atl1_get_permanent_address(hw)) {
541 		eth_random_addr(hw->perm_mac_addr);
542 		ret = 1;
543 	}
544 
545 	for (i = 0; i < ETH_ALEN; i++)
546 		hw->mac_addr[i] = hw->perm_mac_addr[i];
547 	return ret;
548 }
549 
550 /*
551  * Hashes an address to determine its location in the multicast table
552  * hw - Struct containing variables accessed by shared code
553  * mc_addr - the multicast address to hash
554  *
555  * atl1_hash_mc_addr
556  *  purpose
557  *      set hash value for a multicast address
558  *      hash calcu processing :
559  *          1. calcu 32bit CRC for multicast address
560  *          2. reverse crc with MSB to LSB
561  */
562 static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
563 {
564 	u32 crc32, value = 0;
565 	int i;
566 
567 	crc32 = ether_crc_le(6, mc_addr);
568 	for (i = 0; i < 32; i++)
569 		value |= (((crc32 >> i) & 1) << (31 - i));
570 
571 	return value;
572 }
573 
574 /*
575  * Sets the bit in the multicast table corresponding to the hash value.
576  * hw - Struct containing variables accessed by shared code
577  * hash_value - Multicast address hash value
578  */
579 static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
580 {
581 	u32 hash_bit, hash_reg;
582 	u32 mta;
583 
584 	/*
585 	 * The HASH Table  is a register array of 2 32-bit registers.
586 	 * It is treated like an array of 64 bits.  We want to set
587 	 * bit BitArray[hash_value]. So we figure out what register
588 	 * the bit is in, read it, OR in the new bit, then write
589 	 * back the new value.  The register is determined by the
590 	 * upper 7 bits of the hash value and the bit within that
591 	 * register are determined by the lower 5 bits of the value.
592 	 */
593 	hash_reg = (hash_value >> 31) & 0x1;
594 	hash_bit = (hash_value >> 26) & 0x1F;
595 	mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
596 	mta |= (1 << hash_bit);
597 	iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
598 }
599 
600 /*
601  * Writes a value to a PHY register
602  * hw - Struct containing variables accessed by shared code
603  * reg_addr - address of the PHY register to write
604  * data - data to write to the PHY
605  */
606 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
607 {
608 	int i;
609 	u32 val;
610 
611 	val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
612 	    (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
613 	    MDIO_SUP_PREAMBLE |
614 	    MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
615 	iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
616 	ioread32(hw->hw_addr + REG_MDIO_CTRL);
617 
618 	for (i = 0; i < MDIO_WAIT_TIMES; i++) {
619 		udelay(2);
620 		val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
621 		if (!(val & (MDIO_START | MDIO_BUSY)))
622 			break;
623 	}
624 
625 	if (!(val & (MDIO_START | MDIO_BUSY)))
626 		return 0;
627 
628 	return ATLX_ERR_PHY;
629 }
630 
631 /*
632  * Make L001's PHY out of Power Saving State (bug)
633  * hw - Struct containing variables accessed by shared code
634  * when power on, L001's PHY always on Power saving State
635  * (Gigabit Link forbidden)
636  */
637 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
638 {
639 	s32 ret;
640 	ret = atl1_write_phy_reg(hw, 29, 0x0029);
641 	if (ret)
642 		return ret;
643 	return atl1_write_phy_reg(hw, 30, 0);
644 }
645 
646 /*
647  * Resets the PHY and make all config validate
648  * hw - Struct containing variables accessed by shared code
649  *
650  * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
651  */
652 static s32 atl1_phy_reset(struct atl1_hw *hw)
653 {
654 	struct pci_dev *pdev = hw->back->pdev;
655 	struct atl1_adapter *adapter = hw->back;
656 	s32 ret_val;
657 	u16 phy_data;
658 
659 	if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
660 	    hw->media_type == MEDIA_TYPE_1000M_FULL)
661 		phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
662 	else {
663 		switch (hw->media_type) {
664 		case MEDIA_TYPE_100M_FULL:
665 			phy_data =
666 			    MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
667 			    MII_CR_RESET;
668 			break;
669 		case MEDIA_TYPE_100M_HALF:
670 			phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
671 			break;
672 		case MEDIA_TYPE_10M_FULL:
673 			phy_data =
674 			    MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
675 			break;
676 		default:
677 			/* MEDIA_TYPE_10M_HALF: */
678 			phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
679 			break;
680 		}
681 	}
682 
683 	ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
684 	if (ret_val) {
685 		u32 val;
686 		int i;
687 		/* pcie serdes link may be down! */
688 		if (netif_msg_hw(adapter))
689 			dev_dbg(&pdev->dev, "pcie phy link down\n");
690 
691 		for (i = 0; i < 25; i++) {
692 			msleep(1);
693 			val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
694 			if (!(val & (MDIO_START | MDIO_BUSY)))
695 				break;
696 		}
697 
698 		if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
699 			if (netif_msg_hw(adapter))
700 				dev_warn(&pdev->dev,
701 					"pcie link down at least 25ms\n");
702 			return ret_val;
703 		}
704 	}
705 	return 0;
706 }
707 
708 /*
709  * Configures PHY autoneg and flow control advertisement settings
710  * hw - Struct containing variables accessed by shared code
711  */
712 static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
713 {
714 	s32 ret_val;
715 	s16 mii_autoneg_adv_reg;
716 	s16 mii_1000t_ctrl_reg;
717 
718 	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
719 	mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
720 
721 	/* Read the MII 1000Base-T Control Register (Address 9). */
722 	mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
723 
724 	/*
725 	 * First we clear all the 10/100 mb speed bits in the Auto-Neg
726 	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
727 	 * the  1000Base-T Control Register (Address 9).
728 	 */
729 	mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
730 	mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
731 
732 	/*
733 	 * Need to parse media_type  and set up
734 	 * the appropriate PHY registers.
735 	 */
736 	switch (hw->media_type) {
737 	case MEDIA_TYPE_AUTO_SENSOR:
738 		mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
739 					MII_AR_10T_FD_CAPS |
740 					MII_AR_100TX_HD_CAPS |
741 					MII_AR_100TX_FD_CAPS);
742 		mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
743 		break;
744 
745 	case MEDIA_TYPE_1000M_FULL:
746 		mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
747 		break;
748 
749 	case MEDIA_TYPE_100M_FULL:
750 		mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
751 		break;
752 
753 	case MEDIA_TYPE_100M_HALF:
754 		mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
755 		break;
756 
757 	case MEDIA_TYPE_10M_FULL:
758 		mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
759 		break;
760 
761 	default:
762 		mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
763 		break;
764 	}
765 
766 	/* flow control fixed to enable all */
767 	mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
768 
769 	hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
770 	hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
771 
772 	ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
773 	if (ret_val)
774 		return ret_val;
775 
776 	ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
777 	if (ret_val)
778 		return ret_val;
779 
780 	return 0;
781 }
782 
783 /*
784  * Configures link settings.
785  * hw - Struct containing variables accessed by shared code
786  * Assumes the hardware has previously been reset and the
787  * transmitter and receiver are not enabled.
788  */
789 static s32 atl1_setup_link(struct atl1_hw *hw)
790 {
791 	struct pci_dev *pdev = hw->back->pdev;
792 	struct atl1_adapter *adapter = hw->back;
793 	s32 ret_val;
794 
795 	/*
796 	 * Options:
797 	 *  PHY will advertise value(s) parsed from
798 	 *  autoneg_advertised and fc
799 	 *  no matter what autoneg is , We will not wait link result.
800 	 */
801 	ret_val = atl1_phy_setup_autoneg_adv(hw);
802 	if (ret_val) {
803 		if (netif_msg_link(adapter))
804 			dev_dbg(&pdev->dev,
805 				"error setting up autonegotiation\n");
806 		return ret_val;
807 	}
808 	/* SW.Reset , En-Auto-Neg if needed */
809 	ret_val = atl1_phy_reset(hw);
810 	if (ret_val) {
811 		if (netif_msg_link(adapter))
812 			dev_dbg(&pdev->dev, "error resetting phy\n");
813 		return ret_val;
814 	}
815 	hw->phy_configured = true;
816 	return ret_val;
817 }
818 
819 static void atl1_init_flash_opcode(struct atl1_hw *hw)
820 {
821 	if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
822 		/* Atmel */
823 		hw->flash_vendor = 0;
824 
825 	/* Init OP table */
826 	iowrite8(flash_table[hw->flash_vendor].cmd_program,
827 		hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
828 	iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
829 		hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
830 	iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
831 		hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
832 	iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
833 		hw->hw_addr + REG_SPI_FLASH_OP_RDID);
834 	iowrite8(flash_table[hw->flash_vendor].cmd_wren,
835 		hw->hw_addr + REG_SPI_FLASH_OP_WREN);
836 	iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
837 		hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
838 	iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
839 		hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
840 	iowrite8(flash_table[hw->flash_vendor].cmd_read,
841 		hw->hw_addr + REG_SPI_FLASH_OP_READ);
842 }
843 
844 /*
845  * Performs basic configuration of the adapter.
846  * hw - Struct containing variables accessed by shared code
847  * Assumes that the controller has previously been reset and is in a
848  * post-reset uninitialized state. Initializes multicast table,
849  * and  Calls routines to setup link
850  * Leaves the transmit and receive units disabled and uninitialized.
851  */
852 static s32 atl1_init_hw(struct atl1_hw *hw)
853 {
854 	u32 ret_val = 0;
855 
856 	/* Zero out the Multicast HASH table */
857 	iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
858 	/* clear the old settings from the multicast hash table */
859 	iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
860 
861 	atl1_init_flash_opcode(hw);
862 
863 	if (!hw->phy_configured) {
864 		/* enable GPHY LinkChange Interrupt */
865 		ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
866 		if (ret_val)
867 			return ret_val;
868 		/* make PHY out of power-saving state */
869 		ret_val = atl1_phy_leave_power_saving(hw);
870 		if (ret_val)
871 			return ret_val;
872 		/* Call a subroutine to configure the link */
873 		ret_val = atl1_setup_link(hw);
874 	}
875 	return ret_val;
876 }
877 
878 /*
879  * Detects the current speed and duplex settings of the hardware.
880  * hw - Struct containing variables accessed by shared code
881  * speed - Speed of the connection
882  * duplex - Duplex setting of the connection
883  */
884 static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
885 {
886 	struct pci_dev *pdev = hw->back->pdev;
887 	struct atl1_adapter *adapter = hw->back;
888 	s32 ret_val;
889 	u16 phy_data;
890 
891 	/* ; --- Read   PHY Specific Status Register (17) */
892 	ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
893 	if (ret_val)
894 		return ret_val;
895 
896 	if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
897 		return ATLX_ERR_PHY_RES;
898 
899 	switch (phy_data & MII_ATLX_PSSR_SPEED) {
900 	case MII_ATLX_PSSR_1000MBS:
901 		*speed = SPEED_1000;
902 		break;
903 	case MII_ATLX_PSSR_100MBS:
904 		*speed = SPEED_100;
905 		break;
906 	case MII_ATLX_PSSR_10MBS:
907 		*speed = SPEED_10;
908 		break;
909 	default:
910 		if (netif_msg_hw(adapter))
911 			dev_dbg(&pdev->dev, "error getting speed\n");
912 		return ATLX_ERR_PHY_SPEED;
913 		break;
914 	}
915 	if (phy_data & MII_ATLX_PSSR_DPLX)
916 		*duplex = FULL_DUPLEX;
917 	else
918 		*duplex = HALF_DUPLEX;
919 
920 	return 0;
921 }
922 
923 static void atl1_set_mac_addr(struct atl1_hw *hw)
924 {
925 	u32 value;
926 	/*
927 	 * 00-0B-6A-F6-00-DC
928 	 * 0:  6AF600DC   1: 000B
929 	 * low dword
930 	 */
931 	value = (((u32) hw->mac_addr[2]) << 24) |
932 	    (((u32) hw->mac_addr[3]) << 16) |
933 	    (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
934 	iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
935 	/* high dword */
936 	value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
937 	iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
938 }
939 
940 /**
941  * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
942  * @adapter: board private structure to initialize
943  *
944  * atl1_sw_init initializes the Adapter private data structure.
945  * Fields are initialized based on PCI device information and
946  * OS network device settings (MTU size).
947  */
948 static int atl1_sw_init(struct atl1_adapter *adapter)
949 {
950 	struct atl1_hw *hw = &adapter->hw;
951 	struct net_device *netdev = adapter->netdev;
952 
953 	hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
954 	hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
955 
956 	adapter->wol = 0;
957 	device_set_wakeup_enable(&adapter->pdev->dev, false);
958 	adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
959 	adapter->ict = 50000;		/* 100ms */
960 	adapter->link_speed = SPEED_0;	/* hardware init */
961 	adapter->link_duplex = FULL_DUPLEX;
962 
963 	hw->phy_configured = false;
964 	hw->preamble_len = 7;
965 	hw->ipgt = 0x60;
966 	hw->min_ifg = 0x50;
967 	hw->ipgr1 = 0x40;
968 	hw->ipgr2 = 0x60;
969 	hw->max_retry = 0xf;
970 	hw->lcol = 0x37;
971 	hw->jam_ipg = 7;
972 	hw->rfd_burst = 8;
973 	hw->rrd_burst = 8;
974 	hw->rfd_fetch_gap = 1;
975 	hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
976 	hw->rx_jumbo_lkah = 1;
977 	hw->rrd_ret_timer = 16;
978 	hw->tpd_burst = 4;
979 	hw->tpd_fetch_th = 16;
980 	hw->txf_burst = 0x100;
981 	hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
982 	hw->tpd_fetch_gap = 1;
983 	hw->rcb_value = atl1_rcb_64;
984 	hw->dma_ord = atl1_dma_ord_enh;
985 	hw->dmar_block = atl1_dma_req_256;
986 	hw->dmaw_block = atl1_dma_req_256;
987 	hw->cmb_rrd = 4;
988 	hw->cmb_tpd = 4;
989 	hw->cmb_rx_timer = 1;	/* about 2us */
990 	hw->cmb_tx_timer = 1;	/* about 2us */
991 	hw->smb_timer = 100000;	/* about 200ms */
992 
993 	spin_lock_init(&adapter->lock);
994 	spin_lock_init(&adapter->mb_lock);
995 
996 	return 0;
997 }
998 
999 static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
1000 {
1001 	struct atl1_adapter *adapter = netdev_priv(netdev);
1002 	u16 result;
1003 
1004 	atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
1005 
1006 	return result;
1007 }
1008 
1009 static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
1010 	int val)
1011 {
1012 	struct atl1_adapter *adapter = netdev_priv(netdev);
1013 
1014 	atl1_write_phy_reg(&adapter->hw, reg_num, val);
1015 }
1016 
1017 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1018 {
1019 	struct atl1_adapter *adapter = netdev_priv(netdev);
1020 	unsigned long flags;
1021 	int retval;
1022 
1023 	if (!netif_running(netdev))
1024 		return -EINVAL;
1025 
1026 	spin_lock_irqsave(&adapter->lock, flags);
1027 	retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1028 	spin_unlock_irqrestore(&adapter->lock, flags);
1029 
1030 	return retval;
1031 }
1032 
1033 /**
1034  * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1035  * @adapter: board private structure
1036  *
1037  * Return 0 on success, negative on failure
1038  */
1039 static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
1040 {
1041 	struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1042 	struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1043 	struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1044 	struct atl1_ring_header *ring_header = &adapter->ring_header;
1045 	struct pci_dev *pdev = adapter->pdev;
1046 	int size;
1047 	u8 offset = 0;
1048 
1049 	size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
1050 	tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
1051 	if (unlikely(!tpd_ring->buffer_info)) {
1052 		if (netif_msg_drv(adapter))
1053 			dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
1054 				size);
1055 		goto err_nomem;
1056 	}
1057 	rfd_ring->buffer_info =
1058 		(tpd_ring->buffer_info + tpd_ring->count);
1059 
1060 	/*
1061 	 * real ring DMA buffer
1062 	 * each ring/block may need up to 8 bytes for alignment, hence the
1063 	 * additional 40 bytes tacked onto the end.
1064 	 */
1065 	ring_header->size = size =
1066 		sizeof(struct tx_packet_desc) * tpd_ring->count
1067 		+ sizeof(struct rx_free_desc) * rfd_ring->count
1068 		+ sizeof(struct rx_return_desc) * rrd_ring->count
1069 		+ sizeof(struct coals_msg_block)
1070 		+ sizeof(struct stats_msg_block)
1071 		+ 40;
1072 
1073 	ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
1074 		&ring_header->dma);
1075 	if (unlikely(!ring_header->desc)) {
1076 		if (netif_msg_drv(adapter))
1077 			dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
1078 		goto err_nomem;
1079 	}
1080 
1081 	memset(ring_header->desc, 0, ring_header->size);
1082 
1083 	/* init TPD ring */
1084 	tpd_ring->dma = ring_header->dma;
1085 	offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
1086 	tpd_ring->dma += offset;
1087 	tpd_ring->desc = (u8 *) ring_header->desc + offset;
1088 	tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
1089 
1090 	/* init RFD ring */
1091 	rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
1092 	offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
1093 	rfd_ring->dma += offset;
1094 	rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
1095 	rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
1096 
1097 
1098 	/* init RRD ring */
1099 	rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
1100 	offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
1101 	rrd_ring->dma += offset;
1102 	rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
1103 	rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
1104 
1105 
1106 	/* init CMB */
1107 	adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
1108 	offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
1109 	adapter->cmb.dma += offset;
1110 	adapter->cmb.cmb = (struct coals_msg_block *)
1111 		((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
1112 
1113 	/* init SMB */
1114 	adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
1115 	offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
1116 	adapter->smb.dma += offset;
1117 	adapter->smb.smb = (struct stats_msg_block *)
1118 		((u8 *) adapter->cmb.cmb +
1119 		(sizeof(struct coals_msg_block) + offset));
1120 
1121 	return 0;
1122 
1123 err_nomem:
1124 	kfree(tpd_ring->buffer_info);
1125 	return -ENOMEM;
1126 }
1127 
1128 static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
1129 {
1130 	struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1131 	struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1132 	struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1133 
1134 	atomic_set(&tpd_ring->next_to_use, 0);
1135 	atomic_set(&tpd_ring->next_to_clean, 0);
1136 
1137 	rfd_ring->next_to_clean = 0;
1138 	atomic_set(&rfd_ring->next_to_use, 0);
1139 
1140 	rrd_ring->next_to_use = 0;
1141 	atomic_set(&rrd_ring->next_to_clean, 0);
1142 }
1143 
1144 /**
1145  * atl1_clean_rx_ring - Free RFD Buffers
1146  * @adapter: board private structure
1147  */
1148 static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
1149 {
1150 	struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1151 	struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1152 	struct atl1_buffer *buffer_info;
1153 	struct pci_dev *pdev = adapter->pdev;
1154 	unsigned long size;
1155 	unsigned int i;
1156 
1157 	/* Free all the Rx ring sk_buffs */
1158 	for (i = 0; i < rfd_ring->count; i++) {
1159 		buffer_info = &rfd_ring->buffer_info[i];
1160 		if (buffer_info->dma) {
1161 			pci_unmap_page(pdev, buffer_info->dma,
1162 				buffer_info->length, PCI_DMA_FROMDEVICE);
1163 			buffer_info->dma = 0;
1164 		}
1165 		if (buffer_info->skb) {
1166 			dev_kfree_skb(buffer_info->skb);
1167 			buffer_info->skb = NULL;
1168 		}
1169 	}
1170 
1171 	size = sizeof(struct atl1_buffer) * rfd_ring->count;
1172 	memset(rfd_ring->buffer_info, 0, size);
1173 
1174 	/* Zero out the descriptor ring */
1175 	memset(rfd_ring->desc, 0, rfd_ring->size);
1176 
1177 	rfd_ring->next_to_clean = 0;
1178 	atomic_set(&rfd_ring->next_to_use, 0);
1179 
1180 	rrd_ring->next_to_use = 0;
1181 	atomic_set(&rrd_ring->next_to_clean, 0);
1182 }
1183 
1184 /**
1185  * atl1_clean_tx_ring - Free Tx Buffers
1186  * @adapter: board private structure
1187  */
1188 static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
1189 {
1190 	struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1191 	struct atl1_buffer *buffer_info;
1192 	struct pci_dev *pdev = adapter->pdev;
1193 	unsigned long size;
1194 	unsigned int i;
1195 
1196 	/* Free all the Tx ring sk_buffs */
1197 	for (i = 0; i < tpd_ring->count; i++) {
1198 		buffer_info = &tpd_ring->buffer_info[i];
1199 		if (buffer_info->dma) {
1200 			pci_unmap_page(pdev, buffer_info->dma,
1201 				buffer_info->length, PCI_DMA_TODEVICE);
1202 			buffer_info->dma = 0;
1203 		}
1204 	}
1205 
1206 	for (i = 0; i < tpd_ring->count; i++) {
1207 		buffer_info = &tpd_ring->buffer_info[i];
1208 		if (buffer_info->skb) {
1209 			dev_kfree_skb_any(buffer_info->skb);
1210 			buffer_info->skb = NULL;
1211 		}
1212 	}
1213 
1214 	size = sizeof(struct atl1_buffer) * tpd_ring->count;
1215 	memset(tpd_ring->buffer_info, 0, size);
1216 
1217 	/* Zero out the descriptor ring */
1218 	memset(tpd_ring->desc, 0, tpd_ring->size);
1219 
1220 	atomic_set(&tpd_ring->next_to_use, 0);
1221 	atomic_set(&tpd_ring->next_to_clean, 0);
1222 }
1223 
1224 /**
1225  * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1226  * @adapter: board private structure
1227  *
1228  * Free all transmit software resources
1229  */
1230 static void atl1_free_ring_resources(struct atl1_adapter *adapter)
1231 {
1232 	struct pci_dev *pdev = adapter->pdev;
1233 	struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1234 	struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1235 	struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1236 	struct atl1_ring_header *ring_header = &adapter->ring_header;
1237 
1238 	atl1_clean_tx_ring(adapter);
1239 	atl1_clean_rx_ring(adapter);
1240 
1241 	kfree(tpd_ring->buffer_info);
1242 	pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1243 		ring_header->dma);
1244 
1245 	tpd_ring->buffer_info = NULL;
1246 	tpd_ring->desc = NULL;
1247 	tpd_ring->dma = 0;
1248 
1249 	rfd_ring->buffer_info = NULL;
1250 	rfd_ring->desc = NULL;
1251 	rfd_ring->dma = 0;
1252 
1253 	rrd_ring->desc = NULL;
1254 	rrd_ring->dma = 0;
1255 
1256 	adapter->cmb.dma = 0;
1257 	adapter->cmb.cmb = NULL;
1258 
1259 	adapter->smb.dma = 0;
1260 	adapter->smb.smb = NULL;
1261 }
1262 
1263 static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
1264 {
1265 	u32 value;
1266 	struct atl1_hw *hw = &adapter->hw;
1267 	struct net_device *netdev = adapter->netdev;
1268 	/* Config MAC CTRL Register */
1269 	value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1270 	/* duplex */
1271 	if (FULL_DUPLEX == adapter->link_duplex)
1272 		value |= MAC_CTRL_DUPLX;
1273 	/* speed */
1274 	value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1275 			 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1276 		  MAC_CTRL_SPEED_SHIFT);
1277 	/* flow control */
1278 	value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1279 	/* PAD & CRC */
1280 	value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1281 	/* preamble length */
1282 	value |= (((u32) adapter->hw.preamble_len
1283 		   & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1284 	/* vlan */
1285 	__atlx_vlan_mode(netdev->features, &value);
1286 	/* rx checksum
1287 	   if (adapter->rx_csum)
1288 	   value |= MAC_CTRL_RX_CHKSUM_EN;
1289 	 */
1290 	/* filter mode */
1291 	value |= MAC_CTRL_BC_EN;
1292 	if (netdev->flags & IFF_PROMISC)
1293 		value |= MAC_CTRL_PROMIS_EN;
1294 	else if (netdev->flags & IFF_ALLMULTI)
1295 		value |= MAC_CTRL_MC_ALL_EN;
1296 	/* value |= MAC_CTRL_LOOPBACK; */
1297 	iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1298 }
1299 
1300 static u32 atl1_check_link(struct atl1_adapter *adapter)
1301 {
1302 	struct atl1_hw *hw = &adapter->hw;
1303 	struct net_device *netdev = adapter->netdev;
1304 	u32 ret_val;
1305 	u16 speed, duplex, phy_data;
1306 	int reconfig = 0;
1307 
1308 	/* MII_BMSR must read twice */
1309 	atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1310 	atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1311 	if (!(phy_data & BMSR_LSTATUS)) {
1312 		/* link down */
1313 		if (netif_carrier_ok(netdev)) {
1314 			/* old link state: Up */
1315 			if (netif_msg_link(adapter))
1316 				dev_info(&adapter->pdev->dev, "link is down\n");
1317 			adapter->link_speed = SPEED_0;
1318 			netif_carrier_off(netdev);
1319 		}
1320 		return 0;
1321 	}
1322 
1323 	/* Link Up */
1324 	ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1325 	if (ret_val)
1326 		return ret_val;
1327 
1328 	switch (hw->media_type) {
1329 	case MEDIA_TYPE_1000M_FULL:
1330 		if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
1331 			reconfig = 1;
1332 		break;
1333 	case MEDIA_TYPE_100M_FULL:
1334 		if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1335 			reconfig = 1;
1336 		break;
1337 	case MEDIA_TYPE_100M_HALF:
1338 		if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1339 			reconfig = 1;
1340 		break;
1341 	case MEDIA_TYPE_10M_FULL:
1342 		if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1343 			reconfig = 1;
1344 		break;
1345 	case MEDIA_TYPE_10M_HALF:
1346 		if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1347 			reconfig = 1;
1348 		break;
1349 	}
1350 
1351 	/* link result is our setting */
1352 	if (!reconfig) {
1353 		if (adapter->link_speed != speed ||
1354 		    adapter->link_duplex != duplex) {
1355 			adapter->link_speed = speed;
1356 			adapter->link_duplex = duplex;
1357 			atl1_setup_mac_ctrl(adapter);
1358 			if (netif_msg_link(adapter))
1359 				dev_info(&adapter->pdev->dev,
1360 					"%s link is up %d Mbps %s\n",
1361 					netdev->name, adapter->link_speed,
1362 					adapter->link_duplex == FULL_DUPLEX ?
1363 					"full duplex" : "half duplex");
1364 		}
1365 		if (!netif_carrier_ok(netdev)) {
1366 			/* Link down -> Up */
1367 			netif_carrier_on(netdev);
1368 		}
1369 		return 0;
1370 	}
1371 
1372 	/* change original link status */
1373 	if (netif_carrier_ok(netdev)) {
1374 		adapter->link_speed = SPEED_0;
1375 		netif_carrier_off(netdev);
1376 		netif_stop_queue(netdev);
1377 	}
1378 
1379 	if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1380 	    hw->media_type != MEDIA_TYPE_1000M_FULL) {
1381 		switch (hw->media_type) {
1382 		case MEDIA_TYPE_100M_FULL:
1383 			phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1384 			           MII_CR_RESET;
1385 			break;
1386 		case MEDIA_TYPE_100M_HALF:
1387 			phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1388 			break;
1389 		case MEDIA_TYPE_10M_FULL:
1390 			phy_data =
1391 			    MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
1392 			break;
1393 		default:
1394 			/* MEDIA_TYPE_10M_HALF: */
1395 			phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1396 			break;
1397 		}
1398 		atl1_write_phy_reg(hw, MII_BMCR, phy_data);
1399 		return 0;
1400 	}
1401 
1402 	/* auto-neg, insert timer to re-config phy */
1403 	if (!adapter->phy_timer_pending) {
1404 		adapter->phy_timer_pending = true;
1405 		mod_timer(&adapter->phy_config_timer,
1406 			  round_jiffies(jiffies + 3 * HZ));
1407 	}
1408 
1409 	return 0;
1410 }
1411 
1412 static void set_flow_ctrl_old(struct atl1_adapter *adapter)
1413 {
1414 	u32 hi, lo, value;
1415 
1416 	/* RFD Flow Control */
1417 	value = adapter->rfd_ring.count;
1418 	hi = value / 16;
1419 	if (hi < 2)
1420 		hi = 2;
1421 	lo = value * 7 / 8;
1422 
1423 	value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1424 		((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1425 	iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1426 
1427 	/* RRD Flow Control */
1428 	value = adapter->rrd_ring.count;
1429 	lo = value / 16;
1430 	hi = value * 7 / 8;
1431 	if (lo < 2)
1432 		lo = 2;
1433 	value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1434 		((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1435 	iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1436 }
1437 
1438 static void set_flow_ctrl_new(struct atl1_hw *hw)
1439 {
1440 	u32 hi, lo, value;
1441 
1442 	/* RXF Flow Control */
1443 	value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1444 	lo = value / 16;
1445 	if (lo < 192)
1446 		lo = 192;
1447 	hi = value * 7 / 8;
1448 	if (hi < lo)
1449 		hi = lo + 16;
1450 	value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1451 		((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1452 	iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1453 
1454 	/* RRD Flow Control */
1455 	value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1456 	lo = value / 8;
1457 	hi = value * 7 / 8;
1458 	if (lo < 2)
1459 		lo = 2;
1460 	if (hi < lo)
1461 		hi = lo + 3;
1462 	value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1463 		((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1464 	iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1465 }
1466 
1467 /**
1468  * atl1_configure - Configure Transmit&Receive Unit after Reset
1469  * @adapter: board private structure
1470  *
1471  * Configure the Tx /Rx unit of the MAC after a reset.
1472  */
1473 static u32 atl1_configure(struct atl1_adapter *adapter)
1474 {
1475 	struct atl1_hw *hw = &adapter->hw;
1476 	u32 value;
1477 
1478 	/* clear interrupt status */
1479 	iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1480 
1481 	/* set MAC Address */
1482 	value = (((u32) hw->mac_addr[2]) << 24) |
1483 		(((u32) hw->mac_addr[3]) << 16) |
1484 		(((u32) hw->mac_addr[4]) << 8) |
1485 		(((u32) hw->mac_addr[5]));
1486 	iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1487 	value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1488 	iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1489 
1490 	/* tx / rx ring */
1491 
1492 	/* HI base address */
1493 	iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1494 		hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1495 	/* LO base address */
1496 	iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1497 		hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1498 	iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1499 		hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1500 	iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1501 		hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1502 	iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1503 		hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1504 	iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1505 		hw->hw_addr + REG_DESC_SMB_ADDR_LO);
1506 
1507 	/* element count */
1508 	value = adapter->rrd_ring.count;
1509 	value <<= 16;
1510 	value += adapter->rfd_ring.count;
1511 	iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1512 	iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1513 		REG_DESC_TPD_RING_SIZE);
1514 
1515 	/* Load Ptr */
1516 	iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
1517 
1518 	/* config Mailbox */
1519 	value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1520 		  & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1521 		((atomic_read(&adapter->rrd_ring.next_to_clean)
1522 		& MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1523 		((atomic_read(&adapter->rfd_ring.next_to_use)
1524 		& MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1525 	iowrite32(value, hw->hw_addr + REG_MAILBOX);
1526 
1527 	/* config IPG/IFG */
1528 	value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1529 		 << MAC_IPG_IFG_IPGT_SHIFT) |
1530 		(((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1531 		<< MAC_IPG_IFG_MIFG_SHIFT) |
1532 		(((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1533 		<< MAC_IPG_IFG_IPGR1_SHIFT) |
1534 		(((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1535 		<< MAC_IPG_IFG_IPGR2_SHIFT);
1536 	iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1537 
1538 	/* config  Half-Duplex Control */
1539 	value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1540 		(((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1541 		<< MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1542 		MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1543 		(0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1544 		(((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1545 		<< MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1546 	iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1547 
1548 	/* set Interrupt Moderator Timer */
1549 	iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1550 	iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
1551 
1552 	/* set Interrupt Clear Timer */
1553 	iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
1554 
1555 	/* set max frame size hw will accept */
1556 	iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
1557 
1558 	/* jumbo size & rrd retirement timer */
1559 	value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1560 		 << RXQ_JMBOSZ_TH_SHIFT) |
1561 		(((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1562 		<< RXQ_JMBO_LKAH_SHIFT) |
1563 		(((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1564 		<< RXQ_RRD_TIMER_SHIFT);
1565 	iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1566 
1567 	/* Flow Control */
1568 	switch (hw->dev_rev) {
1569 	case 0x8001:
1570 	case 0x9001:
1571 	case 0x9002:
1572 	case 0x9003:
1573 		set_flow_ctrl_old(adapter);
1574 		break;
1575 	default:
1576 		set_flow_ctrl_new(hw);
1577 		break;
1578 	}
1579 
1580 	/* config TXQ */
1581 	value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1582 		 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1583 		(((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1584 		<< TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1585 		(((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1586 		<< TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
1587 		TXQ_CTRL_EN;
1588 	iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1589 
1590 	/* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1591 	value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1592 		<< TX_JUMBO_TASK_TH_SHIFT) |
1593 		(((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1594 		<< TX_TPD_MIN_IPG_SHIFT);
1595 	iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1596 
1597 	/* config RXQ */
1598 	value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1599 		<< RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1600 		(((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1601 		<< RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1602 		(((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1603 		<< RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
1604 		RXQ_CTRL_EN;
1605 	iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1606 
1607 	/* config DMA Engine */
1608 	value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1609 		<< DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
1610 		((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1611 		<< DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
1612 		DMA_CTRL_DMAW_EN;
1613 	value |= (u32) hw->dma_ord;
1614 	if (atl1_rcb_128 == hw->rcb_value)
1615 		value |= DMA_CTRL_RCB_VALUE;
1616 	iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1617 
1618 	/* config CMB / SMB */
1619 	value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1620 		hw->cmb_tpd : adapter->tpd_ring.count;
1621 	value <<= 16;
1622 	value |= hw->cmb_rrd;
1623 	iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1624 	value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1625 	iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1626 	iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
1627 
1628 	/* --- enable CMB / SMB */
1629 	value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1630 	iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1631 
1632 	value = ioread32(adapter->hw.hw_addr + REG_ISR);
1633 	if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1634 		value = 1;	/* config failed */
1635 	else
1636 		value = 0;
1637 
1638 	/* clear all interrupt status */
1639 	iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1640 	iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1641 	return value;
1642 }
1643 
1644 /*
1645  * atl1_pcie_patch - Patch for PCIE module
1646  */
1647 static void atl1_pcie_patch(struct atl1_adapter *adapter)
1648 {
1649 	u32 value;
1650 
1651 	/* much vendor magic here */
1652 	value = 0x6500;
1653 	iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1654 	/* pcie flow control mode change */
1655 	value = ioread32(adapter->hw.hw_addr + 0x1008);
1656 	value |= 0x8000;
1657 	iowrite32(value, adapter->hw.hw_addr + 0x1008);
1658 }
1659 
1660 /*
1661  * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1662  * on PCI Command register is disable.
1663  * The function enable this bit.
1664  * Brackett, 2006/03/15
1665  */
1666 static void atl1_via_workaround(struct atl1_adapter *adapter)
1667 {
1668 	unsigned long value;
1669 
1670 	value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1671 	if (value & PCI_COMMAND_INTX_DISABLE)
1672 		value &= ~PCI_COMMAND_INTX_DISABLE;
1673 	iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
1674 }
1675 
1676 static void atl1_inc_smb(struct atl1_adapter *adapter)
1677 {
1678 	struct net_device *netdev = adapter->netdev;
1679 	struct stats_msg_block *smb = adapter->smb.smb;
1680 
1681 	u64 new_rx_errors = smb->rx_frag +
1682 			    smb->rx_fcs_err +
1683 			    smb->rx_len_err +
1684 			    smb->rx_sz_ov +
1685 			    smb->rx_rxf_ov +
1686 			    smb->rx_rrd_ov +
1687 			    smb->rx_align_err;
1688 	u64 new_tx_errors = smb->tx_late_col +
1689 			    smb->tx_abort_col +
1690 			    smb->tx_underrun +
1691 			    smb->tx_trunc;
1692 
1693 	/* Fill out the OS statistics structure */
1694 	adapter->soft_stats.rx_packets += smb->rx_ok + new_rx_errors;
1695 	adapter->soft_stats.tx_packets += smb->tx_ok + new_tx_errors;
1696 	adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1697 	adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1698 	adapter->soft_stats.multicast += smb->rx_mcast;
1699 	adapter->soft_stats.collisions += smb->tx_1_col +
1700 					  smb->tx_2_col +
1701 					  smb->tx_late_col +
1702 					  smb->tx_abort_col;
1703 
1704 	/* Rx Errors */
1705 	adapter->soft_stats.rx_errors += new_rx_errors;
1706 	adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1707 	adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1708 	adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1709 	adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1710 
1711 	adapter->soft_stats.rx_pause += smb->rx_pause;
1712 	adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1713 	adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
1714 
1715 	/* Tx Errors */
1716 	adapter->soft_stats.tx_errors += new_tx_errors;
1717 	adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1718 	adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1719 	adapter->soft_stats.tx_window_errors += smb->tx_late_col;
1720 
1721 	adapter->soft_stats.excecol += smb->tx_abort_col;
1722 	adapter->soft_stats.deffer += smb->tx_defer;
1723 	adapter->soft_stats.scc += smb->tx_1_col;
1724 	adapter->soft_stats.mcc += smb->tx_2_col;
1725 	adapter->soft_stats.latecol += smb->tx_late_col;
1726 	adapter->soft_stats.tx_underun += smb->tx_underrun;
1727 	adapter->soft_stats.tx_trunc += smb->tx_trunc;
1728 	adapter->soft_stats.tx_pause += smb->tx_pause;
1729 
1730 	netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes;
1731 	netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes;
1732 	netdev->stats.multicast = adapter->soft_stats.multicast;
1733 	netdev->stats.collisions = adapter->soft_stats.collisions;
1734 	netdev->stats.rx_errors = adapter->soft_stats.rx_errors;
1735 	netdev->stats.rx_length_errors =
1736 		adapter->soft_stats.rx_length_errors;
1737 	netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1738 	netdev->stats.rx_frame_errors =
1739 		adapter->soft_stats.rx_frame_errors;
1740 	netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1741 	netdev->stats.rx_dropped = adapter->soft_stats.rx_rrd_ov;
1742 	netdev->stats.tx_errors = adapter->soft_stats.tx_errors;
1743 	netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1744 	netdev->stats.tx_aborted_errors =
1745 		adapter->soft_stats.tx_aborted_errors;
1746 	netdev->stats.tx_window_errors =
1747 		adapter->soft_stats.tx_window_errors;
1748 	netdev->stats.tx_carrier_errors =
1749 		adapter->soft_stats.tx_carrier_errors;
1750 
1751 	netdev->stats.rx_packets = adapter->soft_stats.rx_packets;
1752 	netdev->stats.tx_packets = adapter->soft_stats.tx_packets;
1753 }
1754 
1755 static void atl1_update_mailbox(struct atl1_adapter *adapter)
1756 {
1757 	unsigned long flags;
1758 	u32 tpd_next_to_use;
1759 	u32 rfd_next_to_use;
1760 	u32 rrd_next_to_clean;
1761 	u32 value;
1762 
1763 	spin_lock_irqsave(&adapter->mb_lock, flags);
1764 
1765 	tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1766 	rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1767 	rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
1768 
1769 	value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1770 		MB_RFD_PROD_INDX_SHIFT) |
1771 		((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1772 		MB_RRD_CONS_INDX_SHIFT) |
1773 		((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1774 		MB_TPD_PROD_INDX_SHIFT);
1775 	iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1776 
1777 	spin_unlock_irqrestore(&adapter->mb_lock, flags);
1778 }
1779 
1780 static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
1781 	struct rx_return_desc *rrd, u16 offset)
1782 {
1783 	struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1784 
1785 	while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
1786 		rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
1787 		if (++rfd_ring->next_to_clean == rfd_ring->count) {
1788 			rfd_ring->next_to_clean = 0;
1789 		}
1790 	}
1791 }
1792 
1793 static void atl1_update_rfd_index(struct atl1_adapter *adapter,
1794 	struct rx_return_desc *rrd)
1795 {
1796 	u16 num_buf;
1797 
1798 	num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
1799 		adapter->rx_buffer_len;
1800 	if (rrd->num_buf == num_buf)
1801 		/* clean alloc flag for bad rrd */
1802 		atl1_clean_alloc_flag(adapter, rrd, num_buf);
1803 }
1804 
1805 static void atl1_rx_checksum(struct atl1_adapter *adapter,
1806 	struct rx_return_desc *rrd, struct sk_buff *skb)
1807 {
1808 	struct pci_dev *pdev = adapter->pdev;
1809 
1810 	/*
1811 	 * The L1 hardware contains a bug that erroneously sets the
1812 	 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a
1813 	 * fragmented IP packet is received, even though the packet
1814 	 * is perfectly valid and its checksum is correct. There's
1815 	 * no way to distinguish between one of these good packets
1816 	 * and a packet that actually contains a TCP/UDP checksum
1817 	 * error, so all we can do is allow it to be handed up to
1818 	 * the higher layers and let it be sorted out there.
1819 	 */
1820 
1821 	skb_checksum_none_assert(skb);
1822 
1823 	if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1824 		if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
1825 					ERR_FLAG_CODE | ERR_FLAG_OV)) {
1826 			adapter->hw_csum_err++;
1827 			if (netif_msg_rx_err(adapter))
1828 				dev_printk(KERN_DEBUG, &pdev->dev,
1829 					"rx checksum error\n");
1830 			return;
1831 		}
1832 	}
1833 
1834 	/* not IPv4 */
1835 	if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
1836 		/* checksum is invalid, but it's not an IPv4 pkt, so ok */
1837 		return;
1838 
1839 	/* IPv4 packet */
1840 	if (likely(!(rrd->err_flg &
1841 		(ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
1842 		skb->ip_summed = CHECKSUM_UNNECESSARY;
1843 		adapter->hw_csum_good++;
1844 		return;
1845 	}
1846 }
1847 
1848 /**
1849  * atl1_alloc_rx_buffers - Replace used receive buffers
1850  * @adapter: address of board private structure
1851  */
1852 static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
1853 {
1854 	struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1855 	struct pci_dev *pdev = adapter->pdev;
1856 	struct page *page;
1857 	unsigned long offset;
1858 	struct atl1_buffer *buffer_info, *next_info;
1859 	struct sk_buff *skb;
1860 	u16 num_alloc = 0;
1861 	u16 rfd_next_to_use, next_next;
1862 	struct rx_free_desc *rfd_desc;
1863 
1864 	next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
1865 	if (++next_next == rfd_ring->count)
1866 		next_next = 0;
1867 	buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1868 	next_info = &rfd_ring->buffer_info[next_next];
1869 
1870 	while (!buffer_info->alloced && !next_info->alloced) {
1871 		if (buffer_info->skb) {
1872 			buffer_info->alloced = 1;
1873 			goto next;
1874 		}
1875 
1876 		rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
1877 
1878 		skb = netdev_alloc_skb_ip_align(adapter->netdev,
1879 						adapter->rx_buffer_len);
1880 		if (unlikely(!skb)) {
1881 			/* Better luck next round */
1882 			adapter->soft_stats.rx_dropped++;
1883 			break;
1884 		}
1885 
1886 		buffer_info->alloced = 1;
1887 		buffer_info->skb = skb;
1888 		buffer_info->length = (u16) adapter->rx_buffer_len;
1889 		page = virt_to_page(skb->data);
1890 		offset = (unsigned long)skb->data & ~PAGE_MASK;
1891 		buffer_info->dma = pci_map_page(pdev, page, offset,
1892 						adapter->rx_buffer_len,
1893 						PCI_DMA_FROMDEVICE);
1894 		rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1895 		rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
1896 		rfd_desc->coalese = 0;
1897 
1898 next:
1899 		rfd_next_to_use = next_next;
1900 		if (unlikely(++next_next == rfd_ring->count))
1901 			next_next = 0;
1902 
1903 		buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1904 		next_info = &rfd_ring->buffer_info[next_next];
1905 		num_alloc++;
1906 	}
1907 
1908 	if (num_alloc) {
1909 		/*
1910 		 * Force memory writes to complete before letting h/w
1911 		 * know there are new descriptors to fetch.  (Only
1912 		 * applicable for weak-ordered memory model archs,
1913 		 * such as IA-64).
1914 		 */
1915 		wmb();
1916 		atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
1917 	}
1918 	return num_alloc;
1919 }
1920 
1921 static int atl1_intr_rx(struct atl1_adapter *adapter, int budget)
1922 {
1923 	int i, count;
1924 	u16 length;
1925 	u16 rrd_next_to_clean;
1926 	u32 value;
1927 	struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1928 	struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1929 	struct atl1_buffer *buffer_info;
1930 	struct rx_return_desc *rrd;
1931 	struct sk_buff *skb;
1932 
1933 	count = 0;
1934 
1935 	rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
1936 
1937 	while (count < budget) {
1938 		rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
1939 		i = 1;
1940 		if (likely(rrd->xsz.valid)) {	/* packet valid */
1941 chk_rrd:
1942 			/* check rrd status */
1943 			if (likely(rrd->num_buf == 1))
1944 				goto rrd_ok;
1945 			else if (netif_msg_rx_err(adapter)) {
1946 				dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1947 					"unexpected RRD buffer count\n");
1948 				dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1949 					"rx_buf_len = %d\n",
1950 					adapter->rx_buffer_len);
1951 				dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1952 					"RRD num_buf = %d\n",
1953 					rrd->num_buf);
1954 				dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1955 					"RRD pkt_len = %d\n",
1956 					rrd->xsz.xsum_sz.pkt_size);
1957 				dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1958 					"RRD pkt_flg = 0x%08X\n",
1959 					rrd->pkt_flg);
1960 				dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1961 					"RRD err_flg = 0x%08X\n",
1962 					rrd->err_flg);
1963 				dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1964 					"RRD vlan_tag = 0x%08X\n",
1965 					rrd->vlan_tag);
1966 			}
1967 
1968 			/* rrd seems to be bad */
1969 			if (unlikely(i-- > 0)) {
1970 				/* rrd may not be DMAed completely */
1971 				udelay(1);
1972 				goto chk_rrd;
1973 			}
1974 			/* bad rrd */
1975 			if (netif_msg_rx_err(adapter))
1976 				dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1977 					"bad RRD\n");
1978 			/* see if update RFD index */
1979 			if (rrd->num_buf > 1)
1980 				atl1_update_rfd_index(adapter, rrd);
1981 
1982 			/* update rrd */
1983 			rrd->xsz.valid = 0;
1984 			if (++rrd_next_to_clean == rrd_ring->count)
1985 				rrd_next_to_clean = 0;
1986 			count++;
1987 			continue;
1988 		} else {	/* current rrd still not be updated */
1989 
1990 			break;
1991 		}
1992 rrd_ok:
1993 		/* clean alloc flag for bad rrd */
1994 		atl1_clean_alloc_flag(adapter, rrd, 0);
1995 
1996 		buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
1997 		if (++rfd_ring->next_to_clean == rfd_ring->count)
1998 			rfd_ring->next_to_clean = 0;
1999 
2000 		/* update rrd next to clean */
2001 		if (++rrd_next_to_clean == rrd_ring->count)
2002 			rrd_next_to_clean = 0;
2003 		count++;
2004 
2005 		if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
2006 			if (!(rrd->err_flg &
2007 				(ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
2008 				| ERR_FLAG_LEN))) {
2009 				/* packet error, don't need upstream */
2010 				buffer_info->alloced = 0;
2011 				rrd->xsz.valid = 0;
2012 				continue;
2013 			}
2014 		}
2015 
2016 		/* Good Receive */
2017 		pci_unmap_page(adapter->pdev, buffer_info->dma,
2018 			       buffer_info->length, PCI_DMA_FROMDEVICE);
2019 		buffer_info->dma = 0;
2020 		skb = buffer_info->skb;
2021 		length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
2022 
2023 		skb_put(skb, length - ETH_FCS_LEN);
2024 
2025 		/* Receive Checksum Offload */
2026 		atl1_rx_checksum(adapter, rrd, skb);
2027 		skb->protocol = eth_type_trans(skb, adapter->netdev);
2028 
2029 		if (rrd->pkt_flg & PACKET_FLAG_VLAN_INS) {
2030 			u16 vlan_tag = (rrd->vlan_tag >> 4) |
2031 					((rrd->vlan_tag & 7) << 13) |
2032 					((rrd->vlan_tag & 8) << 9);
2033 
2034 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
2035 		}
2036 		netif_receive_skb(skb);
2037 
2038 		/* let protocol layer free skb */
2039 		buffer_info->skb = NULL;
2040 		buffer_info->alloced = 0;
2041 		rrd->xsz.valid = 0;
2042 	}
2043 
2044 	atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
2045 
2046 	atl1_alloc_rx_buffers(adapter);
2047 
2048 	/* update mailbox ? */
2049 	if (count) {
2050 		u32 tpd_next_to_use;
2051 		u32 rfd_next_to_use;
2052 
2053 		spin_lock(&adapter->mb_lock);
2054 
2055 		tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
2056 		rfd_next_to_use =
2057 		    atomic_read(&adapter->rfd_ring.next_to_use);
2058 		rrd_next_to_clean =
2059 		    atomic_read(&adapter->rrd_ring.next_to_clean);
2060 		value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
2061 			MB_RFD_PROD_INDX_SHIFT) |
2062                         ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
2063 			MB_RRD_CONS_INDX_SHIFT) |
2064                         ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
2065 			MB_TPD_PROD_INDX_SHIFT);
2066 		iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2067 		spin_unlock(&adapter->mb_lock);
2068 	}
2069 
2070 	return count;
2071 }
2072 
2073 static int atl1_intr_tx(struct atl1_adapter *adapter)
2074 {
2075 	struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2076 	struct atl1_buffer *buffer_info;
2077 	u16 sw_tpd_next_to_clean;
2078 	u16 cmb_tpd_next_to_clean;
2079 	int count = 0;
2080 
2081 	sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2082 	cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
2083 
2084 	while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
2085 		buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
2086 		if (buffer_info->dma) {
2087 			pci_unmap_page(adapter->pdev, buffer_info->dma,
2088 				       buffer_info->length, PCI_DMA_TODEVICE);
2089 			buffer_info->dma = 0;
2090 		}
2091 
2092 		if (buffer_info->skb) {
2093 			dev_kfree_skb_irq(buffer_info->skb);
2094 			buffer_info->skb = NULL;
2095 		}
2096 
2097 		if (++sw_tpd_next_to_clean == tpd_ring->count)
2098 			sw_tpd_next_to_clean = 0;
2099 
2100 		count++;
2101 	}
2102 	atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
2103 
2104 	if (netif_queue_stopped(adapter->netdev) &&
2105 	    netif_carrier_ok(adapter->netdev))
2106 		netif_wake_queue(adapter->netdev);
2107 
2108 	return count;
2109 }
2110 
2111 static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
2112 {
2113 	u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2114 	u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
2115 	return (next_to_clean > next_to_use) ?
2116 		next_to_clean - next_to_use - 1 :
2117 		tpd_ring->count + next_to_clean - next_to_use - 1;
2118 }
2119 
2120 static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
2121 		    struct tx_packet_desc *ptpd)
2122 {
2123 	u8 hdr_len, ip_off;
2124 	u32 real_len;
2125 
2126 	if (skb_shinfo(skb)->gso_size) {
2127 		int err;
2128 
2129 		err = skb_cow_head(skb, 0);
2130 		if (err < 0)
2131 			return err;
2132 
2133 		if (skb->protocol == htons(ETH_P_IP)) {
2134 			struct iphdr *iph = ip_hdr(skb);
2135 
2136 			real_len = (((unsigned char *)iph - skb->data) +
2137 				ntohs(iph->tot_len));
2138 			if (real_len < skb->len)
2139 				pskb_trim(skb, real_len);
2140 			hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2141 			if (skb->len == hdr_len) {
2142 				iph->check = 0;
2143 				tcp_hdr(skb)->check =
2144 					~csum_tcpudp_magic(iph->saddr,
2145 					iph->daddr, tcp_hdrlen(skb),
2146 					IPPROTO_TCP, 0);
2147 				ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2148 					TPD_IPHL_SHIFT;
2149 				ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2150 					TPD_TCPHDRLEN_MASK) <<
2151 					TPD_TCPHDRLEN_SHIFT;
2152 				ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
2153 				ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
2154 				return 1;
2155 			}
2156 
2157 			iph->check = 0;
2158 			tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2159 					iph->daddr, 0, IPPROTO_TCP, 0);
2160 			ip_off = (unsigned char *)iph -
2161 				(unsigned char *) skb_network_header(skb);
2162 			if (ip_off == 8) /* 802.3-SNAP frame */
2163 				ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
2164 			else if (ip_off != 0)
2165 				return -2;
2166 
2167 			ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2168 				TPD_IPHL_SHIFT;
2169 			ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2170 				TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
2171 			ptpd->word3 |= (skb_shinfo(skb)->gso_size &
2172 				TPD_MSS_MASK) << TPD_MSS_SHIFT;
2173 			ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
2174 			return 3;
2175 		}
2176 	}
2177 	return 0;
2178 }
2179 
2180 static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
2181 	struct tx_packet_desc *ptpd)
2182 {
2183 	u8 css, cso;
2184 
2185 	if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2186 		css = skb_checksum_start_offset(skb);
2187 		cso = css + (u8) skb->csum_offset;
2188 		if (unlikely(css & 0x1)) {
2189 			/* L1 hardware requires an even number here */
2190 			if (netif_msg_tx_err(adapter))
2191 				dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2192 					"payload offset not an even number\n");
2193 			return -1;
2194 		}
2195 		ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
2196 			TPD_PLOADOFFSET_SHIFT;
2197 		ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
2198 			TPD_CCSUMOFFSET_SHIFT;
2199 		ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
2200 		return true;
2201 	}
2202 	return 0;
2203 }
2204 
2205 static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
2206 	struct tx_packet_desc *ptpd)
2207 {
2208 	struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2209 	struct atl1_buffer *buffer_info;
2210 	u16 buf_len = skb->len;
2211 	struct page *page;
2212 	unsigned long offset;
2213 	unsigned int nr_frags;
2214 	unsigned int f;
2215 	int retval;
2216 	u16 next_to_use;
2217 	u16 data_len;
2218 	u8 hdr_len;
2219 
2220 	buf_len -= skb->data_len;
2221 	nr_frags = skb_shinfo(skb)->nr_frags;
2222 	next_to_use = atomic_read(&tpd_ring->next_to_use);
2223 	buffer_info = &tpd_ring->buffer_info[next_to_use];
2224 	BUG_ON(buffer_info->skb);
2225 	/* put skb in last TPD */
2226 	buffer_info->skb = NULL;
2227 
2228 	retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
2229 	if (retval) {
2230 		/* TSO */
2231 		hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2232 		buffer_info->length = hdr_len;
2233 		page = virt_to_page(skb->data);
2234 		offset = (unsigned long)skb->data & ~PAGE_MASK;
2235 		buffer_info->dma = pci_map_page(adapter->pdev, page,
2236 						offset, hdr_len,
2237 						PCI_DMA_TODEVICE);
2238 
2239 		if (++next_to_use == tpd_ring->count)
2240 			next_to_use = 0;
2241 
2242 		if (buf_len > hdr_len) {
2243 			int i, nseg;
2244 
2245 			data_len = buf_len - hdr_len;
2246 			nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
2247 				ATL1_MAX_TX_BUF_LEN;
2248 			for (i = 0; i < nseg; i++) {
2249 				buffer_info =
2250 				    &tpd_ring->buffer_info[next_to_use];
2251 				buffer_info->skb = NULL;
2252 				buffer_info->length =
2253 				    (ATL1_MAX_TX_BUF_LEN >=
2254 				     data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
2255 				data_len -= buffer_info->length;
2256 				page = virt_to_page(skb->data +
2257 					(hdr_len + i * ATL1_MAX_TX_BUF_LEN));
2258 				offset = (unsigned long)(skb->data +
2259 					(hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
2260 					~PAGE_MASK;
2261 				buffer_info->dma = pci_map_page(adapter->pdev,
2262 					page, offset, buffer_info->length,
2263 					PCI_DMA_TODEVICE);
2264 				if (++next_to_use == tpd_ring->count)
2265 					next_to_use = 0;
2266 			}
2267 		}
2268 	} else {
2269 		/* not TSO */
2270 		buffer_info->length = buf_len;
2271 		page = virt_to_page(skb->data);
2272 		offset = (unsigned long)skb->data & ~PAGE_MASK;
2273 		buffer_info->dma = pci_map_page(adapter->pdev, page,
2274 			offset, buf_len, PCI_DMA_TODEVICE);
2275 		if (++next_to_use == tpd_ring->count)
2276 			next_to_use = 0;
2277 	}
2278 
2279 	for (f = 0; f < nr_frags; f++) {
2280 		const struct skb_frag_struct *frag;
2281 		u16 i, nseg;
2282 
2283 		frag = &skb_shinfo(skb)->frags[f];
2284 		buf_len = skb_frag_size(frag);
2285 
2286 		nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
2287 			ATL1_MAX_TX_BUF_LEN;
2288 		for (i = 0; i < nseg; i++) {
2289 			buffer_info = &tpd_ring->buffer_info[next_to_use];
2290 			BUG_ON(buffer_info->skb);
2291 
2292 			buffer_info->skb = NULL;
2293 			buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
2294 				ATL1_MAX_TX_BUF_LEN : buf_len;
2295 			buf_len -= buffer_info->length;
2296 			buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev,
2297 				frag, i * ATL1_MAX_TX_BUF_LEN,
2298 				buffer_info->length, DMA_TO_DEVICE);
2299 
2300 			if (++next_to_use == tpd_ring->count)
2301 				next_to_use = 0;
2302 		}
2303 	}
2304 
2305 	/* last tpd's buffer-info */
2306 	buffer_info->skb = skb;
2307 }
2308 
2309 static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
2310        struct tx_packet_desc *ptpd)
2311 {
2312 	struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2313 	struct atl1_buffer *buffer_info;
2314 	struct tx_packet_desc *tpd;
2315 	u16 j;
2316 	u32 val;
2317 	u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
2318 
2319 	for (j = 0; j < count; j++) {
2320 		buffer_info = &tpd_ring->buffer_info[next_to_use];
2321 		tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
2322 		if (tpd != ptpd)
2323 			memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
2324 		tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2325 		tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT);
2326 		tpd->word2 |= (cpu_to_le16(buffer_info->length) &
2327 			TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
2328 
2329 		/*
2330 		 * if this is the first packet in a TSO chain, set
2331 		 * TPD_HDRFLAG, otherwise, clear it.
2332 		 */
2333 		val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
2334 			TPD_SEGMENT_EN_MASK;
2335 		if (val) {
2336 			if (!j)
2337 				tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
2338 			else
2339 				tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
2340 		}
2341 
2342 		if (j == (count - 1))
2343 			tpd->word3 |= 1 << TPD_EOP_SHIFT;
2344 
2345 		if (++next_to_use == tpd_ring->count)
2346 			next_to_use = 0;
2347 	}
2348 	/*
2349 	 * Force memory writes to complete before letting h/w
2350 	 * know there are new descriptors to fetch.  (Only
2351 	 * applicable for weak-ordered memory model archs,
2352 	 * such as IA-64).
2353 	 */
2354 	wmb();
2355 
2356 	atomic_set(&tpd_ring->next_to_use, next_to_use);
2357 }
2358 
2359 static netdev_tx_t atl1_xmit_frame(struct sk_buff *skb,
2360 					 struct net_device *netdev)
2361 {
2362 	struct atl1_adapter *adapter = netdev_priv(netdev);
2363 	struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2364 	int len;
2365 	int tso;
2366 	int count = 1;
2367 	int ret_val;
2368 	struct tx_packet_desc *ptpd;
2369 	u16 vlan_tag;
2370 	unsigned int nr_frags = 0;
2371 	unsigned int mss = 0;
2372 	unsigned int f;
2373 	unsigned int proto_hdr_len;
2374 
2375 	len = skb_headlen(skb);
2376 
2377 	if (unlikely(skb->len <= 0)) {
2378 		dev_kfree_skb_any(skb);
2379 		return NETDEV_TX_OK;
2380 	}
2381 
2382 	nr_frags = skb_shinfo(skb)->nr_frags;
2383 	for (f = 0; f < nr_frags; f++) {
2384 		unsigned int f_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2385 		count += (f_size + ATL1_MAX_TX_BUF_LEN - 1) /
2386 			 ATL1_MAX_TX_BUF_LEN;
2387 	}
2388 
2389 	mss = skb_shinfo(skb)->gso_size;
2390 	if (mss) {
2391 		if (skb->protocol == htons(ETH_P_IP)) {
2392 			proto_hdr_len = (skb_transport_offset(skb) +
2393 					 tcp_hdrlen(skb));
2394 			if (unlikely(proto_hdr_len > len)) {
2395 				dev_kfree_skb_any(skb);
2396 				return NETDEV_TX_OK;
2397 			}
2398 			/* need additional TPD ? */
2399 			if (proto_hdr_len != len)
2400 				count += (len - proto_hdr_len +
2401 					ATL1_MAX_TX_BUF_LEN - 1) /
2402 					ATL1_MAX_TX_BUF_LEN;
2403 		}
2404 	}
2405 
2406 	if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
2407 		/* not enough descriptors */
2408 		netif_stop_queue(netdev);
2409 		if (netif_msg_tx_queued(adapter))
2410 			dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2411 				"tx busy\n");
2412 		return NETDEV_TX_BUSY;
2413 	}
2414 
2415 	ptpd = ATL1_TPD_DESC(tpd_ring,
2416 		(u16) atomic_read(&tpd_ring->next_to_use));
2417 	memset(ptpd, 0, sizeof(struct tx_packet_desc));
2418 
2419 	if (vlan_tx_tag_present(skb)) {
2420 		vlan_tag = vlan_tx_tag_get(skb);
2421 		vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
2422 			((vlan_tag >> 9) & 0x8);
2423 		ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
2424 		ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) <<
2425 			TPD_VLANTAG_SHIFT;
2426 	}
2427 
2428 	tso = atl1_tso(adapter, skb, ptpd);
2429 	if (tso < 0) {
2430 		dev_kfree_skb_any(skb);
2431 		return NETDEV_TX_OK;
2432 	}
2433 
2434 	if (!tso) {
2435 		ret_val = atl1_tx_csum(adapter, skb, ptpd);
2436 		if (ret_val < 0) {
2437 			dev_kfree_skb_any(skb);
2438 			return NETDEV_TX_OK;
2439 		}
2440 	}
2441 
2442 	atl1_tx_map(adapter, skb, ptpd);
2443 	atl1_tx_queue(adapter, count, ptpd);
2444 	atl1_update_mailbox(adapter);
2445 	mmiowb();
2446 	return NETDEV_TX_OK;
2447 }
2448 
2449 static int atl1_rings_clean(struct napi_struct *napi, int budget)
2450 {
2451 	struct atl1_adapter *adapter = container_of(napi, struct atl1_adapter, napi);
2452 	int work_done = atl1_intr_rx(adapter, budget);
2453 
2454 	if (atl1_intr_tx(adapter))
2455 		work_done = budget;
2456 
2457 	/* Let's come again to process some more packets */
2458 	if (work_done >= budget)
2459 		return work_done;
2460 
2461 	napi_complete(napi);
2462 	/* re-enable Interrupt */
2463 	if (likely(adapter->int_enabled))
2464 		atlx_imr_set(adapter, IMR_NORMAL_MASK);
2465 	return work_done;
2466 }
2467 
2468 static inline int atl1_sched_rings_clean(struct atl1_adapter* adapter)
2469 {
2470 	if (!napi_schedule_prep(&adapter->napi))
2471 		/* It is possible in case even the RX/TX ints are disabled via IMR
2472 		 * register the ISR bits are set anyway (but do not produce IRQ).
2473 		 * To handle such situation the napi functions used to check is
2474 		 * something scheduled or not.
2475 		 */
2476 		return 0;
2477 
2478 	__napi_schedule(&adapter->napi);
2479 
2480 	/*
2481 	 * Disable RX/TX ints via IMR register if it is
2482 	 * allowed. NAPI handler must reenable them in same
2483 	 * way.
2484 	 */
2485 	if (!adapter->int_enabled)
2486 		return 1;
2487 
2488 	atlx_imr_set(adapter, IMR_NORXTX_MASK);
2489 	return 1;
2490 }
2491 
2492 /**
2493  * atl1_intr - Interrupt Handler
2494  * @irq: interrupt number
2495  * @data: pointer to a network interface device structure
2496  */
2497 static irqreturn_t atl1_intr(int irq, void *data)
2498 {
2499 	struct atl1_adapter *adapter = netdev_priv(data);
2500 	u32 status;
2501 
2502 	status = adapter->cmb.cmb->int_stats;
2503 	if (!status)
2504 		return IRQ_NONE;
2505 
2506 	/* clear CMB interrupt status at once,
2507 	 * but leave rx/tx interrupt status in case it should be dropped
2508 	 * only if rx/tx processing queued. In other case interrupt
2509 	 * can be lost.
2510 	 */
2511 	adapter->cmb.cmb->int_stats = status & (ISR_CMB_TX | ISR_CMB_RX);
2512 
2513 	if (status & ISR_GPHY)	/* clear phy status */
2514 		atlx_clear_phy_int(adapter);
2515 
2516 	/* clear ISR status, and Enable CMB DMA/Disable Interrupt */
2517 	iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
2518 
2519 	/* check if SMB intr */
2520 	if (status & ISR_SMB)
2521 		atl1_inc_smb(adapter);
2522 
2523 	/* check if PCIE PHY Link down */
2524 	if (status & ISR_PHY_LINKDOWN) {
2525 		if (netif_msg_intr(adapter))
2526 			dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2527 				"pcie phy link down %x\n", status);
2528 		if (netif_running(adapter->netdev)) {	/* reset MAC */
2529 			atlx_irq_disable(adapter);
2530 			schedule_work(&adapter->reset_dev_task);
2531 			return IRQ_HANDLED;
2532 		}
2533 	}
2534 
2535 	/* check if DMA read/write error ? */
2536 	if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
2537 		if (netif_msg_intr(adapter))
2538 			dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2539 				"pcie DMA r/w error (status = 0x%x)\n",
2540 				status);
2541 		atlx_irq_disable(adapter);
2542 		schedule_work(&adapter->reset_dev_task);
2543 		return IRQ_HANDLED;
2544 	}
2545 
2546 	/* link event */
2547 	if (status & ISR_GPHY) {
2548 		adapter->soft_stats.tx_carrier_errors++;
2549 		atl1_check_for_link(adapter);
2550 	}
2551 
2552 	/* transmit or receive event */
2553 	if (status & (ISR_CMB_TX | ISR_CMB_RX) &&
2554 	    atl1_sched_rings_clean(adapter))
2555 		adapter->cmb.cmb->int_stats = adapter->cmb.cmb->int_stats &
2556 					      ~(ISR_CMB_TX | ISR_CMB_RX);
2557 
2558 	/* rx exception */
2559 	if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2560 		ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2561 		ISR_HOST_RRD_OV))) {
2562 		if (netif_msg_intr(adapter))
2563 			dev_printk(KERN_DEBUG,
2564 				&adapter->pdev->dev,
2565 				"rx exception, ISR = 0x%x\n",
2566 				status);
2567 		atl1_sched_rings_clean(adapter);
2568 	}
2569 
2570 	/* re-enable Interrupt */
2571 	iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
2572 	return IRQ_HANDLED;
2573 }
2574 
2575 
2576 /**
2577  * atl1_phy_config - Timer Call-back
2578  * @data: pointer to netdev cast into an unsigned long
2579  */
2580 static void atl1_phy_config(unsigned long data)
2581 {
2582 	struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2583 	struct atl1_hw *hw = &adapter->hw;
2584 	unsigned long flags;
2585 
2586 	spin_lock_irqsave(&adapter->lock, flags);
2587 	adapter->phy_timer_pending = false;
2588 	atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
2589 	atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
2590 	atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
2591 	spin_unlock_irqrestore(&adapter->lock, flags);
2592 }
2593 
2594 /*
2595  * Orphaned vendor comment left intact here:
2596  * <vendor comment>
2597  * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2598  * will assert. We do soft reset <0x1400=1> according
2599  * with the SPEC. BUT, it seemes that PCIE or DMA
2600  * state-machine will not be reset. DMAR_TO_INT will
2601  * assert again and again.
2602  * </vendor comment>
2603  */
2604 
2605 static int atl1_reset(struct atl1_adapter *adapter)
2606 {
2607 	int ret;
2608 	ret = atl1_reset_hw(&adapter->hw);
2609 	if (ret)
2610 		return ret;
2611 	return atl1_init_hw(&adapter->hw);
2612 }
2613 
2614 static s32 atl1_up(struct atl1_adapter *adapter)
2615 {
2616 	struct net_device *netdev = adapter->netdev;
2617 	int err;
2618 	int irq_flags = 0;
2619 
2620 	/* hardware has been reset, we need to reload some things */
2621 	atlx_set_multi(netdev);
2622 	atl1_init_ring_ptrs(adapter);
2623 	atlx_restore_vlan(adapter);
2624 	err = atl1_alloc_rx_buffers(adapter);
2625 	if (unlikely(!err))
2626 		/* no RX BUFFER allocated */
2627 		return -ENOMEM;
2628 
2629 	if (unlikely(atl1_configure(adapter))) {
2630 		err = -EIO;
2631 		goto err_up;
2632 	}
2633 
2634 	err = pci_enable_msi(adapter->pdev);
2635 	if (err) {
2636 		if (netif_msg_ifup(adapter))
2637 			dev_info(&adapter->pdev->dev,
2638 				"Unable to enable MSI: %d\n", err);
2639 		irq_flags |= IRQF_SHARED;
2640 	}
2641 
2642 	err = request_irq(adapter->pdev->irq, atl1_intr, irq_flags,
2643 			netdev->name, netdev);
2644 	if (unlikely(err))
2645 		goto err_up;
2646 
2647 	napi_enable(&adapter->napi);
2648 	atlx_irq_enable(adapter);
2649 	atl1_check_link(adapter);
2650 	netif_start_queue(netdev);
2651 	return 0;
2652 
2653 err_up:
2654 	pci_disable_msi(adapter->pdev);
2655 	/* free rx_buffers */
2656 	atl1_clean_rx_ring(adapter);
2657 	return err;
2658 }
2659 
2660 static void atl1_down(struct atl1_adapter *adapter)
2661 {
2662 	struct net_device *netdev = adapter->netdev;
2663 
2664 	napi_disable(&adapter->napi);
2665 	netif_stop_queue(netdev);
2666 	del_timer_sync(&adapter->phy_config_timer);
2667 	adapter->phy_timer_pending = false;
2668 
2669 	atlx_irq_disable(adapter);
2670 	free_irq(adapter->pdev->irq, netdev);
2671 	pci_disable_msi(adapter->pdev);
2672 	atl1_reset_hw(&adapter->hw);
2673 	adapter->cmb.cmb->int_stats = 0;
2674 
2675 	adapter->link_speed = SPEED_0;
2676 	adapter->link_duplex = -1;
2677 	netif_carrier_off(netdev);
2678 
2679 	atl1_clean_tx_ring(adapter);
2680 	atl1_clean_rx_ring(adapter);
2681 }
2682 
2683 static void atl1_reset_dev_task(struct work_struct *work)
2684 {
2685 	struct atl1_adapter *adapter =
2686 		container_of(work, struct atl1_adapter, reset_dev_task);
2687 	struct net_device *netdev = adapter->netdev;
2688 
2689 	netif_device_detach(netdev);
2690 	atl1_down(adapter);
2691 	atl1_up(adapter);
2692 	netif_device_attach(netdev);
2693 }
2694 
2695 /**
2696  * atl1_change_mtu - Change the Maximum Transfer Unit
2697  * @netdev: network interface device structure
2698  * @new_mtu: new value for maximum frame size
2699  *
2700  * Returns 0 on success, negative on failure
2701  */
2702 static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
2703 {
2704 	struct atl1_adapter *adapter = netdev_priv(netdev);
2705 	int old_mtu = netdev->mtu;
2706 	int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
2707 
2708 	if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2709 	    (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2710 		if (netif_msg_link(adapter))
2711 			dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
2712 		return -EINVAL;
2713 	}
2714 
2715 	adapter->hw.max_frame_size = max_frame;
2716 	adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
2717 	adapter->rx_buffer_len = (max_frame + 7) & ~7;
2718 	adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
2719 
2720 	netdev->mtu = new_mtu;
2721 	if ((old_mtu != new_mtu) && netif_running(netdev)) {
2722 		atl1_down(adapter);
2723 		atl1_up(adapter);
2724 	}
2725 
2726 	return 0;
2727 }
2728 
2729 /**
2730  * atl1_open - Called when a network interface is made active
2731  * @netdev: network interface device structure
2732  *
2733  * Returns 0 on success, negative value on failure
2734  *
2735  * The open entry point is called when a network interface is made
2736  * active by the system (IFF_UP).  At this point all resources needed
2737  * for transmit and receive operations are allocated, the interrupt
2738  * handler is registered with the OS, the watchdog timer is started,
2739  * and the stack is notified that the interface is ready.
2740  */
2741 static int atl1_open(struct net_device *netdev)
2742 {
2743 	struct atl1_adapter *adapter = netdev_priv(netdev);
2744 	int err;
2745 
2746 	netif_carrier_off(netdev);
2747 
2748 	/* allocate transmit descriptors */
2749 	err = atl1_setup_ring_resources(adapter);
2750 	if (err)
2751 		return err;
2752 
2753 	err = atl1_up(adapter);
2754 	if (err)
2755 		goto err_up;
2756 
2757 	return 0;
2758 
2759 err_up:
2760 	atl1_reset(adapter);
2761 	return err;
2762 }
2763 
2764 /**
2765  * atl1_close - Disables a network interface
2766  * @netdev: network interface device structure
2767  *
2768  * Returns 0, this is not allowed to fail
2769  *
2770  * The close entry point is called when an interface is de-activated
2771  * by the OS.  The hardware is still under the drivers control, but
2772  * needs to be disabled.  A global MAC reset is issued to stop the
2773  * hardware, and all transmit and receive resources are freed.
2774  */
2775 static int atl1_close(struct net_device *netdev)
2776 {
2777 	struct atl1_adapter *adapter = netdev_priv(netdev);
2778 	atl1_down(adapter);
2779 	atl1_free_ring_resources(adapter);
2780 	return 0;
2781 }
2782 
2783 #ifdef CONFIG_PM_SLEEP
2784 static int atl1_suspend(struct device *dev)
2785 {
2786 	struct pci_dev *pdev = to_pci_dev(dev);
2787 	struct net_device *netdev = pci_get_drvdata(pdev);
2788 	struct atl1_adapter *adapter = netdev_priv(netdev);
2789 	struct atl1_hw *hw = &adapter->hw;
2790 	u32 ctrl = 0;
2791 	u32 wufc = adapter->wol;
2792 	u32 val;
2793 	u16 speed;
2794 	u16 duplex;
2795 
2796 	netif_device_detach(netdev);
2797 	if (netif_running(netdev))
2798 		atl1_down(adapter);
2799 
2800 	atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2801 	atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2802 	val = ctrl & BMSR_LSTATUS;
2803 	if (val)
2804 		wufc &= ~ATLX_WUFC_LNKC;
2805 	if (!wufc)
2806 		goto disable_wol;
2807 
2808 	if (val) {
2809 		val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
2810 		if (val) {
2811 			if (netif_msg_ifdown(adapter))
2812 				dev_printk(KERN_DEBUG, &pdev->dev,
2813 					"error getting speed/duplex\n");
2814 			goto disable_wol;
2815 		}
2816 
2817 		ctrl = 0;
2818 
2819 		/* enable magic packet WOL */
2820 		if (wufc & ATLX_WUFC_MAG)
2821 			ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
2822 		iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2823 		ioread32(hw->hw_addr + REG_WOL_CTRL);
2824 
2825 		/* configure the mac */
2826 		ctrl = MAC_CTRL_RX_EN;
2827 		ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 :
2828 			MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT);
2829 		if (duplex == FULL_DUPLEX)
2830 			ctrl |= MAC_CTRL_DUPLX;
2831 		ctrl |= (((u32)adapter->hw.preamble_len &
2832 			MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
2833 		__atlx_vlan_mode(netdev->features, &ctrl);
2834 		if (wufc & ATLX_WUFC_MAG)
2835 			ctrl |= MAC_CTRL_BC_EN;
2836 		iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2837 		ioread32(hw->hw_addr + REG_MAC_CTRL);
2838 
2839 		/* poke the PHY */
2840 		ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2841 		ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2842 		iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2843 		ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2844 	} else {
2845 		ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2846 		iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2847 		ioread32(hw->hw_addr + REG_WOL_CTRL);
2848 		iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
2849 		ioread32(hw->hw_addr + REG_MAC_CTRL);
2850 		hw->phy_configured = false;
2851 	}
2852 
2853 	return 0;
2854 
2855  disable_wol:
2856 	iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2857 	ioread32(hw->hw_addr + REG_WOL_CTRL);
2858 	ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2859 	ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2860 	iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2861 	ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2862 	hw->phy_configured = false;
2863 
2864 	return 0;
2865 }
2866 
2867 static int atl1_resume(struct device *dev)
2868 {
2869 	struct pci_dev *pdev = to_pci_dev(dev);
2870 	struct net_device *netdev = pci_get_drvdata(pdev);
2871 	struct atl1_adapter *adapter = netdev_priv(netdev);
2872 
2873 	iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
2874 
2875 	atl1_reset_hw(&adapter->hw);
2876 
2877 	if (netif_running(netdev)) {
2878 		adapter->cmb.cmb->int_stats = 0;
2879 		atl1_up(adapter);
2880 	}
2881 	netif_device_attach(netdev);
2882 
2883 	return 0;
2884 }
2885 #endif
2886 
2887 static SIMPLE_DEV_PM_OPS(atl1_pm_ops, atl1_suspend, atl1_resume);
2888 
2889 static void atl1_shutdown(struct pci_dev *pdev)
2890 {
2891 	struct net_device *netdev = pci_get_drvdata(pdev);
2892 	struct atl1_adapter *adapter = netdev_priv(netdev);
2893 
2894 #ifdef CONFIG_PM_SLEEP
2895 	atl1_suspend(&pdev->dev);
2896 #endif
2897 	pci_wake_from_d3(pdev, adapter->wol);
2898 	pci_set_power_state(pdev, PCI_D3hot);
2899 }
2900 
2901 #ifdef CONFIG_NET_POLL_CONTROLLER
2902 static void atl1_poll_controller(struct net_device *netdev)
2903 {
2904 	disable_irq(netdev->irq);
2905 	atl1_intr(netdev->irq, netdev);
2906 	enable_irq(netdev->irq);
2907 }
2908 #endif
2909 
2910 static const struct net_device_ops atl1_netdev_ops = {
2911 	.ndo_open		= atl1_open,
2912 	.ndo_stop		= atl1_close,
2913 	.ndo_start_xmit		= atl1_xmit_frame,
2914 	.ndo_set_rx_mode	= atlx_set_multi,
2915 	.ndo_validate_addr	= eth_validate_addr,
2916 	.ndo_set_mac_address	= atl1_set_mac,
2917 	.ndo_change_mtu		= atl1_change_mtu,
2918 	.ndo_fix_features	= atlx_fix_features,
2919 	.ndo_set_features	= atlx_set_features,
2920 	.ndo_do_ioctl		= atlx_ioctl,
2921 	.ndo_tx_timeout		= atlx_tx_timeout,
2922 #ifdef CONFIG_NET_POLL_CONTROLLER
2923 	.ndo_poll_controller	= atl1_poll_controller,
2924 #endif
2925 };
2926 
2927 /**
2928  * atl1_probe - Device Initialization Routine
2929  * @pdev: PCI device information struct
2930  * @ent: entry in atl1_pci_tbl
2931  *
2932  * Returns 0 on success, negative on failure
2933  *
2934  * atl1_probe initializes an adapter identified by a pci_dev structure.
2935  * The OS initialization, configuring of the adapter private structure,
2936  * and a hardware reset occur.
2937  */
2938 static int atl1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2939 {
2940 	struct net_device *netdev;
2941 	struct atl1_adapter *adapter;
2942 	static int cards_found = 0;
2943 	int err;
2944 
2945 	err = pci_enable_device(pdev);
2946 	if (err)
2947 		return err;
2948 
2949 	/*
2950 	 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2951 	 * shared register for the high 32 bits, so only a single, aligned,
2952 	 * 4 GB physical address range can be used at a time.
2953 	 *
2954 	 * Supporting 64-bit DMA on this hardware is more trouble than it's
2955 	 * worth.  It is far easier to limit to 32-bit DMA than update
2956 	 * various kernel subsystems to support the mechanics required by a
2957 	 * fixed-high-32-bit system.
2958 	 */
2959 	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2960 	if (err) {
2961 		dev_err(&pdev->dev, "no usable DMA configuration\n");
2962 		goto err_dma;
2963 	}
2964 	/*
2965 	 * Mark all PCI regions associated with PCI device
2966 	 * pdev as being reserved by owner atl1_driver_name
2967 	 */
2968 	err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
2969 	if (err)
2970 		goto err_request_regions;
2971 
2972 	/*
2973 	 * Enables bus-mastering on the device and calls
2974 	 * pcibios_set_master to do the needed arch specific settings
2975 	 */
2976 	pci_set_master(pdev);
2977 
2978 	netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2979 	if (!netdev) {
2980 		err = -ENOMEM;
2981 		goto err_alloc_etherdev;
2982 	}
2983 	SET_NETDEV_DEV(netdev, &pdev->dev);
2984 
2985 	pci_set_drvdata(pdev, netdev);
2986 	adapter = netdev_priv(netdev);
2987 	adapter->netdev = netdev;
2988 	adapter->pdev = pdev;
2989 	adapter->hw.back = adapter;
2990 	adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
2991 
2992 	adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2993 	if (!adapter->hw.hw_addr) {
2994 		err = -EIO;
2995 		goto err_pci_iomap;
2996 	}
2997 	/* get device revision number */
2998 	adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
2999 		(REG_MASTER_CTRL + 2));
3000 	if (netif_msg_probe(adapter))
3001 		dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
3002 
3003 	/* set default ring resource counts */
3004 	adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
3005 	adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
3006 
3007 	adapter->mii.dev = netdev;
3008 	adapter->mii.mdio_read = mdio_read;
3009 	adapter->mii.mdio_write = mdio_write;
3010 	adapter->mii.phy_id_mask = 0x1f;
3011 	adapter->mii.reg_num_mask = 0x1f;
3012 
3013 	netdev->netdev_ops = &atl1_netdev_ops;
3014 	netdev->watchdog_timeo = 5 * HZ;
3015 	netif_napi_add(netdev, &adapter->napi, atl1_rings_clean, 64);
3016 
3017 	netdev->ethtool_ops = &atl1_ethtool_ops;
3018 	adapter->bd_number = cards_found;
3019 
3020 	/* setup the private structure */
3021 	err = atl1_sw_init(adapter);
3022 	if (err)
3023 		goto err_common;
3024 
3025 	netdev->features = NETIF_F_HW_CSUM;
3026 	netdev->features |= NETIF_F_SG;
3027 	netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
3028 
3029 	netdev->hw_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_TSO |
3030 			      NETIF_F_HW_VLAN_CTAG_RX;
3031 
3032 	/* is this valid? see atl1_setup_mac_ctrl() */
3033 	netdev->features |= NETIF_F_RXCSUM;
3034 
3035 	/*
3036 	 * patch for some L1 of old version,
3037 	 * the final version of L1 may not need these
3038 	 * patches
3039 	 */
3040 	/* atl1_pcie_patch(adapter); */
3041 
3042 	/* really reset GPHY core */
3043 	iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3044 
3045 	/*
3046 	 * reset the controller to
3047 	 * put the device in a known good starting state
3048 	 */
3049 	if (atl1_reset_hw(&adapter->hw)) {
3050 		err = -EIO;
3051 		goto err_common;
3052 	}
3053 
3054 	/* copy the MAC address out of the EEPROM */
3055 	if (atl1_read_mac_addr(&adapter->hw)) {
3056 		/* mark random mac */
3057 		netdev->addr_assign_type = NET_ADDR_RANDOM;
3058 	}
3059 	memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
3060 
3061 	if (!is_valid_ether_addr(netdev->dev_addr)) {
3062 		err = -EIO;
3063 		goto err_common;
3064 	}
3065 
3066 	atl1_check_options(adapter);
3067 
3068 	/* pre-init the MAC, and setup link */
3069 	err = atl1_init_hw(&adapter->hw);
3070 	if (err) {
3071 		err = -EIO;
3072 		goto err_common;
3073 	}
3074 
3075 	atl1_pcie_patch(adapter);
3076 	/* assume we have no link for now */
3077 	netif_carrier_off(netdev);
3078 
3079 	setup_timer(&adapter->phy_config_timer, atl1_phy_config,
3080 		    (unsigned long)adapter);
3081 	adapter->phy_timer_pending = false;
3082 
3083 	INIT_WORK(&adapter->reset_dev_task, atl1_reset_dev_task);
3084 
3085 	INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
3086 
3087 	err = register_netdev(netdev);
3088 	if (err)
3089 		goto err_common;
3090 
3091 	cards_found++;
3092 	atl1_via_workaround(adapter);
3093 	return 0;
3094 
3095 err_common:
3096 	pci_iounmap(pdev, adapter->hw.hw_addr);
3097 err_pci_iomap:
3098 	free_netdev(netdev);
3099 err_alloc_etherdev:
3100 	pci_release_regions(pdev);
3101 err_dma:
3102 err_request_regions:
3103 	pci_disable_device(pdev);
3104 	return err;
3105 }
3106 
3107 /**
3108  * atl1_remove - Device Removal Routine
3109  * @pdev: PCI device information struct
3110  *
3111  * atl1_remove is called by the PCI subsystem to alert the driver
3112  * that it should release a PCI device.  The could be caused by a
3113  * Hot-Plug event, or because the driver is going to be removed from
3114  * memory.
3115  */
3116 static void atl1_remove(struct pci_dev *pdev)
3117 {
3118 	struct net_device *netdev = pci_get_drvdata(pdev);
3119 	struct atl1_adapter *adapter;
3120 	/* Device not available. Return. */
3121 	if (!netdev)
3122 		return;
3123 
3124 	adapter = netdev_priv(netdev);
3125 
3126 	/*
3127 	 * Some atl1 boards lack persistent storage for their MAC, and get it
3128 	 * from the BIOS during POST.  If we've been messing with the MAC
3129 	 * address, we need to save the permanent one.
3130 	 */
3131 	if (!ether_addr_equal_unaligned(adapter->hw.mac_addr,
3132 					adapter->hw.perm_mac_addr)) {
3133 		memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
3134 			ETH_ALEN);
3135 		atl1_set_mac_addr(&adapter->hw);
3136 	}
3137 
3138 	iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3139 	unregister_netdev(netdev);
3140 	pci_iounmap(pdev, adapter->hw.hw_addr);
3141 	pci_release_regions(pdev);
3142 	free_netdev(netdev);
3143 	pci_disable_device(pdev);
3144 }
3145 
3146 static struct pci_driver atl1_driver = {
3147 	.name = ATLX_DRIVER_NAME,
3148 	.id_table = atl1_pci_tbl,
3149 	.probe = atl1_probe,
3150 	.remove = atl1_remove,
3151 	.shutdown = atl1_shutdown,
3152 	.driver.pm = &atl1_pm_ops,
3153 };
3154 
3155 struct atl1_stats {
3156 	char stat_string[ETH_GSTRING_LEN];
3157 	int sizeof_stat;
3158 	int stat_offset;
3159 };
3160 
3161 #define ATL1_STAT(m) \
3162 	sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
3163 
3164 static struct atl1_stats atl1_gstrings_stats[] = {
3165 	{"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
3166 	{"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
3167 	{"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
3168 	{"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
3169 	{"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
3170 	{"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
3171 	{"multicast", ATL1_STAT(soft_stats.multicast)},
3172 	{"collisions", ATL1_STAT(soft_stats.collisions)},
3173 	{"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
3174 	{"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3175 	{"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
3176 	{"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
3177 	{"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
3178 	{"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3179 	{"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
3180 	{"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
3181 	{"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
3182 	{"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
3183 	{"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
3184 	{"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
3185 	{"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
3186 	{"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
3187 	{"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
3188 	{"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
3189 	{"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
3190 	{"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
3191 	{"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
3192 	{"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
3193 	{"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
3194 };
3195 
3196 static void atl1_get_ethtool_stats(struct net_device *netdev,
3197 	struct ethtool_stats *stats, u64 *data)
3198 {
3199 	struct atl1_adapter *adapter = netdev_priv(netdev);
3200 	int i;
3201 	char *p;
3202 
3203 	for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3204 		p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
3205 		data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
3206 			sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
3207 	}
3208 
3209 }
3210 
3211 static int atl1_get_sset_count(struct net_device *netdev, int sset)
3212 {
3213 	switch (sset) {
3214 	case ETH_SS_STATS:
3215 		return ARRAY_SIZE(atl1_gstrings_stats);
3216 	default:
3217 		return -EOPNOTSUPP;
3218 	}
3219 }
3220 
3221 static int atl1_get_settings(struct net_device *netdev,
3222 	struct ethtool_cmd *ecmd)
3223 {
3224 	struct atl1_adapter *adapter = netdev_priv(netdev);
3225 	struct atl1_hw *hw = &adapter->hw;
3226 
3227 	ecmd->supported = (SUPPORTED_10baseT_Half |
3228 			   SUPPORTED_10baseT_Full |
3229 			   SUPPORTED_100baseT_Half |
3230 			   SUPPORTED_100baseT_Full |
3231 			   SUPPORTED_1000baseT_Full |
3232 			   SUPPORTED_Autoneg | SUPPORTED_TP);
3233 	ecmd->advertising = ADVERTISED_TP;
3234 	if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3235 	    hw->media_type == MEDIA_TYPE_1000M_FULL) {
3236 		ecmd->advertising |= ADVERTISED_Autoneg;
3237 		if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
3238 			ecmd->advertising |= ADVERTISED_Autoneg;
3239 			ecmd->advertising |=
3240 			    (ADVERTISED_10baseT_Half |
3241 			     ADVERTISED_10baseT_Full |
3242 			     ADVERTISED_100baseT_Half |
3243 			     ADVERTISED_100baseT_Full |
3244 			     ADVERTISED_1000baseT_Full);
3245 		} else
3246 			ecmd->advertising |= (ADVERTISED_1000baseT_Full);
3247 	}
3248 	ecmd->port = PORT_TP;
3249 	ecmd->phy_address = 0;
3250 	ecmd->transceiver = XCVR_INTERNAL;
3251 
3252 	if (netif_carrier_ok(adapter->netdev)) {
3253 		u16 link_speed, link_duplex;
3254 		atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
3255 		ethtool_cmd_speed_set(ecmd, link_speed);
3256 		if (link_duplex == FULL_DUPLEX)
3257 			ecmd->duplex = DUPLEX_FULL;
3258 		else
3259 			ecmd->duplex = DUPLEX_HALF;
3260 	} else {
3261 		ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3262 		ecmd->duplex = DUPLEX_UNKNOWN;
3263 	}
3264 	if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3265 	    hw->media_type == MEDIA_TYPE_1000M_FULL)
3266 		ecmd->autoneg = AUTONEG_ENABLE;
3267 	else
3268 		ecmd->autoneg = AUTONEG_DISABLE;
3269 
3270 	return 0;
3271 }
3272 
3273 static int atl1_set_settings(struct net_device *netdev,
3274 	struct ethtool_cmd *ecmd)
3275 {
3276 	struct atl1_adapter *adapter = netdev_priv(netdev);
3277 	struct atl1_hw *hw = &adapter->hw;
3278 	u16 phy_data;
3279 	int ret_val = 0;
3280 	u16 old_media_type = hw->media_type;
3281 
3282 	if (netif_running(adapter->netdev)) {
3283 		if (netif_msg_link(adapter))
3284 			dev_dbg(&adapter->pdev->dev,
3285 				"ethtool shutting down adapter\n");
3286 		atl1_down(adapter);
3287 	}
3288 
3289 	if (ecmd->autoneg == AUTONEG_ENABLE)
3290 		hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
3291 	else {
3292 		u32 speed = ethtool_cmd_speed(ecmd);
3293 		if (speed == SPEED_1000) {
3294 			if (ecmd->duplex != DUPLEX_FULL) {
3295 				if (netif_msg_link(adapter))
3296 					dev_warn(&adapter->pdev->dev,
3297 						"1000M half is invalid\n");
3298 				ret_val = -EINVAL;
3299 				goto exit_sset;
3300 			}
3301 			hw->media_type = MEDIA_TYPE_1000M_FULL;
3302 		} else if (speed == SPEED_100) {
3303 			if (ecmd->duplex == DUPLEX_FULL)
3304 				hw->media_type = MEDIA_TYPE_100M_FULL;
3305 			else
3306 				hw->media_type = MEDIA_TYPE_100M_HALF;
3307 		} else {
3308 			if (ecmd->duplex == DUPLEX_FULL)
3309 				hw->media_type = MEDIA_TYPE_10M_FULL;
3310 			else
3311 				hw->media_type = MEDIA_TYPE_10M_HALF;
3312 		}
3313 	}
3314 	switch (hw->media_type) {
3315 	case MEDIA_TYPE_AUTO_SENSOR:
3316 		ecmd->advertising =
3317 		    ADVERTISED_10baseT_Half |
3318 		    ADVERTISED_10baseT_Full |
3319 		    ADVERTISED_100baseT_Half |
3320 		    ADVERTISED_100baseT_Full |
3321 		    ADVERTISED_1000baseT_Full |
3322 		    ADVERTISED_Autoneg | ADVERTISED_TP;
3323 		break;
3324 	case MEDIA_TYPE_1000M_FULL:
3325 		ecmd->advertising =
3326 		    ADVERTISED_1000baseT_Full |
3327 		    ADVERTISED_Autoneg | ADVERTISED_TP;
3328 		break;
3329 	default:
3330 		ecmd->advertising = 0;
3331 		break;
3332 	}
3333 	if (atl1_phy_setup_autoneg_adv(hw)) {
3334 		ret_val = -EINVAL;
3335 		if (netif_msg_link(adapter))
3336 			dev_warn(&adapter->pdev->dev,
3337 				"invalid ethtool speed/duplex setting\n");
3338 		goto exit_sset;
3339 	}
3340 	if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3341 	    hw->media_type == MEDIA_TYPE_1000M_FULL)
3342 		phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3343 	else {
3344 		switch (hw->media_type) {
3345 		case MEDIA_TYPE_100M_FULL:
3346 			phy_data =
3347 			    MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3348 			    MII_CR_RESET;
3349 			break;
3350 		case MEDIA_TYPE_100M_HALF:
3351 			phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3352 			break;
3353 		case MEDIA_TYPE_10M_FULL:
3354 			phy_data =
3355 			    MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3356 			break;
3357 		default:
3358 			/* MEDIA_TYPE_10M_HALF: */
3359 			phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3360 			break;
3361 		}
3362 	}
3363 	atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3364 exit_sset:
3365 	if (ret_val)
3366 		hw->media_type = old_media_type;
3367 
3368 	if (netif_running(adapter->netdev)) {
3369 		if (netif_msg_link(adapter))
3370 			dev_dbg(&adapter->pdev->dev,
3371 				"ethtool starting adapter\n");
3372 		atl1_up(adapter);
3373 	} else if (!ret_val) {
3374 		if (netif_msg_link(adapter))
3375 			dev_dbg(&adapter->pdev->dev,
3376 				"ethtool resetting adapter\n");
3377 		atl1_reset(adapter);
3378 	}
3379 	return ret_val;
3380 }
3381 
3382 static void atl1_get_drvinfo(struct net_device *netdev,
3383 	struct ethtool_drvinfo *drvinfo)
3384 {
3385 	struct atl1_adapter *adapter = netdev_priv(netdev);
3386 
3387 	strlcpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
3388 	strlcpy(drvinfo->version, ATLX_DRIVER_VERSION,
3389 		sizeof(drvinfo->version));
3390 	strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
3391 		sizeof(drvinfo->bus_info));
3392 	drvinfo->eedump_len = ATL1_EEDUMP_LEN;
3393 }
3394 
3395 static void atl1_get_wol(struct net_device *netdev,
3396 	struct ethtool_wolinfo *wol)
3397 {
3398 	struct atl1_adapter *adapter = netdev_priv(netdev);
3399 
3400 	wol->supported = WAKE_MAGIC;
3401 	wol->wolopts = 0;
3402 	if (adapter->wol & ATLX_WUFC_MAG)
3403 		wol->wolopts |= WAKE_MAGIC;
3404 }
3405 
3406 static int atl1_set_wol(struct net_device *netdev,
3407 	struct ethtool_wolinfo *wol)
3408 {
3409 	struct atl1_adapter *adapter = netdev_priv(netdev);
3410 
3411 	if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
3412 		WAKE_ARP | WAKE_MAGICSECURE))
3413 		return -EOPNOTSUPP;
3414 	adapter->wol = 0;
3415 	if (wol->wolopts & WAKE_MAGIC)
3416 		adapter->wol |= ATLX_WUFC_MAG;
3417 
3418 	device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
3419 
3420 	return 0;
3421 }
3422 
3423 static u32 atl1_get_msglevel(struct net_device *netdev)
3424 {
3425 	struct atl1_adapter *adapter = netdev_priv(netdev);
3426 	return adapter->msg_enable;
3427 }
3428 
3429 static void atl1_set_msglevel(struct net_device *netdev, u32 value)
3430 {
3431 	struct atl1_adapter *adapter = netdev_priv(netdev);
3432 	adapter->msg_enable = value;
3433 }
3434 
3435 static int atl1_get_regs_len(struct net_device *netdev)
3436 {
3437 	return ATL1_REG_COUNT * sizeof(u32);
3438 }
3439 
3440 static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
3441 	void *p)
3442 {
3443 	struct atl1_adapter *adapter = netdev_priv(netdev);
3444 	struct atl1_hw *hw = &adapter->hw;
3445 	unsigned int i;
3446 	u32 *regbuf = p;
3447 
3448 	for (i = 0; i < ATL1_REG_COUNT; i++) {
3449 		/*
3450 		 * This switch statement avoids reserved regions
3451 		 * of register space.
3452 		 */
3453 		switch (i) {
3454 		case 6 ... 9:
3455 		case 14:
3456 		case 29 ... 31:
3457 		case 34 ... 63:
3458 		case 75 ... 127:
3459 		case 136 ... 1023:
3460 		case 1027 ... 1087:
3461 		case 1091 ... 1151:
3462 		case 1194 ... 1195:
3463 		case 1200 ... 1201:
3464 		case 1206 ... 1213:
3465 		case 1216 ... 1279:
3466 		case 1290 ... 1311:
3467 		case 1323 ... 1343:
3468 		case 1358 ... 1359:
3469 		case 1368 ... 1375:
3470 		case 1378 ... 1383:
3471 		case 1388 ... 1391:
3472 		case 1393 ... 1395:
3473 		case 1402 ... 1403:
3474 		case 1410 ... 1471:
3475 		case 1522 ... 1535:
3476 			/* reserved region; don't read it */
3477 			regbuf[i] = 0;
3478 			break;
3479 		default:
3480 			/* unreserved region */
3481 			regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
3482 		}
3483 	}
3484 }
3485 
3486 static void atl1_get_ringparam(struct net_device *netdev,
3487 	struct ethtool_ringparam *ring)
3488 {
3489 	struct atl1_adapter *adapter = netdev_priv(netdev);
3490 	struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
3491 	struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
3492 
3493 	ring->rx_max_pending = ATL1_MAX_RFD;
3494 	ring->tx_max_pending = ATL1_MAX_TPD;
3495 	ring->rx_pending = rxdr->count;
3496 	ring->tx_pending = txdr->count;
3497 }
3498 
3499 static int atl1_set_ringparam(struct net_device *netdev,
3500 	struct ethtool_ringparam *ring)
3501 {
3502 	struct atl1_adapter *adapter = netdev_priv(netdev);
3503 	struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
3504 	struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
3505 	struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
3506 
3507 	struct atl1_tpd_ring tpd_old, tpd_new;
3508 	struct atl1_rfd_ring rfd_old, rfd_new;
3509 	struct atl1_rrd_ring rrd_old, rrd_new;
3510 	struct atl1_ring_header rhdr_old, rhdr_new;
3511 	struct atl1_smb smb;
3512 	struct atl1_cmb cmb;
3513 	int err;
3514 
3515 	tpd_old = adapter->tpd_ring;
3516 	rfd_old = adapter->rfd_ring;
3517 	rrd_old = adapter->rrd_ring;
3518 	rhdr_old = adapter->ring_header;
3519 
3520 	if (netif_running(adapter->netdev))
3521 		atl1_down(adapter);
3522 
3523 	rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
3524 	rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
3525 			rfdr->count;
3526 	rfdr->count = (rfdr->count + 3) & ~3;
3527 	rrdr->count = rfdr->count;
3528 
3529 	tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
3530 	tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
3531 			tpdr->count;
3532 	tpdr->count = (tpdr->count + 3) & ~3;
3533 
3534 	if (netif_running(adapter->netdev)) {
3535 		/* try to get new resources before deleting old */
3536 		err = atl1_setup_ring_resources(adapter);
3537 		if (err)
3538 			goto err_setup_ring;
3539 
3540 		/*
3541 		 * save the new, restore the old in order to free it,
3542 		 * then restore the new back again
3543 		 */
3544 
3545 		rfd_new = adapter->rfd_ring;
3546 		rrd_new = adapter->rrd_ring;
3547 		tpd_new = adapter->tpd_ring;
3548 		rhdr_new = adapter->ring_header;
3549 		adapter->rfd_ring = rfd_old;
3550 		adapter->rrd_ring = rrd_old;
3551 		adapter->tpd_ring = tpd_old;
3552 		adapter->ring_header = rhdr_old;
3553 		/*
3554 		 * Save SMB and CMB, since atl1_free_ring_resources
3555 		 * will clear them.
3556 		 */
3557 		smb = adapter->smb;
3558 		cmb = adapter->cmb;
3559 		atl1_free_ring_resources(adapter);
3560 		adapter->rfd_ring = rfd_new;
3561 		adapter->rrd_ring = rrd_new;
3562 		adapter->tpd_ring = tpd_new;
3563 		adapter->ring_header = rhdr_new;
3564 		adapter->smb = smb;
3565 		adapter->cmb = cmb;
3566 
3567 		err = atl1_up(adapter);
3568 		if (err)
3569 			return err;
3570 	}
3571 	return 0;
3572 
3573 err_setup_ring:
3574 	adapter->rfd_ring = rfd_old;
3575 	adapter->rrd_ring = rrd_old;
3576 	adapter->tpd_ring = tpd_old;
3577 	adapter->ring_header = rhdr_old;
3578 	atl1_up(adapter);
3579 	return err;
3580 }
3581 
3582 static void atl1_get_pauseparam(struct net_device *netdev,
3583 	struct ethtool_pauseparam *epause)
3584 {
3585 	struct atl1_adapter *adapter = netdev_priv(netdev);
3586 	struct atl1_hw *hw = &adapter->hw;
3587 
3588 	if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3589 	    hw->media_type == MEDIA_TYPE_1000M_FULL) {
3590 		epause->autoneg = AUTONEG_ENABLE;
3591 	} else {
3592 		epause->autoneg = AUTONEG_DISABLE;
3593 	}
3594 	epause->rx_pause = 1;
3595 	epause->tx_pause = 1;
3596 }
3597 
3598 static int atl1_set_pauseparam(struct net_device *netdev,
3599 	struct ethtool_pauseparam *epause)
3600 {
3601 	struct atl1_adapter *adapter = netdev_priv(netdev);
3602 	struct atl1_hw *hw = &adapter->hw;
3603 
3604 	if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3605 	    hw->media_type == MEDIA_TYPE_1000M_FULL) {
3606 		epause->autoneg = AUTONEG_ENABLE;
3607 	} else {
3608 		epause->autoneg = AUTONEG_DISABLE;
3609 	}
3610 
3611 	epause->rx_pause = 1;
3612 	epause->tx_pause = 1;
3613 
3614 	return 0;
3615 }
3616 
3617 static void atl1_get_strings(struct net_device *netdev, u32 stringset,
3618 	u8 *data)
3619 {
3620 	u8 *p = data;
3621 	int i;
3622 
3623 	switch (stringset) {
3624 	case ETH_SS_STATS:
3625 		for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3626 			memcpy(p, atl1_gstrings_stats[i].stat_string,
3627 				ETH_GSTRING_LEN);
3628 			p += ETH_GSTRING_LEN;
3629 		}
3630 		break;
3631 	}
3632 }
3633 
3634 static int atl1_nway_reset(struct net_device *netdev)
3635 {
3636 	struct atl1_adapter *adapter = netdev_priv(netdev);
3637 	struct atl1_hw *hw = &adapter->hw;
3638 
3639 	if (netif_running(netdev)) {
3640 		u16 phy_data;
3641 		atl1_down(adapter);
3642 
3643 		if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3644 			hw->media_type == MEDIA_TYPE_1000M_FULL) {
3645 			phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3646 		} else {
3647 			switch (hw->media_type) {
3648 			case MEDIA_TYPE_100M_FULL:
3649 				phy_data = MII_CR_FULL_DUPLEX |
3650 					MII_CR_SPEED_100 | MII_CR_RESET;
3651 				break;
3652 			case MEDIA_TYPE_100M_HALF:
3653 				phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3654 				break;
3655 			case MEDIA_TYPE_10M_FULL:
3656 				phy_data = MII_CR_FULL_DUPLEX |
3657 					MII_CR_SPEED_10 | MII_CR_RESET;
3658 				break;
3659 			default:
3660 				/* MEDIA_TYPE_10M_HALF */
3661 				phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3662 			}
3663 		}
3664 		atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3665 		atl1_up(adapter);
3666 	}
3667 	return 0;
3668 }
3669 
3670 static const struct ethtool_ops atl1_ethtool_ops = {
3671 	.get_settings		= atl1_get_settings,
3672 	.set_settings		= atl1_set_settings,
3673 	.get_drvinfo		= atl1_get_drvinfo,
3674 	.get_wol		= atl1_get_wol,
3675 	.set_wol		= atl1_set_wol,
3676 	.get_msglevel		= atl1_get_msglevel,
3677 	.set_msglevel		= atl1_set_msglevel,
3678 	.get_regs_len		= atl1_get_regs_len,
3679 	.get_regs		= atl1_get_regs,
3680 	.get_ringparam		= atl1_get_ringparam,
3681 	.set_ringparam		= atl1_set_ringparam,
3682 	.get_pauseparam		= atl1_get_pauseparam,
3683 	.set_pauseparam		= atl1_set_pauseparam,
3684 	.get_link		= ethtool_op_get_link,
3685 	.get_strings		= atl1_get_strings,
3686 	.nway_reset		= atl1_nway_reset,
3687 	.get_ethtool_stats	= atl1_get_ethtool_stats,
3688 	.get_sset_count		= atl1_get_sset_count,
3689 };
3690 
3691 module_pci_driver(atl1_driver);
3692