1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. 4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com> 5 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com> 6 * 7 * Derived from Intel e1000 driver 8 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 9 * 10 * Contact Information: 11 * Xiong Huang <xiong.huang@atheros.com> 12 * Jie Yang <jie.yang@atheros.com> 13 * Chris Snook <csnook@redhat.com> 14 * Jay Cliburn <jcliburn@gmail.com> 15 * 16 * This version is adapted from the Attansic reference driver. 17 * 18 * TODO: 19 * Add more ethtool functions. 20 * Fix abstruse irq enable/disable condition described here: 21 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2 22 * 23 * NEEDS TESTING: 24 * VLAN 25 * multicast 26 * promiscuous mode 27 * interrupt coalescing 28 * SMP torture testing 29 */ 30 31 #include <linux/atomic.h> 32 #include <asm/byteorder.h> 33 34 #include <linux/compiler.h> 35 #include <linux/crc32.h> 36 #include <linux/delay.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/etherdevice.h> 39 #include <linux/hardirq.h> 40 #include <linux/if_ether.h> 41 #include <linux/if_vlan.h> 42 #include <linux/in.h> 43 #include <linux/interrupt.h> 44 #include <linux/ip.h> 45 #include <linux/irqflags.h> 46 #include <linux/irqreturn.h> 47 #include <linux/jiffies.h> 48 #include <linux/mii.h> 49 #include <linux/module.h> 50 #include <linux/net.h> 51 #include <linux/netdevice.h> 52 #include <linux/pci.h> 53 #include <linux/pci_ids.h> 54 #include <linux/pm.h> 55 #include <linux/skbuff.h> 56 #include <linux/slab.h> 57 #include <linux/spinlock.h> 58 #include <linux/string.h> 59 #include <linux/tcp.h> 60 #include <linux/timer.h> 61 #include <linux/types.h> 62 #include <linux/workqueue.h> 63 64 #include <net/checksum.h> 65 66 #include "atl1.h" 67 68 #define ATLX_DRIVER_VERSION "2.1.3" 69 MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, " 70 "Chris Snook <csnook@redhat.com>, " 71 "Jay Cliburn <jcliburn@gmail.com>"); 72 MODULE_LICENSE("GPL"); 73 MODULE_VERSION(ATLX_DRIVER_VERSION); 74 75 /* Temporary hack for merging atl1 and atl2 */ 76 #include "atlx.c" 77 78 static const struct ethtool_ops atl1_ethtool_ops; 79 80 /* 81 * This is the only thing that needs to be changed to adjust the 82 * maximum number of ports that the driver can manage. 83 */ 84 #define ATL1_MAX_NIC 4 85 86 #define OPTION_UNSET -1 87 #define OPTION_DISABLED 0 88 #define OPTION_ENABLED 1 89 90 #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET } 91 92 /* 93 * Interrupt Moderate Timer in units of 2 us 94 * 95 * Valid Range: 10-65535 96 * 97 * Default Value: 100 (200us) 98 */ 99 static int int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT; 100 static unsigned int num_int_mod_timer; 101 module_param_array_named(int_mod_timer, int_mod_timer, int, 102 &num_int_mod_timer, 0); 103 MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer"); 104 105 #define DEFAULT_INT_MOD_CNT 100 /* 200us */ 106 #define MAX_INT_MOD_CNT 65000 107 #define MIN_INT_MOD_CNT 50 108 109 struct atl1_option { 110 enum { enable_option, range_option, list_option } type; 111 char *name; 112 char *err; 113 int def; 114 union { 115 struct { /* range_option info */ 116 int min; 117 int max; 118 } r; 119 struct { /* list_option info */ 120 int nr; 121 struct atl1_opt_list { 122 int i; 123 char *str; 124 } *p; 125 } l; 126 } arg; 127 }; 128 129 static int atl1_validate_option(int *value, struct atl1_option *opt, 130 struct pci_dev *pdev) 131 { 132 if (*value == OPTION_UNSET) { 133 *value = opt->def; 134 return 0; 135 } 136 137 switch (opt->type) { 138 case enable_option: 139 switch (*value) { 140 case OPTION_ENABLED: 141 dev_info(&pdev->dev, "%s enabled\n", opt->name); 142 return 0; 143 case OPTION_DISABLED: 144 dev_info(&pdev->dev, "%s disabled\n", opt->name); 145 return 0; 146 } 147 break; 148 case range_option: 149 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 150 dev_info(&pdev->dev, "%s set to %i\n", opt->name, 151 *value); 152 return 0; 153 } 154 break; 155 case list_option:{ 156 int i; 157 struct atl1_opt_list *ent; 158 159 for (i = 0; i < opt->arg.l.nr; i++) { 160 ent = &opt->arg.l.p[i]; 161 if (*value == ent->i) { 162 if (ent->str[0] != '\0') 163 dev_info(&pdev->dev, "%s\n", 164 ent->str); 165 return 0; 166 } 167 } 168 } 169 break; 170 171 default: 172 break; 173 } 174 175 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n", 176 opt->name, *value, opt->err); 177 *value = opt->def; 178 return -1; 179 } 180 181 /** 182 * atl1_check_options - Range Checking for Command Line Parameters 183 * @adapter: board private structure 184 * 185 * This routine checks all command line parameters for valid user 186 * input. If an invalid value is given, or if no user specified 187 * value exists, a default value is used. The final value is stored 188 * in a variable in the adapter structure. 189 */ 190 static void atl1_check_options(struct atl1_adapter *adapter) 191 { 192 struct pci_dev *pdev = adapter->pdev; 193 int bd = adapter->bd_number; 194 if (bd >= ATL1_MAX_NIC) { 195 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd); 196 dev_notice(&pdev->dev, "using defaults for all values\n"); 197 } 198 { /* Interrupt Moderate Timer */ 199 struct atl1_option opt = { 200 .type = range_option, 201 .name = "Interrupt Moderator Timer", 202 .err = "using default of " 203 __MODULE_STRING(DEFAULT_INT_MOD_CNT), 204 .def = DEFAULT_INT_MOD_CNT, 205 .arg = {.r = {.min = MIN_INT_MOD_CNT, 206 .max = MAX_INT_MOD_CNT} } 207 }; 208 int val; 209 if (num_int_mod_timer > bd) { 210 val = int_mod_timer[bd]; 211 atl1_validate_option(&val, &opt, pdev); 212 adapter->imt = (u16) val; 213 } else 214 adapter->imt = (u16) (opt.def); 215 } 216 } 217 218 /* 219 * atl1_pci_tbl - PCI Device ID Table 220 */ 221 static const struct pci_device_id atl1_pci_tbl[] = { 222 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)}, 223 /* required last entry */ 224 {0,} 225 }; 226 MODULE_DEVICE_TABLE(pci, atl1_pci_tbl); 227 228 static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | 229 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP; 230 231 static int debug = -1; 232 module_param(debug, int, 0); 233 MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)"); 234 235 /* 236 * Reset the transmit and receive units; mask and clear all interrupts. 237 * hw - Struct containing variables accessed by shared code 238 * return : 0 or idle status (if error) 239 */ 240 static s32 atl1_reset_hw(struct atl1_hw *hw) 241 { 242 struct pci_dev *pdev = hw->back->pdev; 243 struct atl1_adapter *adapter = hw->back; 244 u32 icr; 245 int i; 246 247 /* 248 * Clear Interrupt mask to stop board from generating 249 * interrupts & Clear any pending interrupt events 250 */ 251 /* 252 * atlx_irq_disable(adapter); 253 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR); 254 */ 255 256 /* 257 * Issue Soft Reset to the MAC. This will reset the chip's 258 * transmit, receive, DMA. It will not effect 259 * the current PCI configuration. The global reset bit is self- 260 * clearing, and should clear within a microsecond. 261 */ 262 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL); 263 ioread32(hw->hw_addr + REG_MASTER_CTRL); 264 265 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE); 266 ioread16(hw->hw_addr + REG_PHY_ENABLE); 267 268 /* delay about 1ms */ 269 msleep(1); 270 271 /* Wait at least 10ms for All module to be Idle */ 272 for (i = 0; i < 10; i++) { 273 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS); 274 if (!icr) 275 break; 276 /* delay 1 ms */ 277 msleep(1); 278 /* FIXME: still the right way to do this? */ 279 cpu_relax(); 280 } 281 282 if (icr) { 283 if (netif_msg_hw(adapter)) 284 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr); 285 return icr; 286 } 287 288 return 0; 289 } 290 291 /* function about EEPROM 292 * 293 * check_eeprom_exist 294 * return 0 if eeprom exist 295 */ 296 static int atl1_check_eeprom_exist(struct atl1_hw *hw) 297 { 298 u32 value; 299 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); 300 if (value & SPI_FLASH_CTRL_EN_VPD) { 301 value &= ~SPI_FLASH_CTRL_EN_VPD; 302 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); 303 } 304 305 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST); 306 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 307 } 308 309 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value) 310 { 311 int i; 312 u32 control; 313 314 if (offset & 3) 315 /* address do not align */ 316 return false; 317 318 iowrite32(0, hw->hw_addr + REG_VPD_DATA); 319 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 320 iowrite32(control, hw->hw_addr + REG_VPD_CAP); 321 ioread32(hw->hw_addr + REG_VPD_CAP); 322 323 for (i = 0; i < 10; i++) { 324 msleep(2); 325 control = ioread32(hw->hw_addr + REG_VPD_CAP); 326 if (control & VPD_CAP_VPD_FLAG) 327 break; 328 } 329 if (control & VPD_CAP_VPD_FLAG) { 330 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA); 331 return true; 332 } 333 /* timeout */ 334 return false; 335 } 336 337 /* 338 * Reads the value from a PHY register 339 * hw - Struct containing variables accessed by shared code 340 * reg_addr - address of the PHY register to read 341 */ 342 static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data) 343 { 344 u32 val; 345 int i; 346 347 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 348 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 << 349 MDIO_CLK_SEL_SHIFT; 350 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); 351 ioread32(hw->hw_addr + REG_MDIO_CTRL); 352 353 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 354 udelay(2); 355 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); 356 if (!(val & (MDIO_START | MDIO_BUSY))) 357 break; 358 } 359 if (!(val & (MDIO_START | MDIO_BUSY))) { 360 *phy_data = (u16) val; 361 return 0; 362 } 363 return ATLX_ERR_PHY; 364 } 365 366 #define CUSTOM_SPI_CS_SETUP 2 367 #define CUSTOM_SPI_CLK_HI 2 368 #define CUSTOM_SPI_CLK_LO 2 369 #define CUSTOM_SPI_CS_HOLD 2 370 #define CUSTOM_SPI_CS_HI 3 371 372 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf) 373 { 374 int i; 375 u32 value; 376 377 iowrite32(0, hw->hw_addr + REG_SPI_DATA); 378 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR); 379 380 value = SPI_FLASH_CTRL_WAIT_READY | 381 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << 382 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI & 383 SPI_FLASH_CTRL_CLK_HI_MASK) << 384 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO & 385 SPI_FLASH_CTRL_CLK_LO_MASK) << 386 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD & 387 SPI_FLASH_CTRL_CS_HOLD_MASK) << 388 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI & 389 SPI_FLASH_CTRL_CS_HI_MASK) << 390 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) << 391 SPI_FLASH_CTRL_INS_SHIFT; 392 393 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); 394 395 value |= SPI_FLASH_CTRL_START; 396 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); 397 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); 398 399 for (i = 0; i < 10; i++) { 400 msleep(1); 401 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); 402 if (!(value & SPI_FLASH_CTRL_START)) 403 break; 404 } 405 406 if (value & SPI_FLASH_CTRL_START) 407 return false; 408 409 *buf = ioread32(hw->hw_addr + REG_SPI_DATA); 410 411 return true; 412 } 413 414 /* 415 * get_permanent_address 416 * return 0 if get valid mac address, 417 */ 418 static int atl1_get_permanent_address(struct atl1_hw *hw) 419 { 420 u32 addr[2]; 421 u32 i, control; 422 u16 reg; 423 u8 eth_addr[ETH_ALEN]; 424 bool key_valid; 425 426 if (is_valid_ether_addr(hw->perm_mac_addr)) 427 return 0; 428 429 /* init */ 430 addr[0] = addr[1] = 0; 431 432 if (!atl1_check_eeprom_exist(hw)) { 433 reg = 0; 434 key_valid = false; 435 /* Read out all EEPROM content */ 436 i = 0; 437 while (1) { 438 if (atl1_read_eeprom(hw, i + 0x100, &control)) { 439 if (key_valid) { 440 if (reg == REG_MAC_STA_ADDR) 441 addr[0] = control; 442 else if (reg == (REG_MAC_STA_ADDR + 4)) 443 addr[1] = control; 444 key_valid = false; 445 } else if ((control & 0xff) == 0x5A) { 446 key_valid = true; 447 reg = (u16) (control >> 16); 448 } else 449 break; 450 } else 451 /* read error */ 452 break; 453 i += 4; 454 } 455 456 *(u32 *) ð_addr[2] = swab32(addr[0]); 457 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); 458 if (is_valid_ether_addr(eth_addr)) { 459 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 460 return 0; 461 } 462 } 463 464 /* see if SPI FLAGS exist ? */ 465 addr[0] = addr[1] = 0; 466 reg = 0; 467 key_valid = false; 468 i = 0; 469 while (1) { 470 if (atl1_spi_read(hw, i + 0x1f000, &control)) { 471 if (key_valid) { 472 if (reg == REG_MAC_STA_ADDR) 473 addr[0] = control; 474 else if (reg == (REG_MAC_STA_ADDR + 4)) 475 addr[1] = control; 476 key_valid = false; 477 } else if ((control & 0xff) == 0x5A) { 478 key_valid = true; 479 reg = (u16) (control >> 16); 480 } else 481 /* data end */ 482 break; 483 } else 484 /* read error */ 485 break; 486 i += 4; 487 } 488 489 *(u32 *) ð_addr[2] = swab32(addr[0]); 490 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); 491 if (is_valid_ether_addr(eth_addr)) { 492 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 493 return 0; 494 } 495 496 /* 497 * On some motherboards, the MAC address is written by the 498 * BIOS directly to the MAC register during POST, and is 499 * not stored in eeprom. If all else thus far has failed 500 * to fetch the permanent MAC address, try reading it directly. 501 */ 502 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR); 503 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4)); 504 *(u32 *) ð_addr[2] = swab32(addr[0]); 505 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); 506 if (is_valid_ether_addr(eth_addr)) { 507 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 508 return 0; 509 } 510 511 return 1; 512 } 513 514 /* 515 * Reads the adapter's MAC address from the EEPROM 516 * hw - Struct containing variables accessed by shared code 517 */ 518 static s32 atl1_read_mac_addr(struct atl1_hw *hw) 519 { 520 s32 ret = 0; 521 u16 i; 522 523 if (atl1_get_permanent_address(hw)) { 524 eth_random_addr(hw->perm_mac_addr); 525 ret = 1; 526 } 527 528 for (i = 0; i < ETH_ALEN; i++) 529 hw->mac_addr[i] = hw->perm_mac_addr[i]; 530 return ret; 531 } 532 533 /* 534 * Hashes an address to determine its location in the multicast table 535 * hw - Struct containing variables accessed by shared code 536 * mc_addr - the multicast address to hash 537 * 538 * atl1_hash_mc_addr 539 * purpose 540 * set hash value for a multicast address 541 * hash calcu processing : 542 * 1. calcu 32bit CRC for multicast address 543 * 2. reverse crc with MSB to LSB 544 */ 545 static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr) 546 { 547 u32 crc32, value = 0; 548 int i; 549 550 crc32 = ether_crc_le(6, mc_addr); 551 for (i = 0; i < 32; i++) 552 value |= (((crc32 >> i) & 1) << (31 - i)); 553 554 return value; 555 } 556 557 /* 558 * Sets the bit in the multicast table corresponding to the hash value. 559 * hw - Struct containing variables accessed by shared code 560 * hash_value - Multicast address hash value 561 */ 562 static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value) 563 { 564 u32 hash_bit, hash_reg; 565 u32 mta; 566 567 /* 568 * The HASH Table is a register array of 2 32-bit registers. 569 * It is treated like an array of 64 bits. We want to set 570 * bit BitArray[hash_value]. So we figure out what register 571 * the bit is in, read it, OR in the new bit, then write 572 * back the new value. The register is determined by the 573 * upper 7 bits of the hash value and the bit within that 574 * register are determined by the lower 5 bits of the value. 575 */ 576 hash_reg = (hash_value >> 31) & 0x1; 577 hash_bit = (hash_value >> 26) & 0x1F; 578 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); 579 mta |= (1 << hash_bit); 580 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); 581 } 582 583 /* 584 * Writes a value to a PHY register 585 * hw - Struct containing variables accessed by shared code 586 * reg_addr - address of the PHY register to write 587 * data - data to write to the PHY 588 */ 589 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data) 590 { 591 int i; 592 u32 val; 593 594 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 595 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 596 MDIO_SUP_PREAMBLE | 597 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 598 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); 599 ioread32(hw->hw_addr + REG_MDIO_CTRL); 600 601 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 602 udelay(2); 603 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); 604 if (!(val & (MDIO_START | MDIO_BUSY))) 605 break; 606 } 607 608 if (!(val & (MDIO_START | MDIO_BUSY))) 609 return 0; 610 611 return ATLX_ERR_PHY; 612 } 613 614 /* 615 * Make L001's PHY out of Power Saving State (bug) 616 * hw - Struct containing variables accessed by shared code 617 * when power on, L001's PHY always on Power saving State 618 * (Gigabit Link forbidden) 619 */ 620 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw) 621 { 622 s32 ret; 623 ret = atl1_write_phy_reg(hw, 29, 0x0029); 624 if (ret) 625 return ret; 626 return atl1_write_phy_reg(hw, 30, 0); 627 } 628 629 /* 630 * Resets the PHY and make all config validate 631 * hw - Struct containing variables accessed by shared code 632 * 633 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) 634 */ 635 static s32 atl1_phy_reset(struct atl1_hw *hw) 636 { 637 struct pci_dev *pdev = hw->back->pdev; 638 struct atl1_adapter *adapter = hw->back; 639 s32 ret_val; 640 u16 phy_data; 641 642 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 643 hw->media_type == MEDIA_TYPE_1000M_FULL) 644 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 645 else { 646 switch (hw->media_type) { 647 case MEDIA_TYPE_100M_FULL: 648 phy_data = 649 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | 650 MII_CR_RESET; 651 break; 652 case MEDIA_TYPE_100M_HALF: 653 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 654 break; 655 case MEDIA_TYPE_10M_FULL: 656 phy_data = 657 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 658 break; 659 default: 660 /* MEDIA_TYPE_10M_HALF: */ 661 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 662 break; 663 } 664 } 665 666 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data); 667 if (ret_val) { 668 u32 val; 669 int i; 670 /* pcie serdes link may be down! */ 671 if (netif_msg_hw(adapter)) 672 dev_dbg(&pdev->dev, "pcie phy link down\n"); 673 674 for (i = 0; i < 25; i++) { 675 msleep(1); 676 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); 677 if (!(val & (MDIO_START | MDIO_BUSY))) 678 break; 679 } 680 681 if ((val & (MDIO_START | MDIO_BUSY)) != 0) { 682 if (netif_msg_hw(adapter)) 683 dev_warn(&pdev->dev, 684 "pcie link down at least 25ms\n"); 685 return ret_val; 686 } 687 } 688 return 0; 689 } 690 691 /* 692 * Configures PHY autoneg and flow control advertisement settings 693 * hw - Struct containing variables accessed by shared code 694 */ 695 static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw) 696 { 697 s32 ret_val; 698 s16 mii_autoneg_adv_reg; 699 s16 mii_1000t_ctrl_reg; 700 701 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 702 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 703 704 /* Read the MII 1000Base-T Control Register (Address 9). */ 705 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK; 706 707 /* 708 * First we clear all the 10/100 mb speed bits in the Auto-Neg 709 * Advertisement Register (Address 4) and the 1000 mb speed bits in 710 * the 1000Base-T Control Register (Address 9). 711 */ 712 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 713 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK; 714 715 /* 716 * Need to parse media_type and set up 717 * the appropriate PHY registers. 718 */ 719 switch (hw->media_type) { 720 case MEDIA_TYPE_AUTO_SENSOR: 721 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS | 722 MII_AR_10T_FD_CAPS | 723 MII_AR_100TX_HD_CAPS | 724 MII_AR_100TX_FD_CAPS); 725 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS; 726 break; 727 728 case MEDIA_TYPE_1000M_FULL: 729 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS; 730 break; 731 732 case MEDIA_TYPE_100M_FULL: 733 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 734 break; 735 736 case MEDIA_TYPE_100M_HALF: 737 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 738 break; 739 740 case MEDIA_TYPE_10M_FULL: 741 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 742 break; 743 744 default: 745 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 746 break; 747 } 748 749 /* flow control fixed to enable all */ 750 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 751 752 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 753 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; 754 755 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 756 if (ret_val) 757 return ret_val; 758 759 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg); 760 if (ret_val) 761 return ret_val; 762 763 return 0; 764 } 765 766 /* 767 * Configures link settings. 768 * hw - Struct containing variables accessed by shared code 769 * Assumes the hardware has previously been reset and the 770 * transmitter and receiver are not enabled. 771 */ 772 static s32 atl1_setup_link(struct atl1_hw *hw) 773 { 774 struct pci_dev *pdev = hw->back->pdev; 775 struct atl1_adapter *adapter = hw->back; 776 s32 ret_val; 777 778 /* 779 * Options: 780 * PHY will advertise value(s) parsed from 781 * autoneg_advertised and fc 782 * no matter what autoneg is , We will not wait link result. 783 */ 784 ret_val = atl1_phy_setup_autoneg_adv(hw); 785 if (ret_val) { 786 if (netif_msg_link(adapter)) 787 dev_dbg(&pdev->dev, 788 "error setting up autonegotiation\n"); 789 return ret_val; 790 } 791 /* SW.Reset , En-Auto-Neg if needed */ 792 ret_val = atl1_phy_reset(hw); 793 if (ret_val) { 794 if (netif_msg_link(adapter)) 795 dev_dbg(&pdev->dev, "error resetting phy\n"); 796 return ret_val; 797 } 798 hw->phy_configured = true; 799 return ret_val; 800 } 801 802 static void atl1_init_flash_opcode(struct atl1_hw *hw) 803 { 804 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) 805 /* Atmel */ 806 hw->flash_vendor = 0; 807 808 /* Init OP table */ 809 iowrite8(flash_table[hw->flash_vendor].cmd_program, 810 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM); 811 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase, 812 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE); 813 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase, 814 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE); 815 iowrite8(flash_table[hw->flash_vendor].cmd_rdid, 816 hw->hw_addr + REG_SPI_FLASH_OP_RDID); 817 iowrite8(flash_table[hw->flash_vendor].cmd_wren, 818 hw->hw_addr + REG_SPI_FLASH_OP_WREN); 819 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr, 820 hw->hw_addr + REG_SPI_FLASH_OP_RDSR); 821 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr, 822 hw->hw_addr + REG_SPI_FLASH_OP_WRSR); 823 iowrite8(flash_table[hw->flash_vendor].cmd_read, 824 hw->hw_addr + REG_SPI_FLASH_OP_READ); 825 } 826 827 /* 828 * Performs basic configuration of the adapter. 829 * hw - Struct containing variables accessed by shared code 830 * Assumes that the controller has previously been reset and is in a 831 * post-reset uninitialized state. Initializes multicast table, 832 * and Calls routines to setup link 833 * Leaves the transmit and receive units disabled and uninitialized. 834 */ 835 static s32 atl1_init_hw(struct atl1_hw *hw) 836 { 837 u32 ret_val = 0; 838 839 /* Zero out the Multicast HASH table */ 840 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE); 841 /* clear the old settings from the multicast hash table */ 842 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2)); 843 844 atl1_init_flash_opcode(hw); 845 846 if (!hw->phy_configured) { 847 /* enable GPHY LinkChange Interrupt */ 848 ret_val = atl1_write_phy_reg(hw, 18, 0xC00); 849 if (ret_val) 850 return ret_val; 851 /* make PHY out of power-saving state */ 852 ret_val = atl1_phy_leave_power_saving(hw); 853 if (ret_val) 854 return ret_val; 855 /* Call a subroutine to configure the link */ 856 ret_val = atl1_setup_link(hw); 857 } 858 return ret_val; 859 } 860 861 /* 862 * Detects the current speed and duplex settings of the hardware. 863 * hw - Struct containing variables accessed by shared code 864 * speed - Speed of the connection 865 * duplex - Duplex setting of the connection 866 */ 867 static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex) 868 { 869 struct pci_dev *pdev = hw->back->pdev; 870 struct atl1_adapter *adapter = hw->back; 871 s32 ret_val; 872 u16 phy_data; 873 874 /* ; --- Read PHY Specific Status Register (17) */ 875 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); 876 if (ret_val) 877 return ret_val; 878 879 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) 880 return ATLX_ERR_PHY_RES; 881 882 switch (phy_data & MII_ATLX_PSSR_SPEED) { 883 case MII_ATLX_PSSR_1000MBS: 884 *speed = SPEED_1000; 885 break; 886 case MII_ATLX_PSSR_100MBS: 887 *speed = SPEED_100; 888 break; 889 case MII_ATLX_PSSR_10MBS: 890 *speed = SPEED_10; 891 break; 892 default: 893 if (netif_msg_hw(adapter)) 894 dev_dbg(&pdev->dev, "error getting speed\n"); 895 return ATLX_ERR_PHY_SPEED; 896 } 897 if (phy_data & MII_ATLX_PSSR_DPLX) 898 *duplex = FULL_DUPLEX; 899 else 900 *duplex = HALF_DUPLEX; 901 902 return 0; 903 } 904 905 static void atl1_set_mac_addr(struct atl1_hw *hw) 906 { 907 u32 value; 908 /* 909 * 00-0B-6A-F6-00-DC 910 * 0: 6AF600DC 1: 000B 911 * low dword 912 */ 913 value = (((u32) hw->mac_addr[2]) << 24) | 914 (((u32) hw->mac_addr[3]) << 16) | 915 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5])); 916 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); 917 /* high dword */ 918 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); 919 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2)); 920 } 921 922 /** 923 * atl1_sw_init - Initialize general software structures (struct atl1_adapter) 924 * @adapter: board private structure to initialize 925 * 926 * atl1_sw_init initializes the Adapter private data structure. 927 * Fields are initialized based on PCI device information and 928 * OS network device settings (MTU size). 929 */ 930 static int atl1_sw_init(struct atl1_adapter *adapter) 931 { 932 struct atl1_hw *hw = &adapter->hw; 933 struct net_device *netdev = adapter->netdev; 934 935 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 936 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 937 938 adapter->wol = 0; 939 device_set_wakeup_enable(&adapter->pdev->dev, false); 940 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7; 941 adapter->ict = 50000; /* 100ms */ 942 adapter->link_speed = SPEED_0; /* hardware init */ 943 adapter->link_duplex = FULL_DUPLEX; 944 945 hw->phy_configured = false; 946 hw->preamble_len = 7; 947 hw->ipgt = 0x60; 948 hw->min_ifg = 0x50; 949 hw->ipgr1 = 0x40; 950 hw->ipgr2 = 0x60; 951 hw->max_retry = 0xf; 952 hw->lcol = 0x37; 953 hw->jam_ipg = 7; 954 hw->rfd_burst = 8; 955 hw->rrd_burst = 8; 956 hw->rfd_fetch_gap = 1; 957 hw->rx_jumbo_th = adapter->rx_buffer_len / 8; 958 hw->rx_jumbo_lkah = 1; 959 hw->rrd_ret_timer = 16; 960 hw->tpd_burst = 4; 961 hw->tpd_fetch_th = 16; 962 hw->txf_burst = 0x100; 963 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3; 964 hw->tpd_fetch_gap = 1; 965 hw->rcb_value = atl1_rcb_64; 966 hw->dma_ord = atl1_dma_ord_enh; 967 hw->dmar_block = atl1_dma_req_256; 968 hw->dmaw_block = atl1_dma_req_256; 969 hw->cmb_rrd = 4; 970 hw->cmb_tpd = 4; 971 hw->cmb_rx_timer = 1; /* about 2us */ 972 hw->cmb_tx_timer = 1; /* about 2us */ 973 hw->smb_timer = 100000; /* about 200ms */ 974 975 spin_lock_init(&adapter->lock); 976 spin_lock_init(&adapter->mb_lock); 977 978 return 0; 979 } 980 981 static int mdio_read(struct net_device *netdev, int phy_id, int reg_num) 982 { 983 struct atl1_adapter *adapter = netdev_priv(netdev); 984 u16 result; 985 986 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result); 987 988 return result; 989 } 990 991 static void mdio_write(struct net_device *netdev, int phy_id, int reg_num, 992 int val) 993 { 994 struct atl1_adapter *adapter = netdev_priv(netdev); 995 996 atl1_write_phy_reg(&adapter->hw, reg_num, val); 997 } 998 999 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1000 { 1001 struct atl1_adapter *adapter = netdev_priv(netdev); 1002 unsigned long flags; 1003 int retval; 1004 1005 if (!netif_running(netdev)) 1006 return -EINVAL; 1007 1008 spin_lock_irqsave(&adapter->lock, flags); 1009 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL); 1010 spin_unlock_irqrestore(&adapter->lock, flags); 1011 1012 return retval; 1013 } 1014 1015 /** 1016 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources 1017 * @adapter: board private structure 1018 * 1019 * Return 0 on success, negative on failure 1020 */ 1021 static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter) 1022 { 1023 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1024 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1025 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1026 struct atl1_ring_header *ring_header = &adapter->ring_header; 1027 struct pci_dev *pdev = adapter->pdev; 1028 int size; 1029 u8 offset = 0; 1030 1031 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count); 1032 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL); 1033 if (unlikely(!tpd_ring->buffer_info)) { 1034 if (netif_msg_drv(adapter)) 1035 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n", 1036 size); 1037 goto err_nomem; 1038 } 1039 rfd_ring->buffer_info = 1040 (tpd_ring->buffer_info + tpd_ring->count); 1041 1042 /* 1043 * real ring DMA buffer 1044 * each ring/block may need up to 8 bytes for alignment, hence the 1045 * additional 40 bytes tacked onto the end. 1046 */ 1047 ring_header->size = size = 1048 sizeof(struct tx_packet_desc) * tpd_ring->count 1049 + sizeof(struct rx_free_desc) * rfd_ring->count 1050 + sizeof(struct rx_return_desc) * rrd_ring->count 1051 + sizeof(struct coals_msg_block) 1052 + sizeof(struct stats_msg_block) 1053 + 40; 1054 1055 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size, 1056 &ring_header->dma); 1057 if (unlikely(!ring_header->desc)) { 1058 if (netif_msg_drv(adapter)) 1059 dev_err(&pdev->dev, "pci_alloc_consistent failed\n"); 1060 goto err_nomem; 1061 } 1062 1063 memset(ring_header->desc, 0, ring_header->size); 1064 1065 /* init TPD ring */ 1066 tpd_ring->dma = ring_header->dma; 1067 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0; 1068 tpd_ring->dma += offset; 1069 tpd_ring->desc = (u8 *) ring_header->desc + offset; 1070 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count; 1071 1072 /* init RFD ring */ 1073 rfd_ring->dma = tpd_ring->dma + tpd_ring->size; 1074 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0; 1075 rfd_ring->dma += offset; 1076 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset); 1077 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count; 1078 1079 1080 /* init RRD ring */ 1081 rrd_ring->dma = rfd_ring->dma + rfd_ring->size; 1082 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0; 1083 rrd_ring->dma += offset; 1084 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset); 1085 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count; 1086 1087 1088 /* init CMB */ 1089 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size; 1090 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0; 1091 adapter->cmb.dma += offset; 1092 adapter->cmb.cmb = (struct coals_msg_block *) 1093 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset)); 1094 1095 /* init SMB */ 1096 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block); 1097 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0; 1098 adapter->smb.dma += offset; 1099 adapter->smb.smb = (struct stats_msg_block *) 1100 ((u8 *) adapter->cmb.cmb + 1101 (sizeof(struct coals_msg_block) + offset)); 1102 1103 return 0; 1104 1105 err_nomem: 1106 kfree(tpd_ring->buffer_info); 1107 return -ENOMEM; 1108 } 1109 1110 static void atl1_init_ring_ptrs(struct atl1_adapter *adapter) 1111 { 1112 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1113 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1114 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1115 1116 atomic_set(&tpd_ring->next_to_use, 0); 1117 atomic_set(&tpd_ring->next_to_clean, 0); 1118 1119 rfd_ring->next_to_clean = 0; 1120 atomic_set(&rfd_ring->next_to_use, 0); 1121 1122 rrd_ring->next_to_use = 0; 1123 atomic_set(&rrd_ring->next_to_clean, 0); 1124 } 1125 1126 /** 1127 * atl1_clean_rx_ring - Free RFD Buffers 1128 * @adapter: board private structure 1129 */ 1130 static void atl1_clean_rx_ring(struct atl1_adapter *adapter) 1131 { 1132 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1133 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1134 struct atl1_buffer *buffer_info; 1135 struct pci_dev *pdev = adapter->pdev; 1136 unsigned long size; 1137 unsigned int i; 1138 1139 /* Free all the Rx ring sk_buffs */ 1140 for (i = 0; i < rfd_ring->count; i++) { 1141 buffer_info = &rfd_ring->buffer_info[i]; 1142 if (buffer_info->dma) { 1143 pci_unmap_page(pdev, buffer_info->dma, 1144 buffer_info->length, PCI_DMA_FROMDEVICE); 1145 buffer_info->dma = 0; 1146 } 1147 if (buffer_info->skb) { 1148 dev_kfree_skb(buffer_info->skb); 1149 buffer_info->skb = NULL; 1150 } 1151 } 1152 1153 size = sizeof(struct atl1_buffer) * rfd_ring->count; 1154 memset(rfd_ring->buffer_info, 0, size); 1155 1156 /* Zero out the descriptor ring */ 1157 memset(rfd_ring->desc, 0, rfd_ring->size); 1158 1159 rfd_ring->next_to_clean = 0; 1160 atomic_set(&rfd_ring->next_to_use, 0); 1161 1162 rrd_ring->next_to_use = 0; 1163 atomic_set(&rrd_ring->next_to_clean, 0); 1164 } 1165 1166 /** 1167 * atl1_clean_tx_ring - Free Tx Buffers 1168 * @adapter: board private structure 1169 */ 1170 static void atl1_clean_tx_ring(struct atl1_adapter *adapter) 1171 { 1172 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1173 struct atl1_buffer *buffer_info; 1174 struct pci_dev *pdev = adapter->pdev; 1175 unsigned long size; 1176 unsigned int i; 1177 1178 /* Free all the Tx ring sk_buffs */ 1179 for (i = 0; i < tpd_ring->count; i++) { 1180 buffer_info = &tpd_ring->buffer_info[i]; 1181 if (buffer_info->dma) { 1182 pci_unmap_page(pdev, buffer_info->dma, 1183 buffer_info->length, PCI_DMA_TODEVICE); 1184 buffer_info->dma = 0; 1185 } 1186 } 1187 1188 for (i = 0; i < tpd_ring->count; i++) { 1189 buffer_info = &tpd_ring->buffer_info[i]; 1190 if (buffer_info->skb) { 1191 dev_kfree_skb_any(buffer_info->skb); 1192 buffer_info->skb = NULL; 1193 } 1194 } 1195 1196 size = sizeof(struct atl1_buffer) * tpd_ring->count; 1197 memset(tpd_ring->buffer_info, 0, size); 1198 1199 /* Zero out the descriptor ring */ 1200 memset(tpd_ring->desc, 0, tpd_ring->size); 1201 1202 atomic_set(&tpd_ring->next_to_use, 0); 1203 atomic_set(&tpd_ring->next_to_clean, 0); 1204 } 1205 1206 /** 1207 * atl1_free_ring_resources - Free Tx / RX descriptor Resources 1208 * @adapter: board private structure 1209 * 1210 * Free all transmit software resources 1211 */ 1212 static void atl1_free_ring_resources(struct atl1_adapter *adapter) 1213 { 1214 struct pci_dev *pdev = adapter->pdev; 1215 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1216 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1217 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1218 struct atl1_ring_header *ring_header = &adapter->ring_header; 1219 1220 atl1_clean_tx_ring(adapter); 1221 atl1_clean_rx_ring(adapter); 1222 1223 kfree(tpd_ring->buffer_info); 1224 pci_free_consistent(pdev, ring_header->size, ring_header->desc, 1225 ring_header->dma); 1226 1227 tpd_ring->buffer_info = NULL; 1228 tpd_ring->desc = NULL; 1229 tpd_ring->dma = 0; 1230 1231 rfd_ring->buffer_info = NULL; 1232 rfd_ring->desc = NULL; 1233 rfd_ring->dma = 0; 1234 1235 rrd_ring->desc = NULL; 1236 rrd_ring->dma = 0; 1237 1238 adapter->cmb.dma = 0; 1239 adapter->cmb.cmb = NULL; 1240 1241 adapter->smb.dma = 0; 1242 adapter->smb.smb = NULL; 1243 } 1244 1245 static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter) 1246 { 1247 u32 value; 1248 struct atl1_hw *hw = &adapter->hw; 1249 struct net_device *netdev = adapter->netdev; 1250 /* Config MAC CTRL Register */ 1251 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN; 1252 /* duplex */ 1253 if (FULL_DUPLEX == adapter->link_duplex) 1254 value |= MAC_CTRL_DUPLX; 1255 /* speed */ 1256 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ? 1257 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) << 1258 MAC_CTRL_SPEED_SHIFT); 1259 /* flow control */ 1260 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 1261 /* PAD & CRC */ 1262 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1263 /* preamble length */ 1264 value |= (((u32) adapter->hw.preamble_len 1265 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 1266 /* vlan */ 1267 __atlx_vlan_mode(netdev->features, &value); 1268 /* rx checksum 1269 if (adapter->rx_csum) 1270 value |= MAC_CTRL_RX_CHKSUM_EN; 1271 */ 1272 /* filter mode */ 1273 value |= MAC_CTRL_BC_EN; 1274 if (netdev->flags & IFF_PROMISC) 1275 value |= MAC_CTRL_PROMIS_EN; 1276 else if (netdev->flags & IFF_ALLMULTI) 1277 value |= MAC_CTRL_MC_ALL_EN; 1278 /* value |= MAC_CTRL_LOOPBACK; */ 1279 iowrite32(value, hw->hw_addr + REG_MAC_CTRL); 1280 } 1281 1282 static u32 atl1_check_link(struct atl1_adapter *adapter) 1283 { 1284 struct atl1_hw *hw = &adapter->hw; 1285 struct net_device *netdev = adapter->netdev; 1286 u32 ret_val; 1287 u16 speed, duplex, phy_data; 1288 int reconfig = 0; 1289 1290 /* MII_BMSR must read twice */ 1291 atl1_read_phy_reg(hw, MII_BMSR, &phy_data); 1292 atl1_read_phy_reg(hw, MII_BMSR, &phy_data); 1293 if (!(phy_data & BMSR_LSTATUS)) { 1294 /* link down */ 1295 if (netif_carrier_ok(netdev)) { 1296 /* old link state: Up */ 1297 if (netif_msg_link(adapter)) 1298 dev_info(&adapter->pdev->dev, "link is down\n"); 1299 adapter->link_speed = SPEED_0; 1300 netif_carrier_off(netdev); 1301 } 1302 return 0; 1303 } 1304 1305 /* Link Up */ 1306 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex); 1307 if (ret_val) 1308 return ret_val; 1309 1310 switch (hw->media_type) { 1311 case MEDIA_TYPE_1000M_FULL: 1312 if (speed != SPEED_1000 || duplex != FULL_DUPLEX) 1313 reconfig = 1; 1314 break; 1315 case MEDIA_TYPE_100M_FULL: 1316 if (speed != SPEED_100 || duplex != FULL_DUPLEX) 1317 reconfig = 1; 1318 break; 1319 case MEDIA_TYPE_100M_HALF: 1320 if (speed != SPEED_100 || duplex != HALF_DUPLEX) 1321 reconfig = 1; 1322 break; 1323 case MEDIA_TYPE_10M_FULL: 1324 if (speed != SPEED_10 || duplex != FULL_DUPLEX) 1325 reconfig = 1; 1326 break; 1327 case MEDIA_TYPE_10M_HALF: 1328 if (speed != SPEED_10 || duplex != HALF_DUPLEX) 1329 reconfig = 1; 1330 break; 1331 } 1332 1333 /* link result is our setting */ 1334 if (!reconfig) { 1335 if (adapter->link_speed != speed || 1336 adapter->link_duplex != duplex) { 1337 adapter->link_speed = speed; 1338 adapter->link_duplex = duplex; 1339 atl1_setup_mac_ctrl(adapter); 1340 if (netif_msg_link(adapter)) 1341 dev_info(&adapter->pdev->dev, 1342 "%s link is up %d Mbps %s\n", 1343 netdev->name, adapter->link_speed, 1344 adapter->link_duplex == FULL_DUPLEX ? 1345 "full duplex" : "half duplex"); 1346 } 1347 if (!netif_carrier_ok(netdev)) { 1348 /* Link down -> Up */ 1349 netif_carrier_on(netdev); 1350 } 1351 return 0; 1352 } 1353 1354 /* change original link status */ 1355 if (netif_carrier_ok(netdev)) { 1356 adapter->link_speed = SPEED_0; 1357 netif_carrier_off(netdev); 1358 netif_stop_queue(netdev); 1359 } 1360 1361 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR && 1362 hw->media_type != MEDIA_TYPE_1000M_FULL) { 1363 switch (hw->media_type) { 1364 case MEDIA_TYPE_100M_FULL: 1365 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | 1366 MII_CR_RESET; 1367 break; 1368 case MEDIA_TYPE_100M_HALF: 1369 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 1370 break; 1371 case MEDIA_TYPE_10M_FULL: 1372 phy_data = 1373 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 1374 break; 1375 default: 1376 /* MEDIA_TYPE_10M_HALF: */ 1377 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 1378 break; 1379 } 1380 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 1381 return 0; 1382 } 1383 1384 /* auto-neg, insert timer to re-config phy */ 1385 if (!adapter->phy_timer_pending) { 1386 adapter->phy_timer_pending = true; 1387 mod_timer(&adapter->phy_config_timer, 1388 round_jiffies(jiffies + 3 * HZ)); 1389 } 1390 1391 return 0; 1392 } 1393 1394 static void set_flow_ctrl_old(struct atl1_adapter *adapter) 1395 { 1396 u32 hi, lo, value; 1397 1398 /* RFD Flow Control */ 1399 value = adapter->rfd_ring.count; 1400 hi = value / 16; 1401 if (hi < 2) 1402 hi = 2; 1403 lo = value * 7 / 8; 1404 1405 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | 1406 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); 1407 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH); 1408 1409 /* RRD Flow Control */ 1410 value = adapter->rrd_ring.count; 1411 lo = value / 16; 1412 hi = value * 7 / 8; 1413 if (lo < 2) 1414 lo = 2; 1415 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | 1416 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); 1417 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH); 1418 } 1419 1420 static void set_flow_ctrl_new(struct atl1_hw *hw) 1421 { 1422 u32 hi, lo, value; 1423 1424 /* RXF Flow Control */ 1425 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN); 1426 lo = value / 16; 1427 if (lo < 192) 1428 lo = 192; 1429 hi = value * 7 / 8; 1430 if (hi < lo) 1431 hi = lo + 16; 1432 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | 1433 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); 1434 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH); 1435 1436 /* RRD Flow Control */ 1437 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN); 1438 lo = value / 8; 1439 hi = value * 7 / 8; 1440 if (lo < 2) 1441 lo = 2; 1442 if (hi < lo) 1443 hi = lo + 3; 1444 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | 1445 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); 1446 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH); 1447 } 1448 1449 /** 1450 * atl1_configure - Configure Transmit&Receive Unit after Reset 1451 * @adapter: board private structure 1452 * 1453 * Configure the Tx /Rx unit of the MAC after a reset. 1454 */ 1455 static u32 atl1_configure(struct atl1_adapter *adapter) 1456 { 1457 struct atl1_hw *hw = &adapter->hw; 1458 u32 value; 1459 1460 /* clear interrupt status */ 1461 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR); 1462 1463 /* set MAC Address */ 1464 value = (((u32) hw->mac_addr[2]) << 24) | 1465 (((u32) hw->mac_addr[3]) << 16) | 1466 (((u32) hw->mac_addr[4]) << 8) | 1467 (((u32) hw->mac_addr[5])); 1468 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); 1469 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); 1470 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4)); 1471 1472 /* tx / rx ring */ 1473 1474 /* HI base address */ 1475 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32), 1476 hw->hw_addr + REG_DESC_BASE_ADDR_HI); 1477 /* LO base address */ 1478 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL), 1479 hw->hw_addr + REG_DESC_RFD_ADDR_LO); 1480 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL), 1481 hw->hw_addr + REG_DESC_RRD_ADDR_LO); 1482 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL), 1483 hw->hw_addr + REG_DESC_TPD_ADDR_LO); 1484 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL), 1485 hw->hw_addr + REG_DESC_CMB_ADDR_LO); 1486 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL), 1487 hw->hw_addr + REG_DESC_SMB_ADDR_LO); 1488 1489 /* element count */ 1490 value = adapter->rrd_ring.count; 1491 value <<= 16; 1492 value += adapter->rfd_ring.count; 1493 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE); 1494 iowrite32(adapter->tpd_ring.count, hw->hw_addr + 1495 REG_DESC_TPD_RING_SIZE); 1496 1497 /* Load Ptr */ 1498 iowrite32(1, hw->hw_addr + REG_LOAD_PTR); 1499 1500 /* config Mailbox */ 1501 value = ((atomic_read(&adapter->tpd_ring.next_to_use) 1502 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) | 1503 ((atomic_read(&adapter->rrd_ring.next_to_clean) 1504 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) | 1505 ((atomic_read(&adapter->rfd_ring.next_to_use) 1506 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT); 1507 iowrite32(value, hw->hw_addr + REG_MAILBOX); 1508 1509 /* config IPG/IFG */ 1510 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK) 1511 << MAC_IPG_IFG_IPGT_SHIFT) | 1512 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) 1513 << MAC_IPG_IFG_MIFG_SHIFT) | 1514 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) 1515 << MAC_IPG_IFG_IPGR1_SHIFT) | 1516 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) 1517 << MAC_IPG_IFG_IPGR2_SHIFT); 1518 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG); 1519 1520 /* config Half-Duplex Control */ 1521 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | 1522 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) 1523 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | 1524 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | 1525 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | 1526 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) 1527 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); 1528 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL); 1529 1530 /* set Interrupt Moderator Timer */ 1531 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT); 1532 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL); 1533 1534 /* set Interrupt Clear Timer */ 1535 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER); 1536 1537 /* set max frame size hw will accept */ 1538 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU); 1539 1540 /* jumbo size & rrd retirement timer */ 1541 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) 1542 << RXQ_JMBOSZ_TH_SHIFT) | 1543 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK) 1544 << RXQ_JMBO_LKAH_SHIFT) | 1545 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK) 1546 << RXQ_RRD_TIMER_SHIFT); 1547 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM); 1548 1549 /* Flow Control */ 1550 switch (hw->dev_rev) { 1551 case 0x8001: 1552 case 0x9001: 1553 case 0x9002: 1554 case 0x9003: 1555 set_flow_ctrl_old(adapter); 1556 break; 1557 default: 1558 set_flow_ctrl_new(hw); 1559 break; 1560 } 1561 1562 /* config TXQ */ 1563 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK) 1564 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) | 1565 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK) 1566 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) | 1567 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK) 1568 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE | 1569 TXQ_CTRL_EN; 1570 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL); 1571 1572 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */ 1573 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK) 1574 << TX_JUMBO_TASK_TH_SHIFT) | 1575 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK) 1576 << TX_TPD_MIN_IPG_SHIFT); 1577 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG); 1578 1579 /* config RXQ */ 1580 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK) 1581 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) | 1582 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK) 1583 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) | 1584 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK) 1585 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN | 1586 RXQ_CTRL_EN; 1587 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL); 1588 1589 /* config DMA Engine */ 1590 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK) 1591 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) | 1592 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK) 1593 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN | 1594 DMA_CTRL_DMAW_EN; 1595 value |= (u32) hw->dma_ord; 1596 if (atl1_rcb_128 == hw->rcb_value) 1597 value |= DMA_CTRL_RCB_VALUE; 1598 iowrite32(value, hw->hw_addr + REG_DMA_CTRL); 1599 1600 /* config CMB / SMB */ 1601 value = (hw->cmb_tpd > adapter->tpd_ring.count) ? 1602 hw->cmb_tpd : adapter->tpd_ring.count; 1603 value <<= 16; 1604 value |= hw->cmb_rrd; 1605 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH); 1606 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16); 1607 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER); 1608 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER); 1609 1610 /* --- enable CMB / SMB */ 1611 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN; 1612 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL); 1613 1614 value = ioread32(adapter->hw.hw_addr + REG_ISR); 1615 if (unlikely((value & ISR_PHY_LINKDOWN) != 0)) 1616 value = 1; /* config failed */ 1617 else 1618 value = 0; 1619 1620 /* clear all interrupt status */ 1621 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR); 1622 iowrite32(0, adapter->hw.hw_addr + REG_ISR); 1623 return value; 1624 } 1625 1626 /* 1627 * atl1_pcie_patch - Patch for PCIE module 1628 */ 1629 static void atl1_pcie_patch(struct atl1_adapter *adapter) 1630 { 1631 u32 value; 1632 1633 /* much vendor magic here */ 1634 value = 0x6500; 1635 iowrite32(value, adapter->hw.hw_addr + 0x12FC); 1636 /* pcie flow control mode change */ 1637 value = ioread32(adapter->hw.hw_addr + 0x1008); 1638 value |= 0x8000; 1639 iowrite32(value, adapter->hw.hw_addr + 0x1008); 1640 } 1641 1642 /* 1643 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400 1644 * on PCI Command register is disable. 1645 * The function enable this bit. 1646 * Brackett, 2006/03/15 1647 */ 1648 static void atl1_via_workaround(struct atl1_adapter *adapter) 1649 { 1650 unsigned long value; 1651 1652 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND); 1653 if (value & PCI_COMMAND_INTX_DISABLE) 1654 value &= ~PCI_COMMAND_INTX_DISABLE; 1655 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND); 1656 } 1657 1658 static void atl1_inc_smb(struct atl1_adapter *adapter) 1659 { 1660 struct net_device *netdev = adapter->netdev; 1661 struct stats_msg_block *smb = adapter->smb.smb; 1662 1663 u64 new_rx_errors = smb->rx_frag + 1664 smb->rx_fcs_err + 1665 smb->rx_len_err + 1666 smb->rx_sz_ov + 1667 smb->rx_rxf_ov + 1668 smb->rx_rrd_ov + 1669 smb->rx_align_err; 1670 u64 new_tx_errors = smb->tx_late_col + 1671 smb->tx_abort_col + 1672 smb->tx_underrun + 1673 smb->tx_trunc; 1674 1675 /* Fill out the OS statistics structure */ 1676 adapter->soft_stats.rx_packets += smb->rx_ok + new_rx_errors; 1677 adapter->soft_stats.tx_packets += smb->tx_ok + new_tx_errors; 1678 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt; 1679 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt; 1680 adapter->soft_stats.multicast += smb->rx_mcast; 1681 adapter->soft_stats.collisions += smb->tx_1_col + 1682 smb->tx_2_col + 1683 smb->tx_late_col + 1684 smb->tx_abort_col; 1685 1686 /* Rx Errors */ 1687 adapter->soft_stats.rx_errors += new_rx_errors; 1688 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov; 1689 adapter->soft_stats.rx_length_errors += smb->rx_len_err; 1690 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err; 1691 adapter->soft_stats.rx_frame_errors += smb->rx_align_err; 1692 1693 adapter->soft_stats.rx_pause += smb->rx_pause; 1694 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov; 1695 adapter->soft_stats.rx_trunc += smb->rx_sz_ov; 1696 1697 /* Tx Errors */ 1698 adapter->soft_stats.tx_errors += new_tx_errors; 1699 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun; 1700 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col; 1701 adapter->soft_stats.tx_window_errors += smb->tx_late_col; 1702 1703 adapter->soft_stats.excecol += smb->tx_abort_col; 1704 adapter->soft_stats.deffer += smb->tx_defer; 1705 adapter->soft_stats.scc += smb->tx_1_col; 1706 adapter->soft_stats.mcc += smb->tx_2_col; 1707 adapter->soft_stats.latecol += smb->tx_late_col; 1708 adapter->soft_stats.tx_underrun += smb->tx_underrun; 1709 adapter->soft_stats.tx_trunc += smb->tx_trunc; 1710 adapter->soft_stats.tx_pause += smb->tx_pause; 1711 1712 netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes; 1713 netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes; 1714 netdev->stats.multicast = adapter->soft_stats.multicast; 1715 netdev->stats.collisions = adapter->soft_stats.collisions; 1716 netdev->stats.rx_errors = adapter->soft_stats.rx_errors; 1717 netdev->stats.rx_length_errors = 1718 adapter->soft_stats.rx_length_errors; 1719 netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors; 1720 netdev->stats.rx_frame_errors = 1721 adapter->soft_stats.rx_frame_errors; 1722 netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors; 1723 netdev->stats.rx_dropped = adapter->soft_stats.rx_rrd_ov; 1724 netdev->stats.tx_errors = adapter->soft_stats.tx_errors; 1725 netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors; 1726 netdev->stats.tx_aborted_errors = 1727 adapter->soft_stats.tx_aborted_errors; 1728 netdev->stats.tx_window_errors = 1729 adapter->soft_stats.tx_window_errors; 1730 netdev->stats.tx_carrier_errors = 1731 adapter->soft_stats.tx_carrier_errors; 1732 1733 netdev->stats.rx_packets = adapter->soft_stats.rx_packets; 1734 netdev->stats.tx_packets = adapter->soft_stats.tx_packets; 1735 } 1736 1737 static void atl1_update_mailbox(struct atl1_adapter *adapter) 1738 { 1739 unsigned long flags; 1740 u32 tpd_next_to_use; 1741 u32 rfd_next_to_use; 1742 u32 rrd_next_to_clean; 1743 u32 value; 1744 1745 spin_lock_irqsave(&adapter->mb_lock, flags); 1746 1747 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); 1748 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use); 1749 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean); 1750 1751 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << 1752 MB_RFD_PROD_INDX_SHIFT) | 1753 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << 1754 MB_RRD_CONS_INDX_SHIFT) | 1755 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << 1756 MB_TPD_PROD_INDX_SHIFT); 1757 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); 1758 1759 spin_unlock_irqrestore(&adapter->mb_lock, flags); 1760 } 1761 1762 static void atl1_clean_alloc_flag(struct atl1_adapter *adapter, 1763 struct rx_return_desc *rrd, u16 offset) 1764 { 1765 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1766 1767 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) { 1768 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0; 1769 if (++rfd_ring->next_to_clean == rfd_ring->count) { 1770 rfd_ring->next_to_clean = 0; 1771 } 1772 } 1773 } 1774 1775 static void atl1_update_rfd_index(struct atl1_adapter *adapter, 1776 struct rx_return_desc *rrd) 1777 { 1778 u16 num_buf; 1779 1780 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) / 1781 adapter->rx_buffer_len; 1782 if (rrd->num_buf == num_buf) 1783 /* clean alloc flag for bad rrd */ 1784 atl1_clean_alloc_flag(adapter, rrd, num_buf); 1785 } 1786 1787 static void atl1_rx_checksum(struct atl1_adapter *adapter, 1788 struct rx_return_desc *rrd, struct sk_buff *skb) 1789 { 1790 struct pci_dev *pdev = adapter->pdev; 1791 1792 /* 1793 * The L1 hardware contains a bug that erroneously sets the 1794 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a 1795 * fragmented IP packet is received, even though the packet 1796 * is perfectly valid and its checksum is correct. There's 1797 * no way to distinguish between one of these good packets 1798 * and a packet that actually contains a TCP/UDP checksum 1799 * error, so all we can do is allow it to be handed up to 1800 * the higher layers and let it be sorted out there. 1801 */ 1802 1803 skb_checksum_none_assert(skb); 1804 1805 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { 1806 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC | 1807 ERR_FLAG_CODE | ERR_FLAG_OV)) { 1808 adapter->hw_csum_err++; 1809 if (netif_msg_rx_err(adapter)) 1810 dev_printk(KERN_DEBUG, &pdev->dev, 1811 "rx checksum error\n"); 1812 return; 1813 } 1814 } 1815 1816 /* not IPv4 */ 1817 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4)) 1818 /* checksum is invalid, but it's not an IPv4 pkt, so ok */ 1819 return; 1820 1821 /* IPv4 packet */ 1822 if (likely(!(rrd->err_flg & 1823 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) { 1824 skb->ip_summed = CHECKSUM_UNNECESSARY; 1825 adapter->hw_csum_good++; 1826 return; 1827 } 1828 } 1829 1830 /** 1831 * atl1_alloc_rx_buffers - Replace used receive buffers 1832 * @adapter: address of board private structure 1833 */ 1834 static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter) 1835 { 1836 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1837 struct pci_dev *pdev = adapter->pdev; 1838 struct page *page; 1839 unsigned long offset; 1840 struct atl1_buffer *buffer_info, *next_info; 1841 struct sk_buff *skb; 1842 u16 num_alloc = 0; 1843 u16 rfd_next_to_use, next_next; 1844 struct rx_free_desc *rfd_desc; 1845 1846 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use); 1847 if (++next_next == rfd_ring->count) 1848 next_next = 0; 1849 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; 1850 next_info = &rfd_ring->buffer_info[next_next]; 1851 1852 while (!buffer_info->alloced && !next_info->alloced) { 1853 if (buffer_info->skb) { 1854 buffer_info->alloced = 1; 1855 goto next; 1856 } 1857 1858 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use); 1859 1860 skb = netdev_alloc_skb_ip_align(adapter->netdev, 1861 adapter->rx_buffer_len); 1862 if (unlikely(!skb)) { 1863 /* Better luck next round */ 1864 adapter->soft_stats.rx_dropped++; 1865 break; 1866 } 1867 1868 buffer_info->alloced = 1; 1869 buffer_info->skb = skb; 1870 buffer_info->length = (u16) adapter->rx_buffer_len; 1871 page = virt_to_page(skb->data); 1872 offset = offset_in_page(skb->data); 1873 buffer_info->dma = pci_map_page(pdev, page, offset, 1874 adapter->rx_buffer_len, 1875 PCI_DMA_FROMDEVICE); 1876 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 1877 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len); 1878 rfd_desc->coalese = 0; 1879 1880 next: 1881 rfd_next_to_use = next_next; 1882 if (unlikely(++next_next == rfd_ring->count)) 1883 next_next = 0; 1884 1885 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; 1886 next_info = &rfd_ring->buffer_info[next_next]; 1887 num_alloc++; 1888 } 1889 1890 if (num_alloc) { 1891 /* 1892 * Force memory writes to complete before letting h/w 1893 * know there are new descriptors to fetch. (Only 1894 * applicable for weak-ordered memory model archs, 1895 * such as IA-64). 1896 */ 1897 wmb(); 1898 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use); 1899 } 1900 return num_alloc; 1901 } 1902 1903 static int atl1_intr_rx(struct atl1_adapter *adapter, int budget) 1904 { 1905 int i, count; 1906 u16 length; 1907 u16 rrd_next_to_clean; 1908 u32 value; 1909 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1910 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1911 struct atl1_buffer *buffer_info; 1912 struct rx_return_desc *rrd; 1913 struct sk_buff *skb; 1914 1915 count = 0; 1916 1917 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean); 1918 1919 while (count < budget) { 1920 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean); 1921 i = 1; 1922 if (likely(rrd->xsz.valid)) { /* packet valid */ 1923 chk_rrd: 1924 /* check rrd status */ 1925 if (likely(rrd->num_buf == 1)) 1926 goto rrd_ok; 1927 else if (netif_msg_rx_err(adapter)) { 1928 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1929 "unexpected RRD buffer count\n"); 1930 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1931 "rx_buf_len = %d\n", 1932 adapter->rx_buffer_len); 1933 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1934 "RRD num_buf = %d\n", 1935 rrd->num_buf); 1936 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1937 "RRD pkt_len = %d\n", 1938 rrd->xsz.xsum_sz.pkt_size); 1939 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1940 "RRD pkt_flg = 0x%08X\n", 1941 rrd->pkt_flg); 1942 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1943 "RRD err_flg = 0x%08X\n", 1944 rrd->err_flg); 1945 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1946 "RRD vlan_tag = 0x%08X\n", 1947 rrd->vlan_tag); 1948 } 1949 1950 /* rrd seems to be bad */ 1951 if (unlikely(i-- > 0)) { 1952 /* rrd may not be DMAed completely */ 1953 udelay(1); 1954 goto chk_rrd; 1955 } 1956 /* bad rrd */ 1957 if (netif_msg_rx_err(adapter)) 1958 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1959 "bad RRD\n"); 1960 /* see if update RFD index */ 1961 if (rrd->num_buf > 1) 1962 atl1_update_rfd_index(adapter, rrd); 1963 1964 /* update rrd */ 1965 rrd->xsz.valid = 0; 1966 if (++rrd_next_to_clean == rrd_ring->count) 1967 rrd_next_to_clean = 0; 1968 count++; 1969 continue; 1970 } else { /* current rrd still not be updated */ 1971 1972 break; 1973 } 1974 rrd_ok: 1975 /* clean alloc flag for bad rrd */ 1976 atl1_clean_alloc_flag(adapter, rrd, 0); 1977 1978 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx]; 1979 if (++rfd_ring->next_to_clean == rfd_ring->count) 1980 rfd_ring->next_to_clean = 0; 1981 1982 /* update rrd next to clean */ 1983 if (++rrd_next_to_clean == rrd_ring->count) 1984 rrd_next_to_clean = 0; 1985 count++; 1986 1987 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { 1988 if (!(rrd->err_flg & 1989 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM 1990 | ERR_FLAG_LEN))) { 1991 /* packet error, don't need upstream */ 1992 buffer_info->alloced = 0; 1993 rrd->xsz.valid = 0; 1994 continue; 1995 } 1996 } 1997 1998 /* Good Receive */ 1999 pci_unmap_page(adapter->pdev, buffer_info->dma, 2000 buffer_info->length, PCI_DMA_FROMDEVICE); 2001 buffer_info->dma = 0; 2002 skb = buffer_info->skb; 2003 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size); 2004 2005 skb_put(skb, length - ETH_FCS_LEN); 2006 2007 /* Receive Checksum Offload */ 2008 atl1_rx_checksum(adapter, rrd, skb); 2009 skb->protocol = eth_type_trans(skb, adapter->netdev); 2010 2011 if (rrd->pkt_flg & PACKET_FLAG_VLAN_INS) { 2012 u16 vlan_tag = (rrd->vlan_tag >> 4) | 2013 ((rrd->vlan_tag & 7) << 13) | 2014 ((rrd->vlan_tag & 8) << 9); 2015 2016 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 2017 } 2018 netif_receive_skb(skb); 2019 2020 /* let protocol layer free skb */ 2021 buffer_info->skb = NULL; 2022 buffer_info->alloced = 0; 2023 rrd->xsz.valid = 0; 2024 } 2025 2026 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean); 2027 2028 atl1_alloc_rx_buffers(adapter); 2029 2030 /* update mailbox ? */ 2031 if (count) { 2032 u32 tpd_next_to_use; 2033 u32 rfd_next_to_use; 2034 2035 spin_lock(&adapter->mb_lock); 2036 2037 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); 2038 rfd_next_to_use = 2039 atomic_read(&adapter->rfd_ring.next_to_use); 2040 rrd_next_to_clean = 2041 atomic_read(&adapter->rrd_ring.next_to_clean); 2042 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << 2043 MB_RFD_PROD_INDX_SHIFT) | 2044 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << 2045 MB_RRD_CONS_INDX_SHIFT) | 2046 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << 2047 MB_TPD_PROD_INDX_SHIFT); 2048 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); 2049 spin_unlock(&adapter->mb_lock); 2050 } 2051 2052 return count; 2053 } 2054 2055 static int atl1_intr_tx(struct atl1_adapter *adapter) 2056 { 2057 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2058 struct atl1_buffer *buffer_info; 2059 u16 sw_tpd_next_to_clean; 2060 u16 cmb_tpd_next_to_clean; 2061 int count = 0; 2062 2063 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean); 2064 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx); 2065 2066 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) { 2067 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean]; 2068 if (buffer_info->dma) { 2069 pci_unmap_page(adapter->pdev, buffer_info->dma, 2070 buffer_info->length, PCI_DMA_TODEVICE); 2071 buffer_info->dma = 0; 2072 } 2073 2074 if (buffer_info->skb) { 2075 dev_consume_skb_irq(buffer_info->skb); 2076 buffer_info->skb = NULL; 2077 } 2078 2079 if (++sw_tpd_next_to_clean == tpd_ring->count) 2080 sw_tpd_next_to_clean = 0; 2081 2082 count++; 2083 } 2084 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean); 2085 2086 if (netif_queue_stopped(adapter->netdev) && 2087 netif_carrier_ok(adapter->netdev)) 2088 netif_wake_queue(adapter->netdev); 2089 2090 return count; 2091 } 2092 2093 static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring) 2094 { 2095 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean); 2096 u16 next_to_use = atomic_read(&tpd_ring->next_to_use); 2097 return (next_to_clean > next_to_use) ? 2098 next_to_clean - next_to_use - 1 : 2099 tpd_ring->count + next_to_clean - next_to_use - 1; 2100 } 2101 2102 static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb, 2103 struct tx_packet_desc *ptpd) 2104 { 2105 u8 hdr_len, ip_off; 2106 u32 real_len; 2107 2108 if (skb_shinfo(skb)->gso_size) { 2109 int err; 2110 2111 err = skb_cow_head(skb, 0); 2112 if (err < 0) 2113 return err; 2114 2115 if (skb->protocol == htons(ETH_P_IP)) { 2116 struct iphdr *iph = ip_hdr(skb); 2117 2118 real_len = (((unsigned char *)iph - skb->data) + 2119 ntohs(iph->tot_len)); 2120 if (real_len < skb->len) 2121 pskb_trim(skb, real_len); 2122 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb)); 2123 if (skb->len == hdr_len) { 2124 iph->check = 0; 2125 tcp_hdr(skb)->check = 2126 ~csum_tcpudp_magic(iph->saddr, 2127 iph->daddr, tcp_hdrlen(skb), 2128 IPPROTO_TCP, 0); 2129 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) << 2130 TPD_IPHL_SHIFT; 2131 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) & 2132 TPD_TCPHDRLEN_MASK) << 2133 TPD_TCPHDRLEN_SHIFT; 2134 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT; 2135 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT; 2136 return 1; 2137 } 2138 2139 iph->check = 0; 2140 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 2141 iph->daddr, 0, IPPROTO_TCP, 0); 2142 ip_off = (unsigned char *)iph - 2143 (unsigned char *) skb_network_header(skb); 2144 if (ip_off == 8) /* 802.3-SNAP frame */ 2145 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; 2146 else if (ip_off != 0) 2147 return -2; 2148 2149 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) << 2150 TPD_IPHL_SHIFT; 2151 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) & 2152 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT; 2153 ptpd->word3 |= (skb_shinfo(skb)->gso_size & 2154 TPD_MSS_MASK) << TPD_MSS_SHIFT; 2155 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT; 2156 return 3; 2157 } 2158 } 2159 return 0; 2160 } 2161 2162 static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb, 2163 struct tx_packet_desc *ptpd) 2164 { 2165 u8 css, cso; 2166 2167 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 2168 css = skb_checksum_start_offset(skb); 2169 cso = css + (u8) skb->csum_offset; 2170 if (unlikely(css & 0x1)) { 2171 /* L1 hardware requires an even number here */ 2172 if (netif_msg_tx_err(adapter)) 2173 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2174 "payload offset not an even number\n"); 2175 return -1; 2176 } 2177 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) << 2178 TPD_PLOADOFFSET_SHIFT; 2179 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) << 2180 TPD_CCSUMOFFSET_SHIFT; 2181 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT; 2182 return true; 2183 } 2184 return 0; 2185 } 2186 2187 static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb, 2188 struct tx_packet_desc *ptpd) 2189 { 2190 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2191 struct atl1_buffer *buffer_info; 2192 u16 buf_len = skb->len; 2193 struct page *page; 2194 unsigned long offset; 2195 unsigned int nr_frags; 2196 unsigned int f; 2197 int retval; 2198 u16 next_to_use; 2199 u16 data_len; 2200 u8 hdr_len; 2201 2202 buf_len -= skb->data_len; 2203 nr_frags = skb_shinfo(skb)->nr_frags; 2204 next_to_use = atomic_read(&tpd_ring->next_to_use); 2205 buffer_info = &tpd_ring->buffer_info[next_to_use]; 2206 BUG_ON(buffer_info->skb); 2207 /* put skb in last TPD */ 2208 buffer_info->skb = NULL; 2209 2210 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK; 2211 if (retval) { 2212 /* TSO */ 2213 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2214 buffer_info->length = hdr_len; 2215 page = virt_to_page(skb->data); 2216 offset = offset_in_page(skb->data); 2217 buffer_info->dma = pci_map_page(adapter->pdev, page, 2218 offset, hdr_len, 2219 PCI_DMA_TODEVICE); 2220 2221 if (++next_to_use == tpd_ring->count) 2222 next_to_use = 0; 2223 2224 if (buf_len > hdr_len) { 2225 int i, nseg; 2226 2227 data_len = buf_len - hdr_len; 2228 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) / 2229 ATL1_MAX_TX_BUF_LEN; 2230 for (i = 0; i < nseg; i++) { 2231 buffer_info = 2232 &tpd_ring->buffer_info[next_to_use]; 2233 buffer_info->skb = NULL; 2234 buffer_info->length = 2235 (ATL1_MAX_TX_BUF_LEN >= 2236 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len; 2237 data_len -= buffer_info->length; 2238 page = virt_to_page(skb->data + 2239 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)); 2240 offset = offset_in_page(skb->data + 2241 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)); 2242 buffer_info->dma = pci_map_page(adapter->pdev, 2243 page, offset, buffer_info->length, 2244 PCI_DMA_TODEVICE); 2245 if (++next_to_use == tpd_ring->count) 2246 next_to_use = 0; 2247 } 2248 } 2249 } else { 2250 /* not TSO */ 2251 buffer_info->length = buf_len; 2252 page = virt_to_page(skb->data); 2253 offset = offset_in_page(skb->data); 2254 buffer_info->dma = pci_map_page(adapter->pdev, page, 2255 offset, buf_len, PCI_DMA_TODEVICE); 2256 if (++next_to_use == tpd_ring->count) 2257 next_to_use = 0; 2258 } 2259 2260 for (f = 0; f < nr_frags; f++) { 2261 const struct skb_frag_struct *frag; 2262 u16 i, nseg; 2263 2264 frag = &skb_shinfo(skb)->frags[f]; 2265 buf_len = skb_frag_size(frag); 2266 2267 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) / 2268 ATL1_MAX_TX_BUF_LEN; 2269 for (i = 0; i < nseg; i++) { 2270 buffer_info = &tpd_ring->buffer_info[next_to_use]; 2271 BUG_ON(buffer_info->skb); 2272 2273 buffer_info->skb = NULL; 2274 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ? 2275 ATL1_MAX_TX_BUF_LEN : buf_len; 2276 buf_len -= buffer_info->length; 2277 buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev, 2278 frag, i * ATL1_MAX_TX_BUF_LEN, 2279 buffer_info->length, DMA_TO_DEVICE); 2280 2281 if (++next_to_use == tpd_ring->count) 2282 next_to_use = 0; 2283 } 2284 } 2285 2286 /* last tpd's buffer-info */ 2287 buffer_info->skb = skb; 2288 } 2289 2290 static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count, 2291 struct tx_packet_desc *ptpd) 2292 { 2293 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2294 struct atl1_buffer *buffer_info; 2295 struct tx_packet_desc *tpd; 2296 u16 j; 2297 u32 val; 2298 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use); 2299 2300 for (j = 0; j < count; j++) { 2301 buffer_info = &tpd_ring->buffer_info[next_to_use]; 2302 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use); 2303 if (tpd != ptpd) 2304 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc)); 2305 tpd->buffer_addr = cpu_to_le64(buffer_info->dma); 2306 tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT); 2307 tpd->word2 |= (cpu_to_le16(buffer_info->length) & 2308 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT; 2309 2310 /* 2311 * if this is the first packet in a TSO chain, set 2312 * TPD_HDRFLAG, otherwise, clear it. 2313 */ 2314 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & 2315 TPD_SEGMENT_EN_MASK; 2316 if (val) { 2317 if (!j) 2318 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT; 2319 else 2320 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT); 2321 } 2322 2323 if (j == (count - 1)) 2324 tpd->word3 |= 1 << TPD_EOP_SHIFT; 2325 2326 if (++next_to_use == tpd_ring->count) 2327 next_to_use = 0; 2328 } 2329 /* 2330 * Force memory writes to complete before letting h/w 2331 * know there are new descriptors to fetch. (Only 2332 * applicable for weak-ordered memory model archs, 2333 * such as IA-64). 2334 */ 2335 wmb(); 2336 2337 atomic_set(&tpd_ring->next_to_use, next_to_use); 2338 } 2339 2340 static netdev_tx_t atl1_xmit_frame(struct sk_buff *skb, 2341 struct net_device *netdev) 2342 { 2343 struct atl1_adapter *adapter = netdev_priv(netdev); 2344 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2345 int len; 2346 int tso; 2347 int count = 1; 2348 int ret_val; 2349 struct tx_packet_desc *ptpd; 2350 u16 vlan_tag; 2351 unsigned int nr_frags = 0; 2352 unsigned int mss = 0; 2353 unsigned int f; 2354 unsigned int proto_hdr_len; 2355 2356 len = skb_headlen(skb); 2357 2358 if (unlikely(skb->len <= 0)) { 2359 dev_kfree_skb_any(skb); 2360 return NETDEV_TX_OK; 2361 } 2362 2363 nr_frags = skb_shinfo(skb)->nr_frags; 2364 for (f = 0; f < nr_frags; f++) { 2365 unsigned int f_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); 2366 count += (f_size + ATL1_MAX_TX_BUF_LEN - 1) / 2367 ATL1_MAX_TX_BUF_LEN; 2368 } 2369 2370 mss = skb_shinfo(skb)->gso_size; 2371 if (mss) { 2372 if (skb->protocol == htons(ETH_P_IP)) { 2373 proto_hdr_len = (skb_transport_offset(skb) + 2374 tcp_hdrlen(skb)); 2375 if (unlikely(proto_hdr_len > len)) { 2376 dev_kfree_skb_any(skb); 2377 return NETDEV_TX_OK; 2378 } 2379 /* need additional TPD ? */ 2380 if (proto_hdr_len != len) 2381 count += (len - proto_hdr_len + 2382 ATL1_MAX_TX_BUF_LEN - 1) / 2383 ATL1_MAX_TX_BUF_LEN; 2384 } 2385 } 2386 2387 if (atl1_tpd_avail(&adapter->tpd_ring) < count) { 2388 /* not enough descriptors */ 2389 netif_stop_queue(netdev); 2390 if (netif_msg_tx_queued(adapter)) 2391 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2392 "tx busy\n"); 2393 return NETDEV_TX_BUSY; 2394 } 2395 2396 ptpd = ATL1_TPD_DESC(tpd_ring, 2397 (u16) atomic_read(&tpd_ring->next_to_use)); 2398 memset(ptpd, 0, sizeof(struct tx_packet_desc)); 2399 2400 if (skb_vlan_tag_present(skb)) { 2401 vlan_tag = skb_vlan_tag_get(skb); 2402 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) | 2403 ((vlan_tag >> 9) & 0x8); 2404 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT; 2405 ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) << 2406 TPD_VLANTAG_SHIFT; 2407 } 2408 2409 tso = atl1_tso(adapter, skb, ptpd); 2410 if (tso < 0) { 2411 dev_kfree_skb_any(skb); 2412 return NETDEV_TX_OK; 2413 } 2414 2415 if (!tso) { 2416 ret_val = atl1_tx_csum(adapter, skb, ptpd); 2417 if (ret_val < 0) { 2418 dev_kfree_skb_any(skb); 2419 return NETDEV_TX_OK; 2420 } 2421 } 2422 2423 atl1_tx_map(adapter, skb, ptpd); 2424 atl1_tx_queue(adapter, count, ptpd); 2425 atl1_update_mailbox(adapter); 2426 return NETDEV_TX_OK; 2427 } 2428 2429 static int atl1_rings_clean(struct napi_struct *napi, int budget) 2430 { 2431 struct atl1_adapter *adapter = container_of(napi, struct atl1_adapter, napi); 2432 int work_done = atl1_intr_rx(adapter, budget); 2433 2434 if (atl1_intr_tx(adapter)) 2435 work_done = budget; 2436 2437 /* Let's come again to process some more packets */ 2438 if (work_done >= budget) 2439 return work_done; 2440 2441 napi_complete_done(napi, work_done); 2442 /* re-enable Interrupt */ 2443 if (likely(adapter->int_enabled)) 2444 atlx_imr_set(adapter, IMR_NORMAL_MASK); 2445 return work_done; 2446 } 2447 2448 static inline int atl1_sched_rings_clean(struct atl1_adapter* adapter) 2449 { 2450 if (!napi_schedule_prep(&adapter->napi)) 2451 /* It is possible in case even the RX/TX ints are disabled via IMR 2452 * register the ISR bits are set anyway (but do not produce IRQ). 2453 * To handle such situation the napi functions used to check is 2454 * something scheduled or not. 2455 */ 2456 return 0; 2457 2458 __napi_schedule(&adapter->napi); 2459 2460 /* 2461 * Disable RX/TX ints via IMR register if it is 2462 * allowed. NAPI handler must reenable them in same 2463 * way. 2464 */ 2465 if (!adapter->int_enabled) 2466 return 1; 2467 2468 atlx_imr_set(adapter, IMR_NORXTX_MASK); 2469 return 1; 2470 } 2471 2472 /** 2473 * atl1_intr - Interrupt Handler 2474 * @irq: interrupt number 2475 * @data: pointer to a network interface device structure 2476 */ 2477 static irqreturn_t atl1_intr(int irq, void *data) 2478 { 2479 struct atl1_adapter *adapter = netdev_priv(data); 2480 u32 status; 2481 2482 status = adapter->cmb.cmb->int_stats; 2483 if (!status) 2484 return IRQ_NONE; 2485 2486 /* clear CMB interrupt status at once, 2487 * but leave rx/tx interrupt status in case it should be dropped 2488 * only if rx/tx processing queued. In other case interrupt 2489 * can be lost. 2490 */ 2491 adapter->cmb.cmb->int_stats = status & (ISR_CMB_TX | ISR_CMB_RX); 2492 2493 if (status & ISR_GPHY) /* clear phy status */ 2494 atlx_clear_phy_int(adapter); 2495 2496 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 2497 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR); 2498 2499 /* check if SMB intr */ 2500 if (status & ISR_SMB) 2501 atl1_inc_smb(adapter); 2502 2503 /* check if PCIE PHY Link down */ 2504 if (status & ISR_PHY_LINKDOWN) { 2505 if (netif_msg_intr(adapter)) 2506 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2507 "pcie phy link down %x\n", status); 2508 if (netif_running(adapter->netdev)) { /* reset MAC */ 2509 atlx_irq_disable(adapter); 2510 schedule_work(&adapter->reset_dev_task); 2511 return IRQ_HANDLED; 2512 } 2513 } 2514 2515 /* check if DMA read/write error ? */ 2516 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 2517 if (netif_msg_intr(adapter)) 2518 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2519 "pcie DMA r/w error (status = 0x%x)\n", 2520 status); 2521 atlx_irq_disable(adapter); 2522 schedule_work(&adapter->reset_dev_task); 2523 return IRQ_HANDLED; 2524 } 2525 2526 /* link event */ 2527 if (status & ISR_GPHY) { 2528 adapter->soft_stats.tx_carrier_errors++; 2529 atl1_check_for_link(adapter); 2530 } 2531 2532 /* transmit or receive event */ 2533 if (status & (ISR_CMB_TX | ISR_CMB_RX) && 2534 atl1_sched_rings_clean(adapter)) 2535 adapter->cmb.cmb->int_stats = adapter->cmb.cmb->int_stats & 2536 ~(ISR_CMB_TX | ISR_CMB_RX); 2537 2538 /* rx exception */ 2539 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN | 2540 ISR_RRD_OV | ISR_HOST_RFD_UNRUN | 2541 ISR_HOST_RRD_OV))) { 2542 if (netif_msg_intr(adapter)) 2543 dev_printk(KERN_DEBUG, 2544 &adapter->pdev->dev, 2545 "rx exception, ISR = 0x%x\n", 2546 status); 2547 atl1_sched_rings_clean(adapter); 2548 } 2549 2550 /* re-enable Interrupt */ 2551 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR); 2552 return IRQ_HANDLED; 2553 } 2554 2555 2556 /** 2557 * atl1_phy_config - Timer Call-back 2558 * @data: pointer to netdev cast into an unsigned long 2559 */ 2560 static void atl1_phy_config(struct timer_list *t) 2561 { 2562 struct atl1_adapter *adapter = from_timer(adapter, t, 2563 phy_config_timer); 2564 struct atl1_hw *hw = &adapter->hw; 2565 unsigned long flags; 2566 2567 spin_lock_irqsave(&adapter->lock, flags); 2568 adapter->phy_timer_pending = false; 2569 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 2570 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg); 2571 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN); 2572 spin_unlock_irqrestore(&adapter->lock, flags); 2573 } 2574 2575 /* 2576 * Orphaned vendor comment left intact here: 2577 * <vendor comment> 2578 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT 2579 * will assert. We do soft reset <0x1400=1> according 2580 * with the SPEC. BUT, it seemes that PCIE or DMA 2581 * state-machine will not be reset. DMAR_TO_INT will 2582 * assert again and again. 2583 * </vendor comment> 2584 */ 2585 2586 static int atl1_reset(struct atl1_adapter *adapter) 2587 { 2588 int ret; 2589 ret = atl1_reset_hw(&adapter->hw); 2590 if (ret) 2591 return ret; 2592 return atl1_init_hw(&adapter->hw); 2593 } 2594 2595 static s32 atl1_up(struct atl1_adapter *adapter) 2596 { 2597 struct net_device *netdev = adapter->netdev; 2598 int err; 2599 int irq_flags = 0; 2600 2601 /* hardware has been reset, we need to reload some things */ 2602 atlx_set_multi(netdev); 2603 atl1_init_ring_ptrs(adapter); 2604 atlx_restore_vlan(adapter); 2605 err = atl1_alloc_rx_buffers(adapter); 2606 if (unlikely(!err)) 2607 /* no RX BUFFER allocated */ 2608 return -ENOMEM; 2609 2610 if (unlikely(atl1_configure(adapter))) { 2611 err = -EIO; 2612 goto err_up; 2613 } 2614 2615 err = pci_enable_msi(adapter->pdev); 2616 if (err) { 2617 if (netif_msg_ifup(adapter)) 2618 dev_info(&adapter->pdev->dev, 2619 "Unable to enable MSI: %d\n", err); 2620 irq_flags |= IRQF_SHARED; 2621 } 2622 2623 err = request_irq(adapter->pdev->irq, atl1_intr, irq_flags, 2624 netdev->name, netdev); 2625 if (unlikely(err)) 2626 goto err_up; 2627 2628 napi_enable(&adapter->napi); 2629 atlx_irq_enable(adapter); 2630 atl1_check_link(adapter); 2631 netif_start_queue(netdev); 2632 return 0; 2633 2634 err_up: 2635 pci_disable_msi(adapter->pdev); 2636 /* free rx_buffers */ 2637 atl1_clean_rx_ring(adapter); 2638 return err; 2639 } 2640 2641 static void atl1_down(struct atl1_adapter *adapter) 2642 { 2643 struct net_device *netdev = adapter->netdev; 2644 2645 napi_disable(&adapter->napi); 2646 netif_stop_queue(netdev); 2647 del_timer_sync(&adapter->phy_config_timer); 2648 adapter->phy_timer_pending = false; 2649 2650 atlx_irq_disable(adapter); 2651 free_irq(adapter->pdev->irq, netdev); 2652 pci_disable_msi(adapter->pdev); 2653 atl1_reset_hw(&adapter->hw); 2654 adapter->cmb.cmb->int_stats = 0; 2655 2656 adapter->link_speed = SPEED_0; 2657 adapter->link_duplex = -1; 2658 netif_carrier_off(netdev); 2659 2660 atl1_clean_tx_ring(adapter); 2661 atl1_clean_rx_ring(adapter); 2662 } 2663 2664 static void atl1_reset_dev_task(struct work_struct *work) 2665 { 2666 struct atl1_adapter *adapter = 2667 container_of(work, struct atl1_adapter, reset_dev_task); 2668 struct net_device *netdev = adapter->netdev; 2669 2670 netif_device_detach(netdev); 2671 atl1_down(adapter); 2672 atl1_up(adapter); 2673 netif_device_attach(netdev); 2674 } 2675 2676 /** 2677 * atl1_change_mtu - Change the Maximum Transfer Unit 2678 * @netdev: network interface device structure 2679 * @new_mtu: new value for maximum frame size 2680 * 2681 * Returns 0 on success, negative on failure 2682 */ 2683 static int atl1_change_mtu(struct net_device *netdev, int new_mtu) 2684 { 2685 struct atl1_adapter *adapter = netdev_priv(netdev); 2686 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 2687 2688 adapter->hw.max_frame_size = max_frame; 2689 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3; 2690 adapter->rx_buffer_len = (max_frame + 7) & ~7; 2691 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8; 2692 2693 netdev->mtu = new_mtu; 2694 if (netif_running(netdev)) { 2695 atl1_down(adapter); 2696 atl1_up(adapter); 2697 } 2698 2699 return 0; 2700 } 2701 2702 /** 2703 * atl1_open - Called when a network interface is made active 2704 * @netdev: network interface device structure 2705 * 2706 * Returns 0 on success, negative value on failure 2707 * 2708 * The open entry point is called when a network interface is made 2709 * active by the system (IFF_UP). At this point all resources needed 2710 * for transmit and receive operations are allocated, the interrupt 2711 * handler is registered with the OS, the watchdog timer is started, 2712 * and the stack is notified that the interface is ready. 2713 */ 2714 static int atl1_open(struct net_device *netdev) 2715 { 2716 struct atl1_adapter *adapter = netdev_priv(netdev); 2717 int err; 2718 2719 netif_carrier_off(netdev); 2720 2721 /* allocate transmit descriptors */ 2722 err = atl1_setup_ring_resources(adapter); 2723 if (err) 2724 return err; 2725 2726 err = atl1_up(adapter); 2727 if (err) 2728 goto err_up; 2729 2730 return 0; 2731 2732 err_up: 2733 atl1_reset(adapter); 2734 return err; 2735 } 2736 2737 /** 2738 * atl1_close - Disables a network interface 2739 * @netdev: network interface device structure 2740 * 2741 * Returns 0, this is not allowed to fail 2742 * 2743 * The close entry point is called when an interface is de-activated 2744 * by the OS. The hardware is still under the drivers control, but 2745 * needs to be disabled. A global MAC reset is issued to stop the 2746 * hardware, and all transmit and receive resources are freed. 2747 */ 2748 static int atl1_close(struct net_device *netdev) 2749 { 2750 struct atl1_adapter *adapter = netdev_priv(netdev); 2751 atl1_down(adapter); 2752 atl1_free_ring_resources(adapter); 2753 return 0; 2754 } 2755 2756 #ifdef CONFIG_PM_SLEEP 2757 static int atl1_suspend(struct device *dev) 2758 { 2759 struct pci_dev *pdev = to_pci_dev(dev); 2760 struct net_device *netdev = pci_get_drvdata(pdev); 2761 struct atl1_adapter *adapter = netdev_priv(netdev); 2762 struct atl1_hw *hw = &adapter->hw; 2763 u32 ctrl = 0; 2764 u32 wufc = adapter->wol; 2765 u32 val; 2766 u16 speed; 2767 u16 duplex; 2768 2769 netif_device_detach(netdev); 2770 if (netif_running(netdev)) 2771 atl1_down(adapter); 2772 2773 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); 2774 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); 2775 val = ctrl & BMSR_LSTATUS; 2776 if (val) 2777 wufc &= ~ATLX_WUFC_LNKC; 2778 if (!wufc) 2779 goto disable_wol; 2780 2781 if (val) { 2782 val = atl1_get_speed_and_duplex(hw, &speed, &duplex); 2783 if (val) { 2784 if (netif_msg_ifdown(adapter)) 2785 dev_printk(KERN_DEBUG, &pdev->dev, 2786 "error getting speed/duplex\n"); 2787 goto disable_wol; 2788 } 2789 2790 ctrl = 0; 2791 2792 /* enable magic packet WOL */ 2793 if (wufc & ATLX_WUFC_MAG) 2794 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); 2795 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); 2796 ioread32(hw->hw_addr + REG_WOL_CTRL); 2797 2798 /* configure the mac */ 2799 ctrl = MAC_CTRL_RX_EN; 2800 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 : 2801 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT); 2802 if (duplex == FULL_DUPLEX) 2803 ctrl |= MAC_CTRL_DUPLX; 2804 ctrl |= (((u32)adapter->hw.preamble_len & 2805 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 2806 __atlx_vlan_mode(netdev->features, &ctrl); 2807 if (wufc & ATLX_WUFC_MAG) 2808 ctrl |= MAC_CTRL_BC_EN; 2809 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL); 2810 ioread32(hw->hw_addr + REG_MAC_CTRL); 2811 2812 /* poke the PHY */ 2813 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2814 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 2815 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); 2816 ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2817 } else { 2818 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 2819 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); 2820 ioread32(hw->hw_addr + REG_WOL_CTRL); 2821 iowrite32(0, hw->hw_addr + REG_MAC_CTRL); 2822 ioread32(hw->hw_addr + REG_MAC_CTRL); 2823 hw->phy_configured = false; 2824 } 2825 2826 return 0; 2827 2828 disable_wol: 2829 iowrite32(0, hw->hw_addr + REG_WOL_CTRL); 2830 ioread32(hw->hw_addr + REG_WOL_CTRL); 2831 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2832 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 2833 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); 2834 ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2835 hw->phy_configured = false; 2836 2837 return 0; 2838 } 2839 2840 static int atl1_resume(struct device *dev) 2841 { 2842 struct pci_dev *pdev = to_pci_dev(dev); 2843 struct net_device *netdev = pci_get_drvdata(pdev); 2844 struct atl1_adapter *adapter = netdev_priv(netdev); 2845 2846 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL); 2847 2848 atl1_reset_hw(&adapter->hw); 2849 2850 if (netif_running(netdev)) { 2851 adapter->cmb.cmb->int_stats = 0; 2852 atl1_up(adapter); 2853 } 2854 netif_device_attach(netdev); 2855 2856 return 0; 2857 } 2858 #endif 2859 2860 static SIMPLE_DEV_PM_OPS(atl1_pm_ops, atl1_suspend, atl1_resume); 2861 2862 static void atl1_shutdown(struct pci_dev *pdev) 2863 { 2864 struct net_device *netdev = pci_get_drvdata(pdev); 2865 struct atl1_adapter *adapter = netdev_priv(netdev); 2866 2867 #ifdef CONFIG_PM_SLEEP 2868 atl1_suspend(&pdev->dev); 2869 #endif 2870 pci_wake_from_d3(pdev, adapter->wol); 2871 pci_set_power_state(pdev, PCI_D3hot); 2872 } 2873 2874 #ifdef CONFIG_NET_POLL_CONTROLLER 2875 static void atl1_poll_controller(struct net_device *netdev) 2876 { 2877 disable_irq(netdev->irq); 2878 atl1_intr(netdev->irq, netdev); 2879 enable_irq(netdev->irq); 2880 } 2881 #endif 2882 2883 static const struct net_device_ops atl1_netdev_ops = { 2884 .ndo_open = atl1_open, 2885 .ndo_stop = atl1_close, 2886 .ndo_start_xmit = atl1_xmit_frame, 2887 .ndo_set_rx_mode = atlx_set_multi, 2888 .ndo_validate_addr = eth_validate_addr, 2889 .ndo_set_mac_address = atl1_set_mac, 2890 .ndo_change_mtu = atl1_change_mtu, 2891 .ndo_fix_features = atlx_fix_features, 2892 .ndo_set_features = atlx_set_features, 2893 .ndo_do_ioctl = atlx_ioctl, 2894 .ndo_tx_timeout = atlx_tx_timeout, 2895 #ifdef CONFIG_NET_POLL_CONTROLLER 2896 .ndo_poll_controller = atl1_poll_controller, 2897 #endif 2898 }; 2899 2900 /** 2901 * atl1_probe - Device Initialization Routine 2902 * @pdev: PCI device information struct 2903 * @ent: entry in atl1_pci_tbl 2904 * 2905 * Returns 0 on success, negative on failure 2906 * 2907 * atl1_probe initializes an adapter identified by a pci_dev structure. 2908 * The OS initialization, configuring of the adapter private structure, 2909 * and a hardware reset occur. 2910 */ 2911 static int atl1_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2912 { 2913 struct net_device *netdev; 2914 struct atl1_adapter *adapter; 2915 static int cards_found = 0; 2916 int err; 2917 2918 err = pci_enable_device(pdev); 2919 if (err) 2920 return err; 2921 2922 /* 2923 * The atl1 chip can DMA to 64-bit addresses, but it uses a single 2924 * shared register for the high 32 bits, so only a single, aligned, 2925 * 4 GB physical address range can be used at a time. 2926 * 2927 * Supporting 64-bit DMA on this hardware is more trouble than it's 2928 * worth. It is far easier to limit to 32-bit DMA than update 2929 * various kernel subsystems to support the mechanics required by a 2930 * fixed-high-32-bit system. 2931 */ 2932 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2933 if (err) { 2934 dev_err(&pdev->dev, "no usable DMA configuration\n"); 2935 goto err_dma; 2936 } 2937 /* 2938 * Mark all PCI regions associated with PCI device 2939 * pdev as being reserved by owner atl1_driver_name 2940 */ 2941 err = pci_request_regions(pdev, ATLX_DRIVER_NAME); 2942 if (err) 2943 goto err_request_regions; 2944 2945 /* 2946 * Enables bus-mastering on the device and calls 2947 * pcibios_set_master to do the needed arch specific settings 2948 */ 2949 pci_set_master(pdev); 2950 2951 netdev = alloc_etherdev(sizeof(struct atl1_adapter)); 2952 if (!netdev) { 2953 err = -ENOMEM; 2954 goto err_alloc_etherdev; 2955 } 2956 SET_NETDEV_DEV(netdev, &pdev->dev); 2957 2958 pci_set_drvdata(pdev, netdev); 2959 adapter = netdev_priv(netdev); 2960 adapter->netdev = netdev; 2961 adapter->pdev = pdev; 2962 adapter->hw.back = adapter; 2963 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg); 2964 2965 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0); 2966 if (!adapter->hw.hw_addr) { 2967 err = -EIO; 2968 goto err_pci_iomap; 2969 } 2970 /* get device revision number */ 2971 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr + 2972 (REG_MASTER_CTRL + 2)); 2973 if (netif_msg_probe(adapter)) 2974 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION); 2975 2976 /* set default ring resource counts */ 2977 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD; 2978 adapter->tpd_ring.count = ATL1_DEFAULT_TPD; 2979 2980 adapter->mii.dev = netdev; 2981 adapter->mii.mdio_read = mdio_read; 2982 adapter->mii.mdio_write = mdio_write; 2983 adapter->mii.phy_id_mask = 0x1f; 2984 adapter->mii.reg_num_mask = 0x1f; 2985 2986 netdev->netdev_ops = &atl1_netdev_ops; 2987 netdev->watchdog_timeo = 5 * HZ; 2988 netif_napi_add(netdev, &adapter->napi, atl1_rings_clean, 64); 2989 2990 netdev->ethtool_ops = &atl1_ethtool_ops; 2991 adapter->bd_number = cards_found; 2992 2993 /* setup the private structure */ 2994 err = atl1_sw_init(adapter); 2995 if (err) 2996 goto err_common; 2997 2998 netdev->features = NETIF_F_HW_CSUM; 2999 netdev->features |= NETIF_F_SG; 3000 netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 3001 3002 netdev->hw_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_TSO | 3003 NETIF_F_HW_VLAN_CTAG_RX; 3004 3005 /* is this valid? see atl1_setup_mac_ctrl() */ 3006 netdev->features |= NETIF_F_RXCSUM; 3007 3008 /* MTU range: 42 - 10218 */ 3009 netdev->min_mtu = ETH_ZLEN - (ETH_HLEN + VLAN_HLEN); 3010 netdev->max_mtu = MAX_JUMBO_FRAME_SIZE - 3011 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); 3012 3013 /* 3014 * patch for some L1 of old version, 3015 * the final version of L1 may not need these 3016 * patches 3017 */ 3018 /* atl1_pcie_patch(adapter); */ 3019 3020 /* really reset GPHY core */ 3021 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); 3022 3023 /* 3024 * reset the controller to 3025 * put the device in a known good starting state 3026 */ 3027 if (atl1_reset_hw(&adapter->hw)) { 3028 err = -EIO; 3029 goto err_common; 3030 } 3031 3032 /* copy the MAC address out of the EEPROM */ 3033 if (atl1_read_mac_addr(&adapter->hw)) { 3034 /* mark random mac */ 3035 netdev->addr_assign_type = NET_ADDR_RANDOM; 3036 } 3037 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); 3038 3039 if (!is_valid_ether_addr(netdev->dev_addr)) { 3040 err = -EIO; 3041 goto err_common; 3042 } 3043 3044 atl1_check_options(adapter); 3045 3046 /* pre-init the MAC, and setup link */ 3047 err = atl1_init_hw(&adapter->hw); 3048 if (err) { 3049 err = -EIO; 3050 goto err_common; 3051 } 3052 3053 atl1_pcie_patch(adapter); 3054 /* assume we have no link for now */ 3055 netif_carrier_off(netdev); 3056 3057 timer_setup(&adapter->phy_config_timer, atl1_phy_config, 0); 3058 adapter->phy_timer_pending = false; 3059 3060 INIT_WORK(&adapter->reset_dev_task, atl1_reset_dev_task); 3061 3062 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task); 3063 3064 err = register_netdev(netdev); 3065 if (err) 3066 goto err_common; 3067 3068 cards_found++; 3069 atl1_via_workaround(adapter); 3070 return 0; 3071 3072 err_common: 3073 pci_iounmap(pdev, adapter->hw.hw_addr); 3074 err_pci_iomap: 3075 free_netdev(netdev); 3076 err_alloc_etherdev: 3077 pci_release_regions(pdev); 3078 err_dma: 3079 err_request_regions: 3080 pci_disable_device(pdev); 3081 return err; 3082 } 3083 3084 /** 3085 * atl1_remove - Device Removal Routine 3086 * @pdev: PCI device information struct 3087 * 3088 * atl1_remove is called by the PCI subsystem to alert the driver 3089 * that it should release a PCI device. The could be caused by a 3090 * Hot-Plug event, or because the driver is going to be removed from 3091 * memory. 3092 */ 3093 static void atl1_remove(struct pci_dev *pdev) 3094 { 3095 struct net_device *netdev = pci_get_drvdata(pdev); 3096 struct atl1_adapter *adapter; 3097 /* Device not available. Return. */ 3098 if (!netdev) 3099 return; 3100 3101 adapter = netdev_priv(netdev); 3102 3103 /* 3104 * Some atl1 boards lack persistent storage for their MAC, and get it 3105 * from the BIOS during POST. If we've been messing with the MAC 3106 * address, we need to save the permanent one. 3107 */ 3108 if (!ether_addr_equal_unaligned(adapter->hw.mac_addr, 3109 adapter->hw.perm_mac_addr)) { 3110 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, 3111 ETH_ALEN); 3112 atl1_set_mac_addr(&adapter->hw); 3113 } 3114 3115 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); 3116 unregister_netdev(netdev); 3117 pci_iounmap(pdev, adapter->hw.hw_addr); 3118 pci_release_regions(pdev); 3119 free_netdev(netdev); 3120 pci_disable_device(pdev); 3121 } 3122 3123 static struct pci_driver atl1_driver = { 3124 .name = ATLX_DRIVER_NAME, 3125 .id_table = atl1_pci_tbl, 3126 .probe = atl1_probe, 3127 .remove = atl1_remove, 3128 .shutdown = atl1_shutdown, 3129 .driver.pm = &atl1_pm_ops, 3130 }; 3131 3132 struct atl1_stats { 3133 char stat_string[ETH_GSTRING_LEN]; 3134 int sizeof_stat; 3135 int stat_offset; 3136 }; 3137 3138 #define ATL1_STAT(m) \ 3139 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m) 3140 3141 static struct atl1_stats atl1_gstrings_stats[] = { 3142 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)}, 3143 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)}, 3144 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)}, 3145 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)}, 3146 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)}, 3147 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)}, 3148 {"multicast", ATL1_STAT(soft_stats.multicast)}, 3149 {"collisions", ATL1_STAT(soft_stats.collisions)}, 3150 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)}, 3151 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)}, 3152 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)}, 3153 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)}, 3154 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)}, 3155 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)}, 3156 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)}, 3157 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)}, 3158 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)}, 3159 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)}, 3160 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)}, 3161 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)}, 3162 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)}, 3163 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)}, 3164 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)}, 3165 {"tx_underrun", ATL1_STAT(soft_stats.tx_underrun)}, 3166 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)}, 3167 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)}, 3168 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)}, 3169 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)}, 3170 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)} 3171 }; 3172 3173 static void atl1_get_ethtool_stats(struct net_device *netdev, 3174 struct ethtool_stats *stats, u64 *data) 3175 { 3176 struct atl1_adapter *adapter = netdev_priv(netdev); 3177 int i; 3178 char *p; 3179 3180 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) { 3181 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset; 3182 data[i] = (atl1_gstrings_stats[i].sizeof_stat == 3183 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 3184 } 3185 3186 } 3187 3188 static int atl1_get_sset_count(struct net_device *netdev, int sset) 3189 { 3190 switch (sset) { 3191 case ETH_SS_STATS: 3192 return ARRAY_SIZE(atl1_gstrings_stats); 3193 default: 3194 return -EOPNOTSUPP; 3195 } 3196 } 3197 3198 static int atl1_get_link_ksettings(struct net_device *netdev, 3199 struct ethtool_link_ksettings *cmd) 3200 { 3201 struct atl1_adapter *adapter = netdev_priv(netdev); 3202 struct atl1_hw *hw = &adapter->hw; 3203 u32 supported, advertising; 3204 3205 supported = (SUPPORTED_10baseT_Half | 3206 SUPPORTED_10baseT_Full | 3207 SUPPORTED_100baseT_Half | 3208 SUPPORTED_100baseT_Full | 3209 SUPPORTED_1000baseT_Full | 3210 SUPPORTED_Autoneg | SUPPORTED_TP); 3211 advertising = ADVERTISED_TP; 3212 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3213 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3214 advertising |= ADVERTISED_Autoneg; 3215 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) { 3216 advertising |= ADVERTISED_Autoneg; 3217 advertising |= 3218 (ADVERTISED_10baseT_Half | 3219 ADVERTISED_10baseT_Full | 3220 ADVERTISED_100baseT_Half | 3221 ADVERTISED_100baseT_Full | 3222 ADVERTISED_1000baseT_Full); 3223 } else 3224 advertising |= (ADVERTISED_1000baseT_Full); 3225 } 3226 cmd->base.port = PORT_TP; 3227 cmd->base.phy_address = 0; 3228 3229 if (netif_carrier_ok(adapter->netdev)) { 3230 u16 link_speed, link_duplex; 3231 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex); 3232 cmd->base.speed = link_speed; 3233 if (link_duplex == FULL_DUPLEX) 3234 cmd->base.duplex = DUPLEX_FULL; 3235 else 3236 cmd->base.duplex = DUPLEX_HALF; 3237 } else { 3238 cmd->base.speed = SPEED_UNKNOWN; 3239 cmd->base.duplex = DUPLEX_UNKNOWN; 3240 } 3241 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3242 hw->media_type == MEDIA_TYPE_1000M_FULL) 3243 cmd->base.autoneg = AUTONEG_ENABLE; 3244 else 3245 cmd->base.autoneg = AUTONEG_DISABLE; 3246 3247 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3248 supported); 3249 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3250 advertising); 3251 3252 return 0; 3253 } 3254 3255 static int atl1_set_link_ksettings(struct net_device *netdev, 3256 const struct ethtool_link_ksettings *cmd) 3257 { 3258 struct atl1_adapter *adapter = netdev_priv(netdev); 3259 struct atl1_hw *hw = &adapter->hw; 3260 u16 phy_data; 3261 int ret_val = 0; 3262 u16 old_media_type = hw->media_type; 3263 3264 if (netif_running(adapter->netdev)) { 3265 if (netif_msg_link(adapter)) 3266 dev_dbg(&adapter->pdev->dev, 3267 "ethtool shutting down adapter\n"); 3268 atl1_down(adapter); 3269 } 3270 3271 if (cmd->base.autoneg == AUTONEG_ENABLE) 3272 hw->media_type = MEDIA_TYPE_AUTO_SENSOR; 3273 else { 3274 u32 speed = cmd->base.speed; 3275 if (speed == SPEED_1000) { 3276 if (cmd->base.duplex != DUPLEX_FULL) { 3277 if (netif_msg_link(adapter)) 3278 dev_warn(&adapter->pdev->dev, 3279 "1000M half is invalid\n"); 3280 ret_val = -EINVAL; 3281 goto exit_sset; 3282 } 3283 hw->media_type = MEDIA_TYPE_1000M_FULL; 3284 } else if (speed == SPEED_100) { 3285 if (cmd->base.duplex == DUPLEX_FULL) 3286 hw->media_type = MEDIA_TYPE_100M_FULL; 3287 else 3288 hw->media_type = MEDIA_TYPE_100M_HALF; 3289 } else { 3290 if (cmd->base.duplex == DUPLEX_FULL) 3291 hw->media_type = MEDIA_TYPE_10M_FULL; 3292 else 3293 hw->media_type = MEDIA_TYPE_10M_HALF; 3294 } 3295 } 3296 3297 if (atl1_phy_setup_autoneg_adv(hw)) { 3298 ret_val = -EINVAL; 3299 if (netif_msg_link(adapter)) 3300 dev_warn(&adapter->pdev->dev, 3301 "invalid ethtool speed/duplex setting\n"); 3302 goto exit_sset; 3303 } 3304 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3305 hw->media_type == MEDIA_TYPE_1000M_FULL) 3306 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 3307 else { 3308 switch (hw->media_type) { 3309 case MEDIA_TYPE_100M_FULL: 3310 phy_data = 3311 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | 3312 MII_CR_RESET; 3313 break; 3314 case MEDIA_TYPE_100M_HALF: 3315 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 3316 break; 3317 case MEDIA_TYPE_10M_FULL: 3318 phy_data = 3319 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 3320 break; 3321 default: 3322 /* MEDIA_TYPE_10M_HALF: */ 3323 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 3324 break; 3325 } 3326 } 3327 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 3328 exit_sset: 3329 if (ret_val) 3330 hw->media_type = old_media_type; 3331 3332 if (netif_running(adapter->netdev)) { 3333 if (netif_msg_link(adapter)) 3334 dev_dbg(&adapter->pdev->dev, 3335 "ethtool starting adapter\n"); 3336 atl1_up(adapter); 3337 } else if (!ret_val) { 3338 if (netif_msg_link(adapter)) 3339 dev_dbg(&adapter->pdev->dev, 3340 "ethtool resetting adapter\n"); 3341 atl1_reset(adapter); 3342 } 3343 return ret_val; 3344 } 3345 3346 static void atl1_get_drvinfo(struct net_device *netdev, 3347 struct ethtool_drvinfo *drvinfo) 3348 { 3349 struct atl1_adapter *adapter = netdev_priv(netdev); 3350 3351 strlcpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver)); 3352 strlcpy(drvinfo->version, ATLX_DRIVER_VERSION, 3353 sizeof(drvinfo->version)); 3354 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 3355 sizeof(drvinfo->bus_info)); 3356 } 3357 3358 static void atl1_get_wol(struct net_device *netdev, 3359 struct ethtool_wolinfo *wol) 3360 { 3361 struct atl1_adapter *adapter = netdev_priv(netdev); 3362 3363 wol->supported = WAKE_MAGIC; 3364 wol->wolopts = 0; 3365 if (adapter->wol & ATLX_WUFC_MAG) 3366 wol->wolopts |= WAKE_MAGIC; 3367 } 3368 3369 static int atl1_set_wol(struct net_device *netdev, 3370 struct ethtool_wolinfo *wol) 3371 { 3372 struct atl1_adapter *adapter = netdev_priv(netdev); 3373 3374 if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | 3375 WAKE_ARP | WAKE_MAGICSECURE)) 3376 return -EOPNOTSUPP; 3377 adapter->wol = 0; 3378 if (wol->wolopts & WAKE_MAGIC) 3379 adapter->wol |= ATLX_WUFC_MAG; 3380 3381 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 3382 3383 return 0; 3384 } 3385 3386 static u32 atl1_get_msglevel(struct net_device *netdev) 3387 { 3388 struct atl1_adapter *adapter = netdev_priv(netdev); 3389 return adapter->msg_enable; 3390 } 3391 3392 static void atl1_set_msglevel(struct net_device *netdev, u32 value) 3393 { 3394 struct atl1_adapter *adapter = netdev_priv(netdev); 3395 adapter->msg_enable = value; 3396 } 3397 3398 static int atl1_get_regs_len(struct net_device *netdev) 3399 { 3400 return ATL1_REG_COUNT * sizeof(u32); 3401 } 3402 3403 static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs, 3404 void *p) 3405 { 3406 struct atl1_adapter *adapter = netdev_priv(netdev); 3407 struct atl1_hw *hw = &adapter->hw; 3408 unsigned int i; 3409 u32 *regbuf = p; 3410 3411 for (i = 0; i < ATL1_REG_COUNT; i++) { 3412 /* 3413 * This switch statement avoids reserved regions 3414 * of register space. 3415 */ 3416 switch (i) { 3417 case 6 ... 9: 3418 case 14: 3419 case 29 ... 31: 3420 case 34 ... 63: 3421 case 75 ... 127: 3422 case 136 ... 1023: 3423 case 1027 ... 1087: 3424 case 1091 ... 1151: 3425 case 1194 ... 1195: 3426 case 1200 ... 1201: 3427 case 1206 ... 1213: 3428 case 1216 ... 1279: 3429 case 1290 ... 1311: 3430 case 1323 ... 1343: 3431 case 1358 ... 1359: 3432 case 1368 ... 1375: 3433 case 1378 ... 1383: 3434 case 1388 ... 1391: 3435 case 1393 ... 1395: 3436 case 1402 ... 1403: 3437 case 1410 ... 1471: 3438 case 1522 ... 1535: 3439 /* reserved region; don't read it */ 3440 regbuf[i] = 0; 3441 break; 3442 default: 3443 /* unreserved region */ 3444 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32))); 3445 } 3446 } 3447 } 3448 3449 static void atl1_get_ringparam(struct net_device *netdev, 3450 struct ethtool_ringparam *ring) 3451 { 3452 struct atl1_adapter *adapter = netdev_priv(netdev); 3453 struct atl1_tpd_ring *txdr = &adapter->tpd_ring; 3454 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring; 3455 3456 ring->rx_max_pending = ATL1_MAX_RFD; 3457 ring->tx_max_pending = ATL1_MAX_TPD; 3458 ring->rx_pending = rxdr->count; 3459 ring->tx_pending = txdr->count; 3460 } 3461 3462 static int atl1_set_ringparam(struct net_device *netdev, 3463 struct ethtool_ringparam *ring) 3464 { 3465 struct atl1_adapter *adapter = netdev_priv(netdev); 3466 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring; 3467 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring; 3468 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring; 3469 3470 struct atl1_tpd_ring tpd_old, tpd_new; 3471 struct atl1_rfd_ring rfd_old, rfd_new; 3472 struct atl1_rrd_ring rrd_old, rrd_new; 3473 struct atl1_ring_header rhdr_old, rhdr_new; 3474 struct atl1_smb smb; 3475 struct atl1_cmb cmb; 3476 int err; 3477 3478 tpd_old = adapter->tpd_ring; 3479 rfd_old = adapter->rfd_ring; 3480 rrd_old = adapter->rrd_ring; 3481 rhdr_old = adapter->ring_header; 3482 3483 if (netif_running(adapter->netdev)) 3484 atl1_down(adapter); 3485 3486 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD); 3487 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD : 3488 rfdr->count; 3489 rfdr->count = (rfdr->count + 3) & ~3; 3490 rrdr->count = rfdr->count; 3491 3492 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD); 3493 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD : 3494 tpdr->count; 3495 tpdr->count = (tpdr->count + 3) & ~3; 3496 3497 if (netif_running(adapter->netdev)) { 3498 /* try to get new resources before deleting old */ 3499 err = atl1_setup_ring_resources(adapter); 3500 if (err) 3501 goto err_setup_ring; 3502 3503 /* 3504 * save the new, restore the old in order to free it, 3505 * then restore the new back again 3506 */ 3507 3508 rfd_new = adapter->rfd_ring; 3509 rrd_new = adapter->rrd_ring; 3510 tpd_new = adapter->tpd_ring; 3511 rhdr_new = adapter->ring_header; 3512 adapter->rfd_ring = rfd_old; 3513 adapter->rrd_ring = rrd_old; 3514 adapter->tpd_ring = tpd_old; 3515 adapter->ring_header = rhdr_old; 3516 /* 3517 * Save SMB and CMB, since atl1_free_ring_resources 3518 * will clear them. 3519 */ 3520 smb = adapter->smb; 3521 cmb = adapter->cmb; 3522 atl1_free_ring_resources(adapter); 3523 adapter->rfd_ring = rfd_new; 3524 adapter->rrd_ring = rrd_new; 3525 adapter->tpd_ring = tpd_new; 3526 adapter->ring_header = rhdr_new; 3527 adapter->smb = smb; 3528 adapter->cmb = cmb; 3529 3530 err = atl1_up(adapter); 3531 if (err) 3532 return err; 3533 } 3534 return 0; 3535 3536 err_setup_ring: 3537 adapter->rfd_ring = rfd_old; 3538 adapter->rrd_ring = rrd_old; 3539 adapter->tpd_ring = tpd_old; 3540 adapter->ring_header = rhdr_old; 3541 atl1_up(adapter); 3542 return err; 3543 } 3544 3545 static void atl1_get_pauseparam(struct net_device *netdev, 3546 struct ethtool_pauseparam *epause) 3547 { 3548 struct atl1_adapter *adapter = netdev_priv(netdev); 3549 struct atl1_hw *hw = &adapter->hw; 3550 3551 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3552 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3553 epause->autoneg = AUTONEG_ENABLE; 3554 } else { 3555 epause->autoneg = AUTONEG_DISABLE; 3556 } 3557 epause->rx_pause = 1; 3558 epause->tx_pause = 1; 3559 } 3560 3561 static int atl1_set_pauseparam(struct net_device *netdev, 3562 struct ethtool_pauseparam *epause) 3563 { 3564 struct atl1_adapter *adapter = netdev_priv(netdev); 3565 struct atl1_hw *hw = &adapter->hw; 3566 3567 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3568 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3569 epause->autoneg = AUTONEG_ENABLE; 3570 } else { 3571 epause->autoneg = AUTONEG_DISABLE; 3572 } 3573 3574 epause->rx_pause = 1; 3575 epause->tx_pause = 1; 3576 3577 return 0; 3578 } 3579 3580 static void atl1_get_strings(struct net_device *netdev, u32 stringset, 3581 u8 *data) 3582 { 3583 u8 *p = data; 3584 int i; 3585 3586 switch (stringset) { 3587 case ETH_SS_STATS: 3588 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) { 3589 memcpy(p, atl1_gstrings_stats[i].stat_string, 3590 ETH_GSTRING_LEN); 3591 p += ETH_GSTRING_LEN; 3592 } 3593 break; 3594 } 3595 } 3596 3597 static int atl1_nway_reset(struct net_device *netdev) 3598 { 3599 struct atl1_adapter *adapter = netdev_priv(netdev); 3600 struct atl1_hw *hw = &adapter->hw; 3601 3602 if (netif_running(netdev)) { 3603 u16 phy_data; 3604 atl1_down(adapter); 3605 3606 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3607 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3608 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 3609 } else { 3610 switch (hw->media_type) { 3611 case MEDIA_TYPE_100M_FULL: 3612 phy_data = MII_CR_FULL_DUPLEX | 3613 MII_CR_SPEED_100 | MII_CR_RESET; 3614 break; 3615 case MEDIA_TYPE_100M_HALF: 3616 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 3617 break; 3618 case MEDIA_TYPE_10M_FULL: 3619 phy_data = MII_CR_FULL_DUPLEX | 3620 MII_CR_SPEED_10 | MII_CR_RESET; 3621 break; 3622 default: 3623 /* MEDIA_TYPE_10M_HALF */ 3624 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 3625 } 3626 } 3627 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 3628 atl1_up(adapter); 3629 } 3630 return 0; 3631 } 3632 3633 static const struct ethtool_ops atl1_ethtool_ops = { 3634 .get_drvinfo = atl1_get_drvinfo, 3635 .get_wol = atl1_get_wol, 3636 .set_wol = atl1_set_wol, 3637 .get_msglevel = atl1_get_msglevel, 3638 .set_msglevel = atl1_set_msglevel, 3639 .get_regs_len = atl1_get_regs_len, 3640 .get_regs = atl1_get_regs, 3641 .get_ringparam = atl1_get_ringparam, 3642 .set_ringparam = atl1_set_ringparam, 3643 .get_pauseparam = atl1_get_pauseparam, 3644 .set_pauseparam = atl1_set_pauseparam, 3645 .get_link = ethtool_op_get_link, 3646 .get_strings = atl1_get_strings, 3647 .nway_reset = atl1_nway_reset, 3648 .get_ethtool_stats = atl1_get_ethtool_stats, 3649 .get_sset_count = atl1_get_sset_count, 3650 .get_link_ksettings = atl1_get_link_ksettings, 3651 .set_link_ksettings = atl1_set_link_ksettings, 3652 }; 3653 3654 module_pci_driver(atl1_driver); 3655