1 /* 2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. 3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com> 4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com> 5 * 6 * Derived from Intel e1000 driver 7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the Free 11 * Software Foundation; either version 2 of the License, or (at your option) 12 * any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program; if not, write to the Free Software Foundation, Inc., 59 21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 22 * 23 * The full GNU General Public License is included in this distribution in the 24 * file called COPYING. 25 * 26 * Contact Information: 27 * Xiong Huang <xiong.huang@atheros.com> 28 * Jie Yang <jie.yang@atheros.com> 29 * Chris Snook <csnook@redhat.com> 30 * Jay Cliburn <jcliburn@gmail.com> 31 * 32 * This version is adapted from the Attansic reference driver. 33 * 34 * TODO: 35 * Add more ethtool functions. 36 * Fix abstruse irq enable/disable condition described here: 37 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2 38 * 39 * NEEDS TESTING: 40 * VLAN 41 * multicast 42 * promiscuous mode 43 * interrupt coalescing 44 * SMP torture testing 45 */ 46 47 #include <linux/atomic.h> 48 #include <asm/byteorder.h> 49 50 #include <linux/compiler.h> 51 #include <linux/crc32.h> 52 #include <linux/delay.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/etherdevice.h> 55 #include <linux/hardirq.h> 56 #include <linux/if_ether.h> 57 #include <linux/if_vlan.h> 58 #include <linux/in.h> 59 #include <linux/interrupt.h> 60 #include <linux/ip.h> 61 #include <linux/irqflags.h> 62 #include <linux/irqreturn.h> 63 #include <linux/jiffies.h> 64 #include <linux/mii.h> 65 #include <linux/module.h> 66 #include <linux/net.h> 67 #include <linux/netdevice.h> 68 #include <linux/pci.h> 69 #include <linux/pci_ids.h> 70 #include <linux/pm.h> 71 #include <linux/skbuff.h> 72 #include <linux/slab.h> 73 #include <linux/spinlock.h> 74 #include <linux/string.h> 75 #include <linux/tcp.h> 76 #include <linux/timer.h> 77 #include <linux/types.h> 78 #include <linux/workqueue.h> 79 80 #include <net/checksum.h> 81 82 #include "atl1.h" 83 84 #define ATLX_DRIVER_VERSION "2.1.3" 85 MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, " 86 "Chris Snook <csnook@redhat.com>, " 87 "Jay Cliburn <jcliburn@gmail.com>"); 88 MODULE_LICENSE("GPL"); 89 MODULE_VERSION(ATLX_DRIVER_VERSION); 90 91 /* Temporary hack for merging atl1 and atl2 */ 92 #include "atlx.c" 93 94 static const struct ethtool_ops atl1_ethtool_ops; 95 96 /* 97 * This is the only thing that needs to be changed to adjust the 98 * maximum number of ports that the driver can manage. 99 */ 100 #define ATL1_MAX_NIC 4 101 102 #define OPTION_UNSET -1 103 #define OPTION_DISABLED 0 104 #define OPTION_ENABLED 1 105 106 #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET } 107 108 /* 109 * Interrupt Moderate Timer in units of 2 us 110 * 111 * Valid Range: 10-65535 112 * 113 * Default Value: 100 (200us) 114 */ 115 static int int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT; 116 static unsigned int num_int_mod_timer; 117 module_param_array_named(int_mod_timer, int_mod_timer, int, 118 &num_int_mod_timer, 0); 119 MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer"); 120 121 #define DEFAULT_INT_MOD_CNT 100 /* 200us */ 122 #define MAX_INT_MOD_CNT 65000 123 #define MIN_INT_MOD_CNT 50 124 125 struct atl1_option { 126 enum { enable_option, range_option, list_option } type; 127 char *name; 128 char *err; 129 int def; 130 union { 131 struct { /* range_option info */ 132 int min; 133 int max; 134 } r; 135 struct { /* list_option info */ 136 int nr; 137 struct atl1_opt_list { 138 int i; 139 char *str; 140 } *p; 141 } l; 142 } arg; 143 }; 144 145 static int atl1_validate_option(int *value, struct atl1_option *opt, 146 struct pci_dev *pdev) 147 { 148 if (*value == OPTION_UNSET) { 149 *value = opt->def; 150 return 0; 151 } 152 153 switch (opt->type) { 154 case enable_option: 155 switch (*value) { 156 case OPTION_ENABLED: 157 dev_info(&pdev->dev, "%s enabled\n", opt->name); 158 return 0; 159 case OPTION_DISABLED: 160 dev_info(&pdev->dev, "%s disabled\n", opt->name); 161 return 0; 162 } 163 break; 164 case range_option: 165 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 166 dev_info(&pdev->dev, "%s set to %i\n", opt->name, 167 *value); 168 return 0; 169 } 170 break; 171 case list_option:{ 172 int i; 173 struct atl1_opt_list *ent; 174 175 for (i = 0; i < opt->arg.l.nr; i++) { 176 ent = &opt->arg.l.p[i]; 177 if (*value == ent->i) { 178 if (ent->str[0] != '\0') 179 dev_info(&pdev->dev, "%s\n", 180 ent->str); 181 return 0; 182 } 183 } 184 } 185 break; 186 187 default: 188 break; 189 } 190 191 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n", 192 opt->name, *value, opt->err); 193 *value = opt->def; 194 return -1; 195 } 196 197 /** 198 * atl1_check_options - Range Checking for Command Line Parameters 199 * @adapter: board private structure 200 * 201 * This routine checks all command line parameters for valid user 202 * input. If an invalid value is given, or if no user specified 203 * value exists, a default value is used. The final value is stored 204 * in a variable in the adapter structure. 205 */ 206 static void atl1_check_options(struct atl1_adapter *adapter) 207 { 208 struct pci_dev *pdev = adapter->pdev; 209 int bd = adapter->bd_number; 210 if (bd >= ATL1_MAX_NIC) { 211 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd); 212 dev_notice(&pdev->dev, "using defaults for all values\n"); 213 } 214 { /* Interrupt Moderate Timer */ 215 struct atl1_option opt = { 216 .type = range_option, 217 .name = "Interrupt Moderator Timer", 218 .err = "using default of " 219 __MODULE_STRING(DEFAULT_INT_MOD_CNT), 220 .def = DEFAULT_INT_MOD_CNT, 221 .arg = {.r = {.min = MIN_INT_MOD_CNT, 222 .max = MAX_INT_MOD_CNT} } 223 }; 224 int val; 225 if (num_int_mod_timer > bd) { 226 val = int_mod_timer[bd]; 227 atl1_validate_option(&val, &opt, pdev); 228 adapter->imt = (u16) val; 229 } else 230 adapter->imt = (u16) (opt.def); 231 } 232 } 233 234 /* 235 * atl1_pci_tbl - PCI Device ID Table 236 */ 237 static const struct pci_device_id atl1_pci_tbl[] = { 238 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)}, 239 /* required last entry */ 240 {0,} 241 }; 242 MODULE_DEVICE_TABLE(pci, atl1_pci_tbl); 243 244 static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | 245 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP; 246 247 static int debug = -1; 248 module_param(debug, int, 0); 249 MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)"); 250 251 /* 252 * Reset the transmit and receive units; mask and clear all interrupts. 253 * hw - Struct containing variables accessed by shared code 254 * return : 0 or idle status (if error) 255 */ 256 static s32 atl1_reset_hw(struct atl1_hw *hw) 257 { 258 struct pci_dev *pdev = hw->back->pdev; 259 struct atl1_adapter *adapter = hw->back; 260 u32 icr; 261 int i; 262 263 /* 264 * Clear Interrupt mask to stop board from generating 265 * interrupts & Clear any pending interrupt events 266 */ 267 /* 268 * atlx_irq_disable(adapter); 269 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR); 270 */ 271 272 /* 273 * Issue Soft Reset to the MAC. This will reset the chip's 274 * transmit, receive, DMA. It will not effect 275 * the current PCI configuration. The global reset bit is self- 276 * clearing, and should clear within a microsecond. 277 */ 278 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL); 279 ioread32(hw->hw_addr + REG_MASTER_CTRL); 280 281 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE); 282 ioread16(hw->hw_addr + REG_PHY_ENABLE); 283 284 /* delay about 1ms */ 285 msleep(1); 286 287 /* Wait at least 10ms for All module to be Idle */ 288 for (i = 0; i < 10; i++) { 289 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS); 290 if (!icr) 291 break; 292 /* delay 1 ms */ 293 msleep(1); 294 /* FIXME: still the right way to do this? */ 295 cpu_relax(); 296 } 297 298 if (icr) { 299 if (netif_msg_hw(adapter)) 300 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr); 301 return icr; 302 } 303 304 return 0; 305 } 306 307 /* function about EEPROM 308 * 309 * check_eeprom_exist 310 * return 0 if eeprom exist 311 */ 312 static int atl1_check_eeprom_exist(struct atl1_hw *hw) 313 { 314 u32 value; 315 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); 316 if (value & SPI_FLASH_CTRL_EN_VPD) { 317 value &= ~SPI_FLASH_CTRL_EN_VPD; 318 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); 319 } 320 321 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST); 322 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 323 } 324 325 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value) 326 { 327 int i; 328 u32 control; 329 330 if (offset & 3) 331 /* address do not align */ 332 return false; 333 334 iowrite32(0, hw->hw_addr + REG_VPD_DATA); 335 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 336 iowrite32(control, hw->hw_addr + REG_VPD_CAP); 337 ioread32(hw->hw_addr + REG_VPD_CAP); 338 339 for (i = 0; i < 10; i++) { 340 msleep(2); 341 control = ioread32(hw->hw_addr + REG_VPD_CAP); 342 if (control & VPD_CAP_VPD_FLAG) 343 break; 344 } 345 if (control & VPD_CAP_VPD_FLAG) { 346 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA); 347 return true; 348 } 349 /* timeout */ 350 return false; 351 } 352 353 /* 354 * Reads the value from a PHY register 355 * hw - Struct containing variables accessed by shared code 356 * reg_addr - address of the PHY register to read 357 */ 358 static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data) 359 { 360 u32 val; 361 int i; 362 363 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 364 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 << 365 MDIO_CLK_SEL_SHIFT; 366 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); 367 ioread32(hw->hw_addr + REG_MDIO_CTRL); 368 369 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 370 udelay(2); 371 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); 372 if (!(val & (MDIO_START | MDIO_BUSY))) 373 break; 374 } 375 if (!(val & (MDIO_START | MDIO_BUSY))) { 376 *phy_data = (u16) val; 377 return 0; 378 } 379 return ATLX_ERR_PHY; 380 } 381 382 #define CUSTOM_SPI_CS_SETUP 2 383 #define CUSTOM_SPI_CLK_HI 2 384 #define CUSTOM_SPI_CLK_LO 2 385 #define CUSTOM_SPI_CS_HOLD 2 386 #define CUSTOM_SPI_CS_HI 3 387 388 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf) 389 { 390 int i; 391 u32 value; 392 393 iowrite32(0, hw->hw_addr + REG_SPI_DATA); 394 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR); 395 396 value = SPI_FLASH_CTRL_WAIT_READY | 397 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << 398 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI & 399 SPI_FLASH_CTRL_CLK_HI_MASK) << 400 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO & 401 SPI_FLASH_CTRL_CLK_LO_MASK) << 402 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD & 403 SPI_FLASH_CTRL_CS_HOLD_MASK) << 404 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI & 405 SPI_FLASH_CTRL_CS_HI_MASK) << 406 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) << 407 SPI_FLASH_CTRL_INS_SHIFT; 408 409 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); 410 411 value |= SPI_FLASH_CTRL_START; 412 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); 413 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); 414 415 for (i = 0; i < 10; i++) { 416 msleep(1); 417 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); 418 if (!(value & SPI_FLASH_CTRL_START)) 419 break; 420 } 421 422 if (value & SPI_FLASH_CTRL_START) 423 return false; 424 425 *buf = ioread32(hw->hw_addr + REG_SPI_DATA); 426 427 return true; 428 } 429 430 /* 431 * get_permanent_address 432 * return 0 if get valid mac address, 433 */ 434 static int atl1_get_permanent_address(struct atl1_hw *hw) 435 { 436 u32 addr[2]; 437 u32 i, control; 438 u16 reg; 439 u8 eth_addr[ETH_ALEN]; 440 bool key_valid; 441 442 if (is_valid_ether_addr(hw->perm_mac_addr)) 443 return 0; 444 445 /* init */ 446 addr[0] = addr[1] = 0; 447 448 if (!atl1_check_eeprom_exist(hw)) { 449 reg = 0; 450 key_valid = false; 451 /* Read out all EEPROM content */ 452 i = 0; 453 while (1) { 454 if (atl1_read_eeprom(hw, i + 0x100, &control)) { 455 if (key_valid) { 456 if (reg == REG_MAC_STA_ADDR) 457 addr[0] = control; 458 else if (reg == (REG_MAC_STA_ADDR + 4)) 459 addr[1] = control; 460 key_valid = false; 461 } else if ((control & 0xff) == 0x5A) { 462 key_valid = true; 463 reg = (u16) (control >> 16); 464 } else 465 break; 466 } else 467 /* read error */ 468 break; 469 i += 4; 470 } 471 472 *(u32 *) ð_addr[2] = swab32(addr[0]); 473 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); 474 if (is_valid_ether_addr(eth_addr)) { 475 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 476 return 0; 477 } 478 } 479 480 /* see if SPI FLAGS exist ? */ 481 addr[0] = addr[1] = 0; 482 reg = 0; 483 key_valid = false; 484 i = 0; 485 while (1) { 486 if (atl1_spi_read(hw, i + 0x1f000, &control)) { 487 if (key_valid) { 488 if (reg == REG_MAC_STA_ADDR) 489 addr[0] = control; 490 else if (reg == (REG_MAC_STA_ADDR + 4)) 491 addr[1] = control; 492 key_valid = false; 493 } else if ((control & 0xff) == 0x5A) { 494 key_valid = true; 495 reg = (u16) (control >> 16); 496 } else 497 /* data end */ 498 break; 499 } else 500 /* read error */ 501 break; 502 i += 4; 503 } 504 505 *(u32 *) ð_addr[2] = swab32(addr[0]); 506 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); 507 if (is_valid_ether_addr(eth_addr)) { 508 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 509 return 0; 510 } 511 512 /* 513 * On some motherboards, the MAC address is written by the 514 * BIOS directly to the MAC register during POST, and is 515 * not stored in eeprom. If all else thus far has failed 516 * to fetch the permanent MAC address, try reading it directly. 517 */ 518 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR); 519 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4)); 520 *(u32 *) ð_addr[2] = swab32(addr[0]); 521 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); 522 if (is_valid_ether_addr(eth_addr)) { 523 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 524 return 0; 525 } 526 527 return 1; 528 } 529 530 /* 531 * Reads the adapter's MAC address from the EEPROM 532 * hw - Struct containing variables accessed by shared code 533 */ 534 static s32 atl1_read_mac_addr(struct atl1_hw *hw) 535 { 536 s32 ret = 0; 537 u16 i; 538 539 if (atl1_get_permanent_address(hw)) { 540 eth_random_addr(hw->perm_mac_addr); 541 ret = 1; 542 } 543 544 for (i = 0; i < ETH_ALEN; i++) 545 hw->mac_addr[i] = hw->perm_mac_addr[i]; 546 return ret; 547 } 548 549 /* 550 * Hashes an address to determine its location in the multicast table 551 * hw - Struct containing variables accessed by shared code 552 * mc_addr - the multicast address to hash 553 * 554 * atl1_hash_mc_addr 555 * purpose 556 * set hash value for a multicast address 557 * hash calcu processing : 558 * 1. calcu 32bit CRC for multicast address 559 * 2. reverse crc with MSB to LSB 560 */ 561 static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr) 562 { 563 u32 crc32, value = 0; 564 int i; 565 566 crc32 = ether_crc_le(6, mc_addr); 567 for (i = 0; i < 32; i++) 568 value |= (((crc32 >> i) & 1) << (31 - i)); 569 570 return value; 571 } 572 573 /* 574 * Sets the bit in the multicast table corresponding to the hash value. 575 * hw - Struct containing variables accessed by shared code 576 * hash_value - Multicast address hash value 577 */ 578 static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value) 579 { 580 u32 hash_bit, hash_reg; 581 u32 mta; 582 583 /* 584 * The HASH Table is a register array of 2 32-bit registers. 585 * It is treated like an array of 64 bits. We want to set 586 * bit BitArray[hash_value]. So we figure out what register 587 * the bit is in, read it, OR in the new bit, then write 588 * back the new value. The register is determined by the 589 * upper 7 bits of the hash value and the bit within that 590 * register are determined by the lower 5 bits of the value. 591 */ 592 hash_reg = (hash_value >> 31) & 0x1; 593 hash_bit = (hash_value >> 26) & 0x1F; 594 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); 595 mta |= (1 << hash_bit); 596 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); 597 } 598 599 /* 600 * Writes a value to a PHY register 601 * hw - Struct containing variables accessed by shared code 602 * reg_addr - address of the PHY register to write 603 * data - data to write to the PHY 604 */ 605 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data) 606 { 607 int i; 608 u32 val; 609 610 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 611 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 612 MDIO_SUP_PREAMBLE | 613 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 614 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); 615 ioread32(hw->hw_addr + REG_MDIO_CTRL); 616 617 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 618 udelay(2); 619 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); 620 if (!(val & (MDIO_START | MDIO_BUSY))) 621 break; 622 } 623 624 if (!(val & (MDIO_START | MDIO_BUSY))) 625 return 0; 626 627 return ATLX_ERR_PHY; 628 } 629 630 /* 631 * Make L001's PHY out of Power Saving State (bug) 632 * hw - Struct containing variables accessed by shared code 633 * when power on, L001's PHY always on Power saving State 634 * (Gigabit Link forbidden) 635 */ 636 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw) 637 { 638 s32 ret; 639 ret = atl1_write_phy_reg(hw, 29, 0x0029); 640 if (ret) 641 return ret; 642 return atl1_write_phy_reg(hw, 30, 0); 643 } 644 645 /* 646 * Resets the PHY and make all config validate 647 * hw - Struct containing variables accessed by shared code 648 * 649 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) 650 */ 651 static s32 atl1_phy_reset(struct atl1_hw *hw) 652 { 653 struct pci_dev *pdev = hw->back->pdev; 654 struct atl1_adapter *adapter = hw->back; 655 s32 ret_val; 656 u16 phy_data; 657 658 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 659 hw->media_type == MEDIA_TYPE_1000M_FULL) 660 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 661 else { 662 switch (hw->media_type) { 663 case MEDIA_TYPE_100M_FULL: 664 phy_data = 665 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | 666 MII_CR_RESET; 667 break; 668 case MEDIA_TYPE_100M_HALF: 669 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 670 break; 671 case MEDIA_TYPE_10M_FULL: 672 phy_data = 673 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 674 break; 675 default: 676 /* MEDIA_TYPE_10M_HALF: */ 677 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 678 break; 679 } 680 } 681 682 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data); 683 if (ret_val) { 684 u32 val; 685 int i; 686 /* pcie serdes link may be down! */ 687 if (netif_msg_hw(adapter)) 688 dev_dbg(&pdev->dev, "pcie phy link down\n"); 689 690 for (i = 0; i < 25; i++) { 691 msleep(1); 692 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); 693 if (!(val & (MDIO_START | MDIO_BUSY))) 694 break; 695 } 696 697 if ((val & (MDIO_START | MDIO_BUSY)) != 0) { 698 if (netif_msg_hw(adapter)) 699 dev_warn(&pdev->dev, 700 "pcie link down at least 25ms\n"); 701 return ret_val; 702 } 703 } 704 return 0; 705 } 706 707 /* 708 * Configures PHY autoneg and flow control advertisement settings 709 * hw - Struct containing variables accessed by shared code 710 */ 711 static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw) 712 { 713 s32 ret_val; 714 s16 mii_autoneg_adv_reg; 715 s16 mii_1000t_ctrl_reg; 716 717 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 718 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 719 720 /* Read the MII 1000Base-T Control Register (Address 9). */ 721 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK; 722 723 /* 724 * First we clear all the 10/100 mb speed bits in the Auto-Neg 725 * Advertisement Register (Address 4) and the 1000 mb speed bits in 726 * the 1000Base-T Control Register (Address 9). 727 */ 728 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 729 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK; 730 731 /* 732 * Need to parse media_type and set up 733 * the appropriate PHY registers. 734 */ 735 switch (hw->media_type) { 736 case MEDIA_TYPE_AUTO_SENSOR: 737 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS | 738 MII_AR_10T_FD_CAPS | 739 MII_AR_100TX_HD_CAPS | 740 MII_AR_100TX_FD_CAPS); 741 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS; 742 break; 743 744 case MEDIA_TYPE_1000M_FULL: 745 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS; 746 break; 747 748 case MEDIA_TYPE_100M_FULL: 749 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 750 break; 751 752 case MEDIA_TYPE_100M_HALF: 753 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 754 break; 755 756 case MEDIA_TYPE_10M_FULL: 757 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 758 break; 759 760 default: 761 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 762 break; 763 } 764 765 /* flow control fixed to enable all */ 766 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 767 768 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 769 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; 770 771 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 772 if (ret_val) 773 return ret_val; 774 775 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg); 776 if (ret_val) 777 return ret_val; 778 779 return 0; 780 } 781 782 /* 783 * Configures link settings. 784 * hw - Struct containing variables accessed by shared code 785 * Assumes the hardware has previously been reset and the 786 * transmitter and receiver are not enabled. 787 */ 788 static s32 atl1_setup_link(struct atl1_hw *hw) 789 { 790 struct pci_dev *pdev = hw->back->pdev; 791 struct atl1_adapter *adapter = hw->back; 792 s32 ret_val; 793 794 /* 795 * Options: 796 * PHY will advertise value(s) parsed from 797 * autoneg_advertised and fc 798 * no matter what autoneg is , We will not wait link result. 799 */ 800 ret_val = atl1_phy_setup_autoneg_adv(hw); 801 if (ret_val) { 802 if (netif_msg_link(adapter)) 803 dev_dbg(&pdev->dev, 804 "error setting up autonegotiation\n"); 805 return ret_val; 806 } 807 /* SW.Reset , En-Auto-Neg if needed */ 808 ret_val = atl1_phy_reset(hw); 809 if (ret_val) { 810 if (netif_msg_link(adapter)) 811 dev_dbg(&pdev->dev, "error resetting phy\n"); 812 return ret_val; 813 } 814 hw->phy_configured = true; 815 return ret_val; 816 } 817 818 static void atl1_init_flash_opcode(struct atl1_hw *hw) 819 { 820 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) 821 /* Atmel */ 822 hw->flash_vendor = 0; 823 824 /* Init OP table */ 825 iowrite8(flash_table[hw->flash_vendor].cmd_program, 826 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM); 827 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase, 828 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE); 829 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase, 830 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE); 831 iowrite8(flash_table[hw->flash_vendor].cmd_rdid, 832 hw->hw_addr + REG_SPI_FLASH_OP_RDID); 833 iowrite8(flash_table[hw->flash_vendor].cmd_wren, 834 hw->hw_addr + REG_SPI_FLASH_OP_WREN); 835 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr, 836 hw->hw_addr + REG_SPI_FLASH_OP_RDSR); 837 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr, 838 hw->hw_addr + REG_SPI_FLASH_OP_WRSR); 839 iowrite8(flash_table[hw->flash_vendor].cmd_read, 840 hw->hw_addr + REG_SPI_FLASH_OP_READ); 841 } 842 843 /* 844 * Performs basic configuration of the adapter. 845 * hw - Struct containing variables accessed by shared code 846 * Assumes that the controller has previously been reset and is in a 847 * post-reset uninitialized state. Initializes multicast table, 848 * and Calls routines to setup link 849 * Leaves the transmit and receive units disabled and uninitialized. 850 */ 851 static s32 atl1_init_hw(struct atl1_hw *hw) 852 { 853 u32 ret_val = 0; 854 855 /* Zero out the Multicast HASH table */ 856 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE); 857 /* clear the old settings from the multicast hash table */ 858 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2)); 859 860 atl1_init_flash_opcode(hw); 861 862 if (!hw->phy_configured) { 863 /* enable GPHY LinkChange Interrupt */ 864 ret_val = atl1_write_phy_reg(hw, 18, 0xC00); 865 if (ret_val) 866 return ret_val; 867 /* make PHY out of power-saving state */ 868 ret_val = atl1_phy_leave_power_saving(hw); 869 if (ret_val) 870 return ret_val; 871 /* Call a subroutine to configure the link */ 872 ret_val = atl1_setup_link(hw); 873 } 874 return ret_val; 875 } 876 877 /* 878 * Detects the current speed and duplex settings of the hardware. 879 * hw - Struct containing variables accessed by shared code 880 * speed - Speed of the connection 881 * duplex - Duplex setting of the connection 882 */ 883 static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex) 884 { 885 struct pci_dev *pdev = hw->back->pdev; 886 struct atl1_adapter *adapter = hw->back; 887 s32 ret_val; 888 u16 phy_data; 889 890 /* ; --- Read PHY Specific Status Register (17) */ 891 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); 892 if (ret_val) 893 return ret_val; 894 895 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) 896 return ATLX_ERR_PHY_RES; 897 898 switch (phy_data & MII_ATLX_PSSR_SPEED) { 899 case MII_ATLX_PSSR_1000MBS: 900 *speed = SPEED_1000; 901 break; 902 case MII_ATLX_PSSR_100MBS: 903 *speed = SPEED_100; 904 break; 905 case MII_ATLX_PSSR_10MBS: 906 *speed = SPEED_10; 907 break; 908 default: 909 if (netif_msg_hw(adapter)) 910 dev_dbg(&pdev->dev, "error getting speed\n"); 911 return ATLX_ERR_PHY_SPEED; 912 } 913 if (phy_data & MII_ATLX_PSSR_DPLX) 914 *duplex = FULL_DUPLEX; 915 else 916 *duplex = HALF_DUPLEX; 917 918 return 0; 919 } 920 921 static void atl1_set_mac_addr(struct atl1_hw *hw) 922 { 923 u32 value; 924 /* 925 * 00-0B-6A-F6-00-DC 926 * 0: 6AF600DC 1: 000B 927 * low dword 928 */ 929 value = (((u32) hw->mac_addr[2]) << 24) | 930 (((u32) hw->mac_addr[3]) << 16) | 931 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5])); 932 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); 933 /* high dword */ 934 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); 935 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2)); 936 } 937 938 /** 939 * atl1_sw_init - Initialize general software structures (struct atl1_adapter) 940 * @adapter: board private structure to initialize 941 * 942 * atl1_sw_init initializes the Adapter private data structure. 943 * Fields are initialized based on PCI device information and 944 * OS network device settings (MTU size). 945 */ 946 static int atl1_sw_init(struct atl1_adapter *adapter) 947 { 948 struct atl1_hw *hw = &adapter->hw; 949 struct net_device *netdev = adapter->netdev; 950 951 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 952 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 953 954 adapter->wol = 0; 955 device_set_wakeup_enable(&adapter->pdev->dev, false); 956 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7; 957 adapter->ict = 50000; /* 100ms */ 958 adapter->link_speed = SPEED_0; /* hardware init */ 959 adapter->link_duplex = FULL_DUPLEX; 960 961 hw->phy_configured = false; 962 hw->preamble_len = 7; 963 hw->ipgt = 0x60; 964 hw->min_ifg = 0x50; 965 hw->ipgr1 = 0x40; 966 hw->ipgr2 = 0x60; 967 hw->max_retry = 0xf; 968 hw->lcol = 0x37; 969 hw->jam_ipg = 7; 970 hw->rfd_burst = 8; 971 hw->rrd_burst = 8; 972 hw->rfd_fetch_gap = 1; 973 hw->rx_jumbo_th = adapter->rx_buffer_len / 8; 974 hw->rx_jumbo_lkah = 1; 975 hw->rrd_ret_timer = 16; 976 hw->tpd_burst = 4; 977 hw->tpd_fetch_th = 16; 978 hw->txf_burst = 0x100; 979 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3; 980 hw->tpd_fetch_gap = 1; 981 hw->rcb_value = atl1_rcb_64; 982 hw->dma_ord = atl1_dma_ord_enh; 983 hw->dmar_block = atl1_dma_req_256; 984 hw->dmaw_block = atl1_dma_req_256; 985 hw->cmb_rrd = 4; 986 hw->cmb_tpd = 4; 987 hw->cmb_rx_timer = 1; /* about 2us */ 988 hw->cmb_tx_timer = 1; /* about 2us */ 989 hw->smb_timer = 100000; /* about 200ms */ 990 991 spin_lock_init(&adapter->lock); 992 spin_lock_init(&adapter->mb_lock); 993 994 return 0; 995 } 996 997 static int mdio_read(struct net_device *netdev, int phy_id, int reg_num) 998 { 999 struct atl1_adapter *adapter = netdev_priv(netdev); 1000 u16 result; 1001 1002 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result); 1003 1004 return result; 1005 } 1006 1007 static void mdio_write(struct net_device *netdev, int phy_id, int reg_num, 1008 int val) 1009 { 1010 struct atl1_adapter *adapter = netdev_priv(netdev); 1011 1012 atl1_write_phy_reg(&adapter->hw, reg_num, val); 1013 } 1014 1015 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1016 { 1017 struct atl1_adapter *adapter = netdev_priv(netdev); 1018 unsigned long flags; 1019 int retval; 1020 1021 if (!netif_running(netdev)) 1022 return -EINVAL; 1023 1024 spin_lock_irqsave(&adapter->lock, flags); 1025 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL); 1026 spin_unlock_irqrestore(&adapter->lock, flags); 1027 1028 return retval; 1029 } 1030 1031 /** 1032 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources 1033 * @adapter: board private structure 1034 * 1035 * Return 0 on success, negative on failure 1036 */ 1037 static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter) 1038 { 1039 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1040 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1041 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1042 struct atl1_ring_header *ring_header = &adapter->ring_header; 1043 struct pci_dev *pdev = adapter->pdev; 1044 int size; 1045 u8 offset = 0; 1046 1047 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count); 1048 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL); 1049 if (unlikely(!tpd_ring->buffer_info)) { 1050 if (netif_msg_drv(adapter)) 1051 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n", 1052 size); 1053 goto err_nomem; 1054 } 1055 rfd_ring->buffer_info = 1056 (tpd_ring->buffer_info + tpd_ring->count); 1057 1058 /* 1059 * real ring DMA buffer 1060 * each ring/block may need up to 8 bytes for alignment, hence the 1061 * additional 40 bytes tacked onto the end. 1062 */ 1063 ring_header->size = size = 1064 sizeof(struct tx_packet_desc) * tpd_ring->count 1065 + sizeof(struct rx_free_desc) * rfd_ring->count 1066 + sizeof(struct rx_return_desc) * rrd_ring->count 1067 + sizeof(struct coals_msg_block) 1068 + sizeof(struct stats_msg_block) 1069 + 40; 1070 1071 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size, 1072 &ring_header->dma); 1073 if (unlikely(!ring_header->desc)) { 1074 if (netif_msg_drv(adapter)) 1075 dev_err(&pdev->dev, "pci_alloc_consistent failed\n"); 1076 goto err_nomem; 1077 } 1078 1079 memset(ring_header->desc, 0, ring_header->size); 1080 1081 /* init TPD ring */ 1082 tpd_ring->dma = ring_header->dma; 1083 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0; 1084 tpd_ring->dma += offset; 1085 tpd_ring->desc = (u8 *) ring_header->desc + offset; 1086 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count; 1087 1088 /* init RFD ring */ 1089 rfd_ring->dma = tpd_ring->dma + tpd_ring->size; 1090 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0; 1091 rfd_ring->dma += offset; 1092 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset); 1093 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count; 1094 1095 1096 /* init RRD ring */ 1097 rrd_ring->dma = rfd_ring->dma + rfd_ring->size; 1098 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0; 1099 rrd_ring->dma += offset; 1100 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset); 1101 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count; 1102 1103 1104 /* init CMB */ 1105 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size; 1106 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0; 1107 adapter->cmb.dma += offset; 1108 adapter->cmb.cmb = (struct coals_msg_block *) 1109 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset)); 1110 1111 /* init SMB */ 1112 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block); 1113 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0; 1114 adapter->smb.dma += offset; 1115 adapter->smb.smb = (struct stats_msg_block *) 1116 ((u8 *) adapter->cmb.cmb + 1117 (sizeof(struct coals_msg_block) + offset)); 1118 1119 return 0; 1120 1121 err_nomem: 1122 kfree(tpd_ring->buffer_info); 1123 return -ENOMEM; 1124 } 1125 1126 static void atl1_init_ring_ptrs(struct atl1_adapter *adapter) 1127 { 1128 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1129 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1130 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1131 1132 atomic_set(&tpd_ring->next_to_use, 0); 1133 atomic_set(&tpd_ring->next_to_clean, 0); 1134 1135 rfd_ring->next_to_clean = 0; 1136 atomic_set(&rfd_ring->next_to_use, 0); 1137 1138 rrd_ring->next_to_use = 0; 1139 atomic_set(&rrd_ring->next_to_clean, 0); 1140 } 1141 1142 /** 1143 * atl1_clean_rx_ring - Free RFD Buffers 1144 * @adapter: board private structure 1145 */ 1146 static void atl1_clean_rx_ring(struct atl1_adapter *adapter) 1147 { 1148 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1149 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1150 struct atl1_buffer *buffer_info; 1151 struct pci_dev *pdev = adapter->pdev; 1152 unsigned long size; 1153 unsigned int i; 1154 1155 /* Free all the Rx ring sk_buffs */ 1156 for (i = 0; i < rfd_ring->count; i++) { 1157 buffer_info = &rfd_ring->buffer_info[i]; 1158 if (buffer_info->dma) { 1159 pci_unmap_page(pdev, buffer_info->dma, 1160 buffer_info->length, PCI_DMA_FROMDEVICE); 1161 buffer_info->dma = 0; 1162 } 1163 if (buffer_info->skb) { 1164 dev_kfree_skb(buffer_info->skb); 1165 buffer_info->skb = NULL; 1166 } 1167 } 1168 1169 size = sizeof(struct atl1_buffer) * rfd_ring->count; 1170 memset(rfd_ring->buffer_info, 0, size); 1171 1172 /* Zero out the descriptor ring */ 1173 memset(rfd_ring->desc, 0, rfd_ring->size); 1174 1175 rfd_ring->next_to_clean = 0; 1176 atomic_set(&rfd_ring->next_to_use, 0); 1177 1178 rrd_ring->next_to_use = 0; 1179 atomic_set(&rrd_ring->next_to_clean, 0); 1180 } 1181 1182 /** 1183 * atl1_clean_tx_ring - Free Tx Buffers 1184 * @adapter: board private structure 1185 */ 1186 static void atl1_clean_tx_ring(struct atl1_adapter *adapter) 1187 { 1188 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1189 struct atl1_buffer *buffer_info; 1190 struct pci_dev *pdev = adapter->pdev; 1191 unsigned long size; 1192 unsigned int i; 1193 1194 /* Free all the Tx ring sk_buffs */ 1195 for (i = 0; i < tpd_ring->count; i++) { 1196 buffer_info = &tpd_ring->buffer_info[i]; 1197 if (buffer_info->dma) { 1198 pci_unmap_page(pdev, buffer_info->dma, 1199 buffer_info->length, PCI_DMA_TODEVICE); 1200 buffer_info->dma = 0; 1201 } 1202 } 1203 1204 for (i = 0; i < tpd_ring->count; i++) { 1205 buffer_info = &tpd_ring->buffer_info[i]; 1206 if (buffer_info->skb) { 1207 dev_kfree_skb_any(buffer_info->skb); 1208 buffer_info->skb = NULL; 1209 } 1210 } 1211 1212 size = sizeof(struct atl1_buffer) * tpd_ring->count; 1213 memset(tpd_ring->buffer_info, 0, size); 1214 1215 /* Zero out the descriptor ring */ 1216 memset(tpd_ring->desc, 0, tpd_ring->size); 1217 1218 atomic_set(&tpd_ring->next_to_use, 0); 1219 atomic_set(&tpd_ring->next_to_clean, 0); 1220 } 1221 1222 /** 1223 * atl1_free_ring_resources - Free Tx / RX descriptor Resources 1224 * @adapter: board private structure 1225 * 1226 * Free all transmit software resources 1227 */ 1228 static void atl1_free_ring_resources(struct atl1_adapter *adapter) 1229 { 1230 struct pci_dev *pdev = adapter->pdev; 1231 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1232 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1233 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1234 struct atl1_ring_header *ring_header = &adapter->ring_header; 1235 1236 atl1_clean_tx_ring(adapter); 1237 atl1_clean_rx_ring(adapter); 1238 1239 kfree(tpd_ring->buffer_info); 1240 pci_free_consistent(pdev, ring_header->size, ring_header->desc, 1241 ring_header->dma); 1242 1243 tpd_ring->buffer_info = NULL; 1244 tpd_ring->desc = NULL; 1245 tpd_ring->dma = 0; 1246 1247 rfd_ring->buffer_info = NULL; 1248 rfd_ring->desc = NULL; 1249 rfd_ring->dma = 0; 1250 1251 rrd_ring->desc = NULL; 1252 rrd_ring->dma = 0; 1253 1254 adapter->cmb.dma = 0; 1255 adapter->cmb.cmb = NULL; 1256 1257 adapter->smb.dma = 0; 1258 adapter->smb.smb = NULL; 1259 } 1260 1261 static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter) 1262 { 1263 u32 value; 1264 struct atl1_hw *hw = &adapter->hw; 1265 struct net_device *netdev = adapter->netdev; 1266 /* Config MAC CTRL Register */ 1267 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN; 1268 /* duplex */ 1269 if (FULL_DUPLEX == adapter->link_duplex) 1270 value |= MAC_CTRL_DUPLX; 1271 /* speed */ 1272 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ? 1273 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) << 1274 MAC_CTRL_SPEED_SHIFT); 1275 /* flow control */ 1276 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 1277 /* PAD & CRC */ 1278 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1279 /* preamble length */ 1280 value |= (((u32) adapter->hw.preamble_len 1281 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 1282 /* vlan */ 1283 __atlx_vlan_mode(netdev->features, &value); 1284 /* rx checksum 1285 if (adapter->rx_csum) 1286 value |= MAC_CTRL_RX_CHKSUM_EN; 1287 */ 1288 /* filter mode */ 1289 value |= MAC_CTRL_BC_EN; 1290 if (netdev->flags & IFF_PROMISC) 1291 value |= MAC_CTRL_PROMIS_EN; 1292 else if (netdev->flags & IFF_ALLMULTI) 1293 value |= MAC_CTRL_MC_ALL_EN; 1294 /* value |= MAC_CTRL_LOOPBACK; */ 1295 iowrite32(value, hw->hw_addr + REG_MAC_CTRL); 1296 } 1297 1298 static u32 atl1_check_link(struct atl1_adapter *adapter) 1299 { 1300 struct atl1_hw *hw = &adapter->hw; 1301 struct net_device *netdev = adapter->netdev; 1302 u32 ret_val; 1303 u16 speed, duplex, phy_data; 1304 int reconfig = 0; 1305 1306 /* MII_BMSR must read twice */ 1307 atl1_read_phy_reg(hw, MII_BMSR, &phy_data); 1308 atl1_read_phy_reg(hw, MII_BMSR, &phy_data); 1309 if (!(phy_data & BMSR_LSTATUS)) { 1310 /* link down */ 1311 if (netif_carrier_ok(netdev)) { 1312 /* old link state: Up */ 1313 if (netif_msg_link(adapter)) 1314 dev_info(&adapter->pdev->dev, "link is down\n"); 1315 adapter->link_speed = SPEED_0; 1316 netif_carrier_off(netdev); 1317 } 1318 return 0; 1319 } 1320 1321 /* Link Up */ 1322 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex); 1323 if (ret_val) 1324 return ret_val; 1325 1326 switch (hw->media_type) { 1327 case MEDIA_TYPE_1000M_FULL: 1328 if (speed != SPEED_1000 || duplex != FULL_DUPLEX) 1329 reconfig = 1; 1330 break; 1331 case MEDIA_TYPE_100M_FULL: 1332 if (speed != SPEED_100 || duplex != FULL_DUPLEX) 1333 reconfig = 1; 1334 break; 1335 case MEDIA_TYPE_100M_HALF: 1336 if (speed != SPEED_100 || duplex != HALF_DUPLEX) 1337 reconfig = 1; 1338 break; 1339 case MEDIA_TYPE_10M_FULL: 1340 if (speed != SPEED_10 || duplex != FULL_DUPLEX) 1341 reconfig = 1; 1342 break; 1343 case MEDIA_TYPE_10M_HALF: 1344 if (speed != SPEED_10 || duplex != HALF_DUPLEX) 1345 reconfig = 1; 1346 break; 1347 } 1348 1349 /* link result is our setting */ 1350 if (!reconfig) { 1351 if (adapter->link_speed != speed || 1352 adapter->link_duplex != duplex) { 1353 adapter->link_speed = speed; 1354 adapter->link_duplex = duplex; 1355 atl1_setup_mac_ctrl(adapter); 1356 if (netif_msg_link(adapter)) 1357 dev_info(&adapter->pdev->dev, 1358 "%s link is up %d Mbps %s\n", 1359 netdev->name, adapter->link_speed, 1360 adapter->link_duplex == FULL_DUPLEX ? 1361 "full duplex" : "half duplex"); 1362 } 1363 if (!netif_carrier_ok(netdev)) { 1364 /* Link down -> Up */ 1365 netif_carrier_on(netdev); 1366 } 1367 return 0; 1368 } 1369 1370 /* change original link status */ 1371 if (netif_carrier_ok(netdev)) { 1372 adapter->link_speed = SPEED_0; 1373 netif_carrier_off(netdev); 1374 netif_stop_queue(netdev); 1375 } 1376 1377 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR && 1378 hw->media_type != MEDIA_TYPE_1000M_FULL) { 1379 switch (hw->media_type) { 1380 case MEDIA_TYPE_100M_FULL: 1381 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | 1382 MII_CR_RESET; 1383 break; 1384 case MEDIA_TYPE_100M_HALF: 1385 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 1386 break; 1387 case MEDIA_TYPE_10M_FULL: 1388 phy_data = 1389 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 1390 break; 1391 default: 1392 /* MEDIA_TYPE_10M_HALF: */ 1393 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 1394 break; 1395 } 1396 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 1397 return 0; 1398 } 1399 1400 /* auto-neg, insert timer to re-config phy */ 1401 if (!adapter->phy_timer_pending) { 1402 adapter->phy_timer_pending = true; 1403 mod_timer(&adapter->phy_config_timer, 1404 round_jiffies(jiffies + 3 * HZ)); 1405 } 1406 1407 return 0; 1408 } 1409 1410 static void set_flow_ctrl_old(struct atl1_adapter *adapter) 1411 { 1412 u32 hi, lo, value; 1413 1414 /* RFD Flow Control */ 1415 value = adapter->rfd_ring.count; 1416 hi = value / 16; 1417 if (hi < 2) 1418 hi = 2; 1419 lo = value * 7 / 8; 1420 1421 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | 1422 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); 1423 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH); 1424 1425 /* RRD Flow Control */ 1426 value = adapter->rrd_ring.count; 1427 lo = value / 16; 1428 hi = value * 7 / 8; 1429 if (lo < 2) 1430 lo = 2; 1431 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | 1432 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); 1433 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH); 1434 } 1435 1436 static void set_flow_ctrl_new(struct atl1_hw *hw) 1437 { 1438 u32 hi, lo, value; 1439 1440 /* RXF Flow Control */ 1441 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN); 1442 lo = value / 16; 1443 if (lo < 192) 1444 lo = 192; 1445 hi = value * 7 / 8; 1446 if (hi < lo) 1447 hi = lo + 16; 1448 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | 1449 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); 1450 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH); 1451 1452 /* RRD Flow Control */ 1453 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN); 1454 lo = value / 8; 1455 hi = value * 7 / 8; 1456 if (lo < 2) 1457 lo = 2; 1458 if (hi < lo) 1459 hi = lo + 3; 1460 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | 1461 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); 1462 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH); 1463 } 1464 1465 /** 1466 * atl1_configure - Configure Transmit&Receive Unit after Reset 1467 * @adapter: board private structure 1468 * 1469 * Configure the Tx /Rx unit of the MAC after a reset. 1470 */ 1471 static u32 atl1_configure(struct atl1_adapter *adapter) 1472 { 1473 struct atl1_hw *hw = &adapter->hw; 1474 u32 value; 1475 1476 /* clear interrupt status */ 1477 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR); 1478 1479 /* set MAC Address */ 1480 value = (((u32) hw->mac_addr[2]) << 24) | 1481 (((u32) hw->mac_addr[3]) << 16) | 1482 (((u32) hw->mac_addr[4]) << 8) | 1483 (((u32) hw->mac_addr[5])); 1484 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); 1485 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); 1486 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4)); 1487 1488 /* tx / rx ring */ 1489 1490 /* HI base address */ 1491 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32), 1492 hw->hw_addr + REG_DESC_BASE_ADDR_HI); 1493 /* LO base address */ 1494 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL), 1495 hw->hw_addr + REG_DESC_RFD_ADDR_LO); 1496 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL), 1497 hw->hw_addr + REG_DESC_RRD_ADDR_LO); 1498 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL), 1499 hw->hw_addr + REG_DESC_TPD_ADDR_LO); 1500 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL), 1501 hw->hw_addr + REG_DESC_CMB_ADDR_LO); 1502 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL), 1503 hw->hw_addr + REG_DESC_SMB_ADDR_LO); 1504 1505 /* element count */ 1506 value = adapter->rrd_ring.count; 1507 value <<= 16; 1508 value += adapter->rfd_ring.count; 1509 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE); 1510 iowrite32(adapter->tpd_ring.count, hw->hw_addr + 1511 REG_DESC_TPD_RING_SIZE); 1512 1513 /* Load Ptr */ 1514 iowrite32(1, hw->hw_addr + REG_LOAD_PTR); 1515 1516 /* config Mailbox */ 1517 value = ((atomic_read(&adapter->tpd_ring.next_to_use) 1518 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) | 1519 ((atomic_read(&adapter->rrd_ring.next_to_clean) 1520 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) | 1521 ((atomic_read(&adapter->rfd_ring.next_to_use) 1522 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT); 1523 iowrite32(value, hw->hw_addr + REG_MAILBOX); 1524 1525 /* config IPG/IFG */ 1526 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK) 1527 << MAC_IPG_IFG_IPGT_SHIFT) | 1528 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) 1529 << MAC_IPG_IFG_MIFG_SHIFT) | 1530 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) 1531 << MAC_IPG_IFG_IPGR1_SHIFT) | 1532 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) 1533 << MAC_IPG_IFG_IPGR2_SHIFT); 1534 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG); 1535 1536 /* config Half-Duplex Control */ 1537 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | 1538 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) 1539 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | 1540 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | 1541 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | 1542 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) 1543 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); 1544 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL); 1545 1546 /* set Interrupt Moderator Timer */ 1547 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT); 1548 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL); 1549 1550 /* set Interrupt Clear Timer */ 1551 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER); 1552 1553 /* set max frame size hw will accept */ 1554 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU); 1555 1556 /* jumbo size & rrd retirement timer */ 1557 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) 1558 << RXQ_JMBOSZ_TH_SHIFT) | 1559 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK) 1560 << RXQ_JMBO_LKAH_SHIFT) | 1561 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK) 1562 << RXQ_RRD_TIMER_SHIFT); 1563 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM); 1564 1565 /* Flow Control */ 1566 switch (hw->dev_rev) { 1567 case 0x8001: 1568 case 0x9001: 1569 case 0x9002: 1570 case 0x9003: 1571 set_flow_ctrl_old(adapter); 1572 break; 1573 default: 1574 set_flow_ctrl_new(hw); 1575 break; 1576 } 1577 1578 /* config TXQ */ 1579 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK) 1580 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) | 1581 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK) 1582 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) | 1583 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK) 1584 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE | 1585 TXQ_CTRL_EN; 1586 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL); 1587 1588 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */ 1589 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK) 1590 << TX_JUMBO_TASK_TH_SHIFT) | 1591 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK) 1592 << TX_TPD_MIN_IPG_SHIFT); 1593 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG); 1594 1595 /* config RXQ */ 1596 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK) 1597 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) | 1598 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK) 1599 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) | 1600 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK) 1601 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN | 1602 RXQ_CTRL_EN; 1603 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL); 1604 1605 /* config DMA Engine */ 1606 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK) 1607 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) | 1608 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK) 1609 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN | 1610 DMA_CTRL_DMAW_EN; 1611 value |= (u32) hw->dma_ord; 1612 if (atl1_rcb_128 == hw->rcb_value) 1613 value |= DMA_CTRL_RCB_VALUE; 1614 iowrite32(value, hw->hw_addr + REG_DMA_CTRL); 1615 1616 /* config CMB / SMB */ 1617 value = (hw->cmb_tpd > adapter->tpd_ring.count) ? 1618 hw->cmb_tpd : adapter->tpd_ring.count; 1619 value <<= 16; 1620 value |= hw->cmb_rrd; 1621 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH); 1622 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16); 1623 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER); 1624 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER); 1625 1626 /* --- enable CMB / SMB */ 1627 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN; 1628 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL); 1629 1630 value = ioread32(adapter->hw.hw_addr + REG_ISR); 1631 if (unlikely((value & ISR_PHY_LINKDOWN) != 0)) 1632 value = 1; /* config failed */ 1633 else 1634 value = 0; 1635 1636 /* clear all interrupt status */ 1637 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR); 1638 iowrite32(0, adapter->hw.hw_addr + REG_ISR); 1639 return value; 1640 } 1641 1642 /* 1643 * atl1_pcie_patch - Patch for PCIE module 1644 */ 1645 static void atl1_pcie_patch(struct atl1_adapter *adapter) 1646 { 1647 u32 value; 1648 1649 /* much vendor magic here */ 1650 value = 0x6500; 1651 iowrite32(value, adapter->hw.hw_addr + 0x12FC); 1652 /* pcie flow control mode change */ 1653 value = ioread32(adapter->hw.hw_addr + 0x1008); 1654 value |= 0x8000; 1655 iowrite32(value, adapter->hw.hw_addr + 0x1008); 1656 } 1657 1658 /* 1659 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400 1660 * on PCI Command register is disable. 1661 * The function enable this bit. 1662 * Brackett, 2006/03/15 1663 */ 1664 static void atl1_via_workaround(struct atl1_adapter *adapter) 1665 { 1666 unsigned long value; 1667 1668 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND); 1669 if (value & PCI_COMMAND_INTX_DISABLE) 1670 value &= ~PCI_COMMAND_INTX_DISABLE; 1671 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND); 1672 } 1673 1674 static void atl1_inc_smb(struct atl1_adapter *adapter) 1675 { 1676 struct net_device *netdev = adapter->netdev; 1677 struct stats_msg_block *smb = adapter->smb.smb; 1678 1679 u64 new_rx_errors = smb->rx_frag + 1680 smb->rx_fcs_err + 1681 smb->rx_len_err + 1682 smb->rx_sz_ov + 1683 smb->rx_rxf_ov + 1684 smb->rx_rrd_ov + 1685 smb->rx_align_err; 1686 u64 new_tx_errors = smb->tx_late_col + 1687 smb->tx_abort_col + 1688 smb->tx_underrun + 1689 smb->tx_trunc; 1690 1691 /* Fill out the OS statistics structure */ 1692 adapter->soft_stats.rx_packets += smb->rx_ok + new_rx_errors; 1693 adapter->soft_stats.tx_packets += smb->tx_ok + new_tx_errors; 1694 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt; 1695 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt; 1696 adapter->soft_stats.multicast += smb->rx_mcast; 1697 adapter->soft_stats.collisions += smb->tx_1_col + 1698 smb->tx_2_col + 1699 smb->tx_late_col + 1700 smb->tx_abort_col; 1701 1702 /* Rx Errors */ 1703 adapter->soft_stats.rx_errors += new_rx_errors; 1704 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov; 1705 adapter->soft_stats.rx_length_errors += smb->rx_len_err; 1706 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err; 1707 adapter->soft_stats.rx_frame_errors += smb->rx_align_err; 1708 1709 adapter->soft_stats.rx_pause += smb->rx_pause; 1710 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov; 1711 adapter->soft_stats.rx_trunc += smb->rx_sz_ov; 1712 1713 /* Tx Errors */ 1714 adapter->soft_stats.tx_errors += new_tx_errors; 1715 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun; 1716 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col; 1717 adapter->soft_stats.tx_window_errors += smb->tx_late_col; 1718 1719 adapter->soft_stats.excecol += smb->tx_abort_col; 1720 adapter->soft_stats.deffer += smb->tx_defer; 1721 adapter->soft_stats.scc += smb->tx_1_col; 1722 adapter->soft_stats.mcc += smb->tx_2_col; 1723 adapter->soft_stats.latecol += smb->tx_late_col; 1724 adapter->soft_stats.tx_underun += smb->tx_underrun; 1725 adapter->soft_stats.tx_trunc += smb->tx_trunc; 1726 adapter->soft_stats.tx_pause += smb->tx_pause; 1727 1728 netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes; 1729 netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes; 1730 netdev->stats.multicast = adapter->soft_stats.multicast; 1731 netdev->stats.collisions = adapter->soft_stats.collisions; 1732 netdev->stats.rx_errors = adapter->soft_stats.rx_errors; 1733 netdev->stats.rx_length_errors = 1734 adapter->soft_stats.rx_length_errors; 1735 netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors; 1736 netdev->stats.rx_frame_errors = 1737 adapter->soft_stats.rx_frame_errors; 1738 netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors; 1739 netdev->stats.rx_dropped = adapter->soft_stats.rx_rrd_ov; 1740 netdev->stats.tx_errors = adapter->soft_stats.tx_errors; 1741 netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors; 1742 netdev->stats.tx_aborted_errors = 1743 adapter->soft_stats.tx_aborted_errors; 1744 netdev->stats.tx_window_errors = 1745 adapter->soft_stats.tx_window_errors; 1746 netdev->stats.tx_carrier_errors = 1747 adapter->soft_stats.tx_carrier_errors; 1748 1749 netdev->stats.rx_packets = adapter->soft_stats.rx_packets; 1750 netdev->stats.tx_packets = adapter->soft_stats.tx_packets; 1751 } 1752 1753 static void atl1_update_mailbox(struct atl1_adapter *adapter) 1754 { 1755 unsigned long flags; 1756 u32 tpd_next_to_use; 1757 u32 rfd_next_to_use; 1758 u32 rrd_next_to_clean; 1759 u32 value; 1760 1761 spin_lock_irqsave(&adapter->mb_lock, flags); 1762 1763 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); 1764 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use); 1765 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean); 1766 1767 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << 1768 MB_RFD_PROD_INDX_SHIFT) | 1769 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << 1770 MB_RRD_CONS_INDX_SHIFT) | 1771 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << 1772 MB_TPD_PROD_INDX_SHIFT); 1773 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); 1774 1775 spin_unlock_irqrestore(&adapter->mb_lock, flags); 1776 } 1777 1778 static void atl1_clean_alloc_flag(struct atl1_adapter *adapter, 1779 struct rx_return_desc *rrd, u16 offset) 1780 { 1781 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1782 1783 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) { 1784 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0; 1785 if (++rfd_ring->next_to_clean == rfd_ring->count) { 1786 rfd_ring->next_to_clean = 0; 1787 } 1788 } 1789 } 1790 1791 static void atl1_update_rfd_index(struct atl1_adapter *adapter, 1792 struct rx_return_desc *rrd) 1793 { 1794 u16 num_buf; 1795 1796 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) / 1797 adapter->rx_buffer_len; 1798 if (rrd->num_buf == num_buf) 1799 /* clean alloc flag for bad rrd */ 1800 atl1_clean_alloc_flag(adapter, rrd, num_buf); 1801 } 1802 1803 static void atl1_rx_checksum(struct atl1_adapter *adapter, 1804 struct rx_return_desc *rrd, struct sk_buff *skb) 1805 { 1806 struct pci_dev *pdev = adapter->pdev; 1807 1808 /* 1809 * The L1 hardware contains a bug that erroneously sets the 1810 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a 1811 * fragmented IP packet is received, even though the packet 1812 * is perfectly valid and its checksum is correct. There's 1813 * no way to distinguish between one of these good packets 1814 * and a packet that actually contains a TCP/UDP checksum 1815 * error, so all we can do is allow it to be handed up to 1816 * the higher layers and let it be sorted out there. 1817 */ 1818 1819 skb_checksum_none_assert(skb); 1820 1821 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { 1822 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC | 1823 ERR_FLAG_CODE | ERR_FLAG_OV)) { 1824 adapter->hw_csum_err++; 1825 if (netif_msg_rx_err(adapter)) 1826 dev_printk(KERN_DEBUG, &pdev->dev, 1827 "rx checksum error\n"); 1828 return; 1829 } 1830 } 1831 1832 /* not IPv4 */ 1833 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4)) 1834 /* checksum is invalid, but it's not an IPv4 pkt, so ok */ 1835 return; 1836 1837 /* IPv4 packet */ 1838 if (likely(!(rrd->err_flg & 1839 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) { 1840 skb->ip_summed = CHECKSUM_UNNECESSARY; 1841 adapter->hw_csum_good++; 1842 return; 1843 } 1844 } 1845 1846 /** 1847 * atl1_alloc_rx_buffers - Replace used receive buffers 1848 * @adapter: address of board private structure 1849 */ 1850 static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter) 1851 { 1852 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1853 struct pci_dev *pdev = adapter->pdev; 1854 struct page *page; 1855 unsigned long offset; 1856 struct atl1_buffer *buffer_info, *next_info; 1857 struct sk_buff *skb; 1858 u16 num_alloc = 0; 1859 u16 rfd_next_to_use, next_next; 1860 struct rx_free_desc *rfd_desc; 1861 1862 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use); 1863 if (++next_next == rfd_ring->count) 1864 next_next = 0; 1865 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; 1866 next_info = &rfd_ring->buffer_info[next_next]; 1867 1868 while (!buffer_info->alloced && !next_info->alloced) { 1869 if (buffer_info->skb) { 1870 buffer_info->alloced = 1; 1871 goto next; 1872 } 1873 1874 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use); 1875 1876 skb = netdev_alloc_skb_ip_align(adapter->netdev, 1877 adapter->rx_buffer_len); 1878 if (unlikely(!skb)) { 1879 /* Better luck next round */ 1880 adapter->soft_stats.rx_dropped++; 1881 break; 1882 } 1883 1884 buffer_info->alloced = 1; 1885 buffer_info->skb = skb; 1886 buffer_info->length = (u16) adapter->rx_buffer_len; 1887 page = virt_to_page(skb->data); 1888 offset = offset_in_page(skb->data); 1889 buffer_info->dma = pci_map_page(pdev, page, offset, 1890 adapter->rx_buffer_len, 1891 PCI_DMA_FROMDEVICE); 1892 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 1893 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len); 1894 rfd_desc->coalese = 0; 1895 1896 next: 1897 rfd_next_to_use = next_next; 1898 if (unlikely(++next_next == rfd_ring->count)) 1899 next_next = 0; 1900 1901 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; 1902 next_info = &rfd_ring->buffer_info[next_next]; 1903 num_alloc++; 1904 } 1905 1906 if (num_alloc) { 1907 /* 1908 * Force memory writes to complete before letting h/w 1909 * know there are new descriptors to fetch. (Only 1910 * applicable for weak-ordered memory model archs, 1911 * such as IA-64). 1912 */ 1913 wmb(); 1914 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use); 1915 } 1916 return num_alloc; 1917 } 1918 1919 static int atl1_intr_rx(struct atl1_adapter *adapter, int budget) 1920 { 1921 int i, count; 1922 u16 length; 1923 u16 rrd_next_to_clean; 1924 u32 value; 1925 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1926 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1927 struct atl1_buffer *buffer_info; 1928 struct rx_return_desc *rrd; 1929 struct sk_buff *skb; 1930 1931 count = 0; 1932 1933 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean); 1934 1935 while (count < budget) { 1936 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean); 1937 i = 1; 1938 if (likely(rrd->xsz.valid)) { /* packet valid */ 1939 chk_rrd: 1940 /* check rrd status */ 1941 if (likely(rrd->num_buf == 1)) 1942 goto rrd_ok; 1943 else if (netif_msg_rx_err(adapter)) { 1944 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1945 "unexpected RRD buffer count\n"); 1946 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1947 "rx_buf_len = %d\n", 1948 adapter->rx_buffer_len); 1949 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1950 "RRD num_buf = %d\n", 1951 rrd->num_buf); 1952 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1953 "RRD pkt_len = %d\n", 1954 rrd->xsz.xsum_sz.pkt_size); 1955 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1956 "RRD pkt_flg = 0x%08X\n", 1957 rrd->pkt_flg); 1958 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1959 "RRD err_flg = 0x%08X\n", 1960 rrd->err_flg); 1961 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1962 "RRD vlan_tag = 0x%08X\n", 1963 rrd->vlan_tag); 1964 } 1965 1966 /* rrd seems to be bad */ 1967 if (unlikely(i-- > 0)) { 1968 /* rrd may not be DMAed completely */ 1969 udelay(1); 1970 goto chk_rrd; 1971 } 1972 /* bad rrd */ 1973 if (netif_msg_rx_err(adapter)) 1974 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1975 "bad RRD\n"); 1976 /* see if update RFD index */ 1977 if (rrd->num_buf > 1) 1978 atl1_update_rfd_index(adapter, rrd); 1979 1980 /* update rrd */ 1981 rrd->xsz.valid = 0; 1982 if (++rrd_next_to_clean == rrd_ring->count) 1983 rrd_next_to_clean = 0; 1984 count++; 1985 continue; 1986 } else { /* current rrd still not be updated */ 1987 1988 break; 1989 } 1990 rrd_ok: 1991 /* clean alloc flag for bad rrd */ 1992 atl1_clean_alloc_flag(adapter, rrd, 0); 1993 1994 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx]; 1995 if (++rfd_ring->next_to_clean == rfd_ring->count) 1996 rfd_ring->next_to_clean = 0; 1997 1998 /* update rrd next to clean */ 1999 if (++rrd_next_to_clean == rrd_ring->count) 2000 rrd_next_to_clean = 0; 2001 count++; 2002 2003 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { 2004 if (!(rrd->err_flg & 2005 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM 2006 | ERR_FLAG_LEN))) { 2007 /* packet error, don't need upstream */ 2008 buffer_info->alloced = 0; 2009 rrd->xsz.valid = 0; 2010 continue; 2011 } 2012 } 2013 2014 /* Good Receive */ 2015 pci_unmap_page(adapter->pdev, buffer_info->dma, 2016 buffer_info->length, PCI_DMA_FROMDEVICE); 2017 buffer_info->dma = 0; 2018 skb = buffer_info->skb; 2019 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size); 2020 2021 skb_put(skb, length - ETH_FCS_LEN); 2022 2023 /* Receive Checksum Offload */ 2024 atl1_rx_checksum(adapter, rrd, skb); 2025 skb->protocol = eth_type_trans(skb, adapter->netdev); 2026 2027 if (rrd->pkt_flg & PACKET_FLAG_VLAN_INS) { 2028 u16 vlan_tag = (rrd->vlan_tag >> 4) | 2029 ((rrd->vlan_tag & 7) << 13) | 2030 ((rrd->vlan_tag & 8) << 9); 2031 2032 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 2033 } 2034 netif_receive_skb(skb); 2035 2036 /* let protocol layer free skb */ 2037 buffer_info->skb = NULL; 2038 buffer_info->alloced = 0; 2039 rrd->xsz.valid = 0; 2040 } 2041 2042 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean); 2043 2044 atl1_alloc_rx_buffers(adapter); 2045 2046 /* update mailbox ? */ 2047 if (count) { 2048 u32 tpd_next_to_use; 2049 u32 rfd_next_to_use; 2050 2051 spin_lock(&adapter->mb_lock); 2052 2053 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); 2054 rfd_next_to_use = 2055 atomic_read(&adapter->rfd_ring.next_to_use); 2056 rrd_next_to_clean = 2057 atomic_read(&adapter->rrd_ring.next_to_clean); 2058 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << 2059 MB_RFD_PROD_INDX_SHIFT) | 2060 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << 2061 MB_RRD_CONS_INDX_SHIFT) | 2062 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << 2063 MB_TPD_PROD_INDX_SHIFT); 2064 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); 2065 spin_unlock(&adapter->mb_lock); 2066 } 2067 2068 return count; 2069 } 2070 2071 static int atl1_intr_tx(struct atl1_adapter *adapter) 2072 { 2073 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2074 struct atl1_buffer *buffer_info; 2075 u16 sw_tpd_next_to_clean; 2076 u16 cmb_tpd_next_to_clean; 2077 int count = 0; 2078 2079 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean); 2080 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx); 2081 2082 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) { 2083 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean]; 2084 if (buffer_info->dma) { 2085 pci_unmap_page(adapter->pdev, buffer_info->dma, 2086 buffer_info->length, PCI_DMA_TODEVICE); 2087 buffer_info->dma = 0; 2088 } 2089 2090 if (buffer_info->skb) { 2091 dev_consume_skb_irq(buffer_info->skb); 2092 buffer_info->skb = NULL; 2093 } 2094 2095 if (++sw_tpd_next_to_clean == tpd_ring->count) 2096 sw_tpd_next_to_clean = 0; 2097 2098 count++; 2099 } 2100 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean); 2101 2102 if (netif_queue_stopped(adapter->netdev) && 2103 netif_carrier_ok(adapter->netdev)) 2104 netif_wake_queue(adapter->netdev); 2105 2106 return count; 2107 } 2108 2109 static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring) 2110 { 2111 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean); 2112 u16 next_to_use = atomic_read(&tpd_ring->next_to_use); 2113 return (next_to_clean > next_to_use) ? 2114 next_to_clean - next_to_use - 1 : 2115 tpd_ring->count + next_to_clean - next_to_use - 1; 2116 } 2117 2118 static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb, 2119 struct tx_packet_desc *ptpd) 2120 { 2121 u8 hdr_len, ip_off; 2122 u32 real_len; 2123 2124 if (skb_shinfo(skb)->gso_size) { 2125 int err; 2126 2127 err = skb_cow_head(skb, 0); 2128 if (err < 0) 2129 return err; 2130 2131 if (skb->protocol == htons(ETH_P_IP)) { 2132 struct iphdr *iph = ip_hdr(skb); 2133 2134 real_len = (((unsigned char *)iph - skb->data) + 2135 ntohs(iph->tot_len)); 2136 if (real_len < skb->len) 2137 pskb_trim(skb, real_len); 2138 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb)); 2139 if (skb->len == hdr_len) { 2140 iph->check = 0; 2141 tcp_hdr(skb)->check = 2142 ~csum_tcpudp_magic(iph->saddr, 2143 iph->daddr, tcp_hdrlen(skb), 2144 IPPROTO_TCP, 0); 2145 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) << 2146 TPD_IPHL_SHIFT; 2147 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) & 2148 TPD_TCPHDRLEN_MASK) << 2149 TPD_TCPHDRLEN_SHIFT; 2150 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT; 2151 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT; 2152 return 1; 2153 } 2154 2155 iph->check = 0; 2156 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 2157 iph->daddr, 0, IPPROTO_TCP, 0); 2158 ip_off = (unsigned char *)iph - 2159 (unsigned char *) skb_network_header(skb); 2160 if (ip_off == 8) /* 802.3-SNAP frame */ 2161 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; 2162 else if (ip_off != 0) 2163 return -2; 2164 2165 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) << 2166 TPD_IPHL_SHIFT; 2167 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) & 2168 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT; 2169 ptpd->word3 |= (skb_shinfo(skb)->gso_size & 2170 TPD_MSS_MASK) << TPD_MSS_SHIFT; 2171 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT; 2172 return 3; 2173 } 2174 } 2175 return 0; 2176 } 2177 2178 static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb, 2179 struct tx_packet_desc *ptpd) 2180 { 2181 u8 css, cso; 2182 2183 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 2184 css = skb_checksum_start_offset(skb); 2185 cso = css + (u8) skb->csum_offset; 2186 if (unlikely(css & 0x1)) { 2187 /* L1 hardware requires an even number here */ 2188 if (netif_msg_tx_err(adapter)) 2189 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2190 "payload offset not an even number\n"); 2191 return -1; 2192 } 2193 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) << 2194 TPD_PLOADOFFSET_SHIFT; 2195 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) << 2196 TPD_CCSUMOFFSET_SHIFT; 2197 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT; 2198 return true; 2199 } 2200 return 0; 2201 } 2202 2203 static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb, 2204 struct tx_packet_desc *ptpd) 2205 { 2206 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2207 struct atl1_buffer *buffer_info; 2208 u16 buf_len = skb->len; 2209 struct page *page; 2210 unsigned long offset; 2211 unsigned int nr_frags; 2212 unsigned int f; 2213 int retval; 2214 u16 next_to_use; 2215 u16 data_len; 2216 u8 hdr_len; 2217 2218 buf_len -= skb->data_len; 2219 nr_frags = skb_shinfo(skb)->nr_frags; 2220 next_to_use = atomic_read(&tpd_ring->next_to_use); 2221 buffer_info = &tpd_ring->buffer_info[next_to_use]; 2222 BUG_ON(buffer_info->skb); 2223 /* put skb in last TPD */ 2224 buffer_info->skb = NULL; 2225 2226 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK; 2227 if (retval) { 2228 /* TSO */ 2229 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2230 buffer_info->length = hdr_len; 2231 page = virt_to_page(skb->data); 2232 offset = offset_in_page(skb->data); 2233 buffer_info->dma = pci_map_page(adapter->pdev, page, 2234 offset, hdr_len, 2235 PCI_DMA_TODEVICE); 2236 2237 if (++next_to_use == tpd_ring->count) 2238 next_to_use = 0; 2239 2240 if (buf_len > hdr_len) { 2241 int i, nseg; 2242 2243 data_len = buf_len - hdr_len; 2244 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) / 2245 ATL1_MAX_TX_BUF_LEN; 2246 for (i = 0; i < nseg; i++) { 2247 buffer_info = 2248 &tpd_ring->buffer_info[next_to_use]; 2249 buffer_info->skb = NULL; 2250 buffer_info->length = 2251 (ATL1_MAX_TX_BUF_LEN >= 2252 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len; 2253 data_len -= buffer_info->length; 2254 page = virt_to_page(skb->data + 2255 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)); 2256 offset = offset_in_page(skb->data + 2257 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)); 2258 buffer_info->dma = pci_map_page(adapter->pdev, 2259 page, offset, buffer_info->length, 2260 PCI_DMA_TODEVICE); 2261 if (++next_to_use == tpd_ring->count) 2262 next_to_use = 0; 2263 } 2264 } 2265 } else { 2266 /* not TSO */ 2267 buffer_info->length = buf_len; 2268 page = virt_to_page(skb->data); 2269 offset = offset_in_page(skb->data); 2270 buffer_info->dma = pci_map_page(adapter->pdev, page, 2271 offset, buf_len, PCI_DMA_TODEVICE); 2272 if (++next_to_use == tpd_ring->count) 2273 next_to_use = 0; 2274 } 2275 2276 for (f = 0; f < nr_frags; f++) { 2277 const struct skb_frag_struct *frag; 2278 u16 i, nseg; 2279 2280 frag = &skb_shinfo(skb)->frags[f]; 2281 buf_len = skb_frag_size(frag); 2282 2283 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) / 2284 ATL1_MAX_TX_BUF_LEN; 2285 for (i = 0; i < nseg; i++) { 2286 buffer_info = &tpd_ring->buffer_info[next_to_use]; 2287 BUG_ON(buffer_info->skb); 2288 2289 buffer_info->skb = NULL; 2290 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ? 2291 ATL1_MAX_TX_BUF_LEN : buf_len; 2292 buf_len -= buffer_info->length; 2293 buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev, 2294 frag, i * ATL1_MAX_TX_BUF_LEN, 2295 buffer_info->length, DMA_TO_DEVICE); 2296 2297 if (++next_to_use == tpd_ring->count) 2298 next_to_use = 0; 2299 } 2300 } 2301 2302 /* last tpd's buffer-info */ 2303 buffer_info->skb = skb; 2304 } 2305 2306 static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count, 2307 struct tx_packet_desc *ptpd) 2308 { 2309 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2310 struct atl1_buffer *buffer_info; 2311 struct tx_packet_desc *tpd; 2312 u16 j; 2313 u32 val; 2314 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use); 2315 2316 for (j = 0; j < count; j++) { 2317 buffer_info = &tpd_ring->buffer_info[next_to_use]; 2318 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use); 2319 if (tpd != ptpd) 2320 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc)); 2321 tpd->buffer_addr = cpu_to_le64(buffer_info->dma); 2322 tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT); 2323 tpd->word2 |= (cpu_to_le16(buffer_info->length) & 2324 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT; 2325 2326 /* 2327 * if this is the first packet in a TSO chain, set 2328 * TPD_HDRFLAG, otherwise, clear it. 2329 */ 2330 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & 2331 TPD_SEGMENT_EN_MASK; 2332 if (val) { 2333 if (!j) 2334 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT; 2335 else 2336 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT); 2337 } 2338 2339 if (j == (count - 1)) 2340 tpd->word3 |= 1 << TPD_EOP_SHIFT; 2341 2342 if (++next_to_use == tpd_ring->count) 2343 next_to_use = 0; 2344 } 2345 /* 2346 * Force memory writes to complete before letting h/w 2347 * know there are new descriptors to fetch. (Only 2348 * applicable for weak-ordered memory model archs, 2349 * such as IA-64). 2350 */ 2351 wmb(); 2352 2353 atomic_set(&tpd_ring->next_to_use, next_to_use); 2354 } 2355 2356 static netdev_tx_t atl1_xmit_frame(struct sk_buff *skb, 2357 struct net_device *netdev) 2358 { 2359 struct atl1_adapter *adapter = netdev_priv(netdev); 2360 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2361 int len; 2362 int tso; 2363 int count = 1; 2364 int ret_val; 2365 struct tx_packet_desc *ptpd; 2366 u16 vlan_tag; 2367 unsigned int nr_frags = 0; 2368 unsigned int mss = 0; 2369 unsigned int f; 2370 unsigned int proto_hdr_len; 2371 2372 len = skb_headlen(skb); 2373 2374 if (unlikely(skb->len <= 0)) { 2375 dev_kfree_skb_any(skb); 2376 return NETDEV_TX_OK; 2377 } 2378 2379 nr_frags = skb_shinfo(skb)->nr_frags; 2380 for (f = 0; f < nr_frags; f++) { 2381 unsigned int f_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); 2382 count += (f_size + ATL1_MAX_TX_BUF_LEN - 1) / 2383 ATL1_MAX_TX_BUF_LEN; 2384 } 2385 2386 mss = skb_shinfo(skb)->gso_size; 2387 if (mss) { 2388 if (skb->protocol == htons(ETH_P_IP)) { 2389 proto_hdr_len = (skb_transport_offset(skb) + 2390 tcp_hdrlen(skb)); 2391 if (unlikely(proto_hdr_len > len)) { 2392 dev_kfree_skb_any(skb); 2393 return NETDEV_TX_OK; 2394 } 2395 /* need additional TPD ? */ 2396 if (proto_hdr_len != len) 2397 count += (len - proto_hdr_len + 2398 ATL1_MAX_TX_BUF_LEN - 1) / 2399 ATL1_MAX_TX_BUF_LEN; 2400 } 2401 } 2402 2403 if (atl1_tpd_avail(&adapter->tpd_ring) < count) { 2404 /* not enough descriptors */ 2405 netif_stop_queue(netdev); 2406 if (netif_msg_tx_queued(adapter)) 2407 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2408 "tx busy\n"); 2409 return NETDEV_TX_BUSY; 2410 } 2411 2412 ptpd = ATL1_TPD_DESC(tpd_ring, 2413 (u16) atomic_read(&tpd_ring->next_to_use)); 2414 memset(ptpd, 0, sizeof(struct tx_packet_desc)); 2415 2416 if (skb_vlan_tag_present(skb)) { 2417 vlan_tag = skb_vlan_tag_get(skb); 2418 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) | 2419 ((vlan_tag >> 9) & 0x8); 2420 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT; 2421 ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) << 2422 TPD_VLANTAG_SHIFT; 2423 } 2424 2425 tso = atl1_tso(adapter, skb, ptpd); 2426 if (tso < 0) { 2427 dev_kfree_skb_any(skb); 2428 return NETDEV_TX_OK; 2429 } 2430 2431 if (!tso) { 2432 ret_val = atl1_tx_csum(adapter, skb, ptpd); 2433 if (ret_val < 0) { 2434 dev_kfree_skb_any(skb); 2435 return NETDEV_TX_OK; 2436 } 2437 } 2438 2439 atl1_tx_map(adapter, skb, ptpd); 2440 atl1_tx_queue(adapter, count, ptpd); 2441 atl1_update_mailbox(adapter); 2442 mmiowb(); 2443 return NETDEV_TX_OK; 2444 } 2445 2446 static int atl1_rings_clean(struct napi_struct *napi, int budget) 2447 { 2448 struct atl1_adapter *adapter = container_of(napi, struct atl1_adapter, napi); 2449 int work_done = atl1_intr_rx(adapter, budget); 2450 2451 if (atl1_intr_tx(adapter)) 2452 work_done = budget; 2453 2454 /* Let's come again to process some more packets */ 2455 if (work_done >= budget) 2456 return work_done; 2457 2458 napi_complete_done(napi, work_done); 2459 /* re-enable Interrupt */ 2460 if (likely(adapter->int_enabled)) 2461 atlx_imr_set(adapter, IMR_NORMAL_MASK); 2462 return work_done; 2463 } 2464 2465 static inline int atl1_sched_rings_clean(struct atl1_adapter* adapter) 2466 { 2467 if (!napi_schedule_prep(&adapter->napi)) 2468 /* It is possible in case even the RX/TX ints are disabled via IMR 2469 * register the ISR bits are set anyway (but do not produce IRQ). 2470 * To handle such situation the napi functions used to check is 2471 * something scheduled or not. 2472 */ 2473 return 0; 2474 2475 __napi_schedule(&adapter->napi); 2476 2477 /* 2478 * Disable RX/TX ints via IMR register if it is 2479 * allowed. NAPI handler must reenable them in same 2480 * way. 2481 */ 2482 if (!adapter->int_enabled) 2483 return 1; 2484 2485 atlx_imr_set(adapter, IMR_NORXTX_MASK); 2486 return 1; 2487 } 2488 2489 /** 2490 * atl1_intr - Interrupt Handler 2491 * @irq: interrupt number 2492 * @data: pointer to a network interface device structure 2493 */ 2494 static irqreturn_t atl1_intr(int irq, void *data) 2495 { 2496 struct atl1_adapter *adapter = netdev_priv(data); 2497 u32 status; 2498 2499 status = adapter->cmb.cmb->int_stats; 2500 if (!status) 2501 return IRQ_NONE; 2502 2503 /* clear CMB interrupt status at once, 2504 * but leave rx/tx interrupt status in case it should be dropped 2505 * only if rx/tx processing queued. In other case interrupt 2506 * can be lost. 2507 */ 2508 adapter->cmb.cmb->int_stats = status & (ISR_CMB_TX | ISR_CMB_RX); 2509 2510 if (status & ISR_GPHY) /* clear phy status */ 2511 atlx_clear_phy_int(adapter); 2512 2513 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 2514 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR); 2515 2516 /* check if SMB intr */ 2517 if (status & ISR_SMB) 2518 atl1_inc_smb(adapter); 2519 2520 /* check if PCIE PHY Link down */ 2521 if (status & ISR_PHY_LINKDOWN) { 2522 if (netif_msg_intr(adapter)) 2523 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2524 "pcie phy link down %x\n", status); 2525 if (netif_running(adapter->netdev)) { /* reset MAC */ 2526 atlx_irq_disable(adapter); 2527 schedule_work(&adapter->reset_dev_task); 2528 return IRQ_HANDLED; 2529 } 2530 } 2531 2532 /* check if DMA read/write error ? */ 2533 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 2534 if (netif_msg_intr(adapter)) 2535 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2536 "pcie DMA r/w error (status = 0x%x)\n", 2537 status); 2538 atlx_irq_disable(adapter); 2539 schedule_work(&adapter->reset_dev_task); 2540 return IRQ_HANDLED; 2541 } 2542 2543 /* link event */ 2544 if (status & ISR_GPHY) { 2545 adapter->soft_stats.tx_carrier_errors++; 2546 atl1_check_for_link(adapter); 2547 } 2548 2549 /* transmit or receive event */ 2550 if (status & (ISR_CMB_TX | ISR_CMB_RX) && 2551 atl1_sched_rings_clean(adapter)) 2552 adapter->cmb.cmb->int_stats = adapter->cmb.cmb->int_stats & 2553 ~(ISR_CMB_TX | ISR_CMB_RX); 2554 2555 /* rx exception */ 2556 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN | 2557 ISR_RRD_OV | ISR_HOST_RFD_UNRUN | 2558 ISR_HOST_RRD_OV))) { 2559 if (netif_msg_intr(adapter)) 2560 dev_printk(KERN_DEBUG, 2561 &adapter->pdev->dev, 2562 "rx exception, ISR = 0x%x\n", 2563 status); 2564 atl1_sched_rings_clean(adapter); 2565 } 2566 2567 /* re-enable Interrupt */ 2568 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR); 2569 return IRQ_HANDLED; 2570 } 2571 2572 2573 /** 2574 * atl1_phy_config - Timer Call-back 2575 * @data: pointer to netdev cast into an unsigned long 2576 */ 2577 static void atl1_phy_config(struct timer_list *t) 2578 { 2579 struct atl1_adapter *adapter = from_timer(adapter, t, 2580 phy_config_timer); 2581 struct atl1_hw *hw = &adapter->hw; 2582 unsigned long flags; 2583 2584 spin_lock_irqsave(&adapter->lock, flags); 2585 adapter->phy_timer_pending = false; 2586 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 2587 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg); 2588 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN); 2589 spin_unlock_irqrestore(&adapter->lock, flags); 2590 } 2591 2592 /* 2593 * Orphaned vendor comment left intact here: 2594 * <vendor comment> 2595 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT 2596 * will assert. We do soft reset <0x1400=1> according 2597 * with the SPEC. BUT, it seemes that PCIE or DMA 2598 * state-machine will not be reset. DMAR_TO_INT will 2599 * assert again and again. 2600 * </vendor comment> 2601 */ 2602 2603 static int atl1_reset(struct atl1_adapter *adapter) 2604 { 2605 int ret; 2606 ret = atl1_reset_hw(&adapter->hw); 2607 if (ret) 2608 return ret; 2609 return atl1_init_hw(&adapter->hw); 2610 } 2611 2612 static s32 atl1_up(struct atl1_adapter *adapter) 2613 { 2614 struct net_device *netdev = adapter->netdev; 2615 int err; 2616 int irq_flags = 0; 2617 2618 /* hardware has been reset, we need to reload some things */ 2619 atlx_set_multi(netdev); 2620 atl1_init_ring_ptrs(adapter); 2621 atlx_restore_vlan(adapter); 2622 err = atl1_alloc_rx_buffers(adapter); 2623 if (unlikely(!err)) 2624 /* no RX BUFFER allocated */ 2625 return -ENOMEM; 2626 2627 if (unlikely(atl1_configure(adapter))) { 2628 err = -EIO; 2629 goto err_up; 2630 } 2631 2632 err = pci_enable_msi(adapter->pdev); 2633 if (err) { 2634 if (netif_msg_ifup(adapter)) 2635 dev_info(&adapter->pdev->dev, 2636 "Unable to enable MSI: %d\n", err); 2637 irq_flags |= IRQF_SHARED; 2638 } 2639 2640 err = request_irq(adapter->pdev->irq, atl1_intr, irq_flags, 2641 netdev->name, netdev); 2642 if (unlikely(err)) 2643 goto err_up; 2644 2645 napi_enable(&adapter->napi); 2646 atlx_irq_enable(adapter); 2647 atl1_check_link(adapter); 2648 netif_start_queue(netdev); 2649 return 0; 2650 2651 err_up: 2652 pci_disable_msi(adapter->pdev); 2653 /* free rx_buffers */ 2654 atl1_clean_rx_ring(adapter); 2655 return err; 2656 } 2657 2658 static void atl1_down(struct atl1_adapter *adapter) 2659 { 2660 struct net_device *netdev = adapter->netdev; 2661 2662 napi_disable(&adapter->napi); 2663 netif_stop_queue(netdev); 2664 del_timer_sync(&adapter->phy_config_timer); 2665 adapter->phy_timer_pending = false; 2666 2667 atlx_irq_disable(adapter); 2668 free_irq(adapter->pdev->irq, netdev); 2669 pci_disable_msi(adapter->pdev); 2670 atl1_reset_hw(&adapter->hw); 2671 adapter->cmb.cmb->int_stats = 0; 2672 2673 adapter->link_speed = SPEED_0; 2674 adapter->link_duplex = -1; 2675 netif_carrier_off(netdev); 2676 2677 atl1_clean_tx_ring(adapter); 2678 atl1_clean_rx_ring(adapter); 2679 } 2680 2681 static void atl1_reset_dev_task(struct work_struct *work) 2682 { 2683 struct atl1_adapter *adapter = 2684 container_of(work, struct atl1_adapter, reset_dev_task); 2685 struct net_device *netdev = adapter->netdev; 2686 2687 netif_device_detach(netdev); 2688 atl1_down(adapter); 2689 atl1_up(adapter); 2690 netif_device_attach(netdev); 2691 } 2692 2693 /** 2694 * atl1_change_mtu - Change the Maximum Transfer Unit 2695 * @netdev: network interface device structure 2696 * @new_mtu: new value for maximum frame size 2697 * 2698 * Returns 0 on success, negative on failure 2699 */ 2700 static int atl1_change_mtu(struct net_device *netdev, int new_mtu) 2701 { 2702 struct atl1_adapter *adapter = netdev_priv(netdev); 2703 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 2704 2705 adapter->hw.max_frame_size = max_frame; 2706 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3; 2707 adapter->rx_buffer_len = (max_frame + 7) & ~7; 2708 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8; 2709 2710 netdev->mtu = new_mtu; 2711 if (netif_running(netdev)) { 2712 atl1_down(adapter); 2713 atl1_up(adapter); 2714 } 2715 2716 return 0; 2717 } 2718 2719 /** 2720 * atl1_open - Called when a network interface is made active 2721 * @netdev: network interface device structure 2722 * 2723 * Returns 0 on success, negative value on failure 2724 * 2725 * The open entry point is called when a network interface is made 2726 * active by the system (IFF_UP). At this point all resources needed 2727 * for transmit and receive operations are allocated, the interrupt 2728 * handler is registered with the OS, the watchdog timer is started, 2729 * and the stack is notified that the interface is ready. 2730 */ 2731 static int atl1_open(struct net_device *netdev) 2732 { 2733 struct atl1_adapter *adapter = netdev_priv(netdev); 2734 int err; 2735 2736 netif_carrier_off(netdev); 2737 2738 /* allocate transmit descriptors */ 2739 err = atl1_setup_ring_resources(adapter); 2740 if (err) 2741 return err; 2742 2743 err = atl1_up(adapter); 2744 if (err) 2745 goto err_up; 2746 2747 return 0; 2748 2749 err_up: 2750 atl1_reset(adapter); 2751 return err; 2752 } 2753 2754 /** 2755 * atl1_close - Disables a network interface 2756 * @netdev: network interface device structure 2757 * 2758 * Returns 0, this is not allowed to fail 2759 * 2760 * The close entry point is called when an interface is de-activated 2761 * by the OS. The hardware is still under the drivers control, but 2762 * needs to be disabled. A global MAC reset is issued to stop the 2763 * hardware, and all transmit and receive resources are freed. 2764 */ 2765 static int atl1_close(struct net_device *netdev) 2766 { 2767 struct atl1_adapter *adapter = netdev_priv(netdev); 2768 atl1_down(adapter); 2769 atl1_free_ring_resources(adapter); 2770 return 0; 2771 } 2772 2773 #ifdef CONFIG_PM_SLEEP 2774 static int atl1_suspend(struct device *dev) 2775 { 2776 struct pci_dev *pdev = to_pci_dev(dev); 2777 struct net_device *netdev = pci_get_drvdata(pdev); 2778 struct atl1_adapter *adapter = netdev_priv(netdev); 2779 struct atl1_hw *hw = &adapter->hw; 2780 u32 ctrl = 0; 2781 u32 wufc = adapter->wol; 2782 u32 val; 2783 u16 speed; 2784 u16 duplex; 2785 2786 netif_device_detach(netdev); 2787 if (netif_running(netdev)) 2788 atl1_down(adapter); 2789 2790 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); 2791 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); 2792 val = ctrl & BMSR_LSTATUS; 2793 if (val) 2794 wufc &= ~ATLX_WUFC_LNKC; 2795 if (!wufc) 2796 goto disable_wol; 2797 2798 if (val) { 2799 val = atl1_get_speed_and_duplex(hw, &speed, &duplex); 2800 if (val) { 2801 if (netif_msg_ifdown(adapter)) 2802 dev_printk(KERN_DEBUG, &pdev->dev, 2803 "error getting speed/duplex\n"); 2804 goto disable_wol; 2805 } 2806 2807 ctrl = 0; 2808 2809 /* enable magic packet WOL */ 2810 if (wufc & ATLX_WUFC_MAG) 2811 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); 2812 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); 2813 ioread32(hw->hw_addr + REG_WOL_CTRL); 2814 2815 /* configure the mac */ 2816 ctrl = MAC_CTRL_RX_EN; 2817 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 : 2818 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT); 2819 if (duplex == FULL_DUPLEX) 2820 ctrl |= MAC_CTRL_DUPLX; 2821 ctrl |= (((u32)adapter->hw.preamble_len & 2822 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 2823 __atlx_vlan_mode(netdev->features, &ctrl); 2824 if (wufc & ATLX_WUFC_MAG) 2825 ctrl |= MAC_CTRL_BC_EN; 2826 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL); 2827 ioread32(hw->hw_addr + REG_MAC_CTRL); 2828 2829 /* poke the PHY */ 2830 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2831 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 2832 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); 2833 ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2834 } else { 2835 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 2836 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); 2837 ioread32(hw->hw_addr + REG_WOL_CTRL); 2838 iowrite32(0, hw->hw_addr + REG_MAC_CTRL); 2839 ioread32(hw->hw_addr + REG_MAC_CTRL); 2840 hw->phy_configured = false; 2841 } 2842 2843 return 0; 2844 2845 disable_wol: 2846 iowrite32(0, hw->hw_addr + REG_WOL_CTRL); 2847 ioread32(hw->hw_addr + REG_WOL_CTRL); 2848 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2849 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 2850 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); 2851 ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2852 hw->phy_configured = false; 2853 2854 return 0; 2855 } 2856 2857 static int atl1_resume(struct device *dev) 2858 { 2859 struct pci_dev *pdev = to_pci_dev(dev); 2860 struct net_device *netdev = pci_get_drvdata(pdev); 2861 struct atl1_adapter *adapter = netdev_priv(netdev); 2862 2863 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL); 2864 2865 atl1_reset_hw(&adapter->hw); 2866 2867 if (netif_running(netdev)) { 2868 adapter->cmb.cmb->int_stats = 0; 2869 atl1_up(adapter); 2870 } 2871 netif_device_attach(netdev); 2872 2873 return 0; 2874 } 2875 #endif 2876 2877 static SIMPLE_DEV_PM_OPS(atl1_pm_ops, atl1_suspend, atl1_resume); 2878 2879 static void atl1_shutdown(struct pci_dev *pdev) 2880 { 2881 struct net_device *netdev = pci_get_drvdata(pdev); 2882 struct atl1_adapter *adapter = netdev_priv(netdev); 2883 2884 #ifdef CONFIG_PM_SLEEP 2885 atl1_suspend(&pdev->dev); 2886 #endif 2887 pci_wake_from_d3(pdev, adapter->wol); 2888 pci_set_power_state(pdev, PCI_D3hot); 2889 } 2890 2891 #ifdef CONFIG_NET_POLL_CONTROLLER 2892 static void atl1_poll_controller(struct net_device *netdev) 2893 { 2894 disable_irq(netdev->irq); 2895 atl1_intr(netdev->irq, netdev); 2896 enable_irq(netdev->irq); 2897 } 2898 #endif 2899 2900 static const struct net_device_ops atl1_netdev_ops = { 2901 .ndo_open = atl1_open, 2902 .ndo_stop = atl1_close, 2903 .ndo_start_xmit = atl1_xmit_frame, 2904 .ndo_set_rx_mode = atlx_set_multi, 2905 .ndo_validate_addr = eth_validate_addr, 2906 .ndo_set_mac_address = atl1_set_mac, 2907 .ndo_change_mtu = atl1_change_mtu, 2908 .ndo_fix_features = atlx_fix_features, 2909 .ndo_set_features = atlx_set_features, 2910 .ndo_do_ioctl = atlx_ioctl, 2911 .ndo_tx_timeout = atlx_tx_timeout, 2912 #ifdef CONFIG_NET_POLL_CONTROLLER 2913 .ndo_poll_controller = atl1_poll_controller, 2914 #endif 2915 }; 2916 2917 /** 2918 * atl1_probe - Device Initialization Routine 2919 * @pdev: PCI device information struct 2920 * @ent: entry in atl1_pci_tbl 2921 * 2922 * Returns 0 on success, negative on failure 2923 * 2924 * atl1_probe initializes an adapter identified by a pci_dev structure. 2925 * The OS initialization, configuring of the adapter private structure, 2926 * and a hardware reset occur. 2927 */ 2928 static int atl1_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2929 { 2930 struct net_device *netdev; 2931 struct atl1_adapter *adapter; 2932 static int cards_found = 0; 2933 int err; 2934 2935 err = pci_enable_device(pdev); 2936 if (err) 2937 return err; 2938 2939 /* 2940 * The atl1 chip can DMA to 64-bit addresses, but it uses a single 2941 * shared register for the high 32 bits, so only a single, aligned, 2942 * 4 GB physical address range can be used at a time. 2943 * 2944 * Supporting 64-bit DMA on this hardware is more trouble than it's 2945 * worth. It is far easier to limit to 32-bit DMA than update 2946 * various kernel subsystems to support the mechanics required by a 2947 * fixed-high-32-bit system. 2948 */ 2949 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2950 if (err) { 2951 dev_err(&pdev->dev, "no usable DMA configuration\n"); 2952 goto err_dma; 2953 } 2954 /* 2955 * Mark all PCI regions associated with PCI device 2956 * pdev as being reserved by owner atl1_driver_name 2957 */ 2958 err = pci_request_regions(pdev, ATLX_DRIVER_NAME); 2959 if (err) 2960 goto err_request_regions; 2961 2962 /* 2963 * Enables bus-mastering on the device and calls 2964 * pcibios_set_master to do the needed arch specific settings 2965 */ 2966 pci_set_master(pdev); 2967 2968 netdev = alloc_etherdev(sizeof(struct atl1_adapter)); 2969 if (!netdev) { 2970 err = -ENOMEM; 2971 goto err_alloc_etherdev; 2972 } 2973 SET_NETDEV_DEV(netdev, &pdev->dev); 2974 2975 pci_set_drvdata(pdev, netdev); 2976 adapter = netdev_priv(netdev); 2977 adapter->netdev = netdev; 2978 adapter->pdev = pdev; 2979 adapter->hw.back = adapter; 2980 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg); 2981 2982 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0); 2983 if (!adapter->hw.hw_addr) { 2984 err = -EIO; 2985 goto err_pci_iomap; 2986 } 2987 /* get device revision number */ 2988 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr + 2989 (REG_MASTER_CTRL + 2)); 2990 if (netif_msg_probe(adapter)) 2991 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION); 2992 2993 /* set default ring resource counts */ 2994 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD; 2995 adapter->tpd_ring.count = ATL1_DEFAULT_TPD; 2996 2997 adapter->mii.dev = netdev; 2998 adapter->mii.mdio_read = mdio_read; 2999 adapter->mii.mdio_write = mdio_write; 3000 adapter->mii.phy_id_mask = 0x1f; 3001 adapter->mii.reg_num_mask = 0x1f; 3002 3003 netdev->netdev_ops = &atl1_netdev_ops; 3004 netdev->watchdog_timeo = 5 * HZ; 3005 netif_napi_add(netdev, &adapter->napi, atl1_rings_clean, 64); 3006 3007 netdev->ethtool_ops = &atl1_ethtool_ops; 3008 adapter->bd_number = cards_found; 3009 3010 /* setup the private structure */ 3011 err = atl1_sw_init(adapter); 3012 if (err) 3013 goto err_common; 3014 3015 netdev->features = NETIF_F_HW_CSUM; 3016 netdev->features |= NETIF_F_SG; 3017 netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 3018 3019 netdev->hw_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_TSO | 3020 NETIF_F_HW_VLAN_CTAG_RX; 3021 3022 /* is this valid? see atl1_setup_mac_ctrl() */ 3023 netdev->features |= NETIF_F_RXCSUM; 3024 3025 /* MTU range: 42 - 10218 */ 3026 netdev->min_mtu = ETH_ZLEN - (ETH_HLEN + VLAN_HLEN); 3027 netdev->max_mtu = MAX_JUMBO_FRAME_SIZE - 3028 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); 3029 3030 /* 3031 * patch for some L1 of old version, 3032 * the final version of L1 may not need these 3033 * patches 3034 */ 3035 /* atl1_pcie_patch(adapter); */ 3036 3037 /* really reset GPHY core */ 3038 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); 3039 3040 /* 3041 * reset the controller to 3042 * put the device in a known good starting state 3043 */ 3044 if (atl1_reset_hw(&adapter->hw)) { 3045 err = -EIO; 3046 goto err_common; 3047 } 3048 3049 /* copy the MAC address out of the EEPROM */ 3050 if (atl1_read_mac_addr(&adapter->hw)) { 3051 /* mark random mac */ 3052 netdev->addr_assign_type = NET_ADDR_RANDOM; 3053 } 3054 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); 3055 3056 if (!is_valid_ether_addr(netdev->dev_addr)) { 3057 err = -EIO; 3058 goto err_common; 3059 } 3060 3061 atl1_check_options(adapter); 3062 3063 /* pre-init the MAC, and setup link */ 3064 err = atl1_init_hw(&adapter->hw); 3065 if (err) { 3066 err = -EIO; 3067 goto err_common; 3068 } 3069 3070 atl1_pcie_patch(adapter); 3071 /* assume we have no link for now */ 3072 netif_carrier_off(netdev); 3073 3074 timer_setup(&adapter->phy_config_timer, atl1_phy_config, 0); 3075 adapter->phy_timer_pending = false; 3076 3077 INIT_WORK(&adapter->reset_dev_task, atl1_reset_dev_task); 3078 3079 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task); 3080 3081 err = register_netdev(netdev); 3082 if (err) 3083 goto err_common; 3084 3085 cards_found++; 3086 atl1_via_workaround(adapter); 3087 return 0; 3088 3089 err_common: 3090 pci_iounmap(pdev, adapter->hw.hw_addr); 3091 err_pci_iomap: 3092 free_netdev(netdev); 3093 err_alloc_etherdev: 3094 pci_release_regions(pdev); 3095 err_dma: 3096 err_request_regions: 3097 pci_disable_device(pdev); 3098 return err; 3099 } 3100 3101 /** 3102 * atl1_remove - Device Removal Routine 3103 * @pdev: PCI device information struct 3104 * 3105 * atl1_remove is called by the PCI subsystem to alert the driver 3106 * that it should release a PCI device. The could be caused by a 3107 * Hot-Plug event, or because the driver is going to be removed from 3108 * memory. 3109 */ 3110 static void atl1_remove(struct pci_dev *pdev) 3111 { 3112 struct net_device *netdev = pci_get_drvdata(pdev); 3113 struct atl1_adapter *adapter; 3114 /* Device not available. Return. */ 3115 if (!netdev) 3116 return; 3117 3118 adapter = netdev_priv(netdev); 3119 3120 /* 3121 * Some atl1 boards lack persistent storage for their MAC, and get it 3122 * from the BIOS during POST. If we've been messing with the MAC 3123 * address, we need to save the permanent one. 3124 */ 3125 if (!ether_addr_equal_unaligned(adapter->hw.mac_addr, 3126 adapter->hw.perm_mac_addr)) { 3127 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, 3128 ETH_ALEN); 3129 atl1_set_mac_addr(&adapter->hw); 3130 } 3131 3132 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); 3133 unregister_netdev(netdev); 3134 pci_iounmap(pdev, adapter->hw.hw_addr); 3135 pci_release_regions(pdev); 3136 free_netdev(netdev); 3137 pci_disable_device(pdev); 3138 } 3139 3140 static struct pci_driver atl1_driver = { 3141 .name = ATLX_DRIVER_NAME, 3142 .id_table = atl1_pci_tbl, 3143 .probe = atl1_probe, 3144 .remove = atl1_remove, 3145 .shutdown = atl1_shutdown, 3146 .driver.pm = &atl1_pm_ops, 3147 }; 3148 3149 struct atl1_stats { 3150 char stat_string[ETH_GSTRING_LEN]; 3151 int sizeof_stat; 3152 int stat_offset; 3153 }; 3154 3155 #define ATL1_STAT(m) \ 3156 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m) 3157 3158 static struct atl1_stats atl1_gstrings_stats[] = { 3159 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)}, 3160 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)}, 3161 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)}, 3162 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)}, 3163 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)}, 3164 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)}, 3165 {"multicast", ATL1_STAT(soft_stats.multicast)}, 3166 {"collisions", ATL1_STAT(soft_stats.collisions)}, 3167 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)}, 3168 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)}, 3169 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)}, 3170 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)}, 3171 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)}, 3172 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)}, 3173 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)}, 3174 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)}, 3175 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)}, 3176 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)}, 3177 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)}, 3178 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)}, 3179 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)}, 3180 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)}, 3181 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)}, 3182 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)}, 3183 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)}, 3184 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)}, 3185 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)}, 3186 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)}, 3187 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)} 3188 }; 3189 3190 static void atl1_get_ethtool_stats(struct net_device *netdev, 3191 struct ethtool_stats *stats, u64 *data) 3192 { 3193 struct atl1_adapter *adapter = netdev_priv(netdev); 3194 int i; 3195 char *p; 3196 3197 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) { 3198 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset; 3199 data[i] = (atl1_gstrings_stats[i].sizeof_stat == 3200 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 3201 } 3202 3203 } 3204 3205 static int atl1_get_sset_count(struct net_device *netdev, int sset) 3206 { 3207 switch (sset) { 3208 case ETH_SS_STATS: 3209 return ARRAY_SIZE(atl1_gstrings_stats); 3210 default: 3211 return -EOPNOTSUPP; 3212 } 3213 } 3214 3215 static int atl1_get_link_ksettings(struct net_device *netdev, 3216 struct ethtool_link_ksettings *cmd) 3217 { 3218 struct atl1_adapter *adapter = netdev_priv(netdev); 3219 struct atl1_hw *hw = &adapter->hw; 3220 u32 supported, advertising; 3221 3222 supported = (SUPPORTED_10baseT_Half | 3223 SUPPORTED_10baseT_Full | 3224 SUPPORTED_100baseT_Half | 3225 SUPPORTED_100baseT_Full | 3226 SUPPORTED_1000baseT_Full | 3227 SUPPORTED_Autoneg | SUPPORTED_TP); 3228 advertising = ADVERTISED_TP; 3229 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3230 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3231 advertising |= ADVERTISED_Autoneg; 3232 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) { 3233 advertising |= ADVERTISED_Autoneg; 3234 advertising |= 3235 (ADVERTISED_10baseT_Half | 3236 ADVERTISED_10baseT_Full | 3237 ADVERTISED_100baseT_Half | 3238 ADVERTISED_100baseT_Full | 3239 ADVERTISED_1000baseT_Full); 3240 } else 3241 advertising |= (ADVERTISED_1000baseT_Full); 3242 } 3243 cmd->base.port = PORT_TP; 3244 cmd->base.phy_address = 0; 3245 3246 if (netif_carrier_ok(adapter->netdev)) { 3247 u16 link_speed, link_duplex; 3248 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex); 3249 cmd->base.speed = link_speed; 3250 if (link_duplex == FULL_DUPLEX) 3251 cmd->base.duplex = DUPLEX_FULL; 3252 else 3253 cmd->base.duplex = DUPLEX_HALF; 3254 } else { 3255 cmd->base.speed = SPEED_UNKNOWN; 3256 cmd->base.duplex = DUPLEX_UNKNOWN; 3257 } 3258 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3259 hw->media_type == MEDIA_TYPE_1000M_FULL) 3260 cmd->base.autoneg = AUTONEG_ENABLE; 3261 else 3262 cmd->base.autoneg = AUTONEG_DISABLE; 3263 3264 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3265 supported); 3266 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3267 advertising); 3268 3269 return 0; 3270 } 3271 3272 static int atl1_set_link_ksettings(struct net_device *netdev, 3273 const struct ethtool_link_ksettings *cmd) 3274 { 3275 struct atl1_adapter *adapter = netdev_priv(netdev); 3276 struct atl1_hw *hw = &adapter->hw; 3277 u16 phy_data; 3278 int ret_val = 0; 3279 u16 old_media_type = hw->media_type; 3280 3281 if (netif_running(adapter->netdev)) { 3282 if (netif_msg_link(adapter)) 3283 dev_dbg(&adapter->pdev->dev, 3284 "ethtool shutting down adapter\n"); 3285 atl1_down(adapter); 3286 } 3287 3288 if (cmd->base.autoneg == AUTONEG_ENABLE) 3289 hw->media_type = MEDIA_TYPE_AUTO_SENSOR; 3290 else { 3291 u32 speed = cmd->base.speed; 3292 if (speed == SPEED_1000) { 3293 if (cmd->base.duplex != DUPLEX_FULL) { 3294 if (netif_msg_link(adapter)) 3295 dev_warn(&adapter->pdev->dev, 3296 "1000M half is invalid\n"); 3297 ret_val = -EINVAL; 3298 goto exit_sset; 3299 } 3300 hw->media_type = MEDIA_TYPE_1000M_FULL; 3301 } else if (speed == SPEED_100) { 3302 if (cmd->base.duplex == DUPLEX_FULL) 3303 hw->media_type = MEDIA_TYPE_100M_FULL; 3304 else 3305 hw->media_type = MEDIA_TYPE_100M_HALF; 3306 } else { 3307 if (cmd->base.duplex == DUPLEX_FULL) 3308 hw->media_type = MEDIA_TYPE_10M_FULL; 3309 else 3310 hw->media_type = MEDIA_TYPE_10M_HALF; 3311 } 3312 } 3313 3314 if (atl1_phy_setup_autoneg_adv(hw)) { 3315 ret_val = -EINVAL; 3316 if (netif_msg_link(adapter)) 3317 dev_warn(&adapter->pdev->dev, 3318 "invalid ethtool speed/duplex setting\n"); 3319 goto exit_sset; 3320 } 3321 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3322 hw->media_type == MEDIA_TYPE_1000M_FULL) 3323 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 3324 else { 3325 switch (hw->media_type) { 3326 case MEDIA_TYPE_100M_FULL: 3327 phy_data = 3328 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | 3329 MII_CR_RESET; 3330 break; 3331 case MEDIA_TYPE_100M_HALF: 3332 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 3333 break; 3334 case MEDIA_TYPE_10M_FULL: 3335 phy_data = 3336 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 3337 break; 3338 default: 3339 /* MEDIA_TYPE_10M_HALF: */ 3340 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 3341 break; 3342 } 3343 } 3344 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 3345 exit_sset: 3346 if (ret_val) 3347 hw->media_type = old_media_type; 3348 3349 if (netif_running(adapter->netdev)) { 3350 if (netif_msg_link(adapter)) 3351 dev_dbg(&adapter->pdev->dev, 3352 "ethtool starting adapter\n"); 3353 atl1_up(adapter); 3354 } else if (!ret_val) { 3355 if (netif_msg_link(adapter)) 3356 dev_dbg(&adapter->pdev->dev, 3357 "ethtool resetting adapter\n"); 3358 atl1_reset(adapter); 3359 } 3360 return ret_val; 3361 } 3362 3363 static void atl1_get_drvinfo(struct net_device *netdev, 3364 struct ethtool_drvinfo *drvinfo) 3365 { 3366 struct atl1_adapter *adapter = netdev_priv(netdev); 3367 3368 strlcpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver)); 3369 strlcpy(drvinfo->version, ATLX_DRIVER_VERSION, 3370 sizeof(drvinfo->version)); 3371 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 3372 sizeof(drvinfo->bus_info)); 3373 } 3374 3375 static void atl1_get_wol(struct net_device *netdev, 3376 struct ethtool_wolinfo *wol) 3377 { 3378 struct atl1_adapter *adapter = netdev_priv(netdev); 3379 3380 wol->supported = WAKE_MAGIC; 3381 wol->wolopts = 0; 3382 if (adapter->wol & ATLX_WUFC_MAG) 3383 wol->wolopts |= WAKE_MAGIC; 3384 } 3385 3386 static int atl1_set_wol(struct net_device *netdev, 3387 struct ethtool_wolinfo *wol) 3388 { 3389 struct atl1_adapter *adapter = netdev_priv(netdev); 3390 3391 if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | 3392 WAKE_ARP | WAKE_MAGICSECURE)) 3393 return -EOPNOTSUPP; 3394 adapter->wol = 0; 3395 if (wol->wolopts & WAKE_MAGIC) 3396 adapter->wol |= ATLX_WUFC_MAG; 3397 3398 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 3399 3400 return 0; 3401 } 3402 3403 static u32 atl1_get_msglevel(struct net_device *netdev) 3404 { 3405 struct atl1_adapter *adapter = netdev_priv(netdev); 3406 return adapter->msg_enable; 3407 } 3408 3409 static void atl1_set_msglevel(struct net_device *netdev, u32 value) 3410 { 3411 struct atl1_adapter *adapter = netdev_priv(netdev); 3412 adapter->msg_enable = value; 3413 } 3414 3415 static int atl1_get_regs_len(struct net_device *netdev) 3416 { 3417 return ATL1_REG_COUNT * sizeof(u32); 3418 } 3419 3420 static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs, 3421 void *p) 3422 { 3423 struct atl1_adapter *adapter = netdev_priv(netdev); 3424 struct atl1_hw *hw = &adapter->hw; 3425 unsigned int i; 3426 u32 *regbuf = p; 3427 3428 for (i = 0; i < ATL1_REG_COUNT; i++) { 3429 /* 3430 * This switch statement avoids reserved regions 3431 * of register space. 3432 */ 3433 switch (i) { 3434 case 6 ... 9: 3435 case 14: 3436 case 29 ... 31: 3437 case 34 ... 63: 3438 case 75 ... 127: 3439 case 136 ... 1023: 3440 case 1027 ... 1087: 3441 case 1091 ... 1151: 3442 case 1194 ... 1195: 3443 case 1200 ... 1201: 3444 case 1206 ... 1213: 3445 case 1216 ... 1279: 3446 case 1290 ... 1311: 3447 case 1323 ... 1343: 3448 case 1358 ... 1359: 3449 case 1368 ... 1375: 3450 case 1378 ... 1383: 3451 case 1388 ... 1391: 3452 case 1393 ... 1395: 3453 case 1402 ... 1403: 3454 case 1410 ... 1471: 3455 case 1522 ... 1535: 3456 /* reserved region; don't read it */ 3457 regbuf[i] = 0; 3458 break; 3459 default: 3460 /* unreserved region */ 3461 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32))); 3462 } 3463 } 3464 } 3465 3466 static void atl1_get_ringparam(struct net_device *netdev, 3467 struct ethtool_ringparam *ring) 3468 { 3469 struct atl1_adapter *adapter = netdev_priv(netdev); 3470 struct atl1_tpd_ring *txdr = &adapter->tpd_ring; 3471 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring; 3472 3473 ring->rx_max_pending = ATL1_MAX_RFD; 3474 ring->tx_max_pending = ATL1_MAX_TPD; 3475 ring->rx_pending = rxdr->count; 3476 ring->tx_pending = txdr->count; 3477 } 3478 3479 static int atl1_set_ringparam(struct net_device *netdev, 3480 struct ethtool_ringparam *ring) 3481 { 3482 struct atl1_adapter *adapter = netdev_priv(netdev); 3483 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring; 3484 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring; 3485 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring; 3486 3487 struct atl1_tpd_ring tpd_old, tpd_new; 3488 struct atl1_rfd_ring rfd_old, rfd_new; 3489 struct atl1_rrd_ring rrd_old, rrd_new; 3490 struct atl1_ring_header rhdr_old, rhdr_new; 3491 struct atl1_smb smb; 3492 struct atl1_cmb cmb; 3493 int err; 3494 3495 tpd_old = adapter->tpd_ring; 3496 rfd_old = adapter->rfd_ring; 3497 rrd_old = adapter->rrd_ring; 3498 rhdr_old = adapter->ring_header; 3499 3500 if (netif_running(adapter->netdev)) 3501 atl1_down(adapter); 3502 3503 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD); 3504 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD : 3505 rfdr->count; 3506 rfdr->count = (rfdr->count + 3) & ~3; 3507 rrdr->count = rfdr->count; 3508 3509 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD); 3510 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD : 3511 tpdr->count; 3512 tpdr->count = (tpdr->count + 3) & ~3; 3513 3514 if (netif_running(adapter->netdev)) { 3515 /* try to get new resources before deleting old */ 3516 err = atl1_setup_ring_resources(adapter); 3517 if (err) 3518 goto err_setup_ring; 3519 3520 /* 3521 * save the new, restore the old in order to free it, 3522 * then restore the new back again 3523 */ 3524 3525 rfd_new = adapter->rfd_ring; 3526 rrd_new = adapter->rrd_ring; 3527 tpd_new = adapter->tpd_ring; 3528 rhdr_new = adapter->ring_header; 3529 adapter->rfd_ring = rfd_old; 3530 adapter->rrd_ring = rrd_old; 3531 adapter->tpd_ring = tpd_old; 3532 adapter->ring_header = rhdr_old; 3533 /* 3534 * Save SMB and CMB, since atl1_free_ring_resources 3535 * will clear them. 3536 */ 3537 smb = adapter->smb; 3538 cmb = adapter->cmb; 3539 atl1_free_ring_resources(adapter); 3540 adapter->rfd_ring = rfd_new; 3541 adapter->rrd_ring = rrd_new; 3542 adapter->tpd_ring = tpd_new; 3543 adapter->ring_header = rhdr_new; 3544 adapter->smb = smb; 3545 adapter->cmb = cmb; 3546 3547 err = atl1_up(adapter); 3548 if (err) 3549 return err; 3550 } 3551 return 0; 3552 3553 err_setup_ring: 3554 adapter->rfd_ring = rfd_old; 3555 adapter->rrd_ring = rrd_old; 3556 adapter->tpd_ring = tpd_old; 3557 adapter->ring_header = rhdr_old; 3558 atl1_up(adapter); 3559 return err; 3560 } 3561 3562 static void atl1_get_pauseparam(struct net_device *netdev, 3563 struct ethtool_pauseparam *epause) 3564 { 3565 struct atl1_adapter *adapter = netdev_priv(netdev); 3566 struct atl1_hw *hw = &adapter->hw; 3567 3568 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3569 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3570 epause->autoneg = AUTONEG_ENABLE; 3571 } else { 3572 epause->autoneg = AUTONEG_DISABLE; 3573 } 3574 epause->rx_pause = 1; 3575 epause->tx_pause = 1; 3576 } 3577 3578 static int atl1_set_pauseparam(struct net_device *netdev, 3579 struct ethtool_pauseparam *epause) 3580 { 3581 struct atl1_adapter *adapter = netdev_priv(netdev); 3582 struct atl1_hw *hw = &adapter->hw; 3583 3584 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3585 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3586 epause->autoneg = AUTONEG_ENABLE; 3587 } else { 3588 epause->autoneg = AUTONEG_DISABLE; 3589 } 3590 3591 epause->rx_pause = 1; 3592 epause->tx_pause = 1; 3593 3594 return 0; 3595 } 3596 3597 static void atl1_get_strings(struct net_device *netdev, u32 stringset, 3598 u8 *data) 3599 { 3600 u8 *p = data; 3601 int i; 3602 3603 switch (stringset) { 3604 case ETH_SS_STATS: 3605 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) { 3606 memcpy(p, atl1_gstrings_stats[i].stat_string, 3607 ETH_GSTRING_LEN); 3608 p += ETH_GSTRING_LEN; 3609 } 3610 break; 3611 } 3612 } 3613 3614 static int atl1_nway_reset(struct net_device *netdev) 3615 { 3616 struct atl1_adapter *adapter = netdev_priv(netdev); 3617 struct atl1_hw *hw = &adapter->hw; 3618 3619 if (netif_running(netdev)) { 3620 u16 phy_data; 3621 atl1_down(adapter); 3622 3623 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3624 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3625 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 3626 } else { 3627 switch (hw->media_type) { 3628 case MEDIA_TYPE_100M_FULL: 3629 phy_data = MII_CR_FULL_DUPLEX | 3630 MII_CR_SPEED_100 | MII_CR_RESET; 3631 break; 3632 case MEDIA_TYPE_100M_HALF: 3633 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 3634 break; 3635 case MEDIA_TYPE_10M_FULL: 3636 phy_data = MII_CR_FULL_DUPLEX | 3637 MII_CR_SPEED_10 | MII_CR_RESET; 3638 break; 3639 default: 3640 /* MEDIA_TYPE_10M_HALF */ 3641 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 3642 } 3643 } 3644 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 3645 atl1_up(adapter); 3646 } 3647 return 0; 3648 } 3649 3650 static const struct ethtool_ops atl1_ethtool_ops = { 3651 .get_drvinfo = atl1_get_drvinfo, 3652 .get_wol = atl1_get_wol, 3653 .set_wol = atl1_set_wol, 3654 .get_msglevel = atl1_get_msglevel, 3655 .set_msglevel = atl1_set_msglevel, 3656 .get_regs_len = atl1_get_regs_len, 3657 .get_regs = atl1_get_regs, 3658 .get_ringparam = atl1_get_ringparam, 3659 .set_ringparam = atl1_set_ringparam, 3660 .get_pauseparam = atl1_get_pauseparam, 3661 .set_pauseparam = atl1_set_pauseparam, 3662 .get_link = ethtool_op_get_link, 3663 .get_strings = atl1_get_strings, 3664 .nway_reset = atl1_nway_reset, 3665 .get_ethtool_stats = atl1_get_ethtool_stats, 3666 .get_sset_count = atl1_get_sset_count, 3667 .get_link_ksettings = atl1_get_link_ksettings, 3668 .set_link_ksettings = atl1_set_link_ksettings, 3669 }; 3670 3671 module_pci_driver(atl1_driver); 3672