1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. 4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com> 5 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com> 6 * 7 * Derived from Intel e1000 driver 8 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 9 * 10 * Contact Information: 11 * Xiong Huang <xiong.huang@atheros.com> 12 * Jie Yang <jie.yang@atheros.com> 13 * Chris Snook <csnook@redhat.com> 14 * Jay Cliburn <jcliburn@gmail.com> 15 * 16 * This version is adapted from the Attansic reference driver. 17 * 18 * TODO: 19 * Add more ethtool functions. 20 * Fix abstruse irq enable/disable condition described here: 21 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2 22 * 23 * NEEDS TESTING: 24 * VLAN 25 * multicast 26 * promiscuous mode 27 * interrupt coalescing 28 * SMP torture testing 29 */ 30 31 #include <linux/atomic.h> 32 #include <asm/byteorder.h> 33 34 #include <linux/compiler.h> 35 #include <linux/crc32.h> 36 #include <linux/delay.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/etherdevice.h> 39 #include <linux/hardirq.h> 40 #include <linux/if_ether.h> 41 #include <linux/if_vlan.h> 42 #include <linux/in.h> 43 #include <linux/interrupt.h> 44 #include <linux/ip.h> 45 #include <linux/irqflags.h> 46 #include <linux/irqreturn.h> 47 #include <linux/jiffies.h> 48 #include <linux/mii.h> 49 #include <linux/module.h> 50 #include <linux/net.h> 51 #include <linux/netdevice.h> 52 #include <linux/pci.h> 53 #include <linux/pci_ids.h> 54 #include <linux/pm.h> 55 #include <linux/skbuff.h> 56 #include <linux/slab.h> 57 #include <linux/spinlock.h> 58 #include <linux/string.h> 59 #include <linux/tcp.h> 60 #include <linux/timer.h> 61 #include <linux/types.h> 62 #include <linux/workqueue.h> 63 64 #include <net/checksum.h> 65 66 #include "atl1.h" 67 68 #define ATLX_DRIVER_VERSION "2.1.3" 69 MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, " 70 "Chris Snook <csnook@redhat.com>, " 71 "Jay Cliburn <jcliburn@gmail.com>"); 72 MODULE_LICENSE("GPL"); 73 MODULE_VERSION(ATLX_DRIVER_VERSION); 74 75 /* Temporary hack for merging atl1 and atl2 */ 76 #include "atlx.c" 77 78 static const struct ethtool_ops atl1_ethtool_ops; 79 80 /* 81 * This is the only thing that needs to be changed to adjust the 82 * maximum number of ports that the driver can manage. 83 */ 84 #define ATL1_MAX_NIC 4 85 86 #define OPTION_UNSET -1 87 #define OPTION_DISABLED 0 88 #define OPTION_ENABLED 1 89 90 #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET } 91 92 /* 93 * Interrupt Moderate Timer in units of 2 us 94 * 95 * Valid Range: 10-65535 96 * 97 * Default Value: 100 (200us) 98 */ 99 static int int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT; 100 static unsigned int num_int_mod_timer; 101 module_param_array_named(int_mod_timer, int_mod_timer, int, 102 &num_int_mod_timer, 0); 103 MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer"); 104 105 #define DEFAULT_INT_MOD_CNT 100 /* 200us */ 106 #define MAX_INT_MOD_CNT 65000 107 #define MIN_INT_MOD_CNT 50 108 109 struct atl1_option { 110 enum { enable_option, range_option, list_option } type; 111 char *name; 112 char *err; 113 int def; 114 union { 115 struct { /* range_option info */ 116 int min; 117 int max; 118 } r; 119 struct { /* list_option info */ 120 int nr; 121 struct atl1_opt_list { 122 int i; 123 char *str; 124 } *p; 125 } l; 126 } arg; 127 }; 128 129 static int atl1_validate_option(int *value, struct atl1_option *opt, 130 struct pci_dev *pdev) 131 { 132 if (*value == OPTION_UNSET) { 133 *value = opt->def; 134 return 0; 135 } 136 137 switch (opt->type) { 138 case enable_option: 139 switch (*value) { 140 case OPTION_ENABLED: 141 dev_info(&pdev->dev, "%s enabled\n", opt->name); 142 return 0; 143 case OPTION_DISABLED: 144 dev_info(&pdev->dev, "%s disabled\n", opt->name); 145 return 0; 146 } 147 break; 148 case range_option: 149 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 150 dev_info(&pdev->dev, "%s set to %i\n", opt->name, 151 *value); 152 return 0; 153 } 154 break; 155 case list_option:{ 156 int i; 157 struct atl1_opt_list *ent; 158 159 for (i = 0; i < opt->arg.l.nr; i++) { 160 ent = &opt->arg.l.p[i]; 161 if (*value == ent->i) { 162 if (ent->str[0] != '\0') 163 dev_info(&pdev->dev, "%s\n", 164 ent->str); 165 return 0; 166 } 167 } 168 } 169 break; 170 171 default: 172 break; 173 } 174 175 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n", 176 opt->name, *value, opt->err); 177 *value = opt->def; 178 return -1; 179 } 180 181 /** 182 * atl1_check_options - Range Checking for Command Line Parameters 183 * @adapter: board private structure 184 * 185 * This routine checks all command line parameters for valid user 186 * input. If an invalid value is given, or if no user specified 187 * value exists, a default value is used. The final value is stored 188 * in a variable in the adapter structure. 189 */ 190 static void atl1_check_options(struct atl1_adapter *adapter) 191 { 192 struct pci_dev *pdev = adapter->pdev; 193 int bd = adapter->bd_number; 194 if (bd >= ATL1_MAX_NIC) { 195 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd); 196 dev_notice(&pdev->dev, "using defaults for all values\n"); 197 } 198 { /* Interrupt Moderate Timer */ 199 struct atl1_option opt = { 200 .type = range_option, 201 .name = "Interrupt Moderator Timer", 202 .err = "using default of " 203 __MODULE_STRING(DEFAULT_INT_MOD_CNT), 204 .def = DEFAULT_INT_MOD_CNT, 205 .arg = {.r = {.min = MIN_INT_MOD_CNT, 206 .max = MAX_INT_MOD_CNT} } 207 }; 208 int val; 209 if (num_int_mod_timer > bd) { 210 val = int_mod_timer[bd]; 211 atl1_validate_option(&val, &opt, pdev); 212 adapter->imt = (u16) val; 213 } else 214 adapter->imt = (u16) (opt.def); 215 } 216 } 217 218 /* 219 * atl1_pci_tbl - PCI Device ID Table 220 */ 221 static const struct pci_device_id atl1_pci_tbl[] = { 222 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)}, 223 /* required last entry */ 224 {0,} 225 }; 226 MODULE_DEVICE_TABLE(pci, atl1_pci_tbl); 227 228 static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | 229 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP; 230 231 static int debug = -1; 232 module_param(debug, int, 0); 233 MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)"); 234 235 /* 236 * Reset the transmit and receive units; mask and clear all interrupts. 237 * hw - Struct containing variables accessed by shared code 238 * return : 0 or idle status (if error) 239 */ 240 static s32 atl1_reset_hw(struct atl1_hw *hw) 241 { 242 struct pci_dev *pdev = hw->back->pdev; 243 struct atl1_adapter *adapter = hw->back; 244 u32 icr; 245 int i; 246 247 /* 248 * Clear Interrupt mask to stop board from generating 249 * interrupts & Clear any pending interrupt events 250 */ 251 /* 252 * atlx_irq_disable(adapter); 253 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR); 254 */ 255 256 /* 257 * Issue Soft Reset to the MAC. This will reset the chip's 258 * transmit, receive, DMA. It will not effect 259 * the current PCI configuration. The global reset bit is self- 260 * clearing, and should clear within a microsecond. 261 */ 262 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL); 263 ioread32(hw->hw_addr + REG_MASTER_CTRL); 264 265 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE); 266 ioread16(hw->hw_addr + REG_PHY_ENABLE); 267 268 /* delay about 1ms */ 269 msleep(1); 270 271 /* Wait at least 10ms for All module to be Idle */ 272 for (i = 0; i < 10; i++) { 273 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS); 274 if (!icr) 275 break; 276 /* delay 1 ms */ 277 msleep(1); 278 /* FIXME: still the right way to do this? */ 279 cpu_relax(); 280 } 281 282 if (icr) { 283 if (netif_msg_hw(adapter)) 284 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr); 285 return icr; 286 } 287 288 return 0; 289 } 290 291 /* function about EEPROM 292 * 293 * check_eeprom_exist 294 * return 0 if eeprom exist 295 */ 296 static int atl1_check_eeprom_exist(struct atl1_hw *hw) 297 { 298 u32 value; 299 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); 300 if (value & SPI_FLASH_CTRL_EN_VPD) { 301 value &= ~SPI_FLASH_CTRL_EN_VPD; 302 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); 303 } 304 305 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST); 306 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 307 } 308 309 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value) 310 { 311 int i; 312 u32 control; 313 314 if (offset & 3) 315 /* address do not align */ 316 return false; 317 318 iowrite32(0, hw->hw_addr + REG_VPD_DATA); 319 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 320 iowrite32(control, hw->hw_addr + REG_VPD_CAP); 321 ioread32(hw->hw_addr + REG_VPD_CAP); 322 323 for (i = 0; i < 10; i++) { 324 msleep(2); 325 control = ioread32(hw->hw_addr + REG_VPD_CAP); 326 if (control & VPD_CAP_VPD_FLAG) 327 break; 328 } 329 if (control & VPD_CAP_VPD_FLAG) { 330 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA); 331 return true; 332 } 333 /* timeout */ 334 return false; 335 } 336 337 /* 338 * Reads the value from a PHY register 339 * hw - Struct containing variables accessed by shared code 340 * reg_addr - address of the PHY register to read 341 */ 342 static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data) 343 { 344 u32 val; 345 int i; 346 347 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 348 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 << 349 MDIO_CLK_SEL_SHIFT; 350 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); 351 ioread32(hw->hw_addr + REG_MDIO_CTRL); 352 353 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 354 udelay(2); 355 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); 356 if (!(val & (MDIO_START | MDIO_BUSY))) 357 break; 358 } 359 if (!(val & (MDIO_START | MDIO_BUSY))) { 360 *phy_data = (u16) val; 361 return 0; 362 } 363 return ATLX_ERR_PHY; 364 } 365 366 #define CUSTOM_SPI_CS_SETUP 2 367 #define CUSTOM_SPI_CLK_HI 2 368 #define CUSTOM_SPI_CLK_LO 2 369 #define CUSTOM_SPI_CS_HOLD 2 370 #define CUSTOM_SPI_CS_HI 3 371 372 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf) 373 { 374 int i; 375 u32 value; 376 377 iowrite32(0, hw->hw_addr + REG_SPI_DATA); 378 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR); 379 380 value = SPI_FLASH_CTRL_WAIT_READY | 381 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << 382 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI & 383 SPI_FLASH_CTRL_CLK_HI_MASK) << 384 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO & 385 SPI_FLASH_CTRL_CLK_LO_MASK) << 386 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD & 387 SPI_FLASH_CTRL_CS_HOLD_MASK) << 388 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI & 389 SPI_FLASH_CTRL_CS_HI_MASK) << 390 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) << 391 SPI_FLASH_CTRL_INS_SHIFT; 392 393 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); 394 395 value |= SPI_FLASH_CTRL_START; 396 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); 397 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); 398 399 for (i = 0; i < 10; i++) { 400 msleep(1); 401 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); 402 if (!(value & SPI_FLASH_CTRL_START)) 403 break; 404 } 405 406 if (value & SPI_FLASH_CTRL_START) 407 return false; 408 409 *buf = ioread32(hw->hw_addr + REG_SPI_DATA); 410 411 return true; 412 } 413 414 /* 415 * get_permanent_address 416 * return 0 if get valid mac address, 417 */ 418 static int atl1_get_permanent_address(struct atl1_hw *hw) 419 { 420 u32 addr[2]; 421 u32 i, control; 422 u16 reg; 423 u8 eth_addr[ETH_ALEN]; 424 bool key_valid; 425 426 if (is_valid_ether_addr(hw->perm_mac_addr)) 427 return 0; 428 429 /* init */ 430 addr[0] = addr[1] = 0; 431 432 if (!atl1_check_eeprom_exist(hw)) { 433 reg = 0; 434 key_valid = false; 435 /* Read out all EEPROM content */ 436 i = 0; 437 while (1) { 438 if (atl1_read_eeprom(hw, i + 0x100, &control)) { 439 if (key_valid) { 440 if (reg == REG_MAC_STA_ADDR) 441 addr[0] = control; 442 else if (reg == (REG_MAC_STA_ADDR + 4)) 443 addr[1] = control; 444 key_valid = false; 445 } else if ((control & 0xff) == 0x5A) { 446 key_valid = true; 447 reg = (u16) (control >> 16); 448 } else 449 break; 450 } else 451 /* read error */ 452 break; 453 i += 4; 454 } 455 456 *(u32 *) ð_addr[2] = swab32(addr[0]); 457 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); 458 if (is_valid_ether_addr(eth_addr)) { 459 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 460 return 0; 461 } 462 } 463 464 /* see if SPI FLAGS exist ? */ 465 addr[0] = addr[1] = 0; 466 reg = 0; 467 key_valid = false; 468 i = 0; 469 while (1) { 470 if (atl1_spi_read(hw, i + 0x1f000, &control)) { 471 if (key_valid) { 472 if (reg == REG_MAC_STA_ADDR) 473 addr[0] = control; 474 else if (reg == (REG_MAC_STA_ADDR + 4)) 475 addr[1] = control; 476 key_valid = false; 477 } else if ((control & 0xff) == 0x5A) { 478 key_valid = true; 479 reg = (u16) (control >> 16); 480 } else 481 /* data end */ 482 break; 483 } else 484 /* read error */ 485 break; 486 i += 4; 487 } 488 489 *(u32 *) ð_addr[2] = swab32(addr[0]); 490 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); 491 if (is_valid_ether_addr(eth_addr)) { 492 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 493 return 0; 494 } 495 496 /* 497 * On some motherboards, the MAC address is written by the 498 * BIOS directly to the MAC register during POST, and is 499 * not stored in eeprom. If all else thus far has failed 500 * to fetch the permanent MAC address, try reading it directly. 501 */ 502 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR); 503 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4)); 504 *(u32 *) ð_addr[2] = swab32(addr[0]); 505 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); 506 if (is_valid_ether_addr(eth_addr)) { 507 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 508 return 0; 509 } 510 511 return 1; 512 } 513 514 /* 515 * Reads the adapter's MAC address from the EEPROM 516 * hw - Struct containing variables accessed by shared code 517 */ 518 static s32 atl1_read_mac_addr(struct atl1_hw *hw) 519 { 520 s32 ret = 0; 521 u16 i; 522 523 if (atl1_get_permanent_address(hw)) { 524 eth_random_addr(hw->perm_mac_addr); 525 ret = 1; 526 } 527 528 for (i = 0; i < ETH_ALEN; i++) 529 hw->mac_addr[i] = hw->perm_mac_addr[i]; 530 return ret; 531 } 532 533 /* 534 * Hashes an address to determine its location in the multicast table 535 * hw - Struct containing variables accessed by shared code 536 * mc_addr - the multicast address to hash 537 * 538 * atl1_hash_mc_addr 539 * purpose 540 * set hash value for a multicast address 541 * hash calcu processing : 542 * 1. calcu 32bit CRC for multicast address 543 * 2. reverse crc with MSB to LSB 544 */ 545 static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr) 546 { 547 u32 crc32, value = 0; 548 int i; 549 550 crc32 = ether_crc_le(6, mc_addr); 551 for (i = 0; i < 32; i++) 552 value |= (((crc32 >> i) & 1) << (31 - i)); 553 554 return value; 555 } 556 557 /* 558 * Sets the bit in the multicast table corresponding to the hash value. 559 * hw - Struct containing variables accessed by shared code 560 * hash_value - Multicast address hash value 561 */ 562 static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value) 563 { 564 u32 hash_bit, hash_reg; 565 u32 mta; 566 567 /* 568 * The HASH Table is a register array of 2 32-bit registers. 569 * It is treated like an array of 64 bits. We want to set 570 * bit BitArray[hash_value]. So we figure out what register 571 * the bit is in, read it, OR in the new bit, then write 572 * back the new value. The register is determined by the 573 * upper 7 bits of the hash value and the bit within that 574 * register are determined by the lower 5 bits of the value. 575 */ 576 hash_reg = (hash_value >> 31) & 0x1; 577 hash_bit = (hash_value >> 26) & 0x1F; 578 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); 579 mta |= (1 << hash_bit); 580 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); 581 } 582 583 /* 584 * Writes a value to a PHY register 585 * hw - Struct containing variables accessed by shared code 586 * reg_addr - address of the PHY register to write 587 * data - data to write to the PHY 588 */ 589 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data) 590 { 591 int i; 592 u32 val; 593 594 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 595 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 596 MDIO_SUP_PREAMBLE | 597 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 598 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); 599 ioread32(hw->hw_addr + REG_MDIO_CTRL); 600 601 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 602 udelay(2); 603 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); 604 if (!(val & (MDIO_START | MDIO_BUSY))) 605 break; 606 } 607 608 if (!(val & (MDIO_START | MDIO_BUSY))) 609 return 0; 610 611 return ATLX_ERR_PHY; 612 } 613 614 /* 615 * Make L001's PHY out of Power Saving State (bug) 616 * hw - Struct containing variables accessed by shared code 617 * when power on, L001's PHY always on Power saving State 618 * (Gigabit Link forbidden) 619 */ 620 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw) 621 { 622 s32 ret; 623 ret = atl1_write_phy_reg(hw, 29, 0x0029); 624 if (ret) 625 return ret; 626 return atl1_write_phy_reg(hw, 30, 0); 627 } 628 629 /* 630 * Resets the PHY and make all config validate 631 * hw - Struct containing variables accessed by shared code 632 * 633 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) 634 */ 635 static s32 atl1_phy_reset(struct atl1_hw *hw) 636 { 637 struct pci_dev *pdev = hw->back->pdev; 638 struct atl1_adapter *adapter = hw->back; 639 s32 ret_val; 640 u16 phy_data; 641 642 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 643 hw->media_type == MEDIA_TYPE_1000M_FULL) 644 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 645 else { 646 switch (hw->media_type) { 647 case MEDIA_TYPE_100M_FULL: 648 phy_data = 649 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | 650 MII_CR_RESET; 651 break; 652 case MEDIA_TYPE_100M_HALF: 653 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 654 break; 655 case MEDIA_TYPE_10M_FULL: 656 phy_data = 657 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 658 break; 659 default: 660 /* MEDIA_TYPE_10M_HALF: */ 661 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 662 break; 663 } 664 } 665 666 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data); 667 if (ret_val) { 668 u32 val; 669 int i; 670 /* pcie serdes link may be down! */ 671 if (netif_msg_hw(adapter)) 672 dev_dbg(&pdev->dev, "pcie phy link down\n"); 673 674 for (i = 0; i < 25; i++) { 675 msleep(1); 676 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); 677 if (!(val & (MDIO_START | MDIO_BUSY))) 678 break; 679 } 680 681 if ((val & (MDIO_START | MDIO_BUSY)) != 0) { 682 if (netif_msg_hw(adapter)) 683 dev_warn(&pdev->dev, 684 "pcie link down at least 25ms\n"); 685 return ret_val; 686 } 687 } 688 return 0; 689 } 690 691 /* 692 * Configures PHY autoneg and flow control advertisement settings 693 * hw - Struct containing variables accessed by shared code 694 */ 695 static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw) 696 { 697 s32 ret_val; 698 s16 mii_autoneg_adv_reg; 699 s16 mii_1000t_ctrl_reg; 700 701 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 702 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 703 704 /* Read the MII 1000Base-T Control Register (Address 9). */ 705 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK; 706 707 /* 708 * First we clear all the 10/100 mb speed bits in the Auto-Neg 709 * Advertisement Register (Address 4) and the 1000 mb speed bits in 710 * the 1000Base-T Control Register (Address 9). 711 */ 712 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 713 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK; 714 715 /* 716 * Need to parse media_type and set up 717 * the appropriate PHY registers. 718 */ 719 switch (hw->media_type) { 720 case MEDIA_TYPE_AUTO_SENSOR: 721 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS | 722 MII_AR_10T_FD_CAPS | 723 MII_AR_100TX_HD_CAPS | 724 MII_AR_100TX_FD_CAPS); 725 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS; 726 break; 727 728 case MEDIA_TYPE_1000M_FULL: 729 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS; 730 break; 731 732 case MEDIA_TYPE_100M_FULL: 733 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 734 break; 735 736 case MEDIA_TYPE_100M_HALF: 737 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 738 break; 739 740 case MEDIA_TYPE_10M_FULL: 741 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 742 break; 743 744 default: 745 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 746 break; 747 } 748 749 /* flow control fixed to enable all */ 750 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 751 752 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 753 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; 754 755 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 756 if (ret_val) 757 return ret_val; 758 759 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg); 760 if (ret_val) 761 return ret_val; 762 763 return 0; 764 } 765 766 /* 767 * Configures link settings. 768 * hw - Struct containing variables accessed by shared code 769 * Assumes the hardware has previously been reset and the 770 * transmitter and receiver are not enabled. 771 */ 772 static s32 atl1_setup_link(struct atl1_hw *hw) 773 { 774 struct pci_dev *pdev = hw->back->pdev; 775 struct atl1_adapter *adapter = hw->back; 776 s32 ret_val; 777 778 /* 779 * Options: 780 * PHY will advertise value(s) parsed from 781 * autoneg_advertised and fc 782 * no matter what autoneg is , We will not wait link result. 783 */ 784 ret_val = atl1_phy_setup_autoneg_adv(hw); 785 if (ret_val) { 786 if (netif_msg_link(adapter)) 787 dev_dbg(&pdev->dev, 788 "error setting up autonegotiation\n"); 789 return ret_val; 790 } 791 /* SW.Reset , En-Auto-Neg if needed */ 792 ret_val = atl1_phy_reset(hw); 793 if (ret_val) { 794 if (netif_msg_link(adapter)) 795 dev_dbg(&pdev->dev, "error resetting phy\n"); 796 return ret_val; 797 } 798 hw->phy_configured = true; 799 return ret_val; 800 } 801 802 static void atl1_init_flash_opcode(struct atl1_hw *hw) 803 { 804 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) 805 /* Atmel */ 806 hw->flash_vendor = 0; 807 808 /* Init OP table */ 809 iowrite8(flash_table[hw->flash_vendor].cmd_program, 810 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM); 811 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase, 812 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE); 813 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase, 814 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE); 815 iowrite8(flash_table[hw->flash_vendor].cmd_rdid, 816 hw->hw_addr + REG_SPI_FLASH_OP_RDID); 817 iowrite8(flash_table[hw->flash_vendor].cmd_wren, 818 hw->hw_addr + REG_SPI_FLASH_OP_WREN); 819 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr, 820 hw->hw_addr + REG_SPI_FLASH_OP_RDSR); 821 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr, 822 hw->hw_addr + REG_SPI_FLASH_OP_WRSR); 823 iowrite8(flash_table[hw->flash_vendor].cmd_read, 824 hw->hw_addr + REG_SPI_FLASH_OP_READ); 825 } 826 827 /* 828 * Performs basic configuration of the adapter. 829 * hw - Struct containing variables accessed by shared code 830 * Assumes that the controller has previously been reset and is in a 831 * post-reset uninitialized state. Initializes multicast table, 832 * and Calls routines to setup link 833 * Leaves the transmit and receive units disabled and uninitialized. 834 */ 835 static s32 atl1_init_hw(struct atl1_hw *hw) 836 { 837 u32 ret_val = 0; 838 839 /* Zero out the Multicast HASH table */ 840 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE); 841 /* clear the old settings from the multicast hash table */ 842 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2)); 843 844 atl1_init_flash_opcode(hw); 845 846 if (!hw->phy_configured) { 847 /* enable GPHY LinkChange Interrupt */ 848 ret_val = atl1_write_phy_reg(hw, 18, 0xC00); 849 if (ret_val) 850 return ret_val; 851 /* make PHY out of power-saving state */ 852 ret_val = atl1_phy_leave_power_saving(hw); 853 if (ret_val) 854 return ret_val; 855 /* Call a subroutine to configure the link */ 856 ret_val = atl1_setup_link(hw); 857 } 858 return ret_val; 859 } 860 861 /* 862 * Detects the current speed and duplex settings of the hardware. 863 * hw - Struct containing variables accessed by shared code 864 * speed - Speed of the connection 865 * duplex - Duplex setting of the connection 866 */ 867 static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex) 868 { 869 struct pci_dev *pdev = hw->back->pdev; 870 struct atl1_adapter *adapter = hw->back; 871 s32 ret_val; 872 u16 phy_data; 873 874 /* ; --- Read PHY Specific Status Register (17) */ 875 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); 876 if (ret_val) 877 return ret_val; 878 879 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) 880 return ATLX_ERR_PHY_RES; 881 882 switch (phy_data & MII_ATLX_PSSR_SPEED) { 883 case MII_ATLX_PSSR_1000MBS: 884 *speed = SPEED_1000; 885 break; 886 case MII_ATLX_PSSR_100MBS: 887 *speed = SPEED_100; 888 break; 889 case MII_ATLX_PSSR_10MBS: 890 *speed = SPEED_10; 891 break; 892 default: 893 if (netif_msg_hw(adapter)) 894 dev_dbg(&pdev->dev, "error getting speed\n"); 895 return ATLX_ERR_PHY_SPEED; 896 } 897 if (phy_data & MII_ATLX_PSSR_DPLX) 898 *duplex = FULL_DUPLEX; 899 else 900 *duplex = HALF_DUPLEX; 901 902 return 0; 903 } 904 905 static void atl1_set_mac_addr(struct atl1_hw *hw) 906 { 907 u32 value; 908 /* 909 * 00-0B-6A-F6-00-DC 910 * 0: 6AF600DC 1: 000B 911 * low dword 912 */ 913 value = (((u32) hw->mac_addr[2]) << 24) | 914 (((u32) hw->mac_addr[3]) << 16) | 915 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5])); 916 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); 917 /* high dword */ 918 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); 919 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2)); 920 } 921 922 /** 923 * atl1_sw_init - Initialize general software structures (struct atl1_adapter) 924 * @adapter: board private structure to initialize 925 * 926 * atl1_sw_init initializes the Adapter private data structure. 927 * Fields are initialized based on PCI device information and 928 * OS network device settings (MTU size). 929 */ 930 static int atl1_sw_init(struct atl1_adapter *adapter) 931 { 932 struct atl1_hw *hw = &adapter->hw; 933 struct net_device *netdev = adapter->netdev; 934 935 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 936 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 937 938 adapter->wol = 0; 939 device_set_wakeup_enable(&adapter->pdev->dev, false); 940 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7; 941 adapter->ict = 50000; /* 100ms */ 942 adapter->link_speed = SPEED_0; /* hardware init */ 943 adapter->link_duplex = FULL_DUPLEX; 944 945 hw->phy_configured = false; 946 hw->preamble_len = 7; 947 hw->ipgt = 0x60; 948 hw->min_ifg = 0x50; 949 hw->ipgr1 = 0x40; 950 hw->ipgr2 = 0x60; 951 hw->max_retry = 0xf; 952 hw->lcol = 0x37; 953 hw->jam_ipg = 7; 954 hw->rfd_burst = 8; 955 hw->rrd_burst = 8; 956 hw->rfd_fetch_gap = 1; 957 hw->rx_jumbo_th = adapter->rx_buffer_len / 8; 958 hw->rx_jumbo_lkah = 1; 959 hw->rrd_ret_timer = 16; 960 hw->tpd_burst = 4; 961 hw->tpd_fetch_th = 16; 962 hw->txf_burst = 0x100; 963 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3; 964 hw->tpd_fetch_gap = 1; 965 hw->rcb_value = atl1_rcb_64; 966 hw->dma_ord = atl1_dma_ord_enh; 967 hw->dmar_block = atl1_dma_req_256; 968 hw->dmaw_block = atl1_dma_req_256; 969 hw->cmb_rrd = 4; 970 hw->cmb_tpd = 4; 971 hw->cmb_rx_timer = 1; /* about 2us */ 972 hw->cmb_tx_timer = 1; /* about 2us */ 973 hw->smb_timer = 100000; /* about 200ms */ 974 975 spin_lock_init(&adapter->lock); 976 spin_lock_init(&adapter->mb_lock); 977 978 return 0; 979 } 980 981 static int mdio_read(struct net_device *netdev, int phy_id, int reg_num) 982 { 983 struct atl1_adapter *adapter = netdev_priv(netdev); 984 u16 result; 985 986 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result); 987 988 return result; 989 } 990 991 static void mdio_write(struct net_device *netdev, int phy_id, int reg_num, 992 int val) 993 { 994 struct atl1_adapter *adapter = netdev_priv(netdev); 995 996 atl1_write_phy_reg(&adapter->hw, reg_num, val); 997 } 998 999 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1000 { 1001 struct atl1_adapter *adapter = netdev_priv(netdev); 1002 unsigned long flags; 1003 int retval; 1004 1005 if (!netif_running(netdev)) 1006 return -EINVAL; 1007 1008 spin_lock_irqsave(&adapter->lock, flags); 1009 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL); 1010 spin_unlock_irqrestore(&adapter->lock, flags); 1011 1012 return retval; 1013 } 1014 1015 /** 1016 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources 1017 * @adapter: board private structure 1018 * 1019 * Return 0 on success, negative on failure 1020 */ 1021 static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter) 1022 { 1023 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1024 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1025 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1026 struct atl1_ring_header *ring_header = &adapter->ring_header; 1027 struct pci_dev *pdev = adapter->pdev; 1028 int size; 1029 u8 offset = 0; 1030 1031 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count); 1032 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL); 1033 if (unlikely(!tpd_ring->buffer_info)) { 1034 if (netif_msg_drv(adapter)) 1035 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n", 1036 size); 1037 goto err_nomem; 1038 } 1039 rfd_ring->buffer_info = 1040 (tpd_ring->buffer_info + tpd_ring->count); 1041 1042 /* 1043 * real ring DMA buffer 1044 * each ring/block may need up to 8 bytes for alignment, hence the 1045 * additional 40 bytes tacked onto the end. 1046 */ 1047 ring_header->size = size = 1048 sizeof(struct tx_packet_desc) * tpd_ring->count 1049 + sizeof(struct rx_free_desc) * rfd_ring->count 1050 + sizeof(struct rx_return_desc) * rrd_ring->count 1051 + sizeof(struct coals_msg_block) 1052 + sizeof(struct stats_msg_block) 1053 + 40; 1054 1055 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size, 1056 &ring_header->dma); 1057 if (unlikely(!ring_header->desc)) { 1058 if (netif_msg_drv(adapter)) 1059 dev_err(&pdev->dev, "pci_alloc_consistent failed\n"); 1060 goto err_nomem; 1061 } 1062 1063 /* init TPD ring */ 1064 tpd_ring->dma = ring_header->dma; 1065 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0; 1066 tpd_ring->dma += offset; 1067 tpd_ring->desc = (u8 *) ring_header->desc + offset; 1068 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count; 1069 1070 /* init RFD ring */ 1071 rfd_ring->dma = tpd_ring->dma + tpd_ring->size; 1072 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0; 1073 rfd_ring->dma += offset; 1074 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset); 1075 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count; 1076 1077 1078 /* init RRD ring */ 1079 rrd_ring->dma = rfd_ring->dma + rfd_ring->size; 1080 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0; 1081 rrd_ring->dma += offset; 1082 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset); 1083 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count; 1084 1085 1086 /* init CMB */ 1087 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size; 1088 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0; 1089 adapter->cmb.dma += offset; 1090 adapter->cmb.cmb = (struct coals_msg_block *) 1091 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset)); 1092 1093 /* init SMB */ 1094 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block); 1095 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0; 1096 adapter->smb.dma += offset; 1097 adapter->smb.smb = (struct stats_msg_block *) 1098 ((u8 *) adapter->cmb.cmb + 1099 (sizeof(struct coals_msg_block) + offset)); 1100 1101 return 0; 1102 1103 err_nomem: 1104 kfree(tpd_ring->buffer_info); 1105 return -ENOMEM; 1106 } 1107 1108 static void atl1_init_ring_ptrs(struct atl1_adapter *adapter) 1109 { 1110 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1111 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1112 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1113 1114 atomic_set(&tpd_ring->next_to_use, 0); 1115 atomic_set(&tpd_ring->next_to_clean, 0); 1116 1117 rfd_ring->next_to_clean = 0; 1118 atomic_set(&rfd_ring->next_to_use, 0); 1119 1120 rrd_ring->next_to_use = 0; 1121 atomic_set(&rrd_ring->next_to_clean, 0); 1122 } 1123 1124 /** 1125 * atl1_clean_rx_ring - Free RFD Buffers 1126 * @adapter: board private structure 1127 */ 1128 static void atl1_clean_rx_ring(struct atl1_adapter *adapter) 1129 { 1130 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1131 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1132 struct atl1_buffer *buffer_info; 1133 struct pci_dev *pdev = adapter->pdev; 1134 unsigned long size; 1135 unsigned int i; 1136 1137 /* Free all the Rx ring sk_buffs */ 1138 for (i = 0; i < rfd_ring->count; i++) { 1139 buffer_info = &rfd_ring->buffer_info[i]; 1140 if (buffer_info->dma) { 1141 pci_unmap_page(pdev, buffer_info->dma, 1142 buffer_info->length, PCI_DMA_FROMDEVICE); 1143 buffer_info->dma = 0; 1144 } 1145 if (buffer_info->skb) { 1146 dev_kfree_skb(buffer_info->skb); 1147 buffer_info->skb = NULL; 1148 } 1149 } 1150 1151 size = sizeof(struct atl1_buffer) * rfd_ring->count; 1152 memset(rfd_ring->buffer_info, 0, size); 1153 1154 /* Zero out the descriptor ring */ 1155 memset(rfd_ring->desc, 0, rfd_ring->size); 1156 1157 rfd_ring->next_to_clean = 0; 1158 atomic_set(&rfd_ring->next_to_use, 0); 1159 1160 rrd_ring->next_to_use = 0; 1161 atomic_set(&rrd_ring->next_to_clean, 0); 1162 } 1163 1164 /** 1165 * atl1_clean_tx_ring - Free Tx Buffers 1166 * @adapter: board private structure 1167 */ 1168 static void atl1_clean_tx_ring(struct atl1_adapter *adapter) 1169 { 1170 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1171 struct atl1_buffer *buffer_info; 1172 struct pci_dev *pdev = adapter->pdev; 1173 unsigned long size; 1174 unsigned int i; 1175 1176 /* Free all the Tx ring sk_buffs */ 1177 for (i = 0; i < tpd_ring->count; i++) { 1178 buffer_info = &tpd_ring->buffer_info[i]; 1179 if (buffer_info->dma) { 1180 pci_unmap_page(pdev, buffer_info->dma, 1181 buffer_info->length, PCI_DMA_TODEVICE); 1182 buffer_info->dma = 0; 1183 } 1184 } 1185 1186 for (i = 0; i < tpd_ring->count; i++) { 1187 buffer_info = &tpd_ring->buffer_info[i]; 1188 if (buffer_info->skb) { 1189 dev_kfree_skb_any(buffer_info->skb); 1190 buffer_info->skb = NULL; 1191 } 1192 } 1193 1194 size = sizeof(struct atl1_buffer) * tpd_ring->count; 1195 memset(tpd_ring->buffer_info, 0, size); 1196 1197 /* Zero out the descriptor ring */ 1198 memset(tpd_ring->desc, 0, tpd_ring->size); 1199 1200 atomic_set(&tpd_ring->next_to_use, 0); 1201 atomic_set(&tpd_ring->next_to_clean, 0); 1202 } 1203 1204 /** 1205 * atl1_free_ring_resources - Free Tx / RX descriptor Resources 1206 * @adapter: board private structure 1207 * 1208 * Free all transmit software resources 1209 */ 1210 static void atl1_free_ring_resources(struct atl1_adapter *adapter) 1211 { 1212 struct pci_dev *pdev = adapter->pdev; 1213 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 1214 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1215 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1216 struct atl1_ring_header *ring_header = &adapter->ring_header; 1217 1218 atl1_clean_tx_ring(adapter); 1219 atl1_clean_rx_ring(adapter); 1220 1221 kfree(tpd_ring->buffer_info); 1222 pci_free_consistent(pdev, ring_header->size, ring_header->desc, 1223 ring_header->dma); 1224 1225 tpd_ring->buffer_info = NULL; 1226 tpd_ring->desc = NULL; 1227 tpd_ring->dma = 0; 1228 1229 rfd_ring->buffer_info = NULL; 1230 rfd_ring->desc = NULL; 1231 rfd_ring->dma = 0; 1232 1233 rrd_ring->desc = NULL; 1234 rrd_ring->dma = 0; 1235 1236 adapter->cmb.dma = 0; 1237 adapter->cmb.cmb = NULL; 1238 1239 adapter->smb.dma = 0; 1240 adapter->smb.smb = NULL; 1241 } 1242 1243 static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter) 1244 { 1245 u32 value; 1246 struct atl1_hw *hw = &adapter->hw; 1247 struct net_device *netdev = adapter->netdev; 1248 /* Config MAC CTRL Register */ 1249 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN; 1250 /* duplex */ 1251 if (FULL_DUPLEX == adapter->link_duplex) 1252 value |= MAC_CTRL_DUPLX; 1253 /* speed */ 1254 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ? 1255 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) << 1256 MAC_CTRL_SPEED_SHIFT); 1257 /* flow control */ 1258 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 1259 /* PAD & CRC */ 1260 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1261 /* preamble length */ 1262 value |= (((u32) adapter->hw.preamble_len 1263 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 1264 /* vlan */ 1265 __atlx_vlan_mode(netdev->features, &value); 1266 /* rx checksum 1267 if (adapter->rx_csum) 1268 value |= MAC_CTRL_RX_CHKSUM_EN; 1269 */ 1270 /* filter mode */ 1271 value |= MAC_CTRL_BC_EN; 1272 if (netdev->flags & IFF_PROMISC) 1273 value |= MAC_CTRL_PROMIS_EN; 1274 else if (netdev->flags & IFF_ALLMULTI) 1275 value |= MAC_CTRL_MC_ALL_EN; 1276 /* value |= MAC_CTRL_LOOPBACK; */ 1277 iowrite32(value, hw->hw_addr + REG_MAC_CTRL); 1278 } 1279 1280 static u32 atl1_check_link(struct atl1_adapter *adapter) 1281 { 1282 struct atl1_hw *hw = &adapter->hw; 1283 struct net_device *netdev = adapter->netdev; 1284 u32 ret_val; 1285 u16 speed, duplex, phy_data; 1286 int reconfig = 0; 1287 1288 /* MII_BMSR must read twice */ 1289 atl1_read_phy_reg(hw, MII_BMSR, &phy_data); 1290 atl1_read_phy_reg(hw, MII_BMSR, &phy_data); 1291 if (!(phy_data & BMSR_LSTATUS)) { 1292 /* link down */ 1293 if (netif_carrier_ok(netdev)) { 1294 /* old link state: Up */ 1295 if (netif_msg_link(adapter)) 1296 dev_info(&adapter->pdev->dev, "link is down\n"); 1297 adapter->link_speed = SPEED_0; 1298 netif_carrier_off(netdev); 1299 } 1300 return 0; 1301 } 1302 1303 /* Link Up */ 1304 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex); 1305 if (ret_val) 1306 return ret_val; 1307 1308 switch (hw->media_type) { 1309 case MEDIA_TYPE_1000M_FULL: 1310 if (speed != SPEED_1000 || duplex != FULL_DUPLEX) 1311 reconfig = 1; 1312 break; 1313 case MEDIA_TYPE_100M_FULL: 1314 if (speed != SPEED_100 || duplex != FULL_DUPLEX) 1315 reconfig = 1; 1316 break; 1317 case MEDIA_TYPE_100M_HALF: 1318 if (speed != SPEED_100 || duplex != HALF_DUPLEX) 1319 reconfig = 1; 1320 break; 1321 case MEDIA_TYPE_10M_FULL: 1322 if (speed != SPEED_10 || duplex != FULL_DUPLEX) 1323 reconfig = 1; 1324 break; 1325 case MEDIA_TYPE_10M_HALF: 1326 if (speed != SPEED_10 || duplex != HALF_DUPLEX) 1327 reconfig = 1; 1328 break; 1329 } 1330 1331 /* link result is our setting */ 1332 if (!reconfig) { 1333 if (adapter->link_speed != speed || 1334 adapter->link_duplex != duplex) { 1335 adapter->link_speed = speed; 1336 adapter->link_duplex = duplex; 1337 atl1_setup_mac_ctrl(adapter); 1338 if (netif_msg_link(adapter)) 1339 dev_info(&adapter->pdev->dev, 1340 "%s link is up %d Mbps %s\n", 1341 netdev->name, adapter->link_speed, 1342 adapter->link_duplex == FULL_DUPLEX ? 1343 "full duplex" : "half duplex"); 1344 } 1345 if (!netif_carrier_ok(netdev)) { 1346 /* Link down -> Up */ 1347 netif_carrier_on(netdev); 1348 } 1349 return 0; 1350 } 1351 1352 /* change original link status */ 1353 if (netif_carrier_ok(netdev)) { 1354 adapter->link_speed = SPEED_0; 1355 netif_carrier_off(netdev); 1356 netif_stop_queue(netdev); 1357 } 1358 1359 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR && 1360 hw->media_type != MEDIA_TYPE_1000M_FULL) { 1361 switch (hw->media_type) { 1362 case MEDIA_TYPE_100M_FULL: 1363 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | 1364 MII_CR_RESET; 1365 break; 1366 case MEDIA_TYPE_100M_HALF: 1367 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 1368 break; 1369 case MEDIA_TYPE_10M_FULL: 1370 phy_data = 1371 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 1372 break; 1373 default: 1374 /* MEDIA_TYPE_10M_HALF: */ 1375 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 1376 break; 1377 } 1378 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 1379 return 0; 1380 } 1381 1382 /* auto-neg, insert timer to re-config phy */ 1383 if (!adapter->phy_timer_pending) { 1384 adapter->phy_timer_pending = true; 1385 mod_timer(&adapter->phy_config_timer, 1386 round_jiffies(jiffies + 3 * HZ)); 1387 } 1388 1389 return 0; 1390 } 1391 1392 static void set_flow_ctrl_old(struct atl1_adapter *adapter) 1393 { 1394 u32 hi, lo, value; 1395 1396 /* RFD Flow Control */ 1397 value = adapter->rfd_ring.count; 1398 hi = value / 16; 1399 if (hi < 2) 1400 hi = 2; 1401 lo = value * 7 / 8; 1402 1403 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | 1404 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); 1405 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH); 1406 1407 /* RRD Flow Control */ 1408 value = adapter->rrd_ring.count; 1409 lo = value / 16; 1410 hi = value * 7 / 8; 1411 if (lo < 2) 1412 lo = 2; 1413 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | 1414 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); 1415 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH); 1416 } 1417 1418 static void set_flow_ctrl_new(struct atl1_hw *hw) 1419 { 1420 u32 hi, lo, value; 1421 1422 /* RXF Flow Control */ 1423 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN); 1424 lo = value / 16; 1425 if (lo < 192) 1426 lo = 192; 1427 hi = value * 7 / 8; 1428 if (hi < lo) 1429 hi = lo + 16; 1430 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | 1431 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); 1432 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH); 1433 1434 /* RRD Flow Control */ 1435 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN); 1436 lo = value / 8; 1437 hi = value * 7 / 8; 1438 if (lo < 2) 1439 lo = 2; 1440 if (hi < lo) 1441 hi = lo + 3; 1442 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | 1443 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); 1444 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH); 1445 } 1446 1447 /** 1448 * atl1_configure - Configure Transmit&Receive Unit after Reset 1449 * @adapter: board private structure 1450 * 1451 * Configure the Tx /Rx unit of the MAC after a reset. 1452 */ 1453 static u32 atl1_configure(struct atl1_adapter *adapter) 1454 { 1455 struct atl1_hw *hw = &adapter->hw; 1456 u32 value; 1457 1458 /* clear interrupt status */ 1459 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR); 1460 1461 /* set MAC Address */ 1462 value = (((u32) hw->mac_addr[2]) << 24) | 1463 (((u32) hw->mac_addr[3]) << 16) | 1464 (((u32) hw->mac_addr[4]) << 8) | 1465 (((u32) hw->mac_addr[5])); 1466 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); 1467 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); 1468 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4)); 1469 1470 /* tx / rx ring */ 1471 1472 /* HI base address */ 1473 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32), 1474 hw->hw_addr + REG_DESC_BASE_ADDR_HI); 1475 /* LO base address */ 1476 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL), 1477 hw->hw_addr + REG_DESC_RFD_ADDR_LO); 1478 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL), 1479 hw->hw_addr + REG_DESC_RRD_ADDR_LO); 1480 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL), 1481 hw->hw_addr + REG_DESC_TPD_ADDR_LO); 1482 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL), 1483 hw->hw_addr + REG_DESC_CMB_ADDR_LO); 1484 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL), 1485 hw->hw_addr + REG_DESC_SMB_ADDR_LO); 1486 1487 /* element count */ 1488 value = adapter->rrd_ring.count; 1489 value <<= 16; 1490 value += adapter->rfd_ring.count; 1491 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE); 1492 iowrite32(adapter->tpd_ring.count, hw->hw_addr + 1493 REG_DESC_TPD_RING_SIZE); 1494 1495 /* Load Ptr */ 1496 iowrite32(1, hw->hw_addr + REG_LOAD_PTR); 1497 1498 /* config Mailbox */ 1499 value = ((atomic_read(&adapter->tpd_ring.next_to_use) 1500 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) | 1501 ((atomic_read(&adapter->rrd_ring.next_to_clean) 1502 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) | 1503 ((atomic_read(&adapter->rfd_ring.next_to_use) 1504 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT); 1505 iowrite32(value, hw->hw_addr + REG_MAILBOX); 1506 1507 /* config IPG/IFG */ 1508 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK) 1509 << MAC_IPG_IFG_IPGT_SHIFT) | 1510 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) 1511 << MAC_IPG_IFG_MIFG_SHIFT) | 1512 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) 1513 << MAC_IPG_IFG_IPGR1_SHIFT) | 1514 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) 1515 << MAC_IPG_IFG_IPGR2_SHIFT); 1516 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG); 1517 1518 /* config Half-Duplex Control */ 1519 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | 1520 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) 1521 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | 1522 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | 1523 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | 1524 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) 1525 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); 1526 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL); 1527 1528 /* set Interrupt Moderator Timer */ 1529 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT); 1530 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL); 1531 1532 /* set Interrupt Clear Timer */ 1533 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER); 1534 1535 /* set max frame size hw will accept */ 1536 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU); 1537 1538 /* jumbo size & rrd retirement timer */ 1539 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) 1540 << RXQ_JMBOSZ_TH_SHIFT) | 1541 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK) 1542 << RXQ_JMBO_LKAH_SHIFT) | 1543 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK) 1544 << RXQ_RRD_TIMER_SHIFT); 1545 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM); 1546 1547 /* Flow Control */ 1548 switch (hw->dev_rev) { 1549 case 0x8001: 1550 case 0x9001: 1551 case 0x9002: 1552 case 0x9003: 1553 set_flow_ctrl_old(adapter); 1554 break; 1555 default: 1556 set_flow_ctrl_new(hw); 1557 break; 1558 } 1559 1560 /* config TXQ */ 1561 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK) 1562 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) | 1563 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK) 1564 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) | 1565 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK) 1566 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE | 1567 TXQ_CTRL_EN; 1568 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL); 1569 1570 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */ 1571 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK) 1572 << TX_JUMBO_TASK_TH_SHIFT) | 1573 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK) 1574 << TX_TPD_MIN_IPG_SHIFT); 1575 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG); 1576 1577 /* config RXQ */ 1578 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK) 1579 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) | 1580 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK) 1581 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) | 1582 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK) 1583 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN | 1584 RXQ_CTRL_EN; 1585 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL); 1586 1587 /* config DMA Engine */ 1588 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK) 1589 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) | 1590 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK) 1591 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN | 1592 DMA_CTRL_DMAW_EN; 1593 value |= (u32) hw->dma_ord; 1594 if (atl1_rcb_128 == hw->rcb_value) 1595 value |= DMA_CTRL_RCB_VALUE; 1596 iowrite32(value, hw->hw_addr + REG_DMA_CTRL); 1597 1598 /* config CMB / SMB */ 1599 value = (hw->cmb_tpd > adapter->tpd_ring.count) ? 1600 hw->cmb_tpd : adapter->tpd_ring.count; 1601 value <<= 16; 1602 value |= hw->cmb_rrd; 1603 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH); 1604 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16); 1605 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER); 1606 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER); 1607 1608 /* --- enable CMB / SMB */ 1609 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN; 1610 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL); 1611 1612 value = ioread32(adapter->hw.hw_addr + REG_ISR); 1613 if (unlikely((value & ISR_PHY_LINKDOWN) != 0)) 1614 value = 1; /* config failed */ 1615 else 1616 value = 0; 1617 1618 /* clear all interrupt status */ 1619 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR); 1620 iowrite32(0, adapter->hw.hw_addr + REG_ISR); 1621 return value; 1622 } 1623 1624 /* 1625 * atl1_pcie_patch - Patch for PCIE module 1626 */ 1627 static void atl1_pcie_patch(struct atl1_adapter *adapter) 1628 { 1629 u32 value; 1630 1631 /* much vendor magic here */ 1632 value = 0x6500; 1633 iowrite32(value, adapter->hw.hw_addr + 0x12FC); 1634 /* pcie flow control mode change */ 1635 value = ioread32(adapter->hw.hw_addr + 0x1008); 1636 value |= 0x8000; 1637 iowrite32(value, adapter->hw.hw_addr + 0x1008); 1638 } 1639 1640 /* 1641 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400 1642 * on PCI Command register is disable. 1643 * The function enable this bit. 1644 * Brackett, 2006/03/15 1645 */ 1646 static void atl1_via_workaround(struct atl1_adapter *adapter) 1647 { 1648 unsigned long value; 1649 1650 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND); 1651 if (value & PCI_COMMAND_INTX_DISABLE) 1652 value &= ~PCI_COMMAND_INTX_DISABLE; 1653 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND); 1654 } 1655 1656 static void atl1_inc_smb(struct atl1_adapter *adapter) 1657 { 1658 struct net_device *netdev = adapter->netdev; 1659 struct stats_msg_block *smb = adapter->smb.smb; 1660 1661 u64 new_rx_errors = smb->rx_frag + 1662 smb->rx_fcs_err + 1663 smb->rx_len_err + 1664 smb->rx_sz_ov + 1665 smb->rx_rxf_ov + 1666 smb->rx_rrd_ov + 1667 smb->rx_align_err; 1668 u64 new_tx_errors = smb->tx_late_col + 1669 smb->tx_abort_col + 1670 smb->tx_underrun + 1671 smb->tx_trunc; 1672 1673 /* Fill out the OS statistics structure */ 1674 adapter->soft_stats.rx_packets += smb->rx_ok + new_rx_errors; 1675 adapter->soft_stats.tx_packets += smb->tx_ok + new_tx_errors; 1676 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt; 1677 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt; 1678 adapter->soft_stats.multicast += smb->rx_mcast; 1679 adapter->soft_stats.collisions += smb->tx_1_col + 1680 smb->tx_2_col + 1681 smb->tx_late_col + 1682 smb->tx_abort_col; 1683 1684 /* Rx Errors */ 1685 adapter->soft_stats.rx_errors += new_rx_errors; 1686 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov; 1687 adapter->soft_stats.rx_length_errors += smb->rx_len_err; 1688 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err; 1689 adapter->soft_stats.rx_frame_errors += smb->rx_align_err; 1690 1691 adapter->soft_stats.rx_pause += smb->rx_pause; 1692 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov; 1693 adapter->soft_stats.rx_trunc += smb->rx_sz_ov; 1694 1695 /* Tx Errors */ 1696 adapter->soft_stats.tx_errors += new_tx_errors; 1697 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun; 1698 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col; 1699 adapter->soft_stats.tx_window_errors += smb->tx_late_col; 1700 1701 adapter->soft_stats.excecol += smb->tx_abort_col; 1702 adapter->soft_stats.deffer += smb->tx_defer; 1703 adapter->soft_stats.scc += smb->tx_1_col; 1704 adapter->soft_stats.mcc += smb->tx_2_col; 1705 adapter->soft_stats.latecol += smb->tx_late_col; 1706 adapter->soft_stats.tx_underrun += smb->tx_underrun; 1707 adapter->soft_stats.tx_trunc += smb->tx_trunc; 1708 adapter->soft_stats.tx_pause += smb->tx_pause; 1709 1710 netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes; 1711 netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes; 1712 netdev->stats.multicast = adapter->soft_stats.multicast; 1713 netdev->stats.collisions = adapter->soft_stats.collisions; 1714 netdev->stats.rx_errors = adapter->soft_stats.rx_errors; 1715 netdev->stats.rx_length_errors = 1716 adapter->soft_stats.rx_length_errors; 1717 netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors; 1718 netdev->stats.rx_frame_errors = 1719 adapter->soft_stats.rx_frame_errors; 1720 netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors; 1721 netdev->stats.rx_dropped = adapter->soft_stats.rx_rrd_ov; 1722 netdev->stats.tx_errors = adapter->soft_stats.tx_errors; 1723 netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors; 1724 netdev->stats.tx_aborted_errors = 1725 adapter->soft_stats.tx_aborted_errors; 1726 netdev->stats.tx_window_errors = 1727 adapter->soft_stats.tx_window_errors; 1728 netdev->stats.tx_carrier_errors = 1729 adapter->soft_stats.tx_carrier_errors; 1730 1731 netdev->stats.rx_packets = adapter->soft_stats.rx_packets; 1732 netdev->stats.tx_packets = adapter->soft_stats.tx_packets; 1733 } 1734 1735 static void atl1_update_mailbox(struct atl1_adapter *adapter) 1736 { 1737 unsigned long flags; 1738 u32 tpd_next_to_use; 1739 u32 rfd_next_to_use; 1740 u32 rrd_next_to_clean; 1741 u32 value; 1742 1743 spin_lock_irqsave(&adapter->mb_lock, flags); 1744 1745 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); 1746 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use); 1747 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean); 1748 1749 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << 1750 MB_RFD_PROD_INDX_SHIFT) | 1751 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << 1752 MB_RRD_CONS_INDX_SHIFT) | 1753 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << 1754 MB_TPD_PROD_INDX_SHIFT); 1755 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); 1756 1757 spin_unlock_irqrestore(&adapter->mb_lock, flags); 1758 } 1759 1760 static void atl1_clean_alloc_flag(struct atl1_adapter *adapter, 1761 struct rx_return_desc *rrd, u16 offset) 1762 { 1763 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1764 1765 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) { 1766 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0; 1767 if (++rfd_ring->next_to_clean == rfd_ring->count) { 1768 rfd_ring->next_to_clean = 0; 1769 } 1770 } 1771 } 1772 1773 static void atl1_update_rfd_index(struct atl1_adapter *adapter, 1774 struct rx_return_desc *rrd) 1775 { 1776 u16 num_buf; 1777 1778 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) / 1779 adapter->rx_buffer_len; 1780 if (rrd->num_buf == num_buf) 1781 /* clean alloc flag for bad rrd */ 1782 atl1_clean_alloc_flag(adapter, rrd, num_buf); 1783 } 1784 1785 static void atl1_rx_checksum(struct atl1_adapter *adapter, 1786 struct rx_return_desc *rrd, struct sk_buff *skb) 1787 { 1788 struct pci_dev *pdev = adapter->pdev; 1789 1790 /* 1791 * The L1 hardware contains a bug that erroneously sets the 1792 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a 1793 * fragmented IP packet is received, even though the packet 1794 * is perfectly valid and its checksum is correct. There's 1795 * no way to distinguish between one of these good packets 1796 * and a packet that actually contains a TCP/UDP checksum 1797 * error, so all we can do is allow it to be handed up to 1798 * the higher layers and let it be sorted out there. 1799 */ 1800 1801 skb_checksum_none_assert(skb); 1802 1803 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { 1804 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC | 1805 ERR_FLAG_CODE | ERR_FLAG_OV)) { 1806 adapter->hw_csum_err++; 1807 if (netif_msg_rx_err(adapter)) 1808 dev_printk(KERN_DEBUG, &pdev->dev, 1809 "rx checksum error\n"); 1810 return; 1811 } 1812 } 1813 1814 /* not IPv4 */ 1815 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4)) 1816 /* checksum is invalid, but it's not an IPv4 pkt, so ok */ 1817 return; 1818 1819 /* IPv4 packet */ 1820 if (likely(!(rrd->err_flg & 1821 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) { 1822 skb->ip_summed = CHECKSUM_UNNECESSARY; 1823 adapter->hw_csum_good++; 1824 return; 1825 } 1826 } 1827 1828 /** 1829 * atl1_alloc_rx_buffers - Replace used receive buffers 1830 * @adapter: address of board private structure 1831 */ 1832 static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter) 1833 { 1834 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1835 struct pci_dev *pdev = adapter->pdev; 1836 struct page *page; 1837 unsigned long offset; 1838 struct atl1_buffer *buffer_info, *next_info; 1839 struct sk_buff *skb; 1840 u16 num_alloc = 0; 1841 u16 rfd_next_to_use, next_next; 1842 struct rx_free_desc *rfd_desc; 1843 1844 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use); 1845 if (++next_next == rfd_ring->count) 1846 next_next = 0; 1847 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; 1848 next_info = &rfd_ring->buffer_info[next_next]; 1849 1850 while (!buffer_info->alloced && !next_info->alloced) { 1851 if (buffer_info->skb) { 1852 buffer_info->alloced = 1; 1853 goto next; 1854 } 1855 1856 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use); 1857 1858 skb = netdev_alloc_skb_ip_align(adapter->netdev, 1859 adapter->rx_buffer_len); 1860 if (unlikely(!skb)) { 1861 /* Better luck next round */ 1862 adapter->soft_stats.rx_dropped++; 1863 break; 1864 } 1865 1866 buffer_info->alloced = 1; 1867 buffer_info->skb = skb; 1868 buffer_info->length = (u16) adapter->rx_buffer_len; 1869 page = virt_to_page(skb->data); 1870 offset = offset_in_page(skb->data); 1871 buffer_info->dma = pci_map_page(pdev, page, offset, 1872 adapter->rx_buffer_len, 1873 PCI_DMA_FROMDEVICE); 1874 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 1875 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len); 1876 rfd_desc->coalese = 0; 1877 1878 next: 1879 rfd_next_to_use = next_next; 1880 if (unlikely(++next_next == rfd_ring->count)) 1881 next_next = 0; 1882 1883 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; 1884 next_info = &rfd_ring->buffer_info[next_next]; 1885 num_alloc++; 1886 } 1887 1888 if (num_alloc) { 1889 /* 1890 * Force memory writes to complete before letting h/w 1891 * know there are new descriptors to fetch. (Only 1892 * applicable for weak-ordered memory model archs, 1893 * such as IA-64). 1894 */ 1895 wmb(); 1896 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use); 1897 } 1898 return num_alloc; 1899 } 1900 1901 static int atl1_intr_rx(struct atl1_adapter *adapter, int budget) 1902 { 1903 int i, count; 1904 u16 length; 1905 u16 rrd_next_to_clean; 1906 u32 value; 1907 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; 1908 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; 1909 struct atl1_buffer *buffer_info; 1910 struct rx_return_desc *rrd; 1911 struct sk_buff *skb; 1912 1913 count = 0; 1914 1915 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean); 1916 1917 while (count < budget) { 1918 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean); 1919 i = 1; 1920 if (likely(rrd->xsz.valid)) { /* packet valid */ 1921 chk_rrd: 1922 /* check rrd status */ 1923 if (likely(rrd->num_buf == 1)) 1924 goto rrd_ok; 1925 else if (netif_msg_rx_err(adapter)) { 1926 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1927 "unexpected RRD buffer count\n"); 1928 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1929 "rx_buf_len = %d\n", 1930 adapter->rx_buffer_len); 1931 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1932 "RRD num_buf = %d\n", 1933 rrd->num_buf); 1934 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1935 "RRD pkt_len = %d\n", 1936 rrd->xsz.xsum_sz.pkt_size); 1937 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1938 "RRD pkt_flg = 0x%08X\n", 1939 rrd->pkt_flg); 1940 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1941 "RRD err_flg = 0x%08X\n", 1942 rrd->err_flg); 1943 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1944 "RRD vlan_tag = 0x%08X\n", 1945 rrd->vlan_tag); 1946 } 1947 1948 /* rrd seems to be bad */ 1949 if (unlikely(i-- > 0)) { 1950 /* rrd may not be DMAed completely */ 1951 udelay(1); 1952 goto chk_rrd; 1953 } 1954 /* bad rrd */ 1955 if (netif_msg_rx_err(adapter)) 1956 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 1957 "bad RRD\n"); 1958 /* see if update RFD index */ 1959 if (rrd->num_buf > 1) 1960 atl1_update_rfd_index(adapter, rrd); 1961 1962 /* update rrd */ 1963 rrd->xsz.valid = 0; 1964 if (++rrd_next_to_clean == rrd_ring->count) 1965 rrd_next_to_clean = 0; 1966 count++; 1967 continue; 1968 } else { /* current rrd still not be updated */ 1969 1970 break; 1971 } 1972 rrd_ok: 1973 /* clean alloc flag for bad rrd */ 1974 atl1_clean_alloc_flag(adapter, rrd, 0); 1975 1976 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx]; 1977 if (++rfd_ring->next_to_clean == rfd_ring->count) 1978 rfd_ring->next_to_clean = 0; 1979 1980 /* update rrd next to clean */ 1981 if (++rrd_next_to_clean == rrd_ring->count) 1982 rrd_next_to_clean = 0; 1983 count++; 1984 1985 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { 1986 if (!(rrd->err_flg & 1987 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM 1988 | ERR_FLAG_LEN))) { 1989 /* packet error, don't need upstream */ 1990 buffer_info->alloced = 0; 1991 rrd->xsz.valid = 0; 1992 continue; 1993 } 1994 } 1995 1996 /* Good Receive */ 1997 pci_unmap_page(adapter->pdev, buffer_info->dma, 1998 buffer_info->length, PCI_DMA_FROMDEVICE); 1999 buffer_info->dma = 0; 2000 skb = buffer_info->skb; 2001 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size); 2002 2003 skb_put(skb, length - ETH_FCS_LEN); 2004 2005 /* Receive Checksum Offload */ 2006 atl1_rx_checksum(adapter, rrd, skb); 2007 skb->protocol = eth_type_trans(skb, adapter->netdev); 2008 2009 if (rrd->pkt_flg & PACKET_FLAG_VLAN_INS) { 2010 u16 vlan_tag = (rrd->vlan_tag >> 4) | 2011 ((rrd->vlan_tag & 7) << 13) | 2012 ((rrd->vlan_tag & 8) << 9); 2013 2014 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 2015 } 2016 netif_receive_skb(skb); 2017 2018 /* let protocol layer free skb */ 2019 buffer_info->skb = NULL; 2020 buffer_info->alloced = 0; 2021 rrd->xsz.valid = 0; 2022 } 2023 2024 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean); 2025 2026 atl1_alloc_rx_buffers(adapter); 2027 2028 /* update mailbox ? */ 2029 if (count) { 2030 u32 tpd_next_to_use; 2031 u32 rfd_next_to_use; 2032 2033 spin_lock(&adapter->mb_lock); 2034 2035 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); 2036 rfd_next_to_use = 2037 atomic_read(&adapter->rfd_ring.next_to_use); 2038 rrd_next_to_clean = 2039 atomic_read(&adapter->rrd_ring.next_to_clean); 2040 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << 2041 MB_RFD_PROD_INDX_SHIFT) | 2042 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << 2043 MB_RRD_CONS_INDX_SHIFT) | 2044 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << 2045 MB_TPD_PROD_INDX_SHIFT); 2046 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); 2047 spin_unlock(&adapter->mb_lock); 2048 } 2049 2050 return count; 2051 } 2052 2053 static int atl1_intr_tx(struct atl1_adapter *adapter) 2054 { 2055 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2056 struct atl1_buffer *buffer_info; 2057 u16 sw_tpd_next_to_clean; 2058 u16 cmb_tpd_next_to_clean; 2059 int count = 0; 2060 2061 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean); 2062 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx); 2063 2064 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) { 2065 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean]; 2066 if (buffer_info->dma) { 2067 pci_unmap_page(adapter->pdev, buffer_info->dma, 2068 buffer_info->length, PCI_DMA_TODEVICE); 2069 buffer_info->dma = 0; 2070 } 2071 2072 if (buffer_info->skb) { 2073 dev_consume_skb_irq(buffer_info->skb); 2074 buffer_info->skb = NULL; 2075 } 2076 2077 if (++sw_tpd_next_to_clean == tpd_ring->count) 2078 sw_tpd_next_to_clean = 0; 2079 2080 count++; 2081 } 2082 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean); 2083 2084 if (netif_queue_stopped(adapter->netdev) && 2085 netif_carrier_ok(adapter->netdev)) 2086 netif_wake_queue(adapter->netdev); 2087 2088 return count; 2089 } 2090 2091 static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring) 2092 { 2093 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean); 2094 u16 next_to_use = atomic_read(&tpd_ring->next_to_use); 2095 return (next_to_clean > next_to_use) ? 2096 next_to_clean - next_to_use - 1 : 2097 tpd_ring->count + next_to_clean - next_to_use - 1; 2098 } 2099 2100 static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb, 2101 struct tx_packet_desc *ptpd) 2102 { 2103 u8 hdr_len, ip_off; 2104 u32 real_len; 2105 2106 if (skb_shinfo(skb)->gso_size) { 2107 int err; 2108 2109 err = skb_cow_head(skb, 0); 2110 if (err < 0) 2111 return err; 2112 2113 if (skb->protocol == htons(ETH_P_IP)) { 2114 struct iphdr *iph = ip_hdr(skb); 2115 2116 real_len = (((unsigned char *)iph - skb->data) + 2117 ntohs(iph->tot_len)); 2118 if (real_len < skb->len) 2119 pskb_trim(skb, real_len); 2120 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb)); 2121 if (skb->len == hdr_len) { 2122 iph->check = 0; 2123 tcp_hdr(skb)->check = 2124 ~csum_tcpudp_magic(iph->saddr, 2125 iph->daddr, tcp_hdrlen(skb), 2126 IPPROTO_TCP, 0); 2127 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) << 2128 TPD_IPHL_SHIFT; 2129 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) & 2130 TPD_TCPHDRLEN_MASK) << 2131 TPD_TCPHDRLEN_SHIFT; 2132 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT; 2133 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT; 2134 return 1; 2135 } 2136 2137 iph->check = 0; 2138 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 2139 iph->daddr, 0, IPPROTO_TCP, 0); 2140 ip_off = (unsigned char *)iph - 2141 (unsigned char *) skb_network_header(skb); 2142 if (ip_off == 8) /* 802.3-SNAP frame */ 2143 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; 2144 else if (ip_off != 0) 2145 return -2; 2146 2147 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) << 2148 TPD_IPHL_SHIFT; 2149 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) & 2150 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT; 2151 ptpd->word3 |= (skb_shinfo(skb)->gso_size & 2152 TPD_MSS_MASK) << TPD_MSS_SHIFT; 2153 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT; 2154 return 3; 2155 } 2156 } 2157 return 0; 2158 } 2159 2160 static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb, 2161 struct tx_packet_desc *ptpd) 2162 { 2163 u8 css, cso; 2164 2165 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 2166 css = skb_checksum_start_offset(skb); 2167 cso = css + (u8) skb->csum_offset; 2168 if (unlikely(css & 0x1)) { 2169 /* L1 hardware requires an even number here */ 2170 if (netif_msg_tx_err(adapter)) 2171 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2172 "payload offset not an even number\n"); 2173 return -1; 2174 } 2175 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) << 2176 TPD_PLOADOFFSET_SHIFT; 2177 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) << 2178 TPD_CCSUMOFFSET_SHIFT; 2179 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT; 2180 return true; 2181 } 2182 return 0; 2183 } 2184 2185 static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb, 2186 struct tx_packet_desc *ptpd) 2187 { 2188 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2189 struct atl1_buffer *buffer_info; 2190 u16 buf_len = skb->len; 2191 struct page *page; 2192 unsigned long offset; 2193 unsigned int nr_frags; 2194 unsigned int f; 2195 int retval; 2196 u16 next_to_use; 2197 u16 data_len; 2198 u8 hdr_len; 2199 2200 buf_len -= skb->data_len; 2201 nr_frags = skb_shinfo(skb)->nr_frags; 2202 next_to_use = atomic_read(&tpd_ring->next_to_use); 2203 buffer_info = &tpd_ring->buffer_info[next_to_use]; 2204 BUG_ON(buffer_info->skb); 2205 /* put skb in last TPD */ 2206 buffer_info->skb = NULL; 2207 2208 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK; 2209 if (retval) { 2210 /* TSO */ 2211 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2212 buffer_info->length = hdr_len; 2213 page = virt_to_page(skb->data); 2214 offset = offset_in_page(skb->data); 2215 buffer_info->dma = pci_map_page(adapter->pdev, page, 2216 offset, hdr_len, 2217 PCI_DMA_TODEVICE); 2218 2219 if (++next_to_use == tpd_ring->count) 2220 next_to_use = 0; 2221 2222 if (buf_len > hdr_len) { 2223 int i, nseg; 2224 2225 data_len = buf_len - hdr_len; 2226 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) / 2227 ATL1_MAX_TX_BUF_LEN; 2228 for (i = 0; i < nseg; i++) { 2229 buffer_info = 2230 &tpd_ring->buffer_info[next_to_use]; 2231 buffer_info->skb = NULL; 2232 buffer_info->length = 2233 (ATL1_MAX_TX_BUF_LEN >= 2234 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len; 2235 data_len -= buffer_info->length; 2236 page = virt_to_page(skb->data + 2237 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)); 2238 offset = offset_in_page(skb->data + 2239 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)); 2240 buffer_info->dma = pci_map_page(adapter->pdev, 2241 page, offset, buffer_info->length, 2242 PCI_DMA_TODEVICE); 2243 if (++next_to_use == tpd_ring->count) 2244 next_to_use = 0; 2245 } 2246 } 2247 } else { 2248 /* not TSO */ 2249 buffer_info->length = buf_len; 2250 page = virt_to_page(skb->data); 2251 offset = offset_in_page(skb->data); 2252 buffer_info->dma = pci_map_page(adapter->pdev, page, 2253 offset, buf_len, PCI_DMA_TODEVICE); 2254 if (++next_to_use == tpd_ring->count) 2255 next_to_use = 0; 2256 } 2257 2258 for (f = 0; f < nr_frags; f++) { 2259 const struct skb_frag_struct *frag; 2260 u16 i, nseg; 2261 2262 frag = &skb_shinfo(skb)->frags[f]; 2263 buf_len = skb_frag_size(frag); 2264 2265 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) / 2266 ATL1_MAX_TX_BUF_LEN; 2267 for (i = 0; i < nseg; i++) { 2268 buffer_info = &tpd_ring->buffer_info[next_to_use]; 2269 BUG_ON(buffer_info->skb); 2270 2271 buffer_info->skb = NULL; 2272 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ? 2273 ATL1_MAX_TX_BUF_LEN : buf_len; 2274 buf_len -= buffer_info->length; 2275 buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev, 2276 frag, i * ATL1_MAX_TX_BUF_LEN, 2277 buffer_info->length, DMA_TO_DEVICE); 2278 2279 if (++next_to_use == tpd_ring->count) 2280 next_to_use = 0; 2281 } 2282 } 2283 2284 /* last tpd's buffer-info */ 2285 buffer_info->skb = skb; 2286 } 2287 2288 static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count, 2289 struct tx_packet_desc *ptpd) 2290 { 2291 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2292 struct atl1_buffer *buffer_info; 2293 struct tx_packet_desc *tpd; 2294 u16 j; 2295 u32 val; 2296 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use); 2297 2298 for (j = 0; j < count; j++) { 2299 buffer_info = &tpd_ring->buffer_info[next_to_use]; 2300 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use); 2301 if (tpd != ptpd) 2302 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc)); 2303 tpd->buffer_addr = cpu_to_le64(buffer_info->dma); 2304 tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT); 2305 tpd->word2 |= (cpu_to_le16(buffer_info->length) & 2306 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT; 2307 2308 /* 2309 * if this is the first packet in a TSO chain, set 2310 * TPD_HDRFLAG, otherwise, clear it. 2311 */ 2312 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & 2313 TPD_SEGMENT_EN_MASK; 2314 if (val) { 2315 if (!j) 2316 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT; 2317 else 2318 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT); 2319 } 2320 2321 if (j == (count - 1)) 2322 tpd->word3 |= 1 << TPD_EOP_SHIFT; 2323 2324 if (++next_to_use == tpd_ring->count) 2325 next_to_use = 0; 2326 } 2327 /* 2328 * Force memory writes to complete before letting h/w 2329 * know there are new descriptors to fetch. (Only 2330 * applicable for weak-ordered memory model archs, 2331 * such as IA-64). 2332 */ 2333 wmb(); 2334 2335 atomic_set(&tpd_ring->next_to_use, next_to_use); 2336 } 2337 2338 static netdev_tx_t atl1_xmit_frame(struct sk_buff *skb, 2339 struct net_device *netdev) 2340 { 2341 struct atl1_adapter *adapter = netdev_priv(netdev); 2342 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; 2343 int len; 2344 int tso; 2345 int count = 1; 2346 int ret_val; 2347 struct tx_packet_desc *ptpd; 2348 u16 vlan_tag; 2349 unsigned int nr_frags = 0; 2350 unsigned int mss = 0; 2351 unsigned int f; 2352 unsigned int proto_hdr_len; 2353 2354 len = skb_headlen(skb); 2355 2356 if (unlikely(skb->len <= 0)) { 2357 dev_kfree_skb_any(skb); 2358 return NETDEV_TX_OK; 2359 } 2360 2361 nr_frags = skb_shinfo(skb)->nr_frags; 2362 for (f = 0; f < nr_frags; f++) { 2363 unsigned int f_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); 2364 count += (f_size + ATL1_MAX_TX_BUF_LEN - 1) / 2365 ATL1_MAX_TX_BUF_LEN; 2366 } 2367 2368 mss = skb_shinfo(skb)->gso_size; 2369 if (mss) { 2370 if (skb->protocol == htons(ETH_P_IP)) { 2371 proto_hdr_len = (skb_transport_offset(skb) + 2372 tcp_hdrlen(skb)); 2373 if (unlikely(proto_hdr_len > len)) { 2374 dev_kfree_skb_any(skb); 2375 return NETDEV_TX_OK; 2376 } 2377 /* need additional TPD ? */ 2378 if (proto_hdr_len != len) 2379 count += (len - proto_hdr_len + 2380 ATL1_MAX_TX_BUF_LEN - 1) / 2381 ATL1_MAX_TX_BUF_LEN; 2382 } 2383 } 2384 2385 if (atl1_tpd_avail(&adapter->tpd_ring) < count) { 2386 /* not enough descriptors */ 2387 netif_stop_queue(netdev); 2388 if (netif_msg_tx_queued(adapter)) 2389 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2390 "tx busy\n"); 2391 return NETDEV_TX_BUSY; 2392 } 2393 2394 ptpd = ATL1_TPD_DESC(tpd_ring, 2395 (u16) atomic_read(&tpd_ring->next_to_use)); 2396 memset(ptpd, 0, sizeof(struct tx_packet_desc)); 2397 2398 if (skb_vlan_tag_present(skb)) { 2399 vlan_tag = skb_vlan_tag_get(skb); 2400 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) | 2401 ((vlan_tag >> 9) & 0x8); 2402 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT; 2403 ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) << 2404 TPD_VLANTAG_SHIFT; 2405 } 2406 2407 tso = atl1_tso(adapter, skb, ptpd); 2408 if (tso < 0) { 2409 dev_kfree_skb_any(skb); 2410 return NETDEV_TX_OK; 2411 } 2412 2413 if (!tso) { 2414 ret_val = atl1_tx_csum(adapter, skb, ptpd); 2415 if (ret_val < 0) { 2416 dev_kfree_skb_any(skb); 2417 return NETDEV_TX_OK; 2418 } 2419 } 2420 2421 atl1_tx_map(adapter, skb, ptpd); 2422 atl1_tx_queue(adapter, count, ptpd); 2423 atl1_update_mailbox(adapter); 2424 return NETDEV_TX_OK; 2425 } 2426 2427 static int atl1_rings_clean(struct napi_struct *napi, int budget) 2428 { 2429 struct atl1_adapter *adapter = container_of(napi, struct atl1_adapter, napi); 2430 int work_done = atl1_intr_rx(adapter, budget); 2431 2432 if (atl1_intr_tx(adapter)) 2433 work_done = budget; 2434 2435 /* Let's come again to process some more packets */ 2436 if (work_done >= budget) 2437 return work_done; 2438 2439 napi_complete_done(napi, work_done); 2440 /* re-enable Interrupt */ 2441 if (likely(adapter->int_enabled)) 2442 atlx_imr_set(adapter, IMR_NORMAL_MASK); 2443 return work_done; 2444 } 2445 2446 static inline int atl1_sched_rings_clean(struct atl1_adapter* adapter) 2447 { 2448 if (!napi_schedule_prep(&adapter->napi)) 2449 /* It is possible in case even the RX/TX ints are disabled via IMR 2450 * register the ISR bits are set anyway (but do not produce IRQ). 2451 * To handle such situation the napi functions used to check is 2452 * something scheduled or not. 2453 */ 2454 return 0; 2455 2456 __napi_schedule(&adapter->napi); 2457 2458 /* 2459 * Disable RX/TX ints via IMR register if it is 2460 * allowed. NAPI handler must reenable them in same 2461 * way. 2462 */ 2463 if (!adapter->int_enabled) 2464 return 1; 2465 2466 atlx_imr_set(adapter, IMR_NORXTX_MASK); 2467 return 1; 2468 } 2469 2470 /** 2471 * atl1_intr - Interrupt Handler 2472 * @irq: interrupt number 2473 * @data: pointer to a network interface device structure 2474 */ 2475 static irqreturn_t atl1_intr(int irq, void *data) 2476 { 2477 struct atl1_adapter *adapter = netdev_priv(data); 2478 u32 status; 2479 2480 status = adapter->cmb.cmb->int_stats; 2481 if (!status) 2482 return IRQ_NONE; 2483 2484 /* clear CMB interrupt status at once, 2485 * but leave rx/tx interrupt status in case it should be dropped 2486 * only if rx/tx processing queued. In other case interrupt 2487 * can be lost. 2488 */ 2489 adapter->cmb.cmb->int_stats = status & (ISR_CMB_TX | ISR_CMB_RX); 2490 2491 if (status & ISR_GPHY) /* clear phy status */ 2492 atlx_clear_phy_int(adapter); 2493 2494 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 2495 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR); 2496 2497 /* check if SMB intr */ 2498 if (status & ISR_SMB) 2499 atl1_inc_smb(adapter); 2500 2501 /* check if PCIE PHY Link down */ 2502 if (status & ISR_PHY_LINKDOWN) { 2503 if (netif_msg_intr(adapter)) 2504 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2505 "pcie phy link down %x\n", status); 2506 if (netif_running(adapter->netdev)) { /* reset MAC */ 2507 atlx_irq_disable(adapter); 2508 schedule_work(&adapter->reset_dev_task); 2509 return IRQ_HANDLED; 2510 } 2511 } 2512 2513 /* check if DMA read/write error ? */ 2514 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 2515 if (netif_msg_intr(adapter)) 2516 dev_printk(KERN_DEBUG, &adapter->pdev->dev, 2517 "pcie DMA r/w error (status = 0x%x)\n", 2518 status); 2519 atlx_irq_disable(adapter); 2520 schedule_work(&adapter->reset_dev_task); 2521 return IRQ_HANDLED; 2522 } 2523 2524 /* link event */ 2525 if (status & ISR_GPHY) { 2526 adapter->soft_stats.tx_carrier_errors++; 2527 atl1_check_for_link(adapter); 2528 } 2529 2530 /* transmit or receive event */ 2531 if (status & (ISR_CMB_TX | ISR_CMB_RX) && 2532 atl1_sched_rings_clean(adapter)) 2533 adapter->cmb.cmb->int_stats = adapter->cmb.cmb->int_stats & 2534 ~(ISR_CMB_TX | ISR_CMB_RX); 2535 2536 /* rx exception */ 2537 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN | 2538 ISR_RRD_OV | ISR_HOST_RFD_UNRUN | 2539 ISR_HOST_RRD_OV))) { 2540 if (netif_msg_intr(adapter)) 2541 dev_printk(KERN_DEBUG, 2542 &adapter->pdev->dev, 2543 "rx exception, ISR = 0x%x\n", 2544 status); 2545 atl1_sched_rings_clean(adapter); 2546 } 2547 2548 /* re-enable Interrupt */ 2549 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR); 2550 return IRQ_HANDLED; 2551 } 2552 2553 2554 /** 2555 * atl1_phy_config - Timer Call-back 2556 * @data: pointer to netdev cast into an unsigned long 2557 */ 2558 static void atl1_phy_config(struct timer_list *t) 2559 { 2560 struct atl1_adapter *adapter = from_timer(adapter, t, 2561 phy_config_timer); 2562 struct atl1_hw *hw = &adapter->hw; 2563 unsigned long flags; 2564 2565 spin_lock_irqsave(&adapter->lock, flags); 2566 adapter->phy_timer_pending = false; 2567 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 2568 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg); 2569 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN); 2570 spin_unlock_irqrestore(&adapter->lock, flags); 2571 } 2572 2573 /* 2574 * Orphaned vendor comment left intact here: 2575 * <vendor comment> 2576 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT 2577 * will assert. We do soft reset <0x1400=1> according 2578 * with the SPEC. BUT, it seemes that PCIE or DMA 2579 * state-machine will not be reset. DMAR_TO_INT will 2580 * assert again and again. 2581 * </vendor comment> 2582 */ 2583 2584 static int atl1_reset(struct atl1_adapter *adapter) 2585 { 2586 int ret; 2587 ret = atl1_reset_hw(&adapter->hw); 2588 if (ret) 2589 return ret; 2590 return atl1_init_hw(&adapter->hw); 2591 } 2592 2593 static s32 atl1_up(struct atl1_adapter *adapter) 2594 { 2595 struct net_device *netdev = adapter->netdev; 2596 int err; 2597 int irq_flags = 0; 2598 2599 /* hardware has been reset, we need to reload some things */ 2600 atlx_set_multi(netdev); 2601 atl1_init_ring_ptrs(adapter); 2602 atlx_restore_vlan(adapter); 2603 err = atl1_alloc_rx_buffers(adapter); 2604 if (unlikely(!err)) 2605 /* no RX BUFFER allocated */ 2606 return -ENOMEM; 2607 2608 if (unlikely(atl1_configure(adapter))) { 2609 err = -EIO; 2610 goto err_up; 2611 } 2612 2613 err = pci_enable_msi(adapter->pdev); 2614 if (err) { 2615 if (netif_msg_ifup(adapter)) 2616 dev_info(&adapter->pdev->dev, 2617 "Unable to enable MSI: %d\n", err); 2618 irq_flags |= IRQF_SHARED; 2619 } 2620 2621 err = request_irq(adapter->pdev->irq, atl1_intr, irq_flags, 2622 netdev->name, netdev); 2623 if (unlikely(err)) 2624 goto err_up; 2625 2626 napi_enable(&adapter->napi); 2627 atlx_irq_enable(adapter); 2628 atl1_check_link(adapter); 2629 netif_start_queue(netdev); 2630 return 0; 2631 2632 err_up: 2633 pci_disable_msi(adapter->pdev); 2634 /* free rx_buffers */ 2635 atl1_clean_rx_ring(adapter); 2636 return err; 2637 } 2638 2639 static void atl1_down(struct atl1_adapter *adapter) 2640 { 2641 struct net_device *netdev = adapter->netdev; 2642 2643 napi_disable(&adapter->napi); 2644 netif_stop_queue(netdev); 2645 del_timer_sync(&adapter->phy_config_timer); 2646 adapter->phy_timer_pending = false; 2647 2648 atlx_irq_disable(adapter); 2649 free_irq(adapter->pdev->irq, netdev); 2650 pci_disable_msi(adapter->pdev); 2651 atl1_reset_hw(&adapter->hw); 2652 adapter->cmb.cmb->int_stats = 0; 2653 2654 adapter->link_speed = SPEED_0; 2655 adapter->link_duplex = -1; 2656 netif_carrier_off(netdev); 2657 2658 atl1_clean_tx_ring(adapter); 2659 atl1_clean_rx_ring(adapter); 2660 } 2661 2662 static void atl1_reset_dev_task(struct work_struct *work) 2663 { 2664 struct atl1_adapter *adapter = 2665 container_of(work, struct atl1_adapter, reset_dev_task); 2666 struct net_device *netdev = adapter->netdev; 2667 2668 netif_device_detach(netdev); 2669 atl1_down(adapter); 2670 atl1_up(adapter); 2671 netif_device_attach(netdev); 2672 } 2673 2674 /** 2675 * atl1_change_mtu - Change the Maximum Transfer Unit 2676 * @netdev: network interface device structure 2677 * @new_mtu: new value for maximum frame size 2678 * 2679 * Returns 0 on success, negative on failure 2680 */ 2681 static int atl1_change_mtu(struct net_device *netdev, int new_mtu) 2682 { 2683 struct atl1_adapter *adapter = netdev_priv(netdev); 2684 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 2685 2686 adapter->hw.max_frame_size = max_frame; 2687 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3; 2688 adapter->rx_buffer_len = (max_frame + 7) & ~7; 2689 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8; 2690 2691 netdev->mtu = new_mtu; 2692 if (netif_running(netdev)) { 2693 atl1_down(adapter); 2694 atl1_up(adapter); 2695 } 2696 2697 return 0; 2698 } 2699 2700 /** 2701 * atl1_open - Called when a network interface is made active 2702 * @netdev: network interface device structure 2703 * 2704 * Returns 0 on success, negative value on failure 2705 * 2706 * The open entry point is called when a network interface is made 2707 * active by the system (IFF_UP). At this point all resources needed 2708 * for transmit and receive operations are allocated, the interrupt 2709 * handler is registered with the OS, the watchdog timer is started, 2710 * and the stack is notified that the interface is ready. 2711 */ 2712 static int atl1_open(struct net_device *netdev) 2713 { 2714 struct atl1_adapter *adapter = netdev_priv(netdev); 2715 int err; 2716 2717 netif_carrier_off(netdev); 2718 2719 /* allocate transmit descriptors */ 2720 err = atl1_setup_ring_resources(adapter); 2721 if (err) 2722 return err; 2723 2724 err = atl1_up(adapter); 2725 if (err) 2726 goto err_up; 2727 2728 return 0; 2729 2730 err_up: 2731 atl1_reset(adapter); 2732 return err; 2733 } 2734 2735 /** 2736 * atl1_close - Disables a network interface 2737 * @netdev: network interface device structure 2738 * 2739 * Returns 0, this is not allowed to fail 2740 * 2741 * The close entry point is called when an interface is de-activated 2742 * by the OS. The hardware is still under the drivers control, but 2743 * needs to be disabled. A global MAC reset is issued to stop the 2744 * hardware, and all transmit and receive resources are freed. 2745 */ 2746 static int atl1_close(struct net_device *netdev) 2747 { 2748 struct atl1_adapter *adapter = netdev_priv(netdev); 2749 atl1_down(adapter); 2750 atl1_free_ring_resources(adapter); 2751 return 0; 2752 } 2753 2754 #ifdef CONFIG_PM_SLEEP 2755 static int atl1_suspend(struct device *dev) 2756 { 2757 struct pci_dev *pdev = to_pci_dev(dev); 2758 struct net_device *netdev = pci_get_drvdata(pdev); 2759 struct atl1_adapter *adapter = netdev_priv(netdev); 2760 struct atl1_hw *hw = &adapter->hw; 2761 u32 ctrl = 0; 2762 u32 wufc = adapter->wol; 2763 u32 val; 2764 u16 speed; 2765 u16 duplex; 2766 2767 netif_device_detach(netdev); 2768 if (netif_running(netdev)) 2769 atl1_down(adapter); 2770 2771 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); 2772 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); 2773 val = ctrl & BMSR_LSTATUS; 2774 if (val) 2775 wufc &= ~ATLX_WUFC_LNKC; 2776 if (!wufc) 2777 goto disable_wol; 2778 2779 if (val) { 2780 val = atl1_get_speed_and_duplex(hw, &speed, &duplex); 2781 if (val) { 2782 if (netif_msg_ifdown(adapter)) 2783 dev_printk(KERN_DEBUG, &pdev->dev, 2784 "error getting speed/duplex\n"); 2785 goto disable_wol; 2786 } 2787 2788 ctrl = 0; 2789 2790 /* enable magic packet WOL */ 2791 if (wufc & ATLX_WUFC_MAG) 2792 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); 2793 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); 2794 ioread32(hw->hw_addr + REG_WOL_CTRL); 2795 2796 /* configure the mac */ 2797 ctrl = MAC_CTRL_RX_EN; 2798 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 : 2799 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT); 2800 if (duplex == FULL_DUPLEX) 2801 ctrl |= MAC_CTRL_DUPLX; 2802 ctrl |= (((u32)adapter->hw.preamble_len & 2803 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 2804 __atlx_vlan_mode(netdev->features, &ctrl); 2805 if (wufc & ATLX_WUFC_MAG) 2806 ctrl |= MAC_CTRL_BC_EN; 2807 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL); 2808 ioread32(hw->hw_addr + REG_MAC_CTRL); 2809 2810 /* poke the PHY */ 2811 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2812 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 2813 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); 2814 ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2815 } else { 2816 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 2817 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); 2818 ioread32(hw->hw_addr + REG_WOL_CTRL); 2819 iowrite32(0, hw->hw_addr + REG_MAC_CTRL); 2820 ioread32(hw->hw_addr + REG_MAC_CTRL); 2821 hw->phy_configured = false; 2822 } 2823 2824 return 0; 2825 2826 disable_wol: 2827 iowrite32(0, hw->hw_addr + REG_WOL_CTRL); 2828 ioread32(hw->hw_addr + REG_WOL_CTRL); 2829 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2830 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 2831 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); 2832 ioread32(hw->hw_addr + REG_PCIE_PHYMISC); 2833 hw->phy_configured = false; 2834 2835 return 0; 2836 } 2837 2838 static int atl1_resume(struct device *dev) 2839 { 2840 struct pci_dev *pdev = to_pci_dev(dev); 2841 struct net_device *netdev = pci_get_drvdata(pdev); 2842 struct atl1_adapter *adapter = netdev_priv(netdev); 2843 2844 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL); 2845 2846 atl1_reset_hw(&adapter->hw); 2847 2848 if (netif_running(netdev)) { 2849 adapter->cmb.cmb->int_stats = 0; 2850 atl1_up(adapter); 2851 } 2852 netif_device_attach(netdev); 2853 2854 return 0; 2855 } 2856 #endif 2857 2858 static SIMPLE_DEV_PM_OPS(atl1_pm_ops, atl1_suspend, atl1_resume); 2859 2860 static void atl1_shutdown(struct pci_dev *pdev) 2861 { 2862 struct net_device *netdev = pci_get_drvdata(pdev); 2863 struct atl1_adapter *adapter = netdev_priv(netdev); 2864 2865 #ifdef CONFIG_PM_SLEEP 2866 atl1_suspend(&pdev->dev); 2867 #endif 2868 pci_wake_from_d3(pdev, adapter->wol); 2869 pci_set_power_state(pdev, PCI_D3hot); 2870 } 2871 2872 #ifdef CONFIG_NET_POLL_CONTROLLER 2873 static void atl1_poll_controller(struct net_device *netdev) 2874 { 2875 disable_irq(netdev->irq); 2876 atl1_intr(netdev->irq, netdev); 2877 enable_irq(netdev->irq); 2878 } 2879 #endif 2880 2881 static const struct net_device_ops atl1_netdev_ops = { 2882 .ndo_open = atl1_open, 2883 .ndo_stop = atl1_close, 2884 .ndo_start_xmit = atl1_xmit_frame, 2885 .ndo_set_rx_mode = atlx_set_multi, 2886 .ndo_validate_addr = eth_validate_addr, 2887 .ndo_set_mac_address = atl1_set_mac, 2888 .ndo_change_mtu = atl1_change_mtu, 2889 .ndo_fix_features = atlx_fix_features, 2890 .ndo_set_features = atlx_set_features, 2891 .ndo_do_ioctl = atlx_ioctl, 2892 .ndo_tx_timeout = atlx_tx_timeout, 2893 #ifdef CONFIG_NET_POLL_CONTROLLER 2894 .ndo_poll_controller = atl1_poll_controller, 2895 #endif 2896 }; 2897 2898 /** 2899 * atl1_probe - Device Initialization Routine 2900 * @pdev: PCI device information struct 2901 * @ent: entry in atl1_pci_tbl 2902 * 2903 * Returns 0 on success, negative on failure 2904 * 2905 * atl1_probe initializes an adapter identified by a pci_dev structure. 2906 * The OS initialization, configuring of the adapter private structure, 2907 * and a hardware reset occur. 2908 */ 2909 static int atl1_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2910 { 2911 struct net_device *netdev; 2912 struct atl1_adapter *adapter; 2913 static int cards_found = 0; 2914 int err; 2915 2916 err = pci_enable_device(pdev); 2917 if (err) 2918 return err; 2919 2920 /* 2921 * The atl1 chip can DMA to 64-bit addresses, but it uses a single 2922 * shared register for the high 32 bits, so only a single, aligned, 2923 * 4 GB physical address range can be used at a time. 2924 * 2925 * Supporting 64-bit DMA on this hardware is more trouble than it's 2926 * worth. It is far easier to limit to 32-bit DMA than update 2927 * various kernel subsystems to support the mechanics required by a 2928 * fixed-high-32-bit system. 2929 */ 2930 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2931 if (err) { 2932 dev_err(&pdev->dev, "no usable DMA configuration\n"); 2933 goto err_dma; 2934 } 2935 /* 2936 * Mark all PCI regions associated with PCI device 2937 * pdev as being reserved by owner atl1_driver_name 2938 */ 2939 err = pci_request_regions(pdev, ATLX_DRIVER_NAME); 2940 if (err) 2941 goto err_request_regions; 2942 2943 /* 2944 * Enables bus-mastering on the device and calls 2945 * pcibios_set_master to do the needed arch specific settings 2946 */ 2947 pci_set_master(pdev); 2948 2949 netdev = alloc_etherdev(sizeof(struct atl1_adapter)); 2950 if (!netdev) { 2951 err = -ENOMEM; 2952 goto err_alloc_etherdev; 2953 } 2954 SET_NETDEV_DEV(netdev, &pdev->dev); 2955 2956 pci_set_drvdata(pdev, netdev); 2957 adapter = netdev_priv(netdev); 2958 adapter->netdev = netdev; 2959 adapter->pdev = pdev; 2960 adapter->hw.back = adapter; 2961 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg); 2962 2963 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0); 2964 if (!adapter->hw.hw_addr) { 2965 err = -EIO; 2966 goto err_pci_iomap; 2967 } 2968 /* get device revision number */ 2969 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr + 2970 (REG_MASTER_CTRL + 2)); 2971 if (netif_msg_probe(adapter)) 2972 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION); 2973 2974 /* set default ring resource counts */ 2975 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD; 2976 adapter->tpd_ring.count = ATL1_DEFAULT_TPD; 2977 2978 adapter->mii.dev = netdev; 2979 adapter->mii.mdio_read = mdio_read; 2980 adapter->mii.mdio_write = mdio_write; 2981 adapter->mii.phy_id_mask = 0x1f; 2982 adapter->mii.reg_num_mask = 0x1f; 2983 2984 netdev->netdev_ops = &atl1_netdev_ops; 2985 netdev->watchdog_timeo = 5 * HZ; 2986 netif_napi_add(netdev, &adapter->napi, atl1_rings_clean, 64); 2987 2988 netdev->ethtool_ops = &atl1_ethtool_ops; 2989 adapter->bd_number = cards_found; 2990 2991 /* setup the private structure */ 2992 err = atl1_sw_init(adapter); 2993 if (err) 2994 goto err_common; 2995 2996 netdev->features = NETIF_F_HW_CSUM; 2997 netdev->features |= NETIF_F_SG; 2998 netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2999 3000 netdev->hw_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_TSO | 3001 NETIF_F_HW_VLAN_CTAG_RX; 3002 3003 /* is this valid? see atl1_setup_mac_ctrl() */ 3004 netdev->features |= NETIF_F_RXCSUM; 3005 3006 /* MTU range: 42 - 10218 */ 3007 netdev->min_mtu = ETH_ZLEN - (ETH_HLEN + VLAN_HLEN); 3008 netdev->max_mtu = MAX_JUMBO_FRAME_SIZE - 3009 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); 3010 3011 /* 3012 * patch for some L1 of old version, 3013 * the final version of L1 may not need these 3014 * patches 3015 */ 3016 /* atl1_pcie_patch(adapter); */ 3017 3018 /* really reset GPHY core */ 3019 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); 3020 3021 /* 3022 * reset the controller to 3023 * put the device in a known good starting state 3024 */ 3025 if (atl1_reset_hw(&adapter->hw)) { 3026 err = -EIO; 3027 goto err_common; 3028 } 3029 3030 /* copy the MAC address out of the EEPROM */ 3031 if (atl1_read_mac_addr(&adapter->hw)) { 3032 /* mark random mac */ 3033 netdev->addr_assign_type = NET_ADDR_RANDOM; 3034 } 3035 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); 3036 3037 if (!is_valid_ether_addr(netdev->dev_addr)) { 3038 err = -EIO; 3039 goto err_common; 3040 } 3041 3042 atl1_check_options(adapter); 3043 3044 /* pre-init the MAC, and setup link */ 3045 err = atl1_init_hw(&adapter->hw); 3046 if (err) { 3047 err = -EIO; 3048 goto err_common; 3049 } 3050 3051 atl1_pcie_patch(adapter); 3052 /* assume we have no link for now */ 3053 netif_carrier_off(netdev); 3054 3055 timer_setup(&adapter->phy_config_timer, atl1_phy_config, 0); 3056 adapter->phy_timer_pending = false; 3057 3058 INIT_WORK(&adapter->reset_dev_task, atl1_reset_dev_task); 3059 3060 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task); 3061 3062 err = register_netdev(netdev); 3063 if (err) 3064 goto err_common; 3065 3066 cards_found++; 3067 atl1_via_workaround(adapter); 3068 return 0; 3069 3070 err_common: 3071 pci_iounmap(pdev, adapter->hw.hw_addr); 3072 err_pci_iomap: 3073 free_netdev(netdev); 3074 err_alloc_etherdev: 3075 pci_release_regions(pdev); 3076 err_dma: 3077 err_request_regions: 3078 pci_disable_device(pdev); 3079 return err; 3080 } 3081 3082 /** 3083 * atl1_remove - Device Removal Routine 3084 * @pdev: PCI device information struct 3085 * 3086 * atl1_remove is called by the PCI subsystem to alert the driver 3087 * that it should release a PCI device. The could be caused by a 3088 * Hot-Plug event, or because the driver is going to be removed from 3089 * memory. 3090 */ 3091 static void atl1_remove(struct pci_dev *pdev) 3092 { 3093 struct net_device *netdev = pci_get_drvdata(pdev); 3094 struct atl1_adapter *adapter; 3095 /* Device not available. Return. */ 3096 if (!netdev) 3097 return; 3098 3099 adapter = netdev_priv(netdev); 3100 3101 /* 3102 * Some atl1 boards lack persistent storage for their MAC, and get it 3103 * from the BIOS during POST. If we've been messing with the MAC 3104 * address, we need to save the permanent one. 3105 */ 3106 if (!ether_addr_equal_unaligned(adapter->hw.mac_addr, 3107 adapter->hw.perm_mac_addr)) { 3108 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, 3109 ETH_ALEN); 3110 atl1_set_mac_addr(&adapter->hw); 3111 } 3112 3113 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); 3114 unregister_netdev(netdev); 3115 pci_iounmap(pdev, adapter->hw.hw_addr); 3116 pci_release_regions(pdev); 3117 free_netdev(netdev); 3118 pci_disable_device(pdev); 3119 } 3120 3121 static struct pci_driver atl1_driver = { 3122 .name = ATLX_DRIVER_NAME, 3123 .id_table = atl1_pci_tbl, 3124 .probe = atl1_probe, 3125 .remove = atl1_remove, 3126 .shutdown = atl1_shutdown, 3127 .driver.pm = &atl1_pm_ops, 3128 }; 3129 3130 struct atl1_stats { 3131 char stat_string[ETH_GSTRING_LEN]; 3132 int sizeof_stat; 3133 int stat_offset; 3134 }; 3135 3136 #define ATL1_STAT(m) \ 3137 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m) 3138 3139 static struct atl1_stats atl1_gstrings_stats[] = { 3140 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)}, 3141 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)}, 3142 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)}, 3143 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)}, 3144 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)}, 3145 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)}, 3146 {"multicast", ATL1_STAT(soft_stats.multicast)}, 3147 {"collisions", ATL1_STAT(soft_stats.collisions)}, 3148 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)}, 3149 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)}, 3150 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)}, 3151 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)}, 3152 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)}, 3153 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)}, 3154 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)}, 3155 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)}, 3156 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)}, 3157 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)}, 3158 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)}, 3159 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)}, 3160 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)}, 3161 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)}, 3162 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)}, 3163 {"tx_underrun", ATL1_STAT(soft_stats.tx_underrun)}, 3164 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)}, 3165 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)}, 3166 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)}, 3167 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)}, 3168 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)} 3169 }; 3170 3171 static void atl1_get_ethtool_stats(struct net_device *netdev, 3172 struct ethtool_stats *stats, u64 *data) 3173 { 3174 struct atl1_adapter *adapter = netdev_priv(netdev); 3175 int i; 3176 char *p; 3177 3178 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) { 3179 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset; 3180 data[i] = (atl1_gstrings_stats[i].sizeof_stat == 3181 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 3182 } 3183 3184 } 3185 3186 static int atl1_get_sset_count(struct net_device *netdev, int sset) 3187 { 3188 switch (sset) { 3189 case ETH_SS_STATS: 3190 return ARRAY_SIZE(atl1_gstrings_stats); 3191 default: 3192 return -EOPNOTSUPP; 3193 } 3194 } 3195 3196 static int atl1_get_link_ksettings(struct net_device *netdev, 3197 struct ethtool_link_ksettings *cmd) 3198 { 3199 struct atl1_adapter *adapter = netdev_priv(netdev); 3200 struct atl1_hw *hw = &adapter->hw; 3201 u32 supported, advertising; 3202 3203 supported = (SUPPORTED_10baseT_Half | 3204 SUPPORTED_10baseT_Full | 3205 SUPPORTED_100baseT_Half | 3206 SUPPORTED_100baseT_Full | 3207 SUPPORTED_1000baseT_Full | 3208 SUPPORTED_Autoneg | SUPPORTED_TP); 3209 advertising = ADVERTISED_TP; 3210 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3211 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3212 advertising |= ADVERTISED_Autoneg; 3213 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) { 3214 advertising |= ADVERTISED_Autoneg; 3215 advertising |= 3216 (ADVERTISED_10baseT_Half | 3217 ADVERTISED_10baseT_Full | 3218 ADVERTISED_100baseT_Half | 3219 ADVERTISED_100baseT_Full | 3220 ADVERTISED_1000baseT_Full); 3221 } else 3222 advertising |= (ADVERTISED_1000baseT_Full); 3223 } 3224 cmd->base.port = PORT_TP; 3225 cmd->base.phy_address = 0; 3226 3227 if (netif_carrier_ok(adapter->netdev)) { 3228 u16 link_speed, link_duplex; 3229 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex); 3230 cmd->base.speed = link_speed; 3231 if (link_duplex == FULL_DUPLEX) 3232 cmd->base.duplex = DUPLEX_FULL; 3233 else 3234 cmd->base.duplex = DUPLEX_HALF; 3235 } else { 3236 cmd->base.speed = SPEED_UNKNOWN; 3237 cmd->base.duplex = DUPLEX_UNKNOWN; 3238 } 3239 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3240 hw->media_type == MEDIA_TYPE_1000M_FULL) 3241 cmd->base.autoneg = AUTONEG_ENABLE; 3242 else 3243 cmd->base.autoneg = AUTONEG_DISABLE; 3244 3245 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3246 supported); 3247 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3248 advertising); 3249 3250 return 0; 3251 } 3252 3253 static int atl1_set_link_ksettings(struct net_device *netdev, 3254 const struct ethtool_link_ksettings *cmd) 3255 { 3256 struct atl1_adapter *adapter = netdev_priv(netdev); 3257 struct atl1_hw *hw = &adapter->hw; 3258 u16 phy_data; 3259 int ret_val = 0; 3260 u16 old_media_type = hw->media_type; 3261 3262 if (netif_running(adapter->netdev)) { 3263 if (netif_msg_link(adapter)) 3264 dev_dbg(&adapter->pdev->dev, 3265 "ethtool shutting down adapter\n"); 3266 atl1_down(adapter); 3267 } 3268 3269 if (cmd->base.autoneg == AUTONEG_ENABLE) 3270 hw->media_type = MEDIA_TYPE_AUTO_SENSOR; 3271 else { 3272 u32 speed = cmd->base.speed; 3273 if (speed == SPEED_1000) { 3274 if (cmd->base.duplex != DUPLEX_FULL) { 3275 if (netif_msg_link(adapter)) 3276 dev_warn(&adapter->pdev->dev, 3277 "1000M half is invalid\n"); 3278 ret_val = -EINVAL; 3279 goto exit_sset; 3280 } 3281 hw->media_type = MEDIA_TYPE_1000M_FULL; 3282 } else if (speed == SPEED_100) { 3283 if (cmd->base.duplex == DUPLEX_FULL) 3284 hw->media_type = MEDIA_TYPE_100M_FULL; 3285 else 3286 hw->media_type = MEDIA_TYPE_100M_HALF; 3287 } else { 3288 if (cmd->base.duplex == DUPLEX_FULL) 3289 hw->media_type = MEDIA_TYPE_10M_FULL; 3290 else 3291 hw->media_type = MEDIA_TYPE_10M_HALF; 3292 } 3293 } 3294 3295 if (atl1_phy_setup_autoneg_adv(hw)) { 3296 ret_val = -EINVAL; 3297 if (netif_msg_link(adapter)) 3298 dev_warn(&adapter->pdev->dev, 3299 "invalid ethtool speed/duplex setting\n"); 3300 goto exit_sset; 3301 } 3302 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3303 hw->media_type == MEDIA_TYPE_1000M_FULL) 3304 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 3305 else { 3306 switch (hw->media_type) { 3307 case MEDIA_TYPE_100M_FULL: 3308 phy_data = 3309 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | 3310 MII_CR_RESET; 3311 break; 3312 case MEDIA_TYPE_100M_HALF: 3313 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 3314 break; 3315 case MEDIA_TYPE_10M_FULL: 3316 phy_data = 3317 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; 3318 break; 3319 default: 3320 /* MEDIA_TYPE_10M_HALF: */ 3321 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 3322 break; 3323 } 3324 } 3325 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 3326 exit_sset: 3327 if (ret_val) 3328 hw->media_type = old_media_type; 3329 3330 if (netif_running(adapter->netdev)) { 3331 if (netif_msg_link(adapter)) 3332 dev_dbg(&adapter->pdev->dev, 3333 "ethtool starting adapter\n"); 3334 atl1_up(adapter); 3335 } else if (!ret_val) { 3336 if (netif_msg_link(adapter)) 3337 dev_dbg(&adapter->pdev->dev, 3338 "ethtool resetting adapter\n"); 3339 atl1_reset(adapter); 3340 } 3341 return ret_val; 3342 } 3343 3344 static void atl1_get_drvinfo(struct net_device *netdev, 3345 struct ethtool_drvinfo *drvinfo) 3346 { 3347 struct atl1_adapter *adapter = netdev_priv(netdev); 3348 3349 strlcpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver)); 3350 strlcpy(drvinfo->version, ATLX_DRIVER_VERSION, 3351 sizeof(drvinfo->version)); 3352 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 3353 sizeof(drvinfo->bus_info)); 3354 } 3355 3356 static void atl1_get_wol(struct net_device *netdev, 3357 struct ethtool_wolinfo *wol) 3358 { 3359 struct atl1_adapter *adapter = netdev_priv(netdev); 3360 3361 wol->supported = WAKE_MAGIC; 3362 wol->wolopts = 0; 3363 if (adapter->wol & ATLX_WUFC_MAG) 3364 wol->wolopts |= WAKE_MAGIC; 3365 } 3366 3367 static int atl1_set_wol(struct net_device *netdev, 3368 struct ethtool_wolinfo *wol) 3369 { 3370 struct atl1_adapter *adapter = netdev_priv(netdev); 3371 3372 if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | 3373 WAKE_ARP | WAKE_MAGICSECURE)) 3374 return -EOPNOTSUPP; 3375 adapter->wol = 0; 3376 if (wol->wolopts & WAKE_MAGIC) 3377 adapter->wol |= ATLX_WUFC_MAG; 3378 3379 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 3380 3381 return 0; 3382 } 3383 3384 static u32 atl1_get_msglevel(struct net_device *netdev) 3385 { 3386 struct atl1_adapter *adapter = netdev_priv(netdev); 3387 return adapter->msg_enable; 3388 } 3389 3390 static void atl1_set_msglevel(struct net_device *netdev, u32 value) 3391 { 3392 struct atl1_adapter *adapter = netdev_priv(netdev); 3393 adapter->msg_enable = value; 3394 } 3395 3396 static int atl1_get_regs_len(struct net_device *netdev) 3397 { 3398 return ATL1_REG_COUNT * sizeof(u32); 3399 } 3400 3401 static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs, 3402 void *p) 3403 { 3404 struct atl1_adapter *adapter = netdev_priv(netdev); 3405 struct atl1_hw *hw = &adapter->hw; 3406 unsigned int i; 3407 u32 *regbuf = p; 3408 3409 for (i = 0; i < ATL1_REG_COUNT; i++) { 3410 /* 3411 * This switch statement avoids reserved regions 3412 * of register space. 3413 */ 3414 switch (i) { 3415 case 6 ... 9: 3416 case 14: 3417 case 29 ... 31: 3418 case 34 ... 63: 3419 case 75 ... 127: 3420 case 136 ... 1023: 3421 case 1027 ... 1087: 3422 case 1091 ... 1151: 3423 case 1194 ... 1195: 3424 case 1200 ... 1201: 3425 case 1206 ... 1213: 3426 case 1216 ... 1279: 3427 case 1290 ... 1311: 3428 case 1323 ... 1343: 3429 case 1358 ... 1359: 3430 case 1368 ... 1375: 3431 case 1378 ... 1383: 3432 case 1388 ... 1391: 3433 case 1393 ... 1395: 3434 case 1402 ... 1403: 3435 case 1410 ... 1471: 3436 case 1522 ... 1535: 3437 /* reserved region; don't read it */ 3438 regbuf[i] = 0; 3439 break; 3440 default: 3441 /* unreserved region */ 3442 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32))); 3443 } 3444 } 3445 } 3446 3447 static void atl1_get_ringparam(struct net_device *netdev, 3448 struct ethtool_ringparam *ring) 3449 { 3450 struct atl1_adapter *adapter = netdev_priv(netdev); 3451 struct atl1_tpd_ring *txdr = &adapter->tpd_ring; 3452 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring; 3453 3454 ring->rx_max_pending = ATL1_MAX_RFD; 3455 ring->tx_max_pending = ATL1_MAX_TPD; 3456 ring->rx_pending = rxdr->count; 3457 ring->tx_pending = txdr->count; 3458 } 3459 3460 static int atl1_set_ringparam(struct net_device *netdev, 3461 struct ethtool_ringparam *ring) 3462 { 3463 struct atl1_adapter *adapter = netdev_priv(netdev); 3464 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring; 3465 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring; 3466 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring; 3467 3468 struct atl1_tpd_ring tpd_old, tpd_new; 3469 struct atl1_rfd_ring rfd_old, rfd_new; 3470 struct atl1_rrd_ring rrd_old, rrd_new; 3471 struct atl1_ring_header rhdr_old, rhdr_new; 3472 struct atl1_smb smb; 3473 struct atl1_cmb cmb; 3474 int err; 3475 3476 tpd_old = adapter->tpd_ring; 3477 rfd_old = adapter->rfd_ring; 3478 rrd_old = adapter->rrd_ring; 3479 rhdr_old = adapter->ring_header; 3480 3481 if (netif_running(adapter->netdev)) 3482 atl1_down(adapter); 3483 3484 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD); 3485 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD : 3486 rfdr->count; 3487 rfdr->count = (rfdr->count + 3) & ~3; 3488 rrdr->count = rfdr->count; 3489 3490 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD); 3491 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD : 3492 tpdr->count; 3493 tpdr->count = (tpdr->count + 3) & ~3; 3494 3495 if (netif_running(adapter->netdev)) { 3496 /* try to get new resources before deleting old */ 3497 err = atl1_setup_ring_resources(adapter); 3498 if (err) 3499 goto err_setup_ring; 3500 3501 /* 3502 * save the new, restore the old in order to free it, 3503 * then restore the new back again 3504 */ 3505 3506 rfd_new = adapter->rfd_ring; 3507 rrd_new = adapter->rrd_ring; 3508 tpd_new = adapter->tpd_ring; 3509 rhdr_new = adapter->ring_header; 3510 adapter->rfd_ring = rfd_old; 3511 adapter->rrd_ring = rrd_old; 3512 adapter->tpd_ring = tpd_old; 3513 adapter->ring_header = rhdr_old; 3514 /* 3515 * Save SMB and CMB, since atl1_free_ring_resources 3516 * will clear them. 3517 */ 3518 smb = adapter->smb; 3519 cmb = adapter->cmb; 3520 atl1_free_ring_resources(adapter); 3521 adapter->rfd_ring = rfd_new; 3522 adapter->rrd_ring = rrd_new; 3523 adapter->tpd_ring = tpd_new; 3524 adapter->ring_header = rhdr_new; 3525 adapter->smb = smb; 3526 adapter->cmb = cmb; 3527 3528 err = atl1_up(adapter); 3529 if (err) 3530 return err; 3531 } 3532 return 0; 3533 3534 err_setup_ring: 3535 adapter->rfd_ring = rfd_old; 3536 adapter->rrd_ring = rrd_old; 3537 adapter->tpd_ring = tpd_old; 3538 adapter->ring_header = rhdr_old; 3539 atl1_up(adapter); 3540 return err; 3541 } 3542 3543 static void atl1_get_pauseparam(struct net_device *netdev, 3544 struct ethtool_pauseparam *epause) 3545 { 3546 struct atl1_adapter *adapter = netdev_priv(netdev); 3547 struct atl1_hw *hw = &adapter->hw; 3548 3549 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3550 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3551 epause->autoneg = AUTONEG_ENABLE; 3552 } else { 3553 epause->autoneg = AUTONEG_DISABLE; 3554 } 3555 epause->rx_pause = 1; 3556 epause->tx_pause = 1; 3557 } 3558 3559 static int atl1_set_pauseparam(struct net_device *netdev, 3560 struct ethtool_pauseparam *epause) 3561 { 3562 struct atl1_adapter *adapter = netdev_priv(netdev); 3563 struct atl1_hw *hw = &adapter->hw; 3564 3565 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3566 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3567 epause->autoneg = AUTONEG_ENABLE; 3568 } else { 3569 epause->autoneg = AUTONEG_DISABLE; 3570 } 3571 3572 epause->rx_pause = 1; 3573 epause->tx_pause = 1; 3574 3575 return 0; 3576 } 3577 3578 static void atl1_get_strings(struct net_device *netdev, u32 stringset, 3579 u8 *data) 3580 { 3581 u8 *p = data; 3582 int i; 3583 3584 switch (stringset) { 3585 case ETH_SS_STATS: 3586 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) { 3587 memcpy(p, atl1_gstrings_stats[i].stat_string, 3588 ETH_GSTRING_LEN); 3589 p += ETH_GSTRING_LEN; 3590 } 3591 break; 3592 } 3593 } 3594 3595 static int atl1_nway_reset(struct net_device *netdev) 3596 { 3597 struct atl1_adapter *adapter = netdev_priv(netdev); 3598 struct atl1_hw *hw = &adapter->hw; 3599 3600 if (netif_running(netdev)) { 3601 u16 phy_data; 3602 atl1_down(adapter); 3603 3604 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || 3605 hw->media_type == MEDIA_TYPE_1000M_FULL) { 3606 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 3607 } else { 3608 switch (hw->media_type) { 3609 case MEDIA_TYPE_100M_FULL: 3610 phy_data = MII_CR_FULL_DUPLEX | 3611 MII_CR_SPEED_100 | MII_CR_RESET; 3612 break; 3613 case MEDIA_TYPE_100M_HALF: 3614 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 3615 break; 3616 case MEDIA_TYPE_10M_FULL: 3617 phy_data = MII_CR_FULL_DUPLEX | 3618 MII_CR_SPEED_10 | MII_CR_RESET; 3619 break; 3620 default: 3621 /* MEDIA_TYPE_10M_HALF */ 3622 phy_data = MII_CR_SPEED_10 | MII_CR_RESET; 3623 } 3624 } 3625 atl1_write_phy_reg(hw, MII_BMCR, phy_data); 3626 atl1_up(adapter); 3627 } 3628 return 0; 3629 } 3630 3631 static const struct ethtool_ops atl1_ethtool_ops = { 3632 .get_drvinfo = atl1_get_drvinfo, 3633 .get_wol = atl1_get_wol, 3634 .set_wol = atl1_set_wol, 3635 .get_msglevel = atl1_get_msglevel, 3636 .set_msglevel = atl1_set_msglevel, 3637 .get_regs_len = atl1_get_regs_len, 3638 .get_regs = atl1_get_regs, 3639 .get_ringparam = atl1_get_ringparam, 3640 .set_ringparam = atl1_set_ringparam, 3641 .get_pauseparam = atl1_get_pauseparam, 3642 .set_pauseparam = atl1_set_pauseparam, 3643 .get_link = ethtool_op_get_link, 3644 .get_strings = atl1_get_strings, 3645 .nway_reset = atl1_nway_reset, 3646 .get_ethtool_stats = atl1_get_ethtool_stats, 3647 .get_sset_count = atl1_get_sset_count, 3648 .get_link_ksettings = atl1_get_link_ksettings, 3649 .set_link_ksettings = atl1_set_link_ksettings, 3650 }; 3651 3652 module_pci_driver(atl1_driver); 3653