1 /*
2  * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3  * Copyright(c) 2007 xiong huang <xiong.huang@atheros.com>
4  *
5  * Derived from Intel e1000 driver
6  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of the GNU General Public License as published by the Free
10  * Software Foundation; either version 2 of the License, or (at your option)
11  * any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along with
19  * this program; if not, write to the Free Software Foundation, Inc., 59
20  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
21  */
22 
23 #ifndef _ATL1E_H_
24 #define _ATL1E_H_
25 
26 #include <linux/interrupt.h>
27 #include <linux/types.h>
28 #include <linux/errno.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ioport.h>
35 #include <linux/slab.h>
36 #include <linux/list.h>
37 #include <linux/delay.h>
38 #include <linux/sched.h>
39 #include <linux/in.h>
40 #include <linux/ip.h>
41 #include <linux/ipv6.h>
42 #include <linux/udp.h>
43 #include <linux/mii.h>
44 #include <linux/io.h>
45 #include <linux/vmalloc.h>
46 #include <linux/pagemap.h>
47 #include <linux/tcp.h>
48 #include <linux/ethtool.h>
49 #include <linux/if_vlan.h>
50 #include <linux/workqueue.h>
51 #include <net/checksum.h>
52 #include <net/ip6_checksum.h>
53 
54 #include "atl1e_hw.h"
55 
56 #define PCI_REG_COMMAND	 0x04    /* PCI Command Register */
57 #define CMD_IO_SPACE	 0x0001
58 #define CMD_MEMORY_SPACE 0x0002
59 #define CMD_BUS_MASTER   0x0004
60 
61 #define BAR_0   0
62 #define BAR_1   1
63 #define BAR_5   5
64 
65 /* Wake Up Filter Control */
66 #define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
67 #define AT_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
68 #define AT_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
69 #define AT_WUFC_MC   0x00000008 /* Multicast Wakeup Enable */
70 #define AT_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
71 
72 #define SPEED_0		   0xffff
73 #define HALF_DUPLEX        1
74 #define FULL_DUPLEX        2
75 
76 /* Error Codes */
77 #define AT_ERR_EEPROM      1
78 #define AT_ERR_PHY         2
79 #define AT_ERR_CONFIG      3
80 #define AT_ERR_PARAM       4
81 #define AT_ERR_MAC_TYPE    5
82 #define AT_ERR_PHY_TYPE    6
83 #define AT_ERR_PHY_SPEED   7
84 #define AT_ERR_PHY_RES     8
85 #define AT_ERR_TIMEOUT     9
86 
87 #define MAX_JUMBO_FRAME_SIZE 0x2000
88 
89 #define AT_VLAN_TAG_TO_TPD_TAG(_vlan, _tpd)    \
90 	_tpd = (((_vlan) << (4)) | (((_vlan) >> 13) & 7) |\
91 		 (((_vlan) >> 9) & 8))
92 
93 #define AT_TPD_TAG_TO_VLAN_TAG(_tpd, _vlan)    \
94 	_vlan = (((_tpd) >> 8) | (((_tpd) & 0x77) << 9) |\
95 		   (((_tdp) & 0x88) << 5))
96 
97 #define AT_MAX_RECEIVE_QUEUE    4
98 #define AT_PAGE_NUM_PER_QUEUE   2
99 
100 #define AT_DMA_HI_ADDR_MASK     0xffffffff00000000ULL
101 #define AT_DMA_LO_ADDR_MASK     0x00000000ffffffffULL
102 
103 #define AT_TX_WATCHDOG  (5 * HZ)
104 #define AT_MAX_INT_WORK		10
105 #define AT_TWSI_EEPROM_TIMEOUT 	100
106 #define AT_HW_MAX_IDLE_DELAY 	10
107 #define AT_SUSPEND_LINK_TIMEOUT 28
108 
109 #define AT_REGS_LEN	75
110 #define AT_EEPROM_LEN 	512
111 #define AT_ADV_MASK	(ADVERTISE_10_HALF  |\
112 			 ADVERTISE_10_FULL  |\
113 			 ADVERTISE_100_HALF |\
114 			 ADVERTISE_100_FULL |\
115 			 ADVERTISE_1000_FULL)
116 
117 /* tpd word 2 */
118 #define TPD_BUFLEN_MASK 	0x3FFF
119 #define TPD_BUFLEN_SHIFT        0
120 #define TPD_DMAINT_MASK		0x0001
121 #define TPD_DMAINT_SHIFT        14
122 #define TPD_PKTNT_MASK          0x0001
123 #define TPD_PKTINT_SHIFT        15
124 #define TPD_VLANTAG_MASK        0xFFFF
125 #define TPD_VLAN_SHIFT          16
126 
127 /* tpd word 3 bits 0:4 */
128 #define TPD_EOP_MASK            0x0001
129 #define TPD_EOP_SHIFT           0
130 #define TPD_IP_VERSION_MASK	0x0001
131 #define TPD_IP_VERSION_SHIFT	1	/* 0 : IPV4, 1 : IPV6 */
132 #define TPD_INS_VL_TAG_MASK	0x0001
133 #define TPD_INS_VL_TAG_SHIFT	2
134 #define TPD_CC_SEGMENT_EN_MASK	0x0001
135 #define TPD_CC_SEGMENT_EN_SHIFT	3
136 #define TPD_SEGMENT_EN_MASK     0x0001
137 #define TPD_SEGMENT_EN_SHIFT    4
138 
139 /* tdp word 3 bits 5:7 if ip version is 0 */
140 #define TPD_IP_CSUM_MASK        0x0001
141 #define TPD_IP_CSUM_SHIFT       5
142 #define TPD_TCP_CSUM_MASK       0x0001
143 #define TPD_TCP_CSUM_SHIFT      6
144 #define TPD_UDP_CSUM_MASK       0x0001
145 #define TPD_UDP_CSUM_SHIFT      7
146 
147 /* tdp word 3 bits 5:7 if ip version is 1 */
148 #define TPD_V6_IPHLLO_MASK	0x0007
149 #define TPD_V6_IPHLLO_SHIFT	7
150 
151 /* tpd word 3 bits 8:9 bit */
152 #define TPD_VL_TAGGED_MASK      0x0001
153 #define TPD_VL_TAGGED_SHIFT     8
154 #define TPD_ETHTYPE_MASK        0x0001
155 #define TPD_ETHTYPE_SHIFT       9
156 
157 /* tdp word 3 bits 10:13 if ip version is 0 */
158 #define TDP_V4_IPHL_MASK	0x000F
159 #define TPD_V4_IPHL_SHIFT	10
160 
161 /* tdp word 3 bits 10:13 if ip version is 1 */
162 #define TPD_V6_IPHLHI_MASK	0x000F
163 #define TPD_V6_IPHLHI_SHIFT	10
164 
165 /* tpd word 3 bit 14:31 if segment enabled */
166 #define TPD_TCPHDRLEN_MASK      0x000F
167 #define TPD_TCPHDRLEN_SHIFT     14
168 #define TPD_HDRFLAG_MASK        0x0001
169 #define TPD_HDRFLAG_SHIFT       18
170 #define TPD_MSS_MASK            0x1FFF
171 #define TPD_MSS_SHIFT           19
172 
173 /* tdp word 3 bit 16:31 if custom csum enabled */
174 #define TPD_PLOADOFFSET_MASK    0x00FF
175 #define TPD_PLOADOFFSET_SHIFT   16
176 #define TPD_CCSUMOFFSET_MASK    0x00FF
177 #define TPD_CCSUMOFFSET_SHIFT   24
178 
179 struct atl1e_tpd_desc {
180 	__le64 buffer_addr;
181 	__le32 word2;
182 	__le32 word3;
183 };
184 
185 /* how about 0x2000 */
186 #define MAX_TX_BUF_LEN      0x2000
187 #define MAX_TX_BUF_SHIFT    13
188 #define MAX_TSO_SEG_SIZE    0x3c00
189 
190 /* rrs word 1 bit 0:31 */
191 #define RRS_RX_CSUM_MASK	0xFFFF
192 #define RRS_RX_CSUM_SHIFT	0
193 #define RRS_PKT_SIZE_MASK	0x3FFF
194 #define RRS_PKT_SIZE_SHIFT	16
195 #define RRS_CPU_NUM_MASK	0x0003
196 #define	RRS_CPU_NUM_SHIFT	30
197 
198 #define	RRS_IS_RSS_IPV4		0x0001
199 #define RRS_IS_RSS_IPV4_TCP	0x0002
200 #define RRS_IS_RSS_IPV6		0x0004
201 #define RRS_IS_RSS_IPV6_TCP	0x0008
202 #define RRS_IS_IPV6		0x0010
203 #define RRS_IS_IP_FRAG		0x0020
204 #define RRS_IS_IP_DF		0x0040
205 #define RRS_IS_802_3		0x0080
206 #define RRS_IS_VLAN_TAG		0x0100
207 #define RRS_IS_ERR_FRAME	0x0200
208 #define RRS_IS_IPV4		0x0400
209 #define RRS_IS_UDP		0x0800
210 #define RRS_IS_TCP		0x1000
211 #define RRS_IS_BCAST		0x2000
212 #define RRS_IS_MCAST		0x4000
213 #define RRS_IS_PAUSE		0x8000
214 
215 #define RRS_ERR_BAD_CRC		0x0001
216 #define RRS_ERR_CODE		0x0002
217 #define RRS_ERR_DRIBBLE		0x0004
218 #define RRS_ERR_RUNT		0x0008
219 #define RRS_ERR_RX_OVERFLOW	0x0010
220 #define RRS_ERR_TRUNC		0x0020
221 #define RRS_ERR_IP_CSUM		0x0040
222 #define RRS_ERR_L4_CSUM		0x0080
223 #define RRS_ERR_LENGTH		0x0100
224 #define RRS_ERR_DES_ADDR	0x0200
225 
226 struct atl1e_recv_ret_status {
227 	u16 seq_num;
228 	u16 hash_lo;
229 	__le32	word1;
230 	u16 pkt_flag;
231 	u16 err_flag;
232 	u16 hash_hi;
233 	u16 vtag;
234 };
235 
236 enum atl1e_dma_req_block {
237 	atl1e_dma_req_128 = 0,
238 	atl1e_dma_req_256 = 1,
239 	atl1e_dma_req_512 = 2,
240 	atl1e_dma_req_1024 = 3,
241 	atl1e_dma_req_2048 = 4,
242 	atl1e_dma_req_4096 = 5
243 };
244 
245 enum atl1e_rrs_type {
246 	atl1e_rrs_disable = 0,
247 	atl1e_rrs_ipv4 = 1,
248 	atl1e_rrs_ipv4_tcp = 2,
249 	atl1e_rrs_ipv6 = 4,
250 	atl1e_rrs_ipv6_tcp = 8
251 };
252 
253 enum atl1e_nic_type {
254 	athr_l1e = 0,
255 	athr_l2e_revA = 1,
256 	athr_l2e_revB = 2
257 };
258 
259 struct atl1e_hw_stats {
260 	/* rx */
261 	unsigned long rx_ok;	      /* The number of good packet received. */
262 	unsigned long rx_bcast;       /* The number of good broadcast packet received. */
263 	unsigned long rx_mcast;       /* The number of good multicast packet received. */
264 	unsigned long rx_pause;       /* The number of Pause packet received. */
265 	unsigned long rx_ctrl;        /* The number of Control packet received other than Pause frame. */
266 	unsigned long rx_fcs_err;     /* The number of packets with bad FCS. */
267 	unsigned long rx_len_err;     /* The number of packets with mismatch of length field and actual size. */
268 	unsigned long rx_byte_cnt;    /* The number of bytes of good packet received. FCS is NOT included. */
269 	unsigned long rx_runt;        /* The number of packets received that are less than 64 byte long and with good FCS. */
270 	unsigned long rx_frag;        /* The number of packets received that are less than 64 byte long and with bad FCS. */
271 	unsigned long rx_sz_64;       /* The number of good and bad packets received that are 64 byte long. */
272 	unsigned long rx_sz_65_127;   /* The number of good and bad packets received that are between 65 and 127-byte long. */
273 	unsigned long rx_sz_128_255;  /* The number of good and bad packets received that are between 128 and 255-byte long. */
274 	unsigned long rx_sz_256_511;  /* The number of good and bad packets received that are between 256 and 511-byte long. */
275 	unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
276 	unsigned long rx_sz_1024_1518;    /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
277 	unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
278 	unsigned long rx_sz_ov;       /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
279 	unsigned long rx_rxf_ov;      /* The number of frame dropped due to occurrence of RX FIFO overflow. */
280 	unsigned long rx_rrd_ov;      /* The number of frame dropped due to occurrence of RRD overflow. */
281 	unsigned long rx_align_err;   /* Alignment Error */
282 	unsigned long rx_bcast_byte_cnt;  /* The byte count of broadcast packet received, excluding FCS. */
283 	unsigned long rx_mcast_byte_cnt;  /* The byte count of multicast packet received, excluding FCS. */
284 	unsigned long rx_err_addr;    /* The number of packets dropped due to address filtering. */
285 
286 	/* tx */
287 	unsigned long tx_ok;      /* The number of good packet transmitted. */
288 	unsigned long tx_bcast;       /* The number of good broadcast packet transmitted. */
289 	unsigned long tx_mcast;       /* The number of good multicast packet transmitted. */
290 	unsigned long tx_pause;       /* The number of Pause packet transmitted. */
291 	unsigned long tx_exc_defer;   /* The number of packets transmitted with excessive deferral. */
292 	unsigned long tx_ctrl;        /* The number of packets transmitted is a control frame, excluding Pause frame. */
293 	unsigned long tx_defer;       /* The number of packets transmitted that is deferred. */
294 	unsigned long tx_byte_cnt;    /* The number of bytes of data transmitted. FCS is NOT included. */
295 	unsigned long tx_sz_64;       /* The number of good and bad packets transmitted that are 64 byte long. */
296 	unsigned long tx_sz_65_127;   /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
297 	unsigned long tx_sz_128_255;  /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
298 	unsigned long tx_sz_256_511;  /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
299 	unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
300 	unsigned long tx_sz_1024_1518;    /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
301 	unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
302 	unsigned long tx_1_col;       /* The number of packets subsequently transmitted successfully with a single prior collision. */
303 	unsigned long tx_2_col;       /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
304 	unsigned long tx_late_col;    /* The number of packets transmitted with late collisions. */
305 	unsigned long tx_abort_col;   /* The number of transmit packets aborted due to excessive collisions. */
306 	unsigned long tx_underrun;    /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
307 	unsigned long tx_rd_eop;      /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
308 	unsigned long tx_len_err;     /* The number of transmit packets with length field does NOT match the actual frame size. */
309 	unsigned long tx_trunc;       /* The number of transmit packets truncated due to size exceeding MTU. */
310 	unsigned long tx_bcast_byte;  /* The byte count of broadcast packet transmitted, excluding FCS. */
311 	unsigned long tx_mcast_byte;  /* The byte count of multicast packet transmitted, excluding FCS. */
312 };
313 
314 struct atl1e_hw {
315 	u8 __iomem      *hw_addr;            /* inner register address */
316 	resource_size_t mem_rang;
317 	struct atl1e_adapter *adapter;
318 	enum atl1e_nic_type  nic_type;
319 	u16 device_id;
320 	u16 vendor_id;
321 	u16 subsystem_id;
322 	u16 subsystem_vendor_id;
323 	u8  revision_id;
324 	u16 pci_cmd_word;
325 	u8 mac_addr[ETH_ALEN];
326 	u8 perm_mac_addr[ETH_ALEN];
327 	u8 preamble_len;
328 	u16 max_frame_size;
329 	u16 rx_jumbo_th;
330 	u16 tx_jumbo_th;
331 
332 	u16 media_type;
333 #define MEDIA_TYPE_AUTO_SENSOR  0
334 #define MEDIA_TYPE_100M_FULL    1
335 #define MEDIA_TYPE_100M_HALF    2
336 #define MEDIA_TYPE_10M_FULL     3
337 #define MEDIA_TYPE_10M_HALF     4
338 
339 	u16 autoneg_advertised;
340 #define ADVERTISE_10_HALF               0x0001
341 #define ADVERTISE_10_FULL               0x0002
342 #define ADVERTISE_100_HALF              0x0004
343 #define ADVERTISE_100_FULL              0x0008
344 #define ADVERTISE_1000_HALF             0x0010 /* Not used, just FYI */
345 #define ADVERTISE_1000_FULL             0x0020
346 	u16 mii_autoneg_adv_reg;
347 	u16 mii_1000t_ctrl_reg;
348 
349 	u16 imt;        /* Interrupt Moderator timer ( 2us resolution) */
350 	u16 ict;        /* Interrupt Clear timer (2us resolution) */
351 	u32 smb_timer;
352 	u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
353 			  interrupt request */
354 	u16 tpd_thresh;
355 	u16 rx_count_down; /* 2us resolution */
356 	u16 tx_count_down;
357 
358 	u8 tpd_burst;   /* Number of TPD to prefetch in cache-aligned burst. */
359 	enum atl1e_rrs_type rrs_type;
360 	u32 base_cpu;
361 	u32 indirect_tab;
362 
363 	enum atl1e_dma_req_block dmar_block;
364 	enum atl1e_dma_req_block dmaw_block;
365 	u8 dmaw_dly_cnt;
366 	u8 dmar_dly_cnt;
367 
368 	bool phy_configured;
369 	bool re_autoneg;
370 	bool emi_ca;
371 };
372 
373 /*
374  * wrapper around a pointer to a socket buffer,
375  * so a DMA handle can be stored along with the buffer
376  */
377 struct atl1e_tx_buffer {
378 	struct sk_buff *skb;
379 	u16 flags;
380 #define ATL1E_TX_PCIMAP_SINGLE		0x0001
381 #define ATL1E_TX_PCIMAP_PAGE		0x0002
382 #define ATL1E_TX_PCIMAP_TYPE_MASK	0x0003
383 	u16 length;
384 	dma_addr_t dma;
385 };
386 
387 #define ATL1E_SET_PCIMAP_TYPE(tx_buff, type) do {		\
388 	((tx_buff)->flags) &= ~ATL1E_TX_PCIMAP_TYPE_MASK;	\
389 	((tx_buff)->flags) |= (type);				\
390 	} while (0)
391 
392 struct atl1e_rx_page {
393 	dma_addr_t	dma;    /* receive rage DMA address */
394 	u8		*addr;   /* receive rage virtual address */
395 	dma_addr_t	write_offset_dma;  /* the DMA address which contain the
396 					      receive data offset in the page */
397 	u32		*write_offset_addr; /* the virtaul address which contain
398 					     the receive data offset in the page */
399 	u32		read_offset;       /* the offset where we have read */
400 };
401 
402 struct atl1e_rx_page_desc {
403 	struct atl1e_rx_page   rx_page[AT_PAGE_NUM_PER_QUEUE];
404 	u8  rx_using;
405 	u16 rx_nxseq;
406 };
407 
408 /* transmit packet descriptor (tpd) ring */
409 struct atl1e_tx_ring {
410 	struct atl1e_tpd_desc *desc;  /* descriptor ring virtual address  */
411 	dma_addr_t	   dma;    /* descriptor ring physical address */
412 	u16       	   count;  /* the count of transmit rings  */
413 	rwlock_t	   tx_lock;
414 	u16		   next_to_use;
415 	atomic_t	   next_to_clean;
416 	struct atl1e_tx_buffer *tx_buffer;
417 	dma_addr_t	   cmb_dma;
418 	u32		   *cmb;
419 };
420 
421 /* receive packet descriptor ring */
422 struct atl1e_rx_ring {
423 	void        	*desc;
424 	dma_addr_t  	dma;
425 	int         	size;
426 	u32	    	page_size; /* bytes length of rxf page */
427 	u32		real_page_size; /* real_page_size = page_size + jumbo + aliagn */
428 	struct atl1e_rx_page_desc	rx_page_desc[AT_MAX_RECEIVE_QUEUE];
429 };
430 
431 /* board specific private data structure */
432 struct atl1e_adapter {
433 	struct net_device   *netdev;
434 	struct pci_dev      *pdev;
435 	struct napi_struct  napi;
436 	struct mii_if_info  mii;    /* MII interface info */
437 	struct atl1e_hw        hw;
438 	struct atl1e_hw_stats  hw_stats;
439 
440 	u32 wol;
441 	u16 link_speed;
442 	u16 link_duplex;
443 
444 	spinlock_t mdio_lock;
445 	atomic_t irq_sem;
446 
447 	struct work_struct reset_task;
448 	struct work_struct link_chg_task;
449 	struct timer_list watchdog_timer;
450 	struct timer_list phy_config_timer;
451 
452 	/* All Descriptor memory */
453 	dma_addr_t  	ring_dma;
454 	void     	*ring_vir_addr;
455 	u32             ring_size;
456 
457 	struct atl1e_tx_ring tx_ring;
458 	struct atl1e_rx_ring rx_ring;
459 	int num_rx_queues;
460 	unsigned long flags;
461 #define __AT_TESTING        0x0001
462 #define __AT_RESETTING      0x0002
463 #define __AT_DOWN           0x0003
464 
465 	u32 bd_number;     /* board number;*/
466 	u32 pci_state[16];
467 	u32 *config_space;
468 };
469 
470 #define AT_WRITE_REG(a, reg, value) ( \
471 		writel((value), ((a)->hw_addr + reg)))
472 
473 #define AT_WRITE_FLUSH(a) (\
474 		readl((a)->hw_addr))
475 
476 #define AT_READ_REG(a, reg) ( \
477 		readl((a)->hw_addr + reg))
478 
479 #define AT_WRITE_REGB(a, reg, value) (\
480 		writeb((value), ((a)->hw_addr + reg)))
481 
482 #define AT_READ_REGB(a, reg) (\
483 		readb((a)->hw_addr + reg))
484 
485 #define AT_WRITE_REGW(a, reg, value) (\
486 		writew((value), ((a)->hw_addr + reg)))
487 
488 #define AT_READ_REGW(a, reg) (\
489 		readw((a)->hw_addr + reg))
490 
491 #define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
492 		writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
493 
494 #define AT_READ_REG_ARRAY(a, reg, offset) ( \
495 		readl(((a)->hw_addr + reg) + ((offset) << 2)))
496 
497 extern char atl1e_driver_name[];
498 extern char atl1e_driver_version[];
499 
500 void atl1e_check_options(struct atl1e_adapter *adapter);
501 int atl1e_up(struct atl1e_adapter *adapter);
502 void atl1e_down(struct atl1e_adapter *adapter);
503 void atl1e_reinit_locked(struct atl1e_adapter *adapter);
504 s32 atl1e_reset_hw(struct atl1e_hw *hw);
505 void atl1e_set_ethtool_ops(struct net_device *netdev);
506 #endif /* _ATL1_E_H_ */
507