1 /* 2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. 3 * 4 * Derived from Intel e1000 driver 5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the Free 9 * Software Foundation; either version 2 of the License, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 59 19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 22 #ifndef _ATL1C_HW_H_ 23 #define _ATL1C_HW_H_ 24 25 #include <linux/types.h> 26 #include <linux/mii.h> 27 28 #define FIELD_GETX(_x, _name) ((_x) >> (_name##_SHIFT) & (_name##_MASK)) 29 #define FIELD_SETX(_x, _name, _v) \ 30 (((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\ 31 (((_v) & (_name##_MASK)) << (_name##_SHIFT))) 32 #define FIELDX(_name, _v) (((_v) & (_name##_MASK)) << (_name##_SHIFT)) 33 34 struct atl1c_adapter; 35 struct atl1c_hw; 36 37 /* function prototype */ 38 void atl1c_phy_disable(struct atl1c_hw *hw); 39 void atl1c_hw_set_mac_addr(struct atl1c_hw *hw, u8 *mac_addr); 40 int atl1c_phy_reset(struct atl1c_hw *hw); 41 int atl1c_read_mac_addr(struct atl1c_hw *hw); 42 int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex); 43 u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr); 44 void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value); 45 int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data); 46 int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data); 47 bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value); 48 int atl1c_phy_init(struct atl1c_hw *hw); 49 int atl1c_check_eeprom_exist(struct atl1c_hw *hw); 50 int atl1c_restart_autoneg(struct atl1c_hw *hw); 51 int atl1c_phy_to_ps_link(struct atl1c_hw *hw); 52 int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc); 53 bool atl1c_wait_mdio_idle(struct atl1c_hw *hw); 54 void atl1c_stop_phy_polling(struct atl1c_hw *hw); 55 void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel); 56 int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, 57 u16 reg, u16 *phy_data); 58 int atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, 59 u16 reg, u16 phy_data); 60 int atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr, 61 u16 reg_addr, u16 *phy_data); 62 int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr, 63 u16 reg_addr, u16 phy_data); 64 int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data); 65 int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data); 66 void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed); 67 68 /* hw-ids */ 69 #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062 70 #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063 71 #define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */ 72 #define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */ 73 #define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */ 74 #define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */ 75 #define L2CB_V10 0xc0 76 #define L2CB_V11 0xc1 77 #define L2CB_V20 0xc0 78 #define L2CB_V21 0xc1 79 80 /* register definition */ 81 #define REG_DEVICE_CAP 0x5C 82 #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7 83 #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0 84 85 #define DEVICE_CTRL_MAXRRS_MIN 2 86 87 #define REG_LINK_CTRL 0x68 88 #define LINK_CTRL_L0S_EN 0x01 89 #define LINK_CTRL_L1_EN 0x02 90 #define LINK_CTRL_EXT_SYNC 0x80 91 92 #define REG_PCIE_IND_ACC_ADDR 0x80 93 #define REG_PCIE_IND_ACC_DATA 0x84 94 95 #define REG_DEV_SERIALNUM_CTRL 0x200 96 #define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */ 97 #define REG_DEV_MAC_SEL_SHIFT 0 98 #define REG_DEV_SERIAL_NUM_EN_MASK 0x1 99 #define REG_DEV_SERIAL_NUM_EN_SHIFT 1 100 101 #define REG_TWSI_CTRL 0x218 102 #define TWSI_CTLR_FREQ_MASK 0x3UL 103 #define TWSI_CTRL_FREQ_SHIFT 24 104 #define TWSI_CTRL_FREQ_100K 0 105 #define TWSI_CTRL_FREQ_200K 1 106 #define TWSI_CTRL_FREQ_300K 2 107 #define TWSI_CTRL_FREQ_400K 3 108 #define TWSI_CTRL_LD_EXIST BIT(23) 109 #define TWSI_CTRL_HW_LDSTAT BIT(12) /* 0:finish,1:in progress */ 110 #define TWSI_CTRL_SW_LDSTART BIT(11) 111 #define TWSI_CTRL_LD_OFFSET_MASK 0xFF 112 #define TWSI_CTRL_LD_OFFSET_SHIFT 0 113 114 #define REG_PCIE_DEV_MISC_CTRL 0x21C 115 #define PCIE_DEV_MISC_EXT_PIPE 0x2 116 #define PCIE_DEV_MISC_RETRY_BUFDIS 0x1 117 #define PCIE_DEV_MISC_SPIROM_EXIST 0x4 118 #define PCIE_DEV_MISC_SERDES_ENDIAN 0x8 119 #define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10 120 121 #define REG_PCIE_PHYMISC 0x1000 122 #define PCIE_PHYMISC_FORCE_RCV_DET BIT(2) 123 #define PCIE_PHYMISC_NFTS_MASK 0xFFUL 124 #define PCIE_PHYMISC_NFTS_SHIFT 16 125 126 #define REG_PCIE_PHYMISC2 0x1004 127 #define PCIE_PHYMISC2_L0S_TH_MASK 0x3UL 128 #define PCIE_PHYMISC2_L0S_TH_SHIFT 18 129 #define L2CB1_PCIE_PHYMISC2_L0S_TH 3 130 #define PCIE_PHYMISC2_CDR_BW_MASK 0x3UL 131 #define PCIE_PHYMISC2_CDR_BW_SHIFT 16 132 #define L2CB1_PCIE_PHYMISC2_CDR_BW 3 133 134 #define REG_TWSI_DEBUG 0x1108 135 #define TWSI_DEBUG_DEV_EXIST BIT(29) 136 137 #define REG_DMA_DBG 0x1114 138 #define DMA_DBG_VENDOR_MSG BIT(0) 139 140 #define REG_EEPROM_CTRL 0x12C0 141 #define EEPROM_CTRL_DATA_HI_MASK 0xFFFF 142 #define EEPROM_CTRL_DATA_HI_SHIFT 0 143 #define EEPROM_CTRL_ADDR_MASK 0x3FF 144 #define EEPROM_CTRL_ADDR_SHIFT 16 145 #define EEPROM_CTRL_ACK 0x40000000 146 #define EEPROM_CTRL_RW 0x80000000 147 148 #define REG_EEPROM_DATA_LO 0x12C4 149 150 #define REG_OTP_CTRL 0x12F0 151 #define OTP_CTRL_CLK_EN BIT(1) 152 153 #define REG_PM_CTRL 0x12F8 154 #define PM_CTRL_HOTRST BIT(31) 155 #define PM_CTRL_MAC_ASPM_CHK BIT(30) /* L0s/L1 dis by MAC based on 156 * thrghput(setting in 15A0) */ 157 #define PM_CTRL_SA_DLY_EN BIT(29) 158 #define PM_CTRL_L0S_BUFSRX_EN BIT(28) 159 #define PM_CTRL_LCKDET_TIMER_MASK 0xFUL 160 #define PM_CTRL_LCKDET_TIMER_SHIFT 24 161 #define PM_CTRL_LCKDET_TIMER_DEF 0xC 162 #define PM_CTRL_PM_REQ_TIMER_MASK 0xFUL 163 #define PM_CTRL_PM_REQ_TIMER_SHIFT 20 /* pm_request_l1 time > @ 164 * ->L0s not L1 */ 165 #define PM_CTRL_PM_REQ_TO_DEF 0xF 166 #define PMCTRL_TXL1_AFTER_L0S BIT(19) /* l1dv2.0+ */ 167 #define L1D_PMCTRL_L1_ENTRY_TM_MASK 7UL /* l1dv2.0+, 3bits */ 168 #define L1D_PMCTRL_L1_ENTRY_TM_SHIFT 16 169 #define L1D_PMCTRL_L1_ENTRY_TM_DIS 0 170 #define L1D_PMCTRL_L1_ENTRY_TM_2US 1 171 #define L1D_PMCTRL_L1_ENTRY_TM_4US 2 172 #define L1D_PMCTRL_L1_ENTRY_TM_8US 3 173 #define L1D_PMCTRL_L1_ENTRY_TM_16US 4 174 #define L1D_PMCTRL_L1_ENTRY_TM_24US 5 175 #define L1D_PMCTRL_L1_ENTRY_TM_32US 6 176 #define L1D_PMCTRL_L1_ENTRY_TM_63US 7 177 #define PM_CTRL_L1_ENTRY_TIMER_MASK 0xFUL /* l1C 4bits */ 178 #define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16 179 #define L2CB1_PM_CTRL_L1_ENTRY_TM 7 180 #define L1C_PM_CTRL_L1_ENTRY_TM 0xF 181 #define PM_CTRL_RCVR_WT_TIMER BIT(15) /* 1:1us, 0:2ms */ 182 #define PM_CTRL_CLK_PWM_VER1_1 BIT(14) /* 0:1.0a,1:1.1 */ 183 #define PM_CTRL_CLK_SWH_L1 BIT(13) /* en pcie clk sw in L1 */ 184 #define PM_CTRL_ASPM_L0S_EN BIT(12) 185 #define PM_CTRL_RXL1_AFTER_L0S BIT(11) /* l1dv2.0+ */ 186 #define L1D_PMCTRL_L0S_TIMER_MASK 7UL /* l1d2.0+, 3bits*/ 187 #define L1D_PMCTRL_L0S_TIMER_SHIFT 8 188 #define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xFUL /* l1c, 4bits */ 189 #define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8 190 #define PM_CTRL_SERDES_BUFS_RX_L1_EN BIT(7) 191 #define PM_CTRL_SERDES_PD_EX_L1 BIT(6) /* power down serdes rx */ 192 #define PM_CTRL_SERDES_PLL_L1_EN BIT(5) 193 #define PM_CTRL_SERDES_L1_EN BIT(4) 194 #define PM_CTRL_ASPM_L1_EN BIT(3) 195 #define PM_CTRL_CLK_REQ_EN BIT(2) 196 #define PM_CTRL_RBER_EN BIT(1) 197 #define PM_CTRL_SPRSDWER_EN BIT(0) 198 199 #define REG_LTSSM_ID_CTRL 0x12FC 200 #define LTSSM_ID_EN_WRO 0x1000 201 202 203 /* Selene Master Control Register */ 204 #define REG_MASTER_CTRL 0x1400 205 #define MASTER_CTRL_OTP_SEL BIT(31) 206 #define MASTER_DEV_NUM_MASK 0x7FUL 207 #define MASTER_DEV_NUM_SHIFT 24 208 #define MASTER_REV_NUM_MASK 0xFFUL 209 #define MASTER_REV_NUM_SHIFT 16 210 #define MASTER_CTRL_INT_RDCLR BIT(14) 211 #define MASTER_CTRL_CLK_SEL_DIS BIT(12) /* 1:alwys sel pclk from 212 * serdes, not sw to 25M */ 213 #define MASTER_CTRL_RX_ITIMER_EN BIT(11) /* IRQ MODURATION FOR RX */ 214 #define MASTER_CTRL_TX_ITIMER_EN BIT(10) /* MODURATION FOR TX/RX */ 215 #define MASTER_CTRL_MANU_INT BIT(9) /* SOFT MANUAL INT */ 216 #define MASTER_CTRL_MANUTIMER_EN BIT(8) 217 #define MASTER_CTRL_SA_TIMER_EN BIT(7) /* SYS ALIVE TIMER EN */ 218 #define MASTER_CTRL_OOB_DIS BIT(6) /* OUT OF BOX DIS */ 219 #define MASTER_CTRL_WAKEN_25M BIT(5) /* WAKE WO. PCIE CLK */ 220 #define MASTER_CTRL_BERT_START BIT(4) 221 #define MASTER_PCIE_TSTMOD_MASK 3UL 222 #define MASTER_PCIE_TSTMOD_SHIFT 2 223 #define MASTER_PCIE_RST BIT(1) 224 #define MASTER_CTRL_SOFT_RST BIT(0) /* RST MAC & DMA */ 225 #define DMA_MAC_RST_TO 50 226 227 /* Timer Initial Value Register */ 228 #define REG_MANUAL_TIMER_INIT 0x1404 229 230 /* IRQ ModeratorTimer Initial Value Register */ 231 #define REG_IRQ_MODRT_TIMER_INIT 0x1408 232 #define IRQ_MODRT_TIMER_MASK 0xffff 233 #define IRQ_MODRT_TX_TIMER_SHIFT 0 234 #define IRQ_MODRT_RX_TIMER_SHIFT 16 235 236 #define REG_GPHY_CTRL 0x140C 237 #define GPHY_CTRL_ADDR_MASK 0x1FUL 238 #define GPHY_CTRL_ADDR_SHIFT 19 239 #define GPHY_CTRL_BP_VLTGSW BIT(18) 240 #define GPHY_CTRL_100AB_EN BIT(17) 241 #define GPHY_CTRL_10AB_EN BIT(16) 242 #define GPHY_CTRL_PHY_PLL_BYPASS BIT(15) 243 #define GPHY_CTRL_PWDOWN_HW BIT(14) /* affect MAC&PHY, to low pw */ 244 #define GPHY_CTRL_PHY_PLL_ON BIT(13) /* 1:pll always on, 0:can sw */ 245 #define GPHY_CTRL_SEL_ANA_RST BIT(12) 246 #define GPHY_CTRL_HIB_PULSE BIT(11) 247 #define GPHY_CTRL_HIB_EN BIT(10) 248 #define GPHY_CTRL_GIGA_DIS BIT(9) 249 #define GPHY_CTRL_PHY_IDDQ_DIS BIT(8) /* pw on RST */ 250 #define GPHY_CTRL_PHY_IDDQ BIT(7) /* bit8 affect bit7 while rb */ 251 #define GPHY_CTRL_LPW_EXIT BIT(6) 252 #define GPHY_CTRL_GATE_25M_EN BIT(5) 253 #define GPHY_CTRL_REV_ANEG BIT(4) 254 #define GPHY_CTRL_ANEG_NOW BIT(3) 255 #define GPHY_CTRL_LED_MODE BIT(2) 256 #define GPHY_CTRL_RTL_MODE BIT(1) 257 #define GPHY_CTRL_EXT_RESET BIT(0) /* 1:out of DSP RST status */ 258 #define GPHY_CTRL_EXT_RST_TO 80 /* 800us atmost */ 259 #define GPHY_CTRL_CLS (\ 260 GPHY_CTRL_LED_MODE |\ 261 GPHY_CTRL_100AB_EN |\ 262 GPHY_CTRL_PHY_PLL_ON) 263 264 /* Block IDLE Status Register */ 265 #define REG_IDLE_STATUS 0x1410 266 #define IDLE_STATUS_SFORCE_MASK 0xFUL 267 #define IDLE_STATUS_SFORCE_SHIFT 14 268 #define IDLE_STATUS_CALIB_DONE BIT(13) 269 #define IDLE_STATUS_CALIB_RES_MASK 0x1FUL 270 #define IDLE_STATUS_CALIB_RES_SHIFT 8 271 #define IDLE_STATUS_CALIBERR_MASK 0xFUL 272 #define IDLE_STATUS_CALIBERR_SHIFT 4 273 #define IDLE_STATUS_TXQ_BUSY BIT(3) 274 #define IDLE_STATUS_RXQ_BUSY BIT(2) 275 #define IDLE_STATUS_TXMAC_BUSY BIT(1) 276 #define IDLE_STATUS_RXMAC_BUSY BIT(0) 277 #define IDLE_STATUS_MASK (\ 278 IDLE_STATUS_TXQ_BUSY |\ 279 IDLE_STATUS_RXQ_BUSY |\ 280 IDLE_STATUS_TXMAC_BUSY |\ 281 IDLE_STATUS_RXMAC_BUSY) 282 283 /* MDIO Control Register */ 284 #define REG_MDIO_CTRL 0x1414 285 #define MDIO_CTRL_MODE_EXT BIT(30) 286 #define MDIO_CTRL_POST_READ BIT(29) 287 #define MDIO_CTRL_AP_EN BIT(28) 288 #define MDIO_CTRL_BUSY BIT(27) 289 #define MDIO_CTRL_CLK_SEL_MASK 0x7UL 290 #define MDIO_CTRL_CLK_SEL_SHIFT 24 291 #define MDIO_CTRL_CLK_25_4 0 /* 25MHz divide 4 */ 292 #define MDIO_CTRL_CLK_25_6 2 293 #define MDIO_CTRL_CLK_25_8 3 294 #define MDIO_CTRL_CLK_25_10 4 295 #define MDIO_CTRL_CLK_25_32 5 296 #define MDIO_CTRL_CLK_25_64 6 297 #define MDIO_CTRL_CLK_25_128 7 298 #define MDIO_CTRL_START BIT(23) 299 #define MDIO_CTRL_SPRES_PRMBL BIT(22) 300 #define MDIO_CTRL_OP_READ BIT(21) /* 1:read, 0:write */ 301 #define MDIO_CTRL_REG_MASK 0x1FUL 302 #define MDIO_CTRL_REG_SHIFT 16 303 #define MDIO_CTRL_DATA_MASK 0xFFFFUL 304 #define MDIO_CTRL_DATA_SHIFT 0 305 #define MDIO_MAX_AC_TO 120 /* 1.2ms timeout for slow clk */ 306 307 /* for extension reg access */ 308 #define REG_MDIO_EXTN 0x1448 309 #define MDIO_EXTN_PORTAD_MASK 0x1FUL 310 #define MDIO_EXTN_PORTAD_SHIFT 21 311 #define MDIO_EXTN_DEVAD_MASK 0x1FUL 312 #define MDIO_EXTN_DEVAD_SHIFT 16 313 #define MDIO_EXTN_REG_MASK 0xFFFFUL 314 #define MDIO_EXTN_REG_SHIFT 0 315 316 /* BIST Control and Status Register0 (for the Packet Memory) */ 317 #define REG_BIST0_CTRL 0x141c 318 #define BIST0_NOW 0x1 319 #define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is 320 * un-repairable because 321 * it has address decoder 322 * failure or more than 1 cell 323 * stuck-to-x failure */ 324 #define BIST0_FUSE_FLAG 0x4 325 326 /* BIST Control and Status Register1(for the retry buffer of PCI Express) */ 327 #define REG_BIST1_CTRL 0x1420 328 #define BIST1_NOW 0x1 329 #define BIST1_SRAM_FAIL 0x2 330 #define BIST1_FUSE_FLAG 0x4 331 332 /* SerDes Lock Detect Control and Status Register */ 333 #define REG_SERDES 0x1424 334 #define SERDES_PHY_CLK_SLOWDOWN BIT(18) 335 #define SERDES_MAC_CLK_SLOWDOWN BIT(17) 336 #define SERDES_SELFB_PLL_MASK 0x3UL 337 #define SERDES_SELFB_PLL_SHIFT 14 338 #define SERDES_PHYCLK_SEL_GTX BIT(13) /* 1:gtx_clk, 0:25M */ 339 #define SERDES_PCIECLK_SEL_SRDS BIT(12) /* 1:serdes,0:25M */ 340 #define SERDES_BUFS_RX_EN BIT(11) 341 #define SERDES_PD_RX BIT(10) 342 #define SERDES_PLL_EN BIT(9) 343 #define SERDES_EN BIT(8) 344 #define SERDES_SELFB_PLL_SEL_CSR BIT(6) /* 0:state-machine,1:csr */ 345 #define SERDES_SELFB_PLL_CSR_MASK 0x3UL 346 #define SERDES_SELFB_PLL_CSR_SHIFT 4 347 #define SERDES_SELFB_PLL_CSR_4 3 /* 4-12% OV-CLK */ 348 #define SERDES_SELFB_PLL_CSR_0 2 /* 0-4% OV-CLK */ 349 #define SERDES_SELFB_PLL_CSR_12 1 /* 12-18% OV-CLK */ 350 #define SERDES_SELFB_PLL_CSR_18 0 /* 18-25% OV-CLK */ 351 #define SERDES_VCO_SLOW BIT(3) 352 #define SERDES_VCO_FAST BIT(2) 353 #define SERDES_LOCK_DETECT_EN BIT(1) 354 #define SERDES_LOCK_DETECT BIT(0) 355 356 #define REG_LPI_DECISN_TIMER 0x143C 357 #define L2CB_LPI_DESISN_TIMER 0x7D00 358 359 #define REG_LPI_CTRL 0x1440 360 #define LPI_CTRL_CHK_DA BIT(31) 361 #define LPI_CTRL_ENH_TO_MASK 0x1FFFUL 362 #define LPI_CTRL_ENH_TO_SHIFT 12 363 #define LPI_CTRL_ENH_TH_MASK 0x1FUL 364 #define LPI_CTRL_ENH_TH_SHIFT 6 365 #define LPI_CTRL_ENH_EN BIT(5) 366 #define LPI_CTRL_CHK_RX BIT(4) 367 #define LPI_CTRL_CHK_STATE BIT(3) 368 #define LPI_CTRL_GMII BIT(2) 369 #define LPI_CTRL_TO_PHY BIT(1) 370 #define LPI_CTRL_EN BIT(0) 371 372 #define REG_LPI_WAIT 0x1444 373 #define LPI_WAIT_TIMER_MASK 0xFFFFUL 374 #define LPI_WAIT_TIMER_SHIFT 0 375 376 /* MAC Control Register */ 377 #define REG_MAC_CTRL 0x1480 378 #define MAC_CTRL_SPEED_MODE_SW BIT(30) /* 0:phy,1:sw */ 379 #define MAC_CTRL_HASH_ALG_CRC32 BIT(29) /* 1:legacy,0:lw_5b */ 380 #define MAC_CTRL_SINGLE_PAUSE_EN BIT(28) 381 #define MAC_CTRL_DBG BIT(27) 382 #define MAC_CTRL_BC_EN BIT(26) 383 #define MAC_CTRL_MC_ALL_EN BIT(25) 384 #define MAC_CTRL_RX_CHKSUM_EN BIT(24) 385 #define MAC_CTRL_TX_HUGE BIT(23) 386 #define MAC_CTRL_DBG_TX_BKPRESURE BIT(22) 387 #define MAC_CTRL_SPEED_MASK 3UL 388 #define MAC_CTRL_SPEED_SHIFT 20 389 #define MAC_CTRL_SPEED_10_100 1 390 #define MAC_CTRL_SPEED_1000 2 391 #define MAC_CTRL_TX_SIMURST BIT(19) 392 #define MAC_CTRL_SCNT BIT(17) 393 #define MAC_CTRL_TX_PAUSE BIT(16) 394 #define MAC_CTRL_PROMIS_EN BIT(15) 395 #define MAC_CTRL_RMV_VLAN BIT(14) 396 #define MAC_CTRL_PRMLEN_MASK 0xFUL 397 #define MAC_CTRL_PRMLEN_SHIFT 10 398 #define MAC_CTRL_HUGE_EN BIT(9) 399 #define MAC_CTRL_LENCHK BIT(8) 400 #define MAC_CTRL_PAD BIT(7) 401 #define MAC_CTRL_ADD_CRC BIT(6) 402 #define MAC_CTRL_DUPLX BIT(5) 403 #define MAC_CTRL_LOOPBACK BIT(4) 404 #define MAC_CTRL_RX_FLOW BIT(3) 405 #define MAC_CTRL_TX_FLOW BIT(2) 406 #define MAC_CTRL_RX_EN BIT(1) 407 #define MAC_CTRL_TX_EN BIT(0) 408 409 /* MAC IPG/IFG Control Register */ 410 #define REG_MAC_IPG_IFG 0x1484 411 #define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back 412 * inter-packet gap. The 413 * default is 96-bit time */ 414 #define MAC_IPG_IFG_IPGT_MASK 0x7f 415 #define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to 416 * enforce in between RX frames */ 417 #define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */ 418 #define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */ 419 #define MAC_IPG_IFG_IPGR1_MASK 0x7f 420 #define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */ 421 #define MAC_IPG_IFG_IPGR2_MASK 0x7f 422 423 /* MAC STATION ADDRESS */ 424 #define REG_MAC_STA_ADDR 0x1488 425 426 /* Hash table for multicast address */ 427 #define REG_RX_HASH_TABLE 0x1490 428 429 /* MAC Half-Duplex Control Register */ 430 #define REG_MAC_HALF_DUPLX_CTRL 0x1498 431 #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */ 432 #define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff 433 #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 434 #define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf 435 #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 436 #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 437 #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure, 438 * immediately start the 439 * transmission after back pressure */ 440 #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */ 441 #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */ 442 #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf 443 #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */ 444 #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */ 445 446 /* Maximum Frame Length Control Register */ 447 #define REG_MTU 0x149c 448 449 /* Wake-On-Lan control register */ 450 #define REG_WOL_CTRL 0x14a0 451 #define WOL_PT7_MATCH BIT(31) 452 #define WOL_PT6_MATCH BIT(30) 453 #define WOL_PT5_MATCH BIT(29) 454 #define WOL_PT4_MATCH BIT(28) 455 #define WOL_PT3_MATCH BIT(27) 456 #define WOL_PT2_MATCH BIT(26) 457 #define WOL_PT1_MATCH BIT(25) 458 #define WOL_PT0_MATCH BIT(24) 459 #define WOL_PT7_EN BIT(23) 460 #define WOL_PT6_EN BIT(22) 461 #define WOL_PT5_EN BIT(21) 462 #define WOL_PT4_EN BIT(20) 463 #define WOL_PT3_EN BIT(19) 464 #define WOL_PT2_EN BIT(18) 465 #define WOL_PT1_EN BIT(17) 466 #define WOL_PT0_EN BIT(16) 467 #define WOL_LNKCHG_ST BIT(10) 468 #define WOL_MAGIC_ST BIT(9) 469 #define WOL_PATTERN_ST BIT(8) 470 #define WOL_OOB_EN BIT(6) 471 #define WOL_LINK_CHG_PME_EN BIT(5) 472 #define WOL_LINK_CHG_EN BIT(4) 473 #define WOL_MAGIC_PME_EN BIT(3) 474 #define WOL_MAGIC_EN BIT(2) 475 #define WOL_PATTERN_PME_EN BIT(1) 476 #define WOL_PATTERN_EN BIT(0) 477 478 /* WOL Length ( 2 DWORD ) */ 479 #define REG_WOL_PTLEN1 0x14A4 480 #define WOL_PTLEN1_3_MASK 0xFFUL 481 #define WOL_PTLEN1_3_SHIFT 24 482 #define WOL_PTLEN1_2_MASK 0xFFUL 483 #define WOL_PTLEN1_2_SHIFT 16 484 #define WOL_PTLEN1_1_MASK 0xFFUL 485 #define WOL_PTLEN1_1_SHIFT 8 486 #define WOL_PTLEN1_0_MASK 0xFFUL 487 #define WOL_PTLEN1_0_SHIFT 0 488 489 #define REG_WOL_PTLEN2 0x14A8 490 #define WOL_PTLEN2_7_MASK 0xFFUL 491 #define WOL_PTLEN2_7_SHIFT 24 492 #define WOL_PTLEN2_6_MASK 0xFFUL 493 #define WOL_PTLEN2_6_SHIFT 16 494 #define WOL_PTLEN2_5_MASK 0xFFUL 495 #define WOL_PTLEN2_5_SHIFT 8 496 #define WOL_PTLEN2_4_MASK 0xFFUL 497 #define WOL_PTLEN2_4_SHIFT 0 498 499 /* Internal SRAM Partition Register */ 500 #define RFDX_HEAD_ADDR_MASK 0x03FF 501 #define RFDX_HARD_ADDR_SHIFT 0 502 #define RFDX_TAIL_ADDR_MASK 0x03FF 503 #define RFDX_TAIL_ADDR_SHIFT 16 504 505 #define REG_SRAM_RFD0_INFO 0x1500 506 #define REG_SRAM_RFD1_INFO 0x1504 507 #define REG_SRAM_RFD2_INFO 0x1508 508 #define REG_SRAM_RFD3_INFO 0x150C 509 510 #define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */ 511 #define RFD_NIC_LEN_MASK 0x03FF 512 513 #define REG_SRAM_TRD_ADDR 0x1518 514 #define TPD_HEAD_ADDR_MASK 0x03FF 515 #define TPD_HEAD_ADDR_SHIFT 0 516 #define TPD_TAIL_ADDR_MASK 0x03FF 517 #define TPD_TAIL_ADDR_SHIFT 16 518 519 #define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */ 520 #define TPD_NIC_LEN_MASK 0x03FF 521 522 #define REG_SRAM_RXF_ADDR 0x1520 523 #define REG_SRAM_RXF_LEN 0x1524 524 #define REG_SRAM_TXF_ADDR 0x1528 525 #define REG_SRAM_TXF_LEN 0x152C 526 #define REG_SRAM_TCPH_ADDR 0x1530 527 #define REG_SRAM_PKTH_ADDR 0x1532 528 529 /* 530 * Load Ptr Register 531 * Software sets this bit after the initialization of the head and tail */ 532 #define REG_LOAD_PTR 0x1534 533 534 /* 535 * addresses of all descriptors, as well as the following descriptor 536 * control register, which triggers each function block to load the head 537 * pointer to prepare for the operation. This bit is then self-cleared 538 * after one cycle. 539 */ 540 #define REG_RX_BASE_ADDR_HI 0x1540 541 #define REG_TX_BASE_ADDR_HI 0x1544 542 #define REG_RFD0_HEAD_ADDR_LO 0x1550 543 #define REG_RFD_RING_SIZE 0x1560 544 #define RFD_RING_SIZE_MASK 0x0FFF 545 #define REG_RX_BUF_SIZE 0x1564 546 #define RX_BUF_SIZE_MASK 0xFFFF 547 #define REG_RRD0_HEAD_ADDR_LO 0x1568 548 #define REG_RRD_RING_SIZE 0x1578 549 #define RRD_RING_SIZE_MASK 0x0FFF 550 #define REG_TPD_PRI1_ADDR_LO 0x157C 551 #define REG_TPD_PRI0_ADDR_LO 0x1580 552 #define REG_TPD_RING_SIZE 0x1584 553 #define TPD_RING_SIZE_MASK 0xFFFF 554 555 /* TXQ Control Register */ 556 #define REG_TXQ_CTRL 0x1590 557 #define TXQ_TXF_BURST_NUM_MASK 0xFFFFUL 558 #define TXQ_TXF_BURST_NUM_SHIFT 16 559 #define L1C_TXQ_TXF_BURST_PREF 0x200 560 #define L2CB_TXQ_TXF_BURST_PREF 0x40 561 #define TXQ_CTRL_PEDING_CLR BIT(8) 562 #define TXQ_CTRL_LS_8023_EN BIT(7) 563 #define TXQ_CTRL_ENH_MODE BIT(6) 564 #define TXQ_CTRL_EN BIT(5) 565 #define TXQ_CTRL_IP_OPTION_EN BIT(4) 566 #define TXQ_NUM_TPD_BURST_MASK 0xFUL 567 #define TXQ_NUM_TPD_BURST_SHIFT 0 568 #define TXQ_NUM_TPD_BURST_DEF 5 569 #define TXQ_CFGV (\ 570 FIELDX(TXQ_NUM_TPD_BURST, TXQ_NUM_TPD_BURST_DEF) |\ 571 TXQ_CTRL_ENH_MODE |\ 572 TXQ_CTRL_LS_8023_EN |\ 573 TXQ_CTRL_IP_OPTION_EN) 574 #define L1C_TXQ_CFGV (\ 575 TXQ_CFGV |\ 576 FIELDX(TXQ_TXF_BURST_NUM, L1C_TXQ_TXF_BURST_PREF)) 577 #define L2CB_TXQ_CFGV (\ 578 TXQ_CFGV |\ 579 FIELDX(TXQ_TXF_BURST_NUM, L2CB_TXQ_TXF_BURST_PREF)) 580 581 582 /* Jumbo packet Threshold for task offload */ 583 #define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */ 584 #define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF 585 #define MAX_TSO_FRAME_SIZE (7*1024) 586 587 #define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */ 588 #define TXF_WATER_MARK_MASK 0x0FFF 589 #define TXF_LOW_WATER_MARK_SHIFT 0 590 #define TXF_HIGH_WATER_MARK_SHIFT 16 591 #define TXQ_CTRL_BURST_MODE_EN 0x80000000 592 593 #define REG_THRUPUT_MON_CTRL 0x159C 594 #define THRUPUT_MON_RATE_MASK 0x3 595 #define THRUPUT_MON_RATE_SHIFT 0 596 #define THRUPUT_MON_EN 0x80 597 598 /* RXQ Control Register */ 599 #define REG_RXQ_CTRL 0x15A0 600 #define ASPM_THRUPUT_LIMIT_MASK 0x3 601 #define ASPM_THRUPUT_LIMIT_SHIFT 0 602 #define ASPM_THRUPUT_LIMIT_NO 0x00 603 #define ASPM_THRUPUT_LIMIT_1M 0x01 604 #define ASPM_THRUPUT_LIMIT_10M 0x02 605 #define ASPM_THRUPUT_LIMIT_100M 0x03 606 #define IPV6_CHKSUM_CTRL_EN BIT(7) 607 #define RXQ_RFD_BURST_NUM_MASK 0x003F 608 #define RXQ_RFD_BURST_NUM_SHIFT 20 609 #define RXQ_NUM_RFD_PREF_DEF 8 610 #define RSS_MODE_MASK 3UL 611 #define RSS_MODE_SHIFT 26 612 #define RSS_MODE_DIS 0 613 #define RSS_MODE_SQSI 1 614 #define RSS_MODE_MQSI 2 615 #define RSS_MODE_MQMI 3 616 #define RSS_NIP_QUEUE_SEL BIT(28) /* 0:q0, 1:table */ 617 #define RRS_HASH_CTRL_EN BIT(29) 618 #define RX_CUT_THRU_EN BIT(30) 619 #define RXQ_CTRL_EN BIT(31) 620 621 #define REG_RFD_FREE_THRESH 0x15A4 622 #define RFD_FREE_THRESH_MASK 0x003F 623 #define RFD_FREE_HI_THRESH_SHIFT 0 624 #define RFD_FREE_LO_THRESH_SHIFT 6 625 626 /* RXF flow control register */ 627 #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8 628 #define RXQ_RXF_PAUSE_TH_HI_SHIFT 0 629 #define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF 630 #define RXQ_RXF_PAUSE_TH_LO_SHIFT 16 631 #define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF 632 633 #define REG_RXD_DMA_CTRL 0x15AC 634 #define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */ 635 #define RXD_DMA_THRESH_SHIFT 0 636 #define RXD_DMA_DOWN_TIMER_MASK 0xFFFF 637 #define RXD_DMA_DOWN_TIMER_SHIFT 16 638 639 /* DMA Engine Control Register */ 640 #define REG_DMA_CTRL 0x15C0 641 #define DMA_CTRL_SMB_NOW BIT(31) 642 #define DMA_CTRL_WPEND_CLR BIT(30) 643 #define DMA_CTRL_RPEND_CLR BIT(29) 644 #define DMA_CTRL_WDLY_CNT_MASK 0xFUL 645 #define DMA_CTRL_WDLY_CNT_SHIFT 16 646 #define DMA_CTRL_WDLY_CNT_DEF 4 647 #define DMA_CTRL_RDLY_CNT_MASK 0x1FUL 648 #define DMA_CTRL_RDLY_CNT_SHIFT 11 649 #define DMA_CTRL_RDLY_CNT_DEF 15 650 #define DMA_CTRL_RREQ_PRI_DATA BIT(10) /* 0:tpd, 1:data */ 651 #define DMA_CTRL_WREQ_BLEN_MASK 7UL 652 #define DMA_CTRL_WREQ_BLEN_SHIFT 7 653 #define DMA_CTRL_RREQ_BLEN_MASK 7UL 654 #define DMA_CTRL_RREQ_BLEN_SHIFT 4 655 #define L1C_CTRL_DMA_RCB_LEN128 BIT(3) /* 0:64bytes,1:128bytes */ 656 #define DMA_CTRL_RORDER_MODE_MASK 7UL 657 #define DMA_CTRL_RORDER_MODE_SHIFT 0 658 #define DMA_CTRL_RORDER_MODE_OUT 4 659 #define DMA_CTRL_RORDER_MODE_ENHANCE 2 660 #define DMA_CTRL_RORDER_MODE_IN 1 661 662 /* INT-triggle/SMB Control Register */ 663 #define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */ 664 #define SMB_STAT_TIMER_MASK 0xFFFFFF 665 #define REG_TINT_TPD_THRESH 0x15C8 /* tpd th to trig intrrupt */ 666 667 /* Mail box */ 668 #define MB_RFDX_PROD_IDX_MASK 0xFFFF 669 #define REG_MB_RFD0_PROD_IDX 0x15E0 670 671 #define REG_TPD_PRI1_PIDX 0x15F0 /* 16bit,hi-tpd producer idx */ 672 #define REG_TPD_PRI0_PIDX 0x15F2 /* 16bit,lo-tpd producer idx */ 673 #define REG_TPD_PRI1_CIDX 0x15F4 /* 16bit,hi-tpd consumer idx */ 674 #define REG_TPD_PRI0_CIDX 0x15F6 /* 16bit,lo-tpd consumer idx */ 675 676 #define REG_MB_RFD01_CONS_IDX 0x15F8 677 #define MB_RFD0_CONS_IDX_MASK 0x0000FFFF 678 #define MB_RFD1_CONS_IDX_MASK 0xFFFF0000 679 680 /* Interrupt Status Register */ 681 #define REG_ISR 0x1600 682 #define ISR_SMB 0x00000001 683 #define ISR_TIMER 0x00000002 684 /* 685 * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set 686 * in Table 51 Selene Master Control Register (Offset 0x1400). 687 */ 688 #define ISR_MANUAL 0x00000004 689 #define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */ 690 #define ISR_RFD0_UR 0x00000010 /* RFD0 under run */ 691 #define ISR_RFD1_UR 0x00000020 692 #define ISR_RFD2_UR 0x00000040 693 #define ISR_RFD3_UR 0x00000080 694 #define ISR_TXF_UR 0x00000100 695 #define ISR_DMAR_TO_RST 0x00000200 696 #define ISR_DMAW_TO_RST 0x00000400 697 #define ISR_TX_CREDIT 0x00000800 698 #define ISR_GPHY 0x00001000 699 /* GPHY low power state interrupt */ 700 #define ISR_GPHY_LPW 0x00002000 701 #define ISR_TXQ_TO_RST 0x00004000 702 #define ISR_TX_PKT 0x00008000 703 #define ISR_RX_PKT_0 0x00010000 704 #define ISR_RX_PKT_1 0x00020000 705 #define ISR_RX_PKT_2 0x00040000 706 #define ISR_RX_PKT_3 0x00080000 707 #define ISR_MAC_RX 0x00100000 708 #define ISR_MAC_TX 0x00200000 709 #define ISR_UR_DETECTED 0x00400000 710 #define ISR_FERR_DETECTED 0x00800000 711 #define ISR_NFERR_DETECTED 0x01000000 712 #define ISR_CERR_DETECTED 0x02000000 713 #define ISR_PHY_LINKDOWN 0x04000000 714 #define ISR_DIS_INT 0x80000000 715 716 /* Interrupt Mask Register */ 717 #define REG_IMR 0x1604 718 719 #define IMR_NORMAL_MASK (\ 720 ISR_MANUAL |\ 721 ISR_HW_RXF_OV |\ 722 ISR_RFD0_UR |\ 723 ISR_TXF_UR |\ 724 ISR_DMAR_TO_RST |\ 725 ISR_TXQ_TO_RST |\ 726 ISR_DMAW_TO_RST |\ 727 ISR_GPHY |\ 728 ISR_TX_PKT |\ 729 ISR_RX_PKT_0 |\ 730 ISR_GPHY_LPW |\ 731 ISR_PHY_LINKDOWN) 732 733 #define ISR_RX_PKT (\ 734 ISR_RX_PKT_0 |\ 735 ISR_RX_PKT_1 |\ 736 ISR_RX_PKT_2 |\ 737 ISR_RX_PKT_3) 738 739 #define ISR_OVER (\ 740 ISR_RFD0_UR |\ 741 ISR_RFD1_UR |\ 742 ISR_RFD2_UR |\ 743 ISR_RFD3_UR |\ 744 ISR_HW_RXF_OV |\ 745 ISR_TXF_UR) 746 747 #define ISR_ERROR (\ 748 ISR_DMAR_TO_RST |\ 749 ISR_TXQ_TO_RST |\ 750 ISR_DMAW_TO_RST |\ 751 ISR_PHY_LINKDOWN) 752 753 #define REG_INT_RETRIG_TIMER 0x1608 754 #define INT_RETRIG_TIMER_MASK 0xFFFF 755 756 #define REG_MAC_RX_STATUS_BIN 0x1700 757 #define REG_MAC_RX_STATUS_END 0x175c 758 #define REG_MAC_TX_STATUS_BIN 0x1760 759 #define REG_MAC_TX_STATUS_END 0x17c0 760 761 #define REG_CLK_GATING_CTRL 0x1814 762 #define CLK_GATING_DMAW_EN 0x0001 763 #define CLK_GATING_DMAR_EN 0x0002 764 #define CLK_GATING_TXQ_EN 0x0004 765 #define CLK_GATING_RXQ_EN 0x0008 766 #define CLK_GATING_TXMAC_EN 0x0010 767 #define CLK_GATING_RXMAC_EN 0x0020 768 769 #define CLK_GATING_EN_ALL (CLK_GATING_DMAW_EN |\ 770 CLK_GATING_DMAR_EN |\ 771 CLK_GATING_TXQ_EN |\ 772 CLK_GATING_RXQ_EN |\ 773 CLK_GATING_TXMAC_EN|\ 774 CLK_GATING_RXMAC_EN) 775 776 /* DEBUG ADDR */ 777 #define REG_DEBUG_DATA0 0x1900 778 #define REG_DEBUG_DATA1 0x1904 779 780 #define L1D_MPW_PHYID1 0xD01C /* V7 */ 781 #define L1D_MPW_PHYID2 0xD01D /* V1-V6 */ 782 #define L1D_MPW_PHYID3 0xD01E /* V8 */ 783 784 785 /* Autoneg Advertisement Register */ 786 #define ADVERTISE_DEFAULT_CAP \ 787 (ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM) 788 789 /* 1000BASE-T Control Register */ 790 #define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */ 791 792 #define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 793 #define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 794 #define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 795 #define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 796 #define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 797 #define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 798 #define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 799 #define GIGA_CR_1000T_SPEED_MASK 0x0300 800 #define GIGA_CR_1000T_DEFAULT_CAP 0x0300 801 802 /* PHY Specific Status Register */ 803 #define MII_GIGA_PSSR 0x11 804 #define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 805 #define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 806 #define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 807 #define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */ 808 #define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */ 809 #define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 810 811 /* PHY Interrupt Enable Register */ 812 #define MII_IER 0x12 813 #define IER_LINK_UP 0x0400 814 #define IER_LINK_DOWN 0x0800 815 816 /* PHY Interrupt Status Register */ 817 #define MII_ISR 0x13 818 #define ISR_LINK_UP 0x0400 819 #define ISR_LINK_DOWN 0x0800 820 821 /* Cable-Detect-Test Control Register */ 822 #define MII_CDTC 0x16 823 #define CDTC_EN_OFF 0 /* sc */ 824 #define CDTC_EN_BITS 1 825 #define CDTC_PAIR_OFF 8 826 #define CDTC_PAIR_BIT 2 827 828 /* Cable-Detect-Test Status Register */ 829 #define MII_CDTS 0x1C 830 #define CDTS_STATUS_OFF 8 831 #define CDTS_STATUS_BITS 2 832 #define CDTS_STATUS_NORMAL 0 833 #define CDTS_STATUS_SHORT 1 834 #define CDTS_STATUS_OPEN 2 835 #define CDTS_STATUS_INVALID 3 836 837 #define MII_DBG_ADDR 0x1D 838 #define MII_DBG_DATA 0x1E 839 840 /***************************** debug port *************************************/ 841 842 #define MIIDBG_ANACTRL 0x00 843 #define ANACTRL_CLK125M_DELAY_EN 0x8000 844 #define ANACTRL_VCO_FAST 0x4000 845 #define ANACTRL_VCO_SLOW 0x2000 846 #define ANACTRL_AFE_MODE_EN 0x1000 847 #define ANACTRL_LCKDET_PHY 0x800 848 #define ANACTRL_LCKDET_EN 0x400 849 #define ANACTRL_OEN_125M 0x200 850 #define ANACTRL_HBIAS_EN 0x100 851 #define ANACTRL_HB_EN 0x80 852 #define ANACTRL_SEL_HSP 0x40 853 #define ANACTRL_CLASSA_EN 0x20 854 #define ANACTRL_MANUSWON_SWR_MASK 3U 855 #define ANACTRL_MANUSWON_SWR_SHIFT 2 856 #define ANACTRL_MANUSWON_SWR_2V 0 857 #define ANACTRL_MANUSWON_SWR_1P9V 1 858 #define ANACTRL_MANUSWON_SWR_1P8V 2 859 #define ANACTRL_MANUSWON_SWR_1P7V 3 860 #define ANACTRL_MANUSWON_BW3_4M 0x2 861 #define ANACTRL_RESTART_CAL 0x1 862 #define ANACTRL_DEF 0x02EF 863 864 #define MIIDBG_SYSMODCTRL 0x04 865 #define SYSMODCTRL_IECHOADJ_PFMH_PHY 0x8000 866 #define SYSMODCTRL_IECHOADJ_BIASGEN 0x4000 867 #define SYSMODCTRL_IECHOADJ_PFML_PHY 0x2000 868 #define SYSMODCTRL_IECHOADJ_PS_MASK 3U 869 #define SYSMODCTRL_IECHOADJ_PS_SHIFT 10 870 #define SYSMODCTRL_IECHOADJ_PS_40 3 871 #define SYSMODCTRL_IECHOADJ_PS_20 2 872 #define SYSMODCTRL_IECHOADJ_PS_0 1 873 #define SYSMODCTRL_IECHOADJ_10BT_100MV 0x40 /* 1:100mv, 0:200mv */ 874 #define SYSMODCTRL_IECHOADJ_HLFAP_MASK 3U 875 #define SYSMODCTRL_IECHOADJ_HLFAP_SHIFT 4 876 #define SYSMODCTRL_IECHOADJ_VDFULBW 0x8 877 #define SYSMODCTRL_IECHOADJ_VDBIASHLF 0x4 878 #define SYSMODCTRL_IECHOADJ_VDAMPHLF 0x2 879 #define SYSMODCTRL_IECHOADJ_VDLANSW 0x1 880 #define SYSMODCTRL_IECHOADJ_DEF 0x88BB /* ???? */ 881 882 /* for l1d & l2cb */ 883 #define SYSMODCTRL_IECHOADJ_CUR_ADD 0x8000 884 #define SYSMODCTRL_IECHOADJ_CUR_MASK 7U 885 #define SYSMODCTRL_IECHOADJ_CUR_SHIFT 12 886 #define SYSMODCTRL_IECHOADJ_VOL_MASK 0xFU 887 #define SYSMODCTRL_IECHOADJ_VOL_SHIFT 8 888 #define SYSMODCTRL_IECHOADJ_VOL_17ALL 3 889 #define SYSMODCTRL_IECHOADJ_VOL_100M15 1 890 #define SYSMODCTRL_IECHOADJ_VOL_10M17 0 891 #define SYSMODCTRL_IECHOADJ_BIAS1_MASK 0xFU 892 #define SYSMODCTRL_IECHOADJ_BIAS1_SHIFT 4 893 #define SYSMODCTRL_IECHOADJ_BIAS2_MASK 0xFU 894 #define SYSMODCTRL_IECHOADJ_BIAS2_SHIFT 0 895 #define L1D_SYSMODCTRL_IECHOADJ_DEF 0x4FBB 896 897 #define MIIDBG_SRDSYSMOD 0x05 898 #define SRDSYSMOD_LCKDET_EN 0x2000 899 #define SRDSYSMOD_PLL_EN 0x800 900 #define SRDSYSMOD_SEL_HSP 0x400 901 #define SRDSYSMOD_HLFTXDR 0x200 902 #define SRDSYSMOD_TXCLK_DELAY_EN 0x100 903 #define SRDSYSMOD_TXELECIDLE 0x80 904 #define SRDSYSMOD_DEEMP_EN 0x40 905 #define SRDSYSMOD_MS_PAD 0x4 906 #define SRDSYSMOD_CDR_ADC_VLTG 0x2 907 #define SRDSYSMOD_CDR_DAC_1MA 0x1 908 #define SRDSYSMOD_DEF 0x2C46 909 910 #define MIIDBG_CFGLPSPD 0x0A 911 #define CFGLPSPD_RSTCNT_MASK 3U 912 #define CFGLPSPD_RSTCNT_SHIFT 14 913 #define CFGLPSPD_RSTCNT_CLK125SW 0x2000 914 915 #define MIIDBG_HIBNEG 0x0B 916 #define HIBNEG_PSHIB_EN 0x8000 917 #define HIBNEG_WAKE_BOTH 0x4000 918 #define HIBNEG_ONOFF_ANACHG_SUDEN 0x2000 919 #define HIBNEG_HIB_PULSE 0x1000 920 #define HIBNEG_GATE_25M_EN 0x800 921 #define HIBNEG_RST_80U 0x400 922 #define HIBNEG_RST_TIMER_MASK 3U 923 #define HIBNEG_RST_TIMER_SHIFT 8 924 #define HIBNEG_GTX_CLK_DELAY_MASK 3U 925 #define HIBNEG_GTX_CLK_DELAY_SHIFT 5 926 #define HIBNEG_BYPSS_BRKTIMER 0x10 927 #define HIBNEG_DEF 0xBC40 928 929 #define MIIDBG_TST10BTCFG 0x12 930 #define TST10BTCFG_INTV_TIMER_MASK 3U 931 #define TST10BTCFG_INTV_TIMER_SHIFT 14 932 #define TST10BTCFG_TRIGER_TIMER_MASK 3U 933 #define TST10BTCFG_TRIGER_TIMER_SHIFT 12 934 #define TST10BTCFG_DIV_MAN_MLT3_EN 0x800 935 #define TST10BTCFG_OFF_DAC_IDLE 0x400 936 #define TST10BTCFG_LPBK_DEEP 0x4 /* 1:deep,0:shallow */ 937 #define TST10BTCFG_DEF 0x4C04 938 939 #define MIIDBG_AZ_ANADECT 0x15 940 #define AZ_ANADECT_10BTRX_TH 0x8000 941 #define AZ_ANADECT_BOTH_01CHNL 0x4000 942 #define AZ_ANADECT_INTV_MASK 0x3FU 943 #define AZ_ANADECT_INTV_SHIFT 8 944 #define AZ_ANADECT_THRESH_MASK 0xFU 945 #define AZ_ANADECT_THRESH_SHIFT 4 946 #define AZ_ANADECT_CHNL_MASK 0xFU 947 #define AZ_ANADECT_CHNL_SHIFT 0 948 #define AZ_ANADECT_DEF 0x3220 949 #define AZ_ANADECT_LONG 0xb210 950 951 #define MIIDBG_MSE16DB 0x18 /* l1d */ 952 #define L1D_MSE16DB_UP 0x05EA 953 #define L1D_MSE16DB_DOWN 0x02EA 954 955 #define MIIDBG_LEGCYPS 0x29 956 #define LEGCYPS_EN 0x8000 957 #define LEGCYPS_DAC_AMP1000_MASK 7U 958 #define LEGCYPS_DAC_AMP1000_SHIFT 12 959 #define LEGCYPS_DAC_AMP100_MASK 7U 960 #define LEGCYPS_DAC_AMP100_SHIFT 9 961 #define LEGCYPS_DAC_AMP10_MASK 7U 962 #define LEGCYPS_DAC_AMP10_SHIFT 6 963 #define LEGCYPS_UNPLUG_TIMER_MASK 7U 964 #define LEGCYPS_UNPLUG_TIMER_SHIFT 3 965 #define LEGCYPS_UNPLUG_DECT_EN 0x4 966 #define LEGCYPS_ECNC_PS_EN 0x1 967 #define L1D_LEGCYPS_DEF 0x129D 968 #define L1C_LEGCYPS_DEF 0x36DD 969 970 #define MIIDBG_TST100BTCFG 0x36 971 #define TST100BTCFG_NORMAL_BW_EN 0x8000 972 #define TST100BTCFG_BADLNK_BYPASS 0x4000 973 #define TST100BTCFG_SHORTCABL_TH_MASK 0x3FU 974 #define TST100BTCFG_SHORTCABL_TH_SHIFT 8 975 #define TST100BTCFG_LITCH_EN 0x80 976 #define TST100BTCFG_VLT_SW 0x40 977 #define TST100BTCFG_LONGCABL_TH_MASK 0x3FU 978 #define TST100BTCFG_LONGCABL_TH_SHIFT 0 979 #define TST100BTCFG_DEF 0xE12C 980 981 #define MIIDBG_VOLT_CTRL 0x3B /* only for l2cb 1 & 2 */ 982 #define VOLT_CTRL_CABLE1TH_MASK 0x1FFU 983 #define VOLT_CTRL_CABLE1TH_SHIFT 7 984 #define VOLT_CTRL_AMPCTRL_MASK 3U 985 #define VOLT_CTRL_AMPCTRL_SHIFT 5 986 #define VOLT_CTRL_SW_BYPASS 0x10 987 #define VOLT_CTRL_SWLOWEST 0x8 988 #define VOLT_CTRL_DACAMP10_MASK 7U 989 #define VOLT_CTRL_DACAMP10_SHIFT 0 990 991 #define MIIDBG_CABLE1TH_DET 0x3E 992 #define CABLE1TH_DET_EN 0x8000 993 994 995 /******* dev 3 *********/ 996 #define MIIEXT_PCS 3 997 998 #define MIIEXT_CLDCTRL3 0x8003 999 #define CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000 1000 #define CLDCTRL3_AZ_DISAMP 0x1000 1001 #define L2CB_CLDCTRL3 0x4D19 1002 #define L1D_CLDCTRL3 0xDD19 1003 1004 #define MIIEXT_CLDCTRL6 0x8006 1005 #define CLDCTRL6_CAB_LEN_MASK 0x1FFU 1006 #define CLDCTRL6_CAB_LEN_SHIFT 0 1007 #define CLDCTRL6_CAB_LEN_SHORT 0x50 1008 1009 /********* dev 7 **********/ 1010 #define MIIEXT_ANEG 7 1011 1012 #define MIIEXT_LOCAL_EEEADV 0x3C 1013 #define LOCAL_EEEADV_1000BT 0x4 1014 #define LOCAL_EEEADV_100BT 0x2 1015 1016 #define MIIEXT_REMOTE_EEEADV 0x3D 1017 #define REMOTE_EEEADV_1000BT 0x4 1018 #define REMOTE_EEEADV_100BT 0x2 1019 1020 #define MIIEXT_EEE_ANEG 0x8000 1021 #define EEE_ANEG_1000M 0x4 1022 #define EEE_ANEG_100M 0x2 1023 1024 #endif /*_ATL1C_HW_H_*/ 1025