1 /* 2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. 3 * 4 * Derived from Intel e1000 driver 5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the Free 9 * Software Foundation; either version 2 of the License, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 59 19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 22 #ifndef _ATL1C_H_ 23 #define _ATL1C_H_ 24 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/types.h> 28 #include <linux/errno.h> 29 #include <linux/module.h> 30 #include <linux/pci.h> 31 #include <linux/netdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/ioport.h> 35 #include <linux/slab.h> 36 #include <linux/list.h> 37 #include <linux/delay.h> 38 #include <linux/sched.h> 39 #include <linux/in.h> 40 #include <linux/ip.h> 41 #include <linux/ipv6.h> 42 #include <linux/udp.h> 43 #include <linux/mii.h> 44 #include <linux/io.h> 45 #include <linux/vmalloc.h> 46 #include <linux/pagemap.h> 47 #include <linux/tcp.h> 48 #include <linux/ethtool.h> 49 #include <linux/if_vlan.h> 50 #include <linux/workqueue.h> 51 #include <net/checksum.h> 52 #include <net/ip6_checksum.h> 53 54 #include "atl1c_hw.h" 55 56 /* Wake Up Filter Control */ 57 #define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 58 #define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 59 #define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 60 #define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ 61 #define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 62 63 #define AT_VLAN_TO_TAG(_vlan, _tag) \ 64 _tag = ((((_vlan) >> 8) & 0xFF) |\ 65 (((_vlan) & 0xFF) << 8)) 66 67 #define AT_TAG_TO_VLAN(_tag, _vlan) \ 68 _vlan = ((((_tag) >> 8) & 0xFF) |\ 69 (((_tag) & 0xFF) << 8)) 70 71 #define SPEED_0 0xffff 72 #define HALF_DUPLEX 1 73 #define FULL_DUPLEX 2 74 75 #define AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN) 76 #define MAX_JUMBO_FRAME_SIZE (6*1024) 77 78 #define AT_MAX_RECEIVE_QUEUE 4 79 #define AT_DEF_RECEIVE_QUEUE 1 80 #define AT_MAX_TRANSMIT_QUEUE 2 81 82 #define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL 83 #define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL 84 85 #define AT_TX_WATCHDOG (5 * HZ) 86 #define AT_MAX_INT_WORK 5 87 #define AT_TWSI_EEPROM_TIMEOUT 100 88 #define AT_HW_MAX_IDLE_DELAY 10 89 #define AT_SUSPEND_LINK_TIMEOUT 100 90 91 #define AT_ASPM_L0S_TIMER 6 92 #define AT_ASPM_L1_TIMER 12 93 #define AT_LCKDET_TIMER 12 94 95 #define ATL1C_PCIE_L0S_L1_DISABLE 0x01 96 #define ATL1C_PCIE_PHY_RESET 0x02 97 98 #define ATL1C_ASPM_L0s_ENABLE 0x0001 99 #define ATL1C_ASPM_L1_ENABLE 0x0002 100 101 #define AT_REGS_LEN (74 * sizeof(u32)) 102 #define AT_EEPROM_LEN 512 103 104 #define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) 105 #define ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc) 106 #define ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc) 107 #define ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status) 108 109 /* tpd word 1 bit 0:7 General Checksum task offload */ 110 #define TPD_L4HDR_OFFSET_MASK 0x00FF 111 #define TPD_L4HDR_OFFSET_SHIFT 0 112 113 /* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */ 114 #define TPD_TCPHDR_OFFSET_MASK 0x00FF 115 #define TPD_TCPHDR_OFFSET_SHIFT 0 116 117 /* tpd word 1 bit 0:7 Custom Checksum task offload */ 118 #define TPD_PLOADOFFSET_MASK 0x00FF 119 #define TPD_PLOADOFFSET_SHIFT 0 120 121 /* tpd word 1 bit 8:17 */ 122 #define TPD_CCSUM_EN_MASK 0x0001 123 #define TPD_CCSUM_EN_SHIFT 8 124 #define TPD_IP_CSUM_MASK 0x0001 125 #define TPD_IP_CSUM_SHIFT 9 126 #define TPD_TCP_CSUM_MASK 0x0001 127 #define TPD_TCP_CSUM_SHIFT 10 128 #define TPD_UDP_CSUM_MASK 0x0001 129 #define TPD_UDP_CSUM_SHIFT 11 130 #define TPD_LSO_EN_MASK 0x0001 /* TCP Large Send Offload */ 131 #define TPD_LSO_EN_SHIFT 12 132 #define TPD_LSO_VER_MASK 0x0001 133 #define TPD_LSO_VER_SHIFT 13 /* 0 : ipv4; 1 : ipv4/ipv6 */ 134 #define TPD_CON_VTAG_MASK 0x0001 135 #define TPD_CON_VTAG_SHIFT 14 136 #define TPD_INS_VTAG_MASK 0x0001 137 #define TPD_INS_VTAG_SHIFT 15 138 #define TPD_IPV4_PACKET_MASK 0x0001 /* valid when LSO VER is 1 */ 139 #define TPD_IPV4_PACKET_SHIFT 16 140 #define TPD_ETH_TYPE_MASK 0x0001 141 #define TPD_ETH_TYPE_SHIFT 17 /* 0 : 802.3 frame; 1 : Ethernet */ 142 143 /* tpd word 18:25 Custom Checksum task offload */ 144 #define TPD_CCSUM_OFFSET_MASK 0x00FF 145 #define TPD_CCSUM_OFFSET_SHIFT 18 146 #define TPD_CCSUM_EPAD_MASK 0x0001 147 #define TPD_CCSUM_EPAD_SHIFT 30 148 149 /* tpd word 18:30 Large Send task offload (IPv4/IPV6) */ 150 #define TPD_MSS_MASK 0x1FFF 151 #define TPD_MSS_SHIFT 18 152 153 #define TPD_EOP_MASK 0x0001 154 #define TPD_EOP_SHIFT 31 155 156 struct atl1c_tpd_desc { 157 __le16 buffer_len; /* include 4-byte CRC */ 158 __le16 vlan_tag; 159 __le32 word1; 160 __le64 buffer_addr; 161 }; 162 163 struct atl1c_tpd_ext_desc { 164 u32 reservd_0; 165 __le32 word1; 166 __le32 pkt_len; 167 u32 reservd_1; 168 }; 169 /* rrs word 0 bit 0:31 */ 170 #define RRS_RX_CSUM_MASK 0xFFFF 171 #define RRS_RX_CSUM_SHIFT 0 172 #define RRS_RX_RFD_CNT_MASK 0x000F 173 #define RRS_RX_RFD_CNT_SHIFT 16 174 #define RRS_RX_RFD_INDEX_MASK 0x0FFF 175 #define RRS_RX_RFD_INDEX_SHIFT 20 176 177 /* rrs flag bit 0:16 */ 178 #define RRS_HEAD_LEN_MASK 0x00FF 179 #define RRS_HEAD_LEN_SHIFT 0 180 #define RRS_HDS_TYPE_MASK 0x0003 181 #define RRS_HDS_TYPE_SHIFT 8 182 #define RRS_CPU_NUM_MASK 0x0003 183 #define RRS_CPU_NUM_SHIFT 10 184 #define RRS_HASH_FLG_MASK 0x000F 185 #define RRS_HASH_FLG_SHIFT 12 186 187 #define RRS_HDS_TYPE_HEAD 1 188 #define RRS_HDS_TYPE_DATA 2 189 190 #define RRS_IS_NO_HDS_TYPE(flag) \ 191 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == 0) 192 193 #define RRS_IS_HDS_HEAD(flag) \ 194 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \ 195 RRS_HDS_TYPE_HEAD) 196 197 #define RRS_IS_HDS_DATA(flag) \ 198 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \ 199 RRS_HDS_TYPE_DATA) 200 201 /* rrs word 3 bit 0:31 */ 202 #define RRS_PKT_SIZE_MASK 0x3FFF 203 #define RRS_PKT_SIZE_SHIFT 0 204 #define RRS_ERR_L4_CSUM_MASK 0x0001 205 #define RRS_ERR_L4_CSUM_SHIFT 14 206 #define RRS_ERR_IP_CSUM_MASK 0x0001 207 #define RRS_ERR_IP_CSUM_SHIFT 15 208 #define RRS_VLAN_INS_MASK 0x0001 209 #define RRS_VLAN_INS_SHIFT 16 210 #define RRS_PROT_ID_MASK 0x0007 211 #define RRS_PROT_ID_SHIFT 17 212 #define RRS_RX_ERR_SUM_MASK 0x0001 213 #define RRS_RX_ERR_SUM_SHIFT 20 214 #define RRS_RX_ERR_CRC_MASK 0x0001 215 #define RRS_RX_ERR_CRC_SHIFT 21 216 #define RRS_RX_ERR_FAE_MASK 0x0001 217 #define RRS_RX_ERR_FAE_SHIFT 22 218 #define RRS_RX_ERR_TRUNC_MASK 0x0001 219 #define RRS_RX_ERR_TRUNC_SHIFT 23 220 #define RRS_RX_ERR_RUNC_MASK 0x0001 221 #define RRS_RX_ERR_RUNC_SHIFT 24 222 #define RRS_RX_ERR_ICMP_MASK 0x0001 223 #define RRS_RX_ERR_ICMP_SHIFT 25 224 #define RRS_PACKET_BCAST_MASK 0x0001 225 #define RRS_PACKET_BCAST_SHIFT 26 226 #define RRS_PACKET_MCAST_MASK 0x0001 227 #define RRS_PACKET_MCAST_SHIFT 27 228 #define RRS_PACKET_TYPE_MASK 0x0001 229 #define RRS_PACKET_TYPE_SHIFT 28 230 #define RRS_FIFO_FULL_MASK 0x0001 231 #define RRS_FIFO_FULL_SHIFT 29 232 #define RRS_802_3_LEN_ERR_MASK 0x0001 233 #define RRS_802_3_LEN_ERR_SHIFT 30 234 #define RRS_RXD_UPDATED_MASK 0x0001 235 #define RRS_RXD_UPDATED_SHIFT 31 236 237 #define RRS_ERR_L4_CSUM 0x00004000 238 #define RRS_ERR_IP_CSUM 0x00008000 239 #define RRS_VLAN_INS 0x00010000 240 #define RRS_RX_ERR_SUM 0x00100000 241 #define RRS_RX_ERR_CRC 0x00200000 242 #define RRS_802_3_LEN_ERR 0x40000000 243 #define RRS_RXD_UPDATED 0x80000000 244 245 #define RRS_PACKET_TYPE_802_3 1 246 #define RRS_PACKET_TYPE_ETH 0 247 #define RRS_PACKET_IS_ETH(word) \ 248 ((((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK) == \ 249 RRS_PACKET_TYPE_ETH) 250 #define RRS_RXD_IS_VALID(word) \ 251 ((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1) 252 253 #define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \ 254 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1) 255 #define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \ 256 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6) 257 258 struct atl1c_recv_ret_status { 259 __le32 word0; 260 __le32 rss_hash; 261 __le16 vlan_tag; 262 __le16 flag; 263 __le32 word3; 264 }; 265 266 /* RFD descriptor */ 267 struct atl1c_rx_free_desc { 268 __le64 buffer_addr; 269 }; 270 271 /* DMA Order Settings */ 272 enum atl1c_dma_order { 273 atl1c_dma_ord_in = 1, 274 atl1c_dma_ord_enh = 2, 275 atl1c_dma_ord_out = 4 276 }; 277 278 enum atl1c_dma_rcb { 279 atl1c_rcb_64 = 0, 280 atl1c_rcb_128 = 1 281 }; 282 283 enum atl1c_mac_speed { 284 atl1c_mac_speed_0 = 0, 285 atl1c_mac_speed_10_100 = 1, 286 atl1c_mac_speed_1000 = 2 287 }; 288 289 enum atl1c_dma_req_block { 290 atl1c_dma_req_128 = 0, 291 atl1c_dma_req_256 = 1, 292 atl1c_dma_req_512 = 2, 293 atl1c_dma_req_1024 = 3, 294 atl1c_dma_req_2048 = 4, 295 atl1c_dma_req_4096 = 5 296 }; 297 298 299 enum atl1c_nic_type { 300 athr_l1c = 0, 301 athr_l2c = 1, 302 athr_l2c_b, 303 athr_l2c_b2, 304 athr_l1d, 305 athr_l1d_2, 306 }; 307 308 enum atl1c_trans_queue { 309 atl1c_trans_normal = 0, 310 atl1c_trans_high = 1 311 }; 312 313 struct atl1c_hw_stats { 314 /* rx */ 315 unsigned long rx_ok; /* The number of good packet received. */ 316 unsigned long rx_bcast; /* The number of good broadcast packet received. */ 317 unsigned long rx_mcast; /* The number of good multicast packet received. */ 318 unsigned long rx_pause; /* The number of Pause packet received. */ 319 unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */ 320 unsigned long rx_fcs_err; /* The number of packets with bad FCS. */ 321 unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */ 322 unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */ 323 unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */ 324 unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */ 325 unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */ 326 unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */ 327 unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */ 328 unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */ 329 unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */ 330 unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */ 331 unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */ 332 unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */ 333 unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */ 334 unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */ 335 unsigned long rx_align_err; /* Alignment Error */ 336 unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */ 337 unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */ 338 unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */ 339 340 /* tx */ 341 unsigned long tx_ok; /* The number of good packet transmitted. */ 342 unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */ 343 unsigned long tx_mcast; /* The number of good multicast packet transmitted. */ 344 unsigned long tx_pause; /* The number of Pause packet transmitted. */ 345 unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */ 346 unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */ 347 unsigned long tx_defer; /* The number of packets transmitted that is deferred. */ 348 unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */ 349 unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */ 350 unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */ 351 unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */ 352 unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */ 353 unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */ 354 unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */ 355 unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */ 356 unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */ 357 unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */ 358 unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */ 359 unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */ 360 unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */ 361 unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */ 362 unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */ 363 unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */ 364 unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */ 365 unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */ 366 }; 367 368 struct atl1c_hw { 369 u8 __iomem *hw_addr; /* inner register address */ 370 struct atl1c_adapter *adapter; 371 enum atl1c_nic_type nic_type; 372 enum atl1c_dma_order dma_order; 373 enum atl1c_dma_rcb rcb_value; 374 enum atl1c_dma_req_block dmar_block; 375 376 u16 device_id; 377 u16 vendor_id; 378 u16 subsystem_id; 379 u16 subsystem_vendor_id; 380 u8 revision_id; 381 u16 phy_id1; 382 u16 phy_id2; 383 384 u32 intr_mask; 385 386 u8 preamble_len; 387 u16 max_frame_size; 388 u16 min_frame_size; 389 390 enum atl1c_mac_speed mac_speed; 391 bool mac_duplex; 392 bool hibernate; 393 u16 media_type; 394 #define MEDIA_TYPE_AUTO_SENSOR 0 395 #define MEDIA_TYPE_100M_FULL 1 396 #define MEDIA_TYPE_100M_HALF 2 397 #define MEDIA_TYPE_10M_FULL 3 398 #define MEDIA_TYPE_10M_HALF 4 399 400 u16 autoneg_advertised; 401 u16 mii_autoneg_adv_reg; 402 u16 mii_1000t_ctrl_reg; 403 404 u16 tx_imt; /* TX Interrupt Moderator timer ( 2us resolution) */ 405 u16 rx_imt; /* RX Interrupt Moderator timer ( 2us resolution) */ 406 u16 ict; /* Interrupt Clear timer (2us resolution) */ 407 u16 ctrl_flags; 408 #define ATL1C_INTR_CLEAR_ON_READ 0x0001 409 #define ATL1C_INTR_MODRT_ENABLE 0x0002 410 #define ATL1C_CMB_ENABLE 0x0004 411 #define ATL1C_SMB_ENABLE 0x0010 412 #define ATL1C_TXQ_MODE_ENHANCE 0x0020 413 #define ATL1C_RX_IPV6_CHKSUM 0x0040 414 #define ATL1C_ASPM_L0S_SUPPORT 0x0080 415 #define ATL1C_ASPM_L1_SUPPORT 0x0100 416 #define ATL1C_ASPM_CTRL_MON 0x0200 417 #define ATL1C_HIB_DISABLE 0x0400 418 #define ATL1C_APS_MODE_ENABLE 0x0800 419 #define ATL1C_LINK_EXT_SYNC 0x1000 420 #define ATL1C_CLK_GATING_EN 0x2000 421 #define ATL1C_FPGA_VERSION 0x8000 422 u16 link_cap_flags; 423 #define ATL1C_LINK_CAP_1000M 0x0001 424 u32 smb_timer; 425 426 u16 rrd_thresh; /* Threshold of number of RRD produced to trigger 427 interrupt request */ 428 u16 tpd_thresh; 429 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */ 430 u8 rfd_burst; 431 u32 base_cpu; 432 u32 indirect_tab; 433 u8 mac_addr[ETH_ALEN]; 434 u8 perm_mac_addr[ETH_ALEN]; 435 436 bool phy_configured; 437 bool re_autoneg; 438 bool emi_ca; 439 bool msi_lnkpatch; /* link patch for specific platforms */ 440 }; 441 442 /* 443 * atl1c_ring_header represents a single, contiguous block of DMA space 444 * mapped for the three descriptor rings (tpd, rfd, rrd) described below 445 */ 446 struct atl1c_ring_header { 447 void *desc; /* virtual address */ 448 dma_addr_t dma; /* physical address*/ 449 unsigned int size; /* length in bytes */ 450 }; 451 452 /* 453 * atl1c_buffer is wrapper around a pointer to a socket buffer 454 * so a DMA handle can be stored along with the skb 455 */ 456 struct atl1c_buffer { 457 struct sk_buff *skb; /* socket buffer */ 458 u16 length; /* rx buffer length */ 459 u16 flags; /* information of buffer */ 460 #define ATL1C_BUFFER_FREE 0x0001 461 #define ATL1C_BUFFER_BUSY 0x0002 462 #define ATL1C_BUFFER_STATE_MASK 0x0003 463 464 #define ATL1C_PCIMAP_SINGLE 0x0004 465 #define ATL1C_PCIMAP_PAGE 0x0008 466 #define ATL1C_PCIMAP_TYPE_MASK 0x000C 467 468 #define ATL1C_PCIMAP_TODEVICE 0x0010 469 #define ATL1C_PCIMAP_FROMDEVICE 0x0020 470 #define ATL1C_PCIMAP_DIRECTION_MASK 0x0030 471 dma_addr_t dma; 472 }; 473 474 #define ATL1C_SET_BUFFER_STATE(buff, state) do { \ 475 ((buff)->flags) &= ~ATL1C_BUFFER_STATE_MASK; \ 476 ((buff)->flags) |= (state); \ 477 } while (0) 478 479 #define ATL1C_SET_PCIMAP_TYPE(buff, type, direction) do { \ 480 ((buff)->flags) &= ~ATL1C_PCIMAP_TYPE_MASK; \ 481 ((buff)->flags) |= (type); \ 482 ((buff)->flags) &= ~ATL1C_PCIMAP_DIRECTION_MASK; \ 483 ((buff)->flags) |= (direction); \ 484 } while (0) 485 486 /* transimit packet descriptor (tpd) ring */ 487 struct atl1c_tpd_ring { 488 void *desc; /* descriptor ring virtual address */ 489 dma_addr_t dma; /* descriptor ring physical address */ 490 u16 size; /* descriptor ring length in bytes */ 491 u16 count; /* number of descriptors in the ring */ 492 u16 next_to_use; /* this is protectd by adapter->tx_lock */ 493 atomic_t next_to_clean; 494 struct atl1c_buffer *buffer_info; 495 }; 496 497 /* receive free descriptor (rfd) ring */ 498 struct atl1c_rfd_ring { 499 void *desc; /* descriptor ring virtual address */ 500 dma_addr_t dma; /* descriptor ring physical address */ 501 u16 size; /* descriptor ring length in bytes */ 502 u16 count; /* number of descriptors in the ring */ 503 u16 next_to_use; 504 u16 next_to_clean; 505 struct atl1c_buffer *buffer_info; 506 }; 507 508 /* receive return descriptor (rrd) ring */ 509 struct atl1c_rrd_ring { 510 void *desc; /* descriptor ring virtual address */ 511 dma_addr_t dma; /* descriptor ring physical address */ 512 u16 size; /* descriptor ring length in bytes */ 513 u16 count; /* number of descriptors in the ring */ 514 u16 next_to_use; 515 u16 next_to_clean; 516 }; 517 518 /* board specific private data structure */ 519 struct atl1c_adapter { 520 struct net_device *netdev; 521 struct pci_dev *pdev; 522 struct napi_struct napi; 523 struct atl1c_hw hw; 524 struct atl1c_hw_stats hw_stats; 525 struct mii_if_info mii; /* MII interface info */ 526 u16 rx_buffer_len; 527 528 unsigned long flags; 529 #define __AT_TESTING 0x0001 530 #define __AT_RESETTING 0x0002 531 #define __AT_DOWN 0x0003 532 unsigned long work_event; 533 #define ATL1C_WORK_EVENT_RESET 0 534 #define ATL1C_WORK_EVENT_LINK_CHANGE 1 535 u32 msg_enable; 536 537 bool have_msi; 538 u32 wol; 539 u16 link_speed; 540 u16 link_duplex; 541 542 spinlock_t mdio_lock; 543 spinlock_t tx_lock; 544 atomic_t irq_sem; 545 546 struct work_struct common_task; 547 struct timer_list watchdog_timer; 548 struct timer_list phy_config_timer; 549 550 /* All Descriptor memory */ 551 struct atl1c_ring_header ring_header; 552 struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE]; 553 struct atl1c_rfd_ring rfd_ring; 554 struct atl1c_rrd_ring rrd_ring; 555 u32 bd_number; /* board number;*/ 556 }; 557 558 #define AT_WRITE_REG(a, reg, value) ( \ 559 writel((value), ((a)->hw_addr + reg))) 560 561 #define AT_WRITE_FLUSH(a) (\ 562 readl((a)->hw_addr)) 563 564 #define AT_READ_REG(a, reg, pdata) do { \ 565 if (unlikely((a)->hibernate)) { \ 566 readl((a)->hw_addr + reg); \ 567 *(u32 *)pdata = readl((a)->hw_addr + reg); \ 568 } else { \ 569 *(u32 *)pdata = readl((a)->hw_addr + reg); \ 570 } \ 571 } while (0) 572 573 #define AT_WRITE_REGB(a, reg, value) (\ 574 writeb((value), ((a)->hw_addr + reg))) 575 576 #define AT_READ_REGB(a, reg) (\ 577 readb((a)->hw_addr + reg)) 578 579 #define AT_WRITE_REGW(a, reg, value) (\ 580 writew((value), ((a)->hw_addr + reg))) 581 582 #define AT_READ_REGW(a, reg, pdata) do { \ 583 if (unlikely((a)->hibernate)) { \ 584 readw((a)->hw_addr + reg); \ 585 *(u16 *)pdata = readw((a)->hw_addr + reg); \ 586 } else { \ 587 *(u16 *)pdata = readw((a)->hw_addr + reg); \ 588 } \ 589 } while (0) 590 591 #define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \ 592 writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))) 593 594 #define AT_READ_REG_ARRAY(a, reg, offset) ( \ 595 readl(((a)->hw_addr + reg) + ((offset) << 2))) 596 597 extern char atl1c_driver_name[]; 598 extern char atl1c_driver_version[]; 599 600 extern void atl1c_reinit_locked(struct atl1c_adapter *adapter); 601 extern s32 atl1c_reset_hw(struct atl1c_hw *hw); 602 extern void atl1c_set_ethtool_ops(struct net_device *netdev); 603 #endif /* _ATL1C_H_ */ 604