1 /* 2 * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net> 3 * 4 * This file is free software: you may copy, redistribute and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation, either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This file is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 * This file incorporates work covered by the following copyright and 18 * permission notice: 19 * 20 * Copyright (c) 2012 Qualcomm Atheros, Inc. 21 * 22 * Permission to use, copy, modify, and/or distribute this software for any 23 * purpose with or without fee is hereby granted, provided that the above 24 * copyright notice and this permission notice appear in all copies. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 27 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 29 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 30 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 31 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 32 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 33 */ 34 35 #ifndef ALX_REG_H 36 #define ALX_REG_H 37 38 #define ALX_DEV_ID_AR8161 0x1091 39 #define ALX_DEV_ID_E2200 0xe091 40 #define ALX_DEV_ID_AR8162 0x1090 41 #define ALX_DEV_ID_AR8171 0x10A1 42 #define ALX_DEV_ID_AR8172 0x10A0 43 44 /* rev definition, 45 * bit(0): with xD support 46 * bit(1): with Card Reader function 47 * bit(7:2): real revision 48 */ 49 #define ALX_PCI_REVID_SHIFT 3 50 #define ALX_REV_A0 0 51 #define ALX_REV_A1 1 52 #define ALX_REV_B0 2 53 #define ALX_REV_C0 3 54 55 #define ALX_DEV_CTRL 0x0060 56 #define ALX_DEV_CTRL_MAXRRS_MIN 2 57 58 #define ALX_MSIX_MASK 0x0090 59 60 #define ALX_UE_SVRT 0x010C 61 #define ALX_UE_SVRT_FCPROTERR BIT(13) 62 #define ALX_UE_SVRT_DLPROTERR BIT(4) 63 64 /* eeprom & flash load register */ 65 #define ALX_EFLD 0x0204 66 #define ALX_EFLD_F_EXIST BIT(10) 67 #define ALX_EFLD_E_EXIST BIT(9) 68 #define ALX_EFLD_STAT BIT(5) 69 #define ALX_EFLD_START BIT(0) 70 71 /* eFuse load register */ 72 #define ALX_SLD 0x0218 73 #define ALX_SLD_STAT BIT(12) 74 #define ALX_SLD_START BIT(11) 75 #define ALX_SLD_MAX_TO 100 76 77 #define ALX_PDLL_TRNS1 0x1104 78 #define ALX_PDLL_TRNS1_D3PLLOFF_EN BIT(11) 79 80 #define ALX_PMCTRL 0x12F8 81 #define ALX_PMCTRL_HOTRST_WTEN BIT(31) 82 /* bit30: L0s/L1 controlled by MAC based on throughput(setting in 15A0) */ 83 #define ALX_PMCTRL_ASPM_FCEN BIT(30) 84 #define ALX_PMCTRL_SADLY_EN BIT(29) 85 #define ALX_PMCTRL_LCKDET_TIMER_MASK 0xF 86 #define ALX_PMCTRL_LCKDET_TIMER_SHIFT 24 87 #define ALX_PMCTRL_LCKDET_TIMER_DEF 0xC 88 /* bit[23:20] if pm_request_l1 time > @, then enter L0s not L1 */ 89 #define ALX_PMCTRL_L1REQ_TO_MASK 0xF 90 #define ALX_PMCTRL_L1REQ_TO_SHIFT 20 91 #define ALX_PMCTRL_L1REG_TO_DEF 0xF 92 #define ALX_PMCTRL_TXL1_AFTER_L0S BIT(19) 93 #define ALX_PMCTRL_L1_TIMER_MASK 0x7 94 #define ALX_PMCTRL_L1_TIMER_SHIFT 16 95 #define ALX_PMCTRL_L1_TIMER_16US 4 96 #define ALX_PMCTRL_RCVR_WT_1US BIT(15) 97 /* bit13: enable pcie clk switch in L1 state */ 98 #define ALX_PMCTRL_L1_CLKSW_EN BIT(13) 99 #define ALX_PMCTRL_L0S_EN BIT(12) 100 #define ALX_PMCTRL_RXL1_AFTER_L0S BIT(11) 101 #define ALX_PMCTRL_L1_BUFSRX_EN BIT(7) 102 /* bit6: power down serdes RX */ 103 #define ALX_PMCTRL_L1_SRDSRX_PWD BIT(6) 104 #define ALX_PMCTRL_L1_SRDSPLL_EN BIT(5) 105 #define ALX_PMCTRL_L1_SRDS_EN BIT(4) 106 #define ALX_PMCTRL_L1_EN BIT(3) 107 108 /*******************************************************/ 109 /* following registers are mapped only to memory space */ 110 /*******************************************************/ 111 112 #define ALX_MASTER 0x1400 113 /* bit12: 1:alwys select pclk from serdes, not sw to 25M */ 114 #define ALX_MASTER_PCLKSEL_SRDS BIT(12) 115 /* bit11: irq moduration for rx */ 116 #define ALX_MASTER_IRQMOD2_EN BIT(11) 117 /* bit10: irq moduration for tx/rx */ 118 #define ALX_MASTER_IRQMOD1_EN BIT(10) 119 #define ALX_MASTER_SYSALVTIMER_EN BIT(7) 120 #define ALX_MASTER_OOB_DIS BIT(6) 121 /* bit5: wakeup without pcie clk */ 122 #define ALX_MASTER_WAKEN_25M BIT(5) 123 /* bit0: MAC & DMA reset */ 124 #define ALX_MASTER_DMA_MAC_RST BIT(0) 125 #define ALX_DMA_MAC_RST_TO 50 126 127 #define ALX_IRQ_MODU_TIMER 0x1408 128 #define ALX_IRQ_MODU_TIMER1_MASK 0xFFFF 129 #define ALX_IRQ_MODU_TIMER1_SHIFT 0 130 131 #define ALX_PHY_CTRL 0x140C 132 #define ALX_PHY_CTRL_100AB_EN BIT(17) 133 /* bit14: affect MAC & PHY, go to low power sts */ 134 #define ALX_PHY_CTRL_POWER_DOWN BIT(14) 135 /* bit13: 1:pll always ON, 0:can switch in lpw */ 136 #define ALX_PHY_CTRL_PLL_ON BIT(13) 137 #define ALX_PHY_CTRL_RST_ANALOG BIT(12) 138 #define ALX_PHY_CTRL_HIB_PULSE BIT(11) 139 #define ALX_PHY_CTRL_HIB_EN BIT(10) 140 #define ALX_PHY_CTRL_IDDQ BIT(7) 141 #define ALX_PHY_CTRL_GATE_25M BIT(5) 142 #define ALX_PHY_CTRL_LED_MODE BIT(2) 143 /* bit0: out of dsp RST state */ 144 #define ALX_PHY_CTRL_DSPRST_OUT BIT(0) 145 #define ALX_PHY_CTRL_DSPRST_TO 80 146 #define ALX_PHY_CTRL_CLS (ALX_PHY_CTRL_LED_MODE | \ 147 ALX_PHY_CTRL_100AB_EN | \ 148 ALX_PHY_CTRL_PLL_ON) 149 150 #define ALX_MAC_STS 0x1410 151 #define ALX_MAC_STS_TXQ_BUSY BIT(3) 152 #define ALX_MAC_STS_RXQ_BUSY BIT(2) 153 #define ALX_MAC_STS_TXMAC_BUSY BIT(1) 154 #define ALX_MAC_STS_RXMAC_BUSY BIT(0) 155 #define ALX_MAC_STS_IDLE (ALX_MAC_STS_TXQ_BUSY | \ 156 ALX_MAC_STS_RXQ_BUSY | \ 157 ALX_MAC_STS_TXMAC_BUSY | \ 158 ALX_MAC_STS_RXMAC_BUSY) 159 160 #define ALX_MDIO 0x1414 161 #define ALX_MDIO_MODE_EXT BIT(30) 162 #define ALX_MDIO_BUSY BIT(27) 163 #define ALX_MDIO_CLK_SEL_MASK 0x7 164 #define ALX_MDIO_CLK_SEL_SHIFT 24 165 #define ALX_MDIO_CLK_SEL_25MD4 0 166 #define ALX_MDIO_CLK_SEL_25MD128 7 167 #define ALX_MDIO_START BIT(23) 168 #define ALX_MDIO_SPRES_PRMBL BIT(22) 169 /* bit21: 1:read,0:write */ 170 #define ALX_MDIO_OP_READ BIT(21) 171 #define ALX_MDIO_REG_MASK 0x1F 172 #define ALX_MDIO_REG_SHIFT 16 173 #define ALX_MDIO_DATA_MASK 0xFFFF 174 #define ALX_MDIO_DATA_SHIFT 0 175 #define ALX_MDIO_MAX_AC_TO 120 176 177 #define ALX_MDIO_EXTN 0x1448 178 #define ALX_MDIO_EXTN_DEVAD_MASK 0x1F 179 #define ALX_MDIO_EXTN_DEVAD_SHIFT 16 180 #define ALX_MDIO_EXTN_REG_MASK 0xFFFF 181 #define ALX_MDIO_EXTN_REG_SHIFT 0 182 183 #define ALX_SERDES 0x1424 184 #define ALX_SERDES_PHYCLK_SLWDWN BIT(18) 185 #define ALX_SERDES_MACCLK_SLWDWN BIT(17) 186 187 #define ALX_LPI_CTRL 0x1440 188 #define ALX_LPI_CTRL_EN BIT(0) 189 190 /* for B0+, bit[13..] for C0+ */ 191 #define ALX_HRTBT_EXT_CTRL 0x1AD0 192 #define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_MASK 0x3F 193 #define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_SHIFT 24 194 #define L1F_HRTBT_EXT_CTRL_SWOI_STARTUP_PKT_EN BIT(23) 195 #define L1F_HRTBT_EXT_CTRL_IOAC_2_FRAGMENTED BIT(22) 196 #define L1F_HRTBT_EXT_CTRL_IOAC_1_FRAGMENTED BIT(21) 197 #define L1F_HRTBT_EXT_CTRL_IOAC_1_KEEPALIVE_EN BIT(20) 198 #define L1F_HRTBT_EXT_CTRL_IOAC_1_HAS_VLAN BIT(19) 199 #define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_8023 BIT(18) 200 #define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_IPV6 BIT(17) 201 #define L1F_HRTBT_EXT_CTRL_IOAC_2_KEEPALIVE_EN BIT(16) 202 #define L1F_HRTBT_EXT_CTRL_IOAC_2_HAS_VLAN BIT(15) 203 #define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_8023 BIT(14) 204 #define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_IPV6 BIT(13) 205 #define ALX_HRTBT_EXT_CTRL_NS_EN BIT(12) 206 #define ALX_HRTBT_EXT_CTRL_FRAG_LEN_MASK 0xFF 207 #define ALX_HRTBT_EXT_CTRL_FRAG_LEN_SHIFT 4 208 #define ALX_HRTBT_EXT_CTRL_IS_8023 BIT(3) 209 #define ALX_HRTBT_EXT_CTRL_IS_IPV6 BIT(2) 210 #define ALX_HRTBT_EXT_CTRL_WAKEUP_EN BIT(1) 211 #define ALX_HRTBT_EXT_CTRL_ARP_EN BIT(0) 212 213 #define ALX_HRTBT_REM_IPV4_ADDR 0x1AD4 214 #define ALX_HRTBT_HOST_IPV4_ADDR 0x1478 215 #define ALX_HRTBT_REM_IPV6_ADDR3 0x1AD8 216 #define ALX_HRTBT_REM_IPV6_ADDR2 0x1ADC 217 #define ALX_HRTBT_REM_IPV6_ADDR1 0x1AE0 218 #define ALX_HRTBT_REM_IPV6_ADDR0 0x1AE4 219 220 /* 1B8C ~ 1B94 for C0+ */ 221 #define ALX_SWOI_ACER_CTRL 0x1B8C 222 #define ALX_SWOI_ORIG_ACK_NAK_EN BIT(20) 223 #define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_MASK 0XFF 224 #define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_SHIFT 12 225 #define ALX_SWOI_ORIG_ACK_ADDR_MASK 0XFFF 226 #define ALX_SWOI_ORIG_ACK_ADDR_SHIFT 0 227 228 #define ALX_SWOI_IOAC_CTRL_2 0x1B90 229 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_MASK 0xFF 230 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_SHIFT 24 231 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_MASK 0xFFF 232 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_SHIFT 12 233 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_MASK 0xFFF 234 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_SHIFT 0 235 236 #define ALX_SWOI_IOAC_CTRL_3 0x1B94 237 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_MASK 0xFF 238 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_SHIFT 24 239 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_MASK 0xFFF 240 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_SHIFT 12 241 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_MASK 0xFFF 242 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_SHIFT 0 243 244 /* for B0 */ 245 #define ALX_IDLE_DECISN_TIMER 0x1474 246 /* 1ms */ 247 #define ALX_IDLE_DECISN_TIMER_DEF 0x400 248 249 #define ALX_MAC_CTRL 0x1480 250 #define ALX_MAC_CTRL_FAST_PAUSE BIT(31) 251 #define ALX_MAC_CTRL_WOLSPED_SWEN BIT(30) 252 /* bit29: 1:legacy(hi5b), 0:marvl(lo5b)*/ 253 #define ALX_MAC_CTRL_MHASH_ALG_HI5B BIT(29) 254 #define ALX_MAC_CTRL_BRD_EN BIT(26) 255 #define ALX_MAC_CTRL_MULTIALL_EN BIT(25) 256 #define ALX_MAC_CTRL_SPEED_MASK 0x3 257 #define ALX_MAC_CTRL_SPEED_SHIFT 20 258 #define ALX_MAC_CTRL_SPEED_10_100 1 259 #define ALX_MAC_CTRL_SPEED_1000 2 260 #define ALX_MAC_CTRL_PROMISC_EN BIT(15) 261 #define ALX_MAC_CTRL_VLANSTRIP BIT(14) 262 #define ALX_MAC_CTRL_PRMBLEN_MASK 0xF 263 #define ALX_MAC_CTRL_PRMBLEN_SHIFT 10 264 #define ALX_MAC_CTRL_PCRCE BIT(7) 265 #define ALX_MAC_CTRL_CRCE BIT(6) 266 #define ALX_MAC_CTRL_FULLD BIT(5) 267 #define ALX_MAC_CTRL_RXFC_EN BIT(3) 268 #define ALX_MAC_CTRL_TXFC_EN BIT(2) 269 #define ALX_MAC_CTRL_RX_EN BIT(1) 270 #define ALX_MAC_CTRL_TX_EN BIT(0) 271 272 #define ALX_STAD0 0x1488 273 #define ALX_STAD1 0x148C 274 275 #define ALX_HASH_TBL0 0x1490 276 #define ALX_HASH_TBL1 0x1494 277 278 #define ALX_MTU 0x149C 279 #define ALX_MTU_JUMBO_TH 1514 280 #define ALX_MTU_STD_ALGN 1536 281 282 #define ALX_SRAM5 0x1524 283 #define ALX_SRAM_RXF_LEN_MASK 0xFFF 284 #define ALX_SRAM_RXF_LEN_SHIFT 0 285 #define ALX_SRAM_RXF_LEN_8K (8*1024) 286 287 #define ALX_SRAM9 0x1534 288 #define ALX_SRAM_LOAD_PTR BIT(0) 289 290 #define ALX_RX_BASE_ADDR_HI 0x1540 291 292 #define ALX_TX_BASE_ADDR_HI 0x1544 293 294 #define ALX_RFD_ADDR_LO 0x1550 295 #define ALX_RFD_RING_SZ 0x1560 296 #define ALX_RFD_BUF_SZ 0x1564 297 298 #define ALX_RRD_ADDR_LO 0x1568 299 #define ALX_RRD_RING_SZ 0x1578 300 301 /* pri3: highest, pri0: lowest */ 302 #define ALX_TPD_PRI3_ADDR_LO 0x14E4 303 #define ALX_TPD_PRI2_ADDR_LO 0x14E0 304 #define ALX_TPD_PRI1_ADDR_LO 0x157C 305 #define ALX_TPD_PRI0_ADDR_LO 0x1580 306 307 /* producer index is 16bit */ 308 #define ALX_TPD_PRI3_PIDX 0x1618 309 #define ALX_TPD_PRI2_PIDX 0x161A 310 #define ALX_TPD_PRI1_PIDX 0x15F0 311 #define ALX_TPD_PRI0_PIDX 0x15F2 312 313 /* consumer index is 16bit */ 314 #define ALX_TPD_PRI3_CIDX 0x161C 315 #define ALX_TPD_PRI2_CIDX 0x161E 316 #define ALX_TPD_PRI1_CIDX 0x15F4 317 #define ALX_TPD_PRI0_CIDX 0x15F6 318 319 #define ALX_TPD_RING_SZ 0x1584 320 321 #define ALX_TXQ0 0x1590 322 #define ALX_TXQ0_TXF_BURST_PREF_MASK 0xFFFF 323 #define ALX_TXQ0_TXF_BURST_PREF_SHIFT 16 324 #define ALX_TXQ_TXF_BURST_PREF_DEF 0x200 325 #define ALX_TXQ0_LSO_8023_EN BIT(7) 326 #define ALX_TXQ0_MODE_ENHANCE BIT(6) 327 #define ALX_TXQ0_EN BIT(5) 328 #define ALX_TXQ0_SUPT_IPOPT BIT(4) 329 #define ALX_TXQ0_TPD_BURSTPREF_MASK 0xF 330 #define ALX_TXQ0_TPD_BURSTPREF_SHIFT 0 331 #define ALX_TXQ_TPD_BURSTPREF_DEF 5 332 333 #define ALX_TXQ1 0x1594 334 /* bit11: drop large packet, len > (rfd buf) */ 335 #define ALX_TXQ1_ERRLGPKT_DROP_EN BIT(11) 336 #define ALX_TXQ1_JUMBO_TSO_TH (7*1024) 337 338 #define ALX_RXQ0 0x15A0 339 #define ALX_RXQ0_EN BIT(31) 340 #define ALX_RXQ0_RSS_HASH_EN BIT(29) 341 #define ALX_RXQ0_RSS_MODE_MASK 0x3 342 #define ALX_RXQ0_RSS_MODE_SHIFT 26 343 #define ALX_RXQ0_RSS_MODE_DIS 0 344 #define ALX_RXQ0_RSS_MODE_MQMI 3 345 #define ALX_RXQ0_NUM_RFD_PREF_MASK 0x3F 346 #define ALX_RXQ0_NUM_RFD_PREF_SHIFT 20 347 #define ALX_RXQ0_NUM_RFD_PREF_DEF 8 348 #define ALX_RXQ0_IDT_TBL_SIZE_MASK 0x1FF 349 #define ALX_RXQ0_IDT_TBL_SIZE_SHIFT 8 350 #define ALX_RXQ0_IDT_TBL_SIZE_DEF 0x100 351 #define ALX_RXQ0_IDT_TBL_SIZE_NORMAL 128 352 #define ALX_RXQ0_IPV6_PARSE_EN BIT(7) 353 #define ALX_RXQ0_RSS_HSTYP_MASK 0xF 354 #define ALX_RXQ0_RSS_HSTYP_SHIFT 2 355 #define ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN BIT(5) 356 #define ALX_RXQ0_RSS_HSTYP_IPV6_EN BIT(4) 357 #define ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN BIT(3) 358 #define ALX_RXQ0_RSS_HSTYP_IPV4_EN BIT(2) 359 #define ALX_RXQ0_RSS_HSTYP_ALL (ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN | \ 360 ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN | \ 361 ALX_RXQ0_RSS_HSTYP_IPV6_EN | \ 362 ALX_RXQ0_RSS_HSTYP_IPV4_EN) 363 #define ALX_RXQ0_ASPM_THRESH_MASK 0x3 364 #define ALX_RXQ0_ASPM_THRESH_SHIFT 0 365 #define ALX_RXQ0_ASPM_THRESH_100M 3 366 367 #define ALX_RXQ2 0x15A8 368 #define ALX_RXQ2_RXF_XOFF_THRESH_MASK 0xFFF 369 #define ALX_RXQ2_RXF_XOFF_THRESH_SHIFT 16 370 #define ALX_RXQ2_RXF_XON_THRESH_MASK 0xFFF 371 #define ALX_RXQ2_RXF_XON_THRESH_SHIFT 0 372 /* Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) + 373 * rx-packet(1522) + delay-of-link(64) 374 * = 3212. 375 */ 376 #define ALX_RXQ2_RXF_FLOW_CTRL_RSVD 3212 377 378 #define ALX_DMA 0x15C0 379 #define ALX_DMA_RCHNL_SEL_MASK 0x3 380 #define ALX_DMA_RCHNL_SEL_SHIFT 26 381 #define ALX_DMA_WDLY_CNT_MASK 0xF 382 #define ALX_DMA_WDLY_CNT_SHIFT 16 383 #define ALX_DMA_WDLY_CNT_DEF 4 384 #define ALX_DMA_RDLY_CNT_MASK 0x1F 385 #define ALX_DMA_RDLY_CNT_SHIFT 11 386 #define ALX_DMA_RDLY_CNT_DEF 15 387 /* bit10: 0:tpd with pri, 1: data */ 388 #define ALX_DMA_RREQ_PRI_DATA BIT(10) 389 #define ALX_DMA_RREQ_BLEN_MASK 0x7 390 #define ALX_DMA_RREQ_BLEN_SHIFT 4 391 #define ALX_DMA_RORDER_MODE_MASK 0x7 392 #define ALX_DMA_RORDER_MODE_SHIFT 0 393 #define ALX_DMA_RORDER_MODE_OUT 4 394 395 #define ALX_WOL0 0x14A0 396 #define ALX_WOL0_PME_LINK BIT(5) 397 #define ALX_WOL0_LINK_EN BIT(4) 398 #define ALX_WOL0_PME_MAGIC_EN BIT(3) 399 #define ALX_WOL0_MAGIC_EN BIT(2) 400 401 #define ALX_RFD_PIDX 0x15E0 402 403 #define ALX_RFD_CIDX 0x15F8 404 405 /* MIB */ 406 #define ALX_MIB_BASE 0x1700 407 408 #define ALX_MIB_RX_OK (ALX_MIB_BASE + 0) 409 #define ALX_MIB_RX_BCAST (ALX_MIB_BASE + 4) 410 #define ALX_MIB_RX_MCAST (ALX_MIB_BASE + 8) 411 #define ALX_MIB_RX_PAUSE (ALX_MIB_BASE + 12) 412 #define ALX_MIB_RX_CTRL (ALX_MIB_BASE + 16) 413 #define ALX_MIB_RX_FCS_ERR (ALX_MIB_BASE + 20) 414 #define ALX_MIB_RX_LEN_ERR (ALX_MIB_BASE + 24) 415 #define ALX_MIB_RX_BYTE_CNT (ALX_MIB_BASE + 28) 416 #define ALX_MIB_RX_RUNT (ALX_MIB_BASE + 32) 417 #define ALX_MIB_RX_FRAG (ALX_MIB_BASE + 36) 418 #define ALX_MIB_RX_SZ_64B (ALX_MIB_BASE + 40) 419 #define ALX_MIB_RX_SZ_127B (ALX_MIB_BASE + 44) 420 #define ALX_MIB_RX_SZ_255B (ALX_MIB_BASE + 48) 421 #define ALX_MIB_RX_SZ_511B (ALX_MIB_BASE + 52) 422 #define ALX_MIB_RX_SZ_1023B (ALX_MIB_BASE + 56) 423 #define ALX_MIB_RX_SZ_1518B (ALX_MIB_BASE + 60) 424 #define ALX_MIB_RX_SZ_MAX (ALX_MIB_BASE + 64) 425 #define ALX_MIB_RX_OV_SZ (ALX_MIB_BASE + 68) 426 #define ALX_MIB_RX_OV_RXF (ALX_MIB_BASE + 72) 427 #define ALX_MIB_RX_OV_RRD (ALX_MIB_BASE + 76) 428 #define ALX_MIB_RX_ALIGN_ERR (ALX_MIB_BASE + 80) 429 #define ALX_MIB_RX_BCCNT (ALX_MIB_BASE + 84) 430 #define ALX_MIB_RX_MCCNT (ALX_MIB_BASE + 88) 431 #define ALX_MIB_RX_ERRADDR (ALX_MIB_BASE + 92) 432 433 #define ALX_MIB_TX_OK (ALX_MIB_BASE + 96) 434 #define ALX_MIB_TX_BCAST (ALX_MIB_BASE + 100) 435 #define ALX_MIB_TX_MCAST (ALX_MIB_BASE + 104) 436 #define ALX_MIB_TX_PAUSE (ALX_MIB_BASE + 108) 437 #define ALX_MIB_TX_EXC_DEFER (ALX_MIB_BASE + 112) 438 #define ALX_MIB_TX_CTRL (ALX_MIB_BASE + 116) 439 #define ALX_MIB_TX_DEFER (ALX_MIB_BASE + 120) 440 #define ALX_MIB_TX_BYTE_CNT (ALX_MIB_BASE + 124) 441 #define ALX_MIB_TX_SZ_64B (ALX_MIB_BASE + 128) 442 #define ALX_MIB_TX_SZ_127B (ALX_MIB_BASE + 132) 443 #define ALX_MIB_TX_SZ_255B (ALX_MIB_BASE + 136) 444 #define ALX_MIB_TX_SZ_511B (ALX_MIB_BASE + 140) 445 #define ALX_MIB_TX_SZ_1023B (ALX_MIB_BASE + 144) 446 #define ALX_MIB_TX_SZ_1518B (ALX_MIB_BASE + 148) 447 #define ALX_MIB_TX_SZ_MAX (ALX_MIB_BASE + 152) 448 #define ALX_MIB_TX_SINGLE_COL (ALX_MIB_BASE + 156) 449 #define ALX_MIB_TX_MULTI_COL (ALX_MIB_BASE + 160) 450 #define ALX_MIB_TX_LATE_COL (ALX_MIB_BASE + 164) 451 #define ALX_MIB_TX_ABORT_COL (ALX_MIB_BASE + 168) 452 #define ALX_MIB_TX_UNDERRUN (ALX_MIB_BASE + 172) 453 #define ALX_MIB_TX_TRD_EOP (ALX_MIB_BASE + 176) 454 #define ALX_MIB_TX_LEN_ERR (ALX_MIB_BASE + 180) 455 #define ALX_MIB_TX_TRUNC (ALX_MIB_BASE + 184) 456 #define ALX_MIB_TX_BCCNT (ALX_MIB_BASE + 188) 457 #define ALX_MIB_TX_MCCNT (ALX_MIB_BASE + 192) 458 #define ALX_MIB_UPDATE (ALX_MIB_BASE + 196) 459 460 461 #define ALX_ISR 0x1600 462 #define ALX_ISR_DIS BIT(31) 463 #define ALX_ISR_RX_Q7 BIT(30) 464 #define ALX_ISR_RX_Q6 BIT(29) 465 #define ALX_ISR_RX_Q5 BIT(28) 466 #define ALX_ISR_RX_Q4 BIT(27) 467 #define ALX_ISR_PCIE_LNKDOWN BIT(26) 468 #define ALX_ISR_RX_Q3 BIT(19) 469 #define ALX_ISR_RX_Q2 BIT(18) 470 #define ALX_ISR_RX_Q1 BIT(17) 471 #define ALX_ISR_RX_Q0 BIT(16) 472 #define ALX_ISR_TX_Q0 BIT(15) 473 #define ALX_ISR_PHY BIT(12) 474 #define ALX_ISR_DMAW BIT(10) 475 #define ALX_ISR_DMAR BIT(9) 476 #define ALX_ISR_TXF_UR BIT(8) 477 #define ALX_ISR_TX_Q3 BIT(7) 478 #define ALX_ISR_TX_Q2 BIT(6) 479 #define ALX_ISR_TX_Q1 BIT(5) 480 #define ALX_ISR_RFD_UR BIT(4) 481 #define ALX_ISR_RXF_OV BIT(3) 482 #define ALX_ISR_MANU BIT(2) 483 #define ALX_ISR_TIMER BIT(1) 484 #define ALX_ISR_SMB BIT(0) 485 486 #define ALX_IMR 0x1604 487 488 /* re-send assert msg if SW no response */ 489 #define ALX_INT_RETRIG 0x1608 490 /* 40ms */ 491 #define ALX_INT_RETRIG_TO 20000 492 493 #define ALX_SMB_TIMER 0x15C4 494 495 #define ALX_TINT_TPD_THRSHLD 0x15C8 496 497 #define ALX_TINT_TIMER 0x15CC 498 499 #define ALX_CLK_GATE 0x1814 500 #define ALX_CLK_GATE_RXMAC BIT(5) 501 #define ALX_CLK_GATE_TXMAC BIT(4) 502 #define ALX_CLK_GATE_RXQ BIT(3) 503 #define ALX_CLK_GATE_TXQ BIT(2) 504 #define ALX_CLK_GATE_DMAR BIT(1) 505 #define ALX_CLK_GATE_DMAW BIT(0) 506 #define ALX_CLK_GATE_ALL (ALX_CLK_GATE_RXMAC | \ 507 ALX_CLK_GATE_TXMAC | \ 508 ALX_CLK_GATE_RXQ | \ 509 ALX_CLK_GATE_TXQ | \ 510 ALX_CLK_GATE_DMAR | \ 511 ALX_CLK_GATE_DMAW) 512 513 /* interop between drivers */ 514 #define ALX_DRV 0x1804 515 #define ALX_DRV_PHY_AUTO BIT(28) 516 #define ALX_DRV_PHY_1000 BIT(27) 517 #define ALX_DRV_PHY_100 BIT(26) 518 #define ALX_DRV_PHY_10 BIT(25) 519 #define ALX_DRV_PHY_DUPLEX BIT(24) 520 /* bit23: adv Pause */ 521 #define ALX_DRV_PHY_PAUSE BIT(23) 522 /* bit22: adv Asym Pause */ 523 #define ALX_DRV_PHY_MASK 0xFF 524 #define ALX_DRV_PHY_SHIFT 21 525 #define ALX_DRV_PHY_UNKNOWN 0 526 527 /* flag of phy inited */ 528 #define ALX_PHY_INITED 0x003F 529 530 /* reg 1830 ~ 186C for C0+, 16 bit map patterns and wake packet detection */ 531 #define ALX_WOL_CTRL2 0x1830 532 #define ALX_WOL_CTRL2_DATA_STORE BIT(3) 533 #define ALX_WOL_CTRL2_PTRN_EVT BIT(2) 534 #define ALX_WOL_CTRL2_PME_PTRN_EN BIT(1) 535 #define ALX_WOL_CTRL2_PTRN_EN BIT(0) 536 537 #define ALX_WOL_CTRL3 0x1834 538 #define ALX_WOL_CTRL3_PTRN_ADDR_MASK 0xFFFFF 539 #define ALX_WOL_CTRL3_PTRN_ADDR_SHIFT 0 540 541 #define ALX_WOL_CTRL4 0x1838 542 #define ALX_WOL_CTRL4_PT15_MATCH BIT(31) 543 #define ALX_WOL_CTRL4_PT14_MATCH BIT(30) 544 #define ALX_WOL_CTRL4_PT13_MATCH BIT(29) 545 #define ALX_WOL_CTRL4_PT12_MATCH BIT(28) 546 #define ALX_WOL_CTRL4_PT11_MATCH BIT(27) 547 #define ALX_WOL_CTRL4_PT10_MATCH BIT(26) 548 #define ALX_WOL_CTRL4_PT9_MATCH BIT(25) 549 #define ALX_WOL_CTRL4_PT8_MATCH BIT(24) 550 #define ALX_WOL_CTRL4_PT7_MATCH BIT(23) 551 #define ALX_WOL_CTRL4_PT6_MATCH BIT(22) 552 #define ALX_WOL_CTRL4_PT5_MATCH BIT(21) 553 #define ALX_WOL_CTRL4_PT4_MATCH BIT(20) 554 #define ALX_WOL_CTRL4_PT3_MATCH BIT(19) 555 #define ALX_WOL_CTRL4_PT2_MATCH BIT(18) 556 #define ALX_WOL_CTRL4_PT1_MATCH BIT(17) 557 #define ALX_WOL_CTRL4_PT0_MATCH BIT(16) 558 #define ALX_WOL_CTRL4_PT15_EN BIT(15) 559 #define ALX_WOL_CTRL4_PT14_EN BIT(14) 560 #define ALX_WOL_CTRL4_PT13_EN BIT(13) 561 #define ALX_WOL_CTRL4_PT12_EN BIT(12) 562 #define ALX_WOL_CTRL4_PT11_EN BIT(11) 563 #define ALX_WOL_CTRL4_PT10_EN BIT(10) 564 #define ALX_WOL_CTRL4_PT9_EN BIT(9) 565 #define ALX_WOL_CTRL4_PT8_EN BIT(8) 566 #define ALX_WOL_CTRL4_PT7_EN BIT(7) 567 #define ALX_WOL_CTRL4_PT6_EN BIT(6) 568 #define ALX_WOL_CTRL4_PT5_EN BIT(5) 569 #define ALX_WOL_CTRL4_PT4_EN BIT(4) 570 #define ALX_WOL_CTRL4_PT3_EN BIT(3) 571 #define ALX_WOL_CTRL4_PT2_EN BIT(2) 572 #define ALX_WOL_CTRL4_PT1_EN BIT(1) 573 #define ALX_WOL_CTRL4_PT0_EN BIT(0) 574 575 #define ALX_WOL_CTRL5 0x183C 576 #define ALX_WOL_CTRL5_PT3_LEN_MASK 0xFF 577 #define ALX_WOL_CTRL5_PT3_LEN_SHIFT 24 578 #define ALX_WOL_CTRL5_PT2_LEN_MASK 0xFF 579 #define ALX_WOL_CTRL5_PT2_LEN_SHIFT 16 580 #define ALX_WOL_CTRL5_PT1_LEN_MASK 0xFF 581 #define ALX_WOL_CTRL5_PT1_LEN_SHIFT 8 582 #define ALX_WOL_CTRL5_PT0_LEN_MASK 0xFF 583 #define ALX_WOL_CTRL5_PT0_LEN_SHIFT 0 584 585 #define ALX_WOL_CTRL6 0x1840 586 #define ALX_WOL_CTRL5_PT7_LEN_MASK 0xFF 587 #define ALX_WOL_CTRL5_PT7_LEN_SHIFT 24 588 #define ALX_WOL_CTRL5_PT6_LEN_MASK 0xFF 589 #define ALX_WOL_CTRL5_PT6_LEN_SHIFT 16 590 #define ALX_WOL_CTRL5_PT5_LEN_MASK 0xFF 591 #define ALX_WOL_CTRL5_PT5_LEN_SHIFT 8 592 #define ALX_WOL_CTRL5_PT4_LEN_MASK 0xFF 593 #define ALX_WOL_CTRL5_PT4_LEN_SHIFT 0 594 595 #define ALX_WOL_CTRL7 0x1844 596 #define ALX_WOL_CTRL5_PT11_LEN_MASK 0xFF 597 #define ALX_WOL_CTRL5_PT11_LEN_SHIFT 24 598 #define ALX_WOL_CTRL5_PT10_LEN_MASK 0xFF 599 #define ALX_WOL_CTRL5_PT10_LEN_SHIFT 16 600 #define ALX_WOL_CTRL5_PT9_LEN_MASK 0xFF 601 #define ALX_WOL_CTRL5_PT9_LEN_SHIFT 8 602 #define ALX_WOL_CTRL5_PT8_LEN_MASK 0xFF 603 #define ALX_WOL_CTRL5_PT8_LEN_SHIFT 0 604 605 #define ALX_WOL_CTRL8 0x1848 606 #define ALX_WOL_CTRL5_PT15_LEN_MASK 0xFF 607 #define ALX_WOL_CTRL5_PT15_LEN_SHIFT 24 608 #define ALX_WOL_CTRL5_PT14_LEN_MASK 0xFF 609 #define ALX_WOL_CTRL5_PT14_LEN_SHIFT 16 610 #define ALX_WOL_CTRL5_PT13_LEN_MASK 0xFF 611 #define ALX_WOL_CTRL5_PT13_LEN_SHIFT 8 612 #define ALX_WOL_CTRL5_PT12_LEN_MASK 0xFF 613 #define ALX_WOL_CTRL5_PT12_LEN_SHIFT 0 614 615 #define ALX_ACER_FIXED_PTN0 0x1850 616 #define ALX_ACER_FIXED_PTN0_MASK 0xFFFFFFFF 617 #define ALX_ACER_FIXED_PTN0_SHIFT 0 618 619 #define ALX_ACER_FIXED_PTN1 0x1854 620 #define ALX_ACER_FIXED_PTN1_MASK 0xFFFF 621 #define ALX_ACER_FIXED_PTN1_SHIFT 0 622 623 #define ALX_ACER_RANDOM_NUM0 0x1858 624 #define ALX_ACER_RANDOM_NUM0_MASK 0xFFFFFFFF 625 #define ALX_ACER_RANDOM_NUM0_SHIFT 0 626 627 #define ALX_ACER_RANDOM_NUM1 0x185C 628 #define ALX_ACER_RANDOM_NUM1_MASK 0xFFFFFFFF 629 #define ALX_ACER_RANDOM_NUM1_SHIFT 0 630 631 #define ALX_ACER_RANDOM_NUM2 0x1860 632 #define ALX_ACER_RANDOM_NUM2_MASK 0xFFFFFFFF 633 #define ALX_ACER_RANDOM_NUM2_SHIFT 0 634 635 #define ALX_ACER_RANDOM_NUM3 0x1864 636 #define ALX_ACER_RANDOM_NUM3_MASK 0xFFFFFFFF 637 #define ALX_ACER_RANDOM_NUM3_SHIFT 0 638 639 #define ALX_ACER_MAGIC 0x1868 640 #define ALX_ACER_MAGIC_EN BIT(31) 641 #define ALX_ACER_MAGIC_PME_EN BIT(30) 642 #define ALX_ACER_MAGIC_MATCH BIT(29) 643 #define ALX_ACER_MAGIC_FF_CHECK BIT(10) 644 #define ALX_ACER_MAGIC_RAN_LEN_MASK 0x1F 645 #define ALX_ACER_MAGIC_RAN_LEN_SHIFT 5 646 #define ALX_ACER_MAGIC_FIX_LEN_MASK 0x1F 647 #define ALX_ACER_MAGIC_FIX_LEN_SHIFT 0 648 649 #define ALX_ACER_TIMER 0x186C 650 #define ALX_ACER_TIMER_EN BIT(31) 651 #define ALX_ACER_TIMER_PME_EN BIT(30) 652 #define ALX_ACER_TIMER_MATCH BIT(29) 653 #define ALX_ACER_TIMER_THRES_MASK 0x1FFFF 654 #define ALX_ACER_TIMER_THRES_SHIFT 0 655 #define ALX_ACER_TIMER_THRES_DEF 1 656 657 /* RSS definitions */ 658 #define ALX_RSS_KEY0 0x14B0 659 #define ALX_RSS_KEY1 0x14B4 660 #define ALX_RSS_KEY2 0x14B8 661 #define ALX_RSS_KEY3 0x14BC 662 #define ALX_RSS_KEY4 0x14C0 663 #define ALX_RSS_KEY5 0x14C4 664 #define ALX_RSS_KEY6 0x14C8 665 #define ALX_RSS_KEY7 0x14CC 666 #define ALX_RSS_KEY8 0x14D0 667 #define ALX_RSS_KEY9 0x14D4 668 669 #define ALX_RSS_IDT_TBL0 0x1B00 670 671 #define ALX_MSI_MAP_TBL1 0x15D0 672 #define ALX_MSI_MAP_TBL1_TXQ1_SHIFT 20 673 #define ALX_MSI_MAP_TBL1_TXQ0_SHIFT 16 674 #define ALX_MSI_MAP_TBL1_RXQ3_SHIFT 12 675 #define ALX_MSI_MAP_TBL1_RXQ2_SHIFT 8 676 #define ALX_MSI_MAP_TBL1_RXQ1_SHIFT 4 677 #define ALX_MSI_MAP_TBL1_RXQ0_SHIFT 0 678 679 #define ALX_MSI_MAP_TBL2 0x15D8 680 #define ALX_MSI_MAP_TBL2_TXQ3_SHIFT 20 681 #define ALX_MSI_MAP_TBL2_TXQ2_SHIFT 16 682 #define ALX_MSI_MAP_TBL2_RXQ7_SHIFT 12 683 #define ALX_MSI_MAP_TBL2_RXQ6_SHIFT 8 684 #define ALX_MSI_MAP_TBL2_RXQ5_SHIFT 4 685 #define ALX_MSI_MAP_TBL2_RXQ4_SHIFT 0 686 687 #define ALX_MSI_ID_MAP 0x15D4 688 689 #define ALX_MSI_RETRANS_TIMER 0x1920 690 /* bit16: 1:line,0:standard */ 691 #define ALX_MSI_MASK_SEL_LINE BIT(16) 692 #define ALX_MSI_RETRANS_TM_MASK 0xFFFF 693 #define ALX_MSI_RETRANS_TM_SHIFT 0 694 695 /* CR DMA ctrl */ 696 697 /* TX QoS */ 698 #define ALX_WRR 0x1938 699 #define ALX_WRR_PRI_MASK 0x3 700 #define ALX_WRR_PRI_SHIFT 29 701 #define ALX_WRR_PRI_RESTRICT_NONE 3 702 #define ALX_WRR_PRI3_MASK 0x1F 703 #define ALX_WRR_PRI3_SHIFT 24 704 #define ALX_WRR_PRI2_MASK 0x1F 705 #define ALX_WRR_PRI2_SHIFT 16 706 #define ALX_WRR_PRI1_MASK 0x1F 707 #define ALX_WRR_PRI1_SHIFT 8 708 #define ALX_WRR_PRI0_MASK 0x1F 709 #define ALX_WRR_PRI0_SHIFT 0 710 711 #define ALX_HQTPD 0x193C 712 #define ALX_HQTPD_BURST_EN BIT(31) 713 #define ALX_HQTPD_Q3_NUMPREF_MASK 0xF 714 #define ALX_HQTPD_Q3_NUMPREF_SHIFT 8 715 #define ALX_HQTPD_Q2_NUMPREF_MASK 0xF 716 #define ALX_HQTPD_Q2_NUMPREF_SHIFT 4 717 #define ALX_HQTPD_Q1_NUMPREF_MASK 0xF 718 #define ALX_HQTPD_Q1_NUMPREF_SHIFT 0 719 720 #define ALX_MISC 0x19C0 721 #define ALX_MISC_PSW_OCP_MASK 0x7 722 #define ALX_MISC_PSW_OCP_SHIFT 21 723 #define ALX_MISC_PSW_OCP_DEF 0x7 724 #define ALX_MISC_ISO_EN BIT(12) 725 #define ALX_MISC_INTNLOSC_OPEN BIT(3) 726 727 #define ALX_MSIC2 0x19C8 728 #define ALX_MSIC2_CALB_START BIT(0) 729 730 #define ALX_MISC3 0x19CC 731 /* bit1: 1:Software control 25M */ 732 #define ALX_MISC3_25M_BY_SW BIT(1) 733 /* bit0: 25M switch to intnl OSC */ 734 #define ALX_MISC3_25M_NOTO_INTNL BIT(0) 735 736 /* MSIX tbl in memory space */ 737 #define ALX_MSIX_ENTRY_BASE 0x2000 738 739 /********************* PHY regs definition ***************************/ 740 741 /* PHY Specific Status Register */ 742 #define ALX_MII_GIGA_PSSR 0x11 743 #define ALX_GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 744 #define ALX_GIGA_PSSR_DPLX 0x2000 745 #define ALX_GIGA_PSSR_SPEED 0xC000 746 #define ALX_GIGA_PSSR_10MBS 0x0000 747 #define ALX_GIGA_PSSR_100MBS 0x4000 748 #define ALX_GIGA_PSSR_1000MBS 0x8000 749 750 /* PHY Interrupt Enable Register */ 751 #define ALX_MII_IER 0x12 752 #define ALX_IER_LINK_UP 0x0400 753 #define ALX_IER_LINK_DOWN 0x0800 754 755 /* PHY Interrupt Status Register */ 756 #define ALX_MII_ISR 0x13 757 758 #define ALX_MII_DBG_ADDR 0x1D 759 #define ALX_MII_DBG_DATA 0x1E 760 761 /***************************** debug port *************************************/ 762 763 #define ALX_MIIDBG_ANACTRL 0x00 764 #define ALX_ANACTRL_DEF 0x02EF 765 766 #define ALX_MIIDBG_SYSMODCTRL 0x04 767 /* en half bias */ 768 #define ALX_SYSMODCTRL_IECHOADJ_DEF 0xBB8B 769 770 #define ALX_MIIDBG_SRDSYSMOD 0x05 771 #define ALX_SRDSYSMOD_DEEMP_EN 0x0040 772 #define ALX_SRDSYSMOD_DEF 0x2C46 773 774 #define ALX_MIIDBG_HIBNEG 0x0B 775 #define ALX_HIBNEG_PSHIB_EN 0x8000 776 #define ALX_HIBNEG_HIB_PSE 0x1000 777 #define ALX_HIBNEG_DEF 0xBC40 778 #define ALX_HIBNEG_NOHIB (ALX_HIBNEG_DEF & \ 779 ~(ALX_HIBNEG_PSHIB_EN | ALX_HIBNEG_HIB_PSE)) 780 781 #define ALX_MIIDBG_TST10BTCFG 0x12 782 #define ALX_TST10BTCFG_DEF 0x4C04 783 784 #define ALX_MIIDBG_AZ_ANADECT 0x15 785 #define ALX_AZ_ANADECT_DEF 0x3220 786 #define ALX_AZ_ANADECT_LONG 0x3210 787 788 #define ALX_MIIDBG_MSE16DB 0x18 789 #define ALX_MSE16DB_UP 0x05EA 790 #define ALX_MSE16DB_DOWN 0x02EA 791 792 #define ALX_MIIDBG_MSE20DB 0x1C 793 #define ALX_MSE20DB_TH_MASK 0x7F 794 #define ALX_MSE20DB_TH_SHIFT 2 795 #define ALX_MSE20DB_TH_DEF 0x2E 796 #define ALX_MSE20DB_TH_HI 0x54 797 798 #define ALX_MIIDBG_AGC 0x23 799 #define ALX_AGC_2_VGA_MASK 0x3FU 800 #define ALX_AGC_2_VGA_SHIFT 8 801 #define ALX_AGC_LONG1G_LIMT 40 802 #define ALX_AGC_LONG100M_LIMT 44 803 804 #define ALX_MIIDBG_LEGCYPS 0x29 805 #define ALX_LEGCYPS_EN 0x8000 806 #define ALX_LEGCYPS_DEF 0x129D 807 808 #define ALX_MIIDBG_TST100BTCFG 0x36 809 #define ALX_TST100BTCFG_DEF 0xE12C 810 811 #define ALX_MIIDBG_GREENCFG 0x3B 812 #define ALX_GREENCFG_DEF 0x7078 813 814 #define ALX_MIIDBG_GREENCFG2 0x3D 815 #define ALX_GREENCFG2_BP_GREEN 0x8000 816 #define ALX_GREENCFG2_GATE_DFSE_EN 0x0080 817 818 /******* dev 3 *********/ 819 #define ALX_MIIEXT_PCS 3 820 821 #define ALX_MIIEXT_CLDCTRL3 0x8003 822 #define ALX_CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000 823 824 #define ALX_MIIEXT_CLDCTRL5 0x8005 825 #define ALX_CLDCTRL5_BP_VD_HLFBIAS 0x4000 826 827 #define ALX_MIIEXT_CLDCTRL6 0x8006 828 #define ALX_CLDCTRL6_CAB_LEN_MASK 0xFF 829 #define ALX_CLDCTRL6_CAB_LEN_SHIFT 0 830 #define ALX_CLDCTRL6_CAB_LEN_SHORT1G 116 831 #define ALX_CLDCTRL6_CAB_LEN_SHORT100M 152 832 833 #define ALX_MIIEXT_VDRVBIAS 0x8062 834 #define ALX_VDRVBIAS_DEF 0x3 835 836 /********* dev 7 **********/ 837 #define ALX_MIIEXT_ANEG 7 838 839 #define ALX_MIIEXT_LOCAL_EEEADV 0x3C 840 #define ALX_LOCAL_EEEADV_1000BT 0x0004 841 #define ALX_LOCAL_EEEADV_100BT 0x0002 842 843 #define ALX_MIIEXT_AFE 0x801A 844 #define ALX_AFE_10BT_100M_TH 0x0040 845 846 #define ALX_MIIEXT_S3DIG10 0x8023 847 /* bit0: 1:bypass 10BT rx fifo, 0:original 10BT rx */ 848 #define ALX_MIIEXT_S3DIG10_SL 0x0001 849 #define ALX_MIIEXT_S3DIG10_DEF 0 850 851 #define ALX_MIIEXT_NLP78 0x8027 852 #define ALX_MIIEXT_NLP78_120M_DEF 0x8A05 853 854 #endif 855