1 /* 2 * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net> 3 * 4 * This file is free software: you may copy, redistribute and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation, either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This file is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 * This file incorporates work covered by the following copyright and 18 * permission notice: 19 * 20 * Copyright (c) 2012 Qualcomm Atheros, Inc. 21 * 22 * Permission to use, copy, modify, and/or distribute this software for any 23 * purpose with or without fee is hereby granted, provided that the above 24 * copyright notice and this permission notice appear in all copies. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 27 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 29 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 30 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 31 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 32 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 33 */ 34 #include <linux/etherdevice.h> 35 #include <linux/delay.h> 36 #include <linux/pci.h> 37 #include <linux/mdio.h> 38 #include "reg.h" 39 #include "hw.h" 40 41 static inline bool alx_is_rev_a(u8 rev) 42 { 43 return rev == ALX_REV_A0 || rev == ALX_REV_A1; 44 } 45 46 static int alx_wait_mdio_idle(struct alx_hw *hw) 47 { 48 u32 val; 49 int i; 50 51 for (i = 0; i < ALX_MDIO_MAX_AC_TO; i++) { 52 val = alx_read_mem32(hw, ALX_MDIO); 53 if (!(val & ALX_MDIO_BUSY)) 54 return 0; 55 udelay(10); 56 } 57 58 return -ETIMEDOUT; 59 } 60 61 static int alx_read_phy_core(struct alx_hw *hw, bool ext, u8 dev, 62 u16 reg, u16 *phy_data) 63 { 64 u32 val, clk_sel; 65 int err; 66 67 *phy_data = 0; 68 69 /* use slow clock when it's in hibernation status */ 70 clk_sel = hw->link_speed != SPEED_UNKNOWN ? 71 ALX_MDIO_CLK_SEL_25MD4 : 72 ALX_MDIO_CLK_SEL_25MD128; 73 74 if (ext) { 75 val = dev << ALX_MDIO_EXTN_DEVAD_SHIFT | 76 reg << ALX_MDIO_EXTN_REG_SHIFT; 77 alx_write_mem32(hw, ALX_MDIO_EXTN, val); 78 79 val = ALX_MDIO_SPRES_PRMBL | ALX_MDIO_START | 80 ALX_MDIO_MODE_EXT | ALX_MDIO_OP_READ | 81 clk_sel << ALX_MDIO_CLK_SEL_SHIFT; 82 } else { 83 val = ALX_MDIO_SPRES_PRMBL | 84 clk_sel << ALX_MDIO_CLK_SEL_SHIFT | 85 reg << ALX_MDIO_REG_SHIFT | 86 ALX_MDIO_START | ALX_MDIO_OP_READ; 87 } 88 alx_write_mem32(hw, ALX_MDIO, val); 89 90 err = alx_wait_mdio_idle(hw); 91 if (err) 92 return err; 93 val = alx_read_mem32(hw, ALX_MDIO); 94 *phy_data = ALX_GET_FIELD(val, ALX_MDIO_DATA); 95 return 0; 96 } 97 98 static int alx_write_phy_core(struct alx_hw *hw, bool ext, u8 dev, 99 u16 reg, u16 phy_data) 100 { 101 u32 val, clk_sel; 102 103 /* use slow clock when it's in hibernation status */ 104 clk_sel = hw->link_speed != SPEED_UNKNOWN ? 105 ALX_MDIO_CLK_SEL_25MD4 : 106 ALX_MDIO_CLK_SEL_25MD128; 107 108 if (ext) { 109 val = dev << ALX_MDIO_EXTN_DEVAD_SHIFT | 110 reg << ALX_MDIO_EXTN_REG_SHIFT; 111 alx_write_mem32(hw, ALX_MDIO_EXTN, val); 112 113 val = ALX_MDIO_SPRES_PRMBL | 114 clk_sel << ALX_MDIO_CLK_SEL_SHIFT | 115 phy_data << ALX_MDIO_DATA_SHIFT | 116 ALX_MDIO_START | ALX_MDIO_MODE_EXT; 117 } else { 118 val = ALX_MDIO_SPRES_PRMBL | 119 clk_sel << ALX_MDIO_CLK_SEL_SHIFT | 120 reg << ALX_MDIO_REG_SHIFT | 121 phy_data << ALX_MDIO_DATA_SHIFT | 122 ALX_MDIO_START; 123 } 124 alx_write_mem32(hw, ALX_MDIO, val); 125 126 return alx_wait_mdio_idle(hw); 127 } 128 129 static int __alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data) 130 { 131 return alx_read_phy_core(hw, false, 0, reg, phy_data); 132 } 133 134 static int __alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data) 135 { 136 return alx_write_phy_core(hw, false, 0, reg, phy_data); 137 } 138 139 static int __alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata) 140 { 141 return alx_read_phy_core(hw, true, dev, reg, pdata); 142 } 143 144 static int __alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data) 145 { 146 return alx_write_phy_core(hw, true, dev, reg, data); 147 } 148 149 static int __alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata) 150 { 151 int err; 152 153 err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg); 154 if (err) 155 return err; 156 157 return __alx_read_phy_reg(hw, ALX_MII_DBG_DATA, pdata); 158 } 159 160 static int __alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data) 161 { 162 int err; 163 164 err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg); 165 if (err) 166 return err; 167 168 return __alx_write_phy_reg(hw, ALX_MII_DBG_DATA, data); 169 } 170 171 int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data) 172 { 173 int err; 174 175 spin_lock(&hw->mdio_lock); 176 err = __alx_read_phy_reg(hw, reg, phy_data); 177 spin_unlock(&hw->mdio_lock); 178 179 return err; 180 } 181 182 int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data) 183 { 184 int err; 185 186 spin_lock(&hw->mdio_lock); 187 err = __alx_write_phy_reg(hw, reg, phy_data); 188 spin_unlock(&hw->mdio_lock); 189 190 return err; 191 } 192 193 int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata) 194 { 195 int err; 196 197 spin_lock(&hw->mdio_lock); 198 err = __alx_read_phy_ext(hw, dev, reg, pdata); 199 spin_unlock(&hw->mdio_lock); 200 201 return err; 202 } 203 204 int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data) 205 { 206 int err; 207 208 spin_lock(&hw->mdio_lock); 209 err = __alx_write_phy_ext(hw, dev, reg, data); 210 spin_unlock(&hw->mdio_lock); 211 212 return err; 213 } 214 215 static int alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata) 216 { 217 int err; 218 219 spin_lock(&hw->mdio_lock); 220 err = __alx_read_phy_dbg(hw, reg, pdata); 221 spin_unlock(&hw->mdio_lock); 222 223 return err; 224 } 225 226 static int alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data) 227 { 228 int err; 229 230 spin_lock(&hw->mdio_lock); 231 err = __alx_write_phy_dbg(hw, reg, data); 232 spin_unlock(&hw->mdio_lock); 233 234 return err; 235 } 236 237 static u16 alx_get_phy_config(struct alx_hw *hw) 238 { 239 u32 val; 240 u16 phy_val; 241 242 val = alx_read_mem32(hw, ALX_PHY_CTRL); 243 /* phy in reset */ 244 if ((val & ALX_PHY_CTRL_DSPRST_OUT) == 0) 245 return ALX_DRV_PHY_UNKNOWN; 246 247 val = alx_read_mem32(hw, ALX_DRV); 248 val = ALX_GET_FIELD(val, ALX_DRV_PHY); 249 if (ALX_DRV_PHY_UNKNOWN == val) 250 return ALX_DRV_PHY_UNKNOWN; 251 252 alx_read_phy_reg(hw, ALX_MII_DBG_ADDR, &phy_val); 253 if (ALX_PHY_INITED == phy_val) 254 return val; 255 256 return ALX_DRV_PHY_UNKNOWN; 257 } 258 259 static bool alx_wait_reg(struct alx_hw *hw, u32 reg, u32 wait, u32 *val) 260 { 261 u32 read; 262 int i; 263 264 for (i = 0; i < ALX_SLD_MAX_TO; i++) { 265 read = alx_read_mem32(hw, reg); 266 if ((read & wait) == 0) { 267 if (val) 268 *val = read; 269 return true; 270 } 271 mdelay(1); 272 } 273 274 return false; 275 } 276 277 static bool alx_read_macaddr(struct alx_hw *hw, u8 *addr) 278 { 279 u32 mac0, mac1; 280 281 mac0 = alx_read_mem32(hw, ALX_STAD0); 282 mac1 = alx_read_mem32(hw, ALX_STAD1); 283 284 /* addr should be big-endian */ 285 *(__be32 *)(addr + 2) = cpu_to_be32(mac0); 286 *(__be16 *)addr = cpu_to_be16(mac1); 287 288 return is_valid_ether_addr(addr); 289 } 290 291 int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr) 292 { 293 u32 val; 294 295 /* try to get it from register first */ 296 if (alx_read_macaddr(hw, addr)) 297 return 0; 298 299 /* try to load from efuse */ 300 if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_STAT | ALX_SLD_START, &val)) 301 return -EIO; 302 alx_write_mem32(hw, ALX_SLD, val | ALX_SLD_START); 303 if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_START, NULL)) 304 return -EIO; 305 if (alx_read_macaddr(hw, addr)) 306 return 0; 307 308 /* try to load from flash/eeprom (if present) */ 309 val = alx_read_mem32(hw, ALX_EFLD); 310 if (val & (ALX_EFLD_F_EXIST | ALX_EFLD_E_EXIST)) { 311 if (!alx_wait_reg(hw, ALX_EFLD, 312 ALX_EFLD_STAT | ALX_EFLD_START, &val)) 313 return -EIO; 314 alx_write_mem32(hw, ALX_EFLD, val | ALX_EFLD_START); 315 if (!alx_wait_reg(hw, ALX_EFLD, ALX_EFLD_START, NULL)) 316 return -EIO; 317 if (alx_read_macaddr(hw, addr)) 318 return 0; 319 } 320 321 return -EIO; 322 } 323 324 void alx_set_macaddr(struct alx_hw *hw, const u8 *addr) 325 { 326 u32 val; 327 328 /* for example: 00-0B-6A-F6-00-DC * STAD0=6AF600DC, STAD1=000B */ 329 val = be32_to_cpu(*(__be32 *)(addr + 2)); 330 alx_write_mem32(hw, ALX_STAD0, val); 331 val = be16_to_cpu(*(__be16 *)addr); 332 alx_write_mem32(hw, ALX_STAD1, val); 333 } 334 335 static void alx_enable_osc(struct alx_hw *hw) 336 { 337 u32 val; 338 339 /* rising edge */ 340 val = alx_read_mem32(hw, ALX_MISC); 341 alx_write_mem32(hw, ALX_MISC, val & ~ALX_MISC_INTNLOSC_OPEN); 342 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN); 343 } 344 345 static void alx_reset_osc(struct alx_hw *hw, u8 rev) 346 { 347 u32 val, val2; 348 349 /* clear Internal OSC settings, switching OSC by hw itself */ 350 val = alx_read_mem32(hw, ALX_MISC3); 351 alx_write_mem32(hw, ALX_MISC3, 352 (val & ~ALX_MISC3_25M_BY_SW) | 353 ALX_MISC3_25M_NOTO_INTNL); 354 355 /* 25M clk from chipset may be unstable 1s after de-assert of 356 * PERST, driver need re-calibrate before enter Sleep for WoL 357 */ 358 val = alx_read_mem32(hw, ALX_MISC); 359 if (rev >= ALX_REV_B0) { 360 /* restore over current protection def-val, 361 * this val could be reset by MAC-RST 362 */ 363 ALX_SET_FIELD(val, ALX_MISC_PSW_OCP, ALX_MISC_PSW_OCP_DEF); 364 /* a 0->1 change will update the internal val of osc */ 365 val &= ~ALX_MISC_INTNLOSC_OPEN; 366 alx_write_mem32(hw, ALX_MISC, val); 367 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN); 368 /* hw will automatically dis OSC after cab. */ 369 val2 = alx_read_mem32(hw, ALX_MSIC2); 370 val2 &= ~ALX_MSIC2_CALB_START; 371 alx_write_mem32(hw, ALX_MSIC2, val2); 372 alx_write_mem32(hw, ALX_MSIC2, val2 | ALX_MSIC2_CALB_START); 373 } else { 374 val &= ~ALX_MISC_INTNLOSC_OPEN; 375 /* disable isolate for rev A devices */ 376 if (alx_is_rev_a(rev)) 377 val &= ~ALX_MISC_ISO_EN; 378 379 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN); 380 alx_write_mem32(hw, ALX_MISC, val); 381 } 382 383 udelay(20); 384 } 385 386 static int alx_stop_mac(struct alx_hw *hw) 387 { 388 u32 rxq, txq, val; 389 u16 i; 390 391 rxq = alx_read_mem32(hw, ALX_RXQ0); 392 alx_write_mem32(hw, ALX_RXQ0, rxq & ~ALX_RXQ0_EN); 393 txq = alx_read_mem32(hw, ALX_TXQ0); 394 alx_write_mem32(hw, ALX_TXQ0, txq & ~ALX_TXQ0_EN); 395 396 udelay(40); 397 398 hw->rx_ctrl &= ~(ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN); 399 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); 400 401 for (i = 0; i < ALX_DMA_MAC_RST_TO; i++) { 402 val = alx_read_mem32(hw, ALX_MAC_STS); 403 if (!(val & ALX_MAC_STS_IDLE)) 404 return 0; 405 udelay(10); 406 } 407 408 return -ETIMEDOUT; 409 } 410 411 int alx_reset_mac(struct alx_hw *hw) 412 { 413 u32 val, pmctrl; 414 int i, ret; 415 u8 rev; 416 bool a_cr; 417 418 pmctrl = 0; 419 rev = alx_hw_revision(hw); 420 a_cr = alx_is_rev_a(rev) && alx_hw_with_cr(hw); 421 422 /* disable all interrupts, RXQ/TXQ */ 423 alx_write_mem32(hw, ALX_MSIX_MASK, 0xFFFFFFFF); 424 alx_write_mem32(hw, ALX_IMR, 0); 425 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS); 426 427 ret = alx_stop_mac(hw); 428 if (ret) 429 return ret; 430 431 /* mac reset workaroud */ 432 alx_write_mem32(hw, ALX_RFD_PIDX, 1); 433 434 /* dis l0s/l1 before mac reset */ 435 if (a_cr) { 436 pmctrl = alx_read_mem32(hw, ALX_PMCTRL); 437 if (pmctrl & (ALX_PMCTRL_L1_EN | ALX_PMCTRL_L0S_EN)) 438 alx_write_mem32(hw, ALX_PMCTRL, 439 pmctrl & ~(ALX_PMCTRL_L1_EN | 440 ALX_PMCTRL_L0S_EN)); 441 } 442 443 /* reset whole mac safely */ 444 val = alx_read_mem32(hw, ALX_MASTER); 445 alx_write_mem32(hw, ALX_MASTER, 446 val | ALX_MASTER_DMA_MAC_RST | ALX_MASTER_OOB_DIS); 447 448 /* make sure it's real idle */ 449 udelay(10); 450 for (i = 0; i < ALX_DMA_MAC_RST_TO; i++) { 451 val = alx_read_mem32(hw, ALX_RFD_PIDX); 452 if (val == 0) 453 break; 454 udelay(10); 455 } 456 for (; i < ALX_DMA_MAC_RST_TO; i++) { 457 val = alx_read_mem32(hw, ALX_MASTER); 458 if ((val & ALX_MASTER_DMA_MAC_RST) == 0) 459 break; 460 udelay(10); 461 } 462 if (i == ALX_DMA_MAC_RST_TO) 463 return -EIO; 464 udelay(10); 465 466 if (a_cr) { 467 alx_write_mem32(hw, ALX_MASTER, val | ALX_MASTER_PCLKSEL_SRDS); 468 /* restore l0s / l1 */ 469 if (pmctrl & (ALX_PMCTRL_L1_EN | ALX_PMCTRL_L0S_EN)) 470 alx_write_mem32(hw, ALX_PMCTRL, pmctrl); 471 } 472 473 alx_reset_osc(hw, rev); 474 475 /* clear Internal OSC settings, switching OSC by hw itself, 476 * disable isolate for rev A devices 477 */ 478 val = alx_read_mem32(hw, ALX_MISC3); 479 alx_write_mem32(hw, ALX_MISC3, 480 (val & ~ALX_MISC3_25M_BY_SW) | 481 ALX_MISC3_25M_NOTO_INTNL); 482 val = alx_read_mem32(hw, ALX_MISC); 483 val &= ~ALX_MISC_INTNLOSC_OPEN; 484 if (alx_is_rev_a(rev)) 485 val &= ~ALX_MISC_ISO_EN; 486 alx_write_mem32(hw, ALX_MISC, val); 487 udelay(20); 488 489 /* driver control speed/duplex, hash-alg */ 490 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); 491 492 val = alx_read_mem32(hw, ALX_SERDES); 493 alx_write_mem32(hw, ALX_SERDES, 494 val | ALX_SERDES_MACCLK_SLWDWN | 495 ALX_SERDES_PHYCLK_SLWDWN); 496 497 return 0; 498 } 499 500 void alx_reset_phy(struct alx_hw *hw) 501 { 502 int i; 503 u32 val; 504 u16 phy_val; 505 506 /* (DSP)reset PHY core */ 507 val = alx_read_mem32(hw, ALX_PHY_CTRL); 508 val &= ~(ALX_PHY_CTRL_DSPRST_OUT | ALX_PHY_CTRL_IDDQ | 509 ALX_PHY_CTRL_GATE_25M | ALX_PHY_CTRL_POWER_DOWN | 510 ALX_PHY_CTRL_CLS); 511 val |= ALX_PHY_CTRL_RST_ANALOG; 512 513 val |= (ALX_PHY_CTRL_HIB_PULSE | ALX_PHY_CTRL_HIB_EN); 514 alx_write_mem32(hw, ALX_PHY_CTRL, val); 515 udelay(10); 516 alx_write_mem32(hw, ALX_PHY_CTRL, val | ALX_PHY_CTRL_DSPRST_OUT); 517 518 for (i = 0; i < ALX_PHY_CTRL_DSPRST_TO; i++) 519 udelay(10); 520 521 /* phy power saving & hib */ 522 alx_write_phy_dbg(hw, ALX_MIIDBG_LEGCYPS, ALX_LEGCYPS_DEF); 523 alx_write_phy_dbg(hw, ALX_MIIDBG_SYSMODCTRL, 524 ALX_SYSMODCTRL_IECHOADJ_DEF); 525 alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_VDRVBIAS, 526 ALX_VDRVBIAS_DEF); 527 528 /* EEE advertisement */ 529 val = alx_read_mem32(hw, ALX_LPI_CTRL); 530 alx_write_mem32(hw, ALX_LPI_CTRL, val & ~ALX_LPI_CTRL_EN); 531 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_LOCAL_EEEADV, 0); 532 533 /* phy power saving */ 534 alx_write_phy_dbg(hw, ALX_MIIDBG_TST10BTCFG, ALX_TST10BTCFG_DEF); 535 alx_write_phy_dbg(hw, ALX_MIIDBG_SRDSYSMOD, ALX_SRDSYSMOD_DEF); 536 alx_write_phy_dbg(hw, ALX_MIIDBG_TST100BTCFG, ALX_TST100BTCFG_DEF); 537 alx_write_phy_dbg(hw, ALX_MIIDBG_ANACTRL, ALX_ANACTRL_DEF); 538 alx_read_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, &phy_val); 539 alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, 540 phy_val & ~ALX_GREENCFG2_GATE_DFSE_EN); 541 /* rtl8139c, 120m issue */ 542 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_NLP78, 543 ALX_MIIEXT_NLP78_120M_DEF); 544 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_S3DIG10, 545 ALX_MIIEXT_S3DIG10_DEF); 546 547 if (hw->lnk_patch) { 548 /* Turn off half amplitude */ 549 alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3, 550 &phy_val); 551 alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3, 552 phy_val | ALX_CLDCTRL3_BP_CABLE1TH_DET_GT); 553 /* Turn off Green feature */ 554 alx_read_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, &phy_val); 555 alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, 556 phy_val | ALX_GREENCFG2_BP_GREEN); 557 /* Turn off half Bias */ 558 alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5, 559 &phy_val); 560 alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5, 561 phy_val | ALX_CLDCTRL5_BP_VD_HLFBIAS); 562 } 563 564 /* set phy interrupt mask */ 565 alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP | ALX_IER_LINK_DOWN); 566 } 567 568 #define ALX_PCI_CMD (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 569 570 void alx_reset_pcie(struct alx_hw *hw) 571 { 572 u8 rev = alx_hw_revision(hw); 573 u32 val; 574 u16 val16; 575 576 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ 577 pci_read_config_word(hw->pdev, PCI_COMMAND, &val16); 578 if (!(val16 & ALX_PCI_CMD) || (val16 & PCI_COMMAND_INTX_DISABLE)) { 579 val16 = (val16 | ALX_PCI_CMD) & ~PCI_COMMAND_INTX_DISABLE; 580 pci_write_config_word(hw->pdev, PCI_COMMAND, val16); 581 } 582 583 /* clear WoL setting/status */ 584 val = alx_read_mem32(hw, ALX_WOL0); 585 alx_write_mem32(hw, ALX_WOL0, 0); 586 587 val = alx_read_mem32(hw, ALX_PDLL_TRNS1); 588 alx_write_mem32(hw, ALX_PDLL_TRNS1, val & ~ALX_PDLL_TRNS1_D3PLLOFF_EN); 589 590 /* mask some pcie error bits */ 591 val = alx_read_mem32(hw, ALX_UE_SVRT); 592 val &= ~(ALX_UE_SVRT_DLPROTERR | ALX_UE_SVRT_FCPROTERR); 593 alx_write_mem32(hw, ALX_UE_SVRT, val); 594 595 /* wol 25M & pclk */ 596 val = alx_read_mem32(hw, ALX_MASTER); 597 if (alx_is_rev_a(rev) && alx_hw_with_cr(hw)) { 598 if ((val & ALX_MASTER_WAKEN_25M) == 0 || 599 (val & ALX_MASTER_PCLKSEL_SRDS) == 0) 600 alx_write_mem32(hw, ALX_MASTER, 601 val | ALX_MASTER_PCLKSEL_SRDS | 602 ALX_MASTER_WAKEN_25M); 603 } else { 604 if ((val & ALX_MASTER_WAKEN_25M) == 0 || 605 (val & ALX_MASTER_PCLKSEL_SRDS) != 0) 606 alx_write_mem32(hw, ALX_MASTER, 607 (val & ~ALX_MASTER_PCLKSEL_SRDS) | 608 ALX_MASTER_WAKEN_25M); 609 } 610 611 /* ASPM setting */ 612 alx_enable_aspm(hw, true, true); 613 614 udelay(10); 615 } 616 617 void alx_start_mac(struct alx_hw *hw) 618 { 619 u32 mac, txq, rxq; 620 621 rxq = alx_read_mem32(hw, ALX_RXQ0); 622 alx_write_mem32(hw, ALX_RXQ0, rxq | ALX_RXQ0_EN); 623 txq = alx_read_mem32(hw, ALX_TXQ0); 624 alx_write_mem32(hw, ALX_TXQ0, txq | ALX_TXQ0_EN); 625 626 mac = hw->rx_ctrl; 627 if (hw->link_speed % 10 == DUPLEX_FULL) 628 mac |= ALX_MAC_CTRL_FULLD; 629 else 630 mac &= ~ALX_MAC_CTRL_FULLD; 631 ALX_SET_FIELD(mac, ALX_MAC_CTRL_SPEED, 632 hw->link_speed >= SPEED_1000 ? ALX_MAC_CTRL_SPEED_1000 : 633 ALX_MAC_CTRL_SPEED_10_100); 634 mac |= ALX_MAC_CTRL_TX_EN | ALX_MAC_CTRL_RX_EN; 635 hw->rx_ctrl = mac; 636 alx_write_mem32(hw, ALX_MAC_CTRL, mac); 637 } 638 639 void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc) 640 { 641 if (fc & ALX_FC_RX) 642 hw->rx_ctrl |= ALX_MAC_CTRL_RXFC_EN; 643 else 644 hw->rx_ctrl &= ~ALX_MAC_CTRL_RXFC_EN; 645 646 if (fc & ALX_FC_TX) 647 hw->rx_ctrl |= ALX_MAC_CTRL_TXFC_EN; 648 else 649 hw->rx_ctrl &= ~ALX_MAC_CTRL_TXFC_EN; 650 651 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); 652 } 653 654 void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en) 655 { 656 u32 pmctrl; 657 u8 rev = alx_hw_revision(hw); 658 659 pmctrl = alx_read_mem32(hw, ALX_PMCTRL); 660 661 ALX_SET_FIELD(pmctrl, ALX_PMCTRL_LCKDET_TIMER, 662 ALX_PMCTRL_LCKDET_TIMER_DEF); 663 pmctrl |= ALX_PMCTRL_RCVR_WT_1US | 664 ALX_PMCTRL_L1_CLKSW_EN | 665 ALX_PMCTRL_L1_SRDSRX_PWD; 666 ALX_SET_FIELD(pmctrl, ALX_PMCTRL_L1REQ_TO, ALX_PMCTRL_L1REG_TO_DEF); 667 ALX_SET_FIELD(pmctrl, ALX_PMCTRL_L1_TIMER, ALX_PMCTRL_L1_TIMER_16US); 668 pmctrl &= ~(ALX_PMCTRL_L1_SRDS_EN | 669 ALX_PMCTRL_L1_SRDSPLL_EN | 670 ALX_PMCTRL_L1_BUFSRX_EN | 671 ALX_PMCTRL_SADLY_EN | 672 ALX_PMCTRL_HOTRST_WTEN| 673 ALX_PMCTRL_L0S_EN | 674 ALX_PMCTRL_L1_EN | 675 ALX_PMCTRL_ASPM_FCEN | 676 ALX_PMCTRL_TXL1_AFTER_L0S | 677 ALX_PMCTRL_RXL1_AFTER_L0S); 678 if (alx_is_rev_a(rev) && alx_hw_with_cr(hw)) 679 pmctrl |= ALX_PMCTRL_L1_SRDS_EN | ALX_PMCTRL_L1_SRDSPLL_EN; 680 681 if (l0s_en) 682 pmctrl |= (ALX_PMCTRL_L0S_EN | ALX_PMCTRL_ASPM_FCEN); 683 if (l1_en) 684 pmctrl |= (ALX_PMCTRL_L1_EN | ALX_PMCTRL_ASPM_FCEN); 685 686 alx_write_mem32(hw, ALX_PMCTRL, pmctrl); 687 } 688 689 690 static u32 ethadv_to_hw_cfg(struct alx_hw *hw, u32 ethadv_cfg) 691 { 692 u32 cfg = 0; 693 694 if (ethadv_cfg & ADVERTISED_Autoneg) { 695 cfg |= ALX_DRV_PHY_AUTO; 696 if (ethadv_cfg & ADVERTISED_10baseT_Half) 697 cfg |= ALX_DRV_PHY_10; 698 if (ethadv_cfg & ADVERTISED_10baseT_Full) 699 cfg |= ALX_DRV_PHY_10 | ALX_DRV_PHY_DUPLEX; 700 if (ethadv_cfg & ADVERTISED_100baseT_Half) 701 cfg |= ALX_DRV_PHY_100; 702 if (ethadv_cfg & ADVERTISED_100baseT_Full) 703 cfg |= ALX_DRV_PHY_100 | ALX_DRV_PHY_DUPLEX; 704 if (ethadv_cfg & ADVERTISED_1000baseT_Half) 705 cfg |= ALX_DRV_PHY_1000; 706 if (ethadv_cfg & ADVERTISED_1000baseT_Full) 707 cfg |= ALX_DRV_PHY_100 | ALX_DRV_PHY_DUPLEX; 708 if (ethadv_cfg & ADVERTISED_Pause) 709 cfg |= ADVERTISE_PAUSE_CAP; 710 if (ethadv_cfg & ADVERTISED_Asym_Pause) 711 cfg |= ADVERTISE_PAUSE_ASYM; 712 } else { 713 switch (ethadv_cfg) { 714 case ADVERTISED_10baseT_Half: 715 cfg |= ALX_DRV_PHY_10; 716 break; 717 case ADVERTISED_100baseT_Half: 718 cfg |= ALX_DRV_PHY_100; 719 break; 720 case ADVERTISED_10baseT_Full: 721 cfg |= ALX_DRV_PHY_10 | ALX_DRV_PHY_DUPLEX; 722 break; 723 case ADVERTISED_100baseT_Full: 724 cfg |= ALX_DRV_PHY_100 | ALX_DRV_PHY_DUPLEX; 725 break; 726 } 727 } 728 729 return cfg; 730 } 731 732 int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl) 733 { 734 u16 adv, giga, cr; 735 u32 val; 736 int err = 0; 737 738 alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, 0); 739 val = alx_read_mem32(hw, ALX_DRV); 740 ALX_SET_FIELD(val, ALX_DRV_PHY, 0); 741 742 if (ethadv & ADVERTISED_Autoneg) { 743 adv = ADVERTISE_CSMA; 744 adv |= ethtool_adv_to_mii_adv_t(ethadv); 745 746 if (flowctrl & ALX_FC_ANEG) { 747 if (flowctrl & ALX_FC_RX) { 748 adv |= ADVERTISED_Pause; 749 if (!(flowctrl & ALX_FC_TX)) 750 adv |= ADVERTISED_Asym_Pause; 751 } else if (flowctrl & ALX_FC_TX) { 752 adv |= ADVERTISED_Asym_Pause; 753 } 754 } 755 giga = 0; 756 if (alx_hw_giga(hw)) 757 giga = ethtool_adv_to_mii_ctrl1000_t(ethadv); 758 759 cr = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART; 760 761 if (alx_write_phy_reg(hw, MII_ADVERTISE, adv) || 762 alx_write_phy_reg(hw, MII_CTRL1000, giga) || 763 alx_write_phy_reg(hw, MII_BMCR, cr)) 764 err = -EBUSY; 765 } else { 766 cr = BMCR_RESET; 767 if (ethadv == ADVERTISED_100baseT_Half || 768 ethadv == ADVERTISED_100baseT_Full) 769 cr |= BMCR_SPEED100; 770 if (ethadv == ADVERTISED_10baseT_Full || 771 ethadv == ADVERTISED_100baseT_Full) 772 cr |= BMCR_FULLDPLX; 773 774 err = alx_write_phy_reg(hw, MII_BMCR, cr); 775 } 776 777 if (!err) { 778 alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, ALX_PHY_INITED); 779 val |= ethadv_to_hw_cfg(hw, ethadv); 780 } 781 782 alx_write_mem32(hw, ALX_DRV, val); 783 784 return err; 785 } 786 787 788 void alx_post_phy_link(struct alx_hw *hw) 789 { 790 u16 phy_val, len, agc; 791 u8 revid = alx_hw_revision(hw); 792 bool adj_th = revid == ALX_REV_B0; 793 int speed; 794 795 if (hw->link_speed == SPEED_UNKNOWN) 796 speed = SPEED_UNKNOWN; 797 else 798 speed = hw->link_speed - hw->link_speed % 10; 799 800 if (revid != ALX_REV_B0 && !alx_is_rev_a(revid)) 801 return; 802 803 /* 1000BT/AZ, wrong cable length */ 804 if (speed != SPEED_UNKNOWN) { 805 alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL6, 806 &phy_val); 807 len = ALX_GET_FIELD(phy_val, ALX_CLDCTRL6_CAB_LEN); 808 alx_read_phy_dbg(hw, ALX_MIIDBG_AGC, &phy_val); 809 agc = ALX_GET_FIELD(phy_val, ALX_AGC_2_VGA); 810 811 if ((speed == SPEED_1000 && 812 (len > ALX_CLDCTRL6_CAB_LEN_SHORT1G || 813 (len == 0 && agc > ALX_AGC_LONG1G_LIMT))) || 814 (speed == SPEED_100 && 815 (len > ALX_CLDCTRL6_CAB_LEN_SHORT100M || 816 (len == 0 && agc > ALX_AGC_LONG100M_LIMT)))) { 817 alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT, 818 ALX_AZ_ANADECT_LONG); 819 alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, 820 &phy_val); 821 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, 822 phy_val | ALX_AFE_10BT_100M_TH); 823 } else { 824 alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT, 825 ALX_AZ_ANADECT_DEF); 826 alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, 827 ALX_MIIEXT_AFE, &phy_val); 828 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, 829 phy_val & ~ALX_AFE_10BT_100M_TH); 830 } 831 832 /* threshold adjust */ 833 if (adj_th && hw->lnk_patch) { 834 if (speed == SPEED_100) { 835 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE16DB, 836 ALX_MSE16DB_UP); 837 } else if (speed == SPEED_1000) { 838 /* 839 * Giga link threshold, raise the tolerance of 840 * noise 50% 841 */ 842 alx_read_phy_dbg(hw, ALX_MIIDBG_MSE20DB, 843 &phy_val); 844 ALX_SET_FIELD(phy_val, ALX_MSE20DB_TH, 845 ALX_MSE20DB_TH_HI); 846 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE20DB, 847 phy_val); 848 } 849 } 850 } else { 851 alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, 852 &phy_val); 853 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, 854 phy_val & ~ALX_AFE_10BT_100M_TH); 855 856 if (adj_th && hw->lnk_patch) { 857 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE16DB, 858 ALX_MSE16DB_DOWN); 859 alx_read_phy_dbg(hw, ALX_MIIDBG_MSE20DB, &phy_val); 860 ALX_SET_FIELD(phy_val, ALX_MSE20DB_TH, 861 ALX_MSE20DB_TH_DEF); 862 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE20DB, phy_val); 863 } 864 } 865 } 866 867 868 /* NOTE: 869 * 1. phy link must be established before calling this function 870 * 2. wol option (pattern,magic,link,etc.) is configed before call it. 871 */ 872 int alx_pre_suspend(struct alx_hw *hw, int speed) 873 { 874 u32 master, mac, phy, val; 875 int err = 0; 876 877 master = alx_read_mem32(hw, ALX_MASTER); 878 master &= ~ALX_MASTER_PCLKSEL_SRDS; 879 mac = hw->rx_ctrl; 880 /* 10/100 half */ 881 ALX_SET_FIELD(mac, ALX_MAC_CTRL_SPEED, ALX_MAC_CTRL_SPEED_10_100); 882 mac &= ~(ALX_MAC_CTRL_FULLD | ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN); 883 884 phy = alx_read_mem32(hw, ALX_PHY_CTRL); 885 phy &= ~(ALX_PHY_CTRL_DSPRST_OUT | ALX_PHY_CTRL_CLS); 886 phy |= ALX_PHY_CTRL_RST_ANALOG | ALX_PHY_CTRL_HIB_PULSE | 887 ALX_PHY_CTRL_HIB_EN; 888 889 /* without any activity */ 890 if (!(hw->sleep_ctrl & ALX_SLEEP_ACTIVE)) { 891 err = alx_write_phy_reg(hw, ALX_MII_IER, 0); 892 if (err) 893 return err; 894 phy |= ALX_PHY_CTRL_IDDQ | ALX_PHY_CTRL_POWER_DOWN; 895 } else { 896 if (hw->sleep_ctrl & (ALX_SLEEP_WOL_MAGIC | ALX_SLEEP_CIFS)) 897 mac |= ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_BRD_EN; 898 if (hw->sleep_ctrl & ALX_SLEEP_CIFS) 899 mac |= ALX_MAC_CTRL_TX_EN; 900 if (speed % 10 == DUPLEX_FULL) 901 mac |= ALX_MAC_CTRL_FULLD; 902 if (speed >= SPEED_1000) 903 ALX_SET_FIELD(mac, ALX_MAC_CTRL_SPEED, 904 ALX_MAC_CTRL_SPEED_1000); 905 phy |= ALX_PHY_CTRL_DSPRST_OUT; 906 err = alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, 907 ALX_MIIEXT_S3DIG10, 908 ALX_MIIEXT_S3DIG10_SL); 909 if (err) 910 return err; 911 } 912 913 alx_enable_osc(hw); 914 hw->rx_ctrl = mac; 915 alx_write_mem32(hw, ALX_MASTER, master); 916 alx_write_mem32(hw, ALX_MAC_CTRL, mac); 917 alx_write_mem32(hw, ALX_PHY_CTRL, phy); 918 919 /* set val of PDLL D3PLLOFF */ 920 val = alx_read_mem32(hw, ALX_PDLL_TRNS1); 921 val |= ALX_PDLL_TRNS1_D3PLLOFF_EN; 922 alx_write_mem32(hw, ALX_PDLL_TRNS1, val); 923 924 return 0; 925 } 926 927 bool alx_phy_configured(struct alx_hw *hw) 928 { 929 u32 cfg, hw_cfg; 930 931 cfg = ethadv_to_hw_cfg(hw, hw->adv_cfg); 932 cfg = ALX_GET_FIELD(cfg, ALX_DRV_PHY); 933 hw_cfg = alx_get_phy_config(hw); 934 935 if (hw_cfg == ALX_DRV_PHY_UNKNOWN) 936 return false; 937 938 return cfg == hw_cfg; 939 } 940 941 int alx_get_phy_link(struct alx_hw *hw, int *speed) 942 { 943 struct pci_dev *pdev = hw->pdev; 944 u16 bmsr, giga; 945 int err; 946 947 err = alx_read_phy_reg(hw, MII_BMSR, &bmsr); 948 if (err) 949 return err; 950 951 err = alx_read_phy_reg(hw, MII_BMSR, &bmsr); 952 if (err) 953 return err; 954 955 if (!(bmsr & BMSR_LSTATUS)) { 956 *speed = SPEED_UNKNOWN; 957 return 0; 958 } 959 960 /* speed/duplex result is saved in PHY Specific Status Register */ 961 err = alx_read_phy_reg(hw, ALX_MII_GIGA_PSSR, &giga); 962 if (err) 963 return err; 964 965 if (!(giga & ALX_GIGA_PSSR_SPD_DPLX_RESOLVED)) 966 goto wrong_speed; 967 968 switch (giga & ALX_GIGA_PSSR_SPEED) { 969 case ALX_GIGA_PSSR_1000MBS: 970 *speed = SPEED_1000; 971 break; 972 case ALX_GIGA_PSSR_100MBS: 973 *speed = SPEED_100; 974 break; 975 case ALX_GIGA_PSSR_10MBS: 976 *speed = SPEED_10; 977 break; 978 default: 979 goto wrong_speed; 980 } 981 982 *speed += (giga & ALX_GIGA_PSSR_DPLX) ? DUPLEX_FULL : DUPLEX_HALF; 983 return 1; 984 985 wrong_speed: 986 dev_err(&pdev->dev, "invalid PHY speed/duplex: 0x%x\n", giga); 987 return -EINVAL; 988 } 989 990 int alx_clear_phy_intr(struct alx_hw *hw) 991 { 992 u16 isr; 993 994 /* clear interrupt status by reading it */ 995 return alx_read_phy_reg(hw, ALX_MII_ISR, &isr); 996 } 997 998 int alx_config_wol(struct alx_hw *hw) 999 { 1000 u32 wol = 0; 1001 int err = 0; 1002 1003 /* turn on magic packet event */ 1004 if (hw->sleep_ctrl & ALX_SLEEP_WOL_MAGIC) 1005 wol |= ALX_WOL0_MAGIC_EN | ALX_WOL0_PME_MAGIC_EN; 1006 1007 /* turn on link up event */ 1008 if (hw->sleep_ctrl & ALX_SLEEP_WOL_PHY) { 1009 wol |= ALX_WOL0_LINK_EN | ALX_WOL0_PME_LINK; 1010 /* only link up can wake up */ 1011 err = alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP); 1012 } 1013 alx_write_mem32(hw, ALX_WOL0, wol); 1014 1015 return err; 1016 } 1017 1018 void alx_disable_rss(struct alx_hw *hw) 1019 { 1020 u32 ctrl = alx_read_mem32(hw, ALX_RXQ0); 1021 1022 ctrl &= ~ALX_RXQ0_RSS_HASH_EN; 1023 alx_write_mem32(hw, ALX_RXQ0, ctrl); 1024 } 1025 1026 void alx_configure_basic(struct alx_hw *hw) 1027 { 1028 u32 val, raw_mtu, max_payload; 1029 u16 val16; 1030 u8 chip_rev = alx_hw_revision(hw); 1031 1032 alx_set_macaddr(hw, hw->mac_addr); 1033 1034 alx_write_mem32(hw, ALX_CLK_GATE, ALX_CLK_GATE_ALL); 1035 1036 /* idle timeout to switch clk_125M */ 1037 if (chip_rev >= ALX_REV_B0) 1038 alx_write_mem32(hw, ALX_IDLE_DECISN_TIMER, 1039 ALX_IDLE_DECISN_TIMER_DEF); 1040 1041 alx_write_mem32(hw, ALX_SMB_TIMER, hw->smb_timer * 500UL); 1042 1043 val = alx_read_mem32(hw, ALX_MASTER); 1044 val |= ALX_MASTER_IRQMOD2_EN | 1045 ALX_MASTER_IRQMOD1_EN | 1046 ALX_MASTER_SYSALVTIMER_EN; 1047 alx_write_mem32(hw, ALX_MASTER, val); 1048 alx_write_mem32(hw, ALX_IRQ_MODU_TIMER, 1049 (hw->imt >> 1) << ALX_IRQ_MODU_TIMER1_SHIFT); 1050 /* intr re-trig timeout */ 1051 alx_write_mem32(hw, ALX_INT_RETRIG, ALX_INT_RETRIG_TO); 1052 /* tpd threshold to trig int */ 1053 alx_write_mem32(hw, ALX_TINT_TPD_THRSHLD, hw->ith_tpd); 1054 alx_write_mem32(hw, ALX_TINT_TIMER, hw->imt); 1055 1056 raw_mtu = hw->mtu + ETH_HLEN; 1057 alx_write_mem32(hw, ALX_MTU, raw_mtu + 8); 1058 if (raw_mtu > ALX_MTU_JUMBO_TH) 1059 hw->rx_ctrl &= ~ALX_MAC_CTRL_FAST_PAUSE; 1060 1061 if ((raw_mtu + 8) < ALX_TXQ1_JUMBO_TSO_TH) 1062 val = (raw_mtu + 8 + 7) >> 3; 1063 else 1064 val = ALX_TXQ1_JUMBO_TSO_TH >> 3; 1065 alx_write_mem32(hw, ALX_TXQ1, val | ALX_TXQ1_ERRLGPKT_DROP_EN); 1066 1067 max_payload = pcie_get_readrq(hw->pdev) >> 8; 1068 /* 1069 * if BIOS had changed the default dma read max length, 1070 * restore it to default value 1071 */ 1072 if (max_payload < ALX_DEV_CTRL_MAXRRS_MIN) 1073 pcie_set_readrq(hw->pdev, 128 << ALX_DEV_CTRL_MAXRRS_MIN); 1074 1075 val = ALX_TXQ_TPD_BURSTPREF_DEF << ALX_TXQ0_TPD_BURSTPREF_SHIFT | 1076 ALX_TXQ0_MODE_ENHANCE | ALX_TXQ0_LSO_8023_EN | 1077 ALX_TXQ0_SUPT_IPOPT | 1078 ALX_TXQ_TXF_BURST_PREF_DEF << ALX_TXQ0_TXF_BURST_PREF_SHIFT; 1079 alx_write_mem32(hw, ALX_TXQ0, val); 1080 val = ALX_TXQ_TPD_BURSTPREF_DEF << ALX_HQTPD_Q1_NUMPREF_SHIFT | 1081 ALX_TXQ_TPD_BURSTPREF_DEF << ALX_HQTPD_Q2_NUMPREF_SHIFT | 1082 ALX_TXQ_TPD_BURSTPREF_DEF << ALX_HQTPD_Q3_NUMPREF_SHIFT | 1083 ALX_HQTPD_BURST_EN; 1084 alx_write_mem32(hw, ALX_HQTPD, val); 1085 1086 /* rxq, flow control */ 1087 val = alx_read_mem32(hw, ALX_SRAM5); 1088 val = ALX_GET_FIELD(val, ALX_SRAM_RXF_LEN) << 3; 1089 if (val > ALX_SRAM_RXF_LEN_8K) { 1090 val16 = ALX_MTU_STD_ALGN >> 3; 1091 val = (val - ALX_RXQ2_RXF_FLOW_CTRL_RSVD) >> 3; 1092 } else { 1093 val16 = ALX_MTU_STD_ALGN >> 3; 1094 val = (val - ALX_MTU_STD_ALGN) >> 3; 1095 } 1096 alx_write_mem32(hw, ALX_RXQ2, 1097 val16 << ALX_RXQ2_RXF_XOFF_THRESH_SHIFT | 1098 val << ALX_RXQ2_RXF_XON_THRESH_SHIFT); 1099 val = ALX_RXQ0_NUM_RFD_PREF_DEF << ALX_RXQ0_NUM_RFD_PREF_SHIFT | 1100 ALX_RXQ0_RSS_MODE_DIS << ALX_RXQ0_RSS_MODE_SHIFT | 1101 ALX_RXQ0_IDT_TBL_SIZE_DEF << ALX_RXQ0_IDT_TBL_SIZE_SHIFT | 1102 ALX_RXQ0_RSS_HSTYP_ALL | ALX_RXQ0_RSS_HASH_EN | 1103 ALX_RXQ0_IPV6_PARSE_EN; 1104 1105 if (alx_hw_giga(hw)) 1106 ALX_SET_FIELD(val, ALX_RXQ0_ASPM_THRESH, 1107 ALX_RXQ0_ASPM_THRESH_100M); 1108 1109 alx_write_mem32(hw, ALX_RXQ0, val); 1110 1111 val = alx_read_mem32(hw, ALX_DMA); 1112 val = ALX_DMA_RORDER_MODE_OUT << ALX_DMA_RORDER_MODE_SHIFT | 1113 ALX_DMA_RREQ_PRI_DATA | 1114 max_payload << ALX_DMA_RREQ_BLEN_SHIFT | 1115 ALX_DMA_WDLY_CNT_DEF << ALX_DMA_WDLY_CNT_SHIFT | 1116 ALX_DMA_RDLY_CNT_DEF << ALX_DMA_RDLY_CNT_SHIFT | 1117 (hw->dma_chnl - 1) << ALX_DMA_RCHNL_SEL_SHIFT; 1118 alx_write_mem32(hw, ALX_DMA, val); 1119 1120 /* default multi-tx-q weights */ 1121 val = ALX_WRR_PRI_RESTRICT_NONE << ALX_WRR_PRI_SHIFT | 1122 4 << ALX_WRR_PRI0_SHIFT | 1123 4 << ALX_WRR_PRI1_SHIFT | 1124 4 << ALX_WRR_PRI2_SHIFT | 1125 4 << ALX_WRR_PRI3_SHIFT; 1126 alx_write_mem32(hw, ALX_WRR, val); 1127 } 1128 1129 static inline u32 alx_speed_to_ethadv(int speed) 1130 { 1131 switch (speed) { 1132 case SPEED_1000 + DUPLEX_FULL: 1133 return ADVERTISED_1000baseT_Full; 1134 case SPEED_100 + DUPLEX_FULL: 1135 return ADVERTISED_100baseT_Full; 1136 case SPEED_100 + DUPLEX_HALF: 1137 return ADVERTISED_10baseT_Half; 1138 case SPEED_10 + DUPLEX_FULL: 1139 return ADVERTISED_10baseT_Full; 1140 case SPEED_10 + DUPLEX_HALF: 1141 return ADVERTISED_10baseT_Half; 1142 default: 1143 return 0; 1144 } 1145 } 1146 1147 int alx_select_powersaving_speed(struct alx_hw *hw, int *speed) 1148 { 1149 int i, err, spd; 1150 u16 lpa; 1151 1152 err = alx_get_phy_link(hw, &spd); 1153 if (err < 0) 1154 return err; 1155 1156 if (spd == SPEED_UNKNOWN) 1157 return 0; 1158 1159 err = alx_read_phy_reg(hw, MII_LPA, &lpa); 1160 if (err) 1161 return err; 1162 1163 if (!(lpa & LPA_LPACK)) { 1164 *speed = spd; 1165 return 0; 1166 } 1167 1168 if (lpa & LPA_10FULL) 1169 *speed = SPEED_10 + DUPLEX_FULL; 1170 else if (lpa & LPA_10HALF) 1171 *speed = SPEED_10 + DUPLEX_HALF; 1172 else if (lpa & LPA_100FULL) 1173 *speed = SPEED_100 + DUPLEX_FULL; 1174 else 1175 *speed = SPEED_100 + DUPLEX_HALF; 1176 1177 if (*speed != spd) { 1178 err = alx_write_phy_reg(hw, ALX_MII_IER, 0); 1179 if (err) 1180 return err; 1181 err = alx_setup_speed_duplex(hw, 1182 alx_speed_to_ethadv(*speed) | 1183 ADVERTISED_Autoneg, 1184 ALX_FC_ANEG | ALX_FC_RX | 1185 ALX_FC_TX); 1186 if (err) 1187 return err; 1188 1189 /* wait for linkup */ 1190 for (i = 0; i < ALX_MAX_SETUP_LNK_CYCLE; i++) { 1191 int speed2; 1192 1193 msleep(100); 1194 1195 err = alx_get_phy_link(hw, &speed2); 1196 if (err < 0) 1197 return err; 1198 if (speed2 != SPEED_UNKNOWN) 1199 break; 1200 } 1201 if (i == ALX_MAX_SETUP_LNK_CYCLE) 1202 return -ETIMEDOUT; 1203 } 1204 1205 return 0; 1206 } 1207 1208 bool alx_get_phy_info(struct alx_hw *hw) 1209 { 1210 u16 devs1, devs2; 1211 1212 if (alx_read_phy_reg(hw, MII_PHYSID1, &hw->phy_id[0]) || 1213 alx_read_phy_reg(hw, MII_PHYSID2, &hw->phy_id[1])) 1214 return false; 1215 1216 /* since we haven't PMA/PMD status2 register, we can't 1217 * use mdio45_probe function for prtad and mmds. 1218 * use fixed MMD3 to get mmds. 1219 */ 1220 if (alx_read_phy_ext(hw, 3, MDIO_DEVS1, &devs1) || 1221 alx_read_phy_ext(hw, 3, MDIO_DEVS2, &devs2)) 1222 return false; 1223 hw->mdio.mmds = devs1 | devs2 << 16; 1224 1225 return true; 1226 } 1227