1 // SPDX-License-Identifier: GPL-2.0 2 /* Atheros AR71xx built-in ethernet mac driver 3 * 4 * Copyright (C) 2019 Oleksij Rempel <o.rempel@pengutronix.de> 5 * 6 * List of authors contributed to this driver before mainlining: 7 * Alexander Couzens <lynxis@fe80.eu> 8 * Christian Lamparter <chunkeey@gmail.com> 9 * Chuanhong Guo <gch981213@gmail.com> 10 * Daniel F. Dickinson <cshored@thecshore.com> 11 * David Bauer <mail@david-bauer.net> 12 * Felix Fietkau <nbd@nbd.name> 13 * Gabor Juhos <juhosg@freemail.hu> 14 * Hauke Mehrtens <hauke@hauke-m.de> 15 * Johann Neuhauser <johann@it-neuhauser.de> 16 * John Crispin <john@phrozen.org> 17 * Jo-Philipp Wich <jo@mein.io> 18 * Koen Vandeputte <koen.vandeputte@ncentric.com> 19 * Lucian Cristian <lucian.cristian@gmail.com> 20 * Matt Merhar <mattmerhar@protonmail.com> 21 * Milan Krstic <milan.krstic@gmail.com> 22 * Petr Štetiar <ynezz@true.cz> 23 * Rosen Penev <rosenp@gmail.com> 24 * Stephen Walker <stephendwalker+github@gmail.com> 25 * Vittorio Gambaletta <openwrt@vittgam.net> 26 * Weijie Gao <hackpascal@gmail.com> 27 * Imre Kaloz <kaloz@openwrt.org> 28 */ 29 30 #include <linux/if_vlan.h> 31 #include <linux/mfd/syscon.h> 32 #include <linux/of_mdio.h> 33 #include <linux/of_net.h> 34 #include <linux/of_platform.h> 35 #include <linux/phylink.h> 36 #include <linux/regmap.h> 37 #include <linux/reset.h> 38 #include <linux/clk.h> 39 #include <linux/io.h> 40 #include <net/selftests.h> 41 42 /* For our NAPI weight bigger does *NOT* mean better - it means more 43 * D-cache misses and lots more wasted cycles than we'll ever 44 * possibly gain from saving instructions. 45 */ 46 #define AG71XX_NAPI_WEIGHT 32 47 #define AG71XX_OOM_REFILL (1 + HZ / 10) 48 49 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) 50 #define AG71XX_INT_TX (AG71XX_INT_TX_PS) 51 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) 52 53 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) 54 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) 55 56 #define AG71XX_TX_MTU_LEN 1540 57 58 #define AG71XX_TX_RING_SPLIT 512 59 #define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \ 60 AG71XX_TX_RING_SPLIT) 61 #define AG71XX_TX_RING_SIZE_DEFAULT 128 62 #define AG71XX_RX_RING_SIZE_DEFAULT 256 63 64 #define AG71XX_MDIO_RETRY 1000 65 #define AG71XX_MDIO_DELAY 5 66 #define AG71XX_MDIO_MAX_CLK 5000000 67 68 /* Register offsets */ 69 #define AG71XX_REG_MAC_CFG1 0x0000 70 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */ 71 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ 72 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */ 73 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ 74 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ 75 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ 76 #define MAC_CFG1_SR BIT(31) /* Soft Reset */ 77 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ 78 MAC_CFG1_SRX | MAC_CFG1_STX) 79 80 #define AG71XX_REG_MAC_CFG2 0x0004 81 #define MAC_CFG2_FDX BIT(0) 82 #define MAC_CFG2_PAD_CRC_EN BIT(2) 83 #define MAC_CFG2_LEN_CHECK BIT(4) 84 #define MAC_CFG2_IF_1000 BIT(9) 85 #define MAC_CFG2_IF_10_100 BIT(8) 86 87 #define AG71XX_REG_MAC_MFL 0x0010 88 89 #define AG71XX_REG_MII_CFG 0x0020 90 #define MII_CFG_CLK_DIV_4 0 91 #define MII_CFG_CLK_DIV_6 2 92 #define MII_CFG_CLK_DIV_8 3 93 #define MII_CFG_CLK_DIV_10 4 94 #define MII_CFG_CLK_DIV_14 5 95 #define MII_CFG_CLK_DIV_20 6 96 #define MII_CFG_CLK_DIV_28 7 97 #define MII_CFG_CLK_DIV_34 8 98 #define MII_CFG_CLK_DIV_42 9 99 #define MII_CFG_CLK_DIV_50 10 100 #define MII_CFG_CLK_DIV_58 11 101 #define MII_CFG_CLK_DIV_66 12 102 #define MII_CFG_CLK_DIV_74 13 103 #define MII_CFG_CLK_DIV_82 14 104 #define MII_CFG_CLK_DIV_98 15 105 #define MII_CFG_RESET BIT(31) 106 107 #define AG71XX_REG_MII_CMD 0x0024 108 #define MII_CMD_READ BIT(0) 109 110 #define AG71XX_REG_MII_ADDR 0x0028 111 #define MII_ADDR_SHIFT 8 112 113 #define AG71XX_REG_MII_CTRL 0x002c 114 #define AG71XX_REG_MII_STATUS 0x0030 115 #define AG71XX_REG_MII_IND 0x0034 116 #define MII_IND_BUSY BIT(0) 117 #define MII_IND_INVALID BIT(2) 118 119 #define AG71XX_REG_MAC_IFCTL 0x0038 120 #define MAC_IFCTL_SPEED BIT(16) 121 122 #define AG71XX_REG_MAC_ADDR1 0x0040 123 #define AG71XX_REG_MAC_ADDR2 0x0044 124 #define AG71XX_REG_FIFO_CFG0 0x0048 125 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ 126 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ 127 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ 128 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ 129 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ 130 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ 131 | FIFO_CFG0_TXS | FIFO_CFG0_TXF) 132 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) 133 134 #define FIFO_CFG0_ENABLE_SHIFT 8 135 136 #define AG71XX_REG_FIFO_CFG1 0x004c 137 #define AG71XX_REG_FIFO_CFG2 0x0050 138 #define AG71XX_REG_FIFO_CFG3 0x0054 139 #define AG71XX_REG_FIFO_CFG4 0x0058 140 #define FIFO_CFG4_DE BIT(0) /* Drop Event */ 141 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ 142 #define FIFO_CFG4_FC BIT(2) /* False Carrier */ 143 #define FIFO_CFG4_CE BIT(3) /* Code Error */ 144 #define FIFO_CFG4_CR BIT(4) /* CRC error */ 145 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ 146 #define FIFO_CFG4_LO BIT(6) /* Length out of range */ 147 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */ 148 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ 149 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ 150 #define FIFO_CFG4_DR BIT(10) /* Dribble */ 151 #define FIFO_CFG4_LE BIT(11) /* Long Event */ 152 #define FIFO_CFG4_CF BIT(12) /* Control Frame */ 153 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */ 154 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ 155 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ 156 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ 157 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ 158 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ 159 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ 160 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ 161 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ 162 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ 163 FIFO_CFG4_VT) 164 165 #define AG71XX_REG_FIFO_CFG5 0x005c 166 #define FIFO_CFG5_DE BIT(0) /* Drop Event */ 167 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ 168 #define FIFO_CFG5_FC BIT(2) /* False Carrier */ 169 #define FIFO_CFG5_CE BIT(3) /* Code Error */ 170 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ 171 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ 172 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */ 173 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ 174 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ 175 #define FIFO_CFG5_DR BIT(9) /* Dribble */ 176 #define FIFO_CFG5_CF BIT(10) /* Control Frame */ 177 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */ 178 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ 179 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ 180 #define FIFO_CFG5_LE BIT(14) /* Long Event */ 181 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ 182 #define FIFO_CFG5_16 BIT(16) /* unknown */ 183 #define FIFO_CFG5_17 BIT(17) /* unknown */ 184 #define FIFO_CFG5_SF BIT(18) /* Short Frame */ 185 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */ 186 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ 187 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ 188 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ 189 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ 190 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ 191 FIFO_CFG5_17 | FIFO_CFG5_SF) 192 193 #define AG71XX_REG_TX_CTRL 0x0180 194 #define TX_CTRL_TXE BIT(0) /* Tx Enable */ 195 196 #define AG71XX_REG_TX_DESC 0x0184 197 #define AG71XX_REG_TX_STATUS 0x0188 198 #define TX_STATUS_PS BIT(0) /* Packet Sent */ 199 #define TX_STATUS_UR BIT(1) /* Tx Underrun */ 200 #define TX_STATUS_BE BIT(3) /* Bus Error */ 201 202 #define AG71XX_REG_RX_CTRL 0x018c 203 #define RX_CTRL_RXE BIT(0) /* Rx Enable */ 204 205 #define AG71XX_DMA_RETRY 10 206 #define AG71XX_DMA_DELAY 1 207 208 #define AG71XX_REG_RX_DESC 0x0190 209 #define AG71XX_REG_RX_STATUS 0x0194 210 #define RX_STATUS_PR BIT(0) /* Packet Received */ 211 #define RX_STATUS_OF BIT(2) /* Rx Overflow */ 212 #define RX_STATUS_BE BIT(3) /* Bus Error */ 213 214 #define AG71XX_REG_INT_ENABLE 0x0198 215 #define AG71XX_REG_INT_STATUS 0x019c 216 #define AG71XX_INT_TX_PS BIT(0) 217 #define AG71XX_INT_TX_UR BIT(1) 218 #define AG71XX_INT_TX_BE BIT(3) 219 #define AG71XX_INT_RX_PR BIT(4) 220 #define AG71XX_INT_RX_OF BIT(6) 221 #define AG71XX_INT_RX_BE BIT(7) 222 223 #define AG71XX_REG_FIFO_DEPTH 0x01a8 224 #define AG71XX_REG_RX_SM 0x01b0 225 #define AG71XX_REG_TX_SM 0x01b4 226 227 #define AG71XX_DEFAULT_MSG_ENABLE \ 228 (NETIF_MSG_DRV \ 229 | NETIF_MSG_PROBE \ 230 | NETIF_MSG_LINK \ 231 | NETIF_MSG_TIMER \ 232 | NETIF_MSG_IFDOWN \ 233 | NETIF_MSG_IFUP \ 234 | NETIF_MSG_RX_ERR \ 235 | NETIF_MSG_TX_ERR) 236 237 struct ag71xx_statistic { 238 unsigned short offset; 239 u32 mask; 240 const char name[ETH_GSTRING_LEN]; 241 }; 242 243 static const struct ag71xx_statistic ag71xx_statistics[] = { 244 { 0x0080, GENMASK(17, 0), "Tx/Rx 64 Byte", }, 245 { 0x0084, GENMASK(17, 0), "Tx/Rx 65-127 Byte", }, 246 { 0x0088, GENMASK(17, 0), "Tx/Rx 128-255 Byte", }, 247 { 0x008C, GENMASK(17, 0), "Tx/Rx 256-511 Byte", }, 248 { 0x0090, GENMASK(17, 0), "Tx/Rx 512-1023 Byte", }, 249 { 0x0094, GENMASK(17, 0), "Tx/Rx 1024-1518 Byte", }, 250 { 0x0098, GENMASK(17, 0), "Tx/Rx 1519-1522 Byte VLAN", }, 251 { 0x009C, GENMASK(23, 0), "Rx Byte", }, 252 { 0x00A0, GENMASK(17, 0), "Rx Packet", }, 253 { 0x00A4, GENMASK(11, 0), "Rx FCS Error", }, 254 { 0x00A8, GENMASK(17, 0), "Rx Multicast Packet", }, 255 { 0x00AC, GENMASK(21, 0), "Rx Broadcast Packet", }, 256 { 0x00B0, GENMASK(17, 0), "Rx Control Frame Packet", }, 257 { 0x00B4, GENMASK(11, 0), "Rx Pause Frame Packet", }, 258 { 0x00B8, GENMASK(11, 0), "Rx Unknown OPCode Packet", }, 259 { 0x00BC, GENMASK(11, 0), "Rx Alignment Error", }, 260 { 0x00C0, GENMASK(15, 0), "Rx Frame Length Error", }, 261 { 0x00C4, GENMASK(11, 0), "Rx Code Error", }, 262 { 0x00C8, GENMASK(11, 0), "Rx Carrier Sense Error", }, 263 { 0x00CC, GENMASK(11, 0), "Rx Undersize Packet", }, 264 { 0x00D0, GENMASK(11, 0), "Rx Oversize Packet", }, 265 { 0x00D4, GENMASK(11, 0), "Rx Fragments", }, 266 { 0x00D8, GENMASK(11, 0), "Rx Jabber", }, 267 { 0x00DC, GENMASK(11, 0), "Rx Dropped Packet", }, 268 { 0x00E0, GENMASK(23, 0), "Tx Byte", }, 269 { 0x00E4, GENMASK(17, 0), "Tx Packet", }, 270 { 0x00E8, GENMASK(17, 0), "Tx Multicast Packet", }, 271 { 0x00EC, GENMASK(17, 0), "Tx Broadcast Packet", }, 272 { 0x00F0, GENMASK(11, 0), "Tx Pause Control Frame", }, 273 { 0x00F4, GENMASK(11, 0), "Tx Deferral Packet", }, 274 { 0x00F8, GENMASK(11, 0), "Tx Excessive Deferral Packet", }, 275 { 0x00FC, GENMASK(11, 0), "Tx Single Collision Packet", }, 276 { 0x0100, GENMASK(11, 0), "Tx Multiple Collision", }, 277 { 0x0104, GENMASK(11, 0), "Tx Late Collision Packet", }, 278 { 0x0108, GENMASK(11, 0), "Tx Excessive Collision Packet", }, 279 { 0x010C, GENMASK(12, 0), "Tx Total Collision", }, 280 { 0x0110, GENMASK(11, 0), "Tx Pause Frames Honored", }, 281 { 0x0114, GENMASK(11, 0), "Tx Drop Frame", }, 282 { 0x0118, GENMASK(11, 0), "Tx Jabber Frame", }, 283 { 0x011C, GENMASK(11, 0), "Tx FCS Error", }, 284 { 0x0120, GENMASK(11, 0), "Tx Control Frame", }, 285 { 0x0124, GENMASK(11, 0), "Tx Oversize Frame", }, 286 { 0x0128, GENMASK(11, 0), "Tx Undersize Frame", }, 287 { 0x012C, GENMASK(11, 0), "Tx Fragment", }, 288 }; 289 290 #define DESC_EMPTY BIT(31) 291 #define DESC_MORE BIT(24) 292 #define DESC_PKTLEN_M 0xfff 293 struct ag71xx_desc { 294 u32 data; 295 u32 ctrl; 296 u32 next; 297 u32 pad; 298 } __aligned(4); 299 300 #define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \ 301 L1_CACHE_BYTES) 302 303 struct ag71xx_buf { 304 union { 305 struct { 306 struct sk_buff *skb; 307 unsigned int len; 308 } tx; 309 struct { 310 dma_addr_t dma_addr; 311 void *rx_buf; 312 } rx; 313 }; 314 }; 315 316 struct ag71xx_ring { 317 /* "Hot" fields in the data path. */ 318 unsigned int curr; 319 unsigned int dirty; 320 321 /* "Cold" fields - not used in the data path. */ 322 struct ag71xx_buf *buf; 323 u16 order; 324 u16 desc_split; 325 dma_addr_t descs_dma; 326 u8 *descs_cpu; 327 }; 328 329 enum ag71xx_type { 330 AR7100, 331 AR7240, 332 AR9130, 333 AR9330, 334 AR9340, 335 QCA9530, 336 QCA9550, 337 }; 338 339 struct ag71xx_dcfg { 340 u32 max_frame_len; 341 const u32 *fifodata; 342 u16 desc_pktlen_mask; 343 bool tx_hang_workaround; 344 enum ag71xx_type type; 345 }; 346 347 struct ag71xx { 348 /* Critical data related to the per-packet data path are clustered 349 * early in this structure to help improve the D-cache footprint. 350 */ 351 struct ag71xx_ring rx_ring ____cacheline_aligned; 352 struct ag71xx_ring tx_ring ____cacheline_aligned; 353 354 u16 rx_buf_size; 355 u8 rx_buf_offset; 356 357 struct net_device *ndev; 358 struct platform_device *pdev; 359 struct napi_struct napi; 360 u32 msg_enable; 361 const struct ag71xx_dcfg *dcfg; 362 363 /* From this point onwards we're not looking at per-packet fields. */ 364 void __iomem *mac_base; 365 366 struct ag71xx_desc *stop_desc; 367 dma_addr_t stop_desc_dma; 368 369 phy_interface_t phy_if_mode; 370 struct phylink *phylink; 371 struct phylink_config phylink_config; 372 373 struct delayed_work restart_work; 374 struct timer_list oom_timer; 375 376 struct reset_control *mac_reset; 377 378 u32 fifodata[3]; 379 int mac_idx; 380 381 struct reset_control *mdio_reset; 382 struct mii_bus *mii_bus; 383 struct clk *clk_mdio; 384 struct clk *clk_eth; 385 }; 386 387 static int ag71xx_desc_empty(struct ag71xx_desc *desc) 388 { 389 return (desc->ctrl & DESC_EMPTY) != 0; 390 } 391 392 static struct ag71xx_desc *ag71xx_ring_desc(struct ag71xx_ring *ring, int idx) 393 { 394 return (struct ag71xx_desc *)&ring->descs_cpu[idx * AG71XX_DESC_SIZE]; 395 } 396 397 static int ag71xx_ring_size_order(int size) 398 { 399 return fls(size - 1); 400 } 401 402 static bool ag71xx_is(struct ag71xx *ag, enum ag71xx_type type) 403 { 404 return ag->dcfg->type == type; 405 } 406 407 static void ag71xx_wr(struct ag71xx *ag, unsigned int reg, u32 value) 408 { 409 iowrite32(value, ag->mac_base + reg); 410 /* flush write */ 411 (void)ioread32(ag->mac_base + reg); 412 } 413 414 static u32 ag71xx_rr(struct ag71xx *ag, unsigned int reg) 415 { 416 return ioread32(ag->mac_base + reg); 417 } 418 419 static void ag71xx_sb(struct ag71xx *ag, unsigned int reg, u32 mask) 420 { 421 void __iomem *r; 422 423 r = ag->mac_base + reg; 424 iowrite32(ioread32(r) | mask, r); 425 /* flush write */ 426 (void)ioread32(r); 427 } 428 429 static void ag71xx_cb(struct ag71xx *ag, unsigned int reg, u32 mask) 430 { 431 void __iomem *r; 432 433 r = ag->mac_base + reg; 434 iowrite32(ioread32(r) & ~mask, r); 435 /* flush write */ 436 (void)ioread32(r); 437 } 438 439 static void ag71xx_int_enable(struct ag71xx *ag, u32 ints) 440 { 441 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); 442 } 443 444 static void ag71xx_int_disable(struct ag71xx *ag, u32 ints) 445 { 446 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); 447 } 448 449 static void ag71xx_get_drvinfo(struct net_device *ndev, 450 struct ethtool_drvinfo *info) 451 { 452 struct ag71xx *ag = netdev_priv(ndev); 453 454 strlcpy(info->driver, "ag71xx", sizeof(info->driver)); 455 strlcpy(info->bus_info, of_node_full_name(ag->pdev->dev.of_node), 456 sizeof(info->bus_info)); 457 } 458 459 static int ag71xx_get_link_ksettings(struct net_device *ndev, 460 struct ethtool_link_ksettings *kset) 461 { 462 struct ag71xx *ag = netdev_priv(ndev); 463 464 return phylink_ethtool_ksettings_get(ag->phylink, kset); 465 } 466 467 static int ag71xx_set_link_ksettings(struct net_device *ndev, 468 const struct ethtool_link_ksettings *kset) 469 { 470 struct ag71xx *ag = netdev_priv(ndev); 471 472 return phylink_ethtool_ksettings_set(ag->phylink, kset); 473 } 474 475 static int ag71xx_ethtool_nway_reset(struct net_device *ndev) 476 { 477 struct ag71xx *ag = netdev_priv(ndev); 478 479 return phylink_ethtool_nway_reset(ag->phylink); 480 } 481 482 static void ag71xx_ethtool_get_pauseparam(struct net_device *ndev, 483 struct ethtool_pauseparam *pause) 484 { 485 struct ag71xx *ag = netdev_priv(ndev); 486 487 phylink_ethtool_get_pauseparam(ag->phylink, pause); 488 } 489 490 static int ag71xx_ethtool_set_pauseparam(struct net_device *ndev, 491 struct ethtool_pauseparam *pause) 492 { 493 struct ag71xx *ag = netdev_priv(ndev); 494 495 return phylink_ethtool_set_pauseparam(ag->phylink, pause); 496 } 497 498 static void ag71xx_ethtool_get_strings(struct net_device *netdev, u32 sset, 499 u8 *data) 500 { 501 int i; 502 503 switch (sset) { 504 case ETH_SS_STATS: 505 for (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++) 506 memcpy(data + i * ETH_GSTRING_LEN, 507 ag71xx_statistics[i].name, ETH_GSTRING_LEN); 508 break; 509 case ETH_SS_TEST: 510 net_selftest_get_strings(data); 511 break; 512 } 513 } 514 515 static void ag71xx_ethtool_get_stats(struct net_device *ndev, 516 struct ethtool_stats *stats, u64 *data) 517 { 518 struct ag71xx *ag = netdev_priv(ndev); 519 int i; 520 521 for (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++) 522 *data++ = ag71xx_rr(ag, ag71xx_statistics[i].offset) 523 & ag71xx_statistics[i].mask; 524 } 525 526 static int ag71xx_ethtool_get_sset_count(struct net_device *ndev, int sset) 527 { 528 switch (sset) { 529 case ETH_SS_STATS: 530 return ARRAY_SIZE(ag71xx_statistics); 531 case ETH_SS_TEST: 532 return net_selftest_get_count(); 533 default: 534 return -EOPNOTSUPP; 535 } 536 } 537 538 static const struct ethtool_ops ag71xx_ethtool_ops = { 539 .get_drvinfo = ag71xx_get_drvinfo, 540 .get_link = ethtool_op_get_link, 541 .get_ts_info = ethtool_op_get_ts_info, 542 .get_link_ksettings = ag71xx_get_link_ksettings, 543 .set_link_ksettings = ag71xx_set_link_ksettings, 544 .nway_reset = ag71xx_ethtool_nway_reset, 545 .get_pauseparam = ag71xx_ethtool_get_pauseparam, 546 .set_pauseparam = ag71xx_ethtool_set_pauseparam, 547 .get_strings = ag71xx_ethtool_get_strings, 548 .get_ethtool_stats = ag71xx_ethtool_get_stats, 549 .get_sset_count = ag71xx_ethtool_get_sset_count, 550 .self_test = net_selftest, 551 }; 552 553 static int ag71xx_mdio_wait_busy(struct ag71xx *ag) 554 { 555 struct net_device *ndev = ag->ndev; 556 int i; 557 558 for (i = 0; i < AG71XX_MDIO_RETRY; i++) { 559 u32 busy; 560 561 udelay(AG71XX_MDIO_DELAY); 562 563 busy = ag71xx_rr(ag, AG71XX_REG_MII_IND); 564 if (!busy) 565 return 0; 566 567 udelay(AG71XX_MDIO_DELAY); 568 } 569 570 netif_err(ag, link, ndev, "MDIO operation timed out\n"); 571 572 return -ETIMEDOUT; 573 } 574 575 static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg) 576 { 577 struct ag71xx *ag = bus->priv; 578 int err, val; 579 580 err = ag71xx_mdio_wait_busy(ag); 581 if (err) 582 return err; 583 584 ag71xx_wr(ag, AG71XX_REG_MII_ADDR, 585 ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff)); 586 /* enable read mode */ 587 ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ); 588 589 err = ag71xx_mdio_wait_busy(ag); 590 if (err) 591 return err; 592 593 val = ag71xx_rr(ag, AG71XX_REG_MII_STATUS); 594 /* disable read mode */ 595 ag71xx_wr(ag, AG71XX_REG_MII_CMD, 0); 596 597 netif_dbg(ag, link, ag->ndev, "mii_read: addr=%04x, reg=%04x, value=%04x\n", 598 addr, reg, val); 599 600 return val; 601 } 602 603 static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg, 604 u16 val) 605 { 606 struct ag71xx *ag = bus->priv; 607 608 netif_dbg(ag, link, ag->ndev, "mii_write: addr=%04x, reg=%04x, value=%04x\n", 609 addr, reg, val); 610 611 ag71xx_wr(ag, AG71XX_REG_MII_ADDR, 612 ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff)); 613 ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val); 614 615 return ag71xx_mdio_wait_busy(ag); 616 } 617 618 static const u32 ar71xx_mdio_div_table[] = { 619 4, 4, 6, 8, 10, 14, 20, 28, 620 }; 621 622 static const u32 ar7240_mdio_div_table[] = { 623 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96, 624 }; 625 626 static const u32 ar933x_mdio_div_table[] = { 627 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98, 628 }; 629 630 static int ag71xx_mdio_get_divider(struct ag71xx *ag, u32 *div) 631 { 632 unsigned long ref_clock; 633 const u32 *table; 634 int ndivs, i; 635 636 ref_clock = clk_get_rate(ag->clk_mdio); 637 if (!ref_clock) 638 return -EINVAL; 639 640 if (ag71xx_is(ag, AR9330) || ag71xx_is(ag, AR9340)) { 641 table = ar933x_mdio_div_table; 642 ndivs = ARRAY_SIZE(ar933x_mdio_div_table); 643 } else if (ag71xx_is(ag, AR7240)) { 644 table = ar7240_mdio_div_table; 645 ndivs = ARRAY_SIZE(ar7240_mdio_div_table); 646 } else { 647 table = ar71xx_mdio_div_table; 648 ndivs = ARRAY_SIZE(ar71xx_mdio_div_table); 649 } 650 651 for (i = 0; i < ndivs; i++) { 652 unsigned long t; 653 654 t = ref_clock / table[i]; 655 if (t <= AG71XX_MDIO_MAX_CLK) { 656 *div = i; 657 return 0; 658 } 659 } 660 661 return -ENOENT; 662 } 663 664 static int ag71xx_mdio_reset(struct mii_bus *bus) 665 { 666 struct ag71xx *ag = bus->priv; 667 int err; 668 u32 t; 669 670 err = ag71xx_mdio_get_divider(ag, &t); 671 if (err) 672 return err; 673 674 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); 675 usleep_range(100, 200); 676 677 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t); 678 usleep_range(100, 200); 679 680 return 0; 681 } 682 683 static int ag71xx_mdio_probe(struct ag71xx *ag) 684 { 685 struct device *dev = &ag->pdev->dev; 686 struct net_device *ndev = ag->ndev; 687 static struct mii_bus *mii_bus; 688 struct device_node *np, *mnp; 689 int err; 690 691 np = dev->of_node; 692 ag->mii_bus = NULL; 693 694 ag->clk_mdio = devm_clk_get(dev, "mdio"); 695 if (IS_ERR(ag->clk_mdio)) { 696 netif_err(ag, probe, ndev, "Failed to get mdio clk.\n"); 697 return PTR_ERR(ag->clk_mdio); 698 } 699 700 err = clk_prepare_enable(ag->clk_mdio); 701 if (err) { 702 netif_err(ag, probe, ndev, "Failed to enable mdio clk.\n"); 703 return err; 704 } 705 706 mii_bus = devm_mdiobus_alloc(dev); 707 if (!mii_bus) { 708 err = -ENOMEM; 709 goto mdio_err_put_clk; 710 } 711 712 ag->mdio_reset = of_reset_control_get_exclusive(np, "mdio"); 713 if (IS_ERR(ag->mdio_reset)) { 714 netif_err(ag, probe, ndev, "Failed to get reset mdio.\n"); 715 err = PTR_ERR(ag->mdio_reset); 716 goto mdio_err_put_clk; 717 } 718 719 mii_bus->name = "ag71xx_mdio"; 720 mii_bus->read = ag71xx_mdio_mii_read; 721 mii_bus->write = ag71xx_mdio_mii_write; 722 mii_bus->reset = ag71xx_mdio_reset; 723 mii_bus->priv = ag; 724 mii_bus->parent = dev; 725 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, ag->mac_idx); 726 727 if (!IS_ERR(ag->mdio_reset)) { 728 reset_control_assert(ag->mdio_reset); 729 msleep(100); 730 reset_control_deassert(ag->mdio_reset); 731 msleep(200); 732 } 733 734 mnp = of_get_child_by_name(np, "mdio"); 735 err = of_mdiobus_register(mii_bus, mnp); 736 of_node_put(mnp); 737 if (err) 738 goto mdio_err_put_clk; 739 740 ag->mii_bus = mii_bus; 741 742 return 0; 743 744 mdio_err_put_clk: 745 clk_disable_unprepare(ag->clk_mdio); 746 return err; 747 } 748 749 static void ag71xx_mdio_remove(struct ag71xx *ag) 750 { 751 if (ag->mii_bus) 752 mdiobus_unregister(ag->mii_bus); 753 clk_disable_unprepare(ag->clk_mdio); 754 } 755 756 static void ag71xx_hw_stop(struct ag71xx *ag) 757 { 758 /* disable all interrupts and stop the rx/tx engine */ 759 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); 760 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); 761 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); 762 } 763 764 static bool ag71xx_check_dma_stuck(struct ag71xx *ag) 765 { 766 unsigned long timestamp; 767 u32 rx_sm, tx_sm, rx_fd; 768 769 timestamp = netdev_get_tx_queue(ag->ndev, 0)->trans_start; 770 if (likely(time_before(jiffies, timestamp + HZ / 10))) 771 return false; 772 773 if (!netif_carrier_ok(ag->ndev)) 774 return false; 775 776 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM); 777 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6) 778 return true; 779 780 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM); 781 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH); 782 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) && 783 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0) 784 return true; 785 786 return false; 787 } 788 789 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush) 790 { 791 struct ag71xx_ring *ring = &ag->tx_ring; 792 int sent = 0, bytes_compl = 0, n = 0; 793 struct net_device *ndev = ag->ndev; 794 int ring_mask, ring_size; 795 bool dma_stuck = false; 796 797 ring_mask = BIT(ring->order) - 1; 798 ring_size = BIT(ring->order); 799 800 netif_dbg(ag, tx_queued, ndev, "processing TX ring\n"); 801 802 while (ring->dirty + n != ring->curr) { 803 struct ag71xx_desc *desc; 804 struct sk_buff *skb; 805 unsigned int i; 806 807 i = (ring->dirty + n) & ring_mask; 808 desc = ag71xx_ring_desc(ring, i); 809 skb = ring->buf[i].tx.skb; 810 811 if (!flush && !ag71xx_desc_empty(desc)) { 812 if (ag->dcfg->tx_hang_workaround && 813 ag71xx_check_dma_stuck(ag)) { 814 schedule_delayed_work(&ag->restart_work, 815 HZ / 2); 816 dma_stuck = true; 817 } 818 break; 819 } 820 821 if (flush) 822 desc->ctrl |= DESC_EMPTY; 823 824 n++; 825 if (!skb) 826 continue; 827 828 dev_kfree_skb_any(skb); 829 ring->buf[i].tx.skb = NULL; 830 831 bytes_compl += ring->buf[i].tx.len; 832 833 sent++; 834 ring->dirty += n; 835 836 while (n > 0) { 837 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); 838 n--; 839 } 840 } 841 842 netif_dbg(ag, tx_done, ndev, "%d packets sent out\n", sent); 843 844 if (!sent) 845 return 0; 846 847 ag->ndev->stats.tx_bytes += bytes_compl; 848 ag->ndev->stats.tx_packets += sent; 849 850 netdev_completed_queue(ag->ndev, sent, bytes_compl); 851 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4) 852 netif_wake_queue(ag->ndev); 853 854 if (!dma_stuck) 855 cancel_delayed_work(&ag->restart_work); 856 857 return sent; 858 } 859 860 static void ag71xx_dma_wait_stop(struct ag71xx *ag) 861 { 862 struct net_device *ndev = ag->ndev; 863 int i; 864 865 for (i = 0; i < AG71XX_DMA_RETRY; i++) { 866 u32 rx, tx; 867 868 mdelay(AG71XX_DMA_DELAY); 869 870 rx = ag71xx_rr(ag, AG71XX_REG_RX_CTRL) & RX_CTRL_RXE; 871 tx = ag71xx_rr(ag, AG71XX_REG_TX_CTRL) & TX_CTRL_TXE; 872 if (!rx && !tx) 873 return; 874 } 875 876 netif_err(ag, hw, ndev, "DMA stop operation timed out\n"); 877 } 878 879 static void ag71xx_dma_reset(struct ag71xx *ag) 880 { 881 struct net_device *ndev = ag->ndev; 882 u32 val; 883 int i; 884 885 /* stop RX and TX */ 886 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); 887 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); 888 889 /* give the hardware some time to really stop all rx/tx activity 890 * clearing the descriptors too early causes random memory corruption 891 */ 892 ag71xx_dma_wait_stop(ag); 893 894 /* clear descriptor addresses */ 895 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma); 896 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma); 897 898 /* clear pending RX/TX interrupts */ 899 for (i = 0; i < 256; i++) { 900 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); 901 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); 902 } 903 904 /* clear pending errors */ 905 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); 906 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); 907 908 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); 909 if (val) 910 netif_err(ag, hw, ndev, "unable to clear DMA Rx status: %08x\n", 911 val); 912 913 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); 914 915 /* mask out reserved bits */ 916 val &= ~0xff000000; 917 918 if (val) 919 netif_err(ag, hw, ndev, "unable to clear DMA Tx status: %08x\n", 920 val); 921 } 922 923 static void ag71xx_hw_setup(struct ag71xx *ag) 924 { 925 u32 init = MAC_CFG1_INIT; 926 927 /* setup MAC configuration registers */ 928 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init); 929 930 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, 931 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); 932 933 /* setup max frame length to zero */ 934 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0); 935 936 /* setup FIFO configuration registers */ 937 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); 938 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]); 939 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]); 940 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); 941 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); 942 } 943 944 static unsigned int ag71xx_max_frame_len(unsigned int mtu) 945 { 946 return ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN; 947 } 948 949 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) 950 { 951 u32 t; 952 953 t = (((u32)mac[5]) << 24) | (((u32)mac[4]) << 16) 954 | (((u32)mac[3]) << 8) | ((u32)mac[2]); 955 956 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); 957 958 t = (((u32)mac[1]) << 24) | (((u32)mac[0]) << 16); 959 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); 960 } 961 962 static void ag71xx_fast_reset(struct ag71xx *ag) 963 { 964 struct net_device *dev = ag->ndev; 965 u32 rx_ds; 966 u32 mii_reg; 967 968 ag71xx_hw_stop(ag); 969 970 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG); 971 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC); 972 973 ag71xx_tx_packets(ag, true); 974 975 reset_control_assert(ag->mac_reset); 976 usleep_range(10, 20); 977 reset_control_deassert(ag->mac_reset); 978 usleep_range(10, 20); 979 980 ag71xx_dma_reset(ag); 981 ag71xx_hw_setup(ag); 982 ag->tx_ring.curr = 0; 983 ag->tx_ring.dirty = 0; 984 netdev_reset_queue(ag->ndev); 985 986 /* setup max frame length */ 987 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 988 ag71xx_max_frame_len(ag->ndev->mtu)); 989 990 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds); 991 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); 992 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg); 993 994 ag71xx_hw_set_macaddr(ag, dev->dev_addr); 995 } 996 997 static void ag71xx_hw_start(struct ag71xx *ag) 998 { 999 /* start RX engine */ 1000 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); 1001 1002 /* enable interrupts */ 1003 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); 1004 1005 netif_wake_queue(ag->ndev); 1006 } 1007 1008 static void ag71xx_mac_config(struct phylink_config *config, unsigned int mode, 1009 const struct phylink_link_state *state) 1010 { 1011 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 1012 1013 if (phylink_autoneg_inband(mode)) 1014 return; 1015 1016 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130)) 1017 ag71xx_fast_reset(ag); 1018 1019 if (ag->tx_ring.desc_split) { 1020 ag->fifodata[2] &= 0xffff; 1021 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16; 1022 } 1023 1024 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]); 1025 } 1026 1027 static void ag71xx_mac_validate(struct phylink_config *config, 1028 unsigned long *supported, 1029 struct phylink_link_state *state) 1030 { 1031 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 1032 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1033 1034 switch (state->interface) { 1035 case PHY_INTERFACE_MODE_NA: 1036 break; 1037 case PHY_INTERFACE_MODE_MII: 1038 if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 0) || 1039 ag71xx_is(ag, AR9340) || 1040 ag71xx_is(ag, QCA9530) || 1041 (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1)) 1042 break; 1043 goto unsupported; 1044 case PHY_INTERFACE_MODE_GMII: 1045 if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 1) || 1046 (ag71xx_is(ag, AR9340) && ag->mac_idx == 1) || 1047 (ag71xx_is(ag, QCA9530) && ag->mac_idx == 1)) 1048 break; 1049 goto unsupported; 1050 case PHY_INTERFACE_MODE_SGMII: 1051 if (ag71xx_is(ag, QCA9550) && ag->mac_idx == 0) 1052 break; 1053 goto unsupported; 1054 case PHY_INTERFACE_MODE_RMII: 1055 if (ag71xx_is(ag, AR9340) && ag->mac_idx == 0) 1056 break; 1057 goto unsupported; 1058 case PHY_INTERFACE_MODE_RGMII: 1059 if ((ag71xx_is(ag, AR9340) && ag->mac_idx == 0) || 1060 (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1)) 1061 break; 1062 goto unsupported; 1063 default: 1064 goto unsupported; 1065 } 1066 1067 phylink_set(mask, MII); 1068 1069 phylink_set(mask, Pause); 1070 phylink_set(mask, Asym_Pause); 1071 phylink_set(mask, Autoneg); 1072 phylink_set(mask, 10baseT_Half); 1073 phylink_set(mask, 10baseT_Full); 1074 phylink_set(mask, 100baseT_Half); 1075 phylink_set(mask, 100baseT_Full); 1076 1077 if (state->interface == PHY_INTERFACE_MODE_NA || 1078 state->interface == PHY_INTERFACE_MODE_SGMII || 1079 state->interface == PHY_INTERFACE_MODE_RGMII || 1080 state->interface == PHY_INTERFACE_MODE_GMII) { 1081 phylink_set(mask, 1000baseT_Full); 1082 phylink_set(mask, 1000baseX_Full); 1083 } 1084 1085 bitmap_and(supported, supported, mask, 1086 __ETHTOOL_LINK_MODE_MASK_NBITS); 1087 bitmap_and(state->advertising, state->advertising, mask, 1088 __ETHTOOL_LINK_MODE_MASK_NBITS); 1089 1090 return; 1091 unsupported: 1092 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1093 } 1094 1095 static void ag71xx_mac_pcs_get_state(struct phylink_config *config, 1096 struct phylink_link_state *state) 1097 { 1098 state->link = 0; 1099 } 1100 1101 static void ag71xx_mac_an_restart(struct phylink_config *config) 1102 { 1103 /* Not Supported */ 1104 } 1105 1106 static void ag71xx_mac_link_down(struct phylink_config *config, 1107 unsigned int mode, phy_interface_t interface) 1108 { 1109 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 1110 1111 ag71xx_hw_stop(ag); 1112 } 1113 1114 static void ag71xx_mac_link_up(struct phylink_config *config, 1115 struct phy_device *phy, 1116 unsigned int mode, phy_interface_t interface, 1117 int speed, int duplex, 1118 bool tx_pause, bool rx_pause) 1119 { 1120 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 1121 u32 cfg1, cfg2; 1122 u32 ifctl; 1123 u32 fifo5; 1124 1125 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); 1126 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); 1127 cfg2 |= duplex ? MAC_CFG2_FDX : 0; 1128 1129 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); 1130 ifctl &= ~(MAC_IFCTL_SPEED); 1131 1132 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); 1133 fifo5 &= ~FIFO_CFG5_BM; 1134 1135 switch (speed) { 1136 case SPEED_1000: 1137 cfg2 |= MAC_CFG2_IF_1000; 1138 fifo5 |= FIFO_CFG5_BM; 1139 break; 1140 case SPEED_100: 1141 cfg2 |= MAC_CFG2_IF_10_100; 1142 ifctl |= MAC_IFCTL_SPEED; 1143 break; 1144 case SPEED_10: 1145 cfg2 |= MAC_CFG2_IF_10_100; 1146 break; 1147 default: 1148 return; 1149 } 1150 1151 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); 1152 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); 1153 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); 1154 1155 cfg1 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG1); 1156 cfg1 &= ~(MAC_CFG1_TFC | MAC_CFG1_RFC); 1157 if (tx_pause) 1158 cfg1 |= MAC_CFG1_TFC; 1159 1160 if (rx_pause) 1161 cfg1 |= MAC_CFG1_RFC; 1162 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, cfg1); 1163 1164 ag71xx_hw_start(ag); 1165 } 1166 1167 static const struct phylink_mac_ops ag71xx_phylink_mac_ops = { 1168 .validate = ag71xx_mac_validate, 1169 .mac_pcs_get_state = ag71xx_mac_pcs_get_state, 1170 .mac_an_restart = ag71xx_mac_an_restart, 1171 .mac_config = ag71xx_mac_config, 1172 .mac_link_down = ag71xx_mac_link_down, 1173 .mac_link_up = ag71xx_mac_link_up, 1174 }; 1175 1176 static int ag71xx_phylink_setup(struct ag71xx *ag) 1177 { 1178 struct phylink *phylink; 1179 1180 ag->phylink_config.dev = &ag->ndev->dev; 1181 ag->phylink_config.type = PHYLINK_NETDEV; 1182 1183 phylink = phylink_create(&ag->phylink_config, ag->pdev->dev.fwnode, 1184 ag->phy_if_mode, &ag71xx_phylink_mac_ops); 1185 if (IS_ERR(phylink)) 1186 return PTR_ERR(phylink); 1187 1188 ag->phylink = phylink; 1189 return 0; 1190 } 1191 1192 static void ag71xx_ring_tx_clean(struct ag71xx *ag) 1193 { 1194 struct ag71xx_ring *ring = &ag->tx_ring; 1195 int ring_mask = BIT(ring->order) - 1; 1196 u32 bytes_compl = 0, pkts_compl = 0; 1197 struct net_device *ndev = ag->ndev; 1198 1199 while (ring->curr != ring->dirty) { 1200 struct ag71xx_desc *desc; 1201 u32 i = ring->dirty & ring_mask; 1202 1203 desc = ag71xx_ring_desc(ring, i); 1204 if (!ag71xx_desc_empty(desc)) { 1205 desc->ctrl = 0; 1206 ndev->stats.tx_errors++; 1207 } 1208 1209 if (ring->buf[i].tx.skb) { 1210 bytes_compl += ring->buf[i].tx.len; 1211 pkts_compl++; 1212 dev_kfree_skb_any(ring->buf[i].tx.skb); 1213 } 1214 ring->buf[i].tx.skb = NULL; 1215 ring->dirty++; 1216 } 1217 1218 /* flush descriptors */ 1219 wmb(); 1220 1221 netdev_completed_queue(ndev, pkts_compl, bytes_compl); 1222 } 1223 1224 static void ag71xx_ring_tx_init(struct ag71xx *ag) 1225 { 1226 struct ag71xx_ring *ring = &ag->tx_ring; 1227 int ring_size = BIT(ring->order); 1228 int ring_mask = ring_size - 1; 1229 int i; 1230 1231 for (i = 0; i < ring_size; i++) { 1232 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1233 1234 desc->next = (u32)(ring->descs_dma + 1235 AG71XX_DESC_SIZE * ((i + 1) & ring_mask)); 1236 1237 desc->ctrl = DESC_EMPTY; 1238 ring->buf[i].tx.skb = NULL; 1239 } 1240 1241 /* flush descriptors */ 1242 wmb(); 1243 1244 ring->curr = 0; 1245 ring->dirty = 0; 1246 netdev_reset_queue(ag->ndev); 1247 } 1248 1249 static void ag71xx_ring_rx_clean(struct ag71xx *ag) 1250 { 1251 struct ag71xx_ring *ring = &ag->rx_ring; 1252 int ring_size = BIT(ring->order); 1253 int i; 1254 1255 if (!ring->buf) 1256 return; 1257 1258 for (i = 0; i < ring_size; i++) 1259 if (ring->buf[i].rx.rx_buf) { 1260 dma_unmap_single(&ag->pdev->dev, 1261 ring->buf[i].rx.dma_addr, 1262 ag->rx_buf_size, DMA_FROM_DEVICE); 1263 skb_free_frag(ring->buf[i].rx.rx_buf); 1264 } 1265 } 1266 1267 static int ag71xx_buffer_size(struct ag71xx *ag) 1268 { 1269 return ag->rx_buf_size + 1270 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1271 } 1272 1273 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf, 1274 int offset, 1275 void *(*alloc)(unsigned int size)) 1276 { 1277 struct ag71xx_ring *ring = &ag->rx_ring; 1278 struct ag71xx_desc *desc; 1279 void *data; 1280 1281 desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]); 1282 1283 data = alloc(ag71xx_buffer_size(ag)); 1284 if (!data) 1285 return false; 1286 1287 buf->rx.rx_buf = data; 1288 buf->rx.dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size, 1289 DMA_FROM_DEVICE); 1290 desc->data = (u32)buf->rx.dma_addr + offset; 1291 return true; 1292 } 1293 1294 static int ag71xx_ring_rx_init(struct ag71xx *ag) 1295 { 1296 struct ag71xx_ring *ring = &ag->rx_ring; 1297 struct net_device *ndev = ag->ndev; 1298 int ring_mask = BIT(ring->order) - 1; 1299 int ring_size = BIT(ring->order); 1300 unsigned int i; 1301 int ret; 1302 1303 ret = 0; 1304 for (i = 0; i < ring_size; i++) { 1305 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1306 1307 desc->next = (u32)(ring->descs_dma + 1308 AG71XX_DESC_SIZE * ((i + 1) & ring_mask)); 1309 1310 netif_dbg(ag, rx_status, ndev, "RX desc at %p, next is %08x\n", 1311 desc, desc->next); 1312 } 1313 1314 for (i = 0; i < ring_size; i++) { 1315 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1316 1317 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset, 1318 netdev_alloc_frag)) { 1319 ret = -ENOMEM; 1320 break; 1321 } 1322 1323 desc->ctrl = DESC_EMPTY; 1324 } 1325 1326 /* flush descriptors */ 1327 wmb(); 1328 1329 ring->curr = 0; 1330 ring->dirty = 0; 1331 1332 return ret; 1333 } 1334 1335 static int ag71xx_ring_rx_refill(struct ag71xx *ag) 1336 { 1337 struct ag71xx_ring *ring = &ag->rx_ring; 1338 int ring_mask = BIT(ring->order) - 1; 1339 int offset = ag->rx_buf_offset; 1340 unsigned int count; 1341 1342 count = 0; 1343 for (; ring->curr - ring->dirty > 0; ring->dirty++) { 1344 struct ag71xx_desc *desc; 1345 unsigned int i; 1346 1347 i = ring->dirty & ring_mask; 1348 desc = ag71xx_ring_desc(ring, i); 1349 1350 if (!ring->buf[i].rx.rx_buf && 1351 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset, 1352 napi_alloc_frag)) 1353 break; 1354 1355 desc->ctrl = DESC_EMPTY; 1356 count++; 1357 } 1358 1359 /* flush descriptors */ 1360 wmb(); 1361 1362 netif_dbg(ag, rx_status, ag->ndev, "%u rx descriptors refilled\n", 1363 count); 1364 1365 return count; 1366 } 1367 1368 static int ag71xx_rings_init(struct ag71xx *ag) 1369 { 1370 struct ag71xx_ring *tx = &ag->tx_ring; 1371 struct ag71xx_ring *rx = &ag->rx_ring; 1372 int ring_size, tx_size; 1373 1374 ring_size = BIT(tx->order) + BIT(rx->order); 1375 tx_size = BIT(tx->order); 1376 1377 tx->buf = kcalloc(ring_size, sizeof(*tx->buf), GFP_KERNEL); 1378 if (!tx->buf) 1379 return -ENOMEM; 1380 1381 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, 1382 ring_size * AG71XX_DESC_SIZE, 1383 &tx->descs_dma, GFP_KERNEL); 1384 if (!tx->descs_cpu) { 1385 kfree(tx->buf); 1386 tx->buf = NULL; 1387 return -ENOMEM; 1388 } 1389 1390 rx->buf = &tx->buf[tx_size]; 1391 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE; 1392 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE; 1393 1394 ag71xx_ring_tx_init(ag); 1395 return ag71xx_ring_rx_init(ag); 1396 } 1397 1398 static void ag71xx_rings_free(struct ag71xx *ag) 1399 { 1400 struct ag71xx_ring *tx = &ag->tx_ring; 1401 struct ag71xx_ring *rx = &ag->rx_ring; 1402 int ring_size; 1403 1404 ring_size = BIT(tx->order) + BIT(rx->order); 1405 1406 if (tx->descs_cpu) 1407 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE, 1408 tx->descs_cpu, tx->descs_dma); 1409 1410 kfree(tx->buf); 1411 1412 tx->descs_cpu = NULL; 1413 rx->descs_cpu = NULL; 1414 tx->buf = NULL; 1415 rx->buf = NULL; 1416 } 1417 1418 static void ag71xx_rings_cleanup(struct ag71xx *ag) 1419 { 1420 ag71xx_ring_rx_clean(ag); 1421 ag71xx_ring_tx_clean(ag); 1422 ag71xx_rings_free(ag); 1423 1424 netdev_reset_queue(ag->ndev); 1425 } 1426 1427 static void ag71xx_hw_init(struct ag71xx *ag) 1428 { 1429 ag71xx_hw_stop(ag); 1430 1431 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); 1432 usleep_range(20, 30); 1433 1434 reset_control_assert(ag->mac_reset); 1435 msleep(100); 1436 reset_control_deassert(ag->mac_reset); 1437 msleep(200); 1438 1439 ag71xx_hw_setup(ag); 1440 1441 ag71xx_dma_reset(ag); 1442 } 1443 1444 static int ag71xx_hw_enable(struct ag71xx *ag) 1445 { 1446 int ret; 1447 1448 ret = ag71xx_rings_init(ag); 1449 if (ret) 1450 return ret; 1451 1452 napi_enable(&ag->napi); 1453 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); 1454 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); 1455 netif_start_queue(ag->ndev); 1456 1457 return 0; 1458 } 1459 1460 static void ag71xx_hw_disable(struct ag71xx *ag) 1461 { 1462 netif_stop_queue(ag->ndev); 1463 1464 ag71xx_hw_stop(ag); 1465 ag71xx_dma_reset(ag); 1466 1467 napi_disable(&ag->napi); 1468 del_timer_sync(&ag->oom_timer); 1469 1470 ag71xx_rings_cleanup(ag); 1471 } 1472 1473 static int ag71xx_open(struct net_device *ndev) 1474 { 1475 struct ag71xx *ag = netdev_priv(ndev); 1476 unsigned int max_frame_len; 1477 int ret; 1478 1479 ret = phylink_of_phy_connect(ag->phylink, ag->pdev->dev.of_node, 0); 1480 if (ret) { 1481 netif_err(ag, link, ndev, "phylink_of_phy_connect filed with err: %i\n", 1482 ret); 1483 goto err; 1484 } 1485 1486 max_frame_len = ag71xx_max_frame_len(ndev->mtu); 1487 ag->rx_buf_size = 1488 SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN); 1489 1490 /* setup max frame length */ 1491 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len); 1492 ag71xx_hw_set_macaddr(ag, ndev->dev_addr); 1493 1494 ret = ag71xx_hw_enable(ag); 1495 if (ret) 1496 goto err; 1497 1498 phylink_start(ag->phylink); 1499 1500 return 0; 1501 1502 err: 1503 ag71xx_rings_cleanup(ag); 1504 return ret; 1505 } 1506 1507 static int ag71xx_stop(struct net_device *ndev) 1508 { 1509 struct ag71xx *ag = netdev_priv(ndev); 1510 1511 phylink_stop(ag->phylink); 1512 phylink_disconnect_phy(ag->phylink); 1513 ag71xx_hw_disable(ag); 1514 1515 return 0; 1516 } 1517 1518 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len) 1519 { 1520 int i, ring_mask, ndesc, split; 1521 struct ag71xx_desc *desc; 1522 1523 ring_mask = BIT(ring->order) - 1; 1524 ndesc = 0; 1525 split = ring->desc_split; 1526 1527 if (!split) 1528 split = len; 1529 1530 while (len > 0) { 1531 unsigned int cur_len = len; 1532 1533 i = (ring->curr + ndesc) & ring_mask; 1534 desc = ag71xx_ring_desc(ring, i); 1535 1536 if (!ag71xx_desc_empty(desc)) 1537 return -1; 1538 1539 if (cur_len > split) { 1540 cur_len = split; 1541 1542 /* TX will hang if DMA transfers <= 4 bytes, 1543 * make sure next segment is more than 4 bytes long. 1544 */ 1545 if (len <= split + 4) 1546 cur_len -= 4; 1547 } 1548 1549 desc->data = addr; 1550 addr += cur_len; 1551 len -= cur_len; 1552 1553 if (len > 0) 1554 cur_len |= DESC_MORE; 1555 1556 /* prevent early tx attempt of this descriptor */ 1557 if (!ndesc) 1558 cur_len |= DESC_EMPTY; 1559 1560 desc->ctrl = cur_len; 1561 ndesc++; 1562 } 1563 1564 return ndesc; 1565 } 1566 1567 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, 1568 struct net_device *ndev) 1569 { 1570 int i, n, ring_min, ring_mask, ring_size; 1571 struct ag71xx *ag = netdev_priv(ndev); 1572 struct ag71xx_ring *ring; 1573 struct ag71xx_desc *desc; 1574 dma_addr_t dma_addr; 1575 1576 ring = &ag->tx_ring; 1577 ring_mask = BIT(ring->order) - 1; 1578 ring_size = BIT(ring->order); 1579 1580 if (skb->len <= 4) { 1581 netif_dbg(ag, tx_err, ndev, "packet len is too small\n"); 1582 goto err_drop; 1583 } 1584 1585 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len, 1586 DMA_TO_DEVICE); 1587 1588 i = ring->curr & ring_mask; 1589 desc = ag71xx_ring_desc(ring, i); 1590 1591 /* setup descriptor fields */ 1592 n = ag71xx_fill_dma_desc(ring, (u32)dma_addr, 1593 skb->len & ag->dcfg->desc_pktlen_mask); 1594 if (n < 0) 1595 goto err_drop_unmap; 1596 1597 i = (ring->curr + n - 1) & ring_mask; 1598 ring->buf[i].tx.len = skb->len; 1599 ring->buf[i].tx.skb = skb; 1600 1601 netdev_sent_queue(ndev, skb->len); 1602 1603 skb_tx_timestamp(skb); 1604 1605 desc->ctrl &= ~DESC_EMPTY; 1606 ring->curr += n; 1607 1608 /* flush descriptor */ 1609 wmb(); 1610 1611 ring_min = 2; 1612 if (ring->desc_split) 1613 ring_min *= AG71XX_TX_RING_DS_PER_PKT; 1614 1615 if (ring->curr - ring->dirty >= ring_size - ring_min) { 1616 netif_dbg(ag, tx_err, ndev, "tx queue full\n"); 1617 netif_stop_queue(ndev); 1618 } 1619 1620 netif_dbg(ag, tx_queued, ndev, "packet injected into TX queue\n"); 1621 1622 /* enable TX engine */ 1623 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); 1624 1625 return NETDEV_TX_OK; 1626 1627 err_drop_unmap: 1628 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE); 1629 1630 err_drop: 1631 ndev->stats.tx_dropped++; 1632 1633 dev_kfree_skb(skb); 1634 return NETDEV_TX_OK; 1635 } 1636 1637 static void ag71xx_oom_timer_handler(struct timer_list *t) 1638 { 1639 struct ag71xx *ag = from_timer(ag, t, oom_timer); 1640 1641 napi_schedule(&ag->napi); 1642 } 1643 1644 static void ag71xx_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1645 { 1646 struct ag71xx *ag = netdev_priv(ndev); 1647 1648 netif_err(ag, tx_err, ndev, "tx timeout\n"); 1649 1650 schedule_delayed_work(&ag->restart_work, 1); 1651 } 1652 1653 static void ag71xx_restart_work_func(struct work_struct *work) 1654 { 1655 struct ag71xx *ag = container_of(work, struct ag71xx, 1656 restart_work.work); 1657 1658 rtnl_lock(); 1659 ag71xx_hw_disable(ag); 1660 ag71xx_hw_enable(ag); 1661 1662 phylink_stop(ag->phylink); 1663 phylink_start(ag->phylink); 1664 1665 rtnl_unlock(); 1666 } 1667 1668 static int ag71xx_rx_packets(struct ag71xx *ag, int limit) 1669 { 1670 struct net_device *ndev = ag->ndev; 1671 int ring_mask, ring_size, done = 0; 1672 unsigned int pktlen_mask, offset; 1673 struct ag71xx_ring *ring; 1674 struct list_head rx_list; 1675 struct sk_buff *skb; 1676 1677 ring = &ag->rx_ring; 1678 pktlen_mask = ag->dcfg->desc_pktlen_mask; 1679 offset = ag->rx_buf_offset; 1680 ring_mask = BIT(ring->order) - 1; 1681 ring_size = BIT(ring->order); 1682 1683 netif_dbg(ag, rx_status, ndev, "rx packets, limit=%d, curr=%u, dirty=%u\n", 1684 limit, ring->curr, ring->dirty); 1685 1686 INIT_LIST_HEAD(&rx_list); 1687 1688 while (done < limit) { 1689 unsigned int i = ring->curr & ring_mask; 1690 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1691 int pktlen; 1692 int err = 0; 1693 1694 if (ag71xx_desc_empty(desc)) 1695 break; 1696 1697 if ((ring->dirty + ring_size) == ring->curr) { 1698 WARN_ONCE(1, "RX out of ring"); 1699 break; 1700 } 1701 1702 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); 1703 1704 pktlen = desc->ctrl & pktlen_mask; 1705 pktlen -= ETH_FCS_LEN; 1706 1707 dma_unmap_single(&ag->pdev->dev, ring->buf[i].rx.dma_addr, 1708 ag->rx_buf_size, DMA_FROM_DEVICE); 1709 1710 ndev->stats.rx_packets++; 1711 ndev->stats.rx_bytes += pktlen; 1712 1713 skb = build_skb(ring->buf[i].rx.rx_buf, ag71xx_buffer_size(ag)); 1714 if (!skb) { 1715 skb_free_frag(ring->buf[i].rx.rx_buf); 1716 goto next; 1717 } 1718 1719 skb_reserve(skb, offset); 1720 skb_put(skb, pktlen); 1721 1722 if (err) { 1723 ndev->stats.rx_dropped++; 1724 kfree_skb(skb); 1725 } else { 1726 skb->dev = ndev; 1727 skb->ip_summed = CHECKSUM_NONE; 1728 list_add_tail(&skb->list, &rx_list); 1729 } 1730 1731 next: 1732 ring->buf[i].rx.rx_buf = NULL; 1733 done++; 1734 1735 ring->curr++; 1736 } 1737 1738 ag71xx_ring_rx_refill(ag); 1739 1740 list_for_each_entry(skb, &rx_list, list) 1741 skb->protocol = eth_type_trans(skb, ndev); 1742 netif_receive_skb_list(&rx_list); 1743 1744 netif_dbg(ag, rx_status, ndev, "rx finish, curr=%u, dirty=%u, done=%d\n", 1745 ring->curr, ring->dirty, done); 1746 1747 return done; 1748 } 1749 1750 static int ag71xx_poll(struct napi_struct *napi, int limit) 1751 { 1752 struct ag71xx *ag = container_of(napi, struct ag71xx, napi); 1753 struct ag71xx_ring *rx_ring = &ag->rx_ring; 1754 int rx_ring_size = BIT(rx_ring->order); 1755 struct net_device *ndev = ag->ndev; 1756 int tx_done, rx_done; 1757 u32 status; 1758 1759 tx_done = ag71xx_tx_packets(ag, false); 1760 1761 netif_dbg(ag, rx_status, ndev, "processing RX ring\n"); 1762 rx_done = ag71xx_rx_packets(ag, limit); 1763 1764 if (!rx_ring->buf[rx_ring->dirty % rx_ring_size].rx.rx_buf) 1765 goto oom; 1766 1767 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); 1768 if (unlikely(status & RX_STATUS_OF)) { 1769 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); 1770 ndev->stats.rx_fifo_errors++; 1771 1772 /* restart RX */ 1773 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); 1774 } 1775 1776 if (rx_done < limit) { 1777 if (status & RX_STATUS_PR) 1778 goto more; 1779 1780 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); 1781 if (status & TX_STATUS_PS) 1782 goto more; 1783 1784 netif_dbg(ag, rx_status, ndev, "disable polling mode, rx=%d, tx=%d,limit=%d\n", 1785 rx_done, tx_done, limit); 1786 1787 napi_complete(napi); 1788 1789 /* enable interrupts */ 1790 ag71xx_int_enable(ag, AG71XX_INT_POLL); 1791 return rx_done; 1792 } 1793 1794 more: 1795 netif_dbg(ag, rx_status, ndev, "stay in polling mode, rx=%d, tx=%d, limit=%d\n", 1796 rx_done, tx_done, limit); 1797 return limit; 1798 1799 oom: 1800 netif_err(ag, rx_err, ndev, "out of memory\n"); 1801 1802 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); 1803 napi_complete(napi); 1804 return 0; 1805 } 1806 1807 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) 1808 { 1809 struct net_device *ndev = dev_id; 1810 struct ag71xx *ag; 1811 u32 status; 1812 1813 ag = netdev_priv(ndev); 1814 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); 1815 1816 if (unlikely(!status)) 1817 return IRQ_NONE; 1818 1819 if (unlikely(status & AG71XX_INT_ERR)) { 1820 if (status & AG71XX_INT_TX_BE) { 1821 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); 1822 netif_err(ag, intr, ndev, "TX BUS error\n"); 1823 } 1824 if (status & AG71XX_INT_RX_BE) { 1825 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); 1826 netif_err(ag, intr, ndev, "RX BUS error\n"); 1827 } 1828 } 1829 1830 if (likely(status & AG71XX_INT_POLL)) { 1831 ag71xx_int_disable(ag, AG71XX_INT_POLL); 1832 netif_dbg(ag, intr, ndev, "enable polling mode\n"); 1833 napi_schedule(&ag->napi); 1834 } 1835 1836 return IRQ_HANDLED; 1837 } 1838 1839 static int ag71xx_change_mtu(struct net_device *ndev, int new_mtu) 1840 { 1841 struct ag71xx *ag = netdev_priv(ndev); 1842 1843 ndev->mtu = new_mtu; 1844 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 1845 ag71xx_max_frame_len(ndev->mtu)); 1846 1847 return 0; 1848 } 1849 1850 static const struct net_device_ops ag71xx_netdev_ops = { 1851 .ndo_open = ag71xx_open, 1852 .ndo_stop = ag71xx_stop, 1853 .ndo_start_xmit = ag71xx_hard_start_xmit, 1854 .ndo_do_ioctl = phy_do_ioctl, 1855 .ndo_tx_timeout = ag71xx_tx_timeout, 1856 .ndo_change_mtu = ag71xx_change_mtu, 1857 .ndo_set_mac_address = eth_mac_addr, 1858 .ndo_validate_addr = eth_validate_addr, 1859 }; 1860 1861 static const u32 ar71xx_addr_ar7100[] = { 1862 0x19000000, 0x1a000000, 1863 }; 1864 1865 static int ag71xx_probe(struct platform_device *pdev) 1866 { 1867 struct device_node *np = pdev->dev.of_node; 1868 const struct ag71xx_dcfg *dcfg; 1869 struct net_device *ndev; 1870 struct resource *res; 1871 int tx_size, err, i; 1872 struct ag71xx *ag; 1873 1874 if (!np) 1875 return -ENODEV; 1876 1877 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag)); 1878 if (!ndev) 1879 return -ENOMEM; 1880 1881 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1882 if (!res) 1883 return -EINVAL; 1884 1885 dcfg = of_device_get_match_data(&pdev->dev); 1886 if (!dcfg) 1887 return -EINVAL; 1888 1889 ag = netdev_priv(ndev); 1890 ag->mac_idx = -1; 1891 for (i = 0; i < ARRAY_SIZE(ar71xx_addr_ar7100); i++) { 1892 if (ar71xx_addr_ar7100[i] == res->start) 1893 ag->mac_idx = i; 1894 } 1895 1896 if (ag->mac_idx < 0) { 1897 netif_err(ag, probe, ndev, "unknown mac idx\n"); 1898 return -EINVAL; 1899 } 1900 1901 ag->clk_eth = devm_clk_get(&pdev->dev, "eth"); 1902 if (IS_ERR(ag->clk_eth)) { 1903 netif_err(ag, probe, ndev, "Failed to get eth clk.\n"); 1904 return PTR_ERR(ag->clk_eth); 1905 } 1906 1907 SET_NETDEV_DEV(ndev, &pdev->dev); 1908 1909 ag->pdev = pdev; 1910 ag->ndev = ndev; 1911 ag->dcfg = dcfg; 1912 ag->msg_enable = netif_msg_init(-1, AG71XX_DEFAULT_MSG_ENABLE); 1913 memcpy(ag->fifodata, dcfg->fifodata, sizeof(ag->fifodata)); 1914 1915 ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac"); 1916 if (IS_ERR(ag->mac_reset)) { 1917 netif_err(ag, probe, ndev, "missing mac reset\n"); 1918 err = PTR_ERR(ag->mac_reset); 1919 goto err_free; 1920 } 1921 1922 ag->mac_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1923 if (!ag->mac_base) { 1924 err = -ENOMEM; 1925 goto err_free; 1926 } 1927 1928 ndev->irq = platform_get_irq(pdev, 0); 1929 err = devm_request_irq(&pdev->dev, ndev->irq, ag71xx_interrupt, 1930 0x0, dev_name(&pdev->dev), ndev); 1931 if (err) { 1932 netif_err(ag, probe, ndev, "unable to request IRQ %d\n", 1933 ndev->irq); 1934 goto err_free; 1935 } 1936 1937 ndev->netdev_ops = &ag71xx_netdev_ops; 1938 ndev->ethtool_ops = &ag71xx_ethtool_ops; 1939 1940 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func); 1941 timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0); 1942 1943 tx_size = AG71XX_TX_RING_SIZE_DEFAULT; 1944 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT); 1945 1946 ndev->min_mtu = 68; 1947 ndev->max_mtu = dcfg->max_frame_len - ag71xx_max_frame_len(0); 1948 1949 ag->rx_buf_offset = NET_SKB_PAD; 1950 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130)) 1951 ag->rx_buf_offset += NET_IP_ALIGN; 1952 1953 if (ag71xx_is(ag, AR7100)) { 1954 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT; 1955 tx_size *= AG71XX_TX_RING_DS_PER_PKT; 1956 } 1957 ag->tx_ring.order = ag71xx_ring_size_order(tx_size); 1958 1959 ag->stop_desc = dmam_alloc_coherent(&pdev->dev, 1960 sizeof(struct ag71xx_desc), 1961 &ag->stop_desc_dma, GFP_KERNEL); 1962 if (!ag->stop_desc) { 1963 err = -ENOMEM; 1964 goto err_free; 1965 } 1966 1967 ag->stop_desc->data = 0; 1968 ag->stop_desc->ctrl = 0; 1969 ag->stop_desc->next = (u32)ag->stop_desc_dma; 1970 1971 err = of_get_mac_address(np, ndev->dev_addr); 1972 if (err) { 1973 netif_err(ag, probe, ndev, "invalid MAC address, using random address\n"); 1974 eth_random_addr(ndev->dev_addr); 1975 } 1976 1977 err = of_get_phy_mode(np, &ag->phy_if_mode); 1978 if (err) { 1979 netif_err(ag, probe, ndev, "missing phy-mode property in DT\n"); 1980 goto err_free; 1981 } 1982 1983 netif_napi_add(ndev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); 1984 1985 err = clk_prepare_enable(ag->clk_eth); 1986 if (err) { 1987 netif_err(ag, probe, ndev, "Failed to enable eth clk.\n"); 1988 goto err_free; 1989 } 1990 1991 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0); 1992 1993 ag71xx_hw_init(ag); 1994 1995 err = ag71xx_mdio_probe(ag); 1996 if (err) 1997 goto err_put_clk; 1998 1999 platform_set_drvdata(pdev, ndev); 2000 2001 err = ag71xx_phylink_setup(ag); 2002 if (err) { 2003 netif_err(ag, probe, ndev, "failed to setup phylink (%d)\n", err); 2004 goto err_mdio_remove; 2005 } 2006 2007 err = register_netdev(ndev); 2008 if (err) { 2009 netif_err(ag, probe, ndev, "unable to register net device\n"); 2010 platform_set_drvdata(pdev, NULL); 2011 goto err_mdio_remove; 2012 } 2013 2014 netif_info(ag, probe, ndev, "Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n", 2015 (unsigned long)ag->mac_base, ndev->irq, 2016 phy_modes(ag->phy_if_mode)); 2017 2018 return 0; 2019 2020 err_mdio_remove: 2021 ag71xx_mdio_remove(ag); 2022 err_put_clk: 2023 clk_disable_unprepare(ag->clk_eth); 2024 err_free: 2025 free_netdev(ndev); 2026 return err; 2027 } 2028 2029 static int ag71xx_remove(struct platform_device *pdev) 2030 { 2031 struct net_device *ndev = platform_get_drvdata(pdev); 2032 struct ag71xx *ag; 2033 2034 if (!ndev) 2035 return 0; 2036 2037 ag = netdev_priv(ndev); 2038 unregister_netdev(ndev); 2039 ag71xx_mdio_remove(ag); 2040 clk_disable_unprepare(ag->clk_eth); 2041 platform_set_drvdata(pdev, NULL); 2042 2043 return 0; 2044 } 2045 2046 static const u32 ar71xx_fifo_ar7100[] = { 2047 0x0fff0000, 0x00001fff, 0x00780fff, 2048 }; 2049 2050 static const u32 ar71xx_fifo_ar9130[] = { 2051 0x0fff0000, 0x00001fff, 0x008001ff, 2052 }; 2053 2054 static const u32 ar71xx_fifo_ar9330[] = { 2055 0x0010ffff, 0x015500aa, 0x01f00140, 2056 }; 2057 2058 static const struct ag71xx_dcfg ag71xx_dcfg_ar7100 = { 2059 .type = AR7100, 2060 .fifodata = ar71xx_fifo_ar7100, 2061 .max_frame_len = 1540, 2062 .desc_pktlen_mask = SZ_4K - 1, 2063 .tx_hang_workaround = false, 2064 }; 2065 2066 static const struct ag71xx_dcfg ag71xx_dcfg_ar7240 = { 2067 .type = AR7240, 2068 .fifodata = ar71xx_fifo_ar7100, 2069 .max_frame_len = 1540, 2070 .desc_pktlen_mask = SZ_4K - 1, 2071 .tx_hang_workaround = true, 2072 }; 2073 2074 static const struct ag71xx_dcfg ag71xx_dcfg_ar9130 = { 2075 .type = AR9130, 2076 .fifodata = ar71xx_fifo_ar9130, 2077 .max_frame_len = 1540, 2078 .desc_pktlen_mask = SZ_4K - 1, 2079 .tx_hang_workaround = false, 2080 }; 2081 2082 static const struct ag71xx_dcfg ag71xx_dcfg_ar9330 = { 2083 .type = AR9330, 2084 .fifodata = ar71xx_fifo_ar9330, 2085 .max_frame_len = 1540, 2086 .desc_pktlen_mask = SZ_4K - 1, 2087 .tx_hang_workaround = true, 2088 }; 2089 2090 static const struct ag71xx_dcfg ag71xx_dcfg_ar9340 = { 2091 .type = AR9340, 2092 .fifodata = ar71xx_fifo_ar9330, 2093 .max_frame_len = SZ_16K - 1, 2094 .desc_pktlen_mask = SZ_16K - 1, 2095 .tx_hang_workaround = true, 2096 }; 2097 2098 static const struct ag71xx_dcfg ag71xx_dcfg_qca9530 = { 2099 .type = QCA9530, 2100 .fifodata = ar71xx_fifo_ar9330, 2101 .max_frame_len = SZ_16K - 1, 2102 .desc_pktlen_mask = SZ_16K - 1, 2103 .tx_hang_workaround = true, 2104 }; 2105 2106 static const struct ag71xx_dcfg ag71xx_dcfg_qca9550 = { 2107 .type = QCA9550, 2108 .fifodata = ar71xx_fifo_ar9330, 2109 .max_frame_len = 1540, 2110 .desc_pktlen_mask = SZ_16K - 1, 2111 .tx_hang_workaround = true, 2112 }; 2113 2114 static const struct of_device_id ag71xx_match[] = { 2115 { .compatible = "qca,ar7100-eth", .data = &ag71xx_dcfg_ar7100 }, 2116 { .compatible = "qca,ar7240-eth", .data = &ag71xx_dcfg_ar7240 }, 2117 { .compatible = "qca,ar7241-eth", .data = &ag71xx_dcfg_ar7240 }, 2118 { .compatible = "qca,ar7242-eth", .data = &ag71xx_dcfg_ar7240 }, 2119 { .compatible = "qca,ar9130-eth", .data = &ag71xx_dcfg_ar9130 }, 2120 { .compatible = "qca,ar9330-eth", .data = &ag71xx_dcfg_ar9330 }, 2121 { .compatible = "qca,ar9340-eth", .data = &ag71xx_dcfg_ar9340 }, 2122 { .compatible = "qca,qca9530-eth", .data = &ag71xx_dcfg_qca9530 }, 2123 { .compatible = "qca,qca9550-eth", .data = &ag71xx_dcfg_qca9550 }, 2124 { .compatible = "qca,qca9560-eth", .data = &ag71xx_dcfg_qca9550 }, 2125 {} 2126 }; 2127 2128 static struct platform_driver ag71xx_driver = { 2129 .probe = ag71xx_probe, 2130 .remove = ag71xx_remove, 2131 .driver = { 2132 .name = "ag71xx", 2133 .of_match_table = ag71xx_match, 2134 } 2135 }; 2136 2137 module_platform_driver(ag71xx_driver); 2138 MODULE_LICENSE("GPL v2"); 2139