1 // SPDX-License-Identifier: GPL-2.0 2 /* Atheros AR71xx built-in ethernet mac driver 3 * 4 * Copyright (C) 2019 Oleksij Rempel <o.rempel@pengutronix.de> 5 * 6 * List of authors contributed to this driver before mainlining: 7 * Alexander Couzens <lynxis@fe80.eu> 8 * Christian Lamparter <chunkeey@gmail.com> 9 * Chuanhong Guo <gch981213@gmail.com> 10 * Daniel F. Dickinson <cshored@thecshore.com> 11 * David Bauer <mail@david-bauer.net> 12 * Felix Fietkau <nbd@nbd.name> 13 * Gabor Juhos <juhosg@freemail.hu> 14 * Hauke Mehrtens <hauke@hauke-m.de> 15 * Johann Neuhauser <johann@it-neuhauser.de> 16 * John Crispin <john@phrozen.org> 17 * Jo-Philipp Wich <jo@mein.io> 18 * Koen Vandeputte <koen.vandeputte@ncentric.com> 19 * Lucian Cristian <lucian.cristian@gmail.com> 20 * Matt Merhar <mattmerhar@protonmail.com> 21 * Milan Krstic <milan.krstic@gmail.com> 22 * Petr Štetiar <ynezz@true.cz> 23 * Rosen Penev <rosenp@gmail.com> 24 * Stephen Walker <stephendwalker+github@gmail.com> 25 * Vittorio Gambaletta <openwrt@vittgam.net> 26 * Weijie Gao <hackpascal@gmail.com> 27 * Imre Kaloz <kaloz@openwrt.org> 28 */ 29 30 #include <linux/if_vlan.h> 31 #include <linux/mfd/syscon.h> 32 #include <linux/of_mdio.h> 33 #include <linux/of_net.h> 34 #include <linux/of_platform.h> 35 #include <linux/regmap.h> 36 #include <linux/reset.h> 37 #include <linux/clk.h> 38 39 /* For our NAPI weight bigger does *NOT* mean better - it means more 40 * D-cache misses and lots more wasted cycles than we'll ever 41 * possibly gain from saving instructions. 42 */ 43 #define AG71XX_NAPI_WEIGHT 32 44 #define AG71XX_OOM_REFILL (1 + HZ / 10) 45 46 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) 47 #define AG71XX_INT_TX (AG71XX_INT_TX_PS) 48 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) 49 50 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) 51 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) 52 53 #define AG71XX_TX_MTU_LEN 1540 54 55 #define AG71XX_TX_RING_SPLIT 512 56 #define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \ 57 AG71XX_TX_RING_SPLIT) 58 #define AG71XX_TX_RING_SIZE_DEFAULT 128 59 #define AG71XX_RX_RING_SIZE_DEFAULT 256 60 61 #define AG71XX_MDIO_RETRY 1000 62 #define AG71XX_MDIO_DELAY 5 63 #define AG71XX_MDIO_MAX_CLK 5000000 64 65 /* Register offsets */ 66 #define AG71XX_REG_MAC_CFG1 0x0000 67 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */ 68 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ 69 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */ 70 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ 71 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ 72 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ 73 #define MAC_CFG1_SR BIT(31) /* Soft Reset */ 74 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ 75 MAC_CFG1_SRX | MAC_CFG1_STX) 76 77 #define AG71XX_REG_MAC_CFG2 0x0004 78 #define MAC_CFG2_FDX BIT(0) 79 #define MAC_CFG2_PAD_CRC_EN BIT(2) 80 #define MAC_CFG2_LEN_CHECK BIT(4) 81 #define MAC_CFG2_IF_1000 BIT(9) 82 #define MAC_CFG2_IF_10_100 BIT(8) 83 84 #define AG71XX_REG_MAC_MFL 0x0010 85 86 #define AG71XX_REG_MII_CFG 0x0020 87 #define MII_CFG_CLK_DIV_4 0 88 #define MII_CFG_CLK_DIV_6 2 89 #define MII_CFG_CLK_DIV_8 3 90 #define MII_CFG_CLK_DIV_10 4 91 #define MII_CFG_CLK_DIV_14 5 92 #define MII_CFG_CLK_DIV_20 6 93 #define MII_CFG_CLK_DIV_28 7 94 #define MII_CFG_CLK_DIV_34 8 95 #define MII_CFG_CLK_DIV_42 9 96 #define MII_CFG_CLK_DIV_50 10 97 #define MII_CFG_CLK_DIV_58 11 98 #define MII_CFG_CLK_DIV_66 12 99 #define MII_CFG_CLK_DIV_74 13 100 #define MII_CFG_CLK_DIV_82 14 101 #define MII_CFG_CLK_DIV_98 15 102 #define MII_CFG_RESET BIT(31) 103 104 #define AG71XX_REG_MII_CMD 0x0024 105 #define MII_CMD_READ BIT(0) 106 107 #define AG71XX_REG_MII_ADDR 0x0028 108 #define MII_ADDR_SHIFT 8 109 110 #define AG71XX_REG_MII_CTRL 0x002c 111 #define AG71XX_REG_MII_STATUS 0x0030 112 #define AG71XX_REG_MII_IND 0x0034 113 #define MII_IND_BUSY BIT(0) 114 #define MII_IND_INVALID BIT(2) 115 116 #define AG71XX_REG_MAC_IFCTL 0x0038 117 #define MAC_IFCTL_SPEED BIT(16) 118 119 #define AG71XX_REG_MAC_ADDR1 0x0040 120 #define AG71XX_REG_MAC_ADDR2 0x0044 121 #define AG71XX_REG_FIFO_CFG0 0x0048 122 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ 123 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ 124 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ 125 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ 126 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ 127 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ 128 | FIFO_CFG0_TXS | FIFO_CFG0_TXF) 129 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) 130 131 #define FIFO_CFG0_ENABLE_SHIFT 8 132 133 #define AG71XX_REG_FIFO_CFG1 0x004c 134 #define AG71XX_REG_FIFO_CFG2 0x0050 135 #define AG71XX_REG_FIFO_CFG3 0x0054 136 #define AG71XX_REG_FIFO_CFG4 0x0058 137 #define FIFO_CFG4_DE BIT(0) /* Drop Event */ 138 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ 139 #define FIFO_CFG4_FC BIT(2) /* False Carrier */ 140 #define FIFO_CFG4_CE BIT(3) /* Code Error */ 141 #define FIFO_CFG4_CR BIT(4) /* CRC error */ 142 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ 143 #define FIFO_CFG4_LO BIT(6) /* Length out of range */ 144 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */ 145 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ 146 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ 147 #define FIFO_CFG4_DR BIT(10) /* Dribble */ 148 #define FIFO_CFG4_LE BIT(11) /* Long Event */ 149 #define FIFO_CFG4_CF BIT(12) /* Control Frame */ 150 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */ 151 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ 152 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ 153 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ 154 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ 155 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ 156 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ 157 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ 158 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ 159 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ 160 FIFO_CFG4_VT) 161 162 #define AG71XX_REG_FIFO_CFG5 0x005c 163 #define FIFO_CFG5_DE BIT(0) /* Drop Event */ 164 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ 165 #define FIFO_CFG5_FC BIT(2) /* False Carrier */ 166 #define FIFO_CFG5_CE BIT(3) /* Code Error */ 167 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ 168 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ 169 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */ 170 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ 171 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ 172 #define FIFO_CFG5_DR BIT(9) /* Dribble */ 173 #define FIFO_CFG5_CF BIT(10) /* Control Frame */ 174 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */ 175 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ 176 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ 177 #define FIFO_CFG5_LE BIT(14) /* Long Event */ 178 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ 179 #define FIFO_CFG5_16 BIT(16) /* unknown */ 180 #define FIFO_CFG5_17 BIT(17) /* unknown */ 181 #define FIFO_CFG5_SF BIT(18) /* Short Frame */ 182 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */ 183 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ 184 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ 185 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ 186 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ 187 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ 188 FIFO_CFG5_17 | FIFO_CFG5_SF) 189 190 #define AG71XX_REG_TX_CTRL 0x0180 191 #define TX_CTRL_TXE BIT(0) /* Tx Enable */ 192 193 #define AG71XX_REG_TX_DESC 0x0184 194 #define AG71XX_REG_TX_STATUS 0x0188 195 #define TX_STATUS_PS BIT(0) /* Packet Sent */ 196 #define TX_STATUS_UR BIT(1) /* Tx Underrun */ 197 #define TX_STATUS_BE BIT(3) /* Bus Error */ 198 199 #define AG71XX_REG_RX_CTRL 0x018c 200 #define RX_CTRL_RXE BIT(0) /* Rx Enable */ 201 202 #define AG71XX_DMA_RETRY 10 203 #define AG71XX_DMA_DELAY 1 204 205 #define AG71XX_REG_RX_DESC 0x0190 206 #define AG71XX_REG_RX_STATUS 0x0194 207 #define RX_STATUS_PR BIT(0) /* Packet Received */ 208 #define RX_STATUS_OF BIT(2) /* Rx Overflow */ 209 #define RX_STATUS_BE BIT(3) /* Bus Error */ 210 211 #define AG71XX_REG_INT_ENABLE 0x0198 212 #define AG71XX_REG_INT_STATUS 0x019c 213 #define AG71XX_INT_TX_PS BIT(0) 214 #define AG71XX_INT_TX_UR BIT(1) 215 #define AG71XX_INT_TX_BE BIT(3) 216 #define AG71XX_INT_RX_PR BIT(4) 217 #define AG71XX_INT_RX_OF BIT(6) 218 #define AG71XX_INT_RX_BE BIT(7) 219 220 #define AG71XX_REG_FIFO_DEPTH 0x01a8 221 #define AG71XX_REG_RX_SM 0x01b0 222 #define AG71XX_REG_TX_SM 0x01b4 223 224 #define ETH_SWITCH_HEADER_LEN 2 225 226 #define AG71XX_DEFAULT_MSG_ENABLE \ 227 (NETIF_MSG_DRV \ 228 | NETIF_MSG_PROBE \ 229 | NETIF_MSG_LINK \ 230 | NETIF_MSG_TIMER \ 231 | NETIF_MSG_IFDOWN \ 232 | NETIF_MSG_IFUP \ 233 | NETIF_MSG_RX_ERR \ 234 | NETIF_MSG_TX_ERR) 235 236 #define DESC_EMPTY BIT(31) 237 #define DESC_MORE BIT(24) 238 #define DESC_PKTLEN_M 0xfff 239 struct ag71xx_desc { 240 u32 data; 241 u32 ctrl; 242 u32 next; 243 u32 pad; 244 } __aligned(4); 245 246 #define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \ 247 L1_CACHE_BYTES) 248 249 struct ag71xx_buf { 250 union { 251 struct { 252 struct sk_buff *skb; 253 unsigned int len; 254 } tx; 255 struct { 256 dma_addr_t dma_addr; 257 void *rx_buf; 258 } rx; 259 }; 260 }; 261 262 struct ag71xx_ring { 263 /* "Hot" fields in the data path. */ 264 unsigned int curr; 265 unsigned int dirty; 266 267 /* "Cold" fields - not used in the data path. */ 268 struct ag71xx_buf *buf; 269 u16 order; 270 u16 desc_split; 271 dma_addr_t descs_dma; 272 u8 *descs_cpu; 273 }; 274 275 enum ag71xx_type { 276 AR7100, 277 AR7240, 278 AR9130, 279 AR9330, 280 AR9340, 281 QCA9530, 282 QCA9550, 283 }; 284 285 struct ag71xx_dcfg { 286 u32 max_frame_len; 287 const u32 *fifodata; 288 u16 desc_pktlen_mask; 289 bool tx_hang_workaround; 290 enum ag71xx_type type; 291 }; 292 293 struct ag71xx { 294 /* Critical data related to the per-packet data path are clustered 295 * early in this structure to help improve the D-cache footprint. 296 */ 297 struct ag71xx_ring rx_ring ____cacheline_aligned; 298 struct ag71xx_ring tx_ring ____cacheline_aligned; 299 300 u16 rx_buf_size; 301 u8 rx_buf_offset; 302 303 struct net_device *ndev; 304 struct platform_device *pdev; 305 struct napi_struct napi; 306 u32 msg_enable; 307 const struct ag71xx_dcfg *dcfg; 308 309 /* From this point onwards we're not looking at per-packet fields. */ 310 void __iomem *mac_base; 311 312 struct ag71xx_desc *stop_desc; 313 dma_addr_t stop_desc_dma; 314 315 int phy_if_mode; 316 317 struct delayed_work restart_work; 318 struct timer_list oom_timer; 319 320 struct reset_control *mac_reset; 321 322 u32 fifodata[3]; 323 int mac_idx; 324 325 struct reset_control *mdio_reset; 326 struct mii_bus *mii_bus; 327 struct clk *clk_mdio; 328 struct clk *clk_eth; 329 }; 330 331 static int ag71xx_desc_empty(struct ag71xx_desc *desc) 332 { 333 return (desc->ctrl & DESC_EMPTY) != 0; 334 } 335 336 static struct ag71xx_desc *ag71xx_ring_desc(struct ag71xx_ring *ring, int idx) 337 { 338 return (struct ag71xx_desc *)&ring->descs_cpu[idx * AG71XX_DESC_SIZE]; 339 } 340 341 static int ag71xx_ring_size_order(int size) 342 { 343 return fls(size - 1); 344 } 345 346 static bool ag71xx_is(struct ag71xx *ag, enum ag71xx_type type) 347 { 348 return ag->dcfg->type == type; 349 } 350 351 static void ag71xx_wr(struct ag71xx *ag, unsigned int reg, u32 value) 352 { 353 iowrite32(value, ag->mac_base + reg); 354 /* flush write */ 355 (void)ioread32(ag->mac_base + reg); 356 } 357 358 static u32 ag71xx_rr(struct ag71xx *ag, unsigned int reg) 359 { 360 return ioread32(ag->mac_base + reg); 361 } 362 363 static void ag71xx_sb(struct ag71xx *ag, unsigned int reg, u32 mask) 364 { 365 void __iomem *r; 366 367 r = ag->mac_base + reg; 368 iowrite32(ioread32(r) | mask, r); 369 /* flush write */ 370 (void)ioread32(r); 371 } 372 373 static void ag71xx_cb(struct ag71xx *ag, unsigned int reg, u32 mask) 374 { 375 void __iomem *r; 376 377 r = ag->mac_base + reg; 378 iowrite32(ioread32(r) & ~mask, r); 379 /* flush write */ 380 (void)ioread32(r); 381 } 382 383 static void ag71xx_int_enable(struct ag71xx *ag, u32 ints) 384 { 385 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); 386 } 387 388 static void ag71xx_int_disable(struct ag71xx *ag, u32 ints) 389 { 390 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); 391 } 392 393 static int ag71xx_mdio_wait_busy(struct ag71xx *ag) 394 { 395 struct net_device *ndev = ag->ndev; 396 int i; 397 398 for (i = 0; i < AG71XX_MDIO_RETRY; i++) { 399 u32 busy; 400 401 udelay(AG71XX_MDIO_DELAY); 402 403 busy = ag71xx_rr(ag, AG71XX_REG_MII_IND); 404 if (!busy) 405 return 0; 406 407 udelay(AG71XX_MDIO_DELAY); 408 } 409 410 netif_err(ag, link, ndev, "MDIO operation timed out\n"); 411 412 return -ETIMEDOUT; 413 } 414 415 static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg) 416 { 417 struct ag71xx *ag = bus->priv; 418 int err, val; 419 420 err = ag71xx_mdio_wait_busy(ag); 421 if (err) 422 return err; 423 424 ag71xx_wr(ag, AG71XX_REG_MII_ADDR, 425 ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff)); 426 /* enable read mode */ 427 ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ); 428 429 err = ag71xx_mdio_wait_busy(ag); 430 if (err) 431 return err; 432 433 val = ag71xx_rr(ag, AG71XX_REG_MII_STATUS); 434 /* disable read mode */ 435 ag71xx_wr(ag, AG71XX_REG_MII_CMD, 0); 436 437 netif_dbg(ag, link, ag->ndev, "mii_read: addr=%04x, reg=%04x, value=%04x\n", 438 addr, reg, val); 439 440 return val; 441 } 442 443 static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg, 444 u16 val) 445 { 446 struct ag71xx *ag = bus->priv; 447 448 netif_dbg(ag, link, ag->ndev, "mii_write: addr=%04x, reg=%04x, value=%04x\n", 449 addr, reg, val); 450 451 ag71xx_wr(ag, AG71XX_REG_MII_ADDR, 452 ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff)); 453 ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val); 454 455 return ag71xx_mdio_wait_busy(ag); 456 } 457 458 static const u32 ar71xx_mdio_div_table[] = { 459 4, 4, 6, 8, 10, 14, 20, 28, 460 }; 461 462 static const u32 ar7240_mdio_div_table[] = { 463 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96, 464 }; 465 466 static const u32 ar933x_mdio_div_table[] = { 467 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98, 468 }; 469 470 static int ag71xx_mdio_get_divider(struct ag71xx *ag, u32 *div) 471 { 472 unsigned long ref_clock; 473 const u32 *table; 474 int ndivs, i; 475 476 ref_clock = clk_get_rate(ag->clk_mdio); 477 if (!ref_clock) 478 return -EINVAL; 479 480 if (ag71xx_is(ag, AR9330) || ag71xx_is(ag, AR9340)) { 481 table = ar933x_mdio_div_table; 482 ndivs = ARRAY_SIZE(ar933x_mdio_div_table); 483 } else if (ag71xx_is(ag, AR7240)) { 484 table = ar7240_mdio_div_table; 485 ndivs = ARRAY_SIZE(ar7240_mdio_div_table); 486 } else { 487 table = ar71xx_mdio_div_table; 488 ndivs = ARRAY_SIZE(ar71xx_mdio_div_table); 489 } 490 491 for (i = 0; i < ndivs; i++) { 492 unsigned long t; 493 494 t = ref_clock / table[i]; 495 if (t <= AG71XX_MDIO_MAX_CLK) { 496 *div = i; 497 return 0; 498 } 499 } 500 501 return -ENOENT; 502 } 503 504 static int ag71xx_mdio_reset(struct mii_bus *bus) 505 { 506 struct ag71xx *ag = bus->priv; 507 int err; 508 u32 t; 509 510 err = ag71xx_mdio_get_divider(ag, &t); 511 if (err) 512 return err; 513 514 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); 515 usleep_range(100, 200); 516 517 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t); 518 usleep_range(100, 200); 519 520 return 0; 521 } 522 523 static int ag71xx_mdio_probe(struct ag71xx *ag) 524 { 525 struct device *dev = &ag->pdev->dev; 526 struct net_device *ndev = ag->ndev; 527 static struct mii_bus *mii_bus; 528 struct device_node *np; 529 int err; 530 531 np = dev->of_node; 532 ag->mii_bus = NULL; 533 534 ag->clk_mdio = devm_clk_get(dev, "mdio"); 535 if (IS_ERR(ag->clk_mdio)) { 536 netif_err(ag, probe, ndev, "Failed to get mdio clk.\n"); 537 return PTR_ERR(ag->clk_mdio); 538 } 539 540 err = clk_prepare_enable(ag->clk_mdio); 541 if (err) { 542 netif_err(ag, probe, ndev, "Failed to enable mdio clk.\n"); 543 return err; 544 } 545 546 mii_bus = devm_mdiobus_alloc(dev); 547 if (!mii_bus) { 548 err = -ENOMEM; 549 goto mdio_err_put_clk; 550 } 551 552 ag->mdio_reset = of_reset_control_get_exclusive(np, "mdio"); 553 if (IS_ERR(ag->mdio_reset)) { 554 netif_err(ag, probe, ndev, "Failed to get reset mdio.\n"); 555 return PTR_ERR(ag->mdio_reset); 556 } 557 558 mii_bus->name = "ag71xx_mdio"; 559 mii_bus->read = ag71xx_mdio_mii_read; 560 mii_bus->write = ag71xx_mdio_mii_write; 561 mii_bus->reset = ag71xx_mdio_reset; 562 mii_bus->priv = ag; 563 mii_bus->parent = dev; 564 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, ag->mac_idx); 565 566 if (!IS_ERR(ag->mdio_reset)) { 567 reset_control_assert(ag->mdio_reset); 568 msleep(100); 569 reset_control_deassert(ag->mdio_reset); 570 msleep(200); 571 } 572 573 err = of_mdiobus_register(mii_bus, np); 574 if (err) 575 goto mdio_err_put_clk; 576 577 ag->mii_bus = mii_bus; 578 579 return 0; 580 581 mdio_err_put_clk: 582 clk_disable_unprepare(ag->clk_mdio); 583 return err; 584 } 585 586 static void ag71xx_mdio_remove(struct ag71xx *ag) 587 { 588 if (ag->mii_bus) 589 mdiobus_unregister(ag->mii_bus); 590 clk_disable_unprepare(ag->clk_mdio); 591 } 592 593 static void ag71xx_hw_stop(struct ag71xx *ag) 594 { 595 /* disable all interrupts and stop the rx/tx engine */ 596 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); 597 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); 598 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); 599 } 600 601 static bool ag71xx_check_dma_stuck(struct ag71xx *ag) 602 { 603 unsigned long timestamp; 604 u32 rx_sm, tx_sm, rx_fd; 605 606 timestamp = netdev_get_tx_queue(ag->ndev, 0)->trans_start; 607 if (likely(time_before(jiffies, timestamp + HZ / 10))) 608 return false; 609 610 if (!netif_carrier_ok(ag->ndev)) 611 return false; 612 613 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM); 614 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6) 615 return true; 616 617 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM); 618 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH); 619 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) && 620 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0) 621 return true; 622 623 return false; 624 } 625 626 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush) 627 { 628 struct ag71xx_ring *ring = &ag->tx_ring; 629 int sent = 0, bytes_compl = 0, n = 0; 630 struct net_device *ndev = ag->ndev; 631 int ring_mask, ring_size; 632 bool dma_stuck = false; 633 634 ring_mask = BIT(ring->order) - 1; 635 ring_size = BIT(ring->order); 636 637 netif_dbg(ag, tx_queued, ndev, "processing TX ring\n"); 638 639 while (ring->dirty + n != ring->curr) { 640 struct ag71xx_desc *desc; 641 struct sk_buff *skb; 642 unsigned int i; 643 644 i = (ring->dirty + n) & ring_mask; 645 desc = ag71xx_ring_desc(ring, i); 646 skb = ring->buf[i].tx.skb; 647 648 if (!flush && !ag71xx_desc_empty(desc)) { 649 if (ag->dcfg->tx_hang_workaround && 650 ag71xx_check_dma_stuck(ag)) { 651 schedule_delayed_work(&ag->restart_work, 652 HZ / 2); 653 dma_stuck = true; 654 } 655 break; 656 } 657 658 if (flush) 659 desc->ctrl |= DESC_EMPTY; 660 661 n++; 662 if (!skb) 663 continue; 664 665 dev_kfree_skb_any(skb); 666 ring->buf[i].tx.skb = NULL; 667 668 bytes_compl += ring->buf[i].tx.len; 669 670 sent++; 671 ring->dirty += n; 672 673 while (n > 0) { 674 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); 675 n--; 676 } 677 } 678 679 netif_dbg(ag, tx_done, ndev, "%d packets sent out\n", sent); 680 681 if (!sent) 682 return 0; 683 684 ag->ndev->stats.tx_bytes += bytes_compl; 685 ag->ndev->stats.tx_packets += sent; 686 687 netdev_completed_queue(ag->ndev, sent, bytes_compl); 688 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4) 689 netif_wake_queue(ag->ndev); 690 691 if (!dma_stuck) 692 cancel_delayed_work(&ag->restart_work); 693 694 return sent; 695 } 696 697 static void ag71xx_dma_wait_stop(struct ag71xx *ag) 698 { 699 struct net_device *ndev = ag->ndev; 700 int i; 701 702 for (i = 0; i < AG71XX_DMA_RETRY; i++) { 703 u32 rx, tx; 704 705 mdelay(AG71XX_DMA_DELAY); 706 707 rx = ag71xx_rr(ag, AG71XX_REG_RX_CTRL) & RX_CTRL_RXE; 708 tx = ag71xx_rr(ag, AG71XX_REG_TX_CTRL) & TX_CTRL_TXE; 709 if (!rx && !tx) 710 return; 711 } 712 713 netif_err(ag, hw, ndev, "DMA stop operation timed out\n"); 714 } 715 716 static void ag71xx_dma_reset(struct ag71xx *ag) 717 { 718 struct net_device *ndev = ag->ndev; 719 u32 val; 720 int i; 721 722 /* stop RX and TX */ 723 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); 724 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); 725 726 /* give the hardware some time to really stop all rx/tx activity 727 * clearing the descriptors too early causes random memory corruption 728 */ 729 ag71xx_dma_wait_stop(ag); 730 731 /* clear descriptor addresses */ 732 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma); 733 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma); 734 735 /* clear pending RX/TX interrupts */ 736 for (i = 0; i < 256; i++) { 737 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); 738 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); 739 } 740 741 /* clear pending errors */ 742 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); 743 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); 744 745 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); 746 if (val) 747 netif_err(ag, hw, ndev, "unable to clear DMA Rx status: %08x\n", 748 val); 749 750 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); 751 752 /* mask out reserved bits */ 753 val &= ~0xff000000; 754 755 if (val) 756 netif_err(ag, hw, ndev, "unable to clear DMA Tx status: %08x\n", 757 val); 758 } 759 760 static void ag71xx_hw_setup(struct ag71xx *ag) 761 { 762 u32 init = MAC_CFG1_INIT; 763 764 /* setup MAC configuration registers */ 765 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init); 766 767 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, 768 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); 769 770 /* setup max frame length to zero */ 771 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0); 772 773 /* setup FIFO configuration registers */ 774 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); 775 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]); 776 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]); 777 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); 778 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); 779 } 780 781 static unsigned int ag71xx_max_frame_len(unsigned int mtu) 782 { 783 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN; 784 } 785 786 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) 787 { 788 u32 t; 789 790 t = (((u32)mac[5]) << 24) | (((u32)mac[4]) << 16) 791 | (((u32)mac[3]) << 8) | ((u32)mac[2]); 792 793 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); 794 795 t = (((u32)mac[1]) << 24) | (((u32)mac[0]) << 16); 796 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); 797 } 798 799 static void ag71xx_fast_reset(struct ag71xx *ag) 800 { 801 struct net_device *dev = ag->ndev; 802 u32 rx_ds; 803 u32 mii_reg; 804 805 ag71xx_hw_stop(ag); 806 807 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG); 808 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC); 809 810 ag71xx_tx_packets(ag, true); 811 812 reset_control_assert(ag->mac_reset); 813 usleep_range(10, 20); 814 reset_control_deassert(ag->mac_reset); 815 usleep_range(10, 20); 816 817 ag71xx_dma_reset(ag); 818 ag71xx_hw_setup(ag); 819 ag->tx_ring.curr = 0; 820 ag->tx_ring.dirty = 0; 821 netdev_reset_queue(ag->ndev); 822 823 /* setup max frame length */ 824 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 825 ag71xx_max_frame_len(ag->ndev->mtu)); 826 827 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds); 828 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); 829 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg); 830 831 ag71xx_hw_set_macaddr(ag, dev->dev_addr); 832 } 833 834 static void ag71xx_hw_start(struct ag71xx *ag) 835 { 836 /* start RX engine */ 837 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); 838 839 /* enable interrupts */ 840 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); 841 842 netif_wake_queue(ag->ndev); 843 } 844 845 static void ag71xx_link_adjust(struct ag71xx *ag, bool update) 846 { 847 struct phy_device *phydev = ag->ndev->phydev; 848 u32 cfg2; 849 u32 ifctl; 850 u32 fifo5; 851 852 if (!phydev->link && update) { 853 ag71xx_hw_stop(ag); 854 return; 855 } 856 857 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130)) 858 ag71xx_fast_reset(ag); 859 860 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); 861 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); 862 cfg2 |= (phydev->duplex) ? MAC_CFG2_FDX : 0; 863 864 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); 865 ifctl &= ~(MAC_IFCTL_SPEED); 866 867 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); 868 fifo5 &= ~FIFO_CFG5_BM; 869 870 switch (phydev->speed) { 871 case SPEED_1000: 872 cfg2 |= MAC_CFG2_IF_1000; 873 fifo5 |= FIFO_CFG5_BM; 874 break; 875 case SPEED_100: 876 cfg2 |= MAC_CFG2_IF_10_100; 877 ifctl |= MAC_IFCTL_SPEED; 878 break; 879 case SPEED_10: 880 cfg2 |= MAC_CFG2_IF_10_100; 881 break; 882 default: 883 WARN(1, "not supported speed %i\n", phydev->speed); 884 return; 885 } 886 887 if (ag->tx_ring.desc_split) { 888 ag->fifodata[2] &= 0xffff; 889 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16; 890 } 891 892 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]); 893 894 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); 895 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); 896 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); 897 898 ag71xx_hw_start(ag); 899 900 if (update) 901 phy_print_status(phydev); 902 } 903 904 static void ag71xx_phy_link_adjust(struct net_device *ndev) 905 { 906 struct ag71xx *ag = netdev_priv(ndev); 907 908 ag71xx_link_adjust(ag, true); 909 } 910 911 static int ag71xx_phy_connect(struct ag71xx *ag) 912 { 913 struct device_node *np = ag->pdev->dev.of_node; 914 struct net_device *ndev = ag->ndev; 915 struct device_node *phy_node; 916 struct phy_device *phydev; 917 int ret; 918 919 if (of_phy_is_fixed_link(np)) { 920 ret = of_phy_register_fixed_link(np); 921 if (ret < 0) { 922 netif_err(ag, probe, ndev, "Failed to register fixed PHY link: %d\n", 923 ret); 924 return ret; 925 } 926 927 phy_node = of_node_get(np); 928 } else { 929 phy_node = of_parse_phandle(np, "phy-handle", 0); 930 } 931 932 if (!phy_node) { 933 netif_err(ag, probe, ndev, "Could not find valid phy node\n"); 934 return -ENODEV; 935 } 936 937 phydev = of_phy_connect(ag->ndev, phy_node, ag71xx_phy_link_adjust, 938 0, ag->phy_if_mode); 939 940 of_node_put(phy_node); 941 942 if (!phydev) { 943 netif_err(ag, probe, ndev, "Could not connect to PHY device\n"); 944 return -ENODEV; 945 } 946 947 phy_attached_info(phydev); 948 949 return 0; 950 } 951 952 static void ag71xx_ring_tx_clean(struct ag71xx *ag) 953 { 954 struct ag71xx_ring *ring = &ag->tx_ring; 955 int ring_mask = BIT(ring->order) - 1; 956 u32 bytes_compl = 0, pkts_compl = 0; 957 struct net_device *ndev = ag->ndev; 958 959 while (ring->curr != ring->dirty) { 960 struct ag71xx_desc *desc; 961 u32 i = ring->dirty & ring_mask; 962 963 desc = ag71xx_ring_desc(ring, i); 964 if (!ag71xx_desc_empty(desc)) { 965 desc->ctrl = 0; 966 ndev->stats.tx_errors++; 967 } 968 969 if (ring->buf[i].tx.skb) { 970 bytes_compl += ring->buf[i].tx.len; 971 pkts_compl++; 972 dev_kfree_skb_any(ring->buf[i].tx.skb); 973 } 974 ring->buf[i].tx.skb = NULL; 975 ring->dirty++; 976 } 977 978 /* flush descriptors */ 979 wmb(); 980 981 netdev_completed_queue(ndev, pkts_compl, bytes_compl); 982 } 983 984 static void ag71xx_ring_tx_init(struct ag71xx *ag) 985 { 986 struct ag71xx_ring *ring = &ag->tx_ring; 987 int ring_size = BIT(ring->order); 988 int ring_mask = ring_size - 1; 989 int i; 990 991 for (i = 0; i < ring_size; i++) { 992 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 993 994 desc->next = (u32)(ring->descs_dma + 995 AG71XX_DESC_SIZE * ((i + 1) & ring_mask)); 996 997 desc->ctrl = DESC_EMPTY; 998 ring->buf[i].tx.skb = NULL; 999 } 1000 1001 /* flush descriptors */ 1002 wmb(); 1003 1004 ring->curr = 0; 1005 ring->dirty = 0; 1006 netdev_reset_queue(ag->ndev); 1007 } 1008 1009 static void ag71xx_ring_rx_clean(struct ag71xx *ag) 1010 { 1011 struct ag71xx_ring *ring = &ag->rx_ring; 1012 int ring_size = BIT(ring->order); 1013 int i; 1014 1015 if (!ring->buf) 1016 return; 1017 1018 for (i = 0; i < ring_size; i++) 1019 if (ring->buf[i].rx.rx_buf) { 1020 dma_unmap_single(&ag->pdev->dev, 1021 ring->buf[i].rx.dma_addr, 1022 ag->rx_buf_size, DMA_FROM_DEVICE); 1023 skb_free_frag(ring->buf[i].rx.rx_buf); 1024 } 1025 } 1026 1027 static int ag71xx_buffer_size(struct ag71xx *ag) 1028 { 1029 return ag->rx_buf_size + 1030 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1031 } 1032 1033 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf, 1034 int offset, 1035 void *(*alloc)(unsigned int size)) 1036 { 1037 struct ag71xx_ring *ring = &ag->rx_ring; 1038 struct ag71xx_desc *desc; 1039 void *data; 1040 1041 desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]); 1042 1043 data = alloc(ag71xx_buffer_size(ag)); 1044 if (!data) 1045 return false; 1046 1047 buf->rx.rx_buf = data; 1048 buf->rx.dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size, 1049 DMA_FROM_DEVICE); 1050 desc->data = (u32)buf->rx.dma_addr + offset; 1051 return true; 1052 } 1053 1054 static int ag71xx_ring_rx_init(struct ag71xx *ag) 1055 { 1056 struct ag71xx_ring *ring = &ag->rx_ring; 1057 struct net_device *ndev = ag->ndev; 1058 int ring_mask = BIT(ring->order) - 1; 1059 int ring_size = BIT(ring->order); 1060 unsigned int i; 1061 int ret; 1062 1063 ret = 0; 1064 for (i = 0; i < ring_size; i++) { 1065 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1066 1067 desc->next = (u32)(ring->descs_dma + 1068 AG71XX_DESC_SIZE * ((i + 1) & ring_mask)); 1069 1070 netif_dbg(ag, rx_status, ndev, "RX desc at %p, next is %08x\n", 1071 desc, desc->next); 1072 } 1073 1074 for (i = 0; i < ring_size; i++) { 1075 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1076 1077 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset, 1078 netdev_alloc_frag)) { 1079 ret = -ENOMEM; 1080 break; 1081 } 1082 1083 desc->ctrl = DESC_EMPTY; 1084 } 1085 1086 /* flush descriptors */ 1087 wmb(); 1088 1089 ring->curr = 0; 1090 ring->dirty = 0; 1091 1092 return ret; 1093 } 1094 1095 static int ag71xx_ring_rx_refill(struct ag71xx *ag) 1096 { 1097 struct ag71xx_ring *ring = &ag->rx_ring; 1098 int ring_mask = BIT(ring->order) - 1; 1099 int offset = ag->rx_buf_offset; 1100 unsigned int count; 1101 1102 count = 0; 1103 for (; ring->curr - ring->dirty > 0; ring->dirty++) { 1104 struct ag71xx_desc *desc; 1105 unsigned int i; 1106 1107 i = ring->dirty & ring_mask; 1108 desc = ag71xx_ring_desc(ring, i); 1109 1110 if (!ring->buf[i].rx.rx_buf && 1111 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset, 1112 napi_alloc_frag)) 1113 break; 1114 1115 desc->ctrl = DESC_EMPTY; 1116 count++; 1117 } 1118 1119 /* flush descriptors */ 1120 wmb(); 1121 1122 netif_dbg(ag, rx_status, ag->ndev, "%u rx descriptors refilled\n", 1123 count); 1124 1125 return count; 1126 } 1127 1128 static int ag71xx_rings_init(struct ag71xx *ag) 1129 { 1130 struct ag71xx_ring *tx = &ag->tx_ring; 1131 struct ag71xx_ring *rx = &ag->rx_ring; 1132 int ring_size, tx_size; 1133 1134 ring_size = BIT(tx->order) + BIT(rx->order); 1135 tx_size = BIT(tx->order); 1136 1137 tx->buf = kcalloc(ring_size, sizeof(*tx->buf), GFP_KERNEL); 1138 if (!tx->buf) 1139 return -ENOMEM; 1140 1141 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, 1142 ring_size * AG71XX_DESC_SIZE, 1143 &tx->descs_dma, GFP_ATOMIC); 1144 if (!tx->descs_cpu) { 1145 kfree(tx->buf); 1146 tx->buf = NULL; 1147 return -ENOMEM; 1148 } 1149 1150 rx->buf = &tx->buf[BIT(tx->order)]; 1151 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE; 1152 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE; 1153 1154 ag71xx_ring_tx_init(ag); 1155 return ag71xx_ring_rx_init(ag); 1156 } 1157 1158 static void ag71xx_rings_free(struct ag71xx *ag) 1159 { 1160 struct ag71xx_ring *tx = &ag->tx_ring; 1161 struct ag71xx_ring *rx = &ag->rx_ring; 1162 int ring_size; 1163 1164 ring_size = BIT(tx->order) + BIT(rx->order); 1165 1166 if (tx->descs_cpu) 1167 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE, 1168 tx->descs_cpu, tx->descs_dma); 1169 1170 kfree(tx->buf); 1171 1172 tx->descs_cpu = NULL; 1173 rx->descs_cpu = NULL; 1174 tx->buf = NULL; 1175 rx->buf = NULL; 1176 } 1177 1178 static void ag71xx_rings_cleanup(struct ag71xx *ag) 1179 { 1180 ag71xx_ring_rx_clean(ag); 1181 ag71xx_ring_tx_clean(ag); 1182 ag71xx_rings_free(ag); 1183 1184 netdev_reset_queue(ag->ndev); 1185 } 1186 1187 static void ag71xx_hw_init(struct ag71xx *ag) 1188 { 1189 ag71xx_hw_stop(ag); 1190 1191 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); 1192 usleep_range(20, 30); 1193 1194 reset_control_assert(ag->mac_reset); 1195 msleep(100); 1196 reset_control_deassert(ag->mac_reset); 1197 msleep(200); 1198 1199 ag71xx_hw_setup(ag); 1200 1201 ag71xx_dma_reset(ag); 1202 } 1203 1204 static int ag71xx_hw_enable(struct ag71xx *ag) 1205 { 1206 int ret; 1207 1208 ret = ag71xx_rings_init(ag); 1209 if (ret) 1210 return ret; 1211 1212 napi_enable(&ag->napi); 1213 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); 1214 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); 1215 netif_start_queue(ag->ndev); 1216 1217 return 0; 1218 } 1219 1220 static void ag71xx_hw_disable(struct ag71xx *ag) 1221 { 1222 netif_stop_queue(ag->ndev); 1223 1224 ag71xx_hw_stop(ag); 1225 ag71xx_dma_reset(ag); 1226 1227 napi_disable(&ag->napi); 1228 del_timer_sync(&ag->oom_timer); 1229 1230 ag71xx_rings_cleanup(ag); 1231 } 1232 1233 static int ag71xx_open(struct net_device *ndev) 1234 { 1235 struct ag71xx *ag = netdev_priv(ndev); 1236 unsigned int max_frame_len; 1237 int ret; 1238 1239 max_frame_len = ag71xx_max_frame_len(ndev->mtu); 1240 ag->rx_buf_size = 1241 SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN); 1242 1243 /* setup max frame length */ 1244 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len); 1245 ag71xx_hw_set_macaddr(ag, ndev->dev_addr); 1246 1247 ret = ag71xx_hw_enable(ag); 1248 if (ret) 1249 goto err; 1250 1251 ret = ag71xx_phy_connect(ag); 1252 if (ret) 1253 goto err; 1254 1255 phy_start(ndev->phydev); 1256 1257 return 0; 1258 1259 err: 1260 ag71xx_rings_cleanup(ag); 1261 return ret; 1262 } 1263 1264 static int ag71xx_stop(struct net_device *ndev) 1265 { 1266 struct ag71xx *ag = netdev_priv(ndev); 1267 1268 phy_stop(ndev->phydev); 1269 phy_disconnect(ndev->phydev); 1270 ag71xx_hw_disable(ag); 1271 1272 return 0; 1273 } 1274 1275 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len) 1276 { 1277 int i, ring_mask, ndesc, split; 1278 struct ag71xx_desc *desc; 1279 1280 ring_mask = BIT(ring->order) - 1; 1281 ndesc = 0; 1282 split = ring->desc_split; 1283 1284 if (!split) 1285 split = len; 1286 1287 while (len > 0) { 1288 unsigned int cur_len = len; 1289 1290 i = (ring->curr + ndesc) & ring_mask; 1291 desc = ag71xx_ring_desc(ring, i); 1292 1293 if (!ag71xx_desc_empty(desc)) 1294 return -1; 1295 1296 if (cur_len > split) { 1297 cur_len = split; 1298 1299 /* TX will hang if DMA transfers <= 4 bytes, 1300 * make sure next segment is more than 4 bytes long. 1301 */ 1302 if (len <= split + 4) 1303 cur_len -= 4; 1304 } 1305 1306 desc->data = addr; 1307 addr += cur_len; 1308 len -= cur_len; 1309 1310 if (len > 0) 1311 cur_len |= DESC_MORE; 1312 1313 /* prevent early tx attempt of this descriptor */ 1314 if (!ndesc) 1315 cur_len |= DESC_EMPTY; 1316 1317 desc->ctrl = cur_len; 1318 ndesc++; 1319 } 1320 1321 return ndesc; 1322 } 1323 1324 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, 1325 struct net_device *ndev) 1326 { 1327 int i, n, ring_min, ring_mask, ring_size; 1328 struct ag71xx *ag = netdev_priv(ndev); 1329 struct ag71xx_ring *ring; 1330 struct ag71xx_desc *desc; 1331 dma_addr_t dma_addr; 1332 1333 ring = &ag->tx_ring; 1334 ring_mask = BIT(ring->order) - 1; 1335 ring_size = BIT(ring->order); 1336 1337 if (skb->len <= 4) { 1338 netif_dbg(ag, tx_err, ndev, "packet len is too small\n"); 1339 goto err_drop; 1340 } 1341 1342 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len, 1343 DMA_TO_DEVICE); 1344 1345 i = ring->curr & ring_mask; 1346 desc = ag71xx_ring_desc(ring, i); 1347 1348 /* setup descriptor fields */ 1349 n = ag71xx_fill_dma_desc(ring, (u32)dma_addr, 1350 skb->len & ag->dcfg->desc_pktlen_mask); 1351 if (n < 0) 1352 goto err_drop_unmap; 1353 1354 i = (ring->curr + n - 1) & ring_mask; 1355 ring->buf[i].tx.len = skb->len; 1356 ring->buf[i].tx.skb = skb; 1357 1358 netdev_sent_queue(ndev, skb->len); 1359 1360 skb_tx_timestamp(skb); 1361 1362 desc->ctrl &= ~DESC_EMPTY; 1363 ring->curr += n; 1364 1365 /* flush descriptor */ 1366 wmb(); 1367 1368 ring_min = 2; 1369 if (ring->desc_split) 1370 ring_min *= AG71XX_TX_RING_DS_PER_PKT; 1371 1372 if (ring->curr - ring->dirty >= ring_size - ring_min) { 1373 netif_dbg(ag, tx_err, ndev, "tx queue full\n"); 1374 netif_stop_queue(ndev); 1375 } 1376 1377 netif_dbg(ag, tx_queued, ndev, "packet injected into TX queue\n"); 1378 1379 /* enable TX engine */ 1380 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); 1381 1382 return NETDEV_TX_OK; 1383 1384 err_drop_unmap: 1385 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE); 1386 1387 err_drop: 1388 ndev->stats.tx_dropped++; 1389 1390 dev_kfree_skb(skb); 1391 return NETDEV_TX_OK; 1392 } 1393 1394 static int ag71xx_do_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 1395 { 1396 if (!ndev->phydev) 1397 return -EINVAL; 1398 1399 return phy_mii_ioctl(ndev->phydev, ifr, cmd); 1400 } 1401 1402 static void ag71xx_oom_timer_handler(struct timer_list *t) 1403 { 1404 struct ag71xx *ag = from_timer(ag, t, oom_timer); 1405 1406 napi_schedule(&ag->napi); 1407 } 1408 1409 static void ag71xx_tx_timeout(struct net_device *ndev) 1410 { 1411 struct ag71xx *ag = netdev_priv(ndev); 1412 1413 netif_err(ag, tx_err, ndev, "tx timeout\n"); 1414 1415 schedule_delayed_work(&ag->restart_work, 1); 1416 } 1417 1418 static void ag71xx_restart_work_func(struct work_struct *work) 1419 { 1420 struct ag71xx *ag = container_of(work, struct ag71xx, 1421 restart_work.work); 1422 struct net_device *ndev = ag->ndev; 1423 1424 rtnl_lock(); 1425 ag71xx_hw_disable(ag); 1426 ag71xx_hw_enable(ag); 1427 if (ndev->phydev->link) 1428 ag71xx_link_adjust(ag, false); 1429 rtnl_unlock(); 1430 } 1431 1432 static int ag71xx_rx_packets(struct ag71xx *ag, int limit) 1433 { 1434 struct net_device *ndev = ag->ndev; 1435 int ring_mask, ring_size, done = 0; 1436 unsigned int pktlen_mask, offset; 1437 struct sk_buff *next, *skb; 1438 struct ag71xx_ring *ring; 1439 struct list_head rx_list; 1440 1441 ring = &ag->rx_ring; 1442 pktlen_mask = ag->dcfg->desc_pktlen_mask; 1443 offset = ag->rx_buf_offset; 1444 ring_mask = BIT(ring->order) - 1; 1445 ring_size = BIT(ring->order); 1446 1447 netif_dbg(ag, rx_status, ndev, "rx packets, limit=%d, curr=%u, dirty=%u\n", 1448 limit, ring->curr, ring->dirty); 1449 1450 INIT_LIST_HEAD(&rx_list); 1451 1452 while (done < limit) { 1453 unsigned int i = ring->curr & ring_mask; 1454 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1455 int pktlen; 1456 int err = 0; 1457 1458 if (ag71xx_desc_empty(desc)) 1459 break; 1460 1461 if ((ring->dirty + ring_size) == ring->curr) { 1462 WARN_ONCE(1, "RX out of ring"); 1463 break; 1464 } 1465 1466 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); 1467 1468 pktlen = desc->ctrl & pktlen_mask; 1469 pktlen -= ETH_FCS_LEN; 1470 1471 dma_unmap_single(&ag->pdev->dev, ring->buf[i].rx.dma_addr, 1472 ag->rx_buf_size, DMA_FROM_DEVICE); 1473 1474 ndev->stats.rx_packets++; 1475 ndev->stats.rx_bytes += pktlen; 1476 1477 skb = build_skb(ring->buf[i].rx.rx_buf, ag71xx_buffer_size(ag)); 1478 if (!skb) { 1479 skb_free_frag(ring->buf[i].rx.rx_buf); 1480 goto next; 1481 } 1482 1483 skb_reserve(skb, offset); 1484 skb_put(skb, pktlen); 1485 1486 if (err) { 1487 ndev->stats.rx_dropped++; 1488 kfree_skb(skb); 1489 } else { 1490 skb->dev = ndev; 1491 skb->ip_summed = CHECKSUM_NONE; 1492 list_add_tail(&skb->list, &rx_list); 1493 } 1494 1495 next: 1496 ring->buf[i].rx.rx_buf = NULL; 1497 done++; 1498 1499 ring->curr++; 1500 } 1501 1502 ag71xx_ring_rx_refill(ag); 1503 1504 list_for_each_entry_safe(skb, next, &rx_list, list) 1505 skb->protocol = eth_type_trans(skb, ndev); 1506 netif_receive_skb_list(&rx_list); 1507 1508 netif_dbg(ag, rx_status, ndev, "rx finish, curr=%u, dirty=%u, done=%d\n", 1509 ring->curr, ring->dirty, done); 1510 1511 return done; 1512 } 1513 1514 static int ag71xx_poll(struct napi_struct *napi, int limit) 1515 { 1516 struct ag71xx *ag = container_of(napi, struct ag71xx, napi); 1517 struct ag71xx_ring *rx_ring = &ag->rx_ring; 1518 int rx_ring_size = BIT(rx_ring->order); 1519 struct net_device *ndev = ag->ndev; 1520 int tx_done, rx_done; 1521 u32 status; 1522 1523 tx_done = ag71xx_tx_packets(ag, false); 1524 1525 netif_dbg(ag, rx_status, ndev, "processing RX ring\n"); 1526 rx_done = ag71xx_rx_packets(ag, limit); 1527 1528 if (!rx_ring->buf[rx_ring->dirty % rx_ring_size].rx.rx_buf) 1529 goto oom; 1530 1531 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); 1532 if (unlikely(status & RX_STATUS_OF)) { 1533 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); 1534 ndev->stats.rx_fifo_errors++; 1535 1536 /* restart RX */ 1537 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); 1538 } 1539 1540 if (rx_done < limit) { 1541 if (status & RX_STATUS_PR) 1542 goto more; 1543 1544 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); 1545 if (status & TX_STATUS_PS) 1546 goto more; 1547 1548 netif_dbg(ag, rx_status, ndev, "disable polling mode, rx=%d, tx=%d,limit=%d\n", 1549 rx_done, tx_done, limit); 1550 1551 napi_complete(napi); 1552 1553 /* enable interrupts */ 1554 ag71xx_int_enable(ag, AG71XX_INT_POLL); 1555 return rx_done; 1556 } 1557 1558 more: 1559 netif_dbg(ag, rx_status, ndev, "stay in polling mode, rx=%d, tx=%d, limit=%d\n", 1560 rx_done, tx_done, limit); 1561 return limit; 1562 1563 oom: 1564 netif_err(ag, rx_err, ndev, "out of memory\n"); 1565 1566 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); 1567 napi_complete(napi); 1568 return 0; 1569 } 1570 1571 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) 1572 { 1573 struct net_device *ndev = dev_id; 1574 struct ag71xx *ag; 1575 u32 status; 1576 1577 ag = netdev_priv(ndev); 1578 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); 1579 1580 if (unlikely(!status)) 1581 return IRQ_NONE; 1582 1583 if (unlikely(status & AG71XX_INT_ERR)) { 1584 if (status & AG71XX_INT_TX_BE) { 1585 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); 1586 netif_err(ag, intr, ndev, "TX BUS error\n"); 1587 } 1588 if (status & AG71XX_INT_RX_BE) { 1589 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); 1590 netif_err(ag, intr, ndev, "RX BUS error\n"); 1591 } 1592 } 1593 1594 if (likely(status & AG71XX_INT_POLL)) { 1595 ag71xx_int_disable(ag, AG71XX_INT_POLL); 1596 netif_dbg(ag, intr, ndev, "enable polling mode\n"); 1597 napi_schedule(&ag->napi); 1598 } 1599 1600 return IRQ_HANDLED; 1601 } 1602 1603 static int ag71xx_change_mtu(struct net_device *ndev, int new_mtu) 1604 { 1605 struct ag71xx *ag = netdev_priv(ndev); 1606 1607 ndev->mtu = new_mtu; 1608 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 1609 ag71xx_max_frame_len(ndev->mtu)); 1610 1611 return 0; 1612 } 1613 1614 static const struct net_device_ops ag71xx_netdev_ops = { 1615 .ndo_open = ag71xx_open, 1616 .ndo_stop = ag71xx_stop, 1617 .ndo_start_xmit = ag71xx_hard_start_xmit, 1618 .ndo_do_ioctl = ag71xx_do_ioctl, 1619 .ndo_tx_timeout = ag71xx_tx_timeout, 1620 .ndo_change_mtu = ag71xx_change_mtu, 1621 .ndo_set_mac_address = eth_mac_addr, 1622 .ndo_validate_addr = eth_validate_addr, 1623 }; 1624 1625 static const u32 ar71xx_addr_ar7100[] = { 1626 0x19000000, 0x1a000000, 1627 }; 1628 1629 static int ag71xx_probe(struct platform_device *pdev) 1630 { 1631 struct device_node *np = pdev->dev.of_node; 1632 const struct ag71xx_dcfg *dcfg; 1633 struct net_device *ndev; 1634 struct resource *res; 1635 const void *mac_addr; 1636 int tx_size, err, i; 1637 struct ag71xx *ag; 1638 1639 if (!np) 1640 return -ENODEV; 1641 1642 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag)); 1643 if (!ndev) 1644 return -ENOMEM; 1645 1646 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1647 if (!res) 1648 return -EINVAL; 1649 1650 dcfg = of_device_get_match_data(&pdev->dev); 1651 if (!dcfg) 1652 return -EINVAL; 1653 1654 ag = netdev_priv(ndev); 1655 ag->mac_idx = -1; 1656 for (i = 0; i < ARRAY_SIZE(ar71xx_addr_ar7100); i++) { 1657 if (ar71xx_addr_ar7100[i] == res->start) 1658 ag->mac_idx = i; 1659 } 1660 1661 if (ag->mac_idx < 0) { 1662 netif_err(ag, probe, ndev, "unknown mac idx\n"); 1663 return -EINVAL; 1664 } 1665 1666 ag->clk_eth = devm_clk_get(&pdev->dev, "eth"); 1667 if (IS_ERR(ag->clk_eth)) { 1668 netif_err(ag, probe, ndev, "Failed to get eth clk.\n"); 1669 return PTR_ERR(ag->clk_eth); 1670 } 1671 1672 SET_NETDEV_DEV(ndev, &pdev->dev); 1673 1674 ag->pdev = pdev; 1675 ag->ndev = ndev; 1676 ag->dcfg = dcfg; 1677 ag->msg_enable = netif_msg_init(-1, AG71XX_DEFAULT_MSG_ENABLE); 1678 memcpy(ag->fifodata, dcfg->fifodata, sizeof(ag->fifodata)); 1679 1680 ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac"); 1681 if (IS_ERR(ag->mac_reset)) { 1682 netif_err(ag, probe, ndev, "missing mac reset\n"); 1683 err = PTR_ERR(ag->mac_reset); 1684 goto err_free; 1685 } 1686 1687 ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start, 1688 res->end - res->start + 1); 1689 if (!ag->mac_base) { 1690 err = -ENOMEM; 1691 goto err_free; 1692 } 1693 1694 ndev->irq = platform_get_irq(pdev, 0); 1695 err = devm_request_irq(&pdev->dev, ndev->irq, ag71xx_interrupt, 1696 0x0, dev_name(&pdev->dev), ndev); 1697 if (err) { 1698 netif_err(ag, probe, ndev, "unable to request IRQ %d\n", 1699 ndev->irq); 1700 goto err_free; 1701 } 1702 1703 ndev->netdev_ops = &ag71xx_netdev_ops; 1704 1705 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func); 1706 timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0); 1707 1708 tx_size = AG71XX_TX_RING_SIZE_DEFAULT; 1709 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT); 1710 1711 ndev->min_mtu = 68; 1712 ndev->max_mtu = dcfg->max_frame_len - ag71xx_max_frame_len(0); 1713 1714 ag->rx_buf_offset = NET_SKB_PAD; 1715 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130)) 1716 ag->rx_buf_offset += NET_IP_ALIGN; 1717 1718 if (ag71xx_is(ag, AR7100)) { 1719 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT; 1720 tx_size *= AG71XX_TX_RING_DS_PER_PKT; 1721 } 1722 ag->tx_ring.order = ag71xx_ring_size_order(tx_size); 1723 1724 ag->stop_desc = dmam_alloc_coherent(&pdev->dev, 1725 sizeof(struct ag71xx_desc), 1726 &ag->stop_desc_dma, GFP_KERNEL); 1727 if (!ag->stop_desc) 1728 goto err_free; 1729 1730 ag->stop_desc->data = 0; 1731 ag->stop_desc->ctrl = 0; 1732 ag->stop_desc->next = (u32)ag->stop_desc_dma; 1733 1734 mac_addr = of_get_mac_address(np); 1735 if (mac_addr) 1736 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN); 1737 if (!mac_addr || !is_valid_ether_addr(ndev->dev_addr)) { 1738 netif_err(ag, probe, ndev, "invalid MAC address, using random address\n"); 1739 eth_random_addr(ndev->dev_addr); 1740 } 1741 1742 ag->phy_if_mode = of_get_phy_mode(np); 1743 if (ag->phy_if_mode < 0) { 1744 netif_err(ag, probe, ndev, "missing phy-mode property in DT\n"); 1745 err = ag->phy_if_mode; 1746 goto err_free; 1747 } 1748 1749 netif_napi_add(ndev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); 1750 1751 err = clk_prepare_enable(ag->clk_eth); 1752 if (err) { 1753 netif_err(ag, probe, ndev, "Failed to enable eth clk.\n"); 1754 goto err_free; 1755 } 1756 1757 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0); 1758 1759 ag71xx_hw_init(ag); 1760 1761 err = ag71xx_mdio_probe(ag); 1762 if (err) 1763 goto err_put_clk; 1764 1765 platform_set_drvdata(pdev, ndev); 1766 1767 err = register_netdev(ndev); 1768 if (err) { 1769 netif_err(ag, probe, ndev, "unable to register net device\n"); 1770 platform_set_drvdata(pdev, NULL); 1771 goto err_mdio_remove; 1772 } 1773 1774 netif_info(ag, probe, ndev, "Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n", 1775 (unsigned long)ag->mac_base, ndev->irq, 1776 phy_modes(ag->phy_if_mode)); 1777 1778 return 0; 1779 1780 err_mdio_remove: 1781 ag71xx_mdio_remove(ag); 1782 err_put_clk: 1783 clk_disable_unprepare(ag->clk_eth); 1784 err_free: 1785 free_netdev(ndev); 1786 return err; 1787 } 1788 1789 static int ag71xx_remove(struct platform_device *pdev) 1790 { 1791 struct net_device *ndev = platform_get_drvdata(pdev); 1792 struct ag71xx *ag; 1793 1794 if (!ndev) 1795 return 0; 1796 1797 ag = netdev_priv(ndev); 1798 unregister_netdev(ndev); 1799 ag71xx_mdio_remove(ag); 1800 clk_disable_unprepare(ag->clk_eth); 1801 platform_set_drvdata(pdev, NULL); 1802 1803 return 0; 1804 } 1805 1806 static const u32 ar71xx_fifo_ar7100[] = { 1807 0x0fff0000, 0x00001fff, 0x00780fff, 1808 }; 1809 1810 static const u32 ar71xx_fifo_ar9130[] = { 1811 0x0fff0000, 0x00001fff, 0x008001ff, 1812 }; 1813 1814 static const u32 ar71xx_fifo_ar9330[] = { 1815 0x0010ffff, 0x015500aa, 0x01f00140, 1816 }; 1817 1818 static const struct ag71xx_dcfg ag71xx_dcfg_ar7100 = { 1819 .type = AR7100, 1820 .fifodata = ar71xx_fifo_ar7100, 1821 .max_frame_len = 1540, 1822 .desc_pktlen_mask = SZ_4K - 1, 1823 .tx_hang_workaround = false, 1824 }; 1825 1826 static const struct ag71xx_dcfg ag71xx_dcfg_ar7240 = { 1827 .type = AR7240, 1828 .fifodata = ar71xx_fifo_ar7100, 1829 .max_frame_len = 1540, 1830 .desc_pktlen_mask = SZ_4K - 1, 1831 .tx_hang_workaround = true, 1832 }; 1833 1834 static const struct ag71xx_dcfg ag71xx_dcfg_ar9130 = { 1835 .type = AR9130, 1836 .fifodata = ar71xx_fifo_ar9130, 1837 .max_frame_len = 1540, 1838 .desc_pktlen_mask = SZ_4K - 1, 1839 .tx_hang_workaround = false, 1840 }; 1841 1842 static const struct ag71xx_dcfg ag71xx_dcfg_ar9330 = { 1843 .type = AR9330, 1844 .fifodata = ar71xx_fifo_ar9330, 1845 .max_frame_len = 1540, 1846 .desc_pktlen_mask = SZ_4K - 1, 1847 .tx_hang_workaround = true, 1848 }; 1849 1850 static const struct ag71xx_dcfg ag71xx_dcfg_ar9340 = { 1851 .type = AR9340, 1852 .fifodata = ar71xx_fifo_ar9330, 1853 .max_frame_len = SZ_16K - 1, 1854 .desc_pktlen_mask = SZ_16K - 1, 1855 .tx_hang_workaround = true, 1856 }; 1857 1858 static const struct ag71xx_dcfg ag71xx_dcfg_qca9530 = { 1859 .type = QCA9530, 1860 .fifodata = ar71xx_fifo_ar9330, 1861 .max_frame_len = SZ_16K - 1, 1862 .desc_pktlen_mask = SZ_16K - 1, 1863 .tx_hang_workaround = true, 1864 }; 1865 1866 static const struct ag71xx_dcfg ag71xx_dcfg_qca9550 = { 1867 .type = QCA9550, 1868 .fifodata = ar71xx_fifo_ar9330, 1869 .max_frame_len = 1540, 1870 .desc_pktlen_mask = SZ_16K - 1, 1871 .tx_hang_workaround = true, 1872 }; 1873 1874 static const struct of_device_id ag71xx_match[] = { 1875 { .compatible = "qca,ar7100-eth", .data = &ag71xx_dcfg_ar7100 }, 1876 { .compatible = "qca,ar7240-eth", .data = &ag71xx_dcfg_ar7240 }, 1877 { .compatible = "qca,ar7241-eth", .data = &ag71xx_dcfg_ar7240 }, 1878 { .compatible = "qca,ar7242-eth", .data = &ag71xx_dcfg_ar7240 }, 1879 { .compatible = "qca,ar9130-eth", .data = &ag71xx_dcfg_ar9130 }, 1880 { .compatible = "qca,ar9330-eth", .data = &ag71xx_dcfg_ar9330 }, 1881 { .compatible = "qca,ar9340-eth", .data = &ag71xx_dcfg_ar9340 }, 1882 { .compatible = "qca,qca9530-eth", .data = &ag71xx_dcfg_qca9530 }, 1883 { .compatible = "qca,qca9550-eth", .data = &ag71xx_dcfg_qca9550 }, 1884 { .compatible = "qca,qca9560-eth", .data = &ag71xx_dcfg_qca9550 }, 1885 {} 1886 }; 1887 1888 static struct platform_driver ag71xx_driver = { 1889 .probe = ag71xx_probe, 1890 .remove = ag71xx_remove, 1891 .driver = { 1892 .name = "ag71xx", 1893 .of_match_table = ag71xx_match, 1894 } 1895 }; 1896 1897 module_platform_driver(ag71xx_driver); 1898 MODULE_LICENSE("GPL v2"); 1899