1 /* 2 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com) 3 * 4 * Registers and bits definitions of ARC EMAC 5 */ 6 7 #ifndef ARC_EMAC_H 8 #define ARC_EMAC_H 9 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/netdevice.h> 13 #include <linux/phy.h> 14 15 /* STATUS and ENABLE Register bit masks */ 16 #define TXINT_MASK (1<<0) /* Transmit interrupt */ 17 #define RXINT_MASK (1<<1) /* Receive interrupt */ 18 #define ERR_MASK (1<<2) /* Error interrupt */ 19 #define TXCH_MASK (1<<3) /* Transmit chaining error interrupt */ 20 #define MSER_MASK (1<<4) /* Missed packet counter error */ 21 #define RXCR_MASK (1<<8) /* RXCRCERR counter rolled over */ 22 #define RXFR_MASK (1<<9) /* RXFRAMEERR counter rolled over */ 23 #define RXFL_MASK (1<<10) /* RXOFLOWERR counter rolled over */ 24 #define MDIO_MASK (1<<12) /* MDIO complete interrupt */ 25 #define TXPL_MASK (1<<31) /* Force polling of BD by EMAC */ 26 27 /* CONTROL Register bit masks */ 28 #define EN_MASK (1<<0) /* VMAC enable */ 29 #define TXRN_MASK (1<<3) /* TX enable */ 30 #define RXRN_MASK (1<<4) /* RX enable */ 31 #define DSBC_MASK (1<<8) /* Disable receive broadcast */ 32 #define ENFL_MASK (1<<10) /* Enable Full-duplex */ 33 #define PROM_MASK (1<<11) /* Promiscuous mode */ 34 35 /* Buffer descriptor INFO bit masks */ 36 #define OWN_MASK (1<<31) /* 0-CPU owns buffer, 1-EMAC owns buffer */ 37 #define FIRST_MASK (1<<16) /* First buffer in chain */ 38 #define LAST_MASK (1<<17) /* Last buffer in chain */ 39 #define LEN_MASK 0x000007FF /* last 11 bits */ 40 #define CRLS (1<<21) 41 #define DEFR (1<<22) 42 #define DROP (1<<23) 43 #define RTRY (1<<24) 44 #define LTCL (1<<28) 45 #define UFLO (1<<29) 46 47 #define FOR_EMAC OWN_MASK 48 #define FOR_CPU 0 49 50 /* ARC EMAC register set combines entries for MAC and MDIO */ 51 enum { 52 R_ID = 0, 53 R_STATUS, 54 R_ENABLE, 55 R_CTRL, 56 R_POLLRATE, 57 R_RXERR, 58 R_MISS, 59 R_TX_RING, 60 R_RX_RING, 61 R_ADDRL, 62 R_ADDRH, 63 R_LAFL, 64 R_LAFH, 65 R_MDIO, 66 }; 67 68 #define TX_TIMEOUT (400*HZ/1000) /* Transmission timeout */ 69 70 #define ARC_EMAC_NAPI_WEIGHT 40 /* Workload for NAPI */ 71 72 #define EMAC_BUFFER_SIZE 1536 /* EMAC buffer size */ 73 74 /** 75 * struct arc_emac_bd - EMAC buffer descriptor (BD). 76 * 77 * @info: Contains status information on the buffer itself. 78 * @data: 32-bit byte addressable pointer to the packet data. 79 */ 80 struct arc_emac_bd { 81 __le32 info; 82 dma_addr_t data; 83 }; 84 85 /* Number of Rx/Tx BD's */ 86 #define RX_BD_NUM 128 87 #define TX_BD_NUM 128 88 89 #define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd)) 90 #define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd)) 91 92 /** 93 * struct buffer_state - Stores Rx/Tx buffer state. 94 * @sk_buff: Pointer to socket buffer. 95 * @addr: Start address of DMA-mapped memory region. 96 * @len: Length of DMA-mapped memory region. 97 */ 98 struct buffer_state { 99 struct sk_buff *skb; 100 DEFINE_DMA_UNMAP_ADDR(addr); 101 DEFINE_DMA_UNMAP_LEN(len); 102 }; 103 104 /** 105 * struct arc_emac_priv - Storage of EMAC's private information. 106 * @dev: Pointer to the current device. 107 * @ndev: Pointer to the current network device. 108 * @phy_dev: Pointer to attached PHY device. 109 * @bus: Pointer to the current MII bus. 110 * @regs: Base address of EMAC memory-mapped control registers. 111 * @napi: Structure for NAPI. 112 * @stats: Network device statistics. 113 * @rxbd: Pointer to Rx BD ring. 114 * @txbd: Pointer to Tx BD ring. 115 * @rxbd_dma: DMA handle for Rx BD ring. 116 * @txbd_dma: DMA handle for Tx BD ring. 117 * @rx_buff: Storage for Rx buffers states. 118 * @tx_buff: Storage for Tx buffers states. 119 * @txbd_curr: Index of Tx BD to use on the next "ndo_start_xmit". 120 * @txbd_dirty: Index of Tx BD to free on the next Tx interrupt. 121 * @last_rx_bd: Index of the last Rx BD we've got from EMAC. 122 * @link: PHY's last seen link state. 123 * @duplex: PHY's last set duplex mode. 124 * @speed: PHY's last set speed. 125 * @max_speed: Maximum supported by current system network data-rate. 126 */ 127 struct arc_emac_priv { 128 /* Devices */ 129 struct device *dev; 130 struct net_device *ndev; 131 struct phy_device *phy_dev; 132 struct mii_bus *bus; 133 134 void __iomem *regs; 135 136 struct napi_struct napi; 137 struct net_device_stats stats; 138 139 struct arc_emac_bd *rxbd; 140 struct arc_emac_bd *txbd; 141 142 dma_addr_t rxbd_dma; 143 dma_addr_t txbd_dma; 144 145 struct buffer_state rx_buff[RX_BD_NUM]; 146 struct buffer_state tx_buff[TX_BD_NUM]; 147 unsigned int txbd_curr; 148 unsigned int txbd_dirty; 149 150 unsigned int last_rx_bd; 151 152 unsigned int link; 153 unsigned int duplex; 154 unsigned int speed; 155 unsigned int max_speed; 156 }; 157 158 /** 159 * arc_reg_set - Sets EMAC register with provided value. 160 * @priv: Pointer to ARC EMAC private data structure. 161 * @reg: Register offset from base address. 162 * @value: Value to set in register. 163 */ 164 static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value) 165 { 166 iowrite32(value, priv->regs + reg * sizeof(int)); 167 } 168 169 /** 170 * arc_reg_get - Gets value of specified EMAC register. 171 * @priv: Pointer to ARC EMAC private data structure. 172 * @reg: Register offset from base address. 173 * 174 * returns: Value of requested register. 175 */ 176 static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg) 177 { 178 return ioread32(priv->regs + reg * sizeof(int)); 179 } 180 181 /** 182 * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask"). 183 * @priv: Pointer to ARC EMAC private data structure. 184 * @reg: Register offset from base address. 185 * @mask: Mask to apply to specified register. 186 * 187 * This function reads initial register value, then applies provided mask 188 * to it and then writes register back. 189 */ 190 static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask) 191 { 192 unsigned int value = arc_reg_get(priv, reg); 193 arc_reg_set(priv, reg, value | mask); 194 } 195 196 /** 197 * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask"). 198 * @priv: Pointer to ARC EMAC private data structure. 199 * @reg: Register offset from base address. 200 * @mask: Mask to apply to specified register. 201 * 202 * This function reads initial register value, then applies provided mask 203 * to it and then writes register back. 204 */ 205 static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask) 206 { 207 unsigned int value = arc_reg_get(priv, reg); 208 arc_reg_set(priv, reg, value & ~mask); 209 } 210 211 int arc_mdio_probe(struct platform_device *pdev, struct arc_emac_priv *priv); 212 int arc_mdio_remove(struct arc_emac_priv *priv); 213 214 #endif /* ARC_EMAC_H */ 215