1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Atlantic Network Driver
3  * Copyright (C) 2020 Marvell International Ltd.
4  */
5 
6 #include "hw_atl2_llh.h"
7 #include "hw_atl2_llh_internal.h"
8 #include "aq_hw_utils.h"
9 
10 void hw_atl2_rpf_redirection_table2_select_set(struct aq_hw_s *aq_hw,
11 					       u32 select)
12 {
13 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_ADR,
14 			    HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSK,
15 			    HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_SHIFT, select);
16 }
17 
18 void hw_atl2_rpf_rss_hash_type_set(struct aq_hw_s *aq_hw, u32 rss_hash_type)
19 {
20 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_ADR,
21 			    HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSK,
22 			    HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_SHIFT,
23 			    rss_hash_type);
24 }
25 
26 /* rpf */
27 
28 void hw_atl2_rpf_new_enable_set(struct aq_hw_s *aq_hw, u32 enable)
29 {
30 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_NEW_EN_ADR,
31 			    HW_ATL2_RPF_NEW_EN_MSK,
32 			    HW_ATL2_RPF_NEW_EN_SHIFT,
33 			    enable);
34 }
35 
36 void hw_atl2_rpfl2_uc_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter)
37 {
38 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPFL2UC_TAG_ADR(filter),
39 			    HW_ATL2_RPFL2UC_TAG_MSK,
40 			    HW_ATL2_RPFL2UC_TAG_SHIFT,
41 			    tag);
42 }
43 
44 void hw_atl2_rpfl2_bc_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag)
45 {
46 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_L2_BC_TAG_ADR,
47 			    HW_ATL2_RPF_L2_BC_TAG_MSK,
48 			    HW_ATL2_RPF_L2_BC_TAG_SHIFT,
49 			    tag);
50 }
51 
52 void hw_atl2_new_rpf_rss_redir_set(struct aq_hw_s *aq_hw, u32 tc, u32 index,
53 				   u32 queue)
54 {
55 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_RSS_REDIR_ADR(tc, index),
56 			    HW_ATL2_RPF_RSS_REDIR_MSK(tc),
57 			    HW_ATL2_RPF_RSS_REDIR_SHIFT(tc),
58 			    queue);
59 }
60 
61 void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filter)
62 {
63 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_VL_TAG_ADR(filter),
64 			    HW_ATL2_RPF_VL_TAG_MSK,
65 			    HW_ATL2_RPF_VL_TAG_SHIFT,
66 			    tag);
67 }
68 
69 /* TX */
70 
71 void hw_atl2_tpb_tx_tc_q_rand_map_en_set(struct aq_hw_s *aq_hw,
72 					 const u32 tc_q_rand_map_en)
73 {
74 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_ADR,
75 			    HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSK,
76 			    HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_SHIFT,
77 			    tc_q_rand_map_en);
78 }
79 
80 void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gate_en)
81 {
82 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_ADR,
83 			    HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSK,
84 			    HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_SHIFT,
85 			    clk_gate_en);
86 }
87 
88 void hw_atl2_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
89 					u32 tx_intr_moderation_ctl,
90 					u32 queue)
91 {
92 	aq_hw_write_reg(aq_hw, HW_ATL2_TX_INTR_MODERATION_CTL_ADR(queue),
93 			tx_intr_moderation_ctl);
94 }
95 
96 void hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
97 					       const u32 data_arb_mode)
98 {
99 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TC_ARB_MODE_ADR,
100 			    HW_ATL2_TPS_DATA_TC_ARB_MODE_MSK,
101 			    HW_ATL2_TPS_DATA_TC_ARB_MODE_SHIFT,
102 			    data_arb_mode);
103 }
104 
105 void hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
106 						    const u32 tc,
107 						    const u32 max_credit)
108 {
109 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
110 			    HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK,
111 			    HW_ATL2_TPS_DATA_TCTCREDIT_MAX_SHIFT,
112 			    max_credit);
113 }
114 
115 void hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
116 						const u32 tc,
117 						const u32 weight)
118 {
119 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TCTWEIGHT_ADR(tc),
120 			    HW_ATL2_TPS_DATA_TCTWEIGHT_MSK,
121 			    HW_ATL2_TPS_DATA_TCTWEIGHT_SHIFT,
122 			    weight);
123 }
124 
125 u32 hw_atl2_get_hw_version(struct aq_hw_s *aq_hw)
126 {
127 	return aq_hw_read_reg(aq_hw, HW_ATL2_FPGA_VER_ADR);
128 }
129 
130 void hw_atl2_init_launchtime(struct aq_hw_s *aq_hw)
131 {
132 	u32 hw_ver = hw_atl2_get_hw_version(aq_hw);
133 
134 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_LT_CTRL_ADR,
135 			    HW_ATL2_LT_CTRL_CLK_RATIO_MSK,
136 			    HW_ATL2_LT_CTRL_CLK_RATIO_SHIFT,
137 			    hw_ver  < HW_ATL2_FPGA_VER_U32(1, 0, 0, 0) ?
138 			    HW_ATL2_LT_CTRL_CLK_RATIO_FULL_SPEED :
139 			    hw_ver >= HW_ATL2_FPGA_VER_U32(1, 0, 85, 2) ?
140 			    HW_ATL2_LT_CTRL_CLK_RATIO_HALF_SPEED :
141 			    HW_ATL2_LT_CTRL_CLK_RATIO_QUATER_SPEED);
142 }
143 
144 /* set action resolver record */
145 void hw_atl2_rpf_act_rslvr_record_set(struct aq_hw_s *aq_hw, u8 location,
146 				      u32 tag, u32 mask, u32 action)
147 {
148 	aq_hw_write_reg(aq_hw,
149 			HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_ADR(location),
150 			tag);
151 	aq_hw_write_reg(aq_hw,
152 			HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_ADR(location),
153 			mask);
154 	aq_hw_write_reg(aq_hw,
155 			HW_ATL2_RPF_ACT_RSLVR_ACTN_ADR(location),
156 			action);
157 }
158 
159 void hw_atl2_rpf_act_rslvr_section_en_set(struct aq_hw_s *aq_hw, u32 sections)
160 {
161 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_REC_TAB_EN_ADR,
162 			    HW_ATL2_RPF_REC_TAB_EN_MSK,
163 			    HW_ATL2_RPF_REC_TAB_EN_SHIFT,
164 			    sections);
165 }
166 
167 void hw_atl2_mif_shared_buf_get(struct aq_hw_s *aq_hw, int offset, u32 *data,
168 				int len)
169 {
170 	int j = 0;
171 	int i;
172 
173 	for (i = offset; i < offset + len; i++, j++)
174 		data[j] = aq_hw_read_reg(aq_hw,
175 					 HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(i));
176 }
177 
178 void hw_atl2_mif_shared_buf_write(struct aq_hw_s *aq_hw, int offset, u32 *data,
179 				  int len)
180 {
181 	int j = 0;
182 	int i;
183 
184 	for (i = offset; i < offset + len; i++, j++)
185 		aq_hw_write_reg(aq_hw, HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(i),
186 				data[j]);
187 }
188 
189 void hw_atl2_mif_shared_buf_read(struct aq_hw_s *aq_hw, int offset, u32 *data,
190 				 int len)
191 {
192 	int j = 0;
193 	int i;
194 
195 	for (i = offset; i < offset + len; i++, j++)
196 		data[j] = aq_hw_read_reg(aq_hw,
197 					 HW_ATL2_MIF_SHARED_BUFFER_OUT_ADR(i));
198 }
199 
200 void hw_atl2_mif_host_finished_write_set(struct aq_hw_s *aq_hw, u32 finish)
201 {
202 	aq_hw_write_reg_bit(aq_hw, HW_ATL2_MIF_HOST_FINISHED_WRITE_ADR,
203 			    HW_ATL2_MIF_HOST_FINISHED_WRITE_MSK,
204 			    HW_ATL2_MIF_HOST_FINISHED_WRITE_SHIFT,
205 			    finish);
206 }
207 
208 u32 hw_atl2_mif_mcp_finished_read_get(struct aq_hw_s *aq_hw)
209 {
210 	return aq_hw_read_reg_bit(aq_hw, HW_ATL2_MIF_MCP_FINISHED_READ_ADR,
211 				  HW_ATL2_MIF_MCP_FINISHED_READ_MSK,
212 				  HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT);
213 }
214 
215 u32 hw_atl2_mif_mcp_boot_reg_get(struct aq_hw_s *aq_hw)
216 {
217 	return aq_hw_read_reg(aq_hw, HW_ATL2_MIF_BOOT_REG_ADR);
218 }
219 
220 void hw_atl2_mif_mcp_boot_reg_set(struct aq_hw_s *aq_hw, u32 val)
221 {
222 	return aq_hw_write_reg(aq_hw, HW_ATL2_MIF_BOOT_REG_ADR, val);
223 }
224 
225 u32 hw_atl2_mif_host_req_int_get(struct aq_hw_s *aq_hw)
226 {
227 	return aq_hw_read_reg(aq_hw, HW_ATL2_MCP_HOST_REQ_INT_ADR);
228 }
229 
230 void hw_atl2_mif_host_req_int_clr(struct aq_hw_s *aq_hw, u32 val)
231 {
232 	return aq_hw_write_reg(aq_hw, HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR,
233 			       val);
234 }
235