1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Atlantic Network Driver 3 * Copyright (C) 2020 Marvell International Ltd. 4 */ 5 6 #include "aq_hw.h" 7 #include "aq_hw_utils.h" 8 #include "aq_ring.h" 9 #include "aq_nic.h" 10 #include "hw_atl/hw_atl_b0.h" 11 #include "hw_atl/hw_atl_utils.h" 12 #include "hw_atl/hw_atl_llh.h" 13 #include "hw_atl/hw_atl_llh_internal.h" 14 #include "hw_atl2_utils.h" 15 #include "hw_atl2_llh.h" 16 #include "hw_atl2_internal.h" 17 #include "hw_atl2_llh_internal.h" 18 19 static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location, 20 u32 tag, u32 mask, u32 action); 21 22 #define DEFAULT_BOARD_BASIC_CAPABILITIES \ 23 .is_64_dma = true, \ 24 .msix_irqs = 8U, \ 25 .irq_mask = ~0U, \ 26 .vecs = HW_ATL2_RSS_MAX, \ 27 .tcs_max = HW_ATL2_TC_MAX, \ 28 .rxd_alignment = 1U, \ 29 .rxd_size = HW_ATL2_RXD_SIZE, \ 30 .rxds_max = HW_ATL2_MAX_RXD, \ 31 .rxds_min = HW_ATL2_MIN_RXD, \ 32 .txd_alignment = 1U, \ 33 .txd_size = HW_ATL2_TXD_SIZE, \ 34 .txds_max = HW_ATL2_MAX_TXD, \ 35 .txds_min = HW_ATL2_MIN_TXD, \ 36 .txhwb_alignment = 4096U, \ 37 .tx_rings = HW_ATL2_TX_RINGS, \ 38 .rx_rings = HW_ATL2_RX_RINGS, \ 39 .hw_features = NETIF_F_HW_CSUM | \ 40 NETIF_F_RXCSUM | \ 41 NETIF_F_RXHASH | \ 42 NETIF_F_SG | \ 43 NETIF_F_TSO | \ 44 NETIF_F_TSO6 | \ 45 NETIF_F_LRO | \ 46 NETIF_F_NTUPLE | \ 47 NETIF_F_HW_VLAN_CTAG_FILTER | \ 48 NETIF_F_HW_VLAN_CTAG_RX | \ 49 NETIF_F_HW_VLAN_CTAG_TX | \ 50 NETIF_F_GSO_UDP_L4 | \ 51 NETIF_F_GSO_PARTIAL | \ 52 NETIF_F_HW_TC, \ 53 .hw_priv_flags = IFF_UNICAST_FLT, \ 54 .flow_control = true, \ 55 .mtu = HW_ATL2_MTU_JUMBO, \ 56 .mac_regs_count = 72, \ 57 .hw_alive_check_addr = 0x10U, \ 58 .priv_data_len = sizeof(struct hw_atl2_priv) 59 60 const struct aq_hw_caps_s hw_atl2_caps_aqc113 = { 61 DEFAULT_BOARD_BASIC_CAPABILITIES, 62 .media_type = AQ_HW_MEDIA_TYPE_TP, 63 .link_speed_msk = AQ_NIC_RATE_10G | 64 AQ_NIC_RATE_5G | 65 AQ_NIC_RATE_2G5 | 66 AQ_NIC_RATE_1G | 67 AQ_NIC_RATE_100M | 68 AQ_NIC_RATE_10M, 69 }; 70 71 static u32 hw_atl2_sem_act_rslvr_get(struct aq_hw_s *self) 72 { 73 return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL2_FW_SM_ACT_RSLVR); 74 } 75 76 static int hw_atl2_hw_reset(struct aq_hw_s *self) 77 { 78 struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; 79 int err; 80 81 err = hw_atl2_utils_soft_reset(self); 82 if (err) 83 return err; 84 85 memset(priv, 0, sizeof(*priv)); 86 87 self->aq_fw_ops->set_state(self, MPI_RESET); 88 89 err = aq_hw_err_from_flags(self); 90 91 return err; 92 } 93 94 static int hw_atl2_hw_queue_to_tc_map_set(struct aq_hw_s *self) 95 { 96 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; 97 unsigned int tcs, q_per_tc; 98 unsigned int tc, q; 99 u32 rx_map = 0; 100 u32 tx_map = 0; 101 102 hw_atl2_tpb_tx_tc_q_rand_map_en_set(self, 1U); 103 104 switch (cfg->tc_mode) { 105 case AQ_TC_MODE_8TCS: 106 tcs = 8; 107 q_per_tc = 4; 108 break; 109 case AQ_TC_MODE_4TCS: 110 tcs = 4; 111 q_per_tc = 8; 112 break; 113 default: 114 return -EINVAL; 115 } 116 117 for (tc = 0; tc != tcs; tc++) { 118 unsigned int tc_q_offset = tc * q_per_tc; 119 120 for (q = tc_q_offset; q != tc_q_offset + q_per_tc; q++) { 121 rx_map |= tc << HW_ATL2_RX_Q_TC_MAP_SHIFT(q); 122 if (HW_ATL2_RX_Q_TC_MAP_ADR(q) != 123 HW_ATL2_RX_Q_TC_MAP_ADR(q + 1)) { 124 aq_hw_write_reg(self, 125 HW_ATL2_RX_Q_TC_MAP_ADR(q), 126 rx_map); 127 rx_map = 0; 128 } 129 130 tx_map |= tc << HW_ATL2_TX_Q_TC_MAP_SHIFT(q); 131 if (HW_ATL2_TX_Q_TC_MAP_ADR(q) != 132 HW_ATL2_TX_Q_TC_MAP_ADR(q + 1)) { 133 aq_hw_write_reg(self, 134 HW_ATL2_TX_Q_TC_MAP_ADR(q), 135 tx_map); 136 tx_map = 0; 137 } 138 } 139 } 140 141 return aq_hw_err_from_flags(self); 142 } 143 144 static int hw_atl2_hw_qos_set(struct aq_hw_s *self) 145 { 146 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; 147 u32 tx_buff_size = HW_ATL2_TXBUF_MAX; 148 u32 rx_buff_size = HW_ATL2_RXBUF_MAX; 149 unsigned int prio = 0U; 150 u32 tc = 0U; 151 152 /* TPS Descriptor rate init */ 153 hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U); 154 hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA); 155 156 /* TPS VM init */ 157 hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); 158 159 tx_buff_size /= cfg->tcs; 160 rx_buff_size /= cfg->tcs; 161 for (tc = 0; tc < cfg->tcs; tc++) { 162 u32 threshold = 0U; 163 164 /* Tx buf size TC0 */ 165 hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, tx_buff_size, tc); 166 167 threshold = (tx_buff_size * (1024 / 32U) * 66U) / 100U; 168 hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self, threshold, tc); 169 170 threshold = (tx_buff_size * (1024 / 32U) * 50U) / 100U; 171 hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self, threshold, tc); 172 173 /* QoS Rx buf size per TC */ 174 hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, rx_buff_size, tc); 175 176 threshold = (rx_buff_size * (1024U / 32U) * 66U) / 100U; 177 hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self, threshold, tc); 178 179 threshold = (rx_buff_size * (1024U / 32U) * 50U) / 100U; 180 hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self, threshold, tc); 181 } 182 183 /* QoS 802.1p priority -> TC mapping */ 184 for (prio = 0; prio < 8; ++prio) 185 hw_atl_rpf_rpb_user_priority_tc_map_set(self, prio, 186 cfg->prio_tc_map[prio]); 187 188 /* ATL2 Apply ring to TC mapping */ 189 hw_atl2_hw_queue_to_tc_map_set(self); 190 191 return aq_hw_err_from_flags(self); 192 } 193 194 static int hw_atl2_hw_rss_set(struct aq_hw_s *self, 195 struct aq_rss_parameters *rss_params) 196 { 197 u8 *indirection_table = rss_params->indirection_table; 198 const u32 num_tcs = aq_hw_num_tcs(self); 199 u32 rpf_redir2_enable; 200 int tc; 201 int i; 202 203 rpf_redir2_enable = num_tcs > 4 ? 1 : 0; 204 205 hw_atl2_rpf_redirection_table2_select_set(self, rpf_redir2_enable); 206 207 for (i = HW_ATL2_RSS_REDIRECTION_MAX; i--;) { 208 for (tc = 0; tc != num_tcs; tc++) { 209 hw_atl2_new_rpf_rss_redir_set(self, tc, i, 210 tc * 211 aq_hw_q_per_tc(self) + 212 indirection_table[i]); 213 } 214 } 215 216 return aq_hw_err_from_flags(self); 217 } 218 219 static int hw_atl2_hw_init_tx_tc_rate_limit(struct aq_hw_s *self) 220 { 221 static const u32 max_weight = BIT(HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH) - 1; 222 /* Scale factor is based on the number of bits in fractional portion */ 223 static const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH); 224 static const u32 frac_msk = HW_ATL_TPS_DESC_RATE_Y_MSK >> 225 HW_ATL_TPS_DESC_RATE_Y_SHIFT; 226 const u32 link_speed = self->aq_link_status.mbps; 227 struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg; 228 unsigned long num_min_rated_tcs = 0; 229 u32 tc_weight[AQ_CFG_TCS_MAX]; 230 u32 fixed_max_credit_4b; 231 u32 fixed_max_credit; 232 u8 min_rate_msk = 0; 233 u32 sum_weight = 0; 234 int tc; 235 236 /* By default max_credit is based upon MTU (in unit of 64b) */ 237 fixed_max_credit = nic_cfg->aq_hw_caps->mtu / 64; 238 /* in unit of 4b */ 239 fixed_max_credit_4b = nic_cfg->aq_hw_caps->mtu / 4; 240 241 if (link_speed) { 242 min_rate_msk = nic_cfg->tc_min_rate_msk & 243 (BIT(nic_cfg->tcs) - 1); 244 num_min_rated_tcs = hweight8(min_rate_msk); 245 } 246 247 /* First, calculate weights where min_rate is specified */ 248 if (num_min_rated_tcs) { 249 for (tc = 0; tc != nic_cfg->tcs; tc++) { 250 if (!nic_cfg->tc_min_rate[tc]) { 251 tc_weight[tc] = 0; 252 continue; 253 } 254 255 tc_weight[tc] = (-1L + link_speed + 256 nic_cfg->tc_min_rate[tc] * 257 max_weight) / 258 link_speed; 259 tc_weight[tc] = min(tc_weight[tc], max_weight); 260 sum_weight += tc_weight[tc]; 261 } 262 } 263 264 /* WSP, if min_rate is set for at least one TC. 265 * RR otherwise. 266 */ 267 hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(self, min_rate_msk ? 1U : 0U); 268 /* Data TC Arbiter takes precedence over Descriptor TC Arbiter, 269 * leave Descriptor TC Arbiter as RR. 270 */ 271 hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); 272 273 hw_atl_tps_tx_desc_rate_mode_set(self, nic_cfg->is_qos ? 1U : 0U); 274 275 for (tc = 0; tc != nic_cfg->tcs; tc++) { 276 const u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U; 277 const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0); 278 u32 weight, max_credit; 279 280 hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, tc, 281 fixed_max_credit); 282 hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, tc, 0x1E); 283 284 if (num_min_rated_tcs) { 285 weight = tc_weight[tc]; 286 287 if (!weight && sum_weight < max_weight) 288 weight = (max_weight - sum_weight) / 289 (nic_cfg->tcs - num_min_rated_tcs); 290 else if (!weight) 291 weight = 0x640; 292 293 max_credit = max(2 * weight, fixed_max_credit_4b); 294 } else { 295 weight = 0x640; 296 max_credit = 0xFFF0; 297 } 298 299 hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(self, tc, weight); 300 hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(self, tc, 301 max_credit); 302 303 hw_atl_tps_tx_desc_rate_en_set(self, desc, en); 304 305 if (en) { 306 /* Nominal rate is always 10G */ 307 const u32 rate = 10000U * scale / 308 nic_cfg->tc_max_rate[tc]; 309 const u32 rate_int = rate >> 310 HW_ATL_TPS_DESC_RATE_Y_WIDTH; 311 const u32 rate_frac = rate & frac_msk; 312 313 hw_atl_tps_tx_desc_rate_x_set(self, desc, rate_int); 314 hw_atl_tps_tx_desc_rate_y_set(self, desc, rate_frac); 315 } else { 316 /* A value of 1 indicates the queue is not 317 * rate controlled. 318 */ 319 hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U); 320 hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U); 321 } 322 } 323 for (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) { 324 const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0); 325 326 hw_atl_tps_tx_desc_rate_en_set(self, desc, 0U); 327 hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U); 328 hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U); 329 } 330 331 return aq_hw_err_from_flags(self); 332 } 333 334 static int hw_atl2_hw_init_tx_path(struct aq_hw_s *self) 335 { 336 struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg; 337 338 /* Tx TC/RSS number config */ 339 hw_atl_tpb_tps_tx_tc_mode_set(self, nic_cfg->tc_mode); 340 341 hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U); 342 hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U); 343 hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU); 344 345 /* Tx interrupts */ 346 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U); 347 348 /* misc */ 349 hw_atl_tdm_tx_dca_en_set(self, 0U); 350 hw_atl_tdm_tx_dca_mode_set(self, 0U); 351 352 hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U); 353 354 hw_atl2_tpb_tx_buf_clk_gate_en_set(self, 0U); 355 356 return aq_hw_err_from_flags(self); 357 } 358 359 static void hw_atl2_hw_init_new_rx_filters(struct aq_hw_s *self) 360 { 361 struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; 362 u8 *prio_tc_map = self->aq_nic_cfg->prio_tc_map; 363 u16 action; 364 u8 index; 365 int i; 366 367 /* Action Resolver Table (ART) is used by RPF to decide which action 368 * to take with a packet based upon input tag and tag mask, where: 369 * - input tag is a combination of 3-bit VLan Prio (PTP) and 370 * 29-bit concatenation of all tags from filter block; 371 * - tag mask is a mask used for matching against input tag. 372 * The input_tag is compared with the all the Requested_tags in the 373 * Record table to find a match. Action field of the selected matched 374 * REC entry is used for further processing. If multiple entries match, 375 * the lowest REC entry, Action field will be selected. 376 */ 377 hw_atl2_rpf_act_rslvr_section_en_set(self, 0xFFFF); 378 hw_atl2_rpfl2_uc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC, 379 HW_ATL2_MAC_UC); 380 hw_atl2_rpfl2_bc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC); 381 382 /* FW reserves the beginning of ART, thus all driver entries must 383 * start from the offset specified in FW caps. 384 */ 385 index = priv->art_base_index + HW_ATL2_RPF_L2_PROMISC_OFF_INDEX; 386 hw_atl2_act_rslvr_table_set(self, index, 0, 387 HW_ATL2_RPF_TAG_UC_MASK | 388 HW_ATL2_RPF_TAG_ALLMC_MASK, 389 HW_ATL2_ACTION_DROP); 390 391 index = priv->art_base_index + HW_ATL2_RPF_VLAN_PROMISC_OFF_INDEX; 392 hw_atl2_act_rslvr_table_set(self, index, 0, 393 HW_ATL2_RPF_TAG_VLAN_MASK | 394 HW_ATL2_RPF_TAG_UNTAG_MASK, 395 HW_ATL2_ACTION_DROP); 396 397 /* Configure ART to map given VLan Prio (PCP) to the TC index for 398 * RSS redirection table. 399 */ 400 for (i = 0; i < 8; i++) { 401 action = HW_ATL2_ACTION_ASSIGN_TC(prio_tc_map[i]); 402 403 index = priv->art_base_index + HW_ATL2_RPF_PCP_TO_TC_INDEX + i; 404 hw_atl2_act_rslvr_table_set(self, index, 405 i << HW_ATL2_RPF_TAG_PCP_OFFSET, 406 HW_ATL2_RPF_TAG_PCP_MASK, action); 407 } 408 } 409 410 static void hw_atl2_hw_new_rx_filter_vlan_promisc(struct aq_hw_s *self, 411 bool promisc) 412 { 413 u16 off_action = (!promisc && 414 !hw_atl_rpfl2promiscuous_mode_en_get(self)) ? 415 HW_ATL2_ACTION_DROP : HW_ATL2_ACTION_DISABLE; 416 struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; 417 u8 index; 418 419 index = priv->art_base_index + HW_ATL2_RPF_VLAN_PROMISC_OFF_INDEX; 420 hw_atl2_act_rslvr_table_set(self, index, 0, 421 HW_ATL2_RPF_TAG_VLAN_MASK | 422 HW_ATL2_RPF_TAG_UNTAG_MASK, off_action); 423 } 424 425 static void hw_atl2_hw_new_rx_filter_promisc(struct aq_hw_s *self, bool promisc) 426 { 427 u16 off_action = promisc ? HW_ATL2_ACTION_DISABLE : HW_ATL2_ACTION_DROP; 428 struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; 429 bool vlan_promisc_enable; 430 u8 index; 431 432 index = priv->art_base_index + HW_ATL2_RPF_L2_PROMISC_OFF_INDEX; 433 hw_atl2_act_rslvr_table_set(self, index, 0, 434 HW_ATL2_RPF_TAG_UC_MASK | 435 HW_ATL2_RPF_TAG_ALLMC_MASK, 436 off_action); 437 438 /* turn VLAN promisc mode too */ 439 vlan_promisc_enable = hw_atl_rpf_vlan_prom_mode_en_get(self); 440 hw_atl2_hw_new_rx_filter_vlan_promisc(self, promisc | 441 vlan_promisc_enable); 442 } 443 444 static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location, 445 u32 tag, u32 mask, u32 action) 446 { 447 u32 val; 448 int err; 449 450 err = readx_poll_timeout_atomic(hw_atl2_sem_act_rslvr_get, 451 self, val, val == 1, 452 1, 10000U); 453 if (err) 454 return err; 455 456 hw_atl2_rpf_act_rslvr_record_set(self, location, tag, mask, 457 action); 458 459 hw_atl_reg_glb_cpu_sem_set(self, 1, HW_ATL2_FW_SM_ACT_RSLVR); 460 461 return err; 462 } 463 464 static int hw_atl2_hw_init_rx_path(struct aq_hw_s *self) 465 { 466 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; 467 int i; 468 469 /* Rx TC/RSS number config */ 470 hw_atl_rpb_rpf_rx_traf_class_mode_set(self, cfg->tc_mode); 471 472 /* Rx flow control */ 473 hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U); 474 475 hw_atl2_rpf_rss_hash_type_set(self, HW_ATL2_RPF_RSS_HASH_TYPE_ALL); 476 477 /* RSS Ring selection */ 478 hw_atl_b0_hw_init_rx_rss_ctrl1(self); 479 480 /* Multicast filters */ 481 for (i = HW_ATL2_MAC_MAX; i--;) { 482 hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i); 483 hw_atl_rpfl2unicast_flr_act_set(self, 1U, i); 484 } 485 486 hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U); 487 hw_atl_reg_rx_flr_mcst_flr_set(self, HW_ATL_MCAST_FLT_ANY_TO_HOST, 0U); 488 489 /* Vlan filters */ 490 hw_atl_rpf_vlan_outer_etht_set(self, ETH_P_8021AD); 491 hw_atl_rpf_vlan_inner_etht_set(self, ETH_P_8021Q); 492 493 hw_atl_rpf_vlan_prom_mode_en_set(self, 1); 494 495 /* Always accept untagged packets */ 496 hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U); 497 hw_atl_rpf_vlan_untagged_act_set(self, 1U); 498 499 hw_atl2_hw_init_new_rx_filters(self); 500 501 /* Rx Interrupts */ 502 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U); 503 504 hw_atl_rpfl2broadcast_flr_act_set(self, 1U); 505 hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U)); 506 507 hw_atl_rdm_rx_dca_en_set(self, 0U); 508 hw_atl_rdm_rx_dca_mode_set(self, 0U); 509 510 return aq_hw_err_from_flags(self); 511 } 512 513 static int hw_atl2_hw_init(struct aq_hw_s *self, u8 *mac_addr) 514 { 515 static u32 aq_hw_atl2_igcr_table_[4][2] = { 516 [AQ_HW_IRQ_INVALID] = { 0x20000000U, 0x20000000U }, 517 [AQ_HW_IRQ_LEGACY] = { 0x20000080U, 0x20000080U }, 518 [AQ_HW_IRQ_MSI] = { 0x20000021U, 0x20000025U }, 519 [AQ_HW_IRQ_MSIX] = { 0x20000022U, 0x20000026U }, 520 }; 521 522 struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; 523 struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg; 524 u8 base_index, count; 525 int err; 526 527 err = hw_atl2_utils_get_action_resolve_table_caps(self, &base_index, 528 &count); 529 if (err) 530 return err; 531 532 priv->art_base_index = 8 * base_index; 533 534 hw_atl2_init_launchtime(self); 535 536 hw_atl2_hw_init_tx_path(self); 537 hw_atl2_hw_init_rx_path(self); 538 539 hw_atl_b0_hw_mac_addr_set(self, mac_addr); 540 541 self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk); 542 self->aq_fw_ops->set_state(self, MPI_INIT); 543 544 hw_atl2_hw_qos_set(self); 545 hw_atl2_hw_rss_set(self, &aq_nic_cfg->aq_rss); 546 hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss); 547 548 hw_atl2_rpf_new_enable_set(self, 1); 549 550 /* Reset link status and read out initial hardware counters */ 551 self->aq_link_status.mbps = 0; 552 self->aq_fw_ops->update_stats(self); 553 554 err = aq_hw_err_from_flags(self); 555 if (err < 0) 556 goto err_exit; 557 558 /* Interrupts */ 559 hw_atl_reg_irq_glb_ctl_set(self, 560 aq_hw_atl2_igcr_table_[aq_nic_cfg->irq_type] 561 [(aq_nic_cfg->vecs > 1U) ? 562 1 : 0]); 563 564 hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask); 565 566 /* Interrupts */ 567 hw_atl_reg_gen_irq_map_set(self, 568 ((HW_ATL2_ERR_INT << 0x18) | 569 (1U << 0x1F)) | 570 ((HW_ATL2_ERR_INT << 0x10) | 571 (1U << 0x17)), 0U); 572 573 hw_atl_b0_hw_offload_set(self, aq_nic_cfg); 574 575 err_exit: 576 return err; 577 } 578 579 static int hw_atl2_hw_ring_rx_init(struct aq_hw_s *self, 580 struct aq_ring_s *aq_ring, 581 struct aq_ring_param_s *aq_ring_param) 582 { 583 return hw_atl_b0_hw_ring_rx_init(self, aq_ring, aq_ring_param); 584 } 585 586 static int hw_atl2_hw_ring_tx_init(struct aq_hw_s *self, 587 struct aq_ring_s *aq_ring, 588 struct aq_ring_param_s *aq_ring_param) 589 { 590 return hw_atl_b0_hw_ring_tx_init(self, aq_ring, aq_ring_param); 591 } 592 593 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U) 594 595 static int hw_atl2_hw_packet_filter_set(struct aq_hw_s *self, 596 unsigned int packet_filter) 597 { 598 hw_atl2_hw_new_rx_filter_promisc(self, IS_FILTER_ENABLED(IFF_PROMISC)); 599 600 return hw_atl_b0_hw_packet_filter_set(self, packet_filter); 601 } 602 603 #undef IS_FILTER_ENABLED 604 605 static int hw_atl2_hw_multicast_list_set(struct aq_hw_s *self, 606 u8 ar_mac 607 [AQ_HW_MULTICAST_ADDRESS_MAX] 608 [ETH_ALEN], 609 u32 count) 610 { 611 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; 612 int err = 0; 613 614 if (count > (HW_ATL2_MAC_MAX - HW_ATL2_MAC_MIN)) { 615 err = -EBADRQC; 616 goto err_exit; 617 } 618 for (cfg->mc_list_count = 0U; 619 cfg->mc_list_count < count; 620 ++cfg->mc_list_count) { 621 u32 i = cfg->mc_list_count; 622 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]); 623 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) | 624 (ar_mac[i][4] << 8) | ar_mac[i][5]; 625 626 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL2_MAC_MIN + i); 627 628 hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, 629 HW_ATL2_MAC_MIN + i); 630 631 hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, 632 HW_ATL2_MAC_MIN + i); 633 634 hw_atl2_rpfl2_uc_flr_tag_set(self, 1, HW_ATL2_MAC_MIN + i); 635 636 hw_atl_rpfl2_uc_flr_en_set(self, (cfg->is_mc_list_enabled), 637 HW_ATL2_MAC_MIN + i); 638 } 639 640 err = aq_hw_err_from_flags(self); 641 642 err_exit: 643 return err; 644 } 645 646 static int hw_atl2_hw_interrupt_moderation_set(struct aq_hw_s *self) 647 { 648 unsigned int i = 0U; 649 u32 itr_tx = 2U; 650 u32 itr_rx = 2U; 651 652 switch (self->aq_nic_cfg->itr) { 653 case AQ_CFG_INTERRUPT_MODERATION_ON: 654 case AQ_CFG_INTERRUPT_MODERATION_AUTO: 655 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U); 656 hw_atl_tdm_tdm_intr_moder_en_set(self, 1U); 657 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U); 658 hw_atl_rdm_rdm_intr_moder_en_set(self, 1U); 659 660 if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) { 661 /* HW timers are in 2us units */ 662 int tx_max_timer = self->aq_nic_cfg->tx_itr / 2; 663 int tx_min_timer = tx_max_timer / 2; 664 665 int rx_max_timer = self->aq_nic_cfg->rx_itr / 2; 666 int rx_min_timer = rx_max_timer / 2; 667 668 tx_max_timer = min(HW_ATL2_INTR_MODER_MAX, 669 tx_max_timer); 670 tx_min_timer = min(HW_ATL2_INTR_MODER_MIN, 671 tx_min_timer); 672 rx_max_timer = min(HW_ATL2_INTR_MODER_MAX, 673 rx_max_timer); 674 rx_min_timer = min(HW_ATL2_INTR_MODER_MIN, 675 rx_min_timer); 676 677 itr_tx |= tx_min_timer << 0x8U; 678 itr_tx |= tx_max_timer << 0x10U; 679 itr_rx |= rx_min_timer << 0x8U; 680 itr_rx |= rx_max_timer << 0x10U; 681 } else { 682 static unsigned int hw_atl2_timers_table_tx_[][2] = { 683 {0xfU, 0xffU}, /* 10Gbit */ 684 {0xfU, 0x1ffU}, /* 5Gbit */ 685 {0xfU, 0x1ffU}, /* 5Gbit 5GS */ 686 {0xfU, 0x1ffU}, /* 2.5Gbit */ 687 {0xfU, 0x1ffU}, /* 1Gbit */ 688 {0xfU, 0x1ffU}, /* 100Mbit */ 689 }; 690 static unsigned int hw_atl2_timers_table_rx_[][2] = { 691 {0x6U, 0x38U},/* 10Gbit */ 692 {0xCU, 0x70U},/* 5Gbit */ 693 {0xCU, 0x70U},/* 5Gbit 5GS */ 694 {0x18U, 0xE0U},/* 2.5Gbit */ 695 {0x30U, 0x80U},/* 1Gbit */ 696 {0x4U, 0x50U},/* 100Mbit */ 697 }; 698 unsigned int mbps = self->aq_link_status.mbps; 699 unsigned int speed_index; 700 701 speed_index = hw_atl_utils_mbps_2_speed_index(mbps); 702 703 /* Update user visible ITR settings */ 704 self->aq_nic_cfg->tx_itr = hw_atl2_timers_table_tx_ 705 [speed_index][1] * 2; 706 self->aq_nic_cfg->rx_itr = hw_atl2_timers_table_rx_ 707 [speed_index][1] * 2; 708 709 itr_tx |= hw_atl2_timers_table_tx_ 710 [speed_index][0] << 0x8U; 711 itr_tx |= hw_atl2_timers_table_tx_ 712 [speed_index][1] << 0x10U; 713 714 itr_rx |= hw_atl2_timers_table_rx_ 715 [speed_index][0] << 0x8U; 716 itr_rx |= hw_atl2_timers_table_rx_ 717 [speed_index][1] << 0x10U; 718 } 719 break; 720 case AQ_CFG_INTERRUPT_MODERATION_OFF: 721 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U); 722 hw_atl_tdm_tdm_intr_moder_en_set(self, 0U); 723 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U); 724 hw_atl_rdm_rdm_intr_moder_en_set(self, 0U); 725 itr_tx = 0U; 726 itr_rx = 0U; 727 break; 728 } 729 730 for (i = HW_ATL2_RINGS_MAX; i--;) { 731 hw_atl2_reg_tx_intr_moder_ctrl_set(self, itr_tx, i); 732 hw_atl_reg_rx_intr_moder_ctrl_set(self, itr_rx, i); 733 } 734 735 return aq_hw_err_from_flags(self); 736 } 737 738 static int hw_atl2_hw_stop(struct aq_hw_s *self) 739 { 740 hw_atl_b0_hw_irq_disable(self, HW_ATL2_INT_MASK); 741 742 return 0; 743 } 744 745 static struct aq_stats_s *hw_atl2_utils_get_hw_stats(struct aq_hw_s *self) 746 { 747 return &self->curr_stats; 748 } 749 750 static int hw_atl2_hw_vlan_set(struct aq_hw_s *self, 751 struct aq_rx_filter_vlan *aq_vlans) 752 { 753 struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; 754 u32 queue; 755 u8 index; 756 int i; 757 758 hw_atl_rpf_vlan_prom_mode_en_set(self, 1U); 759 760 for (i = 0; i < HW_ATL_VLAN_MAX_FILTERS; i++) { 761 queue = HW_ATL2_ACTION_ASSIGN_QUEUE(aq_vlans[i].queue); 762 763 hw_atl_rpf_vlan_flr_en_set(self, 0U, i); 764 hw_atl_rpf_vlan_rxq_en_flr_set(self, 0U, i); 765 index = priv->art_base_index + HW_ATL2_RPF_VLAN_USER_INDEX + i; 766 hw_atl2_act_rslvr_table_set(self, index, 0, 0, 767 HW_ATL2_ACTION_DISABLE); 768 if (aq_vlans[i].enable) { 769 hw_atl_rpf_vlan_id_flr_set(self, 770 aq_vlans[i].vlan_id, i); 771 hw_atl_rpf_vlan_flr_act_set(self, 1U, i); 772 hw_atl_rpf_vlan_flr_en_set(self, 1U, i); 773 774 if (aq_vlans[i].queue != 0xFF) { 775 hw_atl_rpf_vlan_rxq_flr_set(self, 776 aq_vlans[i].queue, 777 i); 778 hw_atl_rpf_vlan_rxq_en_flr_set(self, 1U, i); 779 780 hw_atl2_rpf_vlan_flr_tag_set(self, i + 2, i); 781 782 index = priv->art_base_index + 783 HW_ATL2_RPF_VLAN_USER_INDEX + i; 784 hw_atl2_act_rslvr_table_set(self, index, 785 (i + 2) << HW_ATL2_RPF_TAG_VLAN_OFFSET, 786 HW_ATL2_RPF_TAG_VLAN_MASK, queue); 787 } else { 788 hw_atl2_rpf_vlan_flr_tag_set(self, 1, i); 789 } 790 } 791 } 792 793 return aq_hw_err_from_flags(self); 794 } 795 796 static int hw_atl2_hw_vlan_ctrl(struct aq_hw_s *self, bool enable) 797 { 798 /* set promisc in case of disabing the vlan filter */ 799 hw_atl_rpf_vlan_prom_mode_en_set(self, !enable); 800 hw_atl2_hw_new_rx_filter_vlan_promisc(self, !enable); 801 802 return aq_hw_err_from_flags(self); 803 } 804 805 const struct aq_hw_ops hw_atl2_ops = { 806 .hw_soft_reset = hw_atl2_utils_soft_reset, 807 .hw_prepare = hw_atl2_utils_initfw, 808 .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set, 809 .hw_init = hw_atl2_hw_init, 810 .hw_reset = hw_atl2_hw_reset, 811 .hw_start = hw_atl_b0_hw_start, 812 .hw_ring_tx_start = hw_atl_b0_hw_ring_tx_start, 813 .hw_ring_tx_stop = hw_atl_b0_hw_ring_tx_stop, 814 .hw_ring_rx_start = hw_atl_b0_hw_ring_rx_start, 815 .hw_ring_rx_stop = hw_atl_b0_hw_ring_rx_stop, 816 .hw_stop = hw_atl2_hw_stop, 817 818 .hw_ring_tx_xmit = hw_atl_b0_hw_ring_tx_xmit, 819 .hw_ring_tx_head_update = hw_atl_b0_hw_ring_tx_head_update, 820 821 .hw_ring_rx_receive = hw_atl_b0_hw_ring_rx_receive, 822 .hw_ring_rx_fill = hw_atl_b0_hw_ring_rx_fill, 823 824 .hw_irq_enable = hw_atl_b0_hw_irq_enable, 825 .hw_irq_disable = hw_atl_b0_hw_irq_disable, 826 .hw_irq_read = hw_atl_b0_hw_irq_read, 827 828 .hw_ring_rx_init = hw_atl2_hw_ring_rx_init, 829 .hw_ring_tx_init = hw_atl2_hw_ring_tx_init, 830 .hw_packet_filter_set = hw_atl2_hw_packet_filter_set, 831 .hw_filter_vlan_set = hw_atl2_hw_vlan_set, 832 .hw_filter_vlan_ctrl = hw_atl2_hw_vlan_ctrl, 833 .hw_multicast_list_set = hw_atl2_hw_multicast_list_set, 834 .hw_interrupt_moderation_set = hw_atl2_hw_interrupt_moderation_set, 835 .hw_rss_set = hw_atl2_hw_rss_set, 836 .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set, 837 .hw_tc_rate_limit_set = hw_atl2_hw_init_tx_tc_rate_limit, 838 .hw_get_hw_stats = hw_atl2_utils_get_hw_stats, 839 .hw_get_fw_version = hw_atl2_utils_get_fw_version, 840 .hw_set_offload = hw_atl_b0_hw_offload_set, 841 }; 842