1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Atlantic Network Driver
3  * Copyright (C) 2020 Marvell International Ltd.
4  */
5 
6 #include "aq_hw.h"
7 #include "aq_hw_utils.h"
8 #include "aq_ring.h"
9 #include "aq_nic.h"
10 #include "hw_atl/hw_atl_b0.h"
11 #include "hw_atl/hw_atl_utils.h"
12 #include "hw_atl/hw_atl_llh.h"
13 #include "hw_atl/hw_atl_llh_internal.h"
14 #include "hw_atl2_utils.h"
15 #include "hw_atl2_llh.h"
16 #include "hw_atl2_internal.h"
17 #include "hw_atl2_llh_internal.h"
18 
19 static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location,
20 				       u32 tag, u32 mask, u32 action);
21 
22 #define DEFAULT_BOARD_BASIC_CAPABILITIES \
23 	.is_64_dma = true,		  \
24 	.op64bit = true,		  \
25 	.msix_irqs = 8U,		  \
26 	.irq_mask = ~0U,		  \
27 	.vecs = HW_ATL2_RSS_MAX,	  \
28 	.tcs_max = HW_ATL2_TC_MAX,	  \
29 	.rxd_alignment = 1U,		  \
30 	.rxd_size = HW_ATL2_RXD_SIZE,   \
31 	.rxds_max = HW_ATL2_MAX_RXD,    \
32 	.rxds_min = HW_ATL2_MIN_RXD,    \
33 	.txd_alignment = 1U,		  \
34 	.txd_size = HW_ATL2_TXD_SIZE,   \
35 	.txds_max = HW_ATL2_MAX_TXD,    \
36 	.txds_min = HW_ATL2_MIN_TXD,    \
37 	.txhwb_alignment = 4096U,	  \
38 	.tx_rings = HW_ATL2_TX_RINGS,   \
39 	.rx_rings = HW_ATL2_RX_RINGS,   \
40 	.hw_features = NETIF_F_HW_CSUM |  \
41 			NETIF_F_RXCSUM |  \
42 			NETIF_F_RXHASH |  \
43 			NETIF_F_SG |      \
44 			NETIF_F_TSO |     \
45 			NETIF_F_TSO6 |    \
46 			NETIF_F_LRO |     \
47 			NETIF_F_NTUPLE |  \
48 			NETIF_F_HW_VLAN_CTAG_FILTER | \
49 			NETIF_F_HW_VLAN_CTAG_RX |     \
50 			NETIF_F_HW_VLAN_CTAG_TX |     \
51 			NETIF_F_GSO_UDP_L4      |     \
52 			NETIF_F_GSO_PARTIAL     |     \
53 			NETIF_F_HW_TC,                \
54 	.hw_priv_flags = IFF_UNICAST_FLT, \
55 	.flow_control = true,		  \
56 	.mtu = HW_ATL2_MTU_JUMBO,	  \
57 	.mac_regs_count = 72,		  \
58 	.hw_alive_check_addr = 0x10U,     \
59 	.priv_data_len = sizeof(struct hw_atl2_priv)
60 
61 const struct aq_hw_caps_s hw_atl2_caps_aqc113 = {
62 	DEFAULT_BOARD_BASIC_CAPABILITIES,
63 	.media_type = AQ_HW_MEDIA_TYPE_TP,
64 	.link_speed_msk = AQ_NIC_RATE_10G |
65 			  AQ_NIC_RATE_5G  |
66 			  AQ_NIC_RATE_2G5 |
67 			  AQ_NIC_RATE_1G  |
68 			  AQ_NIC_RATE_1G_HALF   |
69 			  AQ_NIC_RATE_100M      |
70 			  AQ_NIC_RATE_100M_HALF |
71 			  AQ_NIC_RATE_10M       |
72 			  AQ_NIC_RATE_10M_HALF,
73 };
74 
75 static u32 hw_atl2_sem_act_rslvr_get(struct aq_hw_s *self)
76 {
77 	return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL2_FW_SM_ACT_RSLVR);
78 }
79 
80 static int hw_atl2_hw_reset(struct aq_hw_s *self)
81 {
82 	struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv;
83 	int err;
84 
85 	err = hw_atl2_utils_soft_reset(self);
86 	if (err)
87 		return err;
88 
89 	memset(priv, 0, sizeof(*priv));
90 
91 	self->aq_fw_ops->set_state(self, MPI_RESET);
92 
93 	err = aq_hw_err_from_flags(self);
94 
95 	return err;
96 }
97 
98 static int hw_atl2_hw_queue_to_tc_map_set(struct aq_hw_s *self)
99 {
100 	struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
101 	unsigned int tcs, q_per_tc;
102 	unsigned int tc, q;
103 	u32 rx_map = 0;
104 	u32 tx_map = 0;
105 
106 	hw_atl2_tpb_tx_tc_q_rand_map_en_set(self, 1U);
107 
108 	switch (cfg->tc_mode) {
109 	case AQ_TC_MODE_8TCS:
110 		tcs = 8;
111 		q_per_tc = 4;
112 		break;
113 	case AQ_TC_MODE_4TCS:
114 		tcs = 4;
115 		q_per_tc = 8;
116 		break;
117 	default:
118 		return -EINVAL;
119 	}
120 
121 	for (tc = 0; tc != tcs; tc++) {
122 		unsigned int tc_q_offset = tc * q_per_tc;
123 
124 		for (q = tc_q_offset; q != tc_q_offset + q_per_tc; q++) {
125 			rx_map |= tc << HW_ATL2_RX_Q_TC_MAP_SHIFT(q);
126 			if (HW_ATL2_RX_Q_TC_MAP_ADR(q) !=
127 			    HW_ATL2_RX_Q_TC_MAP_ADR(q + 1)) {
128 				aq_hw_write_reg(self,
129 						HW_ATL2_RX_Q_TC_MAP_ADR(q),
130 						rx_map);
131 				rx_map = 0;
132 			}
133 
134 			tx_map |= tc << HW_ATL2_TX_Q_TC_MAP_SHIFT(q);
135 			if (HW_ATL2_TX_Q_TC_MAP_ADR(q) !=
136 			    HW_ATL2_TX_Q_TC_MAP_ADR(q + 1)) {
137 				aq_hw_write_reg(self,
138 						HW_ATL2_TX_Q_TC_MAP_ADR(q),
139 						tx_map);
140 				tx_map = 0;
141 			}
142 		}
143 	}
144 
145 	return aq_hw_err_from_flags(self);
146 }
147 
148 static int hw_atl2_hw_qos_set(struct aq_hw_s *self)
149 {
150 	struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
151 	u32 tx_buff_size = HW_ATL2_TXBUF_MAX;
152 	u32 rx_buff_size = HW_ATL2_RXBUF_MAX;
153 	unsigned int prio = 0U;
154 	u32 tc = 0U;
155 
156 	/* TPS Descriptor rate init */
157 	hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
158 	hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
159 
160 	/* TPS VM init */
161 	hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
162 
163 	tx_buff_size /= cfg->tcs;
164 	rx_buff_size /= cfg->tcs;
165 	for (tc = 0; tc < cfg->tcs; tc++) {
166 		u32 threshold = 0U;
167 
168 		/* Tx buf size TC0 */
169 		hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, tx_buff_size, tc);
170 
171 		threshold = (tx_buff_size * (1024 / 32U) * 66U) / 100U;
172 		hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self, threshold, tc);
173 
174 		threshold = (tx_buff_size * (1024 / 32U) * 50U) / 100U;
175 		hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self, threshold, tc);
176 
177 		/* QoS Rx buf size per TC */
178 		hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, rx_buff_size, tc);
179 
180 		threshold = (rx_buff_size * (1024U / 32U) * 66U) / 100U;
181 		hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self, threshold, tc);
182 
183 		threshold = (rx_buff_size * (1024U / 32U) * 50U) / 100U;
184 		hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self, threshold, tc);
185 
186 		hw_atl_b0_set_fc(self, self->aq_nic_cfg->fc.req, tc);
187 	}
188 
189 	/* QoS 802.1p priority -> TC mapping */
190 	for (prio = 0; prio < 8; ++prio)
191 		hw_atl_rpf_rpb_user_priority_tc_map_set(self, prio,
192 							cfg->prio_tc_map[prio]);
193 
194 	/* ATL2 Apply ring to TC mapping */
195 	hw_atl2_hw_queue_to_tc_map_set(self);
196 
197 	return aq_hw_err_from_flags(self);
198 }
199 
200 static int hw_atl2_hw_rss_set(struct aq_hw_s *self,
201 			      struct aq_rss_parameters *rss_params)
202 {
203 	u8 *indirection_table = rss_params->indirection_table;
204 	const u32 num_tcs = aq_hw_num_tcs(self);
205 	u32 rpf_redir2_enable;
206 	int tc;
207 	int i;
208 
209 	rpf_redir2_enable = num_tcs > 4 ? 1 : 0;
210 
211 	hw_atl2_rpf_redirection_table2_select_set(self, rpf_redir2_enable);
212 
213 	for (i = HW_ATL2_RSS_REDIRECTION_MAX; i--;) {
214 		for (tc = 0; tc != num_tcs; tc++) {
215 			hw_atl2_new_rpf_rss_redir_set(self, tc, i,
216 						      tc *
217 						      aq_hw_q_per_tc(self) +
218 						      indirection_table[i]);
219 		}
220 	}
221 
222 	return aq_hw_err_from_flags(self);
223 }
224 
225 static int hw_atl2_hw_init_tx_tc_rate_limit(struct aq_hw_s *self)
226 {
227 	static const u32 max_weight = BIT(HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH) - 1;
228 	/* Scale factor is based on the number of bits in fractional portion */
229 	static const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH);
230 	static const u32 frac_msk = HW_ATL_TPS_DESC_RATE_Y_MSK >>
231 				    HW_ATL_TPS_DESC_RATE_Y_SHIFT;
232 	const u32 link_speed = self->aq_link_status.mbps;
233 	struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg;
234 	unsigned long num_min_rated_tcs = 0;
235 	u32 tc_weight[AQ_CFG_TCS_MAX];
236 	u32 fixed_max_credit_4b;
237 	u32 fixed_max_credit;
238 	u8 min_rate_msk = 0;
239 	u32 sum_weight = 0;
240 	int tc;
241 
242 	/* By default max_credit is based upon MTU (in unit of 64b) */
243 	fixed_max_credit = nic_cfg->aq_hw_caps->mtu / 64;
244 	/* in unit of 4b */
245 	fixed_max_credit_4b = nic_cfg->aq_hw_caps->mtu / 4;
246 
247 	if (link_speed) {
248 		min_rate_msk = nic_cfg->tc_min_rate_msk &
249 			       (BIT(nic_cfg->tcs) - 1);
250 		num_min_rated_tcs = hweight8(min_rate_msk);
251 	}
252 
253 	/* First, calculate weights where min_rate is specified */
254 	if (num_min_rated_tcs) {
255 		for (tc = 0; tc != nic_cfg->tcs; tc++) {
256 			if (!nic_cfg->tc_min_rate[tc]) {
257 				tc_weight[tc] = 0;
258 				continue;
259 			}
260 
261 			tc_weight[tc] = (-1L + link_speed +
262 					 nic_cfg->tc_min_rate[tc] *
263 					 max_weight) /
264 					link_speed;
265 			tc_weight[tc] = min(tc_weight[tc], max_weight);
266 			sum_weight += tc_weight[tc];
267 		}
268 	}
269 
270 	/* WSP, if min_rate is set for at least one TC.
271 	 * RR otherwise.
272 	 */
273 	hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(self, min_rate_msk ? 1U : 0U);
274 	/* Data TC Arbiter takes precedence over Descriptor TC Arbiter,
275 	 * leave Descriptor TC Arbiter as RR.
276 	 */
277 	hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
278 
279 	hw_atl_tps_tx_desc_rate_mode_set(self, nic_cfg->is_qos ? 1U : 0U);
280 
281 	for (tc = 0; tc != nic_cfg->tcs; tc++) {
282 		const u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U;
283 		const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);
284 		u32 weight, max_credit;
285 
286 		hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, tc,
287 							      fixed_max_credit);
288 		hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, tc, 0x1E);
289 
290 		if (num_min_rated_tcs) {
291 			weight = tc_weight[tc];
292 
293 			if (!weight && sum_weight < max_weight)
294 				weight = (max_weight - sum_weight) /
295 					 (nic_cfg->tcs - num_min_rated_tcs);
296 			else if (!weight)
297 				weight = 0x640;
298 
299 			max_credit = max(2 * weight, fixed_max_credit_4b);
300 		} else {
301 			weight = 0x640;
302 			max_credit = 0xFFF0;
303 		}
304 
305 		hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(self, tc, weight);
306 		hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(self, tc,
307 							       max_credit);
308 
309 		hw_atl_tps_tx_desc_rate_en_set(self, desc, en);
310 
311 		if (en) {
312 			/* Nominal rate is always 10G */
313 			const u32 rate = 10000U * scale /
314 					 nic_cfg->tc_max_rate[tc];
315 			const u32 rate_int = rate >>
316 					     HW_ATL_TPS_DESC_RATE_Y_WIDTH;
317 			const u32 rate_frac = rate & frac_msk;
318 
319 			hw_atl_tps_tx_desc_rate_x_set(self, desc, rate_int);
320 			hw_atl_tps_tx_desc_rate_y_set(self, desc, rate_frac);
321 		} else {
322 			/* A value of 1 indicates the queue is not
323 			 * rate controlled.
324 			 */
325 			hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U);
326 			hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U);
327 		}
328 	}
329 	for (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) {
330 		const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);
331 
332 		hw_atl_tps_tx_desc_rate_en_set(self, desc, 0U);
333 		hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U);
334 		hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U);
335 	}
336 
337 	return aq_hw_err_from_flags(self);
338 }
339 
340 static int hw_atl2_hw_init_tx_path(struct aq_hw_s *self)
341 {
342 	struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg;
343 
344 	/* Tx TC/RSS number config */
345 	hw_atl_tpb_tps_tx_tc_mode_set(self, nic_cfg->tc_mode);
346 
347 	hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
348 	hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
349 	hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
350 
351 	/* Tx interrupts */
352 	hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
353 
354 	/* misc */
355 	hw_atl_tdm_tx_dca_en_set(self, 0U);
356 	hw_atl_tdm_tx_dca_mode_set(self, 0U);
357 
358 	hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);
359 
360 	hw_atl2_tpb_tx_buf_clk_gate_en_set(self, 0U);
361 
362 	return aq_hw_err_from_flags(self);
363 }
364 
365 static void hw_atl2_hw_init_new_rx_filters(struct aq_hw_s *self)
366 {
367 	struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv;
368 	u8 *prio_tc_map = self->aq_nic_cfg->prio_tc_map;
369 	u16 action;
370 	u8 index;
371 	int i;
372 
373 	/* Action Resolver Table (ART) is used by RPF to decide which action
374 	 * to take with a packet based upon input tag and tag mask, where:
375 	 *  - input tag is a combination of 3-bit VLan Prio (PTP) and
376 	 *    29-bit concatenation of all tags from filter block;
377 	 *  - tag mask is a mask used for matching against input tag.
378 	 * The input_tag is compared with the all the Requested_tags in the
379 	 * Record table to find a match. Action field of the selected matched
380 	 * REC entry is used for further processing. If multiple entries match,
381 	 * the lowest REC entry, Action field will be selected.
382 	 */
383 	hw_atl2_rpf_act_rslvr_section_en_set(self, 0xFFFF);
384 	hw_atl2_rpfl2_uc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC,
385 				     HW_ATL2_MAC_UC);
386 	hw_atl2_rpfl2_bc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC);
387 
388 	/* FW reserves the beginning of ART, thus all driver entries must
389 	 * start from the offset specified in FW caps.
390 	 */
391 	index = priv->art_base_index + HW_ATL2_RPF_L2_PROMISC_OFF_INDEX;
392 	hw_atl2_act_rslvr_table_set(self, index, 0,
393 				    HW_ATL2_RPF_TAG_UC_MASK |
394 					HW_ATL2_RPF_TAG_ALLMC_MASK,
395 				    HW_ATL2_ACTION_DROP);
396 
397 	index = priv->art_base_index + HW_ATL2_RPF_VLAN_PROMISC_OFF_INDEX;
398 	hw_atl2_act_rslvr_table_set(self, index, 0,
399 				    HW_ATL2_RPF_TAG_VLAN_MASK |
400 					HW_ATL2_RPF_TAG_UNTAG_MASK,
401 				    HW_ATL2_ACTION_DROP);
402 
403 	/* Configure ART to map given VLan Prio (PCP) to the TC index for
404 	 * RSS redirection table.
405 	 */
406 	for (i = 0; i < 8; i++) {
407 		action = HW_ATL2_ACTION_ASSIGN_TC(prio_tc_map[i]);
408 
409 		index = priv->art_base_index + HW_ATL2_RPF_PCP_TO_TC_INDEX + i;
410 		hw_atl2_act_rslvr_table_set(self, index,
411 					    i << HW_ATL2_RPF_TAG_PCP_OFFSET,
412 					    HW_ATL2_RPF_TAG_PCP_MASK, action);
413 	}
414 }
415 
416 static void hw_atl2_hw_new_rx_filter_vlan_promisc(struct aq_hw_s *self,
417 						  bool promisc)
418 {
419 	u16 off_action = (!promisc &&
420 			  !hw_atl_rpfl2promiscuous_mode_en_get(self)) ?
421 				HW_ATL2_ACTION_DROP : HW_ATL2_ACTION_DISABLE;
422 	struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv;
423 	u8 index;
424 
425 	index = priv->art_base_index + HW_ATL2_RPF_VLAN_PROMISC_OFF_INDEX;
426 	hw_atl2_act_rslvr_table_set(self, index, 0,
427 				    HW_ATL2_RPF_TAG_VLAN_MASK |
428 				    HW_ATL2_RPF_TAG_UNTAG_MASK, off_action);
429 }
430 
431 static void hw_atl2_hw_new_rx_filter_promisc(struct aq_hw_s *self, bool promisc)
432 {
433 	u16 off_action = promisc ? HW_ATL2_ACTION_DISABLE : HW_ATL2_ACTION_DROP;
434 	struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv;
435 	bool vlan_promisc_enable;
436 	u8 index;
437 
438 	index = priv->art_base_index + HW_ATL2_RPF_L2_PROMISC_OFF_INDEX;
439 	hw_atl2_act_rslvr_table_set(self, index, 0,
440 				    HW_ATL2_RPF_TAG_UC_MASK |
441 				    HW_ATL2_RPF_TAG_ALLMC_MASK,
442 				    off_action);
443 
444 	/* turn VLAN promisc mode too */
445 	vlan_promisc_enable = hw_atl_rpf_vlan_prom_mode_en_get(self);
446 	hw_atl2_hw_new_rx_filter_vlan_promisc(self, promisc |
447 					      vlan_promisc_enable);
448 }
449 
450 static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location,
451 				       u32 tag, u32 mask, u32 action)
452 {
453 	u32 val;
454 	int err;
455 
456 	err = readx_poll_timeout_atomic(hw_atl2_sem_act_rslvr_get,
457 					self, val, val == 1,
458 					1, 10000U);
459 	if (err)
460 		return err;
461 
462 	hw_atl2_rpf_act_rslvr_record_set(self, location, tag, mask,
463 					 action);
464 
465 	hw_atl_reg_glb_cpu_sem_set(self, 1, HW_ATL2_FW_SM_ACT_RSLVR);
466 
467 	return err;
468 }
469 
470 static int hw_atl2_hw_init_rx_path(struct aq_hw_s *self)
471 {
472 	struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
473 	int i;
474 
475 	/* Rx TC/RSS number config */
476 	hw_atl_rpb_rpf_rx_traf_class_mode_set(self, cfg->tc_mode);
477 
478 	/* Rx flow control */
479 	hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
480 
481 	hw_atl2_rpf_rss_hash_type_set(self, HW_ATL2_RPF_RSS_HASH_TYPE_ALL);
482 
483 	/* RSS Ring selection */
484 	hw_atl_b0_hw_init_rx_rss_ctrl1(self);
485 
486 	/* Multicast filters */
487 	for (i = HW_ATL2_MAC_MAX; i--;) {
488 		hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
489 		hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
490 	}
491 
492 	hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
493 	hw_atl_reg_rx_flr_mcst_flr_set(self, HW_ATL_MCAST_FLT_ANY_TO_HOST, 0U);
494 
495 	/* Vlan filters */
496 	hw_atl_rpf_vlan_outer_etht_set(self, ETH_P_8021AD);
497 	hw_atl_rpf_vlan_inner_etht_set(self, ETH_P_8021Q);
498 
499 	hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
500 
501 	/* Always accept untagged packets */
502 	hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U);
503 	hw_atl_rpf_vlan_untagged_act_set(self, 1U);
504 
505 	hw_atl2_hw_init_new_rx_filters(self);
506 
507 	/* Rx Interrupts */
508 	hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
509 
510 	hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
511 	hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
512 
513 	hw_atl_rdm_rx_dca_en_set(self, 0U);
514 	hw_atl_rdm_rx_dca_mode_set(self, 0U);
515 
516 	return aq_hw_err_from_flags(self);
517 }
518 
519 static int hw_atl2_hw_init(struct aq_hw_s *self, u8 *mac_addr)
520 {
521 	static u32 aq_hw_atl2_igcr_table_[4][2] = {
522 		[AQ_HW_IRQ_INVALID] = { 0x20000000U, 0x20000000U },
523 		[AQ_HW_IRQ_LEGACY]  = { 0x20000080U, 0x20000080U },
524 		[AQ_HW_IRQ_MSI]     = { 0x20000021U, 0x20000025U },
525 		[AQ_HW_IRQ_MSIX]    = { 0x20000022U, 0x20000026U },
526 	};
527 
528 	struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv;
529 	struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
530 	u8 base_index, count;
531 	int err;
532 
533 	err = hw_atl2_utils_get_action_resolve_table_caps(self, &base_index,
534 							  &count);
535 	if (err)
536 		return err;
537 
538 	priv->art_base_index = 8 * base_index;
539 
540 	hw_atl2_init_launchtime(self);
541 
542 	hw_atl2_hw_init_tx_path(self);
543 	hw_atl2_hw_init_rx_path(self);
544 
545 	hw_atl_b0_hw_mac_addr_set(self, mac_addr);
546 
547 	self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);
548 	self->aq_fw_ops->set_state(self, MPI_INIT);
549 
550 	hw_atl2_hw_qos_set(self);
551 	hw_atl2_hw_rss_set(self, &aq_nic_cfg->aq_rss);
552 	hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
553 
554 	hw_atl2_rpf_new_enable_set(self, 1);
555 
556 	/* Reset link status and read out initial hardware counters */
557 	self->aq_link_status.mbps = 0;
558 	self->aq_fw_ops->update_stats(self);
559 
560 	err = aq_hw_err_from_flags(self);
561 	if (err < 0)
562 		goto err_exit;
563 
564 	/* Interrupts */
565 	hw_atl_reg_irq_glb_ctl_set(self,
566 				   aq_hw_atl2_igcr_table_[aq_nic_cfg->irq_type]
567 						 [(aq_nic_cfg->vecs > 1U) ?
568 						  1 : 0]);
569 
570 	hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
571 
572 	/* Interrupts */
573 	hw_atl_reg_gen_irq_map_set(self,
574 				   ((HW_ATL2_ERR_INT << 0x18) |
575 				    (1U << 0x1F)) |
576 				   ((HW_ATL2_ERR_INT << 0x10) |
577 				    (1U << 0x17)), 0U);
578 
579 	hw_atl_b0_hw_offload_set(self, aq_nic_cfg);
580 
581 err_exit:
582 	return err;
583 }
584 
585 static int hw_atl2_hw_ring_rx_init(struct aq_hw_s *self,
586 				   struct aq_ring_s *aq_ring,
587 				   struct aq_ring_param_s *aq_ring_param)
588 {
589 	return hw_atl_b0_hw_ring_rx_init(self, aq_ring, aq_ring_param);
590 }
591 
592 static int hw_atl2_hw_ring_tx_init(struct aq_hw_s *self,
593 				   struct aq_ring_s *aq_ring,
594 				   struct aq_ring_param_s *aq_ring_param)
595 {
596 	return hw_atl_b0_hw_ring_tx_init(self, aq_ring, aq_ring_param);
597 }
598 
599 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
600 
601 static int hw_atl2_hw_packet_filter_set(struct aq_hw_s *self,
602 					unsigned int packet_filter)
603 {
604 	hw_atl2_hw_new_rx_filter_promisc(self, IS_FILTER_ENABLED(IFF_PROMISC));
605 
606 	return hw_atl_b0_hw_packet_filter_set(self, packet_filter);
607 }
608 
609 #undef IS_FILTER_ENABLED
610 
611 static int hw_atl2_hw_multicast_list_set(struct aq_hw_s *self,
612 					 u8 ar_mac
613 					 [AQ_HW_MULTICAST_ADDRESS_MAX]
614 					 [ETH_ALEN],
615 					 u32 count)
616 {
617 	struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
618 	int err = 0;
619 
620 	if (count > (HW_ATL2_MAC_MAX - HW_ATL2_MAC_MIN)) {
621 		err = -EBADRQC;
622 		goto err_exit;
623 	}
624 	for (cfg->mc_list_count = 0U;
625 			cfg->mc_list_count < count;
626 			++cfg->mc_list_count) {
627 		u32 i = cfg->mc_list_count;
628 		u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
629 		u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
630 					(ar_mac[i][4] << 8) | ar_mac[i][5];
631 
632 		hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL2_MAC_MIN + i);
633 
634 		hw_atl_rpfl2unicast_dest_addresslsw_set(self, l,
635 							HW_ATL2_MAC_MIN + i);
636 
637 		hw_atl_rpfl2unicast_dest_addressmsw_set(self, h,
638 							HW_ATL2_MAC_MIN + i);
639 
640 		hw_atl2_rpfl2_uc_flr_tag_set(self, 1, HW_ATL2_MAC_MIN + i);
641 
642 		hw_atl_rpfl2_uc_flr_en_set(self, (cfg->is_mc_list_enabled),
643 					   HW_ATL2_MAC_MIN + i);
644 	}
645 
646 	err = aq_hw_err_from_flags(self);
647 
648 err_exit:
649 	return err;
650 }
651 
652 static int hw_atl2_hw_interrupt_moderation_set(struct aq_hw_s *self)
653 {
654 	unsigned int i = 0U;
655 	u32 itr_tx = 2U;
656 	u32 itr_rx = 2U;
657 
658 	switch (self->aq_nic_cfg->itr) {
659 	case  AQ_CFG_INTERRUPT_MODERATION_ON:
660 	case  AQ_CFG_INTERRUPT_MODERATION_AUTO:
661 		hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
662 		hw_atl_tdm_tdm_intr_moder_en_set(self, 1U);
663 		hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
664 		hw_atl_rdm_rdm_intr_moder_en_set(self, 1U);
665 
666 		if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) {
667 			/* HW timers are in 2us units */
668 			int tx_max_timer = self->aq_nic_cfg->tx_itr / 2;
669 			int tx_min_timer = tx_max_timer / 2;
670 
671 			int rx_max_timer = self->aq_nic_cfg->rx_itr / 2;
672 			int rx_min_timer = rx_max_timer / 2;
673 
674 			tx_max_timer = min(HW_ATL2_INTR_MODER_MAX,
675 					   tx_max_timer);
676 			tx_min_timer = min(HW_ATL2_INTR_MODER_MIN,
677 					   tx_min_timer);
678 			rx_max_timer = min(HW_ATL2_INTR_MODER_MAX,
679 					   rx_max_timer);
680 			rx_min_timer = min(HW_ATL2_INTR_MODER_MIN,
681 					   rx_min_timer);
682 
683 			itr_tx |= tx_min_timer << 0x8U;
684 			itr_tx |= tx_max_timer << 0x10U;
685 			itr_rx |= rx_min_timer << 0x8U;
686 			itr_rx |= rx_max_timer << 0x10U;
687 		} else {
688 			static unsigned int hw_atl2_timers_table_tx_[][2] = {
689 				{0xfU, 0xffU}, /* 10Gbit */
690 				{0xfU, 0x1ffU}, /* 5Gbit */
691 				{0xfU, 0x1ffU}, /* 5Gbit 5GS */
692 				{0xfU, 0x1ffU}, /* 2.5Gbit */
693 				{0xfU, 0x1ffU}, /* 1Gbit */
694 				{0xfU, 0x1ffU}, /* 100Mbit */
695 			};
696 			static unsigned int hw_atl2_timers_table_rx_[][2] = {
697 				{0x6U, 0x38U},/* 10Gbit */
698 				{0xCU, 0x70U},/* 5Gbit */
699 				{0xCU, 0x70U},/* 5Gbit 5GS */
700 				{0x18U, 0xE0U},/* 2.5Gbit */
701 				{0x30U, 0x80U},/* 1Gbit */
702 				{0x4U, 0x50U},/* 100Mbit */
703 			};
704 			unsigned int mbps = self->aq_link_status.mbps;
705 			unsigned int speed_index;
706 
707 			speed_index = hw_atl_utils_mbps_2_speed_index(mbps);
708 
709 			/* Update user visible ITR settings */
710 			self->aq_nic_cfg->tx_itr = hw_atl2_timers_table_tx_
711 							[speed_index][1] * 2;
712 			self->aq_nic_cfg->rx_itr = hw_atl2_timers_table_rx_
713 							[speed_index][1] * 2;
714 
715 			itr_tx |= hw_atl2_timers_table_tx_
716 						[speed_index][0] << 0x8U;
717 			itr_tx |= hw_atl2_timers_table_tx_
718 						[speed_index][1] << 0x10U;
719 
720 			itr_rx |= hw_atl2_timers_table_rx_
721 						[speed_index][0] << 0x8U;
722 			itr_rx |= hw_atl2_timers_table_rx_
723 						[speed_index][1] << 0x10U;
724 		}
725 		break;
726 	case AQ_CFG_INTERRUPT_MODERATION_OFF:
727 		hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
728 		hw_atl_tdm_tdm_intr_moder_en_set(self, 0U);
729 		hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
730 		hw_atl_rdm_rdm_intr_moder_en_set(self, 0U);
731 		itr_tx = 0U;
732 		itr_rx = 0U;
733 		break;
734 	}
735 
736 	for (i = HW_ATL2_RINGS_MAX; i--;) {
737 		hw_atl2_reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
738 		hw_atl_reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
739 	}
740 
741 	return aq_hw_err_from_flags(self);
742 }
743 
744 static int hw_atl2_hw_stop(struct aq_hw_s *self)
745 {
746 	hw_atl_b0_hw_irq_disable(self, HW_ATL2_INT_MASK);
747 
748 	return 0;
749 }
750 
751 static struct aq_stats_s *hw_atl2_utils_get_hw_stats(struct aq_hw_s *self)
752 {
753 	return &self->curr_stats;
754 }
755 
756 static int hw_atl2_hw_vlan_set(struct aq_hw_s *self,
757 			       struct aq_rx_filter_vlan *aq_vlans)
758 {
759 	struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv;
760 	u32 queue;
761 	u8 index;
762 	int i;
763 
764 	hw_atl_rpf_vlan_prom_mode_en_set(self, 1U);
765 
766 	for (i = 0; i < HW_ATL_VLAN_MAX_FILTERS; i++) {
767 		queue = HW_ATL2_ACTION_ASSIGN_QUEUE(aq_vlans[i].queue);
768 
769 		hw_atl_rpf_vlan_flr_en_set(self, 0U, i);
770 		hw_atl_rpf_vlan_rxq_en_flr_set(self, 0U, i);
771 		index = priv->art_base_index + HW_ATL2_RPF_VLAN_USER_INDEX + i;
772 		hw_atl2_act_rslvr_table_set(self, index, 0, 0,
773 					    HW_ATL2_ACTION_DISABLE);
774 		if (aq_vlans[i].enable) {
775 			hw_atl_rpf_vlan_id_flr_set(self,
776 						   aq_vlans[i].vlan_id, i);
777 			hw_atl_rpf_vlan_flr_act_set(self, 1U, i);
778 			hw_atl_rpf_vlan_flr_en_set(self, 1U, i);
779 
780 			if (aq_vlans[i].queue != 0xFF) {
781 				hw_atl_rpf_vlan_rxq_flr_set(self,
782 							    aq_vlans[i].queue,
783 							    i);
784 				hw_atl_rpf_vlan_rxq_en_flr_set(self, 1U, i);
785 
786 				hw_atl2_rpf_vlan_flr_tag_set(self, i + 2, i);
787 
788 				index = priv->art_base_index +
789 					HW_ATL2_RPF_VLAN_USER_INDEX + i;
790 				hw_atl2_act_rslvr_table_set(self, index,
791 					(i + 2) << HW_ATL2_RPF_TAG_VLAN_OFFSET,
792 					HW_ATL2_RPF_TAG_VLAN_MASK, queue);
793 			} else {
794 				hw_atl2_rpf_vlan_flr_tag_set(self, 1, i);
795 			}
796 		}
797 	}
798 
799 	return aq_hw_err_from_flags(self);
800 }
801 
802 static int hw_atl2_hw_vlan_ctrl(struct aq_hw_s *self, bool enable)
803 {
804 	/* set promisc in case of disabing the vlan filter */
805 	hw_atl_rpf_vlan_prom_mode_en_set(self, !enable);
806 	hw_atl2_hw_new_rx_filter_vlan_promisc(self, !enable);
807 
808 	return aq_hw_err_from_flags(self);
809 }
810 
811 const struct aq_hw_ops hw_atl2_ops = {
812 	.hw_soft_reset        = hw_atl2_utils_soft_reset,
813 	.hw_prepare           = hw_atl2_utils_initfw,
814 	.hw_set_mac_address   = hw_atl_b0_hw_mac_addr_set,
815 	.hw_init              = hw_atl2_hw_init,
816 	.hw_reset             = hw_atl2_hw_reset,
817 	.hw_start             = hw_atl_b0_hw_start,
818 	.hw_ring_tx_start     = hw_atl_b0_hw_ring_tx_start,
819 	.hw_ring_tx_stop      = hw_atl_b0_hw_ring_tx_stop,
820 	.hw_ring_rx_start     = hw_atl_b0_hw_ring_rx_start,
821 	.hw_ring_rx_stop      = hw_atl_b0_hw_ring_rx_stop,
822 	.hw_stop              = hw_atl2_hw_stop,
823 
824 	.hw_ring_tx_xmit         = hw_atl_b0_hw_ring_tx_xmit,
825 	.hw_ring_tx_head_update  = hw_atl_b0_hw_ring_tx_head_update,
826 
827 	.hw_ring_rx_receive      = hw_atl_b0_hw_ring_rx_receive,
828 	.hw_ring_rx_fill         = hw_atl_b0_hw_ring_rx_fill,
829 
830 	.hw_irq_enable           = hw_atl_b0_hw_irq_enable,
831 	.hw_irq_disable          = hw_atl_b0_hw_irq_disable,
832 	.hw_irq_read             = hw_atl_b0_hw_irq_read,
833 
834 	.hw_ring_rx_init             = hw_atl2_hw_ring_rx_init,
835 	.hw_ring_tx_init             = hw_atl2_hw_ring_tx_init,
836 	.hw_packet_filter_set        = hw_atl2_hw_packet_filter_set,
837 	.hw_filter_vlan_set          = hw_atl2_hw_vlan_set,
838 	.hw_filter_vlan_ctrl         = hw_atl2_hw_vlan_ctrl,
839 	.hw_multicast_list_set       = hw_atl2_hw_multicast_list_set,
840 	.hw_interrupt_moderation_set = hw_atl2_hw_interrupt_moderation_set,
841 	.hw_rss_set                  = hw_atl2_hw_rss_set,
842 	.hw_rss_hash_set             = hw_atl_b0_hw_rss_hash_set,
843 	.hw_tc_rate_limit_set        = hw_atl2_hw_init_tx_tc_rate_limit,
844 	.hw_get_hw_stats             = hw_atl2_utils_get_hw_stats,
845 	.hw_get_fw_version           = hw_atl2_utils_get_fw_version,
846 	.hw_set_offload              = hw_atl_b0_hw_offload_set,
847 	.hw_set_loopback             = hw_atl_b0_set_loopback,
848 	.hw_set_fc                   = hw_atl_b0_set_fc,
849 };
850